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eZ80F92 Development Kit User Manual - Digi-Key

1. lt 175 3 mm gt lt 43 2 mm gt lt 114 3 mm gt 2 1 8 S o 20 o of ISS 52250 o of 9 9 RIZ o 3 3 5 VOLT SELECT 65555550095000050000000500050009 5 5 FEM i SOCKETMODEM 5 5 560 5 lo opb J9 565555059 1 200 Si U20 loo o a 8 8 157 5 8 SEE E 80 5 52 2 167 6 mm E A16 2 voc 8 20 loo C29 A22 loo 1 Ji J RD o o o O RESET E loo ol o 2 DIS DIS EX TRIG2 TRIG NMI B FLASH FLOS GND 05 momy 20 202 2 ae 04 0070000 1 Wm 9 EMANA HEN N CS2 aa RESET R15 00 2 ND 65 11111177 gt m lo o 5 1 lt 165 1 mm Figure 5 Physical Dimensions of the eZ80 Development Platform UM013904 0203 PRELIMINARY Functional Description eZ80F92 Development Kit User Manual 21106
2. eZ80F92 Development Kit User Manual Z XIN Bi 65 7 R319 XOUT Y2 20 MHz IICSDA TICSCL HC49SM CLK_OUT 16 20pF 20pF 20 2 2 0 06 99 FEE ee eee az more mna 5850009 0 AO 00 8 PD7 RIO Raz A1 5 PD6 DCDO 0 PD5 DSRO PDA DTRO PD3 CTSO PD2 RTSO IR_SD PD1 RxDO IR_RXD L U8 PDO TxDO IR_TXD Ras VDD 85 JTAGO 100 TDI JTAG1 TDI ZDA TRIGOUT AQ eZ80F92 TRIGOUT A10 TCK ZCL TES b TMS BAT 41 vss RTC_VDD MINIMELF_AK TQFP100 RIC RTC XOUT 58 XIN RTC_VDD RTC_XIN rav TT GoldCap VSS VDD Hs 018 HALT_SLP HALT SLP 100nF ne BUSACK_ 54 BUSACK BUSACK BUSRE BUSREQ 5 GOLDCAP_SD E NMI RESET 10k _ RESET R32 RTC XN A Y3 C20 V3 3 220 32 768kHz 18pF XTAL3 RTC VDD C24 vss 18pF GND V3 3 PLACE CAPS CLOSE 1nF 1nF 1nF TO PINS 97 7 33 43 Figure 23 Schematic Diagram 2 of 9 100 Pin QFP eZ80F92 Device PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual 66 50 71 19 20 21 22 23 ET not used here C
3. es 23 Embedded Modem Socket Interface 28 eZ809 Development Platform Memory 30 LEDS mcm 33 Push Buttons W ces eris seed sede 33 01010068 n ks e wu Ay w b ke qi 34 000661018 4 lt eta Glassy PI Daka y Sca ds 39 Console sal 40 Modem 40 Ara EE EE dS Ede 40 DG Characteristics 524 esee a l un das aro oa 41 eZ80F92 Flash Module 43 Functional Description 43 Physical Dimensions 44 Operational Description 47 UM013904 0203 PRELIMINARY Table of Contents vi eZ80F92 Development Kit User Manual 21106 eZ80F92 Flash Module Memory 47 Reset Generatot 48 11805061161 i a onis ced toe RE ne 48 DC 51 Flash Loader Utility gt 51 Mounting the Module 51 Changing the Power Supply Plug 52 5 dte Rei 54 ZDI Target Interface Module 54 JTAG uoce
4. 9 Dis ETH 1445 03 123 _ 24 wa av H EM Dt E A 1 1 8 vor H Ag 5 EM_DO o o 281 Tl I A5 r WR VERB SW PUSHBUTTON 16 1 111 28 VDD LEBA swa 14 EM_WR_OE 1 24 VDD NB WR IORQ gt 2 custo GND 2 OEAB VCC o o gt gt PB2_SS 0 1uF CERA GND 12 SW PUSHBUTTON 22V10A LCC_0 ND ulz gt VDD 1 23 SEAR 0 tuF GND 7ALCXS43 SO GND Figure 18 280 Development Platform Schematic Diagram 2 of 5 0 013904 0203 PRELIMINARY Schematic Diagrams 23 0 00 0 255 5 MEM GEN3 B MEM_CEN4 UM013904 0203 D 7 0 23 0 u17 po H 5 H D2 11 D2 02 12 03 25 ps 5 3 pe 29 5 D7 30 2 VDD c9 0 1uF GN VDDO VDD1 MEM CEN1 E W j WE OE 0 VSS1 AS7C34096 23 0 U18 MEM_CEN2 L C10 WE 0 1uF gt 8 AS7C34096 Dj 7 00 DT D2 11 D2 02 12 03 04 5 D D5 26 D5 05 29 D6 pe D7 17 18 nn NC 5 3 NC MEM_CEN3 OE vsso 10 600 vss1 28 AS7C34096 GND 5 TC74LVC08 8 10 U9B
5. H T3OUT RTSO CON DIS 22 8 IN Your k2 VDP yop GND VOD 23 FORCEON INVALID 21 da 204 LT1086 3 3 T0220 1 H 184 9 c29 PD3 6 17 RsoUT 6150 _ 16 7 RXDO CONSOLE GREEN PD1 R4OUT 3 15 R5OUT RSIN DES Feinga A 5 2 gt gt GND 2 gt gt DIS_0 245 RS485_1_EN R17 10K C21 m 026 PD1 RXDO so wH vcc 0 1 20 RE a bZ R23 uz PD2_RTS0 3 oe ALS a 120 8 y PD0_TXDO 4 5 1 m 5 DI 9 1 v cas of 051487 BEI 1 2 ha 41 ce _1 GND 4 1 5 00 gz e DTR 13 T20UT 1 no vc H 81 PC2 181 lt 3 HIPISI 20 RE pz con8 VED MOD_DIS X 22 FORCEOFF rez RIS 3 pg RIA i PCO_TXD1 GND y FORCEON INVALID 21 2101 2 J18 120 106 RH B 20 051487 05 05816 5 42 3 1 1 64 ROLNE 18 2 1 Ji 1 17 6 PC7_RIK RINE 2 05 6 R3OUT 2 7 RXDf 01 15 016 R40UT RAIN RXD1 1 jeader 3 2 Yosa 8 0 06 00 5 5 R5IN 5485 2 EN DB9 UM013904 0203 i MAX3245CAI Figure 20
6. 54 Application Modules 54 ZDS Av dads 56 57 OVETVIEW hedge ie Dye s na nde 57 Cannot Download Code 57 No Output on Console Port 57 IrDA Port Not 58 Contacting ZiLOG Customer Support 58 Schematic 59 eZ809 Development 11071 eee eee 59 eZ80F92 Flash 64 Appendix oe en Ret en tol a 73 General Array Logic Equations 73 U10 Address 73 015 Address Decoder Eae 76 Customer Feedback 79 Table of Contents PRELIMINARY 0 013904 0203 eZ80F92 Development Kit User Manual List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 UM013904 0203 eZ80 Development Platform Block Diagram with eZ80F92 Flash Module 4 The eZ809 Development Platform
7. 24 LED Anode GPIO Port A Output Control Register 24 GPIO Data 25 Bit Access to the LED Cathode Modem and Triggers 26 Connector JS nannan naunan 28 Connector J9 is dee hha ey 3 RD aa 29 Connector akar los SH es 29 3 0 34 J3 DIS EM egra 35 J7 FlashWE Off Chip 35 J11 DIS Flash Off Chip 36 J12 5VDC 3 3VDC for an Embedded Modem 36 SED aa Rae a 37 5 5485 1 37 6 5485 2 38 ir JI er 38 118 225 39 Addresses 40 DC Current Characteristics of the 780 Development Platform with Different Module Loads 41 PRELIMINARY List of Tables ix eZ80F92 Development Kit User Manual 21106 List of Tables PRELIMINARY 0 013904 0203 eZ80F92 Development Kit Introduction User Manual z L o G The eZ80F92 Development Kit provides a general purpose platform for evaluating the capabilities and operation of ZiLOG s eZ80F92 microcon troller The eZ80F92 is a member of ZiLOG s eZ80Acclaim product line which offers on chip Flash ca
8. A17 A16 PRELIMINARY Appendix A 74 eZ80F92 Development Kit User Manual 2 21106 nEX FL DIS nDIS FL nL RD 1 nmemen2 nmemen3 nmemen4 input nFL DIS ncso 52 7 5 4 Al A0 nEX FL DIS General Array Logic Equations disables Flash on the expansion modul enables Development Platform LED le when Low and Port A emulation circuit disables Module Flash when Low enables local data bus to be read by CPU syn syn syn syn syn syn syn syn syn syn inpu A23 A7 A22 A6 A21 A5 A20 A4 A19 A3 18 2 A17 A1 A16 A0 thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis thesis loc P4 loc P5 locs B3 loc P6 loc P7 100 loc P10 locs P11 loc P12 loc P13 loc P16 loc P2 t 7 0 A upper part of Address Bus of 2 was 23 PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G 75 output nCS EX synthesis loc P17 enables memory on the Expansion Module nmemenl synthesis loc P18 enables memory on the Development Platform nmemen2 synthesis loc P19 nmemen3 synthesis loc P20 nmemen4 synthesis loc P21 nEM EN sy
9. 4 SCL 1 16 VDD D 7 0 5 54 13 03 37 CTO TRIG1 SDA 2 SCL VDD 15 CND 55 ij RESETS acer CT SDA we DI D6 17188 Qe 16 x hor D5 24 OVERR GND D7 18 19 TRIGZ Pin2 LIN 12 D7 Q7 5 B M OUT A 1 3p p p p 5 0 8 11 1 B vec He Mob TRG2 GND 7 MIND M OUT C 12 0 9 56 guy 9 12 5 A 5 5 5 M OUTID xm 4454 Ping PCA8550 74HCT374 GND 5 5 5 5 DIS 1 DLE 4 nene ne ne 4 4 ES 3 530 00 0 AN2 2 1 99 ipo qo H es 9 015 GND 1 1 DIS H q 5 d 0 PHI D4 03 b D5 14 D4 04 TQ74LVT125 TQ74LVT125 06 17406 5148 GND D7 Ds WR OE RD 3 A 18 57 oz He WR ANS 4 lt WR WR J AHAHHH 2 WR vec 28 4 4 4 1 4 1 E 2 CS EX gt SDA 9 5 2 5 Sct 2 0 1uF 5 6 DIS_IRDA 2 6 5 CS2 74HCT374 981 MEM CEN3 7 cs2 GND 6 CS3 cs3 X VDD EX SEL LTP 757 4741 7125 10 R11 R12 10K 10K 10K U15 U16 2 DIS_EM 1 3 17 EM RD 22 EM D 1 100 At B1 EM_D7 AEN 442 H WR 4J A2 2 F21 EM_D6 SAL 13 1 02 E A3 B3 EM D5 o o 280 13 A i4 H22 AH YAR 19 EM_D4 5 1 04 21
10. Changing the Power Supply Plug PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual 211 069 53 Figure 16 Inserting New Plug Configuration UM013904 0203 PRELIMINARY Changing the Power Supply Plug 54 eZ80F92 Development Kit User Manual 21106 ZPAK II ZPAKII is a debug tool used to develop and debug hardware and soft ware It is a networked device featuring an Ethernet interface and an RS232 console port ZPAKII is shipped with a preconfigured IP address that can be changed to suit the user on a local network For more informa tion about using and configuring ZPAKII please refer to the eZ80Acclaim Development Kits Quick Start Guide QS0020 and the ZPAKII Product User Guide PUGO0015 ZDI Target Interface Module JTAG The ZDI Target Interface Module provides a physical interface between ZPAKII and the eZ809 Development Platform The TIM module supports ZDI functions For more information on using the TIM module or ZDI please refer to the eZ80Acclaim Development Kits Quick Start Guide QS0019 the eZ80F92 Ethernet Module Product Specification 50186 and the eZ80F92 Flash Module Product Specification PS0189 Connector P1 is the JTAG connector on the eZ809 Development Plat form JTAG will be supported in the next offering of eZ809 products Application Modules ZPAKII ZiLOG offers the Thermostat Application module which can be used for evaluating and developing process con
11. 2 i O eZ80F92 Development Kit User Manual PRELIMINARY UM013904 0203 ZiLOG Worldwide Headquarters 532 Race Street San Jose 95126 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com eZ80F92 Development Kit User Manual 2 21106 This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www zilog com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated 2003 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Except with the express written approval of ZiLOG use of information devices or technology as critical components of life support systems is no
12. 55 14 D gt 35 0 OR UGA IWATA C JIOcHRDY 74LCX32 55 14 CS 0 3 eS CS1 and CS2 not used here EDO gt IRDA_TXD PD1 IRDA RXD lt IRDA SD IRDA SD R30 10k U2B 0603 DIS_FLASH 3 DISABLE_FLASH 4 CSFLASH CSO RESFLASH gt RESFLASH TSSOP14 741 2 TSSOP14 UeD CSFLASH 7 CSFLASH DISABLE IRDA DIS IRDA IRDA SD PD2 IR 50 43 7ALCXOA TSSOP14 TALCX32 TSSOP14 V3 3 DIS_FLASH eee DIS_IRDA Figure 30 Schematic Diagram 9 of 9 Control Logic UM013904 0203 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual 21106 73 Appendix A General Array Logic Equations This appendix shows the equations for disabling the Ethernet signals pro vided by the U10 and 915 General Array Logic GAL devices U10 Address Decoder define define define define FOR 6280 Development Platform Rev idle 2 b00 statel 2 b01 state2 27511 state3 2 b10 This PAL generates 4 memory chip selects module 92_decod nCS_EX Enables Extension Module s Memory when Low nFL_DIS when Low WEB Module Flash is disabled nDIS_FL 0 ncso 7 6 5 4 2 Al AO ncs2 UM013904 0203 when High nDIS FL depends upon state of nmemenX A23 22 21 A20 A19 A18
13. 280 Development Platform Schematic Diagram 4 of 5 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual iL 63 MATES WITH AMP 749268 1 P1 LENGTH 5 WIRES 28 AWG Figure 21 780 Development Platform Schematic Diagram 5 of 5 RS 485 Cable 0 013904 0203 PRELIMINARY Schematic Diagrams eZ80F92 Flash Module eZ80F92 Development Kit Figures 22 through 30 diagram the layout of the eZ80F92 Flash Module Ethernet circuiting devices are not loaded on the eZ80F92 Flash Module However these devices appear in the following schematics for reference purposes CPU eZ80 DIO 7 23 RD 03 RAM SRAM jos RD bos WR 1 CS1 04 Rom NOR Flash 0 7 A 0 23 RD WR csrLas CSELASH RESFLASH 2 FLASHWE Power PowerSupply V3 3 V3 3 GND GND UM013904 0203 WR Ethernet Peripherals Reset DIS FLASH DIS_IRDA CS8900A IRDA_TXD IRDA_TXD IRDA_RXD RxD IRDA_SD IOREQ RS MREQ INSTRD INSTRD WAIT WAIT 2 HALT_SLP HALT BUSREQ BUSACK NMI CLK_OUT OUT RTC VDD RTC VDD 9 d 34 IICSDA Logic IICSDA leser IICSCL CTRL Logic SET RESET WAIT 7 IRDA_TXD PB O 7 IRDA RXD PCI0 7 7 IRDA SD IRDA SD DIS FLASH PD O 7 zz
14. MoD DIS lt lt 1112 TuS DIS MAT 19 20 2 MWAIT 13 14 WAS 21 22 00 E 15 16 DS 23 24 E mE 17 18 DIS_ETIX 5 25 26 oo 6 08 FL 19 20 MAZZ 27 28 MAB EM D7 gt 21 22 gt gt PD7_RI0 MCST 29 30 M esi EM_D6 23 24 amp PD6 DCDO 2 62 31 32 EM D5 2 25 26 22PD5 DSRO MOT 33 34 MDZ EM_D4 27 28 PD4_DTRO MD3 35 36 Mba EM_D3 29 30 03 60 MDS 37 38 TND MAD EM D2 31 32 PD2 RTSO MDT 39 40 MDS MATO EM D1 33 34 22PD1 RXDO MMEMRG 41 42 MATT GND 35 36 GND PD0 TXD0 43 44 MRD MATZ 37 38 PB7 MOSI 45 46 INSTRD MA13 4 556 0 a 48 BUSREQ PC6 DCD17 41 42 O 49 50 MATS PCS DSRC 43 44 PBI TA O PC4_DTR1 gt 45 46 PB3 SCk R1 d R2 48 OK P2 PC2_RTS 58 Ti 2 55 PB7 MOSI 6 69 PC1_RXDIKC 51 52 5 1 2 PBA TA O 00 PBO TO PB3_SCK 3 4 55 VDD PBi TIT 5 PBO TOT ND 7 8 PCT RIT PC6 DCDi 9 10 PC5_DSRT PC4_DTRT n 2 PC3 CTS1 MA16 PC2_RTST 13 14 T_RXD1 MATT PCO 15 48 PD7 RIO MATS PD6_DCDO 17 18 GND 19 6 19 20 PD4 DTRO MA20 21 22 PD2_RTSO 21 23 24 PDO TXDO 22 TDO 25 26 MA23 686 27 28 TRIGOUT GND 9 3 GND TMS 1 20 VDD AB 32 AS VDD RTC_VDD 1 x M PHI 9 10 vcc A10 18 14 3a 34 GND cas A12 15 16 A13
15. 0 7 PUER Nal 3 510 31 09 0 3 CSFLASH JTAG 1 4 r Li RESFLASH RESELASH TDO The ao i lt 50 0 7 rj SD o 7 3 ALL IOCHRDY IOCHRDY ETHRD ETHWR erano SLEEP ACTIVE ACTIVE Figure 22 Schematic Diagram 1 of 9 Top Level PRELIMINARY User Manual Zi Connector FLASHWE IOREQ INSTRD WAIT HALT SLP 2 BUSREQ BUSACK 2 NMI 4 CLK_OUT 5 RTC VDD 20 71 23 9 WR RD PB 0 7 PDIO 7 CS 0 3 p JTAG 1 4 V3 3 GND Headers RESET FLASHWE IOREQ MREQ INSTRD WAIT HALT_SLP BUSREQ BUSACK NMI CLK_OUT RTC_VDD IICSDA IICSCL D 0 7 A 0 23 WR RD DIS FLASH DIS IRDA PB O 7 6 0 7 PD O 7 CS 0 3 JTAG 1 4 TDO V3 3 EXT GND EXT Schematic Diagrams eZ80 1IC bus master SEDE IICSDA T IICSCL CLK OUT CLK OUT PB O 7 eee PC O 7 eet PD O 7 eee RESET RESET 1 4 4 TDO RD 1 8 WR lt p orea gt __ _ _ MREQ gt JNSTRD lt 5 gt HALT_SLP HALT SLE BUSREQ BUSREQ BUSACK BUSACK NMI A 0 23 lt CS 0 3 9 510 7 RTC_VDD VDD UM013904 0203 V3 3 21 C22 C23
16. 9 must be set Low 0 to illuminate each of the LED s respectively Bit 7 in Table 7 does not carry any significance within the LED matrix It is used for GPIO as a Port A control bit Table 9 indicates the multiple register functions of the LED cathode modem and triggers This table shows the bit configuration for each cath ode bit Bits 5 6 and 7 do not carry any significance within the LED matrix These three bits are control bits for the modem reset Trig1 and Trig2 functions respectively Table 9 Bit Access to the LED Cathode Modem and Triggers Bit Function 7 6 5 4 3 2 1 0 Cathode Row 5 X Cathode Row 4 X Cathode Row 3 X Cathode Row 2 X Cathode Row 1 X Modem RST X Trig 1 X Trig 2 X Operational Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G 27 An LED display sample program is shipped with the eZ80F92 Develop ment Kit Please refer to the eZ80Acclaim Development Kits Quick Start Guide QS0020 or to the Tutorial section in the ZiLOG Developer Stu dio eZ80Acclaim User Manual UM0144 Modem Reset The Modem Reset signal MRESET is used to reset an optional socket modem This signal is controlled by bit 5 in the register shown in Table 9 The MRESET signal is available at the embedded modem socket inter face J9 Pin1 Setting this bit Low places the optional socket modem into a reset state The user must pull this bit High aga
17. TC74LVC08 451 m U9D TC74LVCOB an Figure 19 780 Development Platform Schematic Diagram 3 of 5 PRELIMINARY 0 eZ80F92 Developme nt Kit User Manual D 7 0 A 23 0 U20 7 Do DT D2 11 D2 02 12 D3 04 25 BE D5 26 D5 95 29 D6 pe 30 D7 vopi 2 1 z 0 1uF OE 1 AS7C34096 Schematic Diagrams 61 eZ80F92 Development Kit User Manual 62 riL mE GND 1 022 o 1 a zz o o RXE160 g v J10 2 C20 019 24 3 is T ci v HEADER 5 oa 1 J13 D6 2 0 1 C16 C17 A 245 0 1uF 526 T 1 LL i 1 RESET C22 5 lt 0 PWR JACK 7 V t 0 SN 22uF U25 02 RTSQ
18. User Manual Table 3 eZ80 Development Platform Connector Identification JP2 z L o G Pin Symbol Signal Direction Active Level eZ80F92 Signal 1 7 Bidirectional Yes 2 PB6 Bidirectional Yes 3 PBS Bidirectional Yes 4 PB4 Bidirectional Yes 5 PB3 Bidirectional Yes 6 PB2 Bidirectional Yes 7 PB1 Bidirectional Yes 8 PBO Bidirectional Yes 9 GND 10 PC7 Bidirectional Yes 11 PC6 Bidirectional Yes 12 PC5 Bidirectional Yes 13 PC4 Bidirectional Yes 14 PC3 Bidirectional Yes 15 PC2 Bidirectional Yes 16 PC1 Bidirectional Yes 17 PCO Bidirectional Yes 18 PD7 Bidirectional Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 62 through 64 2 The Power and Ground nets are connected directly to the eZ80F92 device UM013904 0203 PRELIMINARY Operational Description 17 eZ80F92 Development Kit User Manual Table 3 eZ80 Development Platform Connector Identification JP2 Continued Pin Symbol Signal Direction Active Level eZ80F92 Signal 19 PD6 Bidirectional 20 GND 21 PD5 Bidirectional Yes 22 PD4 Bidirectional Yes 23 PD3 Bidirectional Yes 24 PD2 Bidirectional Yes 25 PD1 Bidirectional Yes 26 PDO Bidirectional Yes 27 TDO Input Yes 28 TDI ZDA Output Yes 2
19. release the Reset button on the eZ809 Development Platform prior to selecting Build gt Debug Reset Go in ZDS No Output on Console Port The eZ80F92 Development Kit is shipped with a Flash Loader utility that is loaded in the oleate boot sector of Flash memory U3 Upon power up of the 280 Development Platform and the eZ80F92 Flash MCU Module the eZ80F92 device on the module starts running code from this Flash memory area This code enables the Console port with settings of 57 6kbps 8 N 1 The Console checks the Receive buffer If a space character is received on the Console port the Flash Loader utility is enabled and a boot message should be displayed on your connected device If no message is dis played check the following Jumper J2 must be ON IrDA is disabled On Connector J6 the jumper must be removed from pins 6 and 9 pin names con_dis and GND UM013904 0203 PRELIMINARY Troubleshooting eZ80F92 Development Kit User Manual 58 21106 IrDA Port Not Working If you plan on using the IrDA transceiver on the eZ80F92 Flash Module make sure the hardware is set up as follows e Jumper J2 must be OFF to enable the control gate that drives the IrDA device e Set port pin PD2 Low When this port pin and Jumper J2 are turned OFF the IrDA device is enabled e Install a jumper on connector 16 across pin names con_dis and GND to disable the console serial port driver Contacting ZiLOG Customer S
20. to provide the application developer with a plug in tool to evaluate the memory IrDA and other features of the eZ80F92 device eZ80F92 Flash Module Memory The eZ80F92 Flash Module comprises both off chip SRAM and on chip Flash memory which are described below Static RAM The eZ80F92 Flash Module features 512 KB of fast SRAM Access speed is typically 50ns allowing zero wait state operation at 20 MHz With the CPU at 20MHz SRAM can be accessed with zero wait states in eZ80 mode CS1_CTL chip select CS1 can be set to 08h no wait states Flash Memory The eZ80F92 Flash Module features 128 KB of Flash memory This on chip memory can be programmed a single byte at a time or in bursts of up to 128 bytes Write operations can be performed using either memory or I O instructions Erasing bytes in Flash memory returns them to a value of FFh Both the MASS ERASE and PAGE ERASE operations are self timed by the Flash controller leaving the CPU free to execute other oper ations in parallel Upon power up the on chip Flash memory is located in the address range 000000h 01FFFFh Four wait states are programmed in Flash control register F8h On chip Flash memory is prioritized over all external Chip Selects can be enabled or disabled power on enabled and can be programmed within any 128 address space in 16 address range The eZ80F92 Flash Module features the following memory configura tions UM013904 0203 PRELIMIN
21. 0203 eZ80F92 Development Kit User Manual z L o G 21 the eZ80 Development Platform because the eZ80F92 Flash Module features the eZ80F92 microcontroller To mount an application module use the two male headers J6 and J8 Jumper J6 carries the General Purpose Input Output ports GPIO and jumper J8 carries memory and control signals To design an application module the user should be familiar with the architecture and features of the eZ80F92 Flash Module currently installed Tables 4 and 5 list the sig nals and functions related to each of these jumpers by pin Power and ground signals are omitted for the sake of simplicity Table 4 GPIO Connector J6 Signal Pin Function Direction Notes SCL 5 2 Clock Bidirectional SDA 7 2 Data Bidirectional MOD_DIS 9 Modem Disable Input If a shunt is installed between pins 6 and 9 the modem function on the eZ80 Development Platform is disabled MWAIT 13 Wait signal for the Input CPU EM DO 15 Emulated Port A Bidirectional Bit 0 CS3 17 Chip Select 3 of Output This signal is also present on the CPU the J8 EM D 7 1 21 23 25 Emulated Port A Bidirectional 27 29 31 Bit 7 1 33 Reserved 35 Note All of the signals are driven directly by the CPU UM013904 0203 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 22 21 o 8 Table 4 GPIO Connector J6 Continued Signal Pin Function Direction Notes
22. 5 The eZ80F92 Flash Module 6 Basic 780 Development Platform Block Diagram 8 Physical Dimensions of the eZ809 Development Platform 9 eZ809 Development Platform Peripheral Bus Connector Pin Configuration JP1 11 eZ80 Development Platform I O Connector Pin 2 16 Trigger Pins 121 and J22 KK KK 27 Embedded Modem Socket Interface J1 15 and J9 28 Memory Map of the 780 Development Platform and eZ80F92 Flash Module 32 Physical Dimensions of the eZ80F92 Flash Module 44 eZ80F92 Flash Module Top 45 eZ80F92 Flash Module Bottom Layer 46 IrDA Hardware Connections 49 9VDC Universal Power Supply Components 52 Inserting New Plug Configuration 53 eZ809 Development Platform Schematic Diagram TI OE uut toes uos rd 59 eZ80 Development Platform Schematic Diagram 2 OLD Bison enya de 60 eZ80 Development Platform Schematic Diagram 013 22222224 61 780 Development Platform Schematic Diagram Aya yeka HE ad n n tb 62 PRELIMINARY List of Figures vii viii eZ80F92 Development Kit User Manual 21106 List of Figures Figure 21 Figure 22 Figure 23 Figure 24 Figu
23. 5 spo aqaqaa TINKLED spa TINKLED HGO P22 R22 lt 1 280 MEMW lt XTAL2 Y1 4k7 lt 23 MEMR 5 XTAL1 20 000 MHz 32 INTRQ2 5 AVSS HC49SM INTRQ1 AVDD INTRQO AVSS R23 330 10 516 U7 RES RXD 340 MEMCS16 RXD 66 324 RXD SHBE CS8900A CQ3 AVDD SAO AVSS 1 TXD DO SA2 TQFP100 TXD SA3 AVSS SA4 AVDD DO DO Cl Cl pi LCDA15C 6 BSTATUS HC1 PL x SLEEP P int GND 508150 ND 5 _ TEST pe i p Foco 04990 882 gt gt 00 0 2 lJ TXD TD 00000 O 0 O f device addresses 00300h bis 0030Fh ETHRD ENDE ETHWR IOCHRD HFJ11 1041 qqahh jjaam HALOFASTJACK through hol 5 Hii 1 1 wer TX 221 t der a HEADER 1 lt gt 2 00 71 SIP1 RX lt gt 3 place don t RX lt gt 6 SA 0 3 ALI 2 lt _ _ SLEEP SLEEP ACTIVE lt ACTIVE LANLED Figure 26 Schematic Diagram 5 of 9 eZ80F92 Flash Module 0 013904 0203 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual 69 100nF 0603 R3 2k2 0603 VDD RESET RESET open drain 0 GN C10 MAX6328UR29 10nF SOT 23 13 T 0603 AXEBO2UR29D3 IR transceiver V3 3 R6 2R7 0 25W I
24. 6280 92 PD2 IR_SD Device PD1 RxD PDO TxD Figure 14 IrDA Hardware Connections The eZ80F92 Flash Module features an Infrared Encoder Decoder regis ter that configures the IrDA function This register is located at address OBFh in the internal I O register map The Infrared Encoder Decoder register contains three control bits Bit 0 enables or disables the IrDA encoder decoder block Bit 1 if it is set UM013904 0203 PRELIMINARY Operational Description 50 eZ80F92 Development Kit User Manual 2 21106 enables received data to pass into the UARTO Receive FIFO data buffer Bit 2 is a test function that provides a loopback sequence from the TxD pin to the RxD input Bit 1 the Receive Enable bit is used to block data from filling up the Receive FIFO when the eZ80F92 Flash Module is transmitting data Because IrDA data passes through the air as a light source transmitted data can also be received This Receive Enable bit prevents this data from being received After the eZ80F92 Flash Module completes transmitting this bit is changed to allow for incoming messages The code that follows provides an example of how this function is enabled on the eZ80F92 Flash Module Init_IRDA S U U d Q Ensure to first set PD2 as a port bit an output and set it Low D_ALT1 amp OxFC PDO uartOtx uart0_rx D ALT2 0x03 Enable alternate function LCTLO 0x80 Select
25. 80F92 Flash Module perform their functions Operational Description PRELIMINARY UMO013904 0203 Jumper J3 eZ80F92 Development Kit User Manual z L o G 35 The J3 jumper connection controls Port A emulation mode and communi cation with the 7x5 LED When the shunt is placed Port A emulation is disabled See Table 14 Table 14 J3 DIS_EM Shunt Status Function Affected Device In Application Module Communication with 7x5 LED and Port emulation Hardware Disabled circuit is disabled Out Application Module Communication with 7x5 LED and Port A emulation Hardware Enabled circuit is enabled Jumper J7 The J7 jumper connection controls Flash boot loader programming When the shunt is placed overwriting of the Flash boot loader program is enabled See Table 15 Table 15 J7 FlashWE Off Chip Shunt Status Function Affected Device Out The Flash boot sector of the eZ80F92 Flash boot sector of the eZ80F92 Flash Flash Module is write protected Module In The Flash boot sector of the eZ80F92 Flash boot sector of the eZ80F92 Flash Flash Module is enabled for writing or Module overwriting Note As shipped from the factory external Flash memory is not installed UM013904 0203 PRELIMINARY Operational Description 36 eZ80F92 Development Kit User Manual Jumper J11 The J11 jumper connection controls access to the Flash memory device When the shunt is placed access to the Flash device is disabled pre vented
26. 9 GND 30 TRIGOUT Input High 31 TCK ZCL Output Yes 32 TMS Output High Yes 33 RTC Vpp 34 EZ80CLK Input Yes 35 SCL Bidirectional Yes 36 GND Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 62 through 64 2 The Power and Ground nets are connected directly to the eZ80F92 device Operational Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit 1 User Manual zitoa 19 Table 3 eZ80 Development Platform Connector Identification JP2 Continued Pin Symbol Signal Direction Active Level eZ80F92 Signal 37 SDA Bidirectional Yes 38 GND 39 FlashWE Output Low No 40 GND 41 658 Input Low Yes 42 DIS IrDA Output Low No 43 RESET Bidirectional Low Yes 44 WAIT Output Pull Up 10KQ Low Yes 45 Vpp 46 GND 47 HALT_SLP Input Low Yes 48 NMI Output Low Yes 49 Vpp 50 Reserved Notes For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 62 through 64 The Power and Ground nets are connected directly to the eZ80F92 device Almost all of the connectors signals are received directly from the CPU Three input signals in particular offer options to the application devel oper by disabling certain fu
27. ARY Operational Description eZ80F92 Development Kit User Manual 48 z L 8 On chip SRAM 8KB e Off chip SRAM 512KB e On chip Flash 128 Reset Generator The onboard Reset Generator Chip is connected to the eZ80F92 Reset input pin It performs reliable Power On Reset functions generating reset pulse with a duration of 200 ms if the power supply drops below 2 93 V This reset pulse ensures that the board always starts in a defined condition The RESET pin on the I O connector reflects the status of the RESET line It is a bidirectional pin for resetting external peripheral com ponents or for resetting the eZ80F92 Development Kit with a low imped ance output e g a 100 Ohm push button IrDA Transceiver An onboard IrDA transceiver ZiLOG ZHX1810 is connected to PDO TX PD1 RX and PD2 Shutdown IR SD The IrDA transceiver is of the LED type 870nm Class 1 The IrDA transceiver is accessible via the IrDA controller attached to UARTO on the eZ80F92 device The UARTO console and the IrDA trans ceiver cannot be used simultaneously To use the UARTO for console or to save power the transceiver can be disabled by the software or by an off board signal when using the proper jumper selection The transceiver is disabled by setting PD2 IR SD High or by pulling the DIS IRDA pin on the I O connector Low The shutdown feature is used for power savings To enable the IrDA trans ceiver DIS IRDA is left floating and PD2
28. CND Sw 13 H C34 74LVCB2TISO vec d VDD 92 Header 3 41 MD5 M mr ojas AT MRD 1 op voc 5 5 8099 19 05 GND a 74LVC248 80 gt gt MD 7 0 MDO 1 vec p wo 5 GND gt 7 Figure 17 780 Development Platform Schematic Diagram 1 of 5 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual 60 R6 40k Ferrite Core U10 52 3 17 CS EX IN 4 t l2 FL DIS iu x FL DIS 1 E 412 o1 MEM_CEN1 P4 A23 8 1 02 MEM_CEN2 4 07 64 1 03 MEM_CEN3 Lu jti r 5 1 04 gt MEM_CEN4 4 2 L_RD sm l 107 26 gt gt DI8_FL SIDACTOR P3100SB RJ14 tno 9 27 un AT e 11 wga voo M 4 2 EX_FL_DIS EX FL DIS 22 10 c2 c4 10K R7 0 001uF 0 001uF U12 7 0 GND DT Hoo D2 2 o Le CT2 U13 D3 8 8
29. M Note Key to blocks A Power and serial communications D Application module interfaces B eZ80F92 Flash Module interface E GPIO and LED with Address Decoder C Debug interface Figure 2 The 62805 Development Platform UM013904 0203 PRELIMINARY eZ80 Development Platform Overview eZ80F92 Development Kit User Manual 6 21106 Figure 3 is a photographic representation of the eZ80F92 Flash Module segmented into its key blocks as shown in the legend for the figure Note Key to blocks A eZ80F92 Flash Module interfaces B CPU C IrDA transceiver Figure 3 The eZ80F92 Flash Module The structures of the eZ809 Development Platform and the eZ80F92 Flash Module are illustrated in the Schematic Diagrams starting on page 59 eZ80 Development Platform Overview PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G 7 780 Development Platform This section describes the eZ80 Development Platform hardware its key components and its interfaces including detailed programmer interface information such as memory maps register definitions and interrupt usage Functional Description The eZ80 Development Platform consists of seven major hardware blocks These blocks listed below are diagrammed in Figure 4 eZ80F92 Flash Module interface 2 female headers Power supply for the eZ809 Development Platform the eZ80F92 Flash Module and appl
30. Operational Description The eZ80 Development Platform can accept any eZ80 core based modules provided that the module interfaces correctly to the eZ80 Development Platform The purpose of the eZ809 Development Platform is to provide the application developer with a tool to evaluate the features of the eZ80F92 Flash MCU and to develop an application without build ing additional hardware eZ80F92 Flash Module Interface The eZ80F92 Flash Module interface provides easy connection of the eZ80F92 Flash Module It also provides easy connection for any eZ809 based module designed to this interface This includes modules using future eZ80 devices and user developed modules using current eZ809 devices The eZ80F92 Flash Module interface consists of two 50 pin receptacles JP1 and JP2 Peripheral Bus Connector Figure 6 illustrates the pin layout of the Peripheral Bus Connector in the 50 pin header located at position JP1 on the eZ809 Development Plat form Table 2 describes the pins and their functions Operational Description PRELIMINARY UMO013904 0203 GND_EXT DIS_ETH WR BUSACK HEADER 25X2 IDC50 eZ80F92 Development Kit User Manual 21106 11 INSTRD BUSREQ Figure 6 eZ80 Development Platform Peripheral Bus Connector Pin Configuration JP1 UM013904 0203 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 12 6 Table 2 eZ80 Deve
31. PC 7 0 39 41 43 Port Bit 7 0 Bidirectional 45 47 49 51 53 ID_ 2 0 6 8 10 780 Output Development Platform ID CON DIS 12 Console Disable Input If a shunt is installed between pins 12 and 14 the Console function on the eZ809 Development Platform is disabled Reserved 16 18 PD 7 0 22 24 26 Port D Bit 7 0 Bidirectional 28 30 32 34 36 PB 7 0 40 42 44 Port B Bit 7 0 Bidirectional 46 48 50 52 54 Note All of the signals are driven directly by the CPU Operational Description PRELIMINARY UMO013904 0203 eZ80F92 Development Kit User Manual zitoa 23 Table 5 CPU Bus Connector J8 Signal Pin Function Direction A 0 7 3 10 Address Bus Low Byte Output A 8 15 13 20 Address Bus High Byte Output A 16 23 23 30 Address Bus Upper Byte Output RD 33 Read Signal Output RESET 35 Push Button Reset Output BUSACK 37 CPU Bus Acknowledge Signal Output NMI 39 Nonmaskable Interrupt Input D 0 7 43 50 Data Bus Bidirectional CS 0 3 53 56 Chip Selects MREQ 57 Memory Request Output WR 34 WRITE Signal Output INSTRD 36 Instruction Fetch Output BUSREQ 38 CPU Bus Request signal PHI 40 Clock output of the CPU Output Note All of the signals except BUSACK and INSTRD are driven by low voltage CMOS technology LVC drivers Functionality The eZ80190 microprocessor features General Purpose I O functionality at Port A The eZ80F92 device does not inc
32. PS0153 for more details UM013904 0203 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 2 32 21106 On chip FFFFFFh SRAM Available Address Space DFFFFFh SRAM Memory up to 2 MB CS1 Platform Expansion SRAM Memory up to 4 MB 80FFFFh LED amp GPIO 800000h 7TFFFFFh Off chip Expansion Module Flash memory Flash Memory up to 4 MB 400000h Module Expansion Flash Memory up to 4 MB Off chip 120000h Flash memory 11FFFFh Up to 4 MB CS2 CS0 8 MB Flash Memory 020000h On chip 01FFFFh Flash memory 000000h Figure 10 Memory Map of the eZ80 Development Platform and eZ80F92 Flash Module Operational Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual 21106 33 LEDs As stated earlier LEDs D1 D2 D3 and D4 function as status indicators for an optional modem This section describes each LED and the LED matrix device Data Carrier Detect The Data Carrier Detect DCD signal at D1 indicates that a good carrier signal is being received from the remote modem RX The RX signal at D2 indicates that data is received from the modem Data Terminal Ready The Data Terminal Ready DTR signal at D3 informs the modem that the PC is ready TX The TX signal at D4 indicates that data is transmitted to the modem Push Buttons The eZ80 Development Platform provides user controls in the form of push buttons T
33. RDA_TXD j j ___ 1206 MMA 020 4 IRDA RXD IRDA_SD IRDA_SD IRDA_TXD IRDA_SD IRDA RXD Figure 27 Schematic Diagram 6 of 9 IrDA Reset 0 013904 0203 PRELIMINARY Schematic Diagrams gt 2222L _ connector 1 7 1 50 71 10 09 GND_EXT CSI0 3 R7 R8 8 9 08 0 3 gt 80 P 2 A A5 g A18 IICSDA IICSDA 9 IICSDA lICSCL 2 R9 2 OUT EZ80CLK 5 9 akou gt FUTURE USE 9 DIS FLAS FLASH place near eZ80 21 5 CS_RAM output PHI cso 92 30 9 32 DIS_IRDA 34 5 36 FLASHWI ELASHWE B 937 38 3 40 RTC_VDD D7 RTC MREG 9 41 42 GND EXT 2413 44 945 46 PB O 7 BUSACK 9 BUSREQ PC 0 7 HEADER 25X2 PC 0 7 gt IDC50 PD O 7 lt n RESET PEST RD RD ZWE IOREQ joREQ MREQ INSTRD INSTRD WAT SIP HALT_SLP R11 R12 BUSREQ BUSREQ BUSREQ 10k 10k NMI JTAG1 TDI M gt gt JTAGO TDO 2 TRIGOUT JTAGIT 4 4 TMS V3 3 V33 EXT V3 3 EXT R13 4k7 GND EXT Em GND Figure 28 Schematic Diagram 7 of 9 Headers UM013904 0203 PRELIMINARY eZ80F92 Development Kit User Manual Zw i connecto
34. S1 2051 RD WR WR A18 16 4 7k A1 A15 A2 A13 CS1 6 RD DO D7 51 8 D6 a 9 0 gt 02 05 D3 D4 WR 11 A 10 6 A7 17 8 51266 SRAM U20 SOJ36 400 74LVC04 SO 1 ez U2E U2F 10082 VDD vss 74LVC04 SO 74LVC04 SO OND Figure 24 Schematic Diagram 3 of 9 36 Pin SRAM Device UM013904 0203 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual 67 DFLASHO DFLASH1 DFLASH2 DFLASH3 DFLASH4 DFLASH5 DFLASH6 DFLASH7 CSFLASH R1 10K FLASHWE R2 46 20 21 used for 16 32Mbit Flash Pin37 N C for 4Mbit MT28F008B3VG Flashes TSOP40 20MM 1 U3 IS NOT POPULATED ji 100nF D O 7 V3 3 A o 23 gt 22 23 not used here UDD CSFLASH CSFLASH WR RESFLASH GND RESFLASH FLASHWE pe Note Must be pulled low externally for programming Figure 25 Schematic Diagram 4 of 9 NOR Flash Device 0 013904 0203 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual V3 3 68 VDD A R19 vss A C oJ od de d 10k O O GND 6 N OHO 9 IN 2 5 aa lt oO 292229900 ee eet Q Z 22225 j m r e 5 100 LANLED 2
35. See Table 16 Table 16 J11 DIS_Flash Off Chip Shunt Status Function Affected Device In All access to Flash on the eZ80F92 Flash on eZ80F92 Flash Module Flash Module is disabled Out Flash on the eZ80F92 Flash Module Flash on eZ80F92 Flash Module is enabled Note As shipped from the factory external Flash memory is not installed Jumper J12 The J12 jumper connection controls the selection of a 5 V or 3VDC power supply to the embedded modem if an embedded modem is used See Table 17 Table 17 J12 5VDC 3 3VDC for an Embedded Modem Shunt Status Function Affected Device 1 2 5VDC is provided to power the embedded modem Embedded modem 2 3 3 3VDC is provided to power the embedded modem Embedded modem Operational Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual 21106 37 Jumper 14 The J14 jumper connection controls the polarity of the Ring Indicator See Table 18 Table 18 J14 RI Shunt Status Function Affected Device 1 2 The Ring Indicator for is inverted UART1 2 3 The Ring Indicator for UART1 is not inverted UART1 Jumper J15 The J15 jumper connection controls the selection RS485 circuit along with UARTO When the shunt is placed the RS485 circuit is enabled See Table 19 RS485 functionality will be available in future eZ80 devices Table 19 J15 RS485 1 Shunt Status Function Affected Device In The RS485 circuit is enabled o
36. arameter latch 8 h02 CS3 for CS9800 wire 7 0 address A7 A6 A5 A4 A3 A2 A1 A0 assign nEM WR nDIS_EM 1 nWR 0 amp nEM assign nEM_RD 0 amp address latch nDIS_EM 1 amp 0 amp nEM_EN 0 6 address latch assign nAN_WR nDIS_EM 1 nWR 0 amp nEM assign nCT_WR nDIS_EM 1 nWR 0 amp nEM_ assign nDIS_ETH nCS endmodule General Array Logic Equations PRELIMINARY IN 0 amp address anode 0 address cathode UM013904 0203 eZ80F92 Development Kit User Manual z L o G 79 Customer Feedback Form If you note any inaccuracies while reading this User Manual please copy and complete this form then mail or fax it to ZiLOG see Return Information below We also welcome your suggestions eZ80F92 Development Kit Serial or Board Fab Rev Software Version Document Number Host Computer Description Type Customer Information Name Country Company Phone Address Fax City State Zip E Mail Return Information ZiLOG System Test Customer Support 532 Race Street San Jose CA 95126 Phone 408 558 8500 Fax 408 558 8536 Email zservice zilog com Problem Description or Suggestion Provide a complete description of the problem or your suggestion If you are reporting a specific problem i
37. as 36 0 1uF 17 18 37 38 GND 18 20 GND 10K P 42 DIS_IRDA 6 17 MWAIT A18 2 24 19 LE so GND 20 AZ SU NMT 22 27 28 A23 47 48 5 VDD 29 30 DD 49 50 gt 31 32 Header 25x2 A mon Dis RD 33 34 WR leader R19 vee ES SR 37 38 PHI 4 4 NMI SND 39 40 cm PHI HEADER 00 41 42 Di 10K D 43 44 D3 Da 45 46 55 DE 47 48 D7 ZDI GND 49 50 GND 51 52 INTERFACE 50 53 54 E 55 56 T yoo DK MEMR 57 58 VDD He GNI GND 1 Header 30x2 Header 3x2 VDD DD 5 5 MRESET 10 S LI NA M b KR DCD 2 2 3 GND 773 2 4 1 4 2 d vos 2 i155 GND GND R5 TDI DTR 1K TDO 1 2 1 2 TC74LVT125 TCK 3 4 1 GND rt 5 6 TX TVCC_RESETn 7 8 TMS 1 S 2 HEADER9 HEADER 32 800 PRSTa MODEM CONNECTORS 13 44 con 7x2 UM013904 0203 eZ80F92 Development Kit User Manual 59 U2 GND 1 0 SDA SDA 26 2174 59 hey GND j we NC AT24C128 2 onn Dis IRDA GND HEADER 2 4 FLASHWE 2 U21 HEADER2 2 23 Y CS0 Ha y2 CS2 mwema 18 y4 42 MWR AS H WR RD AB CS3 As 5 SO Yao 1 cer 24 VDD vcc
38. dlab to access baud rate generator DLRLOZOXx2F Baud rate Masterclock 16 baudrate DLRHO 0x00 High byte of baud rate UAR n UART UART CTL0z20x00 Disable dlab FCTLO 0xC7 Clear tx fifo enable fifo CCTLO 0x03 8bit N 1 stop IR_CTL 0x03 enable IRDA Encode decode and Receive 1 RI enable bit DA Xmit IR 0x01 Disable receive Putchar 0xb0 Output a byte to the uart0 port Operational Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G DC Characteristics As different combinations of application modules are loaded onto the eZ80 Development Platform current requirements change Please see Table 24 on page 41 to reference current consumption values for these different module combinations A 0 1 Farad capacitor is provided on the eZ80F92 Flash Module as a short term battery backup for the RTC see the Schematic Diagrams on page 59 The part number of the capacitor made by Panasonic is EECSOHDV The capacitor is connected to RTC_VDD to provide power to the RTC when main power to the chip is removed it is also connected to the 3 3 V supply to the chip for recharging The RTC can operate down to 3 0V it requires 10uA of current The keep alive time this capacitor can supply power to the RTC from 3 3V to 3 0 V is approximately 3000 seconds or 50 minutes Flash Loader Uti
39. e of the U S requires modification The tested modem for this eZ80F92 Development Kit is a MultiTech Sys tems formerly Conexant socket modem part number SC56H1 Either the 3 3 V or the 5 0V version of the modem can be used However jumper J12 should be configured accordingly see Table 17 Information about this modem and its interface is available in the SocketModem data sheet from www multitech com eZ80 Development Platform Memory Memory space on the eZ809 Development Platform consists of onboard SRAM and additional SRAM footprints Onboard SRAM The eZ80 Development Platform features 512KB SRAM at U20 This SRAM provides the basic memory requirement for small applications development This SRAM is in the address range B80000h BFFFFFh With the 512KB of SRAM on the eZ80F92 Flash Module this addressing structure provides 1 MB of contiguous SRAM for immediate use Chip Select 2 is used to access the 512KB of SRAM on the eZ80 Develop ment Platform Additional SRAM The amount of eZ80 Development Platform memory can be extended if required by adding SRAM devices U19 U18 and U17 provide this capa bility However the user should be aware that additional SRAM must be installed in the following order 1 U19 address range B00000h B7FFFFh Operational Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G 31 2 U18 address range A80000h AFFFFFh 3 U17 address range A00000
40. eZ80F92 Signal 16 GND 17 A2 Bidirectional Yes 18 A1 Bidirectional Yes 19 A11 Bidirectional Yes 20 A12 Bidirectional Yes 21 4 Bidirectional Yes 22 A20 Bidirectional Yes 23 A5 Bidirectional Yes 24 A17 Bidirectional Yes 25 DIS ETH Output Low No 26 DIS FLASH Output Low No 27 A21 Bidirectional Yes 28 Vpp 29 A22 Bidirectional Yes 30 A23 Bidirectional Yes Notes For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 62 through 64 The Power and Ground nets are connected directly to the eZ80F92 device External capacitive loads on RD WR MREQ 00 07 and 23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register UM013904 0203 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 14 21106 Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Continued Pin Symbol Signal Direction Active Level eZ80F92 Signal 31 CSO Input Low Yes 32 CS1 Input Low Yes 33 CS2 Input Low Yes 34 DO Bidirectio
41. ed with an external power source UM013904 0203 PRELIMINARY eZ80F92 Flash Module eZ80F92 Development Kit User Manual 44 z L o G Physical Dimensions The dimensions of the eZ80F92 Flash Module PCB 15 64 64mm With an RJ 45 Ethernet connector the overall height is 25mm See Figure 11 lt 63 5 4 mm Top View Connector a o lt 55 88 Figure 11 Physical Dimensions of the eZ80F92 Flash Module Functional Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G Figure 12 illustrates the top layer silkscreen of the eZ80F92 Flash Mod ule D 9 01 2 YI fo QO m 5 24 1011 oo o JP2 o o o Jt a S e 0 ODULE 11 100111111111111 o 2106060 1 COPYRIGHT ZiLOG 5 8280 WEBSERVER i E NET 1111 1 R32 39 8 e m a 20 24 Figure 12 eZ80F92 Flash Module Top Layer UM013904 0203 PRELIMINARY Functional Description eZ80F92 Development Kit User Manual Z z L G Figure 13 illustra
42. em running Module eZ809 Development Platform 350 When the LED demo is eZ80F92 Flash Module and running Thermostat Application Module eZ80 Development Platform 360 When the LED demo is eZ80F92 Flash Module Modem running Module and Thermostat Application Module DC Characteristics PRELIMINARY 0 013904 0203 eZ80F92 Development Kit User Manual z L o G 43 eZ80F92 Flash Module This section describes the eZ80F92 Flash Module hardware its interfaces and key components including the CPU real time clock IrDA trans ceiver and memory Functional Description The eZ80F92 Flash Module is a compact high performance module spe cially designed for the rapid development and deployment of embedded systems Additional devices such as serial ports LED matrices GPIO ports and devices are supported when connected to the eZ809 Devel opment Platform A block diagram representing both of these boards is shown in Figure 1 on page 4 The eZ80F92 Flash Module is developed to be a plug in module to the eZ809 Development Platform This small footprint module provides CPU RAM an IrDA transceiver and a real time clock This low cost expandable module is powered by the eZ80F92 microcontroller members of ZILOG s new eZ80 product family The module also contains a bat tery and an oscillator in support of the on chip Real Time Clock RTC The eZ80F92 Flash Module can also be used as a stand alone develop ment tool when provid
43. erational Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G 29 Table 11 Connector J9 Pin Symbol Description 1 MRESET Reset active Low 50 100ms Closure to GND for reset 3 GND Ground 6 D1 DCD indicator can drive an LED anode without additional circuitry 7 D2 RxD indicator can drive an LED anode without additional circuitry 8 D3 DTR indicator can drive an LED anode without additional circuitry 9 D4 TxD indicator can drive an LED anode without additional circuitry Table 12 Connector J1 Pin Symbol Description 2 MOD_DIS Modem disable active Low 4 5 VDC or 3 3 VDC input 24 GND Ground 25 PC4_DTR1 interface TTL levels 26 PC6 DCD1 DCD interface TTL levels 27 PC3_CTS1 CTS interface TTL levels 28 5 DSR1 DSR interface TTL levels 29 PC7_RI1 Ring Indicator interface TTL levels 30 PCO _TXD1 TxD interface TTL levels 31 PC1 RXD1 RxD interface TTL levels 32 PC2_RTS1 RTS interface TTL levels UM013904 0203 PRELIMINARY Operational Description 30 eZ80F92 Development Kit User Manual 21106 Components P4 U11 provide the phone line interface to the modem On the eZ809 Development Platform LEDs D1 D2 D3 and D4 function as status indicators for this optional modem The phone line connection for the modem is for the United States only Connecting the modem outsid
44. f the register Table 7 LED Anode GPIO Port A Output Control Register Bit Function 7 6 5 4 3 2 1 0 Anode Col 1 X Anode Col 2 X Anode Col 3 X Operational Description PRELIMINARY UMO013904 0203 eZ80F92 Development Kit User Manual 21106 25 Table 7 LED Anode GPIO Port A Output Control Register Continued Bit Function 7 6 5 4 3 2 1 0 Anode Col 4 X Anode Col 5 X Anode Col 6 X Anode Col 6 X GPIO Output X The GPIO Data Register receives inputs or provides outputs for each of the seven GPIO Port A lines depending on the configuration of the port See Table 8 Table 8 GPIO Data Register Function Bit 7 6 5 4 3 2 1 0 GPIODO GPIO D1 X GPIO D2 X GPIO D3 X GPIO D4 X GPIO D5 X GPIO D6 X GPIO D7 X LED Matrix The one 7x 5 LED matrix device on the eZ809 Development Platform is a memory mapped device that can be used to display information such as programmed alphanumeric characters For example the LED display UM013904 0203 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 26 z L 8 sample program that is shipped with this kit displays the alphanumeric message eZ80 To illuminate any LED in the matrix its respective anode bit must be set to 1 and its corresponding cathode bit must be set to 0 Bits 0 6 in Table 7 are LED anode bits They must set High 1 and their corresponding cathode bits bits 0 4 in Table
45. g the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 62 through 64 2 The Power and Ground nets are connected directly to the eZ80F92 device 3 External capacitive loads on RD WR MREQ 00 07 and 23 should be below 10 pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register UM013904 0203 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual Z 16 21106 Connector Figure 7 illustrates the pin layout of I O Connector in the 50 pin header located at position JP2 on the eZ80 Development Platform Table 3 describes the pins and their functions PB7 PBS PB3 PB1 GND EXT PC6 PC4 PC2 PCO PD6 PD5 PD3 PD1 TDO GND EXT TCK RTC VDD IICSCL IICSDA FLASHWE 3 RESET V3 3 EXT HALT SLP V3 3 EXT PB6 PB4 PB2 PBO PC7 PC5 PC3 PC1 PD7 GND_EXT PD4 PD2 PDO TDI TRIGOUT TMS EZ80CLK GND_EXT DIS_IRDA WAIT GND_ EXT NMI HEADER 25X2 IDC50 Figure 7 eZ80 Development Platform Connector Pin Configuration JP2 Operational Description PRELIMINARY 0 013904 0203 eZ80F92 Development Kit
46. h A7FFFFh If SRAM memory is installed in a different order than the above sequence SRAM will not be contiguous unless the user is able to change the address decoder U10 Memory access decoding is performed by this address decoder implemented in the Generic Array Logic device GAL22LV10D U10 On Chip SRAM The eZ80F92 device on the eZ80F92 Flash Module contains 8KB of on chip SRAM Upon power up this SRAM is enabled and mapped to the top 8KB of memory address space Using the RAM Address Register this 8KB memory can be mapped to the top of any 64KB block It can also be disabled Please see the eZ80F92 eZ80F92 Product Specification 50153 for more information Flash Memory The eZ80F92 Development Kit allows off chip Flash memories between 1MB and 4MB This Flash memory is entirely located on the eZ80F92 Flash Module in footprint only as shipped from the factory external Flash is not installed Memory Map A memory map of the eZ80 CPU is illustrated in Figure 10 Flash mem ory and SRAM on the eZ80F92 Flash Module are addressed when CSO and CS1 are active Low SRAM on the eZ80 Development Platform is addressed when CS2 is active Low The location of on chip SRAM is programmable by setting the RAM address upper byte register The upper 8 of any 64 KB memory page can be selected Addresses to enabled on chip memories assume priority over all chip selects Please refer to the eZ80F92 eZ80F92 Product Speci fication
47. hese push buttons serve as input devices to the eZ80F92 microcontroller The programmer can use them as necessary for applica tion development All push buttons are connected to the GPIO Port B pins PBO The PBO push button switch SW1 is connected to bit 0 of GPIO Port B This switch can be used as the port input if required by the user UM013904 0203 PRELIMINARY Operational Description 34 eZ80F92 Development Kit User Manual z L G PB1 The PB1 push button switch SW2 is connected to bit 1 of GPIO Port B This switch can be used as the port input if required by the user PB2 The PB2 push button switch SW3 is connected to bit 2 of GPIO Port B This switch can be used as the port input if required by the user RESET The Reset push button switch SW4 resets the 62 805 CPU and the eZ809 Development Platform Jumpers The eZ80 Development Platform provides a number of jumpers that are used to enable or disable functionality on the platform enable or disable optional features or to provide protection from inadvertent use Jumper J2 The J2 jumper connection enables disables IrDA transceiver functional ity When the shunt is placed IrDA communication is disabled See Table 13 Table 13 J2 DIS IrDA Shunt Status Function Affected Device In IrDA interface disabled UARTO is configured to work with the RS232 or the RS485 interfaces Out IrDA interface enabled The IrDA and UARTO interfaces on the eZ
48. ication modules Application Module interface 2 male headers e GPIO and LED matrix e RS232 serial communications ports Embedded modem interface devices UM013904 0203 PRELIMINARY 780 Development Platform eZ80F92 Development Kit User Manual Z 8 z L o G Peripheral Device Signals Address Bus eZ80 1 Flash MPU Module Data Bus Interface 1 RS232 0 Console SRAM 512 up to 2 MB 4 RS232 1 Modem GPIO and Address Decoder Application Module Headers Figure 4 Basic eZ80 Development Platform Block Diagram Functional Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G Physical Dimensions The dimensions of the eZ809 Development Platform PCB is 177 8 mm x182 9mm The overall height is 38 1mm See Figure 5
49. in to enable the socket modem Reference the appropriate documentation for the socket modem to reset timing requirements User Triggers Two general purpose trigger output pins are provided on the eZ80 Development Platform Labeled J21 Trig2 and J22 Trig1 these pins allow the user a way to trigger external equipment to aid in the debug of the system See Figure 8 for trigger pin details J21 J22 Ground 5 7 Trigger output Trig2 Trig1 Figure 8 Trigger Pins J21 and J22 Bits 6 and 7 in Table 9 are the control bits for the user triggers If either bit is a 1 the corresponding Trig1 and Trig2 signals are driven High If either bit is 0 the corresponding Trig and Trig2 signals are driven Low UM013904 0203 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 28 21106 Embedded Modem Socket Interface The eZ80 Development Platform features a socket for an optional 56K modem a modem is not included in the kit Connectors J1 J5 and J9 provide connection capability The modem socket interface provided by these three connectors is shown in Figure 9 Tables 10 through 12 identify the pins for each connector The embedded modem utilizes UART1 which is available via the Port C pins Figure 9 Embedded Modem Socket Interface J1 J5 and J9 Table 10 Connector J5 Pin Symbol Description 1 M TIP Telephone Line Interface TIP 2 M RING Telephone Line Interface RING Op
50. inal if required Modem Connector P3 provides a terminal for connecting an external moden if used with the eZ80F92 Development Kit RS485 functionality will be available in future 62805 devices IC Devices The two 12 devices on the eZ809 Development Platform are the U2 EEPROM and the U13 Configuration register The EEPROM provides 16KB of memory The Configuration register provides access to control the configuration of an application specific function at the Application Module Interface Neither device is utilized by the eZ80F92 Development Kit software The user is free to develop proprietary software for these two devices The addresses for accessing these devices are listed in Table 23 Table 23 2 Addresses Device Bit 7 6 5 4 3 2 1 0 EEPROM U10 1 0 1 0 0 A1 AO Configuration Register U13 1 0 0 1 1 1 0 R W Note EEPROM address bits AO and A1 are configured for Os I2C Devices PRELIMINARY 0 013904 0203 eZ80F92 Development Kit User Manual z L o G 41 DC Characteristics Understanding proper DC current requirements for the 780 Develop ment Platform when application modules are plugged into it is very important for developing applications This section provides an estimate of the average current requirement when different combinations of these application modules are plugged in to the eZ809 Development Platform The receiver supply current is 90 150 and the transmitter supply cur rent i
51. is set to Low The eZ80F92 Flash Module contains a ZiLOG IrDA transceiver that is connected to the UARTO port This port can be used as a wireless connec tion into the eZ80F92 Flash Module The UARTO can connect to a stan dard RS232 port or it can be configured to control the IrDA transceiver Operational Description PRELIMINARY UMO013904 0203 eZ80F92 Development Kit User Manual z L o G 49 however it cannot do both at the same time Only a few registers are required to configure the UARTO port to send and receive IrDA data The RxD and TxD signals on the transceiver perform the same functions as a standard RS232 port However these signals are processed as IrDA 3 16 coding pulses sometimes called IrDA encoder decoder pulses When the IrDA function is enabled the final output to the RxD and TxD pins are routed through the 3 16 pulse generator Another signal that is used in the eZ80F92 Flash Module s IrDA system is Shut_Down SD The SD pin is connected to PD2 on the eZ80F92 Flash Module The IrDA control software on the user s wireless device must enable this pin to wake the IrDA transceiver The SD pin must be set Low to enable the IrDA transceiver On the eZ80F92 Flash Module a two input OR gate is used to allow an external pin to shut down the IrDA transceiver Both pins must be set Low to enable this function Figure 14 highlights the eZ80F92 Flash Module IrDA hardware connec tions External Disable
52. istor ensure that the device is located at the end of the interface line Operational Description PRELIMINARY UMO013904 0203 eZ80F92 Development Kit User Manual z L o G 39 Jumper J18 The J18 jumper connection controls the selection of the RS485 termina tion resistor circuit When the shunt is placed the RS485 termination resistor circuit is enabled See Table 22 Table 22 J18 RT 2 Shunt Status Function Affected Device In The Termination Resistor for RS485 2 is IN RS485 interface Out The Termination Resistor for RS485 2 is OUT RS485 interface Note Before enabling the termination resistor ensure that the device is located at the end of the interface line Connectors A number of connectors are available for connecting external devices such as the ZPAKII emulator PC serial ports external modems the con sole and LAN telephone lines J6 and J8 are the headers or connectors that provide pin outs to connect any external application module such as ZiLOG s Thermostat Applica tion Module Connector J6 The J6 connector provides pin outs to make use of GPIO functionality Connector J8 The J8 connector provides pin outs to access memory and other control signals UM013904 0203 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 40 21106 Console Connector P2 is the RS232 terminal which can be used for observing the console output P2 can be connected to the HyperTerm
53. lity The Flash Loader utility allows the user a convenient way to program on chip Flash memory Please refer to the External Flash Loader Product User Guide PUGO0016 for more details Mounting the Module When mounting the eZ80F92 Flash Module onto the eZ80 Development Platform check its orientation to the platform to ensure a correct fit Pin 1 of JP1 on the eZ809 Development Platform must align with pin 1 of JP1 on the eZ809 Development Platform Pin 1 of JP2 on eZ80F92 Flash Module must align with pin 1 of JP2 on the eZ809 Development Plat form etc UM013904 0203 PRELIMINARY DC Characteristics 51 eZ80F92 Development Kit User Manual 52 z L G Changing the Power Supply Plug The universal 9VDC power supply offers three different plug configura tions and a tool that aids in removing one plug configuration to insert another as shown in Figure 15 Figure 15 9VDC Universal Power Supply Components To exchange one plug configuration for another perform the following steps 1 Place the tip of the removal tool into the round hole at the top of the current plug configuration 2 Press down to disengage the keeper tab and push the plug configura tion out of its slot 3 Select the plug configuration appropriate for your location and insert it into the slot formerly occupied by the previous plug configuration 4 Push the new plug configuration down until it snaps into place as indicated in Figure 16
54. lopment Platform Peripheral Bus Connector Identification JP1 Pin Symbol Signal Direction Active Level eZ80F92 Signal 1 A6 Bidirectional Yes 2 AO Bidirectional Yes 3 A10 Bidirectional Yes 4 A3 Bidirectional Yes 5 GND 6 7 A8 Bidirectional Yes 8 AT Bidirectional Yes 9 A13 Bidirectional Yes 10 A9 Bidirectional Yes 11 A15 Bidirectional Yes 12 A14 Bidirectional Yes 13 A18 Bidirectional Yes 14 A16 Bidirectional Yes 15 A19 Bidirectional Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 62 through 64 2 The Power and Ground nets are connected directly to the eZ80F92 device 3 External capacitive loads on RD WR IORQ MREQ 00 07 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register Operational Description PRELIMINARY UMO013904 0203 eZ80F92 Development Kit User Manual z L o G 13 Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Continued 1 Pin Symbol Signal Direction Active Level
55. lopment Platform Rev This PAL generates signals that control Expansion Module access LED and Port A emulation This device is a GAL22LV10 5JC 5ns equivalent with Package 28 pin PLCC module F92 em pal nDIS EM nEM EN AQ General Array Logic Equations PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G A1 AZ 23 4 A5 A6 AT nRD ncs nlORQ nEM RD nEM WR nAN WR nCT WR nDIS ETH E input nDIS EM synthesis loc P3 nEM EN synthesis loc P4 A0 synthesis loc P5 Al synthesis loc P6 A2 synthesis loc P10 synthesis loc P11 synthesis loc P12 A5 synthesis loc P13 A6 synthesis loc P27 7 synthesis loc P26 nIORQ synthesis loc P2 UM013904 0203 PRELIMINARY General Array Logic Equations 78 eZ80F92 Development Kit User Manual z L o 8 nRD ncs nWR nMEMRQ output nEM RD nEM WR nCT WR WR synthesis synthesis synthesis synthesis synthesis synthesis synthesis synthesis parameter anode 8 h00 loc P7 loc P25 loc P9 loc P16 loc P17 loc P18 LOGS PIO loc P20 nDIS_ETH synthesis loc P21 parameter cathode 8 h01 p
56. n UARTO IrDA CONSOLE The UARTO CONSOLE interface and IrDA interface RS485 interface disabled Out The RS485 circuit is disabled on UARTO IrDA UARTO CONSOLE interface RS485 interface Note To enable the RS485 circuit the corresponding IrDA RS232 circuit must be disabled UM013904 0203 PRELIMINARY Operational Description 38 eZ80F92 Development Kit User Manual Jumper J16 The J16 jumper connection controls the selection of the RS485 circuit However UART1 MODEM interface and the socket modem interface disabled if the RS485 circuit is enabled When the shunt is placed the RS485 circuit is enabled See Table 20 Table 20 J16 RS485 2 EN Shunt Status Function Affected Device In The RS485 circuit is enabled on UART1 UART1 MODEM interface The UART1 MODEM interface and the Socket Modem Interface and Socket Modem interface are disabled RS485 interface Out The RS485 circuit is disabled on UART1 UART1 MODEM interface Socket Modem Interface and RS485 interface Jumper J17 The J17 jumper connection controls the selection of the RS485 termina tion resistor circuit When the shunt is placed the RS485 termination resistor circuit is enabled See Table 21 Table 21 J17 RT 1 Shunt Status Function Affected Device In The Termination Resistor for RS485 1 is IN RS485 interface Out The Termination Resistor for 5485 1 is OUT RS485 interface Note Before enabling the termination res
57. nal Yes 35 D1 Bidirectional Yes 36 D2 Bidirectional No 37 D3 Bidirectional Yes 38 D4 Bidirectional Yes 39 D5 Bidirectional Yes 40 GND 41 07 Bidirectional Yes 42 D6 Bidirectional Yes 43 MREQ Bidirectional Low Yes 44 IORQ Bidirectional Low Yes 45 GND Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 62 through 64 2 The Power and Ground nets are connected directly to the eZ80F92 device 3 External capacitive loads on RD WR MREQ 00 07 and 23 should be below 10 pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register Operational Description PRELIMINARY UMO013904 0203 eZ80F92 Development Kit User Manual z L o G 15 Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Continued Pin Symbol Signal Direction Active Level eZ80F92 Signal 46 RD Bidirectional Low Yes 47 WR Bidirectional Low Yes 48 INSTRD Input Low Yes 49 BUSACK Input Pull Up 10KQ Low Yes 50 BUSREQ Output Pull Up 10KQ Low Yes Notes 1 For the sake of simplicity in describin
58. nclude all steps leading up to the occurrence of the problem Attach additional pages as necessary UM013904 0203 PRELIMINARY Customer Feedback Form
59. nctions of the eZ80F92 Flash Module UM013904 0203 PRELIMINARY Operational Description 20 eZ80F92 Development Kit User Manual z L G Note These three inputs are e Disable Flash DIS_Flash e Flash Write Enable FlashWE Disable IrDA DIS IrDA These three signals are described below Disable Flash When active Low the DIS Flash input signal disables the Flash chip on the eZ80F92 Flash Module Flash Write Enable When active Low the FlashWE input signal enables Write operations on the Flash boot block of the eZ80F92 Flash Module Disable IrDA When the DIS IrDA input signal is pulled Low the IrDA transceiver located on the eZ80F92 Flash Module is disabled As a result UARTO can be used with the RS232 or the RS485 interfaces on the eZ809 Devel opment Platform These inputs are only used if external Flash is present on the eZ80F92 Flash Module as shipped from the factory external Flash is not installed Application Module Interface An Application Module Interface is provided to allow the user to add an application specific module to the eZ809 Development Platform ZiLOG s Thermostat Application Module not provided in the kit is an example application specific module that demonstrates an HVAC control system Implementing an application module with the Application Mod ule Interface requires that the eZ80F92 Flash Module also be mounted on Operational Description PRELIMINARY UMO013904
60. nthesis loc P24 enables LED and Port A emulation nDIS FL synthesis loc P25 nL RD synthesis loc P23 wire nCS EX 1 2 nmemen3 nmemen4 wire MOD DIS nmemen1 0 nmemen2 0 nmemen3 0 nmemen4 0 if of the signals is Low Flash on the Module will be disabled if nDIS FL is High wire nEXP EN nCS0 0 amp A7 0 amp A6 1 expansion module wire nDIS_FL UM013904 0203 Flash enabled if this is 0 nFL_DIS EN nFL_DIS PRELIMINARY General Array Logic Equations 76 eZ80F92 Development Kit User Manual 2 212110686 wire nDIS_FL nFL_DIS amp nEXP_EN if either of them is 0 Flash is disabled assign nCS EX nEX FL DIS 2 nEXP EN nEX FL DIS assign nL RD nmemen1 0 nmemen2 0 nmemen3 0 nmemen4 0 EN 0 nCS EX 0 assign nmemen4 nCS2 20 amp A7 A6 A5 A4 A3 5 h17 assign nmemen3 nCS2 0 amp A7 A6 A5 A4 A3 5 h16 assign nmemen2 nCS2 0 amp A7 A6 A5 A4 A3 5 h15 assign nmemenl nCS2 0 amp A7 A6 A5 A4 A3 5 h14 assign nEM nCS2 0 amp A7 A6 A5 A4 A3 A2 A1 A0 8 h80 endmodule U15 Address Decoder define anode 8 h00 de de fine cathode 13 Fine latch 8 h02 FOR 6280 Deve
61. orporate this Port A feature The eZ80 Development Platform provides additional I O functionality featuring GPIO for devices without Port A an LED matrix a modem reset and two user triggers UM013904 0203 PRELIMINARY Operational Description 24 eZ80F92 Development Kit User Manual 21106 These functions are memory mapped with an address decoder based on the Generic Array Logic GAL221V10D U15 device manufactured by Lattice Semiconductor and a bidirectional latch U16 Additionally U15 is used to decode addresses for access to the 7x5 LED matrix Table 6 lists the memory map addresses to registers that allow access to the above functions The register at address 800000h controls GPIO Port A Output Control and LED Anode register functions The register at address 800001h controls the register functions for the LED cathode modem reset and user triggers Address 800002h controls GPIO Port A data Table 6 LED and Port Emulation Addresses Address Register Function Access 800000h LED Anode GPIO Port output control WR 800001h LED Cathode Modem Trig WR 800002h GPIO Data RD WR Port A Emulation GPIO Port A is emulated with the use of the GPIO Output Control Regis ter and the GPIO Data Register If bit 7 in the GPIO Output Control Reg ister is 1 all of the lines on GPIO Port A are configured as input ports If this bit is 0 all of the lines on Port A are configured as output ports Table 7 lists the multiple functions o
62. p SRAM Real Time Clock with Battery Back Up ZPAKII Debug Interface e eZ80F92 Development Kit Software and Documentation CD ROM Hardware Specifications Table 1 lists the specifications of the eZ809 Development Platform Table 1 eZ80 Development Platform Hardware Specifications Operating Temperature 20 C 5 C Operating Voltage 9 VDC 2 Also available is the eZ80F93 microcontroller which features 64 KB of internal Flash memory and 4KB of internal SRAM Please contact your local ZiLOG Sales Office for details Kit Features PRELIMINARY 0 013904 0203 eZ80F92 Development Kit User Manual 21106 3 eZ80 Development Platform Overview The purpose of the eZ80 Development Platform is to provide the devel oper with a set of tools for evaluating the features of the eZ809 family of devices and to be able to develop a new application before building appli cation hardware The eZ80F92 Development Kit features two primary boards the eZ80 Development Platform and the eZ80F92 Flash Module This arrangement provides a full development platform when using both boards It can also provide a smaller sized reference platform with the eZ80F92 Flash Mod ule as a stand alone development tool The eZ80 Development Platform is designed to accept a number of application specific modules and Z8 and eZ80 based add on modules including the eZ80F92 Flash Module which features a real time clock an IrDA transcei
63. pability The eZ80F92 Development Kit features two primary boards the eZ809 Development Platform and the eZ80F92 Flash Module This arrangement provides a full develop ment platform when using both boards It can also provide a smaller sized reference platform with the eZ80F92 Flash Module as a stand alone development tool Kit Features The key features of the eZ80F92 Development Kit are eZ809 Development Platform Up to 2MB fast SRAM 12ns access time 1 MB factory installed with 512 KB on module 512KB on platform Embedded modem socket with a U S telephone line interface EEPROM configuration register GPIO logic circuit and memory headers Supported by ZiLOG Developer Studio II and the eZ809 C Compiler LEDs including a 7x5 LED matrix Platform configuration jumpers 1 Other members of the eZ80Acclaim product line include the eZ80F91 and eZ80F93 microcon trollers A scaled down eZ80F92 Ethernet Module is also available Contact your local ZiLOG Sales Office for more information UM013904 0203 PRELIMINARY Introduction 1 eZ80F92 Development Kit User Manual 21106 Two RS232 connectors console modem RS485 connector with cable assembly ZiLOG Debug Interface ZDI JTAG Debug Interface 9VDC power connector Telephone jack eZ amp 80F92 Flash Module eZ80F92 microcontroller operating at 20MHz with 128 KB 256bytes internal Flash and 8 KB internal SRAM 512 KB off chi
64. r 2 JP2 PB7 PB6 PBS 5 5 PB4 0 55 GND EXT 5 7 66 5 5 P PC3 1 6 EE ER EXT 9 PD4 0 0 O GND er 2 9 P TRIGOUT TCK TMS RTC_VDD 0 b EZ80CLK 56 b IICSDA b GND EXT E ASHW CS3 b DIS IRDA q b WAIT V33 GND_EXT 2 b NMI 0 D HEADER25X2 IDC50 Schematic Diagrams eZ80F92 Development Kit User Manual iL 71 common power plane 100nF common ground plane no power supply on board Input VDD V3 3 3 3V 5 Power Pmax 1 6W Ptyp 0 4W Current Imax 200mA IrDA not in use for test purposes Imax 460mA IrDA in use cr 100mA 3 don t stuff E NET Module Rev B 98 Figure 29 Schematic Diagram 8 of 9 Power Supply 0 013904 0203 PRELIMINARY Schematic Diagrams 00 7 lt 2 0 7 D 0 7 500 7 A 0 23 SAI0 3 Aj 23 22 00 28 0 1 2 are used here eZ80F92 Development Kit User Manual l 72 Do LZ spp 7 gt SA O 3 EIHRD 8 ETHRD PD 0 7 lt a and 5 ETHWR ETHWR not used here ETHIRQ e ETHIRQ RESET gt p 4 U2D SLEEP A WAIT 52 gt SLEEP gt D6 _ 2 ACTIVE lt T ACTIVE don t stuff 741 2 L_j P RD CS3 CSETH
65. re 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 780 Development Platform Schematic Diagram 5 of 5 RS 485 Cable 63 Schematic Diagram 1 of 9 Top Level 64 Schematic Diagram 2 of 9 100 Pin QFP eZ80F92 DEVICE EET 65 Schematic Diagram 3 of 9 36 Pin SRAM Device 66 Schematic Diagram 4 of 9 NOR Flash Device 67 Schematic Diagram 5 of 9 eZ80F92 Flash Module 68 Schematic Diagram 6 of 9 IrDA Reset 69 Schematic Diagram 7 of 9 Headers 70 Schematic Diagram 8 of 9 Power Supply 71 Schematic Diagram 9 of 9 Control Logic 72 PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 UM013904 0203 eZ80 Development Platform Hardware Specifications 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 12 eZ80 Development Platform I O Connector Identification JP2 17 GPIO Connector J6 21 CPU Bus Connector J8 23 LED and Port Emulation Addresses
66. s 260mA when the LED is active The measurements of current that are shown in Table 24 are for the user s reference These values can vary depending on the type of application that is developed to run with the platform Table 24 DC Current Characteristics of the eZ80 Development Platform with Different Module Loads Current Platform Modules Configurations Requirement mA Status eZ80 Development Platform 173 When connected only to a and eZ80F92 Flash Module power supply and when no program is running 280 Development Platform 174 When connected only to a eZ80F92 Flash Module and Modem power supply and when Module no program is running 280 Development Platform 195 When connected only to a eZ80F92 Flash Module and power supply and when Thermostat Application Module no program is running eZ80 Development Platform 203 When connected only to a eZ80F92 Flash Module Modem power supply and when Module and Thermostat Application no program is running Module 780 Development Platform 325 When the LED demo is and eZ80F92 Flash Module running UM013904 0203 PRELIMINARY DC Characteristics eZ80F92 Development Kit User Manual 42 z L o G Table 24 DC Current Characteristics of the eZ80 Development Platform with Different Module Loads Continued Current Platform Modules Configurations Requirement mA Status eZ80 Development Platform 325 When the LED demo is eZ80F92 Flash Module and Mod
67. t authorized No licenses are conveyed implicitly or otherwise by this document under any intellectual property rights PRELIMINARY 0 013904 0203 eZ80F92 Development Kit User Manual zicog Safeguards The following precautions must be observed when working with the devices described in this document Z N Caution Always use a grounding strap to prevent damage resulting from electrostatic discharge ESD UM013904 0203 PRELIMINARY Safeguards eZ80F92 Development Kit User Manual IV 21106 PRELIMINARY 0 013904 0203 eZ80F92 Development Kit User Manual Table of Contents Safesuards j kak bese RE See eg ER ev Rd 1151 011181868 Vii List f 100165 gt 4 c tigen EO Oba aaa R 1000061160 1 Kit Features che 1 Hardware 2 eZ80 Development Platform Overview 3 eZ80 Development Platform 7 Functional Description 7 Physical Dimensions 9 Operational Description 10 eZ80F92 Flash Module Interface 10 Application Module Interface 20 VO Functionality lt ss sk xt
68. tes the bottom layer silkscreen of the eZ80F92 Flash Module 2 2 9 5 7 LI R KIRE Ulo o ool o 00 R20 25000 4 0 0 4 Uo o 15 o o 08 be c 5 0111111 7 joo m e DID 2200 8 295200 o e ec 111 Jo o o ol gt 9 oo TIN ili gt oo o ames lo o R9 2 un oojoo 2 58 5 oo oars 28 9 tg o Jo o SI SS o lo o C9 ij o oz IRI RM OO gt 2 8 17104 9 o For oo R28 ojoo o olik 7 20 octi o 9 C24 lool Figure 13 eZ80F92 Flash Module Bottom Layer Functional Description PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual z L o G 47 Operational Description The purpose of the eZ80F92 Flash Module as a feature of the eZ80F92 Development Kit is
69. trol and simple I O applications The Thermostat Application module is equipped with an LCD display that can be used to display process control and other physical parameters PRELIMINARY 0 013904 0203 eZ80F92 Development Kit User Manual 21106 55 For additional reading about the Thermostat application please see the Java Thermostat Demo Application Note 104 on zilog com UM013904 0203 PRELIMINARY Application Modules eZ80F92 Development Kit User Manual 56 21106 ZDS ZiLOG Developer Studio 705 II Integrated Development Environ ment is a complete stand alone system that provides a state of the art development environment Based on the Windows Win98SE NT4 0 SP6 Win2000 SP2 WinXP user interfaces ZDS II integrates a language sensitive editor project manager C Compiler assembler linker librarian and source level symbolic debugger that supports the eZ80F92 For further details about ZDS II for eZ80Acclaim products please refer to the ZILOG Developer Studio eZ80Acclaim User Manual UMO0144 ZDS Il PRELIMINARY 0 013904 0203 eZ80F92 Development Kit User Manual 21106 57 Troubleshooting Overview Before contacting ZiLOG Customer Support to submit a problem report please follow these simple steps If a hardware failure is suspected con tact a local ZiLOG representative for assistance Cannot Download Code If you are unable to download code to RAM using ZDS make sure to press and
70. upport For additional troubleshooting solutions see ZDS Online Help For valuable information about hardware and software development tools visit ZILOG Customer Support online Download the latest released ver sion of ZiLOG Developer Studio Get the latest software updates from ZiLOG as soon as they are available UM013904 0203 Schematic Diagrams eZ80 Development Platform Figures 17 through 21 diagram the layout of the eZ80 Development Platform MAG MAO 23 0 DO NOT USE J6 17 AND J6 35 MAS mE MAD gt gt A 23 0 GND 4 DD 5 5 MAT MAT 4 MATS AEN MAZ D MATS avoc 7 D 2 no 242 MAT 5 e 2 MATS GND MAS SDA GND 7 8 D0 010 1 15 16 MAG MATT 17 18 MAT2 MAT
71. ver and the eZ80F92 microcontroller The eZ80 Development Platform together with its plugged in eZ80F92 Flash Module can operate in stand alone mode with Flash memory or interface via the ZPAKII emulator to a host PC running ZiLOG Devel oper Studio 11 Integrated Development Environment 205 IDE software The address bus data bus and all eZ80F92 Flash Module control signals are buffered on the eZ809 Development Platform to provide sufficient drive capability UM013904 0203 PRELIMINARY eZ80 Development Platform Overview 4 eZ80F92 Development Kit User Manual 2 21106 A block diagram of the eZ809 Development Platform and the eZ80F92 Flash Module is shown in Figure 1 Peripheral Device Signals eZ80F92 Address Bus Address Bus eZ80 Flash MPU Data Bus Module Data Bus Interface SRAM 512 KB up to 2 MB Battery amp Oscillator for RTC Transceiver GPIO and Address Decoder Application Module Headers Figure 1 eZ80 Development Platform Block Diagram with eZ80F92 Flash Module eZ80 Development Platform Overview PRELIMINARY UM013904 0203 eZ80F92 Development Kit User Manual 7 z L o 6 5 Figure 2 is a photographic representation of the eZ80 Development Plat form segmented into its key blocks as shown in the legend for the figure E LI v m ND M

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