DP8160 60A DC-DC Intelligent 8V to 14V Input • 0.7V to 2.75V O DC
Contents
1. 3 8 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 14 3 C CO 9 1 TM QiJ70mmFinishedlhle X2 Non Plated Figure 53 Recommended Footprint Top View Notes 1 NUCLEAR AND MEDICAL APPLICATIONS Power One products are not designed intended for use in or authorized for use as critical components in life support systems equipment used in hazardous environments or nuclear control systems without the express written consent of the respective divisional president of Power One Inc 2 TECHNICAL REVISIONS The appearance of products including safety agency certifications pictured on labels may change depending on the date manufactured Specifications are subject to change without notice C is a trademark of Philips Corporation a a BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 34 of 34 Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Power One DP8160G T0502. a ee ee GI UL eee ee BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 8 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONnE hanging the Shape of Power 6 Typical Performance Characteristics 6 1 Dissipation and Efficiency Curves Vin 12 0V 14 4 Vin 8 0V 43 100 98 S 10 26 4 i 96 2v 94 o C 92 s B Vout 1 5V 2 90 4 Vout 2 75V 88 ms 86 Vout 2 75V 3 8496 4 0 4 i 82 5 25 45 65 80 4 i 4 5 15 25 35 45 55 65 eS Load Amps V i Figure 4 Power Dissipation at Vin 12V Figure 1 Efficiency at Vin 8V 9096 8596 Vin 8 0V 12 4 st 80 gt 759 amp 10 set 7096 S 8 4 Vin 8V z VIN 12V 6 60 3 Vout 1 5 55 41 Vout 2 75V 2 50 t 1 i oO 0 5 1 1 5 2 2 5 3 Vo Volts 0 j T 3 Li Li Li Li 5 25 45 65 Figure 5 Efficiency for Vo vs Vin at 60A Load Load Amps Du 6 2 Thermal Derating Figure 2 Power Dissipation at Vin z 8V 70 Vin 12 0V 60 100 r 98 96 9 50 di 2 9496 4 40 92 5 90 5 Vo 1 5V 30 500 LFM 2 5 m s
3. 2 Bus 7 zM7316 zi D Group A amp 00 DP7115 01 DP7115 Q 04 AoDev Group 02 DP7D15 Q 05 Audev E Group E 05 DP7DU Group ABC Auto Un MIFE Phone FIRE S Monie MEE Poll Poll Pal 2 Paralel Bus a gt Command Log Honitoring step on O4 Fep z0le Honitoring step on d Sep z lz Honitoring ep on 4 Sep z lz Device ZM7316 Bus Voltages Devices Faults User Memory Parameter Addi Mame Alas Vendor Package Sue Output Voltage Current Lint Load Hegulation Mangming High 3 Margining Low X Unider violtage x Power Good Loa Power Good Hig 7 Delay Delay Rising Slew Rate Falling Slew Fate Zerol 02 41 28 02 41 29 02 41 30 No Error Pol 00 00 DP7115 DP7115 Powerrne 22212 2 35 V 138 OU mv A nA BA rae Bn 110 130 20 ms 15 ms 0 20 v Ams A50 V ms Pal 01 01 DP7115 DP7115 Pawer ne 282 4 12 2035V 13 84 LET 5A Fax 905 110 130 20 ms 15 ms 0 20 veins X150 V ms 500 kHz 0 Fight cick table to modify displayed parameters or select Edit Preteencas Pol 2 Pal 3 Pal 04 02 04 DP 015 Aure 0 7015 DP 0U Aure Power ne Power One 222x12 222x12 1 85 V 1 520 1389A J24 mis 0 0 mv aa Ax JA Fox 30 1105 130 ms 13 ms 0 20 V ms
4. 2 75V Output POWET ONE hanging the Shape of Power Tracking Protection when Enabled Default Disabled yp Programmable Latching Non Latching 130ms period Threshold Enabled during output voltage ramping up Threshold Accuracy From instant when threshold is exceeded until Delay the turn off command is generated Overtemperature Warning Threshold Always enabled reported in Status register Threshold Accuracy Hysteresis From instant when threshold is exceeded until the warning signal is generated Power Good Signal PG pin Vour is inside the PG window Vour is outside the PG window Default Programmable in 596 steps Default Upper Threshold Programmable in 596 steps Threshold Accuracy Measured at Vo 2 5 2 9oVOo sET Eo 5 Default ey Programmable to 0 10 50 150 Default PG disabled when Vo reaches PG Off Del low threshold Mid PG disabled at turn off command Programmable same as PG On Delay From the instant when threshold is exceeded until status of PG signal changes high Delay Logic Lower Threshold RUE RUNG UU a a ea esr A BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 5 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power 4 Feature Specifications Current Share Active Single Line Connected in Parallel Current Shar
5. 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power the DPM is waiting for the I2C master to complete a transaction and the master has timed out To avoid such timeout related problems set I2C interface timeout to greater than the time required for polling all dPOLs or 150ms whichever is greater See the Power One I2C Z1 K1 Evaluation Board z1c File Edit View Tools Window Help 1 eS ch E Ect ed LH 02 Ba LV Bal E 0 LT sl 2 Home 120 Bus ZM7316 EE Group 00 DP7115 A 01 DP7115 O04 AuxDev ad Signals Events 09 Group B 3 MDin C3 IN2 in IN in IN in 05 AuxDev1 Group C L3 Crowbar Gl RES Min 03 DPYOO FE Enable 4 in IBY high a IBY low IBY Run Time 460 4 h _ Group Status amp Tw PG TR OT OC Lv Ov PY Pal 00 2 036 V Configure legas enm T Paeaer Simulate Command Log Program Monitoring step on 12 2017 03 05 14 Monitoring step on lz Sep Zz lz 03 05 13 orutor Monitoring step on 12 Sep 7017 03 05 14 Ready Xl Error Device Monitoring programming manual referenced above for the equation used to calculated worst case polling duration gt Monitoring amp Status 4 Parametric Display Controls w E Log to File Controls OnOff Controls System Margining Low Mom High Gop4 Goup
6. Ee ee CAUCA NR Ta BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 31 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output la POWET OM S Changing the Shape of Power IEW IBY TO OTHER dPOLS IBYS AREF Ca T x lt _ WRTN 02 CMPSH 3bE ij RES H 3 Rr ORO CAP GND NCP303LSMZT POST HRES N Figure 51 Block Diagram of Typical Multiple Output Application with Digital Power Manager and Interface Notes BCD 00265 Rev 1 0 5 Feb 2013 Page 32 of 34 WWW power one com AZ POWET ONnE DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output hanging the Shape of Power 11 Safety The DP8160 dPOL converters do not provide isolation from input to output The input devices powering DP8160 must provide relevant isolation requirements according to all IEC60950 based standards Nevertheless if the system using the converter needs to receive safety agency approval certain rules must be followed in the design of the system In particular all of the creepage and clearance requirements of the end use safety requirements must be observed These requirements are included in UL60950 CSA60950 00 and EN60950 although specific applications may have other or additional requirements The DP8160 dPOL converters have no internal fuse If required the external fuse needs to be
7. Vin 12V Vout 0 75V Efficiency Vin 1 2V Vourt 1 0V Fsw 500kHz Vin 1 2V Vourt 1 2M Full Load Vin 1 2V Vourt 1 5V Room temperature Vin 12V Vout 1 8V Vin 12V Vout 2 5V Temperature Coefficient Vin 12V Vout 2 5V lout 0 5 lout max Switching Frequency 50 00 Default Duty Cycle Programmable 1 5696 steps 3 125 Characteristics assume external output capacitance consisting of 4 x 22 uF and 1 x 47 uf ceramic XR7 and 4 x 330uF 20mOhm solid electrolytic capacitors unless noted otherwise DP8160 is a step down converter thus the output voltage is always lower than the input voltage ARUM RUMQUE e OM Go ee ee BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 3 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V 0 7V 2 751 Output POWET ONE hanging the Shape of Power 4 3 Protection Specifications Parameter _ ConditionsiDescripion Nom Max Units Output Overcurrent Protection Default Non Latching 130ms period yp Programmable Latching Non Latching Default 35 2 132 Programmable in 11 steps 132 Yolout 5 Output Overvoltage Protection Default Non Latching 130ms period yp Programmable L atching Non Latching Default 130 Vo sET Threshold Accuracy Measured at Vo ser 2 5V Threshold Dela From instant when threshold is exceeded until us
8. 0 37 0 49 0 61 0 73 or 0 86 mV A BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Vour Upper Regulation Limit Operating Curve Without Point Load Regulation VI Curve With Load Regulation Headroom without Regulation Headroom with Load Regulation Light lout Heavy Load Load Lower Regulation Limit Figure 9 Concept of Optimal Voltage Positioning Figure 9 shows a DP8160 dPOL with 0 mv A load current regulation setting Alternating high and low output load currents causes large transients in Vout to appear with each change Tek Stop Ch1 94 2mV Figure 10 Transient Response without Optimal Voltage Positioning As the Load Regulation parameter is increased step offsets in output voltage begin to appear as shown in Figure 10 Page 11 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power Tek Stop Chl Pk Pk 57 6mV Figure 11 Transient Response with Optimal Voltage Positioning The Load Regulation parameter is an important part of Current Sharing It is used to set one dPOL as a master by assigning a lower mV A load regulation than all other dPOLs which share the load as slaves The dPOL with the lowest Regulation parameter sets the effective overall regulation See Current Sharing elsewhere in this document 7 2 Sequencing an
9. 0 50 500 kHz a Figure 47 Evaluation board Configuration Window showing Shared Bus Assignment BCD 00265 Rev 1 0 5 Feb 2013 www power one com Page 28 of 34 WEF DP8160 60A DC DC Intelligent dPOL PN POWET ONe hanging the Shape of Power 9 Included in the architecture of dPWER dPOLs is a mechanism for simulating errors and faults This allows the designer to test their response configuration without actually needing to induce the fault Testing Fault and Error Response 8V to 14V Input e 0 7V to 2 75V Output The Power One GUI supports this feature in the Monitor window when monitoring is active See Figure 48 When monitoring is off the Fault Injection control boxes are disabled and grayed out Monitor Device DM7332 Addr Ox5e 10 400 l Signals E vents Device Mon INO INT in Crowbar 4 FE Enable Lal IN2 in IN3in RES Min La ALD FAIL in IB 1217 V La EW high IBY low 20 30 Hun Time 110 1 h Current A Pol 00 Pol Vo 1 804 DP7115 lo 11 8 amp Power One T 288C Tw PG TA OT OC Uv OW Py Ld Fault Injection 20 30 an 40 20 20 30 HOO Ot Oo Time s rFerrewr gt Monitoring Status Parametric Display Controls Q Log to File itoring 40 50 B Controls OnO Control
10. 180 and 315 respectively Noise is spread evenly across the switching cycle resulting in more than 1 5 times reduction To achieve similar noise reduction without the interleave will require the addition of an external LC filter Tek M pe 2 40mv t 9 60mV 1 005 136115 i Ch4 Pk Pk 33 4mV Ch4 RMS 6 89mV B 127 00 Figure 40 Input Voltage Noise with Interleave Similar noise reduction can be achieved on the output of dPOLs connected in parallel Figure 41 and Figure 42 show the output noise of two dPOLs connected in parallel without and with a 180 interleave respectively Resulting noise reduction is more than 2 times and is equivalent to doubling switching frequency or adding extra capacitance on the output of the dPOLs Page 23 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONnE hanging the Shape of Power Tek EP rrr rrr u 3 i Ch3 Pk Pk CU 21 62mV i E 3 977mV EEE TEE IE EE E PR S EL PON EE SEL PERT B IT ORTI CST PE ETT RC UTC T CST DEE EE PEEL OEE EI FIC SUCRE CRT M 400ns A Ch3 7 3 00mV Figure 41 Output Voltage Noise Full Load No Interleave Tek Stop el S ul 1 n j 9 684mV 3 ali itt MN E ri HENA v j ija i l Ch3 RMS l W 1 410mV ECAC TEN TRES RT CET
11. Ch2 High 1 850 V Ch3 High 1 520 Y Sy so0mv ch2 soomv Mi 00ms A Chl Soomv Ch3 500mV TOSS 139 40 Figure 17 Tracking Turn On Rising Slew Rate is Programmed at 0 5V ms Vinz12V TekRun Trig Ch1 High Soe eii 2 RD Boeles lo frm High 1 850V 7 7 Ch3 High Sh an 4 1 gt 1 SE 500mV Ch2 s 0mv Mi1 00ms A Chl 7 500mV Ch3 S00mV 5 LE RR I m 15 13 80 Figure 18 Turn On with Slew Rates Programmed as follows V1 at 1 0V ms V2 at 0 5V ms V3 at0 2V ms Vin 12V j Trig Ch1 High 2 050 V 2 s Sou s ou ffffeifleeitiminpntim Zee I AE Ch2 High 1 850 V Ch3 High 1 520 V RR I E UI ELIT Ch3 S00mV 1 13 80 Figure 19 Turn On with Sequencing and Tracking Rising Slew Rate Programmed at 0 5V ms V1 and V2 delays are programmed at 5ms Vinz12V BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Tek Run Ch1 High 2 050 V Ch2 High 1 850 V Ch3 High 1 520 V NN UR TU S IR T E PR S E I I T T e t E RE REI IIR I I RI E RR RE E P e a E E RR 500 Ch2 s00mv M4 00ms A Chl 500 Ch3 S00mV amp 60 20 Figure 20 Two outputs delayed 5ms All slew rates at 0 5V ms 7 3 3 Pre Bias In some applications power may leak from a powered circuit to an unpowered bus typically through
12. Environmental and Mechanical Specifications Ambient Temperature Range EN 40 Storage Temperature Ts ED S S S 95 50 Frequency Range Operating Vibration Magnitude sinusoidal oweep Rate Repetitions in each axis Min Max Min Sweep Acceleration Duration Number of shocks in each axis Peak Reflow Temperature Peak Reflow Temperature Lead Plating 100 Matte Tin Moisture Sensitivity Level DP8160 1 per JEDEC J STD 020C DP8160G 1 Non Operating Shock half sine BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 2 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V 2 751 Output POWET ONE hanging the Shape of Power 4 Electrical Specifications Specifications apply at the input voltage from 8V to 14V output load from 0 to 60A ambient temperature from 40 C to 85 C and default performance parameters settings unless otherwise noted 4 1 Input Specifications Input voltage Vin Operating Range 4 2 Output Specifications Ls monomer ero vo o MG Mi Max Output Voltage Setpoint Resolution Output Voltage Setpoint Accuracy 2ND Vo Loop Enabled Dynamic Regulation 50 75 load step Slew rate 1A us Peak Deviation Fsw 0 5MHz Settling Time to 10 of peak deviation Output Voltage Peak to Peak Vin 12V Vout 0 75V Ripple and Noise Vin 1 2V Vourt 1 0V BW z20MHz Vin 1 2V Vourt 1 BV Full Load Vin 12V Vourz2 5V
13. regulation value The Load Regulation setting insures the master will carry a slightly higher share of the common load Load Regulation is set in the Device Configure Output dialog as noted earlier Best sharing is done when the slave devices have two to three steps higher Load Regulation values Less and sharing is slightly unstable ripple noise increases more regulation and sharing becomes much less equal Note that the GUI does not automatically bump up regulation for dPOLs attached to the same regulation bus his must be done by hand Also it is recommended that the dPOL closest to the biggest load element on the shared output bus be set up to act as the group s master BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com 7 9 2 CS and Interleave Since shared busses tend to have relatively high currents interleaving switching of shared bus dPOLs is generally desirable The lowest noise generation is usually achieved when shared bus dPOL interleave phasing is set to approximately equally spaced intervals 7 10 Monitoring Along with status information dPOL converters can monitor their own performance parameters such as output voltage output current and temperature The output voltage is measured at the output sense pins output current is measured using the ESR of the output inductor and temperature is measured by the thermal sensor built into the controller IC Output current readings are adjusted based on temperatu
14. see Figure 12 This allows using the PG pin to reset load circuits properly Power Good protection remains active during margining voltage transitions BCD 00265 Rev 1 0 5 Feb 2013 www power one com The threshold will vary proportionally to the voltage change see Figure 26 The Power Good Warning pulls the PG pin low and changes the PG bit of the status register ST to O When the output voltage returns within the Power Good window the PG pin is released high the PG bit is cleared and the Power Good Warning is removed The Power Good pin can also be pulled low by an external circuit to initiate the Power Good Warning At turn off the PG pin can be programmed to either be pulled low immediately following the turn off command or then when the voltage actually starts to ramp down Reset vs Power Good functionality in Figure 12 Note To retrieve status information Status Monitoring in the GUI dPOL Group Configuration Window should be enabled refer to Digital Power Manager Data Sheet The DPM will retrieve the status information from each dPOL on a continuous basis 7 5 2 Faults This group includes overcurrent overtemperature undervoltage and tracking protections Triggering any protection in this group will turn off the dPOL For UV and OT faults the turn off can be programmed to sequenced or critical turn off behavior 7 5 2 1 Overcurrent Protection Overcurrent protection is active whenever the output
15. voltage of the dPOL exceeds the prebias voltage if any When the output current reaches the OC threshold the POL control chip asserts an OC fault The dPOL sets the OC bit in the register ST to 0 Both high side and low side switches of the dPOL are turned off instantly fast turn off Current sensing is across the dPOLs choke To compensate for copper winding Tc compensation is added to keep the OC threshold approximately constant at temperatures above room temperature Note that the temperature compensation can be disabled in the dPOL Configure Output window or directly via the I C by writing into the CLS register However it is recommended to keep the temperature compensation enabled Page 16 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output AZ POWET ONnE hanging the Shape of Power 7 5 2 2 Undervoltage Protection The undervoltage protection is only active during steady state operation of the dPOL to prevent nuisance tripping If the output voltage decreases below the UV threshold and there is no OC fault the UV fault signal is generated the dPOL turns off and the UV bit in the register ST is changed to 0 The dPOL switch off can be programmed to follow a sequenced or critical turn off 7 5 2 3 Overtemperature protection is active whenever the dPOL is powered up If temperature of the controller exceeds 120 C the OT fault is generated dPOL turns off and
16. y the turn off command is generated Default Catastrophic Off 4 Programmable to Critical Off Catastrophic Off mE Output Undervoltage Protection Default Non Latching 130ms period yp Programmable L atching Non Latching Default 75 Vo sET Programmable in 5 steps Jo Vo sET 5 Threshold Accuracy Measured at Vo set 2 5V 2 9o VUVP SET From instant when threshold is exceeded until the turn off command is generated Default Sequenced Off 4 Programmable to Sequenced Critical Off Delay Overtemperature Protection Default Non Latching 130ms period Programmable Latching Non Latching Turn Off Threshold Temperature is increasing 1390 C Turn On Threshold Temperature is decreasing after the module was fo C shut down by OTP From instant when the controller junction Delay temperature reaches the OTP threshold until the Us turn off command is generated 4 Default Sequenced Off Programmable to sequenced Critical Off Minimum OVP threshold is 0 5V Sequenced Off The turn off follows the turn off delay and slew rate settings Critical Off At turn off both low and high switches are immediately disabled Catastrophic Off At turn off the high side switch is disabled and the low side switch is enabled BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 4 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V
17. 0 DOF 5 0 Turn Off delay in ms 0x00 0ms 0x01 1ms OxOB 11ms default 63ms Figure 15 Turn Off Delay Register DOF 7T 3 Turn On Off Control Once delays are accounted for turn on and turn off characteristics are simply a function of slew rates which are selectable 7 3 1 Rising and Falling Slew Rates Output voltage ramp up and down control is accomplished by programming the rising and falling slew rates of the output voltage supported in the GUI as shown in Figure 12 which is implemented by the DPM through writing data to the TC register Figure 16 To achieve programmed slew rates the output voltage is being changed in 10mV steps where duration of each step determines the slew rate For example ramping up a 1 0V output with a slew rate of 0 5V ms will require 100 steps duration of 20us each Duration of each voltage step is calculated by dividing the master clock frequency generated by the DPM Since all dPOLs in the system synchronized to the master clock the matching of voltage slew rates of different outputs is very accurate as it can be seen in Figure 17 and Figure 22 During the turn on process a dPOL not only delivers current required by the load li but also charges the load capacitance The charging current can be determined from the equation aV lene Croan X BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Where Coan is load capacitance dVp dt is risi
18. A Q 6 2 35 VIAIO 7 2 75 VINIQ Bit4 TCE Temperature Compensation for Current Limitation Enable 0 7 disabled 1 enabled default Bit3 0 3 0 Current Limit set point when Vo Stationary or Falling 0x0 37 0 1 47 OxB 140 default values higher than OxB are translated to OxB 140 Figure 25 Current Limit Setpoint Register CLS 7 5 1 Warnings This group includes Overtemperature Warning and Power Good Signal The warnings do not turn off dPOLs but rather generate signals that can be transmitted to a host controller via the I C bus 7 5 1 1 Overtemperature Warning The Overtemperature Warning is generated when temperature of the controller exceeds 120 C The Overtemperature Warning changes the PT bit of the status register ST When the temperature falls below 117 the PT bit is cleared and the Overtemperature Warning is removed 7 5 1 2 Power Good Power Good PG is an open collector output that is pulled low if the output voltage is outside of the Power Good window The window is formed by the Power Good High threshold that is programmable at 105 or 110 of the output voltage and the Power Good Low threshold that can be programmed at 90 or 95 of the output voltage The Power Good protection is only enabled after the output voltage reaches its steady state level A programmable delay can be set between O and 150ms to delay the release of the PG pin after the voltage has reached the steady state level
19. Addr Bits Default VIH First Vo Setpoint High Byte O0B 8 VIL First Vo Setpoint Low Byte oxoc 8 V2H Second Vo Setpoint High Byte oxoD 8 Second Vo Setpoint Low Byte 0E 8 hird Vo Setpoint High Byte OF 8 Third Vo Setpoint Low Byte Od0 8 Mapping 12 bit data word left aligned 1LSB 2 5mV Note all registers are readable and writeable always write and read the high byte first Figure 8 Output Voltage Setpoint Register VOS 7 1 2 Output Voltage Margining If the output voltage needs to be varied by a certain percentage the margining function can be utilized The margining can be programmed in the dPOL Configuration window or directly via the lC bus using high level commands as described in the DM7300 Digital Power Manager Programming Manual In order to properly margin dPOLs that are connected in parallel the dPOLs must be members of one of the Parallel Buses Refer to the GUI System Configuration Window shown in Figure 47 7 1 3 Output Load Regulation Control Load Regulation provides for dynamic output voltage change proportional to load current This feature helps to improve step load response by changing the VI characteristic slope at the point of regulation This parameter can be programmed in the GUI Output Configuration window shown in Figure 7 or directly via the bus In the DP81607 Load Regulation can be set to one of eight values 0 0 12 0 24
20. Auto Compensation The GUI will calculate compensation settings from either information entered as to output capacitors in the application circuit or if the SysID function has been run the frequency response measured through the SysID function in the target dPOL This method is usually sufficient but is sensitive to accurate accounting of capacitor values and esr The GUI displays the results of running Auto Compensation as a set of graphs and compensation values Manual Compensation The GUI supports manually adjusting feedback compensation parameters As the parameters are changed the GUI recalculates expected frequency and phase performance System Identification SysiID Auto Compensation Hardware built into the dPOL controller that injects pseudo random bit sequence PRBS noise into PWM calculations and observes the response of the output voltage The GUI collects this data and calculates actual system frequency response Having frequency response data allows the Auto Compensation function to have a better idea of actual output filter characteristics when it calculates feedback coefficients Using noise to plumb the output filter requires current values for compensation be good enough that injected signal can be extracted from system noise and the added noise does not trip a fault or error response A moderately workable solution for compensation must be obtained by calculating from assumed system component values befo
21. ER SL COR SRL TRE TUI TNT TET POM SOO CIT ERI GT TORT TNT TT RHET ENG NET ERN TENES RS CE TNT REN ENS END SS ANS MS TOME RET m1 TEA r Ch3 J 3 00mV Figure 42 Output Voltage Noise Full Load 180 Interleave 7 7 4 Duty Cycle Limit The DP8160 is a step down converter therefore Vout is always less than Vw The relationship between the two parameters is characterized by the duty cycle and can be estimated from the following equation DC Vout VIN MIN Where DC is the duty cycle Voy is the required maximum output voltage including margining S the minimum input voltage The dPOL controller sets PWM duty cycle higher or lower than the above to compensate for drive train losses or to pull excess charge out of the output filter to keep the output voltage where it is supposed to be BCD 00265 Rev 1 0 5 Feb 2013 www power one com A side effect of PWM duty cycle is it also sets the rate of change of current into the output filter A high limit helps deal with transients However if this is too high an overcurrent alarm can be tripped Thus DC limiting must be a compromise between supplying drive train losses and avoiding nuisance trips from transient load responses The duty cycle limit can be programmed in the GUI PWM Controller window Figure 37or directly via the IC bus by writing into the DCL register shown Figure 43 The GUI will supply its own estimate o
22. ESD protection diodes The dPWER controller in the DP7120 holds off turn on its output until the desired ramp up point crosses the pre bias point as seen in Figure 21 Tek Run Trig 1 Chi High 3 41 cCh2High T ARRES N E nar See 1 850 V Ch3 High 1 520 V i MU soomV Ch2 s00mv AM4 ooms A Chl Soomv Ch3 S00mV amp Figure 21 Turn On into Prebiased Load V1 and V2 are Prebiased by V3 via a Diode Vinz12V This figure was captured with an actual system where a diode was added to pre bias a 1 5V bus from a 1 85V bus in order to simulate the effect of current leakage through protection circuits of unpowered logic connected to powered logic outputs a common source of pre bias in power systems Page 14 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output AZ POWET ONnE hanging the Shape of Power 7 4 Turn Off Characteristics Turn of captures show that combining turn off delays and ramp rates Note that while turnoff delays have a lower upper time limit as compared to turn on delays all ramp down rates are available independently to turn on and off Tek Prevu pg Ch1 High 2 022 V j 1 835 V Ch3 High 1 507 V chit simy SN jas ETT n Es X ER 1 gt IE 500mV 23 00 Figure 22 Tracking Turn Off Falling Slew Rate is Programmed at 0 5V ms Vinz12V Trig Ch1 High 2 040 V Ch2 High 1 84
23. Lu SINN s 400 LFM 2 0 m s 8696 Vout 2 75 300 LFM 1 5 m s 84 2 20 200 LFM 1 0 m s v 100 LFM 0 5 m s 82 e 30LFM 0 15 m s 8096 10 5 15 25 35 45 55 65 Load Amps 0 20 30 40 50 60 70 80 90 Figure 3 Efficiency at Vin 12V Ambient Temperature C Figure 6 Thermal Derating Curves Vin 12V Vout 2 5V DIAM a BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 9 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power 7T Programmable Features Performance parameters of DP8160 dPOL converters can be programmed via the industry standard communication bus Each parameter has a default value stored in the volatile memory registers detailed in Table 1 The setup registers 00h through 14h are programmed at the system power up When the user programs new performance parameters the values in the registers are overwritten Upon removal of the input voltage the default values are restored Table 1 DP8160 Memory Registers CONFIGURATION REGISTERS Name Register Addrss Protection Configuration 1 Protection Configuration 2 Protection Configuration 3 Tracking Configuration Interleave and Frequency Configuration Turn On Delay Turn Off Delay Voltage Loop Configuration Current Limit Set poi
24. The capacitor improves noise immunity of the dPOL converter DIA AURA ERE NR a BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 6 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V 2 751 Output POWET ONE hanging the Shape of Power I 5 Signal Specifications Parameter Conditions Description 3 45 VDD Internal supply voltage Logic In Max Pull Up Logic max safe input SYNC DATA Line SD pin CO Co os osvo v wo v _ SS DO O w ioWesmarmGos t m ewe wo wo mw _ manoet 9 _ Patapeumentsouce _ os m O m lt m mma ADDRO ADDR4 Inputs LOW level input voltage HIGH level input voltage External pull down resistance ADDRX forced low Power Good and OK Inputs Outputs ViL x 0 25 ViH x VDD 0 5 RdnL ADDR IN x lup PG lup OK ViL x ViH x Vhyst x gt 100 250 0 3 x VDD VDD 0 5 0 3 x VDD Pull up current source input forced low PG Pull up current source input forced low OK 85 0 30 85 LOW level input voltage 0 5 X 2 0 8 HIGH level input voltage 7 x VDD 4 H T gt Hysteresis of input Schmitt trigger LOW level sink current at 0 5V _ 2 Current Share Bus CS pin Pull up current s
25. default Bit 4 PGLL Power Good Low Level 1 95 of Vo 0 90 of Vo default Bit 3 2 OVPL Over Voltage Protection Level 00 110 of Vo 01 120 of Vo 10 130 of Vo default 11 130 of Vo Bit 1 0 UVPL Under Voltage Protection Level 00 75 of Vo default 01 80 of Vo 10 85 of Vo 11 90 of Vo 1 This register can only be written when PWM is not active RUN RUN is 0 Figure 24 Protection Configuration Register PC2 Note that the overvoltage and undervoltage protection thresholds and Power Good limits are defined as percentages of the output voltage Therefore the absolute levels of the thresholds change when the output voltage setpoint is changed either by output voltage adjustment or by margining Overcurrent limits are set either in teh GUI POL Output configuration dialog or in the dPOL s CLS register as shown in Figure 25 Note that the CLS register includes bits which control the Regulation option settings When writing into this register be careful to not change Regulation by accident Page 15 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power CLS Current Limit Setting Address 0x08 R W 0 R W 0 RW 0 RIW 1 RW 1 RIW 0 RIW 1 RIW 1 B Bit 7 it 0 Bit 7 5 LR 2 0 Load Regulation setting 0 0 V A Q default 1 0 39 V A Q 2 0 78 3 1 18 4 1 57 VIAIQ 5 1 96 V
26. fault is removed and the respective bit in the ST register was cleared or the Turn On command was recycled or the input voltage was recycled BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com PC1 Protection Configuration Register 1 Address 0x00 R W 0 R W 1 RW 0 RIW 0 RIW 0 RIW 0 R W 1 RW 1 Bit 7 Bit 0 Bit 7 TRE Tracking fault enable 1 enabled 0 disabled Bit 6 PVE Phase voltage error enable 1 enabled 0 disabled Bit 5 TRC Tracking Fault Protection Configuration 1 latching 0 non latching Bit 4 OTC Over Temperature Protection Configuration 1 latching 0 non latching Bit 3 OCC Over Current Protection Configuration 1 latching 0 non latching Bit 2 UVC Under Voltage Protection Configuration 1 latching 0 non latching Bit 1 OVC Over Voltage Protection Configuration 1 latching 0 non latching Bit 0 PVC Phase Voltage Protection Configuration 1 latching 0 non latching Figure 28 Protection Configuration Register PC1 7 5 6 Fault and Error Turn Off Control In the GUI dPOL Fault dialog is a column of spin controls which set the Turn Off style OT UV and OV events The choices are defined as Sequenced Outputs shut down according to ramp down rate control settings This is the method used when a dPOL is told to do a normal controlled shut down Critical Both high side and low side switches of the dPOL are turned off instantly Emergency The high side switch is turned
27. in is detected The turn off type of a POL fault error as propagated by the faulty dPOL via the OK line is propagated through the DPM to other dPOLs connected to other Groups per configuration in through its connection sew to their OK line or lines This behavior assures that all dPOLs configured to be affected through Group linkages will switch off with the same turn off type 7 5 12 Protection Summary A summary of protection support their parameters and features are shown in Table 2 56 ms 8 50 V 2 50 ms 8 50 V 3 58 ms 0 50 V STOPPED Figure 35 Turn On into UVP on V3 The UV Fault is programmed to be Non Latching and Propagate From Group C to Group A Ch1 V3 Group c Ch2 V2 Ch3 V1 Group A Table 2 Summary of Protection Parameters and Features Turn Low Side Propagation Disable Off d Temperature Warning Whenever Vin is applied BEBE Status Bit Warning During steady state Bal Whenever Vi is applied Regular Off Critical Type When Active Overtemperature When Vour exceeds prebias UV Undervoltage Fault During steady state Critical Emergenc BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 21 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output MS POUMWCI DIITE hanging the Shape of Power 7 6 OK Fault and Error Coding dPWER dPOLs have an additional functionality added to the OK line signal The OK line is use
28. off instantly and simultaneously the low side switch is turned on to ensure reliable protection of sensitive loads 7 5 7 Fault and Error Status The status of each protection circuit is stored in the ST register shown in Figure 29 When Status monitoring is enabled for a group the DPM will read this register and make the information available for uses such as GUI Monitor display Page 18 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output AZ POWET ONnE hanging the Shape of Power ST Status register Address 0x16 R 0 RIW 19 RIW 1 RIW 19 RIW 19 RIW 19 RNW 1 1 1 T or w OV Bit 7 Bit 0 Bit 7 TW Temperature Warning Bit 6 PG Power Good Warning high and low Bit 5 TR Tracking Fault Bit 4 OT Over Temperature Fault Bit 3 OC Over Current Fault Bit 2 UV Under Voltage Fault Bit 1 OV Over Voltage Error Bit 0 PV Phase Voltage Error Note an activated fault is encoded as 0 Writing a 1 into a fault error bit clears a latching fault error Figure 29 Protection Status Register ST 7 5 8 Fault and Error Propagation The feature adds flexibility to the fault management scheme by giving users control over propagation of fault signals within and outside of the system The propagation means that a fault in one dPOL can be programmed to turn off other dPOLs and devices in the system even if they are not directly a
29. 5 V Ch3 High 1 510 V Chi 500mV ae S00mV AMT A Chi X ik 500mV fy 02 62 80 Figure 23 Turn Off with Tracking and Sequencing Falling Slew Rate is Programmed at 0 5V ms Vin 12V 7 5 Faults Errors and Warnings All dPOL series converters have a comprehensive set of programmable fault and error protection functions that can be classified into three groups based on their effect on system operation warnings faults and errors These are warnings errors and faults Warnings include Thermal Overtemperature limit near and Power Good a warning in a negative sense BCD 00265 Rev 1 0 5 Feb 2013 www power one com Faults in dP series POLs include overcurrent protection overvoltage overtemperature tracking failure detection Errors include only undervoltage Control of responses to Faults and Errors are distributed between different dPOL registers and are configurable in the GUI Thresholds of overcurrent over and undervoltage protections and Power Good limits can be programmed in the GUI Output Configuration window or directly via the 12C bus by writing into the CLS and PC2 registers shown in Figure 25 and Figure 24 PC2 Protection Configuration Register 2 1 Address 0x01 R W 0 RW 0 RIW 1 RW 0 RAW 0 R W 0 Sea PGHL PGLL OVPL1 OVPLO UVPL1 UVPLO Bit 7 Bit 0 Bit7 6 Unimplemented read as 0 Bit 5 PGHL Power Good High Level 1 105 of Vo 0 110 of Vo
30. B Time s PSP o Prat i2c HE bcc CLR ALP Figure 46 DPM Monitoring Window 8 Adding dPOLs to a System dPOL converters are added to a dPWER system through the DPM Configuration Devices dialog Clicking on an empty address location brings up a menu which allows specifying which POL type is needed below is an example using all of the DP7000 series devices currently offered Note that Auto On P Monitor and S Monitor options are only configurable by Group and not by individual dPOL configuration These options affect only DPM behavior Enabling them does not burden a dPOL BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Auto On sets a group to turn on once all IBV power is available and dPOLs are configured This defaults to enabled P Monitor enables periodic query of Vout lout and Temp values from each dPOL in the group where it is enabled dPOLs will always measure these parameters in an ongoing basis even if Vout is not enabled S Monitor enables periodic query of POL Status While a DPM will always be able to detect a low OK condition it requires this option enabled for Monitor function to query status registers Page 27 of 34 PN POWET ONE DP8160 60A DC DC Intelligent dPOL 8V to 14V Input e 0 7V to 2 75V Output S Changing the Shape of Power Power Une 1 1 1 K1 Evaluation Hoard z1c FE 2 e ii cd o 3 31 04 LJ LJ Le LE Le TNT umm ft
31. DP8160 60A DC DC Intelligent dPOL m 8V to 14V 0 7V 2 75V Output POWEr ONE hanging the Shape of Power Features e ROHS lead free and lead solder exempt products are available e Wide input voltage range 8V 14V e High continuous output current 60A e Programmable output voltage range 0 7V 2 75V e Efficiency greater than 92 e Active patented current sharing e Single wire serial communication bus between dPOL and Digital Power Manager DPM e Programmable dynamic output voltage positioning for better load transient response e Overcurrent overvoltage undervoltage and Ra overtemperature protections with programmable Compliant thresholds and hiccup or latching modes e Switching frequency 500KHz e Programmable switching phase delay e Programmable turn on and turn off delays e Programmable turn on and turn off output voltage slew rates with tracking protection Applications e Low voltage high density systems with Intermediate Bus Architectures IBA e Point of load regulators for high performance DSP FPGA ASIC and microprocessors e Compensation Desktops servers and portable computing e In System Loop Identification SysID through Broadband networking optical and pseudo random noise injection communications systems e Power Good signal with programmable threshold and delay e Advance fault management and propagation Benefits e Integrates digi
32. Ls Note SD and OK dashed lines TO OTHER dPOLS may be connected The SD line provides synchronization of all dPOLs to the master clock generated by the DPM and simultaneously performs data transfer between dPOLs and the DPM Each dPOL has a unique 5 bit address programmed by grounding respective address pins To enable the current sharing CS pins of dPOLs connected in parallel are interconnected In addition to the SD line the DP8160 is connected to OK A Any other dPOLs added should connect their OK pins to the OK pins of the DPM associated with their respective Group assignments The type value and the number of output capacitors shown in the schematic are required to meet the specifications published in the data sheet However all dPWER dPOLs are fully operational with different configurations of output capacitors The feedback loop compensation may need to be adjusted to optimize performance of the dPOLs for specific parameters of the output capacitors The supervisory reset circuit in the above diagram U2 is recommended for systems where the 3 3V supply to the DPM does not turn on faster than 0 5 V ms Note The DP8160 is footprint compatible with the ZY8160 No change PCB is needed to upgrade to dPWERG parts However configuration data must be altered through the Power One I2C GUI and programmed into the DPM When upgrading to dPWERG mixing ZY and DP series devices is not recommended All parts must be upgraded
33. ault can be cleared by toggling the EN pin or by commanding the dPOL to turn off and turn off again via the GUI interface obviously more convenient Therefore once the fault trigger is cleared click the Off button of the dPOL or Group clears the fault status LEDs turn back to green and then the On button of the dPOL or Group to re enable it Page 30 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output AZ POWET ONnE hanging the Shape of Power 10 Typical Application Shown in Figure 50 is a block diagram of a multiple dPOL power system The key interconnections needed between the DPM and the dPOLs are Intermediate Voltage Bus IBV SD OK A D and between the first two dPOLs which share a bus load their CS connections Each dPOL has its own output bulk filter capacitors This illustrates how simple a dPOL based system is to implement in hardware SD provides synchronization of all dPOLs as well as communication PG not shown is optional though this is usually used with auxiliary power supplies that are not digitally controlled p Intermediate Voltage Bus Crowbar Optional IBV O 4 5 C6 DM7332 VSSVSS VSS VSS VSS VSS 8 9 26 38 43 58 Figure 50 Multi dPOL Power System Diagram Shown in Figure 51 is a schematic of a typical application using at least one DP8160 dPOL although additional DP8160 or other dPWER series dPO
34. ault window or directly via the I C bus by writing into the register 7 5 3 Faults and Margining As noted earlier UV and OV protection settings are a percentage of Vout As Vout ramps between nominal low or high margin values UVP and OVP limits adjust accordingly This is illustrated in Figure 26 The middle plot of Vo Vout level is the result of a Low Margining command Note that Tracking is not re enabled during changes to Vout from margining commands RUN OC enabled PG enabled Vo Rise Vo Stable Vo Fall Vo Stable Vo Rise Vo Stable Vo Fall gt lt 1 0V pre biased output OVP Limit PGLow Limit UVP Limit gt lt Time Figure 26 Protections Enable Conditions BCD 00265 Rev 1 0 5 Feb 2013 www power one com Page 17 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power 7 5 4 Errors This protection group includes only overvoltage protection 7 5 4 1 Overvoltage Protection The overvoltage protection is set as a percentage of Vout It is active whenever the output voltage of the dPOL exceeds the pre bias voltage if any If the output voltage exceeds the overvoltage protection threshold the overvoltage error signal is generated the dPOL turns off and the OV bit in the register ST is changed to 0 The high side switch is turned off instantly and
35. both high side and low side switches are turned off if the slew rate is not programmed Therefore for the slew rate controlled turn off the ramp down time is included in the turn off delay as shown in Figure 14 User programmed turn off delay Tpr jjp __ gt Turn Off Command Calculated Internal delay Tp Ramp down time ramp down i command 3 Vout Falling slew rate Time Figure 14 Relationship between Turn Off Delay and Falling Slew Rate As it can be seen from the figure the internally calculated delay Tp is determined by the equation below Tp EA dT For proper operation Tp shall be greater than zero The appropriate value of the turn off delay needs to be programmed to satisfy the condition If the falling slew rate control is not utilized the turn off delay only determines an interval from the application of the Turn Off command until both high Page 12 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power side and low side switches are turned off In this case the output voltage ramp down process is determined by load parameters DOF Turn Off Delay Configuration Address 0x06 U U RIW 0 RIW 0 RW 1 RW 0 R W R W 1 DOF5 DOF4 DOF3 DOF2 DOF1 DOFO Bit 7 Bit 0 Bit7 6 Unimplemented read as 0 Bit5
36. controller itself will honor Hee U selection of other frequencies through direct access sos MEME es 7 Default manual post optimization CD 18 casesa of pole zero placement might be CV 4 via the I C bus this is not recommended The GUI only supports the one PWM frequency Each dPOL is equipped with a PLL that locks to the Figure 37 PWM Controller Window 500 KHzSD signal which is generated by the DPM This sets up for switching actions to be synchronous to the falling edge of SD by all dPOLs which are thereby kept coordinated to each other Although synchronized to SD switching frequency selection is independent for each dPOL with the exception of shared load bus groups where dPOLs attached to a shared load bus are forced to use the same frequency by the GUI aaa aaa CUM ee ee a aes aaa BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 22 of 34 op WET DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output AZ POWET ONnE hanging the Shape of Power 7 7 2 Interleave Within the same PWM dialog is the switching Interleave control Interleave is defined as a phase delay between the synchronizing slope of the master clock on the SD pin and the start of each dPOL PWM cycle This parameter can be programmed in the dPOL Controller Configure Compensation window or directly via the I C bus by writ
37. d Tracking Turn on delay turn off delay and rising and falling output voltage slew rates can be programmed in the GUI Sequencing Tracking window shown in Figure 12 or directly via the bus by writing into the DON DOF and TC registers respectively The registers are shown in Figure 13 Figure 15 and Figure 16 Comigue Device DP707 Gowa Addr 00 Type Fault Output Sequencing Controller Vokage V Delays Slew Rates Power Good Desplay Tum On Slew Rate Tum On Delay Delay 0 ms 0 20 V ms q V Show other POLs Tum Off Slew Rate Tum Off Show Aux Devices Delay 11 ms 0 50 Vims Left click a trace 7 Slew ate control to display its label during tum off Figure 12 Sequencing Tracking Window BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com 7 2 1 Turn On Delay Turn on delay is defined as an interval from the application of the Turn On command until the output voltage starts ramping up DON Turn On Delay Configuration Address 0x05 R W 0 R W 0 RW 0 RW 0 0 RW 0 R W 0 RW 0 DON7 DONG DONS DON4 DON3 DON2 DON1 DONO Bit 7 Bit 0 Bit7 0 DON 7 0 Turn On delay in ms 0x00 Oms default 0x01 1ms OxFF 255ms Figure 13 Turn On Delay Register DON 7 2 2 Turn Off Delay Turn off delay is defined as an interval from the application of the Turn Off command until the output voltage reaches zero if the falling slew rate is programmed or until
38. d to propagate and receive information from other devices in the power system belonging to the same group as to the kind of turn off procedure a device has initiated because of a fault Figure 36 shows the three types of OK encoding The bubbles show when the SD and OK line logic levels are sampled by dPOL and DPM logic s V UUU iuWYwW Sequenced Off Fast Off Error Off Figure 36 OK Severity Encoding Waveforms Note that the OK line state changes are always executed by dPOLs at the negative edge of the SD line The chart shows shut down response types as the user can select the kind of response desired for each type of Fault or Error within the limits of choice provided for each type of Fault or Error All dPOL devices in the same Group are expected to trigger the same turn off procedure in order to maintain overall tracking of output voltages in the system And when fault propagation is set to go from one group to another the encoding is passed along un changed 7 7 Switching and Compensation a dPWER dPOLs utilize the digital PWM controller Clone a based on m The controller enables users to program most of the j E cit performance parameters such as switching Magnitude Z Phase frequency PWM duty cycle and limiting interleave wee and feedback loop compensation E 2 C Output Impedance 7 7 1 Switching Frequency TUE The switching frequency for the DP8160 is fixed at E Sa SOOKHz Although the
39. e ug c Fault Injection 0 LIEIETMIEPIEIEIEI 40 50 Device Monitoring B bl Time s gt Monitoring amp Status Parametric Display Controls w 5 Log to File Controls A On Off Controls System GA v 0n Margining Low Nam High Goupb Gop Group D Front End Send Cmd Crad r Bl 90 r al 90 Figure 49 Example Overtemp Fault Injection in the GUI In Figure 49 we see the effects of injecting an Overtemp OT fault Note that dPOL 0 shows an OT fault dPOL 0 and 1 are in the same Group and fault propagation for the dPOL is to propagate to the group dPOL 4 and above are in Groups B and C Propagation is not enabled from Group A to B The OT fault shows up as an orange indicator in the dPOL and RUN status LEDs Group LEDs show yellow indicating all of the members of the group have shut down Fault recovery depends whether the fault is a latching or non latching fault A non latching fault is cleared by unchecking the checkbox clears the fault trigger The dPOL will re BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com start after the 130ms time out of non latching faults hiccup time Group and System follows restart Latching faults clear in one of two ways The first method is to clear the fault trigger uncheck the checkbox note the dPOL remains off since the fault is latching Alternately a latched f
40. e Accuracy lout 220 lout Nom eee Interleave Default Degree Sequencing Default ms Turn ON Delay Programmable in 1ms steps ms 63 ms Default IBN OPIDO Programmable in 1ms steps E os 0 05 5 0 V ms Cm Programmable in 7 steps 0 05 5 0 V ms Optimal Voltage Positioning Load R lation Default mV A QAU TIR MAG Programmable in 7 steps 1 3 mV A Feedback Loop Compensation I Tracking Default Programmable in 7 steps Default Turn ON Slew Rate Turn OFF Slew Rate Proportional Programmable Integral Programmable e O o Differential Programmable Differential Roll Off Programmable Voltage Monitoring Accuracy 12 Bit Resolution over 0 5 2 75V 0 5 Current Monitoring Accuracy 20 lout lt lout S lout 20 Temperature Monitoring Accuracy SURCHOD 5 Remote Voltage Sense VS VS pins Between VS and VOUT Between VS and PGND e i i i e O 1 o Voltage Drop Compensation ev lt Voltage Drop Compensation Timing based functions such as Turn ON Delay are clock count based and subject to the accuracy limits of the SD signal Achieving fast slew rates under specific line and load conditions may require feedback loop adjustment S if the voltage sense outputs are connected remotely it is recommended to place a 0 01 0 1uF ceramic capacitor between VS and VS pins as close to the dPOL converter as possible
41. e of Power 7 5 10 Front End and Crowbar As shown in the propagation dialog if an error is propagated the DPM can be configured to generate commands to turn off a front end a DC DC converter generating the intermediate bus voltage or trigger crowbar protection to accelerate removal of the IBV voltage The two options are independent of inter group propagation and may require some external hardware to interface to the IBV or crow bar SCR device 7 5 11 X Propagation Examples Understanding Fault and Error propagation is easier with the following examples The First example is of of non propagation from a dPOL as shown in Figure 32 An undervoltage error shuts down the Vo but since propagation was not enabled OK A is not pulled down and Vo2 stays up DP7120 Vo1 Voz Vo3 Yod x v v Figure 32 No Group Fault Propagation Figure 33 shows a scope capture an actual system when undervoltage error detection is set to not propagate In this example the dPOL connected to scope Ch 1 encounters the undervoltage fault after turn on Because fault propagation is not enabled for this POL it alone turns off and generates the UV fault signal Because a UV fault triggers the sequenced turn off the dPOL meets its turn off delay and falling slew rate settings during the turn off process as shown in the trace for Chi Since the UV fault is programmed to be non latching the dPOL wvill attempt to restart every 130 ms repeating t
42. f the best DC limit if the Propose button is clicked DCL Duty Cycle Limitation Address 0x09 RIW 1 RW 1 RW 1 RAW JR W 0 DCL5 DCL4 DCL3 DCL2 DCL1 DCLO LL Bit 7 Bit7 2 DCL 5 0 Duty Cycle Limitation 0x00 0 0x01 1 64 0x02 2 64 Ox1F 63 64 Bit 1 0 Unimplemented Read as 0 Figure 43 Duty Cycle Limit Register 7 7 5 Feedback Loop Compensation Programming feedback loop compensation allows optimizing dPOL performance for various application conditions For example increase in bandwidth can significantly improve dynamic response The dPOL implements a programmable PID Proportional Integral and Derivative digital controller to shape the open loop transfer function for desired bandwidth and phase gain margin Feedback loop compensation can be programmed in the GUI PWM Controller window by setting Kr Proportional Ti Integral Td Derivative and Tv Derivative roll off parameters or directly writing into the respective registers CP Cl CD B1 Note that the coefficient Kr and the timing parameters Ti Td Tv displayed in the GUI do not map directly to the register values It is therefore strongly recommended to use only the GUI to set the compensation values The GUI offers 3 ways to compensate the feedback loop Page 24 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power
43. ffected by the fault 7 5 8 1 Fault Propagation When propagation is enabled the faulty dPOL pulls its OK pin low This signals to the DPM and any other dPOL connected to that signal that the dPOL has a Fault or Error condition A low OK line initiates turn off of other dPOLs connected to the same OK line with the same turn off behavior as the faulty dPOL The turn off type is encoded into the OK line when it transitions from high to low 7 5 9 Grouping of dPOLs Interconnecting dPOL OK lines a dPOLs can be arranged in several groups to simplify fault management A group of dPOLs is defined as a number of dPOLs with interconnected OK pins A group can include from 1 to 32 dPOLs f fault propagation within a group is desired the propagation bit needs to be checked in the GUI Fault Management Window The parameters can also be programmed directly via the IC bus by writing into the PC3 register shown in Figure 31 In order for a particular Fault or Error to propagate through the OK line to other groups Propagation needs to be checked in the GUI dPOL Configure Fault Management Window shown in Figure 30 BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Configure v Device 2 7332 Addr Ox5e ID 65535 Type Bus Voltages Devices Faults User Memory Turn On Fault Propagation All correctly programmed Devices will start up Only Groups with no programming error will start up System doesn t start
44. he process described above until the condition causing the undervoltage is removed The 130ms hiccup BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com interval is guaranteed regardless of the turn off delay setting LeCroy 58 ms 8 50 V 2 50 ms 8 50 V 3 56 ms 0 58 V STOPPED Figure 33 Turn On into UVP on V3 The UV Fault is programmed to be Non Latching Ch1 Vo1 Ch2 Vo2 Group A Ch3 Vo3 Group B Vo4 not shown The next example is intra group propagation the dPOL propagates its fault or error events Here fault propagation between POLs is enabled the dPOL powering output Vol again encounters undervoltage error It pulls its OK line low Since the dPOL powering output Vo2 Ch3 in the picture belongs to the same group A in this case pulling down OK A tells that dPOL to execute a regular turn off DPM DM7300 Group B DP7120 DP7120 DP7115 Vo1 Vo2 Vos Vo4 x x v v Figure 34 Intra Group Fault Propagation Since both Vo1 and Vo2 have the same delay and slew rate settings they will continue to turn off and on synchronously every 130ms as shown in Figure 35 until the condition causing the undervoltage is removed Page 20 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONE hanging the Shape of Power Note that the dPOL powering the output Vo2 Ch3 actually reaches its voltage set point before the error
45. if there is a programming error This setting affects the Group auto turn on feature and also the Group System I2C turn on commands Changing this option requires the DPM to be power cycled after programming Group Fault Propagation To On Error FE OM of Bar A ODODO Eu dB OTOC 0 O O O O O E O O O Interrupt Propaqation Figure 30 Fault and Error Propagation Window Note that the turn off type of the fault as it propagates through the DPM will remain unchanged Propagation options for dPOLs can be read or set in the dPOL PC3 register shown in Figure 31 PC3 Protection Configuration Register 3 Address 0x02 RIW 1 RIW 1 RIW 1 R W 1 RIW 1 RW 1 I me p om oc Uve T ove PvP Bit 7 Bit 0 Bit7 6 Unimplemented Read as 0 Bit 5 TRP Tracking Protection Propagation 0 7 disabled 1 enabled Bit 4 OTP Over Temperature Protection Propagation 0 disabled 1 enabled Bit 3 OCP Over Current Protection Propagation 0 disabled 1 enabled Bit 2 UVP Under Voltage Protection Propagation 0 disabled 1 enabled Bit 1 OVP Over Voltage Protection Propagation 0 disabled 1 enabled Bit 0 PVP Phase Voltage Protection Propagation 0 disabled 1 enabled Figure 31 Protection Configuration Register PC3 Page 19 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shap
46. ing into the INT register in 22 5 steps INT Interleave Configuration Address 0x04 R W 0 U R W 0 R W 0 R W 0 R W 0 PRST INT3 INT2 INT INTO Bit 0 Bit7 6 1 0 Phase selection 0 Single phase PWMO 1 Dual phase PWMO and PWM2 2 Triple phase PWMO PWM1 and PWM2 3 Quad phase PWMO PWM1 PWM2 and PMW3 Bit 5 FRQ PWM frequency selection 0 500 kHz default 1 1000 kHz Bit4 Unimplemented Read as 0 Bit3 0 INT 3 0 PWM interleave phase with respect to SD line 0x00 0 phase lag 0x01 22 5 phase lag 0x02 45 phase lag 0 1 F 337 5 phase lag Figure 38 Interleave Configuration Register INT 7 7 3 Interleave and Input Bus Noise When a dPOL turns on its high side switch there is an inrush of current If no interleave is programmed inrush current spikes from all dPOLs in the system reflect back into the input source at the same time adding together as shown in Figure 39 BCD 00265 Rev 1 0 5 Feb 2013 www power one com TA 1 20mv jw 22 0mV JA 1 0045 je 296ns Tek Sto p d d 1 Ch4 Pk Pk 52 amV Ch4 RMS 11 3mV Ul 4o0ns E Cha 16 8mv 10 0mV v 0 37 80 Figure 39 Input Voltage Noise No Interleave Figure 40 shows the input voltage noise of the three output system with programmed interleave Instead of all three dPOLs switching at the same time as in the previous example the dPOLs V1 V2 and V3 switch at 67 5
47. ng voltage slew rate and Icue is charging current TC Tracking Configuration Address 0x03 U RWO RW RW 1 RW RW RW R Rt RO SC F2 F1 FO Bit 7 Bit 0 Bit 7 Unimplemented read as 0 Bit6 4 R 2 0 Vo rising slew rate 0 0 05 V ms default when in bus terminator mode 1 0 1 V ms default 2 0 2 V ms 3 0 25 V ms 4 0 5 V ms 5 1 0 V ms 6 2 0 V ms 7 Reserved Bit 3 SC Turn off slew rate control 0 disabled 1 enabled default F 2 0 Vo falling slew rate 0 0 05 V ms 1 0 1 V ms 2 0 2 Vims 3 0 25 V ms default when in bus terminator mode 4 0 5 default 5 1 0 V ms 6 2 0 V ms 7 Reserved Bit 2 0 Figure 16 Tracking Configuration Register TC When selecting the rising slew rate a user needs to ensure that lioan lcuc lt loce Where locp is the overcurrent protection threshold of the DP8160 If the condition is not met then the overcurrent protection will be triggered during the turn on process avoid this dVp dt and the overcurrent protection threshold should be programmed to meet the condition above 7 3 2 Delay and Slew Rate Combination The effect of setting slew rates and turn on off delays is illustrated in the following sets of figures Page 13 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONE S Changing the Shape of Power Tek Run Ch1 High 2 050 V
48. nt Duty Cycle Limit Protection Configuration 4 Output Voltage Setpoint 1 Low Byte Output Voltage Setpoint 1 High Byte Output Voltage Setpoint 2 Low Byte Output Voltage Setpoint 2 High Byte Output Voltage Setpoint 3 Low Byte Output Voltage Setpoint 3 High Byte Controller Proportional Coefficient Controller Integral Coefficient Controller Derivative Coefficient Controller Derivative Roll Off Coefficient STATUS REGISTERS Register Address Name Reg RUN Run enable status 0x15 ST Status 0x16 MONITORING REGISTERS Name Reg VOH Output Voltage High Byte Monitoring Output Voltage Low Byte Monitoring Output Current Monitoring Temperature Monitoring DP8160 converters can be programmed using the Graphical User Interface or directly via the I C bus by using high and low level commands as described in the DPM Programming Manual DP8160 parameters can be reprogrammed at any time during the system operation and service except for the digital filter coefficients the switching frequency and the duty cycle limit that can only be changed when the dPOL output is turned off BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com 7 1 Output Voltage The output voltage can be programmed in the GUI Output Configuration window shown in the Figure 7 or directly via the lC bus by writing into the VOS register shown in Figure 8 Type Fault Output Sequencing Controller Output Voltage Curren
49. ource at VCS OV 084 LOW level input voltage 0 75 x HIGH level input voltage Hysteresis of input Schmitt trigger a LOW level sink current at 0 5V Tr CS Maximum allowed rise time 10 9095 VDD BEEN gt Oo e lup CS ViL CS gt m 0 3 x VDD ViH CS VDD 0 5 0 45 x Vhyst_CS VDD r gt BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com Page 7 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output AZ POWET ONnE hanging the Shape of Power Pin Assignments and Description Buffer Pin Description Ce pe remesas UU ADDRRA 16 1 PU Tie to GND or o or teave floating fort __ i pu on ass rs Tia GND for O or loaro fata fort ions i pu on aes GND 0 or loaro foaina fort ADDR1 9 ai PU dPOL Address Bit 1 Tie to GND for 0 or leave a a for 1 ADDRO a Puo dPOL Address Bit 0 Tie to GND for 0 or leave Tieto GND for 0 or leave floating for4 for 1 xs w i a Nesatve vonage Sense to me neoa BUS waa mme Posiive Volage Sensa posite BorHPOIOSSHO INOHOSQ OF ES 18 20 ii 22 24 Output Voltage Voltage 7 8 17 PGND E Power Ground 12 12 13 Input Voltage Voltage Legend l input O output I O input output P power A analog PU internal pull up
50. power one com Page 1 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V 2 751 Output POWET ONE hanging the Shape of Power Reference Documents DM7300 Digital Power Manager Data Sheet DM7300 Digital Power Manager Programming Manual Power One I2C GEN II Graphical User Interface DM00056 KIT USB to I C Adapter Kit User Manual Ordering Information RoHS compliance Packaging Option No suffix RoHS compliant T050 50 pcs Tray Intelligent POL Converter Current with Pb solder exemption 60A G RoHS compliant for all Q1 1 pc sample for six substances evaluation only 1 The solder exemption refers to all the restricted materials except lead in solder These materials are Cadmium Cd Hexavalent chromium Cr6 Mercury Hg Dpolybrominated biphenyls PBB Dpolybrominated diphenylethers PBDE and Lead Pb used anywhere except in solder i Packaging option is used only for ordering and not included in the part number printed on the dPOL converter label Example DP8160G R1 A 30 piece tray of RoHS compliant dPOL converters Each dPOL converter is labeled DP8160G 2 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings may cause performance degradation adversely affect long term reliability and cause permanent damage to the converter Inductor Temperature Input Voltage applied 40 Input Voltage 250ms Transient 3
51. provided to protect the converter from catastrophic failure Refer to the Input Fuse Selection for DC DC converters BCD 00265 Rev 1 0 5 Feb 2013 www power one com application note on www power one com for proper selection of the input fuse Both input traces and the chassis ground trace if applicable must be capable of conducting a current of 1 5 times the value of the fuse without opening The fuse must not be placed in the grounded input line Abnormal and component failure tests were conducted with the dPOL input protected by a fast acting 32V 25A fuse If a fuse rated greater than 25 is used additional testing may be required In order for the output of the DP8160 dPOL converter to be considered as SELV Safety Extra Low Voltage according to all IEC60950 based standards the input to the dPOL needs to be supplied by an isolated secondary source providing a SELV also Page 33 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power 12 Mechanical Drawings All Dimensions are in mm Tolerances XX X 0 1 XX XX 0 05 60 96 0 25 14 0 25 10 4 220 27 97 0 25 31 67 3 7 Pin 1 Stabilizing Pin x 2 1 27 5 08 2 54 0 64 sq Plastic 1 5 0 64 21 sq Figure 52 Mechanical Drawing 61 3 Dotted line indicates component 08 2 34 x21 1 00mm Finished hole x 23 keepout area 52 2
52. re readings to compensate for the change of ESR of the inductor with temperature A 12 Bit Analog to Digital Converter ADC converts the output voltage output current and temperature into a digital signal to be transmitted via the serial interface 12Bits for the Voltage 8 Bits for the Current and Temperature Monitored parameters are stored in registers VOM IOM and TMON that are continuously updated in the DPM at a fixed refresh rate of 1sec These monitoring values can be accessed via the lC interface with high and low level commands as described in the DPM Programming Manual Shown in Figure 46 is a capture of the GUI System Monitor while operating the ZM7300 Evaluation board 7 10 1 In System Monitoring In system parametric and status monitoring is implemented through the 126 interface appropriate protocols are covered in the ZM7300 DPM Programming Manual The GUI uses the published commands In writing software for I2C bus transactions it is important to note that 126 responses are lower priority in DPM operation than SD bus transactions If an I2C transaction overlaps an SD bus transaction the DPM will put the I2C bus on hold until it completes its SD activity The GUI is aware of this and such delays are transparent When directly polling dPOLs for information setting I2C bus timeouts too low can cause hangups where Page 26 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input
53. re invoking SysID 7 8 Transient Response The following figures show the deviation of the output voltage in response to alternating 25 and 75 step loads applied at 2 5A us The dPOL converter is switching at 500KHz and has 10 22uF ceramic capacitors connected across the output pins Bandwidth of the feedback loop was optimized for slightly overdamped response BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com TekRun J di J3 Trig d Mi1 00ms A Ch3 X 37 0mV 50 0mV 5 70 00 Figure 44 Transient Response with Regulation set to 0 0 mV A As noted earlier increasing the Load Regulation parameter provides load dependant dynamic load positioning This shows up in Tek Run y Trig d iE 50 0mV 5 70 00 Figure 45 Transient Response with Regulation set to 3 72mV A 7 9 Load Current Sharing The DP7007 is equipped with a patented active digital current share function Setting up for current sharing requires both hardware and software configuration actions To set up for the current sharing interconnect the CS pins of the dPOLs that are to share the load in parallel This pulse width modulated digital signal drives the output currents of all dPOLs to approximately the same level the dominant or Page 25 of 34 AZ POWET ONnE DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Outpu
54. s Group A Paon System 40 50 B Margining Low Nom High Gops BmupB O 9 Gop 9 Group D Front End Send Cmd 40 50 Figure 48 Fault Injection Controls In Monitor Window Fault injection into a dPOL requires selecting that dPOL in the POL status dialog in the left column of the Monitoring dialog window As long as the checkbox is checked the fault trigger is present in the dPOL An injected fault is handle by the dPOL in the same fashion as an actual fault It therefore gets BCD 00265 Rev 1 0 5 Feb 2013 WWW power one com propagated to the other dPOLs Groups and shuts down in the programmed Way the dPOL Group System as programmed for that fault Page 29 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power Monitor v Device DM Fa32 Addr 5 Ib 400 Be 4 5 gH 4 PAG La Lad HUM bai La Lal O Signals E vents gt INO in IN2In 4 NT in Nain 4 Crowbar 4 RES FE Enable AC FAIL in IBY high 4 IBY low IBY 1215 V Hun Time 110 1 h 20 az Tw PG TR DT OC UV Dv PY AD C mmo 5 Bra LL 10 CL La Ld La Ld c 0 Pol 00 A 40 En Paon vo umay DP7115 la Bu Power One T 28 8 C Tw PG TR OT OC UY PY La Lad Lad Lad Temperatur
55. simultaneously the low side switch is turned on to ensure reliable protection of sensitive loads The low side switch provides low impedance path to quickly dissipate energy stored in the output filter and achieve effective voltage limitation The OV threshold can be programmed from 110 to 130 of the output voltage setpoint but not lower than 0 5 Also the OV threshold will always be at least 0 25V above the setpoint 7 5 5 Fault and Error Latching The user has the option of setting up any protection option as either latching non latching propagating or non propagating Propagation and Latching for each dPOL is set up in the GUI Device Configure Faults dialog for dPOL as shown in Figure 27 and readable the dPOL register ST1 Figure 28 Type Faut Output Sequencing Controller Trigger Enable Latching Propagate TJum Off Tracking Differential gt Critical 7 Sequenced Over Curent Ei Critical Under Voltage E v Sequenced Over Voltage Fi v Emergency Figure 27 dPOL Fault Management Window If the non latching protection is selected a dPOL will attempt to restart every 130ms until the condition that triggered the protection is removed When restarting the output voltages follow tracking and sequencing settings If the latching type is selected a dPOL will turn off and stay off The dPOL can be turned on after 130ms if the condition that caused the
56. t hanging the Shape of Power master dPOL will tend to carry slightly more of the load than the others In addition to the CS interconnection the DPM must be informed of the sharing configuration This is done in the DPM Configure Devices window shown in Figure 47 Just to the right of each dPOL address set the spin control to one of 10 possible sharing busses the number is an accounting aid for firmware The GUI automatically copies common parameters changed in one dPOL s setup information into all dPOLs connected to the parallel bus Some parameters such as load sharing must be set independently 7 9 1 CS and Regulation Load Regulation is an important part of setting up two or more dPOLs to share load The dPOL designated the master should have a lower Load Regulation setting than the other dPOL s connected to its sharing bus In operation the negative CS duty cycle in each dPOL is proportional to the unit s load current As the loading goes up the negative period gets wider A dPOL which sees CS duty greater than its internally calculated value will increase its output voltage to increase its load share Non zero regulation on the other hand tends to lower output voltage as loading increases It also tends to retard the calculated CS period The effect of these two actions regulation and CS tracking cause the dPOL or dPOLS with higher regulation values to track the loading of the dPOL with a lower
57. t Voltage 20V Current Limit Load Regulation Monitoring Thresholds 5 Over Voltage 25V PG High 22V 110 3 PG Low 18V Under Voltage 15V Margining High 21V lon 1 2nd Vo Loop Enable 2nd Vo Loop Current A Figure 7 Output Configuration Window Note that the GUI shows the effect of setting PG OV and UV limits as both values and graphical limit bars Vertical hashed lines are error bars for the Overcurrent OC limit 7 1 1 Output Voltage Setpoint The output voltage programming range is from 0 7 V to 2 75 V The resolution is constant across the range and is 2 5 mV A Total of 3 registers are provided one should be used for the normal setpoint voltage the other two can be used to define a low high margining voltage setpoint Note that each register is 16bit wide and that the high byte needs always to be written read first The writing of the low byte triggers the refresh of the whole 16bit register the high byte is written to a shadow register Unlike other configuration registers the dPOL controllers VOS registers are dynamic Changes to VOS values can be made while the output is enabled over the I2C bus through register bypass commands and the dPOL will change its output immediately Page 10 of 34 DP8160 60A DC DC Intelligent dPOL 8V to 14V Input 0 7V to 2 75V Output PN POWET ONe hanging the Shape of Power VOS Output Voltage Set Point Address OxOB 0x10 Coefficient
58. tal power conversion with Start up into pre biased load intelligent power management Real time voltage current and temperature e Eliminates the need for external power measurements monitoring and reporting management components e Industry standard size through hole single in line e Completely programmable via industry standard package 2 4 0 55 IC communication bus e height of 1 1 e One part that covers all applications Wide operating temperature range 0 to 70 C e Reduces board space system cost and e UL 60950 1 CSA 22 2 No 60950 1 07 Second complexity and time to market Edition IEC 60950 1 2005 and EN 60950 1 2006 Description Power One s digital point of load APOL converters are recommended for use with regulated bus converters in an Intermediate Bus Architecture IBA The DP8160 is the second generation intelligent fully programmable multiphase step down point of load DC DC converter integrating digital power conversion and intelligent power management When used with DM7300 Series Digital Power Managers the DP8160 completely eliminates the need for external components for sequencing tracking protection monitoring and reporting All parameters of the DP8160 are programmable via the industry standard IC communication bus and can be changed by a user at any time during product development and service UD CAUCA RDUM NEUE ee eee BCD 00265 Rev 1 0 5 Feb 2013 WWW
59. the OT bit in the register ST is changed to 0 The dPOL switch off can be programmed to follow a sequenced or critical turn off Overtemperature Protection If non latching OTP is programmed the dPOL will restart as soon as the temperature of the controller decreases below the Overtemperature Warning threshold of 110 C 7 5 2 4 Tracking Protection Ramp up and down operations are under control by the dPOL Tracking protection however is active only when the output voltage is ramping up The purpose of the protection is to ensure that the voltage differential between multiple rails being tracked does not exceed 250mV This protection eliminates the need for external clamping diodes Vo between different voltage rails which are frequently recommended by ASIC manufacturers When the tracking protection is enabled the dPOL continuously compares actual value of the output voltage to its programmed value as defined by the output voltage and its rising slew rate If absolute value of the difference exceeds 250mV the tracking fault signal is generated the dPOL turns off and the TR bit in the register ST is changed to 0 Both high side and low side switches of the dPOL are turned off instantly fast turn off The tracking protection can be disabled if it contradicts requirements of a particular system for example turning into high capacitive load where rising slew rate is not important It can be disabled in the dPOL Configure F
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