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SH7216/SH7239/SH7231 Groups Data Transfer Within On

1. tENESAS APPLICATION NOTE SH7216 SH7239 SH7231 Groups ges R01AN1263EJ0100 Data Transfer Within On Chip RAM Burst Mode Rev 1 00 Using the DMAC Dec 07 2012 Abstract This application note describes a sample program for the SH7216 SH7239 and SH7231 Group MCUs that transfers data using the direct memory access controller DMAC in burst mode The operation of this program has the following features e Use of DMAC channel 0 e Use of auto request mode for DMA transfers e Use of burst mode as the bus mode e The transfer source and destination are both in RAM Products SH7216 SH7239 and SH7231 Groups When using this application note with other Renesas MCUs careful evaluation is recommended after making modifications to comply with the alternate MCU RO1AN1263EJ0100 Rev 1 00 Page 1 of 17 Dec 07 2012 ztENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC Contents UNE Tee EE 3 2 Operation Confirmation Conditions cccccceccceeceeceeseeceeeeeceaeeeeaaeeeeeeeceaeeecaaeeeeaeeseneeeseaeeesaeeseneeeeaees 4 3 Reference Application Notes ccccescccceeeeccceeeeeeceeeeeeeaeeeeaaeeeseaaaeeeaeacaaesseaaaeeseeaeeeseeeaeeeseeaaeeeenes 5 Ax Perpheral int TEE 6 E OM WANC eege ci ase sidecases eege eege EZE EES eer Eege eege Ee seed severed 8 Ge TE tele TEE 8 5 2 File Composition rices ected sate ca dncnes Red dedeadinndeeactahced aia aiaia a aac deeg AER 9 53
2. EC 9 54A ee e TEE 9 5 5 FUNCHIOM Specifications c cccicesencecesseceseneseueecuaeccaecerescesvaiecedeneesanceneaecenduetseceaesectenduedeacaecazess 10 Er sFIOWGCM AMS eenegen eseu ee EES 12 566 Malin PROCESSING ET 12 5 6 2 Transfer Source Transfer Destination Memory Area Intialtzaton eeen 13 56 3 INTC initial ati hssr ES aiaia miadan cas 14 564 DM Initialization eise Meed ainena a ria aeaa 15 5 6 5 DMA Transfer Start Processing c cccsseeceeeeeseneeeeaaeeeeneeeeeeeesaaeseeaaeseeeeeseaeeseaaeseeaeeeeeeees 16 5 6 6 DMA Transfer Complete Interrupt PDrocessimg nenn 16 D Reference DOCUIMONt i aise eege a E EES ee EES 17 RO1AN1263EJ0100 Rev 1 00 Page 2 of 17 Dec 07 2012 ztENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 1 Specifications This application note uses the direct memory access controller DMAC to transfer data within internal RAM The sample program sets the DMAC to burst mode and uses auto request as the DMA transfer start factor The sample program performs 128 transfers of 32 bits of data for a total of 512 bytes Table 1 1 lists the peripheral functions used and their uses and figure 1 1 shows the block diagram of the peripheral functions used Table 1 1 Peripheral Functions and Their Applications Direct memory access controller DMAC DMA data transfers Interrupt controller INTC DMA transfer termination processing Internal RAM Transfer source and d
3. dual address DREQ low level detection R01AN1263EJ0100 Rev 1 00 Page 7 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 5 Software 5 1 Operation Overview The sample program writes a pattern to the transfer source memory area in advance and after setting up the DMAC it starts an auto request transfer to the transfer destination memory area by enabling DMAC operation in software Table 5 1 lists the DMAC settings Figure 5 1 presents an overview of this operation Table 5 1 DMAC Settings Item Description Channel used CHO Transfer data length Long word 4 bytes Transfer count 128 transfers 128 transfers x 4 byte data length 512 bytes of data Address mode Dual address mode Transfer request Auto request Bus mode Burst mode Priority Channel priority fixed mode Interrupt An interrupt request is issued to the CPU when the data transfer completes H FFF82000 DMAC Internal RAM ees H FFF81000 SAR 4 512 bytes of data DAR KEE l DMA transfer l i Transfer destination l address 512 bytes of data Legend SAR Source address register DAR Destination address register Figure 5 1 Operation Overview R01AN1263EJ0100 Rev 1 00 Page 8 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 5 2 File Com
4. or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intende
5. software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 9 Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 Itis the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a t
6. src_addr Transfer source memory area start address uint32_t dst_addr Transfer destination memory area start address uint32_t size Memory area size size in bytes memory_init Initializes the pattern local variable written to the transfer data lt 0 destination memory area Initializes the memory access pointer local variable to ptr src_addr the transfer source memory area Writes the pattern and updates the pointer and pattern ptr lt data Has all of the transfer source memory area been initialized Write done Yes Initializes the memory access pointer local variable ptr lt dst_addr to the transfer destination memory area Writes 0 and updates the pointer Has all of the transfer destination memory area been Write done initialized Yes C return p Figure 5 3 Transfer Source Transfer Destination Memory Area Initialization R01AN1263EJ0100 Rev 1 00 Page 13 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 5 6 3 INTC Initialization Figure 5 4 shows the flowchart for INTC initialization Set DMACO interrupt priority e e C y Figure 5 4 INTC Initialization RO1AN1263EJ0100 Rev 1 00 Page 14 of 17 Dec 07 2012 ztENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 5 6 4 DMAC Initialization Figure 5 5 shows the flowchart for DMAC i
7. MA Transfer Complete Interrupt Processing Figure 5 7 shows the flowchart for DMA transfer complete interrupt processing INT_DMACO_DEIO CHCR_0 register Stop DMACO transfers DE bit lt 0 CHCR_0 register Clear transfer complete flag to 0 TE bit lt 0 return Figure 5 7 DMA Transfer Complete Interrupt Processing Reads the register after clearing the flag RO1AN1263EJ0100 Rev 1 00 Page 16 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 6 Reference Documents e Hardware Manual SH7216 Group Users Manual Hardware Rev 3 00 RO1UH0230EJ SH7239 Group Users Manual Hardware Rev 1 00 RO1UHO0086EJ SH7231 Group Users Manual Hardware Rev 2 00 RO1UH0073EJ The latest version can be downloaded from the Renesas Electronics website e Software Manual SH 2A SH2A FPU User s Manual Software Rev 4 00 RO1US0031EJ The latest version can be downloaded from the Renesas Electronics website Website and Support Renesas Electronics website http www renesas com Inquiries http www renesas com contact RO1AN1263EJ0100 Rev 1 00 Page 17 of 17 Dec 07 2012 ztENESAS SH7216 SH7239 SH7231 Groups Application Note REVISION HISTORY Data Transfer Within On Chip RAM Burst Mode Using the DMAC Rev pats Description Summary 1 00 Dec 07 2012 First edition issued All trademarks and registered trademarks are th
8. Value io_dma_init Outline Header Declaration Description Arguments Return Value Main processing void main void This function first initializes the transfer source and transfer destination memory areas Then it initializes the DMAC starts a DMA transfer and waits for that transfer to complete Finally it enters an infinite loop None None Transfer source transfer destination memory area initialization void memory_init uint82_t src_addr uint82_t dst_addr uint32_t size This function writes pattern data to the transfer source memory area It clears the transfer destination memory area to all zeros uint32_t src_addr Transfer source memory area size uint32_t dst_adadr Transfer destination memory area address uint32_t size Transfer source transfer destination memory area sizes in bytes None INTC initialization void io_intc_init void Sets the INTC register None None DMAC initialization void io_dma_init uint32_t src_addr uint32_t dst_addr uint82_t dma_count After clearing the DMAC module standby state this function sets the DMAC registers uint32_t src_addr uint32_t dst_addr uint32_t dma_count None Transfer source memory area size Transfer destination memory area address DMA transfer count number of longwords to transfer RO1AN1263EJ0100 Rev 1 00 Dec 07 2012 Page 10 of 17 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC io
9. _dma_start Outline DMA transfer start processing Header Declaration void io_dma_start void Description Starts a DMA transfer Arguments None Return Value None INT_DMACO_DEIO Outline DMA transfer complete interrupt processing Header Declaration void INT_DMACO0_DEI0 void Description Terminates the DMA transfer and clears the transfer complete flag to 0 Arguments None Return Value None RO1AN1263EJ0100 Rev 1 00 Page 11 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 5 6 Flowcharts 5 6 1 Main Processing Figure 5 2 shows the main processing main Initialize transfer source The addresses of the transfer source transfer transfer destination memory areas destination memory areas and the size are memory_init passed as arguments l Initialize DMAC io_dma_init The addresses of the transfer source transfer destination memory areas and the transfer count are passed as arguments Initialize INTC io_intc_init Start DMA transfer io_dma_start Figure 5 2 Main Processing R01AN1263EJ0100 Rev 1 00 Page 12 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 5 6 2 Transfer Source Transfer Destination Memory Area Initialization Figure 5 3 shows the flowchart for transfer source transfer destination memory area initialization Arguments uint32_t
10. ath errorpath global_volatile 0 opt_range all infinite_loop 0 del_vacant_loop 0 struct_alloc 1 nologo Operating mode Single chip mode Version of the sample code 1 00 Board used ROK572310C0O00BR 3 Reference Application Notes The following application notes are related to this document and should be referred to when using this application note e SH7216 Group Example of Initialization RJJO6B 1073 e SH7239 Group Example of Initialization RO1AN0297EJ e SH7231 Group Example of Initialization RO1AN0322EJ RO1AN1263EJ0100 Rev 1 00 Page 5 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 4 Peripheral Functions This section describes the direct memory access controller DMAC The basic description of this peripheral module is included in the SH7216 Group User s Manual Hardware SH7239 Group User s Manual Hardware and SH7231 Group User s Manual Hardware documents When there are DMA transfer requests the DMAC starts the transfer according to a predetermined channel priority and when the transfer complete conditions are met it terminates the transfer There are three transfer request modes auto request external request and internal peripheral module request The bus mode can be selected to be either burst mode or cycle stealing mode Table 4 1 provides an overview of the DMAC Figure 4 1 shows an example of a cycle stealin
11. d Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer
12. e property of their respective owners A 1 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment
13. er because of the differences in internal memory capacity and layout pattern When changing to products of different tyoe numbers implement a system evaluation test for each of the products Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 4 You should not alter modify copy
14. estination Internal RAM Transfer source a memory area Read gt Initialization DMAC CPU Transfer destination memory area DEIO interrupt Interrupt reception request signal notification Initialization Figure 1 1 Used Peripheral Function Block Diagram RO1AN1263EJ0100 Rev 1 00 Page 3 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 2 Operation Confirmation Conditions The sample code described in this application note has been confirmed to run normally following conditions Table 2 1 Operating Conditions SH7216 Hem Contents MCU used SH7216 Operating frequency Main clock 200 MHz Bus clock 50 MHz Peripheral clock 50 MHz Operating voltage Vcc 3 3 V Integrated development environment Renesas Electronics High performance Embedded Workshop Ver 4 07 00 C compiler Renesas Electronics Renesas SuperH RISC engine Family C C Compiler Package Ver 9 03 Release 00 Compiler options cpu sh2afpu fpu single include WORKSPDIR inc object CONFIGDIR FILELEAF obj debug gbr auto chgincpath errorpath global_volatile 0 opt_range all infinite_loop 0 del_vacant_loop 0 struct_alloc 1 nologo Operating mode User program mode Version of the sample code 1 00 Board used ROK572167C001BR Table 2 2 Operating Conditions SH7239 Hem Conten
15. g normal mode DMA transfer and figure 4 2 shows an example of a burst mode DMA transfer Table 4 1 DMAC Overview Item Description Number of channels e SH7216 and SH7239 8 channels CHO to CH7 Only the four channels CHO to CH3 can accept external requests e SH7231 4 channels CHO to CH3 Only the two channels CHO and CH1 can accept external requests Address space 4 GB Logical address space Transfer data lengths Byte word 2 bytes long word 4 bytes and 16 bytes long word x 4 Maximum transfer count 16 777 216 24 bits transfers Address modes Single address mode and dual address mode Transfer requests External requests internal peripheral module requests auto requests Bus modes Cycle stealing mode normal mode and intermittent mode burst mode Priority Channel priority fixed mode round robin mode Interrupt requests CPU interrupt requests can be generated at data transfer 1 2 complete and at data transfer complete External request detection Low or high level detection and rising or falling edge detection for the DREQ input Transfer request accept signal The active levels for the DACK and TEND signals can be set and transfer complete signal Note The factors supported depend on the MCU RO1AN1263EJ0100 Rev 1 00 Page 6 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC In cycle stealing normal mode the DMAC release
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18. nitialization C io_dma_init Arguments uint382_t src_addr Transfer source memory area start address uint32_t dst_addr Transfer destination memory area start address uint382_t dma_count Transfer count STBCR2 register Clear DMAC module standby state MSTP25 bit lt 0 CHCR_0 register Stop DMACO transfers DE bit 0 Set transfer source address SAR_0 register src_addr Set transfer destination address DAR_0 register dst_addr Set transfer count DMATCR_0 register dma_count CHCR_0 register lt H 80005434 Set up burst mode auto request mode TC bit 1 Set transfer source and transfer destination RLD bit 0 to auto increment eas Enable transfer complete interrupt DM bit B 01 Clear transfer complete flag SM bit Bam RS bit B 0100 H 4 TB bit 1 TS bit B 10 IE bit 1 TE bit 0 DE bit 0 DMAOR register lt H 0001 Set fixed priority Clear status flags Enable DMA mask Figure 5 5 DMAC Initialization RO1AN1263EJ0100 Rev 1 00 Dec 07 2012 PR bit B 00 AE bit 0 NMIF bit 0 DME bit 1 Page 15 of 17 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 5 6 5 DMA Transfer Start Processing Figure 5 6 shows the flowchart for DMA transfer start processing Start DMACO transfers Figure 5 6 DMA Transfer Start Processing CHCR_0 register DE bit lt 1 5 6 6 D
19. position Table 5 2 lists the file used in the sample code Files not generated by the integrated development environment should not be listed in this table Table 5 2 File Used in the Sample Code main c Initialization and DMA transfer processing 5 3 Constants Table 5 3 lists the constants used in the sample code Table 5 3 Constants Used in the Sample Code Constant Name Setting Value Contents IRAM_SRC_ADDR H FFF8 1000 Transfer source start address internal RAM IRAM_DST_ADDR H FFF8 2000 Transfer destination start address internal RAM DMA_COUNT 128 DMA transfer count DMA_ SIZE 4 DMA transfer size 5 4 Functions Table 5 4 lists the functions Table 5 4 Functions Function Name Outline main Main processing memory_init Transfer source transfer destination memory area initialization io_dma_init DMAC initialization io_dma_start DMA transfer start processing INT DMACO DEI DMA transfer complete interrupt handling RO1AN1263EJ0100 Rev 1 00 Page 9 of 17 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC 5 5 Function Specifications The following tables list the sample code function specifications main Outline Header Declaration Description Arguments Return Value memory_init Outline Header Declaration Description Arguments Return Value io_intc_init Outline Header Declaration Description Arguments Return
20. s bus rights to another bus master each time the transfer of a single transfer unit byte word longword or 16 byte unit completes If there is a transfer request after that the DMAC reacquires bus rights from the other master once again performs a single transfer unit transfer and when that transfer completes releases bus rights to another bus master This operation is repeated until the transfer complete conditions are met Cycle stealing normal mode can be used in all transfer periods regardless of the transfer request source transfer source or transfer destination DREQ Bus rights are temporarily returned to the CPU e a Bus cycle CPU CPU CPU DMAC X DMAC CPU DMAC X DMAC CPU Read write Read write Figure 4 1 Cycle Stealing Normal Mode DMA Transfer Example dual address DREQ low level detection In burst mode once the DMAC has acquired bus rights it continues the transfer operations without releasing those rights until the transfer complete conditions are met However in external request mode when level detection is used for DREQ if the DREQ signal transitions away from the active level after the DMAC transfer request that was already accepted completes bus rights will be passed to another bus master even if the transfer complete conditions are not met DREQ Bus cycle x CPU E CPU D CPU X omac X pmac X DMAC X DMAC X CPU X CPU X Read Write Read Write Figure 4 2 Bus Mode DMA Transfer Example
21. ts MCU used SH7239A Operating frequency Operating voltage Integrated development environment Main clock 160 MHz Bus clock 40 MHz Peripheral clock 40 MHz Vcc 3 3 V Renesas Electronics High performance Embedded Workshop Ver 4 07 00 C compiler Operating mode Renesas Electronics Renesas SuperH RISC engine Family C C Compiler Package Ver 9 03 Release 02 Compiler options cpu sh2afpu fpu single include WORKSPDIR inc object CONFIGDIR FILELEAF obj debug gbr auto chgincpath errorpath global_volatile 0 opt_range all infinite_loop 0 del_vacant_loop 0 struct_alloc 1 nologo Single chip mode Version of the sample code 1 00 Board used RO1AN1263EJ0100 Rev 1 00 Dec 07 2012 ROK572390C000BR Page 4 of 17 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Burst Mode Using the DMAC Table 2 3 Operating Conditions SH7231 Hem Contents MCU used SH7231 Operating frequency Main clock 100 MHz Bus clock 50 MHz Peripheral clock 50 MHz Operating voltage Vcc 3 3 V Integrated development Renesas Electronics environment High performance Embedded Workshop Ver 4 08 00 C compiler Renesas Electronics Renesas SuperH RISC engine Family C C Compiler Package Ver 9 04 Release 00 Compiler options cpu sh2afpu fpu single include WORKSPDIR inc object CONFIGDIR FILELEAF obj debug gbr auto chgincp
22. when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable Differences between Products Before changing from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different tyoe numbers may diff

SH7216/SH7239/SH7231 Groups Data Transfer Within On

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