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1. 39 17 What to do after add remove input output signals in a VHDL file 4 18 How to create a VHDL file for the schematic file cccnnnnnnoconononococonononononcnnnnnnnnnnnn nos 42 I9 How 10 COPY a DEO GCL eseboeeie nti esbnctr rtm eyes aiea EA stris vetas ee i EE EER 43 20 Howtochanee tope A 44 21 How t change revision Name oce eme ae oi ete tese o nte testam taies ot nd aciei atm e edu 8 45 22 How to use In System Sources and Probes EditOr ccccccccccccccnococononeninnnoninininininininininenos 48 25 HowTo sta USDA eo 54 December 3 2013 1 1 Create a new project Notice that you should create a working directory in the local disk e g D of the PC before creating a new project Getting Started With Quartus Il Software Start Designing Start Learning Designing with Quartus N software The audio video interactive tutorial teaches requires a project you the basic features of Quartus N software ct reate a New Proje New Project Wizard Open Recent Project Testi test2 light1 light _ YHDL Click Create a New Project New Project Wizard Introduction The New Project Wizard helps you create a new project and preliminary project settings including the Following Project name and directory Name of the top level design entity Project files and libraries Target device Family and device EDA too
2. Location gt Locat For Help press Fl hon Idle NUM PR P nne JU ee H os pee Te pe gt 7 5 T Tutorial DET Ei Labblista TINE po Cabresult aut Ej Exam result h Y Inkorgen Mi For example the revision name is used as the name of the file to be downloaded into FPGA M Quartus I C work Teaching TNE094 Lab_test Demo_2 demo_2 demo 1 1 demo_1_1 cdf e7 WSOP 80 AS File Edit Processing Tools Window a Hardware Setup USB Blaster USB 0 Enable real time ISP to allow background programming for MAX II devices TR TA Ton ali Stop demo 1 1 sof adi Auto Detect gt lt Delete Cab Add File li Change File C Add Device 4 Up I Down For Help press F1 December 3 2013 45 If you want to change the revision name click Project gt Revisions Specify the current revisian for the project create a new revision delete an existing revision or edit the description of a revision Hevisians demo 1 1 demo 2 C escription for revision demo 1 1 coa Click the button Create In other versions of Quartus II the window may also look like the following one Click lt lt new revision gt gt to create a new revirsion Specity the current revision for the project create a new revision delete an existing revision or edit the description of a revision
3. DELI amp S P o amp counter_example 3 2 QSS D P rw SO P Project Navigator x Counter example bdf Files B we Counter27bit vhd En F das Seven seg vhd gt A i Y Counter_example bdf le VIII e amp 6 58 G8 GO S G GO S GO B O e GO B8 B o e GS G G S GO G GO o GO 9G S GS eo G G S G O o o G 8 S8 o GO G G GO S GO G GO S GO GO G 9 S S 9 GO 9 3 M Sar _ Ji T a Type Message OOOO 11 o System A Processing Extra Info A Info A Warning Critical Warning Error A Suppressed A Flag Message Locatiot Loca For Help press F1 313 10 5 B9 X ide B2 dient V 2 Client O 2 Micro Gy Tutorial Quartus Tutorial Z Adobe A E Seagate sv 11 45 Click the file symbol at the bottom of the Project Navigator Double click Counter27bit vhd to open it Alternatively if you don t want to open the VHDL file you can right click on the file name Counter27bit vhd in the file list and choose Create Symbol files for Current file in the pop up menu December 3 2013 16 Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example Counter 27bit vhd api File Edit View Project Assignments Processing Tools Window Help x D c ki ASA gm o Counter
4. OK Assign node line names to the other 3 lines The result is shown in the following window save the file December 3 2013 28 F Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example Counter_example bdf pa ta File Edit View Project Assignments Processing Tools Window Help x Deug amp de Bag Ca Counter exampte dx 2 SES v M me 60 P i Seven seg vhd Counter example bdf Project Navigator x E Files P abe Counter27bit das Seven seg vk gt 4 71 1 PE ea oe oh T eee 6 a en CE ee ral a ai i E g ir Clk clkbit23 H gt FT clkbit25 F BB mood clkbit28 111111111 bed 3 0 display 0 6 L m inst lt wu a m D Message Al E Locate For Help press F1 335 242 5 m Idle EE dB Client Client 3 2 Micro T torial Z Quartus DE1_ tuto Z Adobe A Quartus December 3 2013 29 11 Specify the unused pins setting Click Assignments gt Device in the main toolbar the Device window is shown Select the family and device you want to target for compilation You can install additional device support with the Install Devices command on the Tools menu Device family Show in Available devices list Family Package Devices Al ha Pin count Any hi Target device Speed grade Name filte
5. Pa Counter_example bdf Cyclone Il EP2C20F 484C7 Ej De Counter_example q is bo Counter2 bit inst i BOO bcd seginstl Due ane bij ee E an Nel TU EA oe Oo a 1441254424 174 48 setze m Sey bod 3 0 dispyp 0 ppt rat 3 A E M AA A T D Lana a aa are d ee P ka cu Ctrl X een es EE ooo rr clkbit2 m Losa ea o eaa a E A use BF oe ES S RE MA DUNG ES Copy Ctrl C no a al OA E Lee BE BR WOMEN nh PEDI qM X Delete Del a e es 2144 dh 3 A RN ES Locate Ld RN tet eae Soy ond had AEREA A NA espana oo tesis Mau wd 4 4 E45 9 a A A AA Plug In Me e DOR o EH mis AA ER ON E O Rod Reg SC ae EU Mia aa a io le a ea e Open Design File ee ee III III III 1111111111111 1127 B update Symbol or Block TAO 24 E ab am ad pri 1111111111111 111111171 4h Flip Horizontal rosa a red A Flip Vertical ariond E AE A O Rotate by Degrees 2 Spo A e eee iii ware FW AW RE E QEON n d oH Dun a Sale d n REOR EE b ces e eho ome ae 8 6 oa LOR i li Zoom b gt Properties System A Processing A Extralnfo A Info A Warning A Lriical waming A Error A Suppressed A Flag un o Cn m wu ui pu 8 Message t L 3catiot Locate Edit selected symbol in the Symbol Editor 216 178 Teba lt Idle Start B2 cient V 2 Clientt Inkorgen E Page cle E Quartus II f DE1_tutorials my Tutorial co Sy lt 0 10 28 Select Edit Selected Sy
6. Properties 27 Click Add All Notice that you should have already copied all files in the directory S TN E 094 Digitalteknik och konstruktion VHDL and assignment files to your project December 3 2013 14 directory Alternatively you can also click and navigate to your project directory and find the VHDL files Settings Counter_example Category Libraries Select the design Files you want to include in the project Click Add All to add all design files in the o Device project directory to the project Operating Settings and Conditions Compilation Process Settings REN 1 rt H EDA Tool Settings MEME m ee ae te H Analysis amp Synthesis Settings Filename Type Libram Design entry gt Fitter Settings Counter bit whd WHOL File Mone E Timing Analysis Settings Seven_seg vhd HDL File lt None gt Ren Assembler Counter example bdf Block Diaqgra None gt j m Design Assistant Dy SignalT ap Il Logic Analyzer Logic Analyzer Interface Simulator Settings Simulation Verification Simulation Output Files T PowerPlay Power Analyzer Settings SSM Analyzer ok Cancel The list shows that two VHDL files are added to your project Click OK December 3 2013 15 5 Create a symbol for a VHDL file ts File Edit View Project Assignments Processing Tools Window Help
7. 18 752 lt 1 e fal combinational functions 43 18 752 lt 1 Fow Compilation E Dedicated logic registers 27 18 752 lt 1 Total registers 27 P Compile Design 00 00 33 Total pins 8 315 3 El Analysis amp Synthesis _ 00 00 11 u Total vitual pins 0 Gi gt Fitter Place amp Route 00 00 12 Total memory bits 0 239 616 0 H P Assembler Generate programming files 00 00 06 Embedded Multiplier 9 bit elements 0 52 0 H P Classic Timing Analysis 00 00 04 Total PLLs 0 4 0 gt EDA Netlist Writer Wb Program Device Open Programmer Revision name 4 n h y Info Command quartus tan read settings files off write settings files off demo 2 c demo 1 1 timing analysis only Warning Found pins functioning as undefined clocks and or memory enables y Info Clock CLOCK 50 has Internal fmax of 149 63 MHz between source register Counter27bit inst state 24 and destination register Counter27bit inst state 12 Y Y Y Info tco from clock CLOCK 50 to destination pin HEX0 5 through register Counter27bit inst state 26 is 10 268 ns Info Quartus II Classic Timing Analyzer was successful 0 errors 1 warning E Info Quartus II Full Compilation was successful 0 errors 435 warnings L3 4 n E _ System 17 A Processing 58 A Estralnfo A Info 52 A Warming 6 A Critical Warning Suppressed 5 _ Message of 581 t
8. 9 9 o o 9 o 9 9 v o o 9 o 9 9 o v o o o 0 o 9 v 9 9 o 9 o v 9 9 o o 9 o 9 3 0 9 o 9 o 9 9 o c9 9 o 9 o o o 9 9 o 3 9 9 o n PA O D o Ee P d CREDAM LET ERI Bud aoa cate NN 1 Ee A uu Q UHDUUNNUDBUNBNBUUNDBDNINUSUNUNNS o e om om o9 9 v o 9 9 9 9 9 9 n n9 Clk clkbit23 Ano Rees os ee 2l dd ra i wea Bla C AIRE HIS ADIRI eee bd Sa a ar A A KC XM 18 eo A clkbit25 ER o 2 4 9 o 9 o e e e e e e e M 9 e e o e 9 e vw e c wo 8 O om om d om o 9 o m D 0 8 n9 9 n n9 n9 n clkbit26 wo 9 o9 o9 o9 o9 o9 o9 9 9 9 o9 o9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 c9 9 9 9 9 9 9 o o e 9 o o 0 0 MI A EN A A Rr eee A AA fay EN D did A a e ai do AO delz 1 Info Li cc EE AAA i Info Running Quartus II Create Symbol File i Info Command quartus map read settings files on write_ settings files off Counter example c Counter example generate_symbol i Info Quartus II Create Symbol File was successful 0 errors 0 warnings T lt o System 16 A Processing 4 Extralnfo A Info 4 A Warning Critical Warning Error A Suppressed A Flag Message of 10 F Locati EST For Help press F1 512 117 hae Idle ha 1 J Start 8 2 client to V 2 Clientto O 2 Microsof ww Tutorial cou Quartus II Tutorial cou Z Adobe Acr
9. View Project Assignments Processing Tools Window Help Dung c do Ba B Ca Counter_exampie HLB D Fro bd OH Oo Project Navigator v diy Cyclone Il EP2C20F48 fe Counter dm New Tool AENA Compare Altera SS AED Devices ription Edition Processor Free Subsc QUARTUS II Version 9 1 View Quartus Il Information Documentation a Message i System Processing Extralnfo Info Warming Criticalwaming A Error Suppressed Flag 3 Message Location Lacate For Help press F1 rmssswI i Select File gt New December 3 2013 9 SOPC Builder System Design Files AHOL File lock Diagram Schemat EDIF File State Machine File Systemyerilog HDL File Tel Script File Verlag HDL File WHEL File gt Memory Files Hexadecimal Intel Farmat File Memory Initialization File Yertication sDebugging Files In System Sources and Probes File Logic Analyzer Interface File SignalT ap Il Logic Analyzer File Vector Waveform File Other Files AHDL Include File Block Symbol File Chain Description File Synopsys Design Constraints File Text File Cancel Select BlockDiagram Schematic File and click OK December 3 2013 10 F Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example Block1 bdf fl File Edit View Project Assignments Processing Tools
10. c Specify the width of the probe port The width can be from 0 bit to 256 bits d Specify the width of the source port The width can be from 0 bit to 256 bits 7 On page 3 of the MegaWizard Plug In Manager you can click Advanced Options and specify other options including the following m What is the initial value of the source port in hexadecimal Allows you to specify the initial value driven on the source port at run time m Write data to the source port synchronously to the source clock Allows you to synchronize your source port write transactions with the clock domain of your choice m Create an enable signal for the registered source port When turned on creates a clock enable input for the synchronization registers You can turn on this option only when the Write data to the source port synchronously to the source clock option is turned on 8 Click Next December 3 2013 50 Parameter Settings source probe The megafunction does not have any simulation model files and can not be simulated 9 Click Next Parameter Summary settings Turn on the files you wish to generate A gray checkmark indicates a file that is source probe automatically generated and a green checkmark indicates an optional file Click Finish to generate the selected files The state of each checkbox is maintained in subsequent source 7 0 MegaWizard Plug In Manager sessions probe 3 0 The MegaWizard Plug In Manager create
11. Processing 4 A Extralnfo A Info 4 A Warning Critical Warning Error Suppressed A Flag E Message D of 10 Al For Help press F1 ho Boe Idle EN Start 8 Client to W2Clientto O 2 Microsof wh Tutorial cou i Quartus II Tutorial cou 8 Adobe Acro Click the sign to expand Project in the Libraries box December 3 2013 18 Libraries E Project ET bod seg EF Dounterz7bit c alera S1spz quartus librarie Repeatinsert mode Insert symbol as bloc Cr ft wizard Flu M egawzard Plug in Manager cancel Select Counter27bit Libraries E Project Et bed seg ii Courntere bit Ec Valtera 91 sp2 quartus libraries Clk clk bite clkbit24 clkbit25 clkbit26 M ame Counter 7bit El Repeatinsert mode nsert symbol as block M egawzard Plug in Manager aed Click OK December 3 2013 19 Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example Counter_example bdf a x el File Edit View Project Assignments Processing Tools Window Help Osa S k ER oc Counter_example X 2 DO Dr X P SH A 209 20 2 Compilation Report abe Counter27bit vhd abe Seven seg vhd Project Navigator vT x deh Counter example bdf EA Files ias Counter27bit vhd EC ET m i D Counter_example bdf le eo o 9 9 9 9
12. See Chapter 13 Programming FPGA Chip of this document Running the In System Sources and Probes Editor 1 Open the In System Sources and Probes Editor Click Tools gt In System Sources and Probes Editor If you have not programed FPGA chip you should do Steps 2 5 to program FPGA chip Otherwise you can skip Steps 2 5 2 In the JTAG Chain Configuration pane point to Hardware and then select the hardware communications device You may be prompted to configure your hardware in this case click Setup 3 From the Device list select the FPGA device to which you want to download the design the device may be automatically detected You may need to click Scan Chain to detect your target device 4 In the JT AG Chain Configuration pane click to browse for the SRAM Object File sof that includes the In System Sources and Probes instance or instances The sof may be automatically detected 5 Click Program Device to program the target device Instance Manager The Instance Manager pane provides a list of all ALTSOURCE PROBE instances in the design and allows you to configure how data is acquired from or written to those instances The following buttons and sub panes are provided in the Instance Manager pane m Read Probe Data Samples the probe data in the selected instance and displays the probe data in the In System Sources and Probes Editor pane m Continuously Read Probe Data Continuously samples the probe data of the
13. Window Help 20 m X D cU amp Ea R c Counter_example x SSeS Dr vrs ora exe Block1 bdf Project Mavigator Cyclone Il EP2C20F 48 TU i AAA CPC CR Crece i 3 Counter q CA A A ANN RN 1 o System A Processing Extra Info A Info A Warning Critical Warning Error A Suppressed A Flag wu ui For Help press F1 111 176 Idle pug pd R Select File gt Save as to change the file name to a new name This file name of the schematic will be used as the top level design entity name of your whole design You should choose the same name as the name of top level design entity However please notice that the file name for the schematic cannot be the same as any entity name in the VHDL codes December 3 2013 11 db Senast anvanda dokument Den har datorn Mina X Counter example n tverksplatser Filnamn Counter exam Filformat Block Diagram Schematic File bdf v Add file to current project Click Spara Notice that the file name Counter_ example should be the same as the top level design entity name December 3 2013 12 4 Open an existing VHDL file and add it to a project P Quartus Il E Arbets teaching Altera Sche_VHDL_projects T utorial_counter Counter_example Counter_example Counter_example bdf ta File Edit View Project Assignments Processing Tools Window H
14. allow background programming for MAX Il devices RE CE TR 77 Js JE Ez L ounter example sof EP2C20F484 00149795 FFFFFFFF LI LI n Auto Detect 33 Add File di Change Fie i severe S Add Device d Pom For Help press F1 Make sure the Mode is JTAG Click Start If Start 1s not clickable as shown in the following window click Hardware Setup December 3 2013 34 5 Quartus tercio A 77 IEA File Edit Processing Tools Window Hardware Setup No Hardware Mode TAG Progress Enable real time ISP to allow background programming for MAX II devices sa e TA en TERT TEE Tem TT Te p Auto Detect X Delete Cab Add File i Change File G Save File C Add Device p Down For Help press F1 Click Hardware Setup at the upper left corner of the window Hardware Setup Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware No Hardware Mo Hardware Available hardware items VETAT LIGB Hardware Sever Part Add Hardware LIS B Blaster Local USB 0 Remove Hardware In the pull down menu for Currently selected hardware select USB Blaster USB 0 Click Close Now Start should be clickable Notice that
15. exist Do you want to create it December 3 2013 43 20 How to change top level entity Sometimes you need to change top level entity before compiling the design For example after copying a project if you click File gt Save As to change the file name of the schematic to a new name you need to change the top level entity Click Assignments gt Settings Click General You can change the top level entity for the design however itis recommended that vau create a new revision for each entity in order to maintain settings information i Operating Settings and Conditions H Compilation Process Settings Top lewel entity dema 1 TE H EDA Tool Settings 3 Analysis amp Synthesis Settings Recently selected top level entities femo 1 gt Fitter Settings oor ME H Timing Analysis Settings ass oo Assembler Design Assistant Signal ap Il Logic Analyzer Logic Analyzer Interface H Simulator Settings PowerPlay Power Analyzer Settings ie SSN Analyzer Type a new Select an entity entity name from an entity list Cancel Select an entity from the pull down list for Top level entity Some entity names in the list are the entity names in the VHDL codes Notice that entity names may be different from the VHDL file names There is also an entity name for the schematic in the list The entity name is the same as the file name of the schematic If the new entity name for the
16. i Info Running Quartus II Create Symbol File y y Info Quartus II Create Symbol File was successful 0 errors 0 warnings 5 System 16 A Processing 4 A Extralnfo A Info 4 A Warning Critical Warning Error A Suppressed A Flag un o 8 Message D of 10 F Locatior oe For Help press F1 272 194 Mol A a i es Start dB dientto V 2 Clientto 8 2 Microsof A Tutorial cou Y Quartus II Tutorial_cou Z Adobe Acro Ssv amp 14 02 7 Importing assignments You should use the assignment file DE1 pin assignments csv for your project In this assignment file input and output signal names are assigned to the pins of FPGA These pins of FPGA are connected to various components on the printed circuit board Click Assignments gt Import Assignments in the main toolbar Import Assignments Specify the source and categories of assignments to import File name Categories e Copy existing assignments into Counter_example qsf bak before impor Advanced OR Cancel Click to find the assignment file December 3 2013 21 Select File b O Tutorial counter qe db incremental db Senast anvanda Counter_example gsf dokument T Skrivbord E E pa e Mina dokument EN DE1 pin assignmenbs Es ms Den har datam Mina nabverksplatser Filnamn DET pin assignments Filformat Import Files qsf est act
17. lt Idle rz Start B2 Client t V 2 Client t Inkorgen Page 7 cle Y Quartus II G DEI tutorials Y Tutorial co s KOB 10 29 Double click on the name of the signal Port Properties General Font Format clk bite lt lt same as port name gt Hide alias when symbol is instantiated in design file Type OUTPUT Default statuz Used Change the signal name and click OK Save the file December 3 2013 40 Update symbols Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example Counter_example b df Ta File Edit View Project Assignments Processing Tools Window Help 0 x D hkbg amp b Ea B x cu Counter_example x PIB D Wr SH bk G ES m Project Navigator Counter27bit vhd ffs Counter_example bdf Counter27bit bsf v x Ey Cyclone Il EP2C20F484C7 E der Counter example q i pbo Dounter2 bitinst H abd _ HD D O TERE Uem HE EUN Pe M 1 AS pend L lbod 01 dspryp s ur p d Bl pv TE clkbit25 i Dot ake ero eG d du EE clkbit26 lt REGA bed seg inst a Disce Symbol or Blei sod PE suele ray dosis sme iit ro d iilam x c2 NM PE ec SUP S RR NOCERE QNM NN A ease ven Eis mi af D die sese d cis sire s UG lt Show b Insert Message va o System A Processing Extra Info A Info A Warning Criti
18. o o o 9 B 9 a e e o 9 e a o 6 o a e e a 9 o e e e e n e d gO IR A ee I IRR ee ee ee er ee ee ee eee eee ee o e e e e e o e o e e e ee e e v e e e o e e o e e e e e e e e o ee e e ee e i e Counter_example bdf le A LA a a a A a e a a a a aa aa a A NS a a ara tae a S PT dl C gt H Ck clkbit23 D Neid si oa Syed O IO i clkbit24 bed 3 0 display D 6 sos Now m 8 a eo mo EOS m Rm p m e clkbit25 H i RA NA i clkbit26 Info Started Create Symbol File at Thu May 20 13 18 26 2010 V steuropa normaltid Info Ended Create Symbol File at Thu May 20 13 18 31 2010 V steuropa normaltid Started Create Symbol File at Thu May 20 13 22 24 2010 V steuropa normaltid Info Ended Create Symbol File at Thu May 20 13 22 28 2010 V steuropa normaltid Info Import completed 445 assignments were written out of 445 read Erre E non global assignments were skipped because of entity ne I lt gt S lll ritical Warning Suppressed A Flag 5 ystem 17 A Processing 4 A Extra Info A Info 4 A Warning un Message 0 of 17 For Help press F1 36 304 J Start B 2 Client to V 2 Clientto 6 2 Microsof CY Tutorial co 4 2 Quartus II Mw DE1_ tutorials Click Orthogonal Node Tool for a single signal in the toolbar Use the tool to connect the input CLOCK 50 to the Clk input of C
19. segment display on DEI The input pins of the display are connected to 7 output pins of the FPGA chip For each pre defined signal name you can find the corresponding pin of the FPGA chip in the column Location The 50 MHz oscillator on DEI has a pre defined input signal name CLOCK 50 and it is connected to the pin PIN LI of the FPGA chip 8 Importing input and output symbols Double click on the blank space of the Graphic Editor window or click on the AND gate icon in the toolbar December 3 2013 23 Symbol Libraries gt Project gt c altera 13 0 quartus libraries Repeat insert mode _ Insert symbol as block Launch MegaWizard Plug In MegaWizard Plug In Manager Click the sign to expand c altera 13 0 quartus libraries in the Libraries box You can expand the hierarchy as show in the follow window to find input and output symbols Notice that you can also find the instructions for importing input and output symbols as in the tutorial tut quartus intro schem pdf Libraries ET Dounterz bit E E cc altera S1sp2 quartuslibre HEY megafunctions FC others HE primitives HA buffer HA logic HA other EME pin HEF bidir x an output storage wea Mame linput B Iw Repeatinsert mode Megawizard Plug In Manager canal Click OK December 3 2013 24 The symbol will appear in the schematic You can move the symbol by using the mouse W
20. selected instance and displays the probe data in the In System Sources and Probes Editor pane you can modify the sample rate via the Probe read interval setting December 3 2013 52 Stop Continuously Reading Probe Data Cancels continuous sampling of the probe of the selected instance m Write Source Data Writes data to all source nodes of the selected instance m Probe Read Interval Displays the sample interval of all the In System Sources and Probe instances in your design you can modify the sample interval by clicking Manual m Event Log Controls the event log in the In System Sources and Probes Editor pane m Write Source Data Allows you to manually or continuously write data to the system The status of each instance 1s also displayed beside each entry in the Instance Manager pane The status indicates 1f the instance 1s Not running Offloading data Updating data or 1f an Unexpected JTAG communication error occurs This status indicator provides information about the sources and probes instances in your design In System Sources and Probes Editor Pane The In System Sources and Probes Editor pane allows you to view data from all sources and probes in your design The data is organized according to the index number of the instance The editor provides an easy way to manage your signals and allows you to rename signals or group them into buses All data collected from in system source and probe nodes is recorded in the event l
21. the pin assignment in Quartus II version 13 0 is the setting for Block Design Naming After compilation of your schematic and VHDL codes with the schematic as the top level design entity you should find the names of the input and output signals which you have used in the schematic at the top of the node name list in Pin Planner If you find that there are other signal names which are added into the node name list it 1s an indication that the setting for Block Design Naming is causing a problem for the compilation The synthesized circuit may not work properly The in system sources and probes may also be affected by this problem You can correct the setting for Block Design Naming as follows Click on Assignment gt Settings in the main toolbar the following window is shown gt Settings lab t3 Category General Files Libraries 4 Operating Settings and Conditions Voltage Temperature 4 Compilation Process Settings Early Timing Estimate Incremental Compilation Physical Synthesis Optimizations 4 EDA Tool Settings Design Entry 5ynthesis Simulation Formal Verification Board Level 4 Analysis amp Synthesis Settings VHDL Input Verilog HDL Input Default Parameters Fitter Settings TimeQuest Timing Analyzer Assembler Design Assistant SignalTap II Logic Analyzer Logic Analyzer Interface PowerPlay Power Analyzer Settings SSN Analyzer December 3 2013 Analysis amp Synthesis Settings Specif
22. y Info Running Quartus II Analysis amp Synthesis y Info Command quartus map read settings files on write settings files off lab1_t1 c labl t1 i Info Found 2 design units including 1 entities in source file seven_seg vhd Y Y y E Info Found 2 design units including 1 entities in source file counter27bit vhd Info Found 1 design units including 1 entities in source file labl tl bdf N Info Elaborating entity labl t1 for the top level hierarchy 4 m 8 System 19 A Processing 62 A Extralnfo A Info 56 A Warning 6 Critical Warning Error Suppressed 6 A Flag Message of 591 tl Location Locate ULI LZ Idle NUM uo s wp mmm Ji oe il nmsmmm nc 1 OGO CO ll oa a E e e A naa D onn v M D iae a m A pu fig Inkorgen gmail S gs Labi Quartus LY Quartus ge Lab7 VH ge Tutorial T Tutorial SV lt LANE DE 17 04 Double click the symbols to expand counter27b1t and bcd7seg to view details December 3 2013 36 Chapters 15 23 are not tutorial steps and may be used as a simple user manual 15 Checking the problem with pin assignment Note that this chapter is not a tutorial step When you are looking for the reasons why you circuit does not work you may need to read this chapter and check whether you have a problem with pin assignment One problem with
23. Revisions Revision Name TopdevelEntity Family Device MeetTiming Timing Model Set Current labi t2 labi t4 Cydone II EP2C20F484C7 labi ti lab1 t2 Cydone II EP2C20F484C7 Delete new revision gt gt Compare Apply December 3 2013 46 Create Revision Specify a name and description Far the new revision Tou can base the revision on an existing revision and specify the revision as the current revision Revision name Based on revision demo 1 1 Description Created on Tuesday February 26 2013 Based on demo 1 1 v Copy database Set as current revision Fill in a new revision name and click OK Specify the current revisian For the project create a new revision delete an existing revision or edit the description of a revision Hevisians Top level En Set Current demo 1 1 demo Z Cyclone Il EPZ2C20F48 x demo 2 1 demo Cyclone Il EFZC2UF 48 Compare Customize C escription for revision demo 2 1 Revision name demo 2 1 Created on Tuesday February 26 2013 Based on demo 1 1 OF Cancel Click OK Notice that in the above window if you want to delete the old revision you can click the revision name in the list and click the button Delete All the output files of the revision will be deleted December 3 2013 47 22 How to use In System Sources and Probes Editor The In System Sources
24. Tutorial for Altera DEI and Quartus II Qin Zhong Ye December 2013 This tutorial teaches you the basic steps to use Quartus II version 13 0 to program Altera s FPGA Cyclone II EP2C20 on the Development amp Education Board DEI One can also use it as a simplified user manual Some screen prints are taken from Quartus II version 9 and therefore may be slightly different from that of Quartus II version 13 0 Contents l Create a new SS 2 2 Copy VHDL files and the assignment file for DET occcnccnnnnnnnnnnnnnnnnnonnncnnnononononnnnnnnnnos 9 3 Create dew SEHE URC TIS cpa cease eter CIR UNDE PRATO NE UE REDEEM 9 4 Open an existing VHDL file and add it to a project occccccccnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnoss 13 o Create dus umbo for a VADE JS stilo eio be boiler feas 16 6 Importing symbols to the schematic file sse 18 Te IMPOR 21 8 Importing input and output symbols eese eere 23 9 Connectisymbols maschemati6 soe scocehen naue eMe UM QUAM UU NU Ee SUUS UU DEM RUE eR 26 10 Connect individual signals to a bus sse eene eee 27 11 Specify the un sed pins setting tantos cio 30 INE GLAD 33 I5 Proctamming PPGA CD o osooiepes eto ed trotttror Top tos e t bo Etos ri 34 I4 Viewimo implementation 1081 Corina Su aedi A 36 I5 Checking the problem with pin assignment italia di 37 16 How to update a symbol after making changes to signal names
25. USB driver for DE1 should have been installed If it is not installed follow the instructions in chapter 22 How to install USB driver December 3 2013 35 14 Viewing implementation logic Click Tools gt Netlist Viewers gt RTL Viewer E Quartus II C work Teaching TNE094 Lab_test Lab1 lab1 t1 lab1 t1 RTL Viewer File Edit View Project Assignments Processing Tools Window Help amp x u t cim D ugl amp sejo cmn X z496 o v eo te e S ls lab1_t1 bdf gt Counter27bit vhd ab Seven_seg vhd E Compilation Report Flow Summary amp RTL Viewer gt Hierarchy i Hierarchy List Page Title lab1_t1 Page 1of1 i B labi ti ig B gor lab1_t1bdf a EJ Instances Pins ey Nets d if B de bcd7seg inst1 gt g Counter27bitinst di Hierarchy Files d Design Units x CLOCK 50 El b Compile Design G P Analysis amp Synthesis i Hp Partition Merge i Hi Design Assistant P 1 0 Assignment i UJ Early Timing Esti Fiter Place amp Route i ie Assembler Generate BP Classic Timing Analys _ lt catla d Hierarchy List Find 7 x y Info Fe Se Se Se Ve Se Fe Fe Se Se Se Se Se Ve Se Se Se Se Se Se Se Se Ve Se Se Se Se Se Se Se Se Se Se Se Se Se Se Ve Se Se Ve V Ve Se V Ve d V V de K V H AA K H K H H RRS
26. and Probes Editor in the Quartus II software allows you to easily control any internal signal and provides you with a completely dynamic debugging environment You can get more information on the In System Sources and Probes Editor from the Quartus II Handbook Chapter 16 Volume 3 Verification Section IV System Debugging Tools The In System Sources and Probes Editor consists of the ALTSOURCE PROBE megafunction and an interface to control the ALTSOURCE PROBE megafunction instances during run time Each ALTSOURCE PROBE megafunction instance provides you with source output ports and probe input ports where source ports drive selected signals and probe ports sample selected signals When you compile your design the ALTSOURCE PROBE megafunction sets up a register chain to either drive or sample the selected nodes in your logic design During run time the In System Sources and Probes Editor uses a JTAG connection to shift data to and from the ALTSOURCE PROBE megafunction instances Configuring the ALTSOURCE PROBE Megafunction To use the In System Sources and Probes Editor in your design you must first instantiate the ALTSOURCE PROBE megafunction variation file You can configure the ALTSOURCE PROBE megafunction with the MegaWizard Plug In Manager Each source or probe port can be up to 256 bits You can have up to 128 instances of the ALTSOURCE PROBE megafunction in your design To configure the ALTSOURCE PROBE megafunction performing the f
27. cal Warning Error A Suppressed A Flag un ui D A 3 z 2 Message 4 Locat or Cuts the selection and puts it on the Clipboard 175 326 Mea lt Idle Start B2cientt W2clientt amp 2Miroso Quartus II f DE1 tutorials iu Tutorial co 3 Quartus II SN 310 10 39 Right click in the blank space of the Graphic Editor and click Update Symbol or Block Update Symbol or Block Update C Selected symbol s or Black s All occurences of selected symbol s or block s All symbols or blocks in the file Cancel Click OK 17 What to do after add remove input output signals in a VHDL file If you add remove input output signals in a VHDL file you should create the symbol again by clicking File gt Create Update gt Create Symbol Files for Current File and adding the new symbol to the schematic file December 3 2013 41 18 How to create a VHDL file for the schematic file Click File gt Create Update gt Create HDL Design File for Current File Create HDL Design File for Current File E File type w VHDL Add YHEL Statements f Verlog HDL File name E Arbetz teaching amp ltera Sche VHDL proje Cancel Click OK Notice that the created file is not added in the project since this file is not needed for compilation of your design The VHDL file is useful if you want to move your design to another design tool or softwar
28. cav tst adc Click ppna Import Assignments Specify the source and categories of assignments to import File name E rbetsAteachingr ltera Sche_WHDL_projects M Cat v Copy existing assignments into Counter_example qsf bak before impor Advanced OF Cancel Click OK December 3 2013 22 Click Assignments gt Pin Planner in the main toolbar Quartus Il E Arbets teaching Altera Sche VHDL projects Tutorial counter Counter example Counter Sele File Edit View Processing Tools Window soups Q MTJT T T amp IWZ 2 T VWAImI lt lt O Top Wiem Wire Band Named i Cyclone I EP2C20F484C7 m mm EJ Mode Name Direction lt lt new node gt gt joes go a00 0D 8000 9200 A ogo E TA br fae AU TAO O nca dn Xo HD CEN ts A 00 cu GAGS er E DOU TOC POFFO SG00950 400 E AT AGAO _ NedeNam Direction Location Bank REF Group ta For Help press F1 The content of the assignment file 1s shown in the lower part of the window If you want to connect the output signals of the 7 segment decoder to the input signals of a 7 segment display on DEI you should use the pre defined output signal names in the Node Name column of the assignment editor For example HEXO 0 HEXO 1 HEXO 6 are the 7 output signals of the right most 7
29. counter27bit vhd i Info Found 2 design units including l entities in source file seven seg vhd uy Info Found l design units including l entities in source file counter_example bdf 3 uu Fase Flaharatin i er A System 19 A Processing 11 Extra Info Info 7 A Warning Critical Warning Error 4 Suppressed A Flag E Message D of 22 Location For Help press F1 573 126 hbo Idle Start B2 Client WY 2 Client 2 Micro U Tutorial_ Y 2 Quart Mw DE1_tuto Z Adobe A E Quartus essages Assign a name to a bus Click the selection tool Arrow in the toolbar Select the bus connected to the input of the 7 segment decoder Right click on the bus and select Properties The following window will appear Bus Properties General Font Format M ame br3 0 Hide name in black design file December 3 2013 27 Fill in a bus name any name you like Click OK Assign a name to a node signal line Click the selection tool Arrow in the toolbar Select the node signal line connected to the output of the counter Right click on the line and select Properties The following window will appear Node Properties General Font Format M ame lb 3 Hide name in block design file Fill in a node signal line name which is connected to a single bit of the connected bus For the output signal clkbit26 the node line name is b 3 Click
30. e If you want to view 1t you can open this file by clicking File gt Open Leta Tutorial counter db incremental db Senast anvanda le Counter27bit dokument le counter example e fa Counter example le Seven seq Skrivbord Mina dokument Den har datam j iis Filnamn kounte seme a nabverksplatser remm counter example Filformat Device Design Files Ptdf hd whdl 3 vigs Add file to current project Open as Auto m Select the VHDL file counter example and click ppna The code is an example of the structural style VHDL code There are 2 components bcd7seg and counter27bit in the code December 3 2013 42 19 How to copy a project It is possible to copy an existing project and give the copied project a new project name The copied project can be further improved by adding new components and VHDL codes Click Project gt Project copy When the Copy Project window pops up change the Destination directory and the New project name and click OK Copy Project Destination directory C wok Teaching THEUSA L ab tesk Demo 2 Mew project name demo 2 Iw Open new project This option closes the current project Cancel If the Destination directory does not exist the following window pops up Click Yes Y Destination directory Ci work Teaching TME094 Lab test Demo 2 amp does not
31. elp D c dg e BRIO a Counter example x 4 Q qUOQ D P Ts s 05 Project Navigator x Counter_example bdf Md a a OEA A TAO a NN AS A A a A RR TA A EJ A dy Cyclone Il EP2C20F48 E pesa aaa dies a a oa xd seu S Gow aa ra Gs ida as ada us re en du Ec ers opere B i 3 Counter dm rs E sical ds D Gece eh O Be oh A A Oppna os Leta i EJ Tutorial counter er Be I A M es a d m db EE EE A pe Po Counter_example E ons TET an d rA Senast anvanda a a al lt n dokument A AN Skivbord QQ IN Mina dokument AP a ea Den har datorn E A A a D A Mi CC w Vased tolto Filnamn m gt Filformat Device Design Files tdf vhd vhdl v vlg v Avbryt EI Add file to current project Auto v N System A Processing Extra Info A Info A Warning Critical Warning Error A Suppressed A Flag un ui o Message Al For Help press F1 Start B2 Client V 2 Client O 2 Micro Y Tutorial_ E Quartus f DE tuto 8 Adobe A 3 Seagate Sv K 11 04 Select File gt Open Find the VHDL file and click Oppna Notice that you should have already copied all files in the directory S TN E 094 Digitalteknik och konstruktion VHDL and assignment files to your project directory December 3 2013 13 E Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutoria
32. example x ICE D Ws 5G gt iiias Moma a TES Counter_example bdf gt Counter27bit vhd 3 Files L abd En 1 ArHFilnamn CounterZz 7bit vhd Law Abd Seven_seg vhd 2 En 27 bitars r knare som kan r kna O till 134217727 E C d OF 3 Neddelning av frekvensen fr n oscillatorn med frekvensen 50 MHz ie e Lounter example bdf j 4 E library IEEE 6 use IEEE std logic 1164 all 7 use IEEE std logic arith all 8 use IEEE std logic unsigned all 9 10 S entity Counter27bit is 11 E port Clk in std logic 12 clkbit23 clkbit24 clkbit25 clkbit26 out std logic iz end Counter27bit 14 15 Barchitecture beteende of Counter27bit is 16 subtype statetype is integer range O to 134217727 17 signal state nextstate statetype 18 signal Count std logic vector 26 downto 0 19 20 Bbegin 21 E process state LL begin PS case state is 24 when O to 134217726 gt nextstate lt state 1 E 25 when 134217727 gt nextstate lt 0 v gt System A Processing Extra Info A Info A Warning Critical Warning Error A Suppressed A Flag A Message F Locatic For Help press F1 Ln 1 Col 1 hae Idle ik Start B2 dient V 2 Client O 2 Micro Gy Tutorial Y Quartus Tutorial_ Z Adobe A E Seagate sv 11 50 Select Processing gt Analyze Current File Quartus Il 1 Flow Analyze Current File E 4rbets teachingAlteral5che_YHDL_ projects Tutorial cou
33. f 5 Select the design files you want to include in the project Click Add All to add all design files in the project directory to the project Note vau can always add design Files to the project later File name Add Filename Type Library Desionentw sy Add all Remove Properties Up s a Specify the path names of any non default libraries User Libraries lt Back Finish Avbryt If there is no design file e g schematic or VHDL files to add click Next December 3 2013 5 New Project Wizard Family amp Device Settings page 3 of 5 Select the Family and device you want ta target for compilation Device Family Show in valable device list Cyclone Il Package Any Pin count Ary Target device Speed grade Any Auto device selected by the Fitter i Show advanced devices Specific device selected in Available devices list E Avallable devices Embed PLL EP2C204F4844 7 239616 EP2L20AF 48418 233616 EP2C20F 2566 239616 EPZC20F256C 7 233616 EP2C20F256C8 239616 EP2L2UF 25616 239616 EP2C20F484CE 239616 EP2L2U0F 484L 7 233616 COC Ine Agro 7702176 2 4 4 4 4 4 4 4 4 A 32 JURE RRS LIII lt Back Finish Avbryt If the selected device is EP2C20F484C7 click Next December 3 2013 6 New Project Wizard EDA Tool Settings page 4 of 5 Specify the other EDA tools in addition to the Quartus software used with
34. hen the symbol is at the correct position left click to place the symbol If the repeat insert mode is chosen you can place several symbols You can stop the repeated symbol placement by clicking Esc key on the keyboard Double click on the symbol in the schematic the following window 1s shown Pin Properties General Format To create multiple pins enter a name in AHOL bus notation for example name 3 0 ar enter a comma separated list of names Pin names IHEXD D E You should use these pre defined names e g HEXO 0 CLOCK 50 etc as the pin names for input and output symbols Since the output of the 7 segment decoder is a bus The output symbol should also be a bus Use the notation HEXO 0 6 as the pin name Click OK December 3 2013 25 9 Connect symbols in a schematic Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example Counter_example bdf Ea lx el File Edit View Project Assignments Processing Tools Window Help S x Do dg 3 RR V Counter_example bea LLE Tir M s SE gt D Project Navigator F Counter_example bdf 3 Files O JEI E Compilation Report Counter27bit vhd Seven seg vhd E S NN L aba Seven seq yhd 0 0 o o a e lt lt o G B e 9 o 9 9 A o o e 9 9 e 3 5 e o t o
35. ion clock source Description Directs the device to restart the configuration process automatically if a data error is encountered Tf this option is turned off you must externally direct the device to restart the configuration process if an error occurs Select Unused Pins in Category December 3 2013 31 General Unused Pins Configuration Programming Files Unused Pins Dual Purpose Pins Capacitive Loading Specify device wide options for reserving all unused pins on the device To reserve individual dual purpose confiquration pins qo to the Dual Purpose Pins tab To reserve other pins individually use the Assignment Editor Reserve all unused pins Board Trace Model oa As input tri stated VO Timing As input tri stated with bus hold circuitry Voltage As input tri stated with weak pull up Pin Placement As output driving an unspecified signal Error Detection CRC As output driving qround CvP Settings Partial Reconfiguration Reserves all unused pins on the target device in one of 5 states as inputs that are tri stated as outputs that drive ground as outputs that drive an unspecified signal as input tri stated with bus hold or as input tri stated with weak pull up In the pull down menu select As input tri stated Click OK Click OK in the Device window December 3 2013 32 12 Compilation Click Processing gt Start Compilation If the compilation is successfu
36. l the following window is displayed Quartus Il P 4 1 Full Compilation was successFul 435 warnings Ok The large number of warnings is due to the unused node names in the assignment file Click Assignments gt Pins in the main menu Observe that the used pins are moved to the pat of the list as shown in the following window Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter AE File Edit View Processing Tools Window Tap vw Wire Bowe Cycle Il EPSZZOF 45477 NodeNam Direction gt El HEX0 0 6 Group lt lt new node I ro o ee L Tw aecxs in N T M 2 e mw ow pNEZ 2 AT 3 e mex 0 jux pr 4 ep nep output pum 2d 5 nex owtpue pna 5 g2 3 0 JggN 6 e Ex output 2B 7 e news ope Pm a P rs 9 X X For Help press F1 December 3 2013 33 13 Programming FPGA Chip Check whether the AC DC adapter and the USB cable are connected Turn on the power of DEI by pushing the red button on DEI Click Tools gt Programmer in the main toolbar L Quartus Il E Arbets teaching Altera sche VHDL projects Tutorial counter Counter example Counter Sle File Edit Processing Tools Window EA Hardware Setup LIS B Blaster 056 0 Mode ITAG Progress Enable real time ISP to
37. l settings You can change the settings for an existing project and specify additional project wide settings with the Settings command Assignments menu You can use the varous pages of the Settings dialog box to add functionality to the project Don t show me this introduction again lt Back Finish Avbryt Click Next December 3 2013 2 New Project Wizard Directory Name Top Level Entity page 1 of 5 E What is the working directory for this project C taltera 91 spe quartus bin E What is the name of this project What is the name of the top level design entity for this project This name ls cage sensitive and must exactly match the entity name in the design file Use Existing Project Settings lt Back Finish Avbryt Change the working directory name to your own working directory name A working directory in the local drive e g D of the PC is preferred December 3 2013 3 New Project Wizard Directory Name Top Level Entity page 1 of 5 What is the working directory for this project D ATMBETS lab u What i the name of this project Counter example ux What i the name of the top level design entity Far this project This name is case sensitive and must exactly match the entity name in the design File Counter example an Use Existing Project Settings Click Ja December 3 2013 4 New Project Wizard Add Files page 2 o
38. l_counter Counter_example Counter example Counter example bdf l ef ts File Edit View Project Assignments Processing Tools Window Help E E DEU a DR S o Icounereame Kre DATA DO AO Project Navigator gt gt x x ta Counter_example bdf b amire NO lt 2 oon i gt Counter_ E r 1 a a OY v v 0 e T CCLo AG e v 0 v v v 0 e v 0 v v e 0 0 v v v v e v 0 e e a 2 System A Processing Extra Info A Info A Warning Critical Warning Error A Suppressed A Flag wi d o Message F Location For Help press F1 Start B2 dient V 2 Client O 2 Micro Gy Tutorial E Quartus Tutorial ZS Adobe A Libraries Select the design files you want to include in the project Click Add All to add all design files in the o Device project directory ta the project H Operating Settings and Conditions i Compilation Process Settings j DOO R m H EDA Tool Settings ela za Analysis amp Synthesis Settings Filename sd Type Library Design enw AddAl Fitter Settings Counter example bal Block Diagra z Mone H Timing Analysis Settings Remove i gt Assembler Design Assistant Up SignalT ap Il Logic Analyzer Logic Analyzer Interface Down Simulator Settings gt Simulation Verification Simulation Output Files PowerPlay Power Analyzer Settings SSM Analyzer
39. mbol from the pull down menu December 3 2013 39 Change the names of the signals Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example Counter 27bit bsf File Edit View Project Assignments Processing Tools Window Help Eu M x O c 8 h Bao c Counter example x jq uo D M OM ra ds e amp A RR Counter27bit vhd ff Counter_example bdf Counter27bit bsf Cyclone Il EP2C20F 484C7 E 2 Counter_example q ebd Counter27bitinst i cbc bed seg instl sx Muri ME cosa R EE os RC R E REC EE ED E REC A Sew FS ews OE O48 OF 8 eo Ee WhO aes 84 wee HS we Owe a8 9 p die o 4 v o s on o d 4 e o o 4 e e o v s o 5 v 5 5 e v 5 5 d 5 5 s o Z Z Z Clk clkbit23 X2 e 4 clkbit24 clkbit25 clkbit26 KZ A A A EROS e Z AAA iZ He H inst i 5 c nc oe 00 00 6 ee AAA AAA AA AAA AAA AAA A A AAA NNSNNNNNNNNNNNNNBENNNNNNNNNNNNNNNN ceogseoges0g000ge00g000g000g000g000g000g000g00 4 a s eesti O RN RR we NLS NR RO oye e Se a Type EA b System Processing A Extralnfo Info warning A Critical Warning A Error Suppressed Flag Message Al Location essages Locate For Help press F1 583 16 Mela
40. n the Libraries page of the Settings dialog box Assignments menu Your current user library directories are 4 On page 2a of the MegaWizard Plug In Manager make the following selections a In the Installed Plug Ins list expand the JTAG accessible Extensions folder and select In System Sources and Probes You can also verify that the currently selected device family matches the device you are targeting b Select an output file type and enter the name for example source probel of the ALTSOURCE PROBE megafunction You can choose AHDL tdf VHDL vhd or Verilog HDL v as the output file type 5 Click Next December 3 2013 49 a A AA AAA a MegaWizard Plug In Manager page 3 of 5 Parameter Settings Currently selected device family cyclone II ves Match project de fault EE obe 0 E Do you want to specify an Instance Index No assign it automatically Yes use this number 0 The Instance ID of this instance optional NONE 4 characters How wide should the probe port be bits How wide should the source port be bits Advanced Options 6 On page 3 of the MegaWizard Plug In Manager make the following selections a Under Do you want to specify an Instance Index turn on Yes This index determines the position of the instance in the list of instances of the In System Sources and probes Editor b Specify the Instance ID of this instance
41. nter Counter2 bit hd was 7 successful Click OK Click File gt Create Update gt Create Symbol Files for Current File Quartus LA Create Symbol File was successful Click OK Perform the same operations 1 e open file analyze file create symbol files as above for the VHDL file Seven seg vhd December 3 2013 17 6 Importing symbols to the schematic file Click Counter example bdf to view the schematic file Double click on the blank space of the Graphic Editor window or click on the AND gate icon in the toolbar Pa File Edit View Project Assignments Processing Tools Window Help D u amp X Ea A x gt cx ae Counter example x 4j QUOQ Dr M rs as L4 Eb Project Navigator gt x Counter example bd 3 Files Gag Counter27bit vhd VHO PHD Seven_seg vhd i P Counter example bdf abe Counter27bit vhd abe Seven seg vhd Libraries ae Project c altera S1sp2 quartus libraries Name v Repeatinsert mode Insert symbol as bloc Ej Launch Megawizard Plug lt MegaWizard Plug In Manager i Info ttxxtxx4 Cancel y Info Running Qua L Info Command quartus map read settings files on write settings files off Counter example c Counter example generate_symbol y Info Quartus II Create Symbol File was successful O errors 0 warnings J lt M System 15 A
42. o sv K 13 42 The symbol for Counter27bit will appear in the Graphic Editor window Move the symbol to a proper location and click the left mouse button If the symbol continues to follow the mouse movement click on the Esc button on your keyboard or click the right button of the mouse and select Cancel Perform the same operations as above for the symbol bcd7seg Notice that the symbol name bcd7seg is the same as the entity name in the VHDL file seven seg vhd December 3 2013 20 Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example Counter_example bdf el File Edit View Project Assignments Processing Tools Window Help 8 X j G dg e BAIN a Counter example x jd UQq D P K his k O 2 h Project Nawigator _ 1 Counter example bdf Eb Compilation Report Counter27bit vhd b Seven seg vhd amp Files Pas Counter2 bit vhd E i 22 Counter example bdf po uu Clk clkbit23 e 9 v v v o 0 c3 i e 9 9 9 9 v v o v 9 9 clkbit24 TE bed 3 0 display D 5 Beet clkbit25 TEE Bell rn nnn nn aem a NSIN SIG he s 0 0 0 v 0 v o o 0 0 s Message Info WWW NN NN UU UN NUN NU UN n n e NN NN NN NN SE Info Command quartus map read settings files on write settings files off Counter example c Counter example generate_symbol 1
43. ock Balancing Disable Register Merging Across Hierarchies Extract VHDL State Machines Extract Verilog State Machines Force Use of Synchronous Clear Signals HDL message level Specify the naming scheme used for the block design This option is ignored if it is assigned to anything other than a design entity Double click on Auto of the setting Block Design Naming The pull down menu will show 3 alternatives Select Quartus II and click OK to close the window Compile your project again and check whether the synthesized circuit works Note that the added names in the node name list might still be there in Pin Planner But they are not causing the problem If you notice any problems or errors with this part of text please let me know December 3 2013 38 16 How to update a symbol after making changes to signal names If you change the names of any input output signals in a VHDL file you should do the following steps Click Processing gt Analyze Current File to check the modified VHDL code View the schematic in Graphic Editor Right click on the symbol Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example Counter_example b df Ea lx fel File Edit View Project Assignments Processing Tools Window Help D bi a c d Ba e cs Counter example Ix 2 dU OQ D rro Project Navigator Bm x CX abe Counter2 bit vhd
44. og and you can view the data as a timing diagram Reading Probe Data You can read data by selecting the ALTSOURCE PROBE instance in the Instance Manager pane and clicking Read Probe Data This action produces a single sample of the probe data and updates the data column of the selected index in the In System Sources and Probes Editor pane Y ou can save the data to an event log by turning on the Save data to event log option in the Instance Manager pane If you want to sample data from your probe instance continuously in the Instance Manager pane click the instance you want to read and then click Continuously read probe data While reading the status of the active instance shows Unloading You can read continuously from multiple instances You can access read data with the shortcut menus in the Instance Manager pane To adjust the probe read interval in the Instance Manager pane turn on the Manual option in the Probe read interval sub pane and specify the sample rate in the text field next to the Manual option The maximum sample rate depends on your computer setup The actual sample rate 1s shown in the Current interval box You can adjust the event log window buffer size in the Maximum Size box Writing Data To modify the source data you want to write into the ALTSOURCE PROBE instance click the name field of the signal you want to change For buses of signals you can double click the data field and type the value you want to drive out
45. ollowing steps 1 On the Tools menu click MegaWizard Plug In Manager 4 MegaWizard Plug In Manager page 1 The MegaWizard Plug In Manager helps you create or modify design files that contain custom variations of megafunctions N Which action do you want to perform amp Create a new custom megafunction variation y Edit an existing custom megafunction variation Copy an existing custom megafunction variation Copyright C 1991 2013 Altera Corporation Cancel lt Back Next gt Finish 2 Select Create a new custom megafunction variation December 3 2013 48 3 Click Next 4 MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Select a megafunction from the list below a 4 2 Installed Plug Ins Lj Arithmetic gt Li Communications gt Lg DSP gt Lj Gates gt B I O gt Interfaces gt LJ JTAG accessible Extensions gt Lj Memory Compiler gt E PLL LJ Click to Open IP MegaStore x pr Which device family wil you be using Which type of output file do you want to create vi Verilog HDL What name do you want for the output file C Teaching TNEO94 Lab_test Lab1_2 Return to this page for another create operation Note To compile a project successfully in the Quartus IT software your design files must be in the project directory in a library specified in the Libraries page of the Options dialog box Tools menu or a library specified i
46. ounter27bit Click Orthogonal Bus Tool for a bus in the toolbar Use the tool to connect the output of the decoder to the output symbol December 3 2013 26 10 Connect individual signals to a bus Connect the counter and the 7 segment decoder as shown in the following window Quartus Il E Arbets teaching Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter _example Counter_example bdf l efx ts File Edit View Project Assignments Processing Tools Window Help L x Oda amp R v Ca Counter_example x S SVS D rr lt O amp 2 prest IDIMSENO SEIEN T Counter example bdf E Compilation Report Flow Summary Counter27bit vhd Seven_seg vhd s Counter27bit Eg Mo A A dvs ooh A A i A wae ee es Ga ie cer ee R A Seu c P UNS Seven seg vt A EP I 2 e By Counter exar l 109259 O QUERN aa COUMEDI gt gt oec rr ns AEREA bh ae wad bak be bat eo Read ha ees E E eas S De EM Pbcd seg np he ae aa sa HIH m clkbit24 EU bcd 3 0 display 0 6 s NOTES gt HE CI Mil Dl i instl e S gt y Info FERRARI ERRE R ERRE RRA NN NN NNNN gt H a Info Running Quartus II Analysis Synthesis i Info Command quartus map read settings files on write settings files off Counter example c Counter example LJ H i Info Found 2 design units including l entities in source file
47. r J Auto device selected by the Fitter E y n devi H rdCopy compatible onl 9 Specific device selected in Available devices list Show advanced devices HardCopy compatible only F Other n a Available devices Name Core Voltage r I Embedded multiplier 9 bit EP2C20F256C8 1 2V 18752 22 239616 EP2C20F2561B8 1 2V 18752 22 230616 EP2C20F484C6 1 2V 18752 315 230616 EP2C20F484C7 1 2V 18 52 315 239616 EP2C20F484C8 1 3W 18752 315 230616 4 I Migration compatibility Companion device Ey Migration Devices HardCopy 0 migration devices selected Iv Limit DSP amp RAM to HardCopy device resources Click Device and Pin Option icon December 3 2013 30 Genera Genera I Configuration Programming Files rs a e ct Unused Pins Dual Purpose Pins Capacitive Loading Auto restart configuration after error Board Trace Model Release clears before tri states JO Timing _ Enable user supplied start up clock CLKUSR ier ad j Enable device wide reset DEV_CLRn in Placemen ieee ee ee Error Detection CRC E Enable device wide output enable DEV OE CvP Settings Enable INIT DONE output Partial Reconfiguration Options Auto usercode JTAG user code 32 bit hexadecimal FFFFFFFF In system programming clamp state Delay entry to user mode Device initializat
48. s the selected files in the following directory C Weaching TNEO094 Lab_test Lab1 2V File source probel vhd E source_probe Linc 7 source probe1 cmp source probei bsf source probe1 inst Descripti Variation file AHDL Include file VHDL component declaration file Quartus II symbol file Instantiation template file 10 Select tick soure probel bsf to create a Quartus II symbol file The symbol can be imported to the schematic of your design Sinec the file source probel vhd is always created you can also create the symbol for the VHDL file See Chapter 5 Create a symbol for a VHDL file of this document 11 Click Finish December 3 2013 51 5 Quartus IIP Files When you create an Altera IP variation a Quartus II IP File is generated Quartus II IP Files are used to represent the Altera IP in your design Do you want to add the Quartus II IP File to the project Automatically add Quartus II IP Files to all projects Note Turning on this option permanently suppresses this dialog box You can change this setting in the Options dialog box LN j Hep 12 Click Yes Import the created symbol to the schematic of your project Follow the instructions 1n Chapter 6 Importing symbols to the schematic file of this document Compile the project Click Processing gt Start Compilation See Chapter 12 Compilation of this document Program FPGA Chip Click Tools gt Programmer
49. samples The time stamp for each sample is logged and is displayed above the event log of the active instance as you move your pointer over the data samples You can save the changes that you make and the recorded data to a Sources and Probes File spf To save changes on the File menu click Save The file contains all the modifications you made to the signal groups as well as the current data event log 23 How to install USB driver USB blaster is the USB device on Altera s FPGA board DE1 When DE l is connected to a PC through a USB cable the USB driver for USB Blaster should be installed The USB driver can be found in the folder altera 9 1sp2 quartus drivers usb blaster 1f Quartus II version 9 1 is installed on the PC When DEI is connected to a PC with Windows XP a pop up window Found New Hardware Wizard will be shown to guide the installation of the driver See the details 1n the manual Getting started with Altera DEI pdf When DE is connected to a PC with Windows Vista a pop up window will be shown to guide the installation of the driver Similar steps as for Windows XP should be done When DE is connected to a PC with Windows 7 no pop up window will be shown One should follow the following steps in Manual for installation of Quartus II and USB driver for Windows 7 in Manual install Quartus USBdriver Windows 7 pdf to install the USB driver December 3 2013 54
50. schematic is not in the list you should change the top level entity by typing the new entity name If you only want to compile a VHDL code you can select the entity name of the entity in the VHDL code If you want to compile the whole design you should select the entity name for the schematic December 3 2013 44 21 How to change revision name A revision name is used to set the output file names after compilation Quartus I C work Teaching TNE094 Lab_test Demo_2 demo_2 demo 1 1 Compilation Report Flow Summary El E File Edit View Project Assignments Processing Tools Windo Help 5 x Ds Ed S x R o gt demo 11 Jar gge o rv wore se a b Compilation Report Flow Summary Counter27bit vhd demo_2 bdt Files EH Compilation Report amp B Legal Notice SES Flow Summary i bo Seven_seg vhd i Bbd Counter27bit vhd i VHD M m HE SES Flow Settings ES Flow Non Defau 883 Flow Elapsed Tin EE Flow OS Summa amp B Flow Log 4 81 Analysis amp Syntk 81 Fitter 181 Assembler Flow Status Successful Mon Feb 25 16 54 11 2013 1890 Timing Analyzer Quartus ll Version 9 1 Build 350 03 24 2010 SP 2 SJ Web Edition Revision Name demo 1 1 TopJevel Entity Name demo 2 Family Cyclone II Device EP2C20F484C7 Timing Models Final A Hierarchy E Files d Design Units Met timing rgwffirements Yes _ Total ggf elements 43
51. the project Design Entry Synthesis Tool name MI Format Run this tool automatically to synthesize the current design Simulation Tool name lt MNone gt Format E Hun gate evel simulation automatically after compilation Timing Analysis Tool name lt MNone gt a Format E Aun this tool automatically after compilation lt Back Finish Avbryt Click Next December 3 2013 7 New Project Wizard Summary page 5 of 5 When wou click Finish the project will be created with the following settings Project directory E Arbets teaching Altera 5 che VHDL prajecte T utonal counter Project name Counter example Top level design entity Counter example Number of files added Mumber of user libraries added 0 Device assignments Family name Cyclone Il Device EFZ2C20F484C7 EDA tools Design entrysunthesis zMone Simulation lt None gt Timing analysis lt MNone gt Operating conditions Core woltage 1 Junction temperature range 0 865 C TM Click Finish December 3 2013 8 2 Copy VHDL files and the assignment file for DE1 Use Windows Explorer to copy all files in the directory S TN E 094 Digitalteknik och konstruktion VHDL and assignment files to your project directory 3 Create a new schematic file F Quartus Il E Arbets teac hing Altera Sche_VHDL_projects Tutorial_counter Counter_example Counter_example File Edit
52. to the ALTSOURCE PROBE instance The In System Sources and Probes Editor stores the modified source data values in a temporary buffer Modified values that are not written out to the ALTSOURCE PROBE instances appear in red To update the ALTSOURCE PROBE instance highlight the instance in the Instance Manager pane and click Write source data The Write source data function is also available via the shortcut menus in the Instance Manager pane The In System Sources and Probes Editor provides the option to continuously update each ALTSOURCE PROBE instance Continuous updating allows any modifications you make to the source data buffer to also write immediately to the ALTSOURCE PROBE instances To continuously update the ALTSOURCE PROBE instances change the Write source data field from Manually to Continuously December 3 2013 53 Organizing Data The In System Sources and Probes Editor pane allows you to group signals into buses and also allows you to modify the display options of the data buffer To create a group of signals select the node names you want to group right click and select Group You can modify the display format in the Bus Display Format and the Bus Bit order shortcut menus The In System Sources and Probes Editor pane allows you to rename any signal To rename a signal double click the name of the signal and type the new name The event log contains a record of the most recent samples The buffer size is adjustable up to 128k
53. y options for analysis amp synthesis These options control Quartus II Integrated Synthesis and do not affect VOM or EDIF netlists unless WYSIWYG primitive resynthesis is enabled Optimization Technique O Speed Balanced 3 Area E Timing Driven Synthesis Power Up Don t Care C Perform WYSIWYG primitive resynthesis PowerPlay power optimization N More Settings Description Specifies the overall optimization goal for Analysis amp Synthesis attempt to maximize performance minimize logic usage or balance high performance with minimal logic usage 37 Click on Analysis amp Synthesis Settings and the click on More settings button The following window 1s shown More Analysis amp Synthesis Settings Specify the settings for the logic options in your project Assi override the option settings in this dialog box Mame Allow Any RAM Size For Recognition Allow Any ROM Size For Recognition Allow Any Shift Register Size For Recognition Allow Shift Register Merging across Hierarchies Allow Synchronous Control Signals Analysis 4 Synthesis Message Level Auto Carry Chains Auto Clock Enable Replacement Auto Gated Clock Conversion Auto Open Drain Pins Auto RAM Replacement Auto RAM to Logic Cell Conversion Auto ROM Replacement Auto Resource Sharing Auto Shift Register Replacement Block Design Naming Carry Chain Length Clock MUX Protection Create Debugging Modes for IP Cores DSP Bl

1. Create a new project

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