Correction for Incorrect Description Notice RL78/G10 Descriptions in
Contents
1. Old New 10 9 3 Conflicting operations 10 9 3 Conflicting operations Writing to the ADMO register has priority if conflict between writing to the ADCRH or lt 1 gt Reading from the ADCRH or ADCRL register has priority if conflict between writing ADCRL register and writing 0 to the A D converter mode register 0 ADMO occurs at the end to the A D conversion result register ADCRH ADCRL and reading from ADCRH or of conversion Writing to the ADCRH or ADCRL register is not performed nor is the ADCRL register by software operation occurs at the end of conversion After the conversion end interrupt signal INTAD generated read operation the new conversion result is written to the ADCRH or ADCRH register lt 2 gt Writing to the ADMO register has priority if conflict between writing to the ADCRH or ADCRL register and writing to the A D converter mode register 0 ADMO occurs at the end of conversion Writing to the ADCRH or ADCRL register is not performed nor is the A D conversion end interrupt signal INTAD generated c 2014 Renesas Electronics Corporation All rights reserved Page 9 of 13 sCENESAS RENESAS TECHNICAL UPDATE TN RL A023A E 8 24 3 1 Pin characteristics Page 556 This shows the specifications changed in the ELECTRICAL SPECIFICATIONS of 10 pin products The ELECTRICAL SPECIFICATIONS of Flash ROM 4 KB of 10 pin products and 16 pin products will be made for the next revision of the User s Manual Hardware Old2. 24 3 1 Pin characteristics Ta 40 to 85 C 2 0 V lt Voo lt 5 5 V Vss 0 V i a E current P02 to P04 P40 noez MA high Note 3 rah aovevezesv 00 ma a7vevw lt aov zo ma povevwe 27v as ma roar aovevecesv s00 ma a7vevo 4ov ana ma a at bom POO P01 P02 to P04 Total of all pins low Output ES 0 current POO to P04 P40 Per pin AP Note 4 20 0 0 Total 4 0V lt Vo0 lt 5 5V 4 A 0V lt Vo0 lt 5 5V V lt Vp0 lt 5 5 V 2 7 V lt Voo lt 4 0 V mean 1 aes roa 4oveviosssv eoo ma arvsve lt sov 20 ma poveva 24 ma rationed oo mk omitted POO to P04 c 2014 Renesas Electronics Corporation All rights reserved tENESAS Date Feb 6 2014 New 24 3 1 Pin characteristics Ta 40 to 85 C 2 0 V lt Von lt 5 5 V Vss 0 V ley Note 2 current 10 pin products POO to P04 P40 high 16 pin products POO to P07 P40 P41 Total of 10 pin products P40 16 pin products P40 P41 When duty lt 70 3 Total of o in products P00 t0 P04 37 y lt voo lt 4o V m 16 pin products POO to P0O7 oia 2 0 V lt Voo lt 2 7 V When duty lt 70 Total of all pins When duty lt 70 3 80 0 80 0 Output Per pin for 20 0 current 10 pin products POO to P04 P40 Note 2 low Note 4 16 pin products POO to P07 P40 P41 Total of soveversssv
3. 400 ma tO pinproducts P40 La 7 Vs Von lt 4 0V Mt mr 16 pin products P40 P41 When duty lt 70 Total of 10 pin products POO to P04 16 pin products POO to P07 When duty lt 70 Total of all pins When duty lt 70 omitted Page 10 of 13 RENESAS TECHNICAL UPDATE TN RL A023A E 9 24 6 1 A D converter characteristics Page 567 This shows the specifications changed in the ELECTRICAL SPECIFICATIONS of 10 pin products The ELECTRICAL SPECIFICATIONS of Flash ROM 4 KB of 10 pin products and 16 pin products will be made for the next revision of the User s Manual Hardware Old 24 6 1 A D converter characteristics Target ANI pin ANIO to ANI3 Ta 40 to 85 C 2 4 V lt Voo lt 5 5 V Vss 0 V ce a e eh ae a aeumuevisal ok 1 eson ossy oan rs extn Nesey fon nrs Integral linearity 10 bit Vo 5v f Jo 8882 LSB emeen heroy P Par e linearity error resolution 3y Ta 44 5hlate2 Analog input VAIN V voltage Notes 1 2 _Thi s is the characteristic evaluation value plus or minus 3 hese values are not used in the shipping inspection Excludes quantization error 1 2 LSB c 2014 Renesas Electronics Corporation All rights reserved CENESAS Date Feb 6 2014 New 24 6 1 A D converter characteristics Target pin ANIO to ANIG6 internal reference voltage Ta 40 to 85 C 2 4 V lt Von lt 5 5 V Vss
4. stEN ESAS RENESAS TECHNICAL UPDATE TN RL A023A E Date Feb 6 2014 Corrections in the User s Manual Hardware 1 1 Address Space Pages 22 to 24 Pages 4 to 6 3 5 Timer channel enable status register 0 TEO TEHO 8 bit mode Page 121 Page No Corrections and Applicable Items Pages in this document English RO1UH0384EJ0100 for corrections 6 3 8 Timer output enable register 0 TOEO Page 124 6 4 2 Basic rules of 8 bit timer operation EF function only channels 1 and 3 Pao ee Figure 10 13 Conversion Operation of A D Page 235 Page 8 Converter KA 7 10 9 3 Conflicting operations Page 242 8 24 3 1 Pin characteristics Page 556 Page 10 9 24 6 1 A D converter characteristics Page 567 Pages 11 and 12 10 24 6 4 Data retention power supply voltage Page 568 Page 13 characteristics Bol Incorr with underline Correct Gray hatched Revision History RL78 G10 User s Manual Hardware Rev 1 00 Correction for Incorrect Description Notice Document Number TN RL A023A E Feb 6 2014 First edition issued No 1 to 10 in corrections This notice c 2014 Renesas Electronics Corporation All rights reserved Page 2 of 13 sCENESAS RENESAS TECHNICAL UPDATE TN RL A023A E Date Feb 6 2014 1 Flash ROM 4 KB of 10 pin products and 16 pin products Page 7 Flash ROM 4 KB of 10 pin products and 16 pin products will be added to line up in the group of RL78 G10 The details of functions of 16 pin pr
5. ID setting area EFFFFH CAH 10 bytes EFFFFH mal H l Neat Option byte area Mote 4 bytes CALLT table area 64 bytes OOFFFH OOFFFH Code flash memory Code flash memory AKB 4KB 00000H 00000H Note Set the option bytes to 000COH to 000C3H and the on chip debug security IDs to OOOC4H to OOOCDH Note Set the option bytes to QO0COH to 000C3H and the on chip debug secunity IDs to OO0C4H to OOOCDH Caution Access to the reserved area is prohibited Caution Access to the reserved area is prohibited Page 6 of 13 c 2014 Renesas Electronics Corporation All rights reserved CENESAS RENESAS TECHNICAL UPDATE TN RL A023A E 3 6 3 5 Timer channel enable status register 0 TEO TEHO 8 bit mode Page 121 Incorrect The TEO and TEHO registers are used to enable or stop the timer operation of each channel Each bit of the TEO and TEHO registers correspond to each bit of the timer channel start register O TSO TSHO and the timer channel stop register O TTO TTHO When a bit of the TSO and TSHO registers is set to 1 the corresponding bit of TEO and TEHO is set to 1 When a bit of the TTO and TTHO registers is set to 1 the corresponding bit of TEO and TEHO is cleared to 0 instruction Reset signal generation clears TEO and TEHO registers to OOH 4 6 3 8 Timer output enable register 0 TOEO Page 124 Incorrect The TOEO register is used to enable or disable timer output of each channel Channel n for which timer o
6. RENESAS TECHNICAL UPDATE TN RL A023A E 6 Incorrect lt R gt 1 is written to ADCS y ADCS Conversion start time A D converter Conversion Conversion standby operation start SAR Undefined ADCRH 10 Conversion time gt a Sampling time Sampling Figure 10 13 Conversion Operation of A D Converter Page 235 A D conversion Conversion standby Conversion result Conversion result INTAD A D conversion i Reset signal generation clears the A D conversion result register ADCRL ADCRH to OOH c 2014 Renesas Electronics Corporation All rights reserved rform nce when the bit 7 AD fth D conve tENESAS r mod Date Feb 6 2014 Correct Figure 10 12 Conversion Operation of A D Converter 1 is written to ADCS ADCS A D converter Conversion operation standby SAR Undefined ADCRH ADCRL lt Conversion time aaa Sampling time Sampling A D conversion Conversion standby Conversion result Conversion result INTAD A D conversion is performed once when the bit 7 ADCS of the A D converter mode register 0 ADMO is set to 1 by software The ADCS bit is automatically cleared to 0 after A D conversion ends Reset signal generation clears the A D conversion result register ADCRH ADCRL to OOH Page 8 of 13 RENESAS TECHNICAL UPDATE TN RL A023A E Date Feb 6 2014 7 10 9 3 Conflicting operations Page 242
7. of the data retention power supply voltage range c 2014 Renesas Electronics Corporation All rights reserved tENESAS Date Feb 6 2014 New 24 6 6 Data retention power supply voltage characteristics a 40 to 85 C Vss 0 V Parameter Data retention power VDDDR 1 9 5 5 supply voltage Caution Data in the RESF register is retained until the power supply voltage becomes under the minimum value of the data retention power supply voltage Vpppr Note that data in the RESF register might not be cleared even if the power supply voltage becomes under the minimum value of the data retention power supply voltage Vpppr SPOR reset period Data retention mode Normal operation Normal operation e Rising of V sPoR Falling of VsPorR VDDDR Page 13 of 13
8. 0 V Tresowton res OO 8 to Overall error 10 bit Vop 5V fanz 331 isa Conversion time 10 bit 27v lt VvVo lt 55v 34 184 ps resolution 24V lt Vo0 lt 55V 4 6 18 4 us Target pin Note 5 ANIO to ANI6 10 bit 2 4 V lt Voo lt 5 5 V 4 6 18 4 us resolution Target pin internal reference voltage w o wre vws Toso wes vws oz wre v v soa wr Fwoesv fata tse or ee ww er rs Zero scale 10 bit error Nes 12 3 4 resolution Full scale error 10 bit Notes 1 2 3 4 resolution Integral linearity 10 bit error resolution Differential linearity 10 bit errors 1 2 3 resolution foray s Target pin ANIO to ANI6 rats tT r rm _ 1 Note 6 Notes are listed on the next page Page 11 of 13 Analog input voltage RENESAS TECHNICAL UPDATE TN RL A023A E c 2014 Renesas Electronics Corporation All rights reserved CENESAS Notes 1 Date Feb 6 2014 TYP Value is the average value at Ta 25 C MAX value is the average value 30 at normal distribution These values are the results of characteristic evaluation and are not checked for shipment Excludes quantization error 1 2 LSB This value is indicated as a ratio FSR to the full scale value Set the LVO bit in the A D converter mode register 0 ADMO to 0 when conversion is done in the operating voltage range of 2 4 V lt Voo lt 2 7 V Set the LVO bit in the A D conve
9. 87FFH F87FFH F8000H F8000H F7FFFH F7FFFH FOS00H FOS00H FO7FFH special function register 2nd SFR FO FFH Special function register 2nd SFR cD On chip debug ete FOOOOH 2KB FOO00H 2KB security ID setting area EFFFFH EFFFFH OCA C3 Option byte area Mot 4 bytes CALLT table area 007FFH 007FFH sige var ae l T I l d 28 m 7 Code flash memory 2KB 00000H D0000H Note Set the option bytes to QOOCOH to 000C3H and the on chip debug security IDs to 0004H to 000CDH Note Set the option bytes to QOOCOH to OO0C3H and the on chip debug secunty IDs to 000C4H to OOOCDH Caution Access to the reserved area is prohibited Caution Access to the reserved area is prohibited c 2014 Renesas Electronics Corporation All rights reserved Page 5 of 13 tEN ESAS Date Feb 6 2014 RENESAS TECHNICAL UPDATE TN RL A023A E Incorrect Correct Figure 3 3 Memory Map for the RSFI0Y47ASP FFFFFH OOFFFH FFFFFH OOFFFH Special function register SFR Special function register SFR FFFOOH SARE FFFOOH meat FFEFFH FFEFF FFEF8H FFEFSH FFEFTH FFEEOH FFEEOH FFEDFH FFEDFH RAM 512 bytes FFCEOH FFCEOH FFCDFH FFCDFH Program area F8800H F9000H F87FFH F8FFFH F8000H F8000H FTEFFH FFFFFH F0800H 7 FOB00H FO7FFH Special function register nd SFR CD FO FFH Special function register 2nd SFR On chip debug Net FOOQOQH 2KB security ID setting area l F0000H 2KB security
10. Date Feb 6 2014 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPumcu Document TN RL A023A E Rev 1 00 Category No Correction for Incorrect Description Notice infomation Title RL78 G10 Descriptions in the Hardware User s Manual Technical Notification Rev 1 00 Changed Category Lot No Applicable RL78 G10 Reference RL78 G10 User s Manual Hardware Product R5F10Yxxx D eo roquc All lots OcUMEN R01UH0384EJ0100 Jun 2013 This document describes misstatements found in the RL78 G10 User s Manual Hardware Rev 1 00 RO1UH0384EJ0100 Corrections Applicable Item Applicable Page Flash ROM 4 KB of 10 pin products and 16 pin Specifications added products k 3 1 Address Space Pages 22 to 24 Incorrect descriptions revised 6 3 5 Timer channel enable status register 0 BP I TEO TEHO 8 bit mode Page 121 Incorrect descriptions revised 6 3 8 Timer output enable register 0 TOEO Page 124 Incorrect descriptions revised 6 4 2 Basic rules of 8 bit timer operation function Page 132 Specifications added only channels 1 and 3 24 6 4 Data retention power supply voltage Page 568 Descriptions added characteristics g p Document Improvement The above corrections will be made for the next revision of the User s Manual Hardware c 2014 Renesas Electronics Corporation All rights reserved Page 1 of 13
11. FFEFTH FFEFTH ty FFEEOH FFEEOH FFEDFH FFEDFH FFE6OH FFESFH Program area F8400H F83FFH F8000H F7FFFH F0800H 000CEH Basie FO7FFH Special function register 2nd SFR D00CDH 7 FEN Special function register 2nd SFR ne E 2KB E j ity ID setting are FOO00H secunty ID setting area oooc4H ease ae ae EFFFFH CAH 10b aii a 000c3H Option byte area Option byte area 000COH 4 bytes 4 bytes OO00BFH en CALLT table area 64 bytes 00080H piian 0007FH 003FFH 00000H Note Set the option bytes to O00COH to 000C3H and the on chip debug security IDs to 000C4H to OOOCDH Note Set the option bytes to 000COH to 000C3H and the on chip debug security IDs to 000C4H to OOOCDH si a lal 7 es ee eee Caution Access to th rved area is prohibited Caution Access to the reserved area is prohibited ETE nape tees area eas ae eee c 2014 Renesas Electronics Corporation All rights reserved Page 4 of 13 lt CENESAS Date Feb 6 2014 RENESAS TECHNICAL UPDATE TN RL A023A E Incorrect Correct Figure 3 2 Memory Map for the RSF1I0Y16ASP and ASF10Y46ASP Figure 3 2 Memory Map for the RS5FI0Y16ASP and R5F10Y46A P FFFFFH OO7FFH FFFFFH OO7FFH Special function register SFR Special function register SFR FFFOOH aii FFFOOH oe FFEFFH P EAR FFEFFH FFEF8H Soe FFEFSH FFEFTH FFEFTH FFEEOH FFEEOH FFEDFH FFEDFH FFDEOH FFDEOH FFDDFH FFDDFH Program area F8s00H F8800H F
12. eset by selectable power on reset Internal reset by illegal instruction execution Internal reset by data retention lower limit voltage Note 2 Selectable power on reset circuit Detection voltage Rising edge Vspor 2 25 V 2 68 V 3 02 V 4 45 V max Falling edge Vspor 2 20 V 2 62 V 2 96 V 4 37 V max Power supply voltage Voo 2 0 to 5 5 V Notes Operating ambient temperature Ta 40 to 85 C Notes 1 The number of outputs varies depending on the setting of channels in use and the number of the master see 6 9 4 Operation as multiple PWM output function 2 The illegal instruction is generated when instruction code FFH is executed Reset by the illegal instruction execution not issued by emulation with the on chip debug emulator 3 Use this product within the voltage range from 2 25 to 5 5 V because the detection voltage Vspor of the selectable power on reset SPOR circuit should also be considered c 2014 Renesas Electronics Corporation All rights reserved Page 3 of 13 sCENESAS RENESAS TECHNICAL UPDATE TN RL A023A E Date Feb 6 2014 2 3 1 Address Space Pages 22 to 24 Correct Incorrect Fi 3 1 M Map for the RSFI0Y14ASP and R5F1I0Y44ASP Figure 3 1 Memory Map for the RSFIOY14 ASP and RSFi0Y44ASP ciii ee an l 003FFH FFFFFH FFFFFH A ee ee Special function register SFR Special function register SFR 256 bytes FFFOOH 256 bytes i _ i L et se register 8 bytes FFEF8H FFEF8H
13. oducts will be made for the next revision of the User s Manual Hardware This outline describes the function at the time when Peripheral I O redirection register PIOR is set to OOH R5F10Y14ASP R5F10Y16ASP R5F10Y17ASP R5F10Y44ASP R5F10Y46ASP R5F10Y47ASP 128 B 256 B 512 B 128 B 256 B 512 B High speed system X1 X2 crystal ceramic oscillation external clock main system clock input EXCLK 1 to 20 MHz Vpb 2 7 to 5 5 V 1 to 5 MHz Voo 2 0 to 5 5 V N High speed on chip e 1 25 to 20 MHz Vpb 2 7 to 5 5 V oscillator clock e 1 25 to 5 MHz Voo 2 0 to 5 5 V 83 Low speed on chip oscillator clock 15 kHz TYP General purpose register 8 bit register x 8 Minimum instruction execution time 0 05 us 20 MHz operation Instruction set e Data transfer 8 bits e Adder and subtractor logical operation 8 bits e Multiplication 8 bits x 8 bits e Rotate barrel shift and bit manipulation set reset test and Boolean operation etc 10 N ch open drain output Voo tolerance 4 Ee Clock output buzzer output 2 44 kHz to 10 MHz Peripheral hardware clock fuain 20 MHz operation a A Serial interface 10 pin products CSI 1 channel simplified I C 1 channel UART 1 channel 16 pin products CSI 2 channels simplified C 1 channel UART 1 channel Vectored interrupt Internal SORES External Key interrupt Reset Reset by RESET pin Internal reset by watchdog timer Internal r
14. rter mode register O0 ADMO to 0 when the internal reference voltage is selected as the target for conversion Refer to 24 6 3 Internal reference voltage characteristics Cautions 1 Arrange wiring and insert the capacitor so that no noise appears on the power supply ground line 2 Do not allow any pulses that rapidly change such as digital signals to be input output to from the pins adjacent to the conversion pin during A D conversion 3 Note that the internal reference voltage cannot be used as the reference voltage of the comparator when the internal reference voltage is selected as the target for A D conversion Page 12 of 13 RENESAS TECHNICAL UPDATE TN RL A023A E 10 24 6 4 Data retention power supply voltage characteristics Page 568 This shows the specifications changed in the ELECTRICAL SPECIFICATIONS of 10 pin products The ELECTRICAL SPECIFICATIONS of Flash ROM 4 KB of 10 pin products and 16 pin products will be made for the next revision of the User s Manual Hardware Old 24 6 4 Data retention power supply voltage characteristics a 40 to 85 C Vss 0 V Parameter Data retention power VDDDR 1 9 5 5 supply voltage range Caution Data is retained until the power supply voltage becomes under the minimum value of the data retention power supply voltage range Note that data in the RAM and RESE registers might not be cleared even if the power supply voltage becomes under the minimum value
15. the corresponding bit of TEO and TEHO is set to 1 When a bit of the TTO and TTHO registers is set to 1 the corresponding bit of TEO and TEHO is cleared to 0 The TEO and TEHO registers can be read by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears TEO and TEHO registers to OOH Correct The TOEO register is used to enable or disable timer output of each channel Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOOn bit of timer output register O TOO described later by software and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin TOOn The TOEO register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to OOH New The 8 bit timer operation function makes it possible to use a 16 bit timer channel in a configuration consisting of two 8 bit timer channels This function can only be used for channels 1 and 3 and there are several rules for using it The basic rules for this function are as follows omitted 7 The lower 8 bits operate according to the settings of TMROnH and TMROnL registers The lower 8 bit timer supports the following functions e Interval timer e Square wave output e External event counter e Delay counter e PWM output function e Multiple PWM output function 16 pin products only Page 7 of 13
16. utput has been enabled becomes unable to rewrite the value of the TOOn bit of timer output register O TOO described later by software and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin TOOn he TOFO register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH 5 6 4 2 Basic rules of 8 bit timer operation function only channels 1 and 3 Page 132 Old The 8 bit timer operation function makes it possible to use a 16 bit timer channel in a configuration consisting of two 8 bit timer channels This function can only be used for channels 1 and 3 and there are several rules for using it The basic rules for this function are as follows omitted 7 The lower 8 bits operate according to the settings of TMROnH and TMROnL registers The following four functions support operation of the lower 8 bits e Interval timer function e External event counter function e Delay count function e PWM output c 2014 Renesas Electronics Corporation All rights reserved CENESAS Date Feb 6 2014 Correct The TEO and TEHO registers are used to enable or stop the timer operation of each channel Each bit of the TEO and TEHO registers correspond to each bit of the timer channel start register 0 TSO TSHO and the timer channel stop register O TTO TTHO When a bit of the TSO and TSHO registers is set to 1
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