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ST10F276

1. Register set ST10F276 Table 67 Special function registers ordered by address continued Name adaress address Description veils CC14IC b FF94h CAh CAPCOM register 14 interrupt control register 00h CC15 FE9Eh 4Fh CAPCOM register 15 0000h CC15IC b FF96h CBh CAPCOM register 15 interrupt control register 00h CC16 FE60h 30h CAPCOM register 16 0000h CC16IC b F160h E BOh CAPCOM register 16 interrupt control register 00h CC17 FE62h 31h CAPCOM register 17 0000h CC17IC b F162h E B1h CAPCOM register 17 interrupt control register 00h CC18 FE64h 32h CAPCOM register 18 0000h CC18IC b F164h E B2h CAPCOM register 18 interrupt control register 00h CC19 FE66h 33h CAPCOM register 19 0000h CC19IC b F166h E B3h CAPCOM register 19 interrupt control register 00h CC1IC b FF7Ah BDh CAPCOM register 1 interrupt control register 00h CC2 FE84h 42h CAPCOM register 2 0000h CC20 FE68h 34h CAPCOM register 20 0000h CC20IC b F168h E B4h CAPCOM register 20 interrupt control register 00h CC21 FE6Ah 35h CAPCOM register 21 0000h CC21IC b F16Ah E B5h CAPCOM register 21 interrupt control register 00h CC22 FE6Ch 36h CAPCOM register 22 0000h CC221C b F16Ch E B6h CAPCOM register 22 interrupt control register 00h CC23 FE6Eh 37h CAPCOM register 23 0000h CC23IC b Fi6Eh E B7h CAPCOM register 23 interrupt control register 00h CC24 FE70h 38h CAPCOM
2. Table 67 Special function registers ordered by address continued Name aadress address Description velus PWMCON1 b FF32h 99h PWM module control register 1 0000h PWMIC b F17Eh E BFh PWM Module interrupt control register 00h QRO F004h E 02h MAC unit offset register RO 0000h QR1 FOO6h E 03h MAC unit offset register R1 0000h QX0 Foo0h E 00h MAC unit Offset Register XO 0000h QX1 F002h E 01h MAC unit offset register X1 0000h RPOH b F108h E 84h System start up configuration register read only XXh SOBG FEB4h 5Ah Serial channel O baud rate generator reload register 0000h SOCON b FFBOh D8h Serial channel 0 control register 0000h SOEIC b FF70h B8h Serial channel 0 error interrupt control register 00h SORBUF FEB2h 59h Serial channel 0 receive buffer register read only XXh SORIC b FF6Eh B7h Serial channel 0 receive interrupt control register 00h SOTBIC b Fi9Ch E CEh ceca 0 transmit buffer interrupt control 00h SOTBUF FEBOh 58h Serial channel 0 transmit buffer register write only 0000h SOTIC b FF6Ch B6h Serial channel 0 transmit interrupt control register 00h SP FE12h 09h CPU system stack pointer register FCOOh SSCBR FOB4h E 5Ah SSC baud rate register 0000h SSCCONb FFB2h D9h SSC control register 0000h SSCEIC b FF76h BBh SSC error interrupt control register 00h SSCRB FOB2h E 59h SSC receive buffer read only XXXXh SSCRIC b
3. 23 8 21 External bus arbitration Vpp 5V 10 Vss OV TA 40 to 125 C C 50pF Table 107 External bus arbitration Fcpu 40 MHz Variable CPU Clock Symbol Parameter TCL z 12 5ns 1 2 TCL 1 to 64 MHz Min Max Min Max HOLD input setup time tg SR to CLKOUT 18 5 18 5 ter CC CLKOUT to HLDA high 62 or BREQ low delay 12 5 12 5 tea CC CLKOUT to HLDA low gs or BREQ high delay ns tg CC CSx release 20 20 tes CC CSx drive 4 15 4 15 tes CC Other signals release 20 20 te7 CC Other signals drive 4 15 4 15 Figure 66 External bus arbitration releasing the bus i I I D CLKOUT F WA PNE CUT IN LUE UN em ME HOLD ey 1 ENG l 1 e HLDA 2 5 X l tee BREQ ON 2 Pos des 3 O r P6 x Ioa d d amp Others j i LLL 1 The ST10F276 will complete the currently running bus cycle before granting bus access 2 This is the first possibility for BREQ to become active 3 The CS outputs will be resistive high pull up after tga 220 229 ky ST10F276 Electrical characteristics Figure 67 External bus arbitration regaining the bus 2 CLKOUT i 1 1 le i i HOLD Teo i 1 lt HLDA EE ND E a ile te tes mui s DUE me NN des t EE CE Em ooo NN NI On P6 x i i der Other rp PER signals 1 This is the last chance for BREQ to trigger the indicated regain
4. ST10F276 System reset 19 9 Reset summary A summary of the different reset events is reported in the table below Table 61 Reset event RSTIN WDTCON Flags a E t Q al t o9 Event Cou Zl ES c c cr E E m G2 min max S S S 5 TII S amp uiuo 1 ms VREG 1 2 ms O O N Asynch Reson PLL 111 170 10 2 ms Power on Reset Crystal PLL O 1 N Asynch 1ms VREG 11 1 1 70 1 x x FORBIDDEN X x Y NOT APPLICABLE O O N Asynch 500ns 0 1 1110 Hardware Reset 0 1 N Asynch 500ns 0 1 1 1 0 Asynchronous g o Y Asynch 500ns 0 1 1 1 0 O 1 Y Asynch 500ns 0 1 1 1 0 1032 12 TCL 1 0 N Synch max 4 TCL 500ns max 4 TCL 500ns 0 O0 1 1 0 1032 12 TCL 1 1 N Synch max 4 TCL 500ns max 4 TCL 500ns 0 10 1110 Short Hardware n maxia ToL sons 1002 2 TOL Synchronous 4 110 Y Synch 0 10 1110 Activated by internal logic for 1024 TCL 1032 12 TCL max 4 TCL 500ns 1 1 Y Synch i max 4 TCL S00 0 4 4 0 Activated by internal logic for 1024 TCL 1032 12 TCL 1 0 N Synch max 4 TCL 500ns 0 1 1100 1032 12 TCL 1 1 N Synch max 4 TCL 500ns 0 1 1100 Long Hardware 1032 12 TCL Reset max 4 TCL 500ns 7 Synchronous 1 0 Y Synch 0 1 1100 Activated by internal logic only for 1024 TCL 1032 12 TCL 1 1 Y Syncn max 4 TCL 500ns 0 1 1 1 0
5. ADCTC ADSTC Sample Comparison Extra Total conversion 00 11 TCL 400 TCL 280 TCL 44 TCL 724 11 00 TCL 240 TCL 480 TCL 52 TCL 772 11 01 TCL 280 TCL 560 TCL 28 TCL 868 11 10 TCL 400 TCL 560 TCL 100 TCL 1060 11 11 TCL 800 TCL 560 TCL 52 TCL 1444 10 00 TCL 480 TCL 960 TCL 100 TCL 1540 10 01 TCL 560 TCL 1120 TCL 52 TCL 1732 10 10 TCL 800 TCL 1120 TCL 196 TCL 2116 10 11 TCL 1600 TCL 1120 TCL 164 TCL 2884 Note The total conversion time is compatible with the formula valid for ST10F269 while the meaning of the bit fielas ADCTC and ADSTC is no longer compatible The minimum conversion time is 388 TCL which at 40 MHz CPU frequency corresponds to 4 85us see ST10F269 23 7 2 A D conversion accuracy The A D converter compares the analog voltage sampled on the selected analog input channel to its analog reference voltage Varer and converts it into 10 bit digital data The absolute accuracy of the A D conversion is the deviation between the input analog value and the output digital value It includes the following errors Offset error OFS Gain error GE Quantization error Nonlinearity error differential and integral These four error quantities are explained below using Figure 46 Offset error Offset error is the deviation between actual and ideal A D conversion characteristics when the digital output value changes from
6. Register set ST10F276 Table 66 General purpose registers GPRs bytewise addressing Name address address Description bns RLO CP 0 FOh CPU general purpose byte register RLO UUh RL3 CP 6 F6h CPU general purpose byte register RL3 UUh RH3 CP 7 F7h CPU general purpose byte register RH3 UUh RL4 CP 8 F8h CPU general purpose byte register RL4 UUh RH4 CP 9 F9h CPU general purpose byte register RHA UUh RL5 CP 10 FAh CPU general purpose byte register RL5 UUh RH5 CP 11 FBh CPU general purpose byte register RH5 UUh RL6 CP 12 FCh CPU general purpose byte register RL6 UUh RH6 CP 13 FDh CPU general purpose byte register RH6 UUh RL7 CP 14 FEh CPU general purpose byte register RL7 UUh RH7 CP 15 FFh CPU general purpose byte register RH7 UUh 138 229 ST10F276 Register set 22 3 Special function registers ordered by name The following table lists in alphabetical order all SFRs which are implemented in the ST10F276 Bit addressable SFRs are marked with the letter b in column Name SFRs within the Extended SFR Space ESFRs are marked with the letter E in column Physical Address Table 67 Special function registers ordered by address Name address address Description vas ADCIC b FF98h CCh eu end of conversion
7. Symbol Parameter Test Condition L J4 Unit Min Max Input low voltage TTL mode Vy SR except RSTIN EA NMI RPD 0 3 0 8 XTAL1 READY Input low voltage CMOS mode Vus SR except RSTIN EA NMI RPD 0 3 0 3 Vpp XTAL1 READY Input low voltage RSTIN EA NMI Vi SR RPD 0 3 0 3 Vpp Input low voltage XTAL 1 Direct drive B Vio SR CMOS only mode 0 3 0 3 Vpp Input low voltage READY i E Vi3 SR TTL only 0 3 0 8 Input high voltage uu TL mode Vin SR _ except RSTIN EA Pie I RPD 2 0 Vpp 0 3 XTAL1 Input high volta NER NM mode Vins SR except RSTIN EA NMI RPD 0 7 Vpp Vpp t 0 3 XTAL1 Input high voltage RSTIN EA Vind SR ET ae 9 0 7 Vpp Vpp t 0 3 178 229 ky ST10F276 Electrical characteristics Table 90 DC characteristics continued Limit values Symbol Parameter Test Condition Unit Min Max Input high voltage XTAL1 Direct Drive Vino SR CMOS only mode 0 7 Vpp Vpp 4 0 3 Input high voltage READY _ Vins SR TTL only 2 0 Vpp t 0 3 Input hysteresis TTL mode VHYS CC except RSTIN EA NMI XTAL1 3 400 700 RPD Input Hysteresis CMOS mode VHYSSCC except RSTIN EA NMI XTAL1 3 750 1400 RPD mV VHYS1CC Input hysteresis RSTIN EA NMI 3 750 1400 VHYS2CC Input hysteresis XTAL1 3 0 50 VHYS3CC Inp
8. ST10F276 Electrical characteristics z 10 11 12 This specification is not valid for outputs which are switched to open drain mode In this case the respective output floats and the voltage is imposed by the external circuitry Port 5 leakage values are granted for not selected A D converter channel One channels is always selected by default after reset P5 0 is selected For the selected channel the leakage value is similar to that of other port pins The leakage of P2 0 is higher than other pins due to the additional logic pass gates active only in specific test modes implemented on input path Pay attention to not stress P2 0 input pin with negative overload beyond the specified limits Failures in Flash reading may occur sense amplifier perturbation Refer to next Figure 44 for a scheme of the input circuitry Not 100 tested guaranteed by design characterization Overload conditions occur if the standard operating conditions are exceeded that is the voltage on any pin exceeds the specified range that is Voy gt Vpp 0 3V or Voy lt 0 3V The absolute sum of input overload currents on all port pins may not exceed 50mA The supply voltage must remain within the specified limits This specification is only valid during Reset or during Hold or Adapt mode Port 6 pins are only affected if they are used for CS output and the open drain function is not enabled The maximum current may be
9. 4TCL 12 TCL 1024 8 TCL lt gt lt gt RSTIN gt 50 ns gt 50ns 250ns lt 500 ns lt 500 ns 500 ns STER 1 gt i lt lt _ RSTF i 7 7 After Filter D S24 TCL P0 15 13 X not transparent transparent not tX P0 12 2 X not t transparent not t X PO 1 0 X not transparent not t 4 i o 7TCL IBUS CS i i lt Internal i i l sims i FLARST l 102448 TOL i i lt _ gt i RST i t i i At this time RSTF is sampled LOW so it is definitely LONG reset RSTOUT RD O O o U_U e 1 2001A Discharge PA Vnpp gt 2 5V Asynchronous Reset not entered Notes 1 If during the reset condition RSTIN low RPD voltage drops below the threshold voltage about 2 5V for 5V operation the asynchronous reset is then immediately entered Even if RPD returns above the threshold the reset is defnitively taken as asynchronous 2 Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter refer to Section 21 1 115 229 System reset ST10F276 19 4 116 229 Figure 31 Synchronous long hardware RESET EA 0 4 TCL 12 TCL 1024 8 TCL t gt RSTIN i i 250 ns 2 50 ns 250ns lt 500 ns lt
10. 214 229 ST10F276 Electrical characteristics Figure 62 Demultiplexed bus with without R W delay and extended ALE OJ x A23 A16 A15 A0 P1 BHE Read cycle Data Bus PO D15 D8 D7 DO al U Write cycle Data Bus PO D15 D8 D7 DO e l m li i TNS 222222 1 I l ede uum l i lt t t20 215 229 Electrical characteristics 216 229 Figure 63 Demultiplexed bus with ALE and R W CS CLKOUT Lam Ww A in AN ALE A23 A16 A15 AQ P1 BHE Read cycle Data Bus PO D15 D8 D7 DO Write cycle Data Bus PO D15 D8 D7 DO l l I l l i l l etso t gt I l SS ESO E E WrCSx oN ST10F276 ST10F276 Electrical characteristics Figure 64 Demultiplexed bus no R W delay extended ALE R W CS VERON EEUU AP NY ANA ha ts r i gt tas ALE ANN tie o a i l E ls I 17 T E A23 A16 i BHE a l l l Il Read cycle l i Data Bus PO SS D15 D8 D7 DO 422227 I i l l l lt lao tig gt p 15s lt las gt lt ty7 E E tes g l 1 l Ss l i RdCSx vse eed I MILL l l l tyg l m tag Write cycle l l Data Bus P0 D15 D8 D7 DO i l l l rt tgo E l l I l i i las 5o els gt l
11. 195 229 Electrical characteristics ST10F276 23 8 3 23 8 4 23 8 5 196 229 Clock generation modes The following table associates the combinations of these 3 bits with the respective clock generation mode Table 95 On chip clock generator selections P0 15 13 CPU frequency External clock input POH 7 5 fcpu fyxtaL X F range 2 Notes 1 1 1 FytaL X 4 4 to 8 MHz Default configuration 1 1 O0 FxraLx3 5 3 to 10 6 MHz 1 0 1 FxrAL X 8 4 to 8 MHz 1 0 0 Fyax5 6 4 to 12 MHz O 1 1 Fg x1 1to 64 MHz Direct Drive oscillator bypassed 9 Oo 1 0 Py x 10 4 to 6 4 MHz 0 0 1 Fyqat 2 4 to 12 MHz CPU clock via prescaler 9 0 0 O Fyr x 16 4 MHz The external clock input range refers to a CPU clock range of 1 64 MHz Moreover the PLL usage is limited to 4 12 MHZ input frequency range All configurations need a crystal or ceramic resonator to generate the CPU clock through the internal oscillator amplifier apart from Direct Drive on the contrary the clock can be forced through an external clock source only in Direct Drive mode on chip oscillator amplifier disabled so no crystal or resonator can be used 2 The limits on input frequency are 4 12 MHZ since the usage of the internal oscillator amplifier is required Also when the PLL is not used and the CPU clock corresponds to Fxr4 2 an external crystal or resonator must be used It is not possible to force any clo
12. ERR SUSP BxS z 1 meaning BxFy z 1 meaning 1 Erase error in bank x Erase error in sector y of bank x 0 1 Erase suspended in bank x Erase suspended in sector y of bank x 0 0 Don t care Don t care 4 4 5 Flash data register 0 low The Flash address registers FARH L and the Flash data registers FDR1H L FDROH L are used during the program operations to store Flash Address in which to program and data to program FDROL OxOE 0008 FCR Reset value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DINO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 11 Flash data register 0 low Bit Function Data input 15 0 DIN 15 0 These bits must be written with the data to program the Flash with the following operations word program 32 bit double word program 64 bit and set protection 4 4 6 Flash data register 0 high FDROH 0x0E 000A FCR Reset value FFFFh 15 14 43 12 1 do 9 8 7 6 5 4 3 2 41 0 DIN31 DINSO DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 12 Flash data register 0 high Bit Func
13. 0 00 ee 176 23 2 Recommended operating conditions cee ee eee 176 23 3 Power considerations 2 2265 siecav8eteebwhadivivesesteaeoa bs 177 23 4 Parameter interpretation 00000 ee 178 235 DC characteristics cele eR dicated teed chad RARE A RON RR ah god 178 23 8 Flash characteristics cesses hr RR RR RR ERR ES 183 23 7 A D converter characteristics 00 0 cece eee eee 185 23 7 4 Conversion timing control 00 000 ees 186 23 7 A D conversion accuracy 0000 cee eee 187 23 7 3 Total unadjusted error 0 0 ee ee 188 6 229 ky ST10F276 Contents 23 7 4 Analog reference pins liliis 189 23 75 Analog input pins llle eh 189 23 7 6 Example of external network sizing 0 00 eee eee 193 23 8 AC characteristics lt ccicicesertaas S ERR Rr ERR eee EI ads 194 23 81 Testwaveforms sees 194 23 8 2 Definition of internal timing llle 195 23 8 8 Clock generation modes 000 c eee esee 196 23 8 44 Prescaler operation 0 cee eee 196 23 8 5 Direct drives iocos iso ee ada OREA Leen ER d 196 23 8 6 Oscillator watchdog OWD 0 000 c eee eee 197 23 8 7 Phase locked loop PLL 0 0 cece eee 197 23 8 8 Voltage controlled oscillator 1 2 0 0 00 ee 198 23 3 9 PLL Jitter eo cagenseee seed chase de hebieeee eed a a denne bee 199 23 8 10 Jitter in the input
14. lille 40 Summary of access protection level llis enn 40 Flash write operations llle RR 44 ST10F276 boot mode selection 0 00 cette 47 ST10 configuration in BSL mode 0 00 cee 48 ST10 configuration in UART BSL mode RS232 or K line 0 0000 eee 55 ST10 configuration in CAN BSL sasaaa aaan 59 BRP and PTO values cani cece ete nets 62 Software topics summary 0 000 ae 64 Hardware topics summary 00 ee tees 65 ST10 configuration in alternate boot Mode 1 1 eee 66 ABM bit description 000 eee 68 Selective boot 2 4 vende lade da atdida duerme ea dade ede rie S aes 69 Standard instruction set summary 00 eee 73 MAC instruction set SUMMAary 2 2 tees 75 Interrupt SOUNCES RR 77 X Interrupt detailed mapping 0 eee 80 Trap prioritles usce de SEWER Pen EES T an dae Paes due ce ata 81 Compare modes ssisssleeeeeeeee ehh 83 CAPCOM timer input frequencies resolutions and periods at 40 MHz 83 CAPCOM timer input frequencies resolutions and periods at 64 MHz 83 GPT1 timer input frequencies resolutions and periods at 40 MHz 84 GPT1 timer input frequencies resolutions and periods at 64 MHz 85 GPT2 timer input frequencies resolutions and periods at 40 MHz 86 ST10F276 List of tables Table 49 Table 50 Table 51
15. Figure 29 Synchronous short long hardware RESET EA 0 lt 4 TCL5 12 TCL 1032 TCL lt gt lt gt RSTIN 1 i 4 2 50 ns 250 ns 2 50 ns 500 ns lt 500 ns lt 500 ns c gt gt RSTF After Filter P0 15 13 X not transparent X PO 12 2 X not t transparent 1 nott X PO 1 0 x not transparent nott X i t 18 8T0L3 8TCL i its ALE 1 E 1 i i 1024 TCL 8 TCL i lt aid RST i i this time RSTE is sampled HIGH or LOW so itis SHORT or LONG reset RSTOUT RPD 200mA 2 VRPD 2 5V Asynchronous Reset not entered Notes 1 RSTIN assertion can be released there Refer also to Section 21 1 for details on minimum pulse duration 2 If during the reset condition RSTIN low RPD voltage drops below the threshold voltage about 2 5V for 5V operation the asynchronous reset is then immediately entered 3 3 to 8 TCL depending on clock source selection 4 RSTIN pin is pulled low if bit BDRSTEN bit 3 of SYSCON register was previously set by software Bit BDRSTEN is cleared after reset 5 Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter refer to Section 21 1 114 229 ST10F276 System reset a Figure 30 Synchronous long hardware RESET EA 1
16. 5 4 6 Note Note 5 4 7 Note Computing the baud rate error Considering the following conditions a computation of the error is given as an example e CPU frequency 20 MHz e Target Bit Rate 1 Mbit s In these conditions the content of PTO timer for 29 bits should be 29 x Fepu_ 29x20x6 E LP E9 BitRate 1x10 zm Therefore 574 PTO 586 This gives BRP 0 tq 100 ns Computation of 1 Tseg Tseg2 Considering the equation PTO 58 x 1 BRP x 1 Tseg1 Tseg2 Thus 574 586 lt T 1 Tseg2 1 9 58 seg seg 58 0 In the algorithm a rounding up to the superior value is made if the remainder of the division is greater than half of the divisor This would have been the case if the PTO content was 574 Thus in this example the result is 1 Tseg Tseg2 10 giving a bit time of exactly 1us gt no error in bit rate In most cases 24 MHz 32 MHz 40 MHz of CPU frequency and 125 250 500 or 1Mb s of bit rate there is no error Nevertheless it is better to check for an error with the real application parameters The content of the bit timing register is 0x1640 This gives a sample point at 80 The Re Synchronization Jump Width is fixed to 2 time quanta Bootstrap via CAN After the bootstrap phase the ST10F276 CAN module is configured as follows e The pin P4 6 is configured as output the latch value is 1 recessive to assume CAN1 TxD function e The MO2 i
17. 0 2 00AC 00AD 9 600 0 2 0 0 0207 0208 9 600 0 1 0 2 015A 015B 4 800 0 1 0 0 0410 0411 4 800 0 1 0 1 02B5 02B6 2 400 0 0 0 0 0822 0823 2 400 0 1 0 0 056B 056C 1 200 0 0 0 0 1045 1046 1 200 0 0 0 0 OAD8 OAD9 ky 95 229 Serial channels ST10F276 Table 54 ASC synchronous baud rates by reload value and deviation errors fcp 40 MHz SOBRS 0 fcpy 40 MHz SOBRS 1 fcpy 40 MHz Baud Rate Baud Deviation Error Reload Value Baud Rate Baud Deviation Error Reload Value hex hex 900 0 0 0 0 15B2 15B3 600 0 0 0 0 15B2 15B3 612 0 0 0 0 1FE8 1FE9 407 0 0 0 0 1FFD 1FFE Table 55 ASC synchronous baud rates by reload value and deviation errors fcpy 64 MHz SOBRS 0 fcpu 64 MHz SOBRS 1 fopy 64 MHz Baud Rate Baud Deviation Error Reload Value Baud Rate Baud Deviation Error Reload Value hex hex 8 000 000 0 0 0 0 0000 0000 5 333 333 0 0 0 0 0000 0000 112 000 0 6 0 8 0046 0047 112 000 1 3 0 8 002E 002F 56 000 0 6 0 1 008D 008E 56 000 0 3 0 8 005E 005F 38 400 0 2 0 396 OOCF 00DO 38 400 0 6 0 196 0089 008A 19 200 0 2 0 1 019F 01A0 19 200 0 3 0 1 0114 0115 9 600 x 0 095 0 1 0340 0341 9 600 0 1 0 196
18. 08 FFFF 4 are redirected to the special Test Flash Data read operations will access the internal Flash of the ST10F276 Choosing the baud rate for the BSL via CAN The Bootstrap via CAN acts the same way as in the UART bootstrap mode When the ST10F276 is started in BSL mode it polls the RxDO and CAN1_RxD lines When polling a low level on one of these lines a timer is launched that is stopped when the line returns to high level For CAN communication the algorithm is made to receive a zero frame that is the standard identifier is 0x0 DLC is 0 This frame produces the following levels on the network 5D 1R 5D 1R 5D 1R 5D 1R 5D 1R 4D 1R 1D 11R The algorithm lets the timer run until the detection of the 5 recessive bit This way the bit timing is calculated over the duration of 29 bit times This minimizes the error introduced by the polling Figure 12 Bit rate measurement over a predefined zero frame Start Stuff bit Stuff bit Stuff bit Stuff bit nnnn T lt i Measured time ST10F276 Bootstrap loader Error induced by the polling The code used for the polling is the following WaitCom JNB P4 5 CAN Boot if SOF detected on CAN then go to CAN loader JB P3 11 WaitCom Wait for start bit at RxDO BSET T6R Start Timer T6 CAN Boot BSET PWMCONO 0 Start PWM TimerO0 resolution is 1 CPU clk cycle MPR cc UC WaitRecessiveBit WaitDominantBit J
19. During Power on and Power off transients including Stand by entering exiting phases the relationships between voltages applied to the device and the main Vpp must always be respected In particular power on and power off of Vange must be coherent with the Vpp transient in order to avoid undesired current injection through the on chip protection diodes Recommended operating conditions Table 87 Recommended operating conditions Symbol Parameter Min Max Unit Vpp Operating supply voltage 7 4 5 5 5 Vstpy Operating stand by supply voltage V VAREF Operating analog reference voltage 0 Vpp TA Ambient temperature under bias 125 5 40 D Tj Junction temperature under bias 150 1 The value of the Vstpy voltage is specified in the range 4 5 5 5 volts Nevertheless it is acceptable to exceed the upper limit up to 6 0 volts for a maximum of 100 hours over the global 300000 hours representing the lifetime of the device about 30 years On the other hand it is possible to exceed the lower limit down to 4 0 volts whenever RTC and 32 kHz on chip oscillator amplifier are turned off only Stand by RAM powered through Vsrgy pin in Stand by mode When Vsrgy voltage is lower than main Vpp the input section of Vergy EA pin can generate a spurious static consumption on Vpp power supply in the range of tenth of uh ky ST10F276 Electrical characteristics 23 3 2 For details o
20. Before Flash initialization completion the default setting of the different identification registers are the following IDMANUF 0403h IDCHIP 114xh x silicon revision IDMEM FODOh IDPROG 0040h ST10F276 Register set 22 10 Note System configuration registers The ST10F276 has registers used for a different configuration of the overall system These registers are described below SYSCON FF12h 89h SFR Reset value OxxOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ROM SGT ROM BYT CLK WR CS PWD OWD BDR VISI XPER is 1 DIS EN DIS EN cra cra cra pis sten PEN BLE sHARE RW RW RW RW RW RW RW RW RW RW RW RW RW RW SYSCON Reset Value is 0000 Oxx0 0x00 0000b Table 77 _ SYSCON description Bit Function XBUS peripheral share mode control 0 External accesses to XBUS peripherals are disabled XPER SHARE 1 XRAM1 and XRAM2 are accessible via the external bus during hold mode External accesses to the other XBUS peripherals are not guaranteed in terms of AC timings Visible mode control VISIBLE 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins 1 The on chip X peripherals are enabled XBUS peripheral enable bit XPEN 0 Accesses to the on chip X peripherals and XRAM are disabled Bidirection
21. O being the XPERCON Register powered by internal V g This does not generate any problem because the Stand by Mode switching dedicated circuit continues to confirm the RAM interface freezing irrespective the XRAM2EN bit content XRAM2EN bit status is considered again when internal V g comes back over internal stand by reference Vigsp If internal V4g becomes lower than internal stand by reference V48spg of about 0 3 to 0 45V with bit XRAM2EN set the RAM Supply switching circuit is not active in case of a temporary drop on internal V4a voltage versus internal V4asg during normal code execution no spurious Stand by Mode switching can occur the RAM is not frozen and can still be accessed The ST10F276 Core module generating the RAM control signals is powered by internal Vig supply during turning off transient these control signals follow the V4a while RAM is switched to Vjggp internal reference It could happen that a high level of RAM write strobe from ST10F276 Core active low signal is low enough to be recognized as a logic O by the RAM interface due to V g lower than Vigsp The bus status could contain a valid address for the RAM and an unwanted data corruption could occur For this reason an extra interface powered by the switched supply is used to prevent the RAM from this kind of potential corruption mechanism ST10F276 Power reduction modes 20 3 2 20 3 3 Warning During power off phase it is im
22. Table 37 Selective boot Bit Function UART selection 0 0 UART is not watched for a Start condition 1 UART is watched for a Start condition CAN1 selection 1 0 CAN1 is not watched for a Start condition 1 CAN1 is watched for a Start condition Reserved 2 7 For upward compatibility must be programmed to 0 Therefore a value OxXXO03 configures the Selective Bootstrap Loader to poll for RxDO and CAN1 RxD 0xXX01 configures the Selective Bootstrap Loader to poll only RxDO no boot via CAN OxXXO02 configures the Selective Bootstrap Loader to poll only CAN1_RxD no boot via UART e Other values allow the ST10F276 to execute an endless loop into the Test Flash ky 69 229 Bootstrap loader ST10F276 Figure 13 Reset boot sequence Standard start Yes POL 5 4 01 No POL 5 4 11 Boot mode Yes POL 5 4 10 No POL 5 4 other config oftware checks K1 is OK user reset vector K1 is OK K1 is not OK oftware Checks K2 is not OK alternate reset vector K2 is OK K2 is OK Read 001 FFCh Long jump to 09 0000h SW RESET Running from test Flash ABM User Flash Std Bootstrap Loader Start at 09 0000h Jump to Test Flash Selective Bootstrap Loader User Mode User Flash Jump to Test Flash Start at 00 0000h 70 229 ST10F276 Central processing
23. Watchdog timer The Watchdog Timer is a fail safe mechanism which prevents the microcontroller from malfunctioning for long periods of time The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT end of initialization instruction has been executed Therefore the chip start up procedure is always monitored The software must be designed to service the watchdog timer before it overflows If due to hardware or software related failures the software fails to do so the watchdog timer overflows and generates an internal hardware reset It pulls the RSTOUT pin low in order to allow external hardware components to be reset Each of the different reset sources is indicated in the WDTCON register e Watchdog Timer Reset in case of an overflow e Software Reset in case of execution of the SRST instruction Short Long and Power On Reset in case of hardware reset and depending of reset pulse duration and RPD pin configuration The indicated bits are cleared with the EINIT instruction The source of the reset can be identified during the initialization phase The Watchdog Timer is 16 bit clocked with the system clock divided by 2 or 128 The high Byte of the watchdog timer register can be set to a pre specified reload value stored in WDTREL Each time it is serviced by the application software the high byte of the watchdog timer is reloaded For security rewrite
24. l p Lag gt i Write cycle l 1 I Address Data Add l T Bus P0 l 1 l 1 1 ol e tye ty 4 m tss l x ty m tas gt too gt MM I WrCSx T RN N I l I tg i tag d 211 229 Electrical characteristics ST10F276 23 8 19 Demultiplexed bus Vpp 5V 10 Vss OV Ta 40 to 125 C C 50pF ALE cycle time 4 TCL 2t tc te bOns at 40 MHz CPU clock without wait states Table 105 Demultiplexed bus Fcpu 40 MHz Variable CPU clock Symbol Parameter TCL 12 5ns 1 2 TCL 1 to 64 MHz Min Max Min Max ts CC ALE high time 4 ta TCL 8 5 t4 ns tg CC Address setup to ALE 1 5 t4 TCL 11 amp ta ns Address Unlatched CS tgo CC setup to RD WR 12 5 Qt 2TCL 12 5 2t ns with RW delay Address Unlatched CS tg CC setup to RD WR 0 5 2t4 TCL 12 2t4 ns no RW delay RD WR low time with RW delay RD WR low time no RW delay t2 CC 15 5 tc 2TCL 9 5 tc ns tu CC 28 tc 3TCL 9 5 tc ns RD to valid data in tia SR with RW delay 6 lc 2TCL 19 i ns RD to valid data in tis SR no RW delay 18 5 tc 3TCL 19 tc ns tie SR ALE low to valid data in 17 5 ta lc 3TCL 20 ta t ns Address Unlatched CS 4TCL 30 2t t7 SR valid data in uL sie i tc ns tg SR Data hold after RD E A 7 id rising edge Data float after RD er tog SR risin
25. 2 Pin data Figure 2 Pin configuration top view 7 A15 CC271 6 A14 CC26l 5 A13 CC25l 4 A12 CC24I 3 A11 2 A10 1 A9 0 A8 5 AD13 4 AD12 3 AD11 2 AD10 1 AD9 P POH 0 AD8 H POL 7 AD7 H POL 6 AD6 P POL 5 ADS H POL 4 AD4 H POL 1 AD1 P8 0 XPOUTO CC161O g D POL O ADO P8 1 XPOUT1 CC171O g H EA VSTBY P8 2 XPOUT 2 CC18lO g P8 3 XPOUTS CC191O g P8 4 CC20IO g P8 5 CC21IO t P8 6 RxD1 CC221O g P8 7 TxD1 CC23IO q O0 00 590v PLUSH ON TUB o h P4 6 A22 CANT TxD CAN2 Tx ST10F276 h P4 5 A21 CAN1 RxD CAN2_RxD P7 0 POUTO g P7 1 POUTI tj P7 2 POUT2q P7 3 POUT3 g P7 4 CC28IO g P7 5 CC2910 q P7 6 CC3010 g P7 7 CC3110 g P5 0 ANO rj P5 1 AN1 g P P3 15 CLKOUT P5 2 AN2 g P P3 13 SCLKO P5 3 AN3 q P P3 12 BHE WRH P5 4 ANA r P5 5 AN5 t P5 6 AN6 rj P5 7 AN7 t P5 8 AN8 g P5 9 AN9 g VAREF 4 37 P5 10 AN10 T6EUD P5 11 AN11 T5EUD P2 P2 P2 P2 P2 P2 P2 P2 P3 3 T3OUT P5 12 AN12 T6IN P5 13 AN13 T5IN P5 14 AN14 TAEUD P5 15 AN15 TZEUD P3 4 TSEUD 16 229 Ti ST10F276 Pin data Table 1 Pin description Symbol Pin Type Function 8 bit bidirectional I O port bit wise programmable for input or output via direction bit Programming an I O pin as input forces the corresponding output driver to 1 8 lO
26. 4 Those signals as other configuration signals are latched on the rising edge of RSTIN pin The alternate boot function is divided in two functional parts which are independent from each other Part 1 Selection of reset sequence according to the PortO configuration User mode and alternate mode signatures e Decoding of reset configuration POL 5 1 POL 4 1 selects the normal mode and the user Flash to be mapped from address 00 0000h e Decoding of reset configuration POL 5 1 POL 4 0 selects ST10 standard bootstrap mode Test Flash is active and overlaps user Flash for code fetches from address 00 0000h user Flash is active and available for read and program e Decoding of reset configuration POL 5 0 POL 4 1 activates new verifications to select which bootstrap software to execute if the user mode signature in the user Flash is programmed correctly then a software reset sequence is selected and the user code is executed _ if the user mode signature is not programmed correctly but the alternate mode signature in the user Flash is programmed correctly then the alternate boot mode is selected if both the user and the alternate mode signatures are not programmed correctly in the user Flash then the user key location is read again Its value will determine the behavior of the selected bootstrap loader Part 2 Running of user selected reset sequence e Standard bootstrap loader Jump to a predef
27. Activated by internal logic only for 1024 TCL 127 229 System reset ST10F276 Table 61 Reset event continued RSTIN WDTCON Flags a E t A al o9 Event c ui 2 E c elc E n a2 min max z z amp luo x O N Synch Not activated 0 0 0 1 0 x O N Synch Not activated 0 0 0 1 0 Software Reset O 1 Y Synch Not activated 0 0 0 1 0 1 1 Y Synch Activated by internal logic for 1024 TCL 0 0 0 1 0 x O N Synch Not activated 0 0 0 1 1 x O N Synch Not activated 0 0 0 1 1 Watchdog Reset 2 O 1 Y Synch Not activated 0 0 0 1 1 1 1 Y Synch Activated by internal logic for 1024 TCL 0 0 0 1 1 1 It can degenerate into a Long Hardware Reset and consequently differently flagged see Section 19 3 for details 2 When Bidirectional is active and with RPD 0 it can be followed by a Short Hardware Reset and consequently differently flagged see Section 19 6 for details The start up configurations and some system features are selected on reset sequences as described in Table 62 and Figure 42 Table 62 describes what is the system configuration latched on PORTO in the six different reset modes Figure 42 summarizes the state of bits of PORTO latched in RPOH SYSCON BUSCONO registers Table 62
28. BUSCONO FFOCh 86h SFR Reset value OxxOh 15 14 13 12 11 10 9 8 5 4 3 210 CSWENO CSRENO RDYPOLORDYENO BUSACTO ALECTLO BTYP MTTCO RWDCO MCTC RW RW RW RW RW RW RW RW RW BUSCON1 FF14h 8Ah SFR Reset value 0000h 15 14 13 12 11 10 9 8 5 4 3 2 1 0 CSWEN 1 CSREN 1 RDYPOL1 RDYEN1 BUSACT1 ALECTL1 BTYP MTTC1 RWDC1 MCTC RW RW RW RW RW RW RW RW RW RW BUSCON2 FF16h 8Bh SFR Reset value 0000h 15 14 13 12 11 10 9 8 5 4 3 2 1 0 CSWEN2 CSREN2 RDYPOL2 RDYEN2 BUSACT2 ALECTL2 BTYP MTTC2 RWDC2 MCTC RW RW RW RW RW RW RW RW RW BUSCONG FF18h 8Ch SFR Reset value 0000h 15 14 13 12 11 10 9 8 5 4 3 2 1 0 CSWEN3 CSREN3 RDYPOL3 RDYEN3 BUSACT3 ALECTL3 BTYP MTTC3 RWDC3 MCTC RW RW RW RW RW RW RW RW RW ky ST10F276 Register set BUSCONA FF1Ah 8Dh SFR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 210 CSWEN4 CSREN4 RDYPOL4 RDYEN4 BUSACTA ALECTLA BTYP MTTC4 RWDC4 MCTC RW RW RW RW RW RW RW RW RW Table 78 _BUSCON4 description Bit MCTC Function Memory cycle time control number of memory cycle time wait states 0000 15 wait states Number of wait states 15 MCTC 1111 No wait states RWDCx Read Write delay control for BUSCONx 0 With read write delay the CPU inserts 1 TCL after falling edge of ALE 1 No read write delay RW is activated after falling edge of ALE
29. Cp Cpa Ts t In particular two different transient periods can be distinguished see Figure 48 190 229 Ti ST10F276 Electrical characteristics 1 A first and quick charge transfer from the internal capacitances Cp and Cp to the sampling capacitance Cg occurs Cg is supposed initially completely discharged Considering a worst case since the time constant in reality would be faster in which Cp is reported in parallel to Cp call Cp Cp Cpo the two capacitances Cp and Cs are in series and the time constant is Cp Cg Rip AD Cp Cg t Rew This relation can again be simplified considering only Cg as an additional worst condition In reality the transient is faster but the A D converter circuitry has been designed to also be robust in the very worst case The sampling time Ts is always much longer than the internal time constant 4 lt Rew Rap Cs lt lt Ts The charge of Cp and Cp is also redistributed on Cg determining a new value of the voltage V44 on the capacitance according to the following equation Vat Cg Cpy Cpa Va Cp4 Cp 2 A second charge transfer also involves Cr that is typically bigger than the on chip capacitance through the resistance R Again considering the worst case in which Cpo and Cs were in parallel to Cp since the time constant in reality would be faster the time constant is t9 lt R Cg f Cp4 Cp5 In this case the time
30. Once the Program operation is finished the Erase operation can be resumed in the following way FCROH 0x0800 Set SER in FCROH FCROH 0x8000 Operation resume Notice that during the Program Operation in Erase suspend bits SER and SUSP are low A Word or Double Word Program during Erase Suspend cannot be suspended To summarize A Sector Erase can be suspended by setting SUSP bit To perform a Word Program operation during Erase Suspend firstly bits SUSP and SER must be reset then bit WPG and WMS can be set To resume the Sector Erase operation bit SER must be set again nany case it is forbidden to start any write operation with SUSP bit already set Set protection Example 1 Enable Write Protection of sectors BOF3 0 of Bank 0 in IFLASH module FCROH 0x0100 Set SPR in FCROH FARL OxDFB4 Load Add of register FNVWPIRL in FARL FARH 0x000E Load Add of register FNVWPIRL in FARH FDROL OxFFF0 Load Data in FDROL FDROH OxFFFF Load Data in FDROH FCROH 0x8000 Operation start Notice that bit SMOD of FCROH must not be set since Write Protection bits of IFLASH Module are stored in Test Flash XFLASH Module 43 229 Internal Flash memory ST10F276 4 7 44 229 Example 2 Enable Access and Debug Protection FCROH 0x0100 Set SPR in FCROH FARL FARH FDROL OxFFFC Load 1 FCROH 0x8000 Opera
31. Reference supply current Power Down mode 1 uA ts CC Sample time 4 1 us te CC Conversion time 5 3 us pw CC Differential nonlinearity No overload 1 1 LSB in CC Integral nonlinearity 9 No overload 1 5 1 5 LSB ors CC Offset error 9 No overload 1 5 41 5 LSB iuc m 2 0 20 LSB tue CC Total unadjusted error 3 5 0 5 0 LSB dd 7 0 7 0 LSB Port1 Overload Coupling factor between On both Port5 and 6 e inputs 7 Port T 10 Cp CC 3 pF m Input pin capacitance 8 pou J 4 pF ES Port 6 pF Cs CC Sampling capacitance 9 3 5 pF Port5 600 W Rsw CC ane switch resistance 9 Port1 1600 W Rap CC 1300 Ww 1 Varep can be tied to ground when A D converter is not in use An extra consumption around 200A on main Vpp is added due to internal analog circuitry not completely turned off Therefore it is suggested to maintain the VAngr at Vpp level even when not in use and eventually switch off the A D converter circuitry setting bit ADOFF in ADCON register 2 Vain may exceed Vacnp OF Varer up to the absolute maximum ratings However the conversion result in these cases will be 0x000 or OXSFF respectively 3 Not 100 6 tested guaranteed by design characterization During the sample time the input capacitance Cay can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach its final voltage level with
32. high impedance state Port 6 outputs can be configured as push pull or open drain drivers The input threshold of Port 6 is selectable TTL or CMOS The following Port 6 pins have alternate functions 1 O P6 0 CSO Chip select O output P6 0 P6 7 5 O P6 4 CS4 Chip select 4 output l P6 5 HOLD External master hold request input 6 y o SCLK1 SSC1 master clock output slave clock input O P6 6 HLDA Hold acknowledge output 7 y o MTSR1 SSC1 master transmitter slave receiver O I O P6 7 BREQ Bus request output 8 y o MRST1 SSC1 master receiver slave transmitter I O 8 bit bidirectional I O port bit wise programmable for input or output via direction bit Programming an I O pin as input forces the corresponding output driver to 9 16 l O high impedance state Port 8 outputs can be configured as push pull or open drain drivers The input threshold of Port 8 is selectable TTL or CMOS The following Port 8 pins have alternate functions lO P8 0 CC16lO CAPCOM 2 CC16 capture input compare output 9 O XPWMO PWM1 channel 0 output P8 0 P8 7 i lO P8 3 CC19IO CAPCOM2 CC19 capture input compare output O XPWMO PWM1 channel 3 output 13 lO P8 4 CC20lO CAPCOM 2 CC20 capture input compare output 14 VO P8 5 CC21IO CAPCOM 2 CC21 capture input compare output O P8 6 CC22lIO CAPCOM 2 CC22 capture input compare output 15 y o RxD1 ASC1 Data input Asynchronous or I O Synchronous O P8 7 CC23IO CAPCOM 2 CC23 capture input
33. ky ST10F276 16 bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM Features Highly performant 16 bit CPU with DSP functions 31 25ns instruction cycle time at G4MHz max CPU clock Multiply accumulate unit MAC 16 x 16 bit multiplication 40 bit accumulator Enhanced boolean bit manipulations PQFP144 28 x 28 x 3 4mm Plastic Quad Flat Package LQFP144 20 x 20 x 1 4mm Low Profile Quad Flat Package HU m 4 channel PWM unit 4 channel XPWM Single cycle context switching support AID M Open mamans piod 10 bit 512 Kbyte Flash memory 32 bit fetch l 3 us minimum conversion time 320 Kbyte extension Flash memory 16 bit fetch m Serial channels Single voltage Flash memories with Two synch asynch serial channels erase program controller and 100K Two high speed synchronous channels erasing programming cycles One I C standard interface E Sx andideta 5 MOVES With CAN oF 120 m 2CAN 2 0B interfaces operating on 1 or 2 CAN 2 Kbyte internal RAM IRAM busses 64 or 2x32 message C CAN version 66 Kbyte extension RAM XRAM m Fail safe protection m External bus Programmable watchdog timer Programmable external bus configuration amp n siis Mateo characteristics for different address ranges m On chip bootstrap loader Five programmable chip select signals m Clock generation Hold acknowledge bus arbitrati
34. 21 tc RdCS WrCS low time tg CC with RW delay 15 5 4 tc 2TCL 9 5 tc RdCS WrCS low time tag CC no RW delay 28 tc 3TCL 9 5 tc E tso CC Data valid to WrCS 10 4 tc 2TCL 15 tc ts SR Data hold after RACS 0 0 tso SR DE oat aher MdG 16 5 te 2TCL 8 5 te t CC Address hold after RdCS WrCS 6 te 2TCL 19 tp tss CC Data hold after WrCS 1 Partially tested guaranteed by design characterization ky 207 229 Electrical characteristics ST10F276 Figure 57 Multiplexed bus with without R W delay and normal ALE Wem ANA N7 SF NS NSN l ALE A23 A16 A15 A8 Address l BHE Read cycle tem Address Data Bus P0 X Address Address Write cycle pog m r2 e p oM 13 T i l l l l lo PRA SP gt l I l l I i ots mi Address Data D g E Y z D T 208 229 ST10F276 Electrical characteristics Figure 58 Multiplexed bus with without R W delay and extended ALE I l ALE CSx A23 A16 i A15 A8 Address 2 4 BHE l i i i f i 1 I l i l Read cycle l te gt lt t Bus PO y l l lus l lt ts gt lt tig gt l t j l lig be ty gt lt t la gt l l a B Y lis Write cycle l l l Bus P0 I ts tio E l I to gt lt t ti za
35. 84 229 General purpose timer unit The GPT unit is a flexible multifunctional timer counter structure which is used for time related tasks such as event timing and counting pulse width and duty cycle measurements pulse generation or pulse multiplication The GPT unit contains five 16 bit timers organized into two separate modules GPT1 and GPT2 Each timer in each module may operate independently in several different modes or may be concatenated with another timer of the same module GPT1 Each of the three timers T2 T3 T4 of the GPT1 module can be configured individually for one of four basic modes of operation timer gated timer counter mode and incremental interface mode In timer mode the input clock for a timer is derived from the CPU clock divided by a programmable prescaler In counter mode the timer is clocked in reference to external events Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the gate level on an external input pin For these purposes each timer has one associated port pin TxIN which serves as gate or clock input Table 46 and Table 47 list the timer input frequencies resolution and periods for each pre scaler option at 40MHz and 64MHz CPU clock respectively In Incremental Interface Mode the GPT1 timers T2 T3 T4 can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and
36. Power reduction modes Three different power reduction modes with different levels of power reduction have been implemented in the ST10F276 In Idle mode only CPU is stopped while peripheral still operate In Power Down mode both CPU and peripherals are stopped In Stand by mode the main power supply Vpp can be turned off while a portion of the internal RAM remains powered via Vergy dedicated power pin Idle and Power Down modes are software activated by a protected instruction and are terminated in different ways as described in the following sections Stand by mode is entered simply removing Vpp holding the MCU under reset state All external bus actions are completed before ldle or Power Down mode is entered However Idle or Power Down mode is not entered if READY is enabled but has not been activated driven low for negative polarity or driven high for positive polarity during the last bus access Idle mode Idle mode is entered by running IDLE protected instruction The CPU operation is stopped and the peripherals still run Idle mode is terminate by any interrupt request Whatever the interrupt is serviced or not the instruction following the IDLE instruction will be executed after return from interrupt RETI instruction then the CPU resumes the normal program Power down mode Power Down mode starts by running PWRDN protected instruction Internal clock is stopped all MCU parts are on hold including the watchdog timer
37. Q 5 bie E E gt lt po lt gt 4TCL X OCh not transparent A Yee cb l 3 a S c5 i E 2 E g Br 2 8 NU t A B S c Ei Q 7 c g E E SE bele ee gege mm Sa 55 E z a o E 8 E E a g wo N Ta p n Es Q 5 KS 5 d e e e e tc cc os tt S12 a a a a 125 229 ST10F276 System reset 0 Example of software or watchdog bidirectional reset EA Figure 41 juiod Buigoje v jueyedsuej jou jueyedsuej jou o Lod 1 juiod Buryoye7 y juasedsues jou jueredsuea X 1uejedsuegj jou z Zloda 1 i 1 juiod Buryoye7 1 Yy i jueredsuej JOU jueredsuea A 1uejedsuej jou g zi od 1 f 1 1 i juiod Buiyoje 1 1 1 1 i i 1 i z juejedsuei jou juaredsuey X 1 1ueredsue jou 1 6 1 0d I L L 1 ta 1 1 i 1 L 1 os 19 X l Ik n Xuoo t NM X NO210M i l i i i i L 1 1 1 1 1 TOL E 1 1 i 1 lt gt i y 1 1 1 i sy 1 1 T 1 t 1 7 4 T i gau e 1 1 i n r su 00g gt 250087 y i reap i 1S4 eL z 1S4 Je L V 1 dlS4 T 1 1 i 1 i 1 1 i riti CU NUSH t HIA 1 1 f 1 i LNOLsY 1 i i i LINIS TOL8 lt aBseyo 12 sw Ps sn 8 zl TOL tzOL d 126 229
38. This allows adjusting the ST10F276 A D converter to the properties of the system Fast conversion can be achieved by programming the respective times to their absolute possible minimum This is preferable for scanning high frequency signals However the internal resistance of analog source and analog supply must be sufficiently low High internal resistance can be achieved by programming the respective times to a higher value or to the possible maximum This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible However the conversion rate in this case may be considerably lower The conversion times are programmed via the upper 4 bits of register ADCON Bit fields ADCTC and ADSTC define the basic conversion time and in particular the partition between the sample phase and comparison phases The table below lists the possible combinations The timings refer to the unit TCL where fopy 1 2TCL A complete conversion time includes the conversion itself the sample time and the time required to transfer the digital value to the result register Table 94 A D Converter programming ADCTC ADSTC Sample Comparison Extra Total conversion 00 00 TCL 120 TCL 240 TCL 28 TCL 388 00 01 TCL 140 TCL 280 TCL 16 TCL 436 ST10F276 Electrical characteristics Table 94 A D Converter programming continued
39. compare output 16 O TxD1 ASC1 Clock Data output Asynchronous Synchronous 17 229 Pin data ST10F276 Table 1 Pin description continued Symbol Pin Type Function 8 bit bidirectional I O port bit wise programmable for input or output via direction bit Programming an I O pin as input forces the corresponding output driver to 19 26 l O high impedance state Port 7 outputs can be configured as push pull or open drain drivers The input threshold of Port 7 is selectable TTL or CMOS The following Port 7 pins have alternate functions 19 O P70 POUTO PWMO channel 0 output P7 0 P7 7 22 O P7Z3 POUT3 PWMO channel 3 output 23 VO P7 4 CC28lO CAPCOM CC28 capture input compare output 26 VO P7 7 CC31IO CAPCOM CC31 capture input compare output 16 bit input only port with Schmitt Trigger characteristics The pins of Port 5 can 27 36 be the analog input channels up to 16 for the A D converter where P5 x equals 39 44 ANx Analog input channel x or they are timer inputs The input threshold of Port 5 is selectable TTL or CMOS The following Port 5 pins have alternate functions P5 0 P5 9 39 P5 10 T6EUD GPT2 timer T6 external up down control input P5 10 P5 15 40 P5 11 T5EUD GPT2 timer T5 external up down control input 41 P5 12 T6IN GPT2 timer T6 count input 42 P5 13 T5IN GPT2 timer T5 c
40. enabled by setting bit BDRSTEN in SYSCON register the RSTIN line is pulled low for the duration of the internal reset sequence Internal Reset Indication Output This pin is driven to a low level during RSTOUT 141 O j hardware software or watchdog timer reset RSTOUT remains low until the EINIT end of initialization instruction is executed Non Maskable Interrupt Input A high to low transition at this pin causes the CPU to vector to the NMI trap routine If bit PWDCFG 0 in SYSCON register when mE the PWRDN power down instruction is executed the NMI pin must be low in NMI 142 order to force the ST10F276 to go into power down mode If NMI is high and PWDCFG 0 when PWRDN is executed the part will continue to run in normal mode If not used pin NMI should be pulled high externally VAREF 37 A D converter reference voltage and analog supply VAGND 38 A D converter reference and analog ground RPD 84 _ Timing pin for the return from interruptible power down mode and synchronous asynchronous reset selection 17 46 n ee 72 82 93 Digital supply voltage 5V during normal operation idle and power down Vbp 109 126 modes 136 i It can be turned off when Stand by RAM mode is selected 18 45 55 71 Vss 83 94 Digital ground 110 127 139 1 8V decoupling pin a decoupling capacitor typical value of 10nF max 100nF Vig 56 eae must be connected between this pin and nearest Vas pin 22 229 ky ST1
41. or written e Write accesses must be made with addresses starting in segment 1 from 01 0000h regardless of the value of ROMS1 bit in SYSCON register e Read accesses are made in segment 0 or in segment 1 depending on the ROMS1 value e in BSL mode by default ROMS1 0 so the first 32 Kbytes of IFlash are mapped in segment 0 Example In default configuration to program address 0 the user must put the value 01 0000h in the FARL and FARH registers but to verify the content of the address 0 a read to 00 0000h must be performed ky 51 229 Bootstrap loader ST10F276 Note 5 2 6 52 229 Figure 8 Memory configuration after reset 16 Mbytes 16 Mbytes 16 Mbytes Ru oss Mp Pes ees it De i iB H NI N access to access to external external Depends on bus bus reset config 4 disabled 4 enabled i GA PO int stot int L int ee RAM imi ad RAM Il Ram E 2 0 0 0 exi Eco E ENDE HD P RR Wi 7 7 p 3 S access to 8 Sj access to i i 1 JL int FLASH i int FLASH i Depends on 5 g enabled 5 S enabled reset config IL nd Y Es al ee SH ads oe BSL mode active Yes POL 4 0 Yes POL 4 0 No POL 4 1 EA pin High Low According to application Code Terci rom Test FLASH access Test FLASH access User IFLASH access internal FLASH area D Bia Tete rom User IFLASH access User IFLASH acces
42. word byte operands 2 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV N Move negated direct bit to direct bit 4 BAND BOR BXOR AND OR XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH L Sins ind Hoc bia byte of bit addressable direct word 4 CMP B Compare word byte operands 2 4 CMPD1 2 Compare word data to GPR and decrement GPR by 1 2 2 4 CMPI1 2 Compare word data to GPR and increment GPR by 1 2 2 4 PRIOR Determine number of shift cycles to normalize direct word GPR and 2 store result in direct word GPR SHL SHR Shift left right direct word GPR 2 ROL ROR Rotate left right direct word GPR 2 ASHR Arithmetic sign bit shift right direct word GPR 2 MOV B Move word byte data 2 4 MOVBS Move byte operand to word operand with sign extension 2 4 MOVBZ Move byte operand to word operand with zero extension 2 4 JMPA JMPI JMPR Jump absolute indirect relative if condition is met 4 JMPS Jump absolute to a code segment 4 73 229 Central processing unit CPU ST10F276 Table 38 Standard instruction set summary continued Mnemonic Description Bytes J N B Jump relative if direct bit is not set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CE GALU Call absolute indirect relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL d
43. y Vav Oscillation voltage level Sine wave middle Vpp 2 025 Stable Vpp crystal 3 4 teruP Oscillator start up time ms Stable Vpp resonator 2 3 1 Not 100 tested guaranteed by design characterization 201 229 Electrical characteristics ST10F276 23 8 14 202 229 Figure 54 Crystal oscillator and resonator connection diagram ST10F276 ST10F276 Crystal uum CA mim m CA Resonator Table 99 Negative resistance absolute min value 125 C Vpp 4 5V Ca pF 12 15 18 22 27 33 39 47 4 MHz 4609 550 Q 675 Q 800 Q 8409 10002 11809 12000 8 MHz 380 Q 460 Q 540 Q 640 Q 580 Q 12 MHz 370Q 420 Q 360 Q The given values of Ca do not include the stray capacitance of the package and of the printed circuit board The negative resistance values are calculated assuming additional 5pF to the values in the table The crystal shunt capacitance Co the package and the stray capacitance between XTAL1 and XTAL2 pins is globally assumed equal to 4pF The external resistance between XTAL1 and XTAL2 is not necessary since already present on the silicon 32 kHz Oscillator specifications Conditions Vpp 5V 10 Ty 40 125 C Table 100 32 kHz Oscillator specifications Value Symbol Parameter Conditions Unit Min Typ Max 1 Start up 20 31 50 m g sci
44. 0 cece eee 203 External clock drive XTAL1 0 0 0 teas 204 Multiplexed bus with without R W delay and normal ALE 00000 eu 208 Multiplexed bus with without R W delay and extended ALE 0 005 209 Multiplexed bus with without R W delay normal ALE R WCS 05 210 Multiplexed bus with without R W delay extended ALE R W CS 211 Demultiplexed bus with without read write delay and normal ALE 214 Demultiplexed bus with without R W delay and extended ALE 215 Demultiplexed bus with ALE and RW CS 0 0 0 216 Demultiplexed bus no R W delay extended ALE R WCS 0 00008 217 CLKOUT and READY ss cirie niso i kA ia aok o aa a ae 219 External bus arbitration releasing the bus s illii 220 External bus arbitration regaining the bus liliis 221 SSC master timing 0 0 erre 223 SSC slave timing s c24 0000s cree reme Re eee OEE RR EGO REOR Ra SR Ee doge a e 225 144 pin plastic quad flat package liis 226 144 pin low profile quad flat package 10x10 1 0 cece eee 227 ST10F276 Introduction Introduction The ST10F276 is a derivative of the STMicroelectronics ST10 family of 16 bit single chip CMOS microcontrollers It combines high CPU performance up to 32 million instructions per second with high peripheral functionality and enhanced l O capabilities It also provides on chip high
45. 022A 022B 4 800 0 0 0 0 0681 0682 4 800 0 0 0 1 0456 0457 2 400 0 0 0 0 0D04 0D05 2 400 0 0 0 0 08AD 08AE 1 200 0 0 0 0 1A09 1A0A 1200 0 0 0 0 115B 115C 977 0 0 0 0 1FFB 1FFC 900 0 0 0 0 1724 1725 652 0 0 0 0 1FF2 1FF3 Note The deviation errors given in the Table 54 and Table 55 are rounded To avoid deviation errors use a Baud rate crystal providing a multiple of the ASCO sampling frequency 14 4 High speed synchronous serial interfaces The High Speed Synchronous Serial Interfaces SSCO and SSC1 provides flexible high speed serial communication between the ST10F276 and other microcontrollers microprocessors or external peripherals The SSCx supports full duplex and half duplex synchronous communication The serial clock signal can be generated by the SSCx itself master mode or be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices Transmission and reception of data is double buffered A 16 bit Baud rate generator provides the SSCx with a separate serial clock signal The serial channel SSCx has its own dedicated 16 bit Baud rate generator with 16 bit reload capability allowing Baud rate generation independent from the timers 96 229 ST10F276 Serial channels Table 56 and Table 57 list some possible Baud rates against the required rel
46. 1FFEh memory address for the signature reference The values for operandO operand1 and the signature should be such that the sequence shown in the figure below is successfully executed MOV Rx CheckBlocklAddr 00 0000h for standard reset ADD Rx CheckBlock2Addr 00 1FFCh for standard reset CPLB RLx 1s complement of the lower byte of the sum CMP Rx CheckBlock3Addr 00 1FFEh for standard reset 5 6 9 Alternate boot user software aspects User defined alternate boot code must start at 09 0000h A new SFR created on the ST10F276 indicates that the device is running in Alternate Boot Mode Bit 5 of EMUCON mapped at OxFEOAh is set when the alternate boot is selected by the reset configuration All the other bits are ignored when checking the content of this register to read the value of bit 5 This bit is a read only bit It remains set until the next software or hardware reset 5 6 10 EMUCON register EMUCON FEOAh 05h SFR Reset value xxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ABM E R ky 67 229 Bootstrap loader ST10F276 5 6 11 5 6 12 5 7 68 229 Table 36 ABM bit description Bit Function ABM Flag or TMOD3 0 Alternate Boot Mode is not selected by reset configuration on POL 5 4 1 Alternate Boot Mode is selected by reset configuration on POL 5 4 This bit is set if POL 5 4 01 during hardware reset ABM Int
47. 228 ST10F276 List of figures List of figures Figure 1 Logicsymbol isse m se eom eR on ER eae iog n edd 15 Figure 2 Pin configuration top view ssssseseeee RII I Iren 16 Figure3 Blockdiagram 2 00 ec ee lr hm mr 23 Figure 4 Flash modules structure 1 0 ee re 24 Figure 5 ST10F276 new standard bootstrap loader program flow 000e eee 49 Figure 6 Booting steps for ST10F276 000 cee 50 Figure 7 Hardware provisions to activate the BSL 0 0 c cee 51 Figure 8 Memory configuration after reset 00 kc ree 52 Figure 9 UART bootstrap loader sequence 0c teas 54 Figure 10 Baud rate deviation between host and ST10F276 0 00 c eee eee 56 Figure 11 CAN bootstrap loader sequence 00 0 c eens 57 Figure 12 Bit rate measurement over a predefined zero frame 000 eee 60 Figure 13 Reset boot sequence 0 eect tees 70 Figure 14 CPU Block Diagram MAC Unit not included 0 0000 a 71 Figure 15 MAC unitarchitecture llle mn 72 Figure 16 X Interrupt basic structure 0 0 Rr 80 Figure 17 Block diagram of GPT1 0 0 ccc rn 85 Figure 18 Block diagram of GPT2 0 0 rn 87 Figure 19 Block diagram of PWM module sees 88 Figure 20 Connection to single CAN bus via separate CAN transceivers 000 100 Figure 21 Connection to single CAN bus via common
48. 4 5 9 Access protection 0 cece e 40 4 55 10 Write protection zs xxu pe ER br aes aaa EP ERE ORE 41 4 5 11 Temporary unprotection 00 00 cee ee 41 46 Write operation examples 00 0220 eere 42 47 Write operation summary 000 2c es 44 5 Bootstrap loader ic aue cannes peo cone e ORUM I C ee ease eee 46 5 1 Selection among user code standard or alternate bootstrap 46 5 2 Standard bootstrap loader 2 22 incs sed prp a ER ea 47 5 2 1 Entering the standard bootstrap loader 0 00000 eee aee 47 5 2 2 ST10 configuration in BSL 2 aaaea aaea 48 5 2 8 Bootirig Steps cu ges dune cheese eee oa eee RUE NR ER DR RUE ee 50 5 2 4 Hardware to activate BSL 1 eee 50 5 2 5 Memory configuration in bootstrap loader mode 51 5 2 6 Loading the start up code cece eee 52 5 2 7 Exiting bootstrap loader mode 0 cee ee 53 5 2 8 Hardware requirements liliis lee 53 5 3 Standard bootstrap with UART RS232 or K Line 53 5 8 1 gcc 53 5 3 2 Entering bootstrap via UART 0 00 e eee eee 54 5 3 3 ST10 Configuration in UART BSL RS232 or K Line 55 5 3 4 Loading the start up code 0 eee 55 5 3 5 Choosing the baud rate for the BSL via UART 56 5 4 Standard bootstrap with CAN 02 000 e ee eee 57 5 4 1 FeatUtes cass ise genres d aves aed dee bar
49. 4 x MEMSIZE in Kbyte ODOh for ST10F276 832 Kbytes Internal memory type Oh ROM Less 1h M ROM memory MEMTYP 2h S Standard FLASH memory 3h H High Performance FLASH memory ST10F276 4h Fh reserved IDPROG F078h 3Ch ESFR Reset value 0040h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGVPP PROGVDD R R Table 76 IDPROG description Bit Function Programming VDD voltage VDD voltage when programming EPROM or FLASH devices is calculated using PROGVDD the following formula VDD 20 x PROGVDD 256 volts 40h for ST10F276 5V PROGVPP Programming VPP voltage no need of external VPP 00h All identification words are read only registers The values written inside different Identification Register bits are valid only after the Flash initialization phase is completed When code execution is started from internal memory pin EA held high during reset the Flash has completed its initialization so the bits of Identification Registers are immediately ready to be read out On the contrary when code execution is started from external memory pin EA held low during reset the Flash initialization is not yet completed so the bits of Identification Registers are not ready The user can poll bits 15 and 14 of IDMEM register When both bits are read low the Flash initialization is complete so all Identification Register bits are correct
50. 6 Central processing unit CPU llll l s 71 6 1 Multiplier accumulator unit MAC 0 000 c eee eee 72 6 2 Instruction set summary 00 00 ee 73 6 3 MAC coprocessor specific instructions 000 cee eee eee 75 7 External bus controller 2 2625 usce eR kk RERO A RR RE RUE es 76 8 Interrupt system cieecccciqusds kabeiavda eausa aa See he tae 77 8 1 X Peripheral interrupt llli ee 79 8 2 Exception and error traps list 00 0 eee ee 81 9 Capture compare CAPCOM units 82 10 General purpose timer unit 0 0c eee ee eee 84 DNE C un Mercer 84 10 2 GRT2 sausova RR Re E xAEPRR P ERE RE eas Ree Rs RR RA RR WA 86 11 PYM nodules 5n eee eee eek c 6 e nS CE QR ew Rn 88 12 Parallel ports 2 2isus 442p RR GERA SERERE E ee he in ERR Eos d s 89 12 1 nttod ctlOn 4o esee ERR Ear 9 Er me EET DER pes 89 122 I O s special features sce peed anc iy ERA adn RRECE AU RERRERAGC ENG eer 90 4 229 ky ST10F276 Contents 12 2 1 Open drain mode 0 00 ete 90 12 2 2 Inputthreshold control 0 0 ee 90 12 3 Alternate port functions isis ur RR RE REG AR RREXREREE senwn de 90 13 A D converter x satin i repens on nOn RU Q9 d n D RR io i RU Ree S A ae ese NN a 92 14 Serial Channels chido te arua Rb gode o UU ARCA RCR RF RD Re cs aa 94 14 4 Asynchronous synchronous serial interfaces 00 05 94 14 2 ASCxin asy
51. ADDAT FEAOh 50h A D converter result register 0000h WDT FEAEh 57h Watchdog timer register read only 0000h SOTBUF FEBOh 58h ebur 0 transmit buffer register 0000h SORBUF FEB2h 59h Serial channel 0 receive buffer register read only XXh SOBG FEB4h 5Ah com 0 baud rate generator reload 0000h PECCO FECOh 60h PEC channel 0 control register 0000h PECC1 FEC2h 61h PEC channel 1 control register 0000h PECC2 FEC4h 62h PEC channel 2 control register 0000h PECC3 FEC6h 63h PEC channel 3 control register 0000h PECC4 FEC8h 64h PEC channel 4 control register 0000h PECC5 FECAh 65h PEC channel 5 control register 0000h PECC6 FECCh 66h PEC channel 6 control register 0000h PECC7 FECEh 67h PEC channel 7 control register 0000h POL b FFOOh 80h PortO low register lower half of PORTO 00h POH b FFO2h 81h PortO high register upper half of PORTO 00h P1L b FFO4h 82h Port1 low register lower half of PORT1 00h P1H b FFO6h 83h Port1 high register upper half of PORT1 00h IDXO b FFO8h 84h MAC unit address pointer 0 0000h IDX1 b FFOAh 85h MAC unit address pointer 1 0000h BUSCONO b FFOCh 86h Bus configuration register O OxxOh MDC b FFOEh 87h CPU multiply divide control register 0000h PSW b FF10h 88h CPU program status word 0000h SYSCONb FF12h 89h CPU system configuration register OxxOh BUSCON1 b FF14h 8Ah Bus configuration register 1 0000h BUSCON2 b FF16h 8Bh Bus configuration register 2 0000h BUSCONS b FF18h 8Ch Bus configuration register 3 0000h B
52. IF2 mask 1 FFFFh CAN2IF2M2 EE46h CAN2 IF2 mask 2 FFFFh CAN2IF2MC EE4Ch CAN2 IF2 message control 0000h CAN2IP1 EEAOh CAN2 Interrupt pending 1 0000h CAN2IP2 EEA2h CAN2 Interrupt pending 2 0000h CAN2IR EEO8h CAN 2 Interrupt register 0000h CAN2MV1 EEBOh CAN2 Message valid 1 0000h CAN2MV2 EEB2h CAN2 Message valid 2 0000h CAN2ND1 EE90h CAN2 New data 1 0000h CAN2ND2 EE92h CAN2 New data 2 0000h CAN2SR EEO2h CAN2 Status register 0000h CAN2TR EEOAh CAN 2 Test register 00x0h CAN2TR1 EE80h CAN2 Transmission request 1 0000h CAN2TR2 EE82h CAN2 Transmission request 2 0000h I2CCCR1 EAO06h I2C Clock control register 1 0000h I2CCCR2 EAOEh I2C Clock control register 2 0000h I2CCR EAOOh I2C Control register 0000h I2CDR EAOCh I2C Data register 0000h I2COAR1 EAO8h I2C Own address register 1 0000h I2COAR2 EAOAh I2C Own address register 2 0000h I2CSR1 EA02h 12C Status register 1 0000h I2CSR2 EA04h 12C Status register 2 0000h RTCAH ED14h RTC Alarm register high byte XXXXh RTCAL ED12h RTC Alarm register low byte XXXXh RTCCON EDOOH RTC Control register 000Xh RTCDH EDOCh RTC Divider counter high byte XXXXh RTCDL EDOAh RTC Divider counter low byte XXXXh RTCH ED10h RTC Programmable counter high byte XXXXh 155 229 Register set ST10F276 Table 69 X Registers ordered by name continued Name Bec Description Reset value RTCL EDOEh RTC Programmable counter low by
53. MTTCx Memory tristate time control 0 1 wait state 1 No wait state BTYP ALECTLx External bus configuration 00 8 bit Demultiplexed Bus 01 8 bit Multiplexed Bus 10 16 bit Demultiplexed Bus 117 16 bit Multiplexed Bus Note For BUSCONO BTYP is defined via PORTO during reset ALE lengthening control 0 Normal ALE signal 1 Lengthened ALE signal BUSACTx Bus active control 0 External bus disabled 1 External bus enabled within the respective address window see ADDRSEL RDYENx Ready input enable 0 External bus cycle is controlled by bit field MCTC only 1 External bus cycle is controlled by the READY input signal RDYPOLx Ready active level control 0 Active level on the READY pin is low bus cycle terminates with a 0 on READY pin 1 Active level on the READY pin is high bus cycle terminates with a 1 on READY pin CSRENx Read chip select enable 0 The CS signal is independent of the read command RD 1 The CS signal is generated for the duration of the read command CSWENx Write chip select enable 0 The CS signal is independent of the write command WR WRL WRH 1 The CS signal is generated for the duration of the write command 169 229 Register set ST10F276 Note 1 BTYP bit 6 and 7 is set according to the configuration of the bit IG an
54. PLL synchronization if needed that is PO 15 13 changed Longer than 500ns to take into account of Input Filter on RSTIN pin Note 2 3 to 8 TCL depending on clock source selection Exit from asynchronous reset state When the RSTIN pin is pulled high the device restarts as already mentioned if internal FLASH is used the restarting occurs after the embedded FLASH initialization routine is completed The system configuration is latched from PortO ALE RD and WR WRL pins are driven to their inactive level The ST10F276 starts program execution from memory location 00 0000h in code segment O This starting location will typically point to the general initialization routine Timing of asynchronous Hardware Reset sequence are summarized in Figure 26 and Figure 27 Synchronous reset warm reset A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high level In order to properly activate the internal reset logic of the device the RSTIN pin must be held low at least during 4 TCL 2 periods of CPU clock refer also to Section 19 1 for details on minimum reset pulse duration The I O pins are set to high impedance and RSTOUT pin is driven low After RSTIN level is detected a short duration of a maximum of 12 TCL six periods of CPU clock elapses during which pending internal hold states are cancelled and the current internal access cycle if any is completed External bus cycle is aborted The internal pull down
55. RAM Real time clock and stand by mode When Stand by mode is entered turning off the main supply Vpp the Real Time Clock counting can be maintained running in case the on chip 32 kHz oscillator is used to provide the reference to the counter This is not possible if the main oscillator is used as reference for the counter Being the main oscillator powered by Vpp once this is switched off the oscillator is stopped 133 229 Power reduction modes ST10F276 20 3 4 Power reduction modes summary In the following Table 63 Power reduction modes summary a summary of the different Power reduction modes is reported Table 63 Power reduction modes summary 7 Oo o z gt E o Mode G B amp H E 2 N a gt d F E x m x y 5 T on on off on off run off biased biased e on on off on on run on biased biased on on off off off off off biased biased Power Down on on off off on on off biased biased on on off off on off on biased biased off on off off off off off biased off Stand by off on off off on off on biased off 134 229 ST10F276 Programmable output clock divider 21 Programmable output clock divider A specific register mapped on the XBUS allows to choose the division factor on the CLKOUT signal P3 15 This register is mapped on X Miscellaneous memory address range When CLKOUT function is enabled by setting bit CLKEN of register
56. Recommended operating conditions 00 ee eee 176 Thermal characteristics lile n 177 Package characteristics 0 00 ee 178 DC characteristics 2 0 6c rhe 178 Flash characteristic llli 183 Data retention characteristics llli 184 A D Converter programming 1 2 0 0 00 res 186 On chip clock generator selections liliis 196 Internal PLL divider mechanism 0000 cece ee rh 198 PLL lock unlock timing l lseselselse eR Rm m 201 Main oscillator specifications 0 2 0 ce II 201 Negative resistance absolute min value 1250C VDD 4 5V 004 202 32 kHz Oscillator specifications 0 eee 202 Minimum values of negative resistance module 00000 e eee eee 203 9 229 List of tables ST10F276 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 10 229 External clock drive timing 0 0 cece eee eae 204 Memory cycle variables 0 0 0 ete en 204 Multiplexed bus s cues meg dee bee dela e hx Yd xen e ed x 206 Demultiplexed bus lslsseeeeeeeee n rr 212 CEKOUT and READY sa x seu ed steer Rex ee rb cr ace ex e ae Fare 218 External bus arbitration 0 0 0 eee eae 220 Master mode issus sese sek ea ee ee ee ede ee a n Y edd ee 222 Slave mode sse Oia Pe eR Re ee MERI OA ae ee gee ds 224 Document revision history 0 0 ce eee
57. Round CoCMP Compare Accumulator with Operands CoLOAD 2 Load Accumulator with Operands CoMAC R u s rnd Un Signed Un Signed Multiply Accumulate amp Optional Round CoMACM R u s rnd Un Signed Un Signed Multiply Accumulate with Parallel Data Move amp Optional Round CoMAX CoMIN Maximum Minimum of Operands and Accumulator CoMOV Memory to Memory Move CoMUL u s rnd Un Signed Un Signed multiply amp Optional Round CoNEG rnd Negate Accumulator amp Optional Round CoNOP No Operation CoRND Round Accumulator CoSHL CoSHR Accumulator Logical Shift Left Right CoSTORE Store a MAC Unit Register CoSUB 2 R Substraction 75 229 External bus controller ST10F276 7 76 229 External bus controller All of the external memory accesses are performed by the on chip external bus controller The EBC can be programmed to single chip mode when no external memory is required or to one of four different external memory access modes e 16 18 20 24 bit addresses and 16 bit data demultiplexed e 16 18 20 24 bit addresses and 16 bit data multiplexed e 16 18 20 24 bit addresses and 8 bit data multiplexed e 16 18 20 24 bit addresses and 8 bit data demultiplexed In demultiplexed bus modes addresses are output on PORT1 and data is input output on PORTO or POL respectively In the multiplexed bus modes both addresses and data use PORTO for in
58. SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow Figure 14 CPU Block Diagram MAC Unit not included 2 Kbyte Internal RAM MDH MDL SP STKOV STKUN Mul Div HW Bit Mask Gen pj Omm A Sy z Bank Exec Unit General n Instr Ptr Purpose 4 4 Stage ALU Registers Pipeline J 16 Bit PSW eee RO SYSCON Barrel Shift CP 512 Kbyte Flash memory bonu BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 1 ADDRSEL Z ADDRSEL 4 Code Seg Ptr Data Pg Ptrs 71 229 Central processing unit CPU ST10F276 6 1 72 229 Multiplier accumulator unit MAC The MAC coprocessor is a specialized coprocessor added to the ST10 CPU Core in order to improve the performances of the ST10 Family in signal processing algorithms The standard ST10 CPU has been modified to include new addressing capabilities which enable the CPU to supply the new coprocessor with up to 2 operands per instruction cycle This new coprocessor so called MAC contains a fast multiply accumulate unit and a repeat unit The coprocessor instructions extend the ST10 CPU instruction set with multiply multiply accumulate 32 bit signed arithmetic operations Figure 15 MA
59. ST10F276 Register set 22 7 Flash registers ordered by name The following table lists by order of their names all FLASH control registers which are implemented in the ST10F276 Note that as they are physically mapped on the X Bus these registers are not bit addressable Table 71 Flash registers ordered by name Name Physical Description Reset value address FARH OxOOOE 0012 Flash address register High 0000h FARL OxOOOE 0010 Flash address register Low 0000h FCROH OxOOOE 0002 Flash control register O High 0000h FCROL OxOOOE 0000 Flash control register O Low 0000h FCR1H OxOOOE 0006 Flash control register 1 High 0000h FCR1L OxOOOE 0004 Flash control register 1 Low 0000h FDROH OxOOOE 000A Flash data register O High FFFFh FDROL OxOOOE 0008 Flash data register 0 Low FFFFh FDR1H OxOOOE OOOE Flash data register 1 High FFFFh FDR1L OxOOOE OOOC Flash data register 1 Low FFFFh FER OxOOOE 0014 Flash error register 0000h FNVAPRO OxOOOE DFB8 Flash nonvolatile access protection Reg 0 ACFFh FNVAPR1H 0x000E DEBE fears access protection Reg 1 FFFFh ENVAPRIL 0x000E DFBC s nonvolatile access protection Reg 1 FFFFh FNVWPIRH Ox000E DFB6 Flash nonvolatile protection Reg High FFFFh FNVWPIRL Ox000E DFB4 Flash nonvolatile protection Reg Low FFFFh FNVWPXRH Ox000E DFB2 Flash nonvolatile protection X Reg High FFFFh FNVWPXRL 0x000E DFBO Flash
60. STCL 19 tc tig SR ALE low to valid data in eH STOL AO tatte t tat te gp Address Unlatched cs 20 2t4 4TCL 30 1 to valid data in dc 2ta to tg SR Data hold after RD 0 B 0 H rising edge tig SR Data float after RD1 16 5 te 2TCL 8 5 tp t CC Data valid to WR 10 4 tc 2TCL 15 tc t CC Data hold after WR 4 tE 2TCL 8 5 tF ALE rising edge after tos CC RD WR 15 tf 2TCL 10 tf Address Unlatched CS t CC hold after RD WR 10 tf 2TCL 15 tf ST10F276 Electrical characteristics Table 104 Multiplexed bus continued Fcpu 40 MHz Variable CPU clock Symbol Parameter TCL 12 5ns 1 2 TCL 1 to 64 MHz t Min Max Min Max ALE falling edge to tag CC Latched CS 4 ta 10 ta 4 ta 10 ta Latched CS low to valid t39 SR data In 16 5 ic 2ta 3TCL 21 tc 2ta Latched CS hold after tao cc RD WR 27 te 3TCL 10 5 te ALE fall edge to RdCS t42 CC WCS with RW delay eae ALE fall edge to RdCS t CC WICS no RW delay 5 5 t 5 5 t Address float after t44 CC RdCS WrCS with RW 1 5 1 5 delay 1 Address float after tas CC RACS WrCS no RW 14 TCL 4 1 5 delay B RdCS t lid data P o valid data In tag SR with RW delay 4 tc 2TCL 21 tc RdCS to valid data In t47 SR no RW delay 16 5 tc 3TCL
61. SYSCON by default the CPU clock is output on P3 15 Setting bit XMISCEN of register XPERCON and bit XPEN of register SYSCON it is possible to program the clock prescaling factor in this way on P3 15 a prescaled value of the CPU clock can be output When CLKOUT function is not enabled bit CLKEN of register SYSCON cleared P3 15 does not output any clock signal even though XCLKOUTDIV register is programmed ky 135 229 Register set ST10F276 22 22 1 136 229 Register set This section summarizes all registers implemented in the ST10F276 and explains the description format used in the chapters to describe the function and layout of the SFRs For easy reference the registers except for GPRs are sorted in two ways Sorted by address to check which register is referenced by a given address Sorted by register name to find the location of a specific register Register description format Throughout the document the function and the layout of the different registers is described in a specific format The example below explains this format A word register is displayed as REG NAME A16h A8h SFR ESFR XBUS Reset value h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res write IN road std lis bitfield bitfield only bit only bit bit W RW R RW RW RW RW Table 64 Description Bit Function Explanation of bit fiel B
62. Short e lIf8 TCL 500ns Fcpy gt 8 MHz the reset event could be recognized either as Short or Long depending on the real filter delay between 50 and 500ns and the CPU frequency RSTF sampled High means Short reset RSTF sampled Low means Long reset Note that in case a Long Reset is recognized once the 8 TCL are elapsed the P0 15 13 pins becomes transparent so the system clock can be re configured The port returns not transparent 3 4TCL after the internal RSTF signal becomes high The same behavior just described occurs also when unidirectional reset is selected and RSTIN pin is held low till the end of the internal sequence exactly 1024TCL max 16 TCL and released exactly at that time When running with CPU frequency lower than 40 MHz the minimum valid reset pulse to be recognized by the CPU 4 TCL could be longer than the minimum analog filter delay 50ns so it might happen that a short reset pulse is not filtered by the analog input filter but on the other hand it is not long enough to trigger a CPU reset shorter than 4 TCL this would generate a FLASH reset but not a system reset In this condition the FLASH answers always with FFFFh which leads to an illegal opcode and consequently a trap event is generated Exit from synchronous reset state The reset sequence is extended until RSTIN level becomes high Besides it is internally prolonged by the FLASH initialization when EA 1 internal memory selected
63. The following Port 3 pins have alternate functions 65 P3 0 TOIN CAPCOM timer TO count input 66 O P3 1 T6OUT GPT2 timer T6 toggle latch output 67 P32 CAPIN GPT2 register CAPREL capture input 68 O P33 T3OUT GPT1 timer T3 toggle latch output 69 P3 4 T3EUD GPT1 timer T3 external up down control input 70 P23 5 T4N GPT1 timer T4 input for count gate reload capture 73 l P3 6 T3IN GPT1 timer T3 count gate input 74 P3 7 T2IN GPT1 timer T2 input for count gate reload capture 75 O P3 8 MRSTO SSCO0 master receiver slave transmitter I O 76 VO P3 9 MTSRO SSCO master transmitter slave receiver O I 77 O P3 10 TxDO ASCO clock data output asynchronous synchronous 78 VO P3 11 RxXDO ASCO data input asynchronous or I O synchronous 79 O P3 12 BHE External memory high byte enable signal WRH External memory high byte write strobe 80 VO P3 13 SCLKO SSCO master clock output slave clock input 81 O P315 CLKOUT System clock output programmable divider on CPU clock 19 229 Pin data ST10F276 Table 1 Pin description continued Symbol P4 0 P4 7 Pin 85 92 Type Function Port 4 is an 8 bit bidirectional I O port It is bit wise programmable for input or output via direction bit Programming an I O pin as input forces the corresponding output driver to high impedance state The input threshold is selectable TTL or CMOS Port 4 4 4 5 4 6 and 4 7 o
64. Then the code execution restarts The system configuration is latched from Porto and ALE RD and WR WRL pins are driven to their inactive level The ST10F276 starts program execution from memory location 00 0000h in code segment O This starting location will typically point to the general initialization routine Timing of synchronous reset sequence are summarized in Figures 28 and 29 where a Short Reset event is shown with particular highlighting on the fact that it can degenerate into Long Reset the two figures show the behavior when booting from internal or external memory respectively Figures 30 and 31 reports the timing of a typical synchronous Long Reset again when booting from internal or external memory 111 229 System reset ST10F276 112 229 Synchronous reset and RPD pin Whenever the RSTIN pin is pulled low by external hardware or as a consequence of a Bidirectional reset the RPD internal weak pull down is activated The external capacitance if any on RPD pin is slowly discharged through the internal weak pull down If the voltage level on RPD pin reaches the input low threshold around 2 5V the reset event becomes immediately asynchronous In case of hardware reset short or long the situation goes immediately to the one illustrated in Figure 26 There is no effect if RPD comes again above the input threshold the asynchronous reset is completed coherently To grant the normal completion of a synchronous reset th
65. TxEUD Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position The third position sensor signal TOPO can be connected to an interrupt input Timer T3 has output toggle latches TxXOTL which changes state on each timer over flow underflow The state of this latch may be output on port pins TXOUT for time out monitoring of external hardware components or may be used internally to clock timers T2 and T4 for high resolution of long duration measurements In addition to their basic operating modes timers T2 and T4 may be configured as reload or capture registers for timer T3 Table 46 GPT1 timer input frequencies resolutions and periods at 40 MHz Timer Input Selection T2l T31 TAI fcpu 40 MHz 000b 001b 010b 011b 100b 101b 110b 111b Aic 8 16 32 64 128 256 512 1024 factor 1 25 312 5 156 25 78 125 Input frequency 5MHz 2 5MHz MHz 625 kHz kHz kHz kHz 39 1 kHz ky ST10F276 General purpose timer unit Table 46 GPT1 timer input frequencies resolutions and periods at 40 MHz Timer Input Selection T2I T3l T4I fcpu 40 MHz 000b 001b 010b 011b 100b 101b 110b 111b Resolution 200ns 400ns 0 8us 1 6us 3 2us 6 4us 12 8us 25 6us Period 13 1ms 26 2ms 52 4ms 0 9 5997ms 419 4ms 838 9ms 1 678s maximum ms Table 47 GP
66. and the modules are reset to Read mode At following Power on an interrupted Flash write operation must be repeated 4 4 Registers description 4 4 1 Flash control register 0 low The Flash control register 0 low FCROL together with the Flash control register 0 high FCROH is used to enable and to monitor all the write operations for both the Flash modules The user has no access in write mode to the test Flash BOTF Besides test Flash block is seen by the user in Bootstrap mode only FCROL OxOE 0000 FCR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BSY1BSYOLOCK res BSY3 BSY2 res R R R R R Table 6 Flash control register 0 low Bit Function Bank 3 2 Busy XFLASH These bits indicate that a write operation is running on the corresponding Bank of XFLASH They are automatically set when bit WMS is set Setting Protection operation sets bit BSY2 since protection registers are in the Block B2 When these BSY 3 2 bits are set every read access to the corresponding Bank will output invalid data software trap 009Bh while every write access to the Bank will be ignored At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the Bank returns to read mode After a Program or Erase Resume these bits are automatically set again 28 229 Ti ST10F276 Internal Flash memory 4 4 2 Table 6 Flash co
67. clock 0 cee ee 199 23 8 11 Noise in the PLL loop ee ee 199 23 8 12 PLL lock unloCK pir 22 4 bee FG eee Ped RE itkewu e Lek 201 23 8 13 Main oscillator specifications llle 201 23 8 14 32 kHz Oscillator specifications llli esee 202 23 8 15 External clock drive XTAL1 0 0 cee ee 203 23 8 16 Memory cycle variables 0 0 c eee 204 23 8 17 External memory bus timing 0 c eee eee 205 23 8 18 Multiplexed bus 00 eee 206 23 8 19 Demultiplexed bus ssec ssi pariri eee 212 23 8 20 CLKOUT and READY sss rn 218 23 8 24 External bus arbitration llle 220 23 8 22 High speed synchronous serial interface SSC timing modes 222 24 Package information 000 c eee eee 226 25 Revision history aai ncs a8 gan weer tone ae NUS ON CR RC ee ees 228 ky 7 229 List of tables ST10F276 List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 8 229 Pin desc
68. constant depends on the external circuit In particular imposing that the transient is completed well before the end of sampling time Ts a constraint on R sizing is obtained 10 15 2 10 Ri Cg Cp Cpos Ts Of course R must also be sized according to the current limitation constraints in combination with Rg source impedance and Rr filter resistance Being that Cr is definitely bigger than Cp4 Cp and Cs then the final voltage V4 at the end of the charge transfer transient will be much higher than V4 The following equation must be respected charge balance assuming now Cg already charged at V44 Va2 Cs Cp4 Cpt Ce VaCet Va Cp Cp5 t Cg The two transients above are not influenced by the voltage source that due to the presence of the ReCr filter cannot provide the extra charge to compensate for the voltage drop on Cs with respect to the ideal source V4 the time constant ReCr of the filter is very high with respect to the sampling time Ts The filter is typically designed to act as anti aliasing see Figure 49 Calling f the bandwidth of the source signal and as a consequence the cut off frequency of the anti aliasing filter f according to Nyquist theorem the conversion rate fc must be at least 2fo meaning that the constant time of the filter is greater than or at least equal to twice the conversion period Tc Again the conversion period Tc is longer than the sampling time Ts which is just a portion of i
69. cycles until the pin returns to the selected active level ALE 98 Address latch enable output In case of use of external addressing or of multiplexed mode this signal is the latch command of the address lines 20 229 ST10F276 Pin data Table 1 Pin description continued Symbol Pin Type Function EA Vsrav 99 External access enable pin A low level applied to this pin during and after Reset forces the ST10F276 to start the program from the external memory space A high level forces ST10F276 to start in the internal memory space This pin is also used when Stand by mode is entered that is ST10F276 under reset and main Vpp turned off to bias the 32 kHz oscillator amplifier circuit and to provide a reference voltage for the low power embedded voltage regulator which generates the internal 1 8V supply for the RTC module when not disabled and to retain data inside the Stand by portion of the XRAM 16Kbyte It can range from 4 5 to 5 5V 6V for a reduced amount of time during the device life 4 0V when RTC and 32 kHz on chip oscillator amplifier are turned off In running mode this pin can be tied low during reset without affecting 32 kHz oscillator RTC and XRAM activities since the presence of a stable Vpp guarantees the proper biasing of all those modules POL O POL 7 POH O POH 1 POH 7 100 107 108 111 117 1 0 Two 8 bit bidirectional I O ports POL and POH bit wise
70. end of the Word Program operation SUSP Suspend This bit must be set to suspend the current Program Word or Double Word or Sector Erase operation in order to read data in one of the Sectors of the Bank under modification or to program data in another Bank The Suspend operation resets the Flash Bank to normal read mode automatically resetting bits BSYx When in Program Suspend the two Flash modules accept only the following operations Read and Program Resume When in Erase Suspend the modules accept only the following operations Read Erase Resume and Program Word or Double Word Program operations cannot be suspended during Erase Suspend To resume the suspended operation the WMS bit must be set again together with the selection bit corresponding to the operation to resume WPG DWPG SER Note It is forbidden to start a new Write operation with bit SUSP already set WMS Write mode start This bit must be set to start every write operation in the Flash modules At the end of the write operation or during a Suspend this bit is automatically reset To resume a suspended operation this bit must be set again It is forbidden to set this bit if bit ERR of FER is high the operation is not accepted It is also forbidden to start a new write program or erase operation by setting WMS high when bit SUSP of FCRO is high Resetting this bit by software has no effect 30 229 ST10F276 Internal Flash m
71. interrupt control 00h ADCON b FFAOh DOh A D converter control register 0000h ADDAT FEAOh 50h A D converter result register 0000h ADDAT2 FOAOh E 50h A D converter 2 result register 0000h ADDRSEL1 FE18h OCh Address select register 1 0000h ADDRSEL2 FE1Ah ODh Address select register 2 0000h ADDRSEL3 FE1Ch OEh Address select register 3 0000h ADDRSELA FE1Eh OFh Address select register 4 0000h ADEIC b FF9Ah CDh A D converter overrun error interrupt control register 00h BUSCONO b FFOCh 86h Bus configuration register 0 OxxOh BUSCON1 b FF14h 8Ah Bus configuration register 1 0000h BUSCON b FF16h 8Bh Bus configuration register 2 0000h BUSCONS b FF18h 8Ch Bus configuration register 3 0000h BUSCONA b FF1Ah 8Dh Bus configuration register 4 0000h CAPREL FE4Ah 25h GPT2 capture reload register 0000h CCO FE80h 40h CAPCOM register 0 0000h CCOIC b FF78h BCh CAPCOM register 0 interrupt control register 00h CC1 FE82h 41h CAPCOM register 1 0000h CC10 FE94h 4Ah CAPCOM register 10 0000h CC10IC b FF8Ch C6h CAPCOM register 10 interrupt control register 00h CC11 FE96h 4Bh CAPCOM register 11 0000h CC11IC b FF8Eh C7h CAPCOM register 11 interrupt control register 00h CC12 FE98h 4Ch CAPCOM register 12 0000h CC121C b FF90h C8h CAPCOM register 12 interrupt control register 00h CC13 FE9Ah 4Dh CAPCOM register 13 0000h CC13IC b FF92h C9h CAPCOM register 13 interrupt control register 00h CC14 FE9Ch 4Eh CAPCOM register 14 0000h 139 229
72. mode several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match several compare events per timer period are possible Interrupt only compare mode only one compare interrupt per timer period is Mode 2 generated Pin set 1 on match pin reset 0 on compare time overflow only one compare Mode 3 pon event per timer period is generated Double Register Two registers operate on one pin pin toggles on each compare match several Mode compare events per timer period are possible Table 44 CAPCOM timer input frequencies resolutions and periods at 40 MHz Timer Input Selection Txl fcpu 40 MHz 000b 001b 010b 011b 100b 101b 110b 111b Pre scal r for 8 16 32 64 128 256 512 1024 fcpu 312 5 156 25 78 125 39 1 Input Frequency 5MHz 2 5MHz 1 25MHz 625 kHz kHz kHz kHz kHz Resolution 200ns 400ns 0 8us 1 6us 3 2us 6 4us 12 8us 25 6us Period 13 1ms 26 2ms 52 4ms bn 209 7ms 419 4ms 838 9ms 1 678s Table 45 CAPCOM timer input frequencies resolutions and periods at 64 MHz Timer Input Selection Txl fopy 64 MHz 000b 001b 010b 011b 100b 101b 110b 111b Bre scale sar 8 16 32 64 128 256 512 1024 fopu Input Frequency 8MHz 4MHz 2MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz Resolution 125ns 250ns 0 5us 1 0us 2 0us 4 0us 8 0us 16 0us Period 8 2ms 16 4ms 32 8ms 65 5ms 131 1ms 262 1ms 524 3ms 1 049s 83 229 General purpose timer unit ST10F276 10 10 1
73. operations can be suspended in the following way FCROH 0x4000 Set SUSP in FCROH Then the operation can be resumed in the following way FCROH 0x0800 Set SER in FCROH FCROH 0x8000 Operation resume Before resuming a suspended Erase FCR1H FCR1L must be read to check if the Erase is already completed FCR1H FCR1L 0x0000 if Erase is complete Original setup of Select Operation bits in FCROH L must be restored before the operation resume otherwise the operation is aborted and bit RESER of FER is set 42 229 ky ST10F276 Internal Flash memory Erase suspend program and resume A Sector Erase operation can be suspended in order to program Word or Double Word another Sector Example Sector Erase of sector B3F1 of Bank 3 in XFLASH Module FCROH 0x0800 Set SER in FCROH FCR1H 0x0002 Set B3F1 FCROH 0x8000 Operation start Example Sector Erase Suspend FCROH 0x4000 Set SUSP in FCROH do Loop to wait for LOCK 0 and WMS 0 tmpl FCROL tmp2 FCROH while tmpl amp amp 0x0010 tmp2 amp amp 0x8000 Example Word Program of data 0x5555AAAA at address 0x0C5554 in XFLASH module FCROH amp OxBFFF Rst SUSP in FCROH FCROH 0x2000 Set WPG in FCROH FARL 0x5554 Load Add in FARL FARH 0x000C Load Add in FARH FDROL OxAAAA Load Data in FDROL FDROH 0x5555 Load Data in FDROH FCROH 0x8000 Operation start
74. operations for both the Flash modules The user has no access in write mode to the Test Flash BOTF Besides test Flash block is seen by the user in Bootstrap mode only FCROH 0x0E 0002 FCR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WMS SUSP WPG DWPG SER Reserved SPR SMOD Reserved RW RW RW RW RW RW RW Table 7 Flash control register 0 high Bit Function Select module If this bit is reset the Write Operation is performed on XFLASH Module if this bit is set the Write Operation is performed on IFLASH Module SMOD bit is automatically reset at the end of the Write operation SMOD Set protection This bit must be set to select the Set Protection operation The Set Protection operation allows to program Os in place of 1s in the Flash Non Volatile Protection SPR Registers The Flash Address in which to program must be written in the FARH L registers while the Flash Data to be programmed must be written in the FDROH L before starting the execution by setting bit WMS A sequence error is flagged by bit SEQER of FER if the address written in FARH L is not in the range OXOEDFBO OxOEDFBF SPR bit is automatically reset at the end of the Set Protection operation 29 229 Internal Flash memory ST10F276 Table 7 Flash control register 0 high continued Bit SER Function Sector erase This bit must be set
75. some numbers in the timing formulas become zero or negative which in most cases is not acceptable or meaningful In these cases the speed of the bus settings t4 tc and te must be correctly adjusted Note All External Memory Bus Timings and SSC Timings presented in the following tables are given by design characterization and not fully tested in production ky 205 229 Electrical characteristics ST10F276 23 8 18 206 229 Multiplexed bus VDD 5V 10 Vss OV TA 40 to 4125 C C 50pF ALE cycle time 6 TCL 2t tc te 75ns at 40 MHz CPU clock without wait states Table 104 Multiplexed bus Fcpu 40 MHz Variable CPU clock Symbol Parameter TCL 12 5ns 1 2 TCL 1 to 64 MHz Min Max Min Max ts CC ALE high time 4 tA TCL 8 5 t tg CC Address setup to ALE 1 5 4 t4 TCL 11 t t CC Address hold after ALE 4 t TCL 8 5 t4 ALE falling edge to RD ALE falling edge to RD tg cc WR 8 5 ta 8 5 ta no RW delay Address float after RD tio CC WR with Rw delay Address float after RD g J ty CC WR 18 5 TCL 6 no RW delay 1 RD WR low time t2 CC with RW delay 15 5 4 tc 2TCL 9 5 tc RD WR low time 7 tu CC no RW delay 28 tc STCL 9 5 tc ns RD to valid data in ta SR with RW delay 6 tc 2TCL 19 tc RD to valid data in t5 SR no RW delay 18 5 tc
76. speed single voltage Flash memory on chip high speed RAM and clock generation via PLL ST10F276 is processed in 0 18um CMOS technology The MCU core and the logic is supplied with a 5V to 1 8V on chip voltage regulator The part is supplied with a single 5V supply and I Os work at 5V The device is upward compatible with the ST10F269 device with the following set of differences e Flash control interface is now based on STMicroelectronics third generation of stand alone Flash memories M29F400 series with an embedded Program Erase Controller This completely frees up the CPU during programming or erasing the Flash e Only one supply pin ex DC1 in ST10F269 renamed into V48 on the QFP144 package is used for decoupling the internally generated 1 8V core logic supply Do not connect this pin to 5 0V external supply Instead this pin should be connected to a decoupling capacitor ceramic type typical value 10nF maximum value 100nF e The AC and DC parameters are modified due to a difference in the maximum CPU frequency e Anew Vpppin replaces DC2 of ST10F269 e EA pin assumes a new alternate functionality it is also used to provide a dedicated power supply see Vsrpy to maintain biased a portion of the XRAM 16Kbytes when the main Power Supply of the device Vpp and consequently the internally generated V4g is turned off for low power mode allowing data retention Vstpy voltage shall be in the range 4 5 5 5 Volt and a dedicate
77. t Bank 3 erase 128K Fs us i S not pre pragramma 2 2 6 2 9 0 preprogrammed 27 2 38 4 not preprogrammed l Module erase 512K 4 ie s preprog 7 6 23 5 34 7 preprogrammed 24 3 not preprogrammed X Module erase 320K 13 s s ds 4 9 14 8 21 8 preprogrammed 62 6 not preprogrammed Chip erase 832K 9 185 sen s preprog 12 0 37 9 56 1 preprogrammed Recovery from 6 power down tpp 40 ao Hs Program suspend _ latency 10 m Hs 183 229 Electrical characteristics ST10F276 Table 91 Flash characteristics continued Typical Maximum Parameter Ta 25 C Ta 125 C Unit Notes 0 cycles 0 cycles 100k cycles Erase suspend latency 6 30 30 us EUM request 20 20 20 me Min delay between ate two requests Set protection 40 170 170 us 1 The figures are given after about 100 cycles due to testing routines 0 cycles at the final customer 2 Word and Double Word Programming times are provided as average value derived from a full sector programming time Absolute value of a Word or Double Word Programming time could be longer than the provided average value 3 Bank Erase is obtained through a multiple Sector Erase operation setting bits related to all sectors of the Bank 4 Module Erase is obtained through a sequence of two Bank Erase operations since each module is composed by two Banks Chip Erase is obtained through a sequence of two Module Erase operations on l and X Modu
78. tenes 28 4 4 Registers description e sspes ked DRE aeee 28 4 4 1 Flash control register Olow 0 cee ee 28 4 4 2 Flash control register O high lille 29 4 4 3 Flash control register 1 low 0 cee eee 31 4 4 4 Flash control register 1 high 0 eee ee 32 4 4 5 Flash data register O low 0 cece eee 33 4 4 6 Flash data register O high 00 e eee eee 33 4 4 7 Flash data register 1 low 0 0 0 2c ee eee 33 4 4 8 Flash data register 1 high 0 0 cece eee eee 34 4 4 9 Flash address register low llle 34 4 4 10 Flash address register high 00 cee eee eee 35 44 11 Flash error register 0 e eee eee 35 4 4 12 XFlash interface control register llle 36 4 5 Protection strategy codes reb xa exo RE Ra Ried pecie d a 37 4 5 1 Protection registers 0 0 ee ern 37 4 5 2 Flash non volatile write protection X register low 37 4 5 8 Flash non volatile write protection X register high 38 4 5 4 Flash non volatile write protection register low 38 4 5 5 Flash non volatile write protection register high 38 4 5 6 Flash non volatile access protection register O 39 2 229 ky ST10F276 Contents 4 5 7 Flash non volatile access protection register 1low 39 4 5 8 Flash non volatile access protection register 1 high 40
79. the minimum zero voltage 00 to 01 Figure 46 see OFS Gain error Gain error is the deviation between the actual and ideal A D conversion characteristics when the digital output value changes from the 3FE to the maximum 3FF once offset error is sub tracted Gain error combined with offset error represents the so called full scale error Figure 46 OFS GE Quantization error Quantization error is the intrinsic error of the A D converter and is expressed as 1 2 LSB ky 187 229 Electrical characteristics ST10F276 Note 23 7 3 188 229 Nonlinearity error Nonlinearity error is the deviation between actual and the best fitting A D conversion charac teristics see Figure 46 Differential nonlinearity error is the actual step dimension versus the ideal one 1 LSBipea Integral nonlinearity error is the distance between the center of the actual step and the center of the bisector line in the actual characteristics Note that for integral nonlinearity error the effect of offset gain and quantization errors is not included Bisector characteristic is obtained drawing a line from 1 2 LSB before the first step of the real characteristic and 1 2 LSB after the last step again of the real characteristic Total unadjusted error The total unadjusted error TUE specifies the maximum deviation from the ideal character istic The number provided in the datasheet represents the maximum error with respect to the
80. this architecture Varer and Vagawp pins also represent the power supply of the analog cir cuitry of the A D converter There is an effective DC current requirement from the reference voltage by the internal resistor string in the R C DAC array and by the rest of the analog cir cuitry An external resistance on Vangr could introduce error under certain conditions For this rea sons series resistance is not advisable and more generally any series devices in the filter network should be designed to minimize the DC resistance Analog input pins To improve the accuracy of the A D converter analog input pins must have low AC imped ance Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective The capacitor should be as large as possible ideally infinite This capacitor contributes to attenuating the noise present on the input pin moreover its source charges during the sampling phase when the analog signal source is a high impedance source A real filter is typically obtained by using a series resistance with a capacitor on the input pin simple RC Filter The RC filtering may be limited according to the value of source imped ance of the transducer or circuit supplying the analog signal to be measured The filter at the input pins must be designed taking into account the dynamic characteristics of the input sig nal bandwidth Figure 47 A D converter input pins scheme EXTE
81. 000h XS1TBUF E908h XASC transmit buffer register 0000h XSSCBR E80Ah XSSC baud rate register 0000h XSSCCON E800h XSSC control register 0000h XSSCCONCLR E804h XSSC clear control register write only 0000h XSSCCONSET E802h XSSC set control register write only 0000h XSSCPORT E880h XSSC port control register 0000h XSSCRB E808h XSSC receive buffer XXXXh XSSCTB E806h XSSC transmit buffer 0000h 157 229 Register set ST10F276 22 6 X registers ordered by address The following table lists by order of their physical addresses all X Bus registers which are implemented in the ST10F276 Although also physically mapped on X Bus memory space the Flash control registers are listed in a separate section Note The X registers are not bit addressable Table 70 X registers ordered by address Name Physical Description Reset value address XSSCCON E800h XSSC control register 0000h XSSCCONSET E802h XSSC set control register write only 0000h XSSCCONCLR E804h XSSC clear control register write only 0000h XSSCTB E806h XSSC transmit buffer 0000h XSSCRB E808h XSSC receive buffer XXXXh XSSCBR E80Ah XSSC baud rate register 0000h XSSCPORT E880h XSSC port control register 0000h XS1CON E900h XASC control register 0000h XS1CONSET E902h XASC set control register write only 0000h XS1CONCLR E904h XASC clear control register write only 0000h XS1BG E906h XASC baud rate gene
82. 00h T3IC b FF62h Bih GPT1 timer 3 interrupt control register 00h T4IC b FF64h B2h GPT1 timer 4 interrupt control register 00h T5IC b FF66h B3h GPT2 timer 5 interrupt control register 00h T6IC b FF68h B4h GPT2 timer 6 interrupt control register 00h CRIC b FF6Ah B5h GPT2 CAPREL interrupt control register 00h SOTIC b FF6Ch B6h Serial channel 0 transmit interrupt control register 00h SORIC b FF6Eh B7h Serial channel 0 receive interrupt control register 00h SOEIC b FF70h B8h Serial channel 0 error interrupt control register 00h SSCTIC b FF72h B9h SSC transmit interrupt control register 00h SSCRIC b FF74h BAh SSC receive interrupt control register 00h SSCEIC b FF76h BBh SSC error interrupt control register 00h CCOIC b FF78h BCh CAPCOM register 0 interrupt control register 00h CC1IC b FF7Ah BDh CAPCOM register 1 interrupt control register 00h CC2IC b FF7Ch BEh CAPCOM register 2 interrupt control register 00h CC3IC b FF7Eh BFh CAPCOM register 3 interrupt control register 00h 151 229 Register set ST10F276 Table 68 Special function registers ordered by address continued Name harees addross Description velie CCAIC b FF80h COh CAPCOM register 4 interrupt control register 00h CC5IC b FF82h Cih CAPCOM register 5 interrupt control register 00h CC6IC b FF84h C2h CAPCOM register 6 interrupt con
83. 09h CPU system stack pointer register FCOOh STKOV FE14h OAh CPU stack overflow pointer register FAO00h STKUN FE16h OBh CPU stack underflow pointer register FCOOh ADDRSEL1 FE18h OCh Address select register 1 0000h ADDRSEL2 FE1Ah ODh Address select register 2 0000h ADDRSEL3 FE1Ch OEh Address select register 3 0000h ADDRSELA FE1Eh OFh Address select register 4 0000h PWO FE30h 18h PWM module pulse width register 0 0000h PW1 FE32h 19h PWM module pulse width register 1 0000h PW2 FE34h 1Ah PWM module pulse width register 2 0000h PW3 FE36h 1Bh PWM module pulse width register 3 0000h T2 FE40h 20h GPT1 timer 2 register 0000h T3 FE42h 21h GPT1 timer 3 register 0000h T4 FE44h 22h GPT1 timer 4 register 0000h T5 FE46h 23h GPT2 timer 5 register 0000h T6 FE48h 24h GPT2 timer 6 register 0000h ky ST10F276 Register set Table 68 Special function registers ordered by address continued Name address address Description value CAPREL FE4Ah 25h GPT2 capture reload register 0000h TO FE50h 28h CAPCOM timer 0 register 0000h T1 FE52h 29h CAPCOM timer 1 register 0000h TOREL FE54h 2Ah CAPCOM timer 0 reload register 0000h T1REL FE56h 2Bh CAPCOM timer 1 reload register 0000h MAL FE5Ch 2bEh MAC unit accumulator Low word 0000h MAH FE5Eh 2Fh MAC unit accumulator High word 0000h CC16 FE60h 30h CAPCOM register 16 0000h CC17 FE62h 31h
84. 0F276 Electrical characteristics 23 8 6 23 8 7 Therefore the timings given in this chapter refer to the minimum TCL This minimum value can be calculated by the following formula TCLmign7 1 fxTAL X DC min DC duty cycle For two consecutive TCLs the deviation caused by the duty cycle of fA is compensated so the duration of 2TCL is always 1 fyra The minimum value TCLmin is used only once for timings that require an odd number of TCLs 1 3 Timings that require an even number of TCLs 2 4 may use the formula 2TCL 1 fxTAL The address float timings in multiplexed bus mode t44 and t45 use the maximum duration of TCL TCLmax 1 fxtaL X DCmax instead of TCL pin Similarly to what happens for Prescaler Operation if the bit OWDDIS in SYSCON register is cleared the PLL runs on its free running frequency and delivers the clock signal for the Oscillator Watchdog If bit OWDDIS is set then the PLL is switched off Oscillator watchdog OWD An on chip watchdog oscillator is implemented in the ST10F276 This feature is used for safety operation with an external crystal oscillator available only when using direct drive mode with or without prescaler so the PLL is not used to generate the CPU clock multiplying the frequency of the external crystal oscillator This watchdog oscillator operates as following The reset default configuration enables the watchdog oscillator It can be disabled by setting the
85. 0F276 Functional description 3 Functional description The architecture of the ST10F276 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem The block diagram gives an overview of the different on chip components and the high bandwidth internal bus structure of the ST10F276 Figure 3 Block diagram 16 16 32 XFLASH IFLASH 16 320K fe 512K CPU Core and MAC Unit Cc ed 16 16 ay XRAM LL XRTC 48K Kn r Watchdog 16 PEC Kal XRAM 16 16 lt p 16K N Oscillator TRY 16 32kHz Ky XPWM o doo22c2c Oscillator XRAM ie 46 2K Interrupt Controller PEC KO Ko XASC PLL 16 16 XI2C Kc Ka XSSC 5V 1 8V 16 16 aoe eguiator XCAN1 KG Ka XCAN2 i 4 aS L 16 5m 8 o 8 TE a as a Oo zo lt o 8 8 z Q Q 16 ce l2 8991 s 9 a 46 S 99 T e lt a a ub i9 8 aa ae 8 es BRG BRG o n Port 6 Port 5 Port 3 Port 7 Port 8 84i 1613 154 ag EEGs ky 23 229 Internal Flash memory ST10F276 4 4 1 4 2 4 2 1 24 229 Internal Flash memory Overview The on chip Flash is composed by two matrix modules each one containing one array divi
86. 0x000E 0008 0x000E 000F 8 byte FAR Flash address registers 0x000E 0010 0x000E 0013 4 byte FER Flash error register OxO00E 0014 Ox000E 0015 2 byte pisvwx en Cer velat pioleciion Ox000E DFBO 0x000E DFB3 4 byte X register 16 bit ENIM 228 Don OURIUIS BIG ISO 0x000E DFB4 0x000E DFB7 4 byte UP U9 register ENVAPHO LO non velalle aterss 0x000E DFB8 0x000E DFB9 2 byte protection register O ENVAPER oon volatile access OxO00E DFBC 0x000E DFBF 4 byte protection register 1 XFICR XFlash interface control register Ox000E E000 0x000E E001 2 byte 4 2 3 Low power mode Note 4 3 Note The Flash modules are automatically switched off executing PWRDN instruction The consumption is drastically reduced but exiting this state can require a long time tpp Recovery time from Power Down mode for the Flash modules is anyway shorter than the main oscillator start up time To avoid any problem in restarting to fetch code from the Flash it is important to size properly the external circuit on RPD pin Power off Flash mode is entered only at the end of the eventually running Flash write operation Write operation The Flash modules have one single register interface mapped in the memory space of the XFlash module OxOE 0000 to OxOE 0013 All the operations are enabled through four 16 bit control registers Flash Control Register 1 0 High Low FCR1H L FCROH L Eight other 16 bit registers are used to store Flash Address
87. 1 2 ms for resonator oscillation PLL stabilization lt 10 2 ms for crystal oscillation PLL stabilization tS gt 2 1 ms for on chip VREG stabilization A Vpp RPD i RSTIN gt 50ns j 500ns RSTF T 7 After Filter 18 4 TCL 1 1 P0 15 13 transparent not t not t X P0 12 2 transparent l motx PO 1 0 not transparent not t X i ZTCL IBUS CS i Internal i i lt 1ms FLARST i RST A Latching point of PortO for system start up configuration 107 229 System reset ST10F276 Figure 25 Asynchronous power on RESET EA 0 2 1 2 ms for resonator oscillation 4 PLL stabilization 2 10 2 ms for crystal oscillation PLL stabilization 2 1 ms for on chip VREG stabilization 3 8 TCL n MITA gt 50ns 500 ns RSTF After Filter 3 4 TCL lt gt P0 15 13 transparent not t X P0 12 2 transparent PO 1 0 not transparent A Latching point of PortO for system start up configuration Note 1 3 to 8 TCL depending on clock source selection Hardware reset The asynchronous reset must be used to recover from catastrophic situations of the application It may be triggered by the hardware of the application Internal hard
88. 1 timer 4 interrupt control register 00h T5 FE46h 23h GPT2 timer 5 register 0000h T5CON b FF46h A3h GPT2 timer 5 control register 0000h T5IC b FF66h B3h GPT2 timer 5 interrupt control register 00h T6 FE48h 24h GPT2 timer 6 register 0000h T6CON b FF48h A4h GPT2 timer 6 control register 0000h T6IC b FF68h B4h GPT2 timer 6 interrupt control register 00h T7 F050h E 28h CAPCOM timer 7 register 0000h T78CON b FF20h 90h CAPCOM timer 7 and 8 control register 0000h T7IC b F17Ah E BDh CAPCOM timer 7 interrupt control register 00h T7REL F054h E 2Ah CAPCOM timer 7 reload register 0000h T8 F052h E 29h CAPCOM timer 8 register 0000h T8IC b F17Ch E BEh CAPCOM timer 8 interrupt control register 00h T8REL F056h E 2Bh CAPCOM timer 8 reload register 0000h TFR b FFACh D6h Trap flag register 0000h WDT FEAEh 57h Watchdog timer register read only 0000h WDTCONb FFAEh D7h Watchdog timer control register 00xxh XADRS3 FO1Ch E OEh XPER address select register 3 800Bh XPOIC b F186h E C3h See Section 8 1 00h XP1IC b F18Eh E C7h See Section 8 1 00h XP2IC b F196h E CBh See Section 8 1 00h XP3IC b F19Eh E CFh See Section 8 1 00h XPERCON F024h E 12h XPER configuration register 05h ZEROS b FF1Ch 8Eh Constant value 0 s register read only 0000h 145 229 Register set ST10F276 Note 22 4 146 229 1 2 3 The system configuration is selected during reset SYSCON reset value is 0000 Oxx0 x000 0000b Re
89. 10MHz 5MHz 2 5MHz MHz 625 kHz kHz kHz kHz Resolution 100ns 200ns 400ns 0 8us 1 6us 3 2us 6 4us 12 8us Period 6 55ms 13 1ms 26 2ms 52 4ms 104 8ms 209 7ms 419 4ms 838 9ms maximum Table 49 GPT2 timer input frequencies resolutions and periods at 64 MHz Timer Input Selection T5I T6l fc 64MHz 000b 001b 010b 011b 100b 101b 110b 111b Pre scaler factor 4 8 16 32 64 128 256 512 Input Freq 16MHz 8MHz 4MHz 2MHz 1kHz 500 kHz 250 kHz 128 kHz Resolution 62 5ns 125ns 250ns 0 5us 1 0us 2 0us 4 0us 8 0us Period 4 1ms 8 2ms 16 4ms 32 8ms 65 5ms 131 1ms 262 1ms 524 3ms maximum ST10F276 General purpose timer unit Figure 18 Block diagram of GPT2 T5EUD CPU Clock Interrupt Mode GPT2 Timer T5 gt Reauest TSIN Control m a Capture Interrupt gQ Request CAPREL Reload le Interrupt Request Tein G Toggle FF Mode GPT2 Timer T6 L T60TL 4l TeOUT CPU Clock 2n n 2 9 Control f U D to CAPCOM T6EUD Timers ky 87 229 PWM modules ST10F276 11 88 229 PWM modules Two pulse width modulation modules are available on ST10F276 standard PWMO and XBUS PWM1 They can generate
90. 2h Port 5 digital disable register 0000h P6 b FFCCh E6h Port 6 register 8 bit 00h P7 b FFDOh E8h Port 7 register 8 bit 00h P8 b FFD4h EAh Port 8 register 8 bit 00h PECCO FECOh 60h PEC channel 0 control register 0000h PECC1 FEC2h 61h PEC channel 1 control register 0000h PECC2 FEC4h 62h PEC channel 2 control register 0000h PECC3 FEC6h 63h PEC channel 3 control register 0000h PECC4 FEC8h 64h PEC channel 4 control register 0000h PECC5 FECAh 65h PEC channel 5 control register 0000h PECC6 FECCh 66h PEC channel 6 control register 0000h PECC7 FECEh 67h PEC channel 7 control register 0000h PICON b F1C4h E E2h Port input threshold control register 00h PPO FO38h E 1Ch PWM module period register 0 0000h PP1 FO3Ah E 1Dh PWM module period register 1 0000h PP2 FO3Ch E 1Eh PWM module period register 2 0000h PP3 FOSEh E 1Fh PWM module period register 3 0000h PSWb FF10h 88h CPU program status word 0000h PTO FO30h E 18h PWM module up down counter 0 0000h PT1 FO32h E 19h PWM module up down counter 1 0000h PT2 F034h E 1Ah PWM module up down counter 2 0000h PT3 FO36h E 1Bh PWM module up down counter 3 0000h PWO FESOh 18h PWM module pulse width register 0 0000h PW1 FE32h 19h PWM module pulse width register 1 0000h PW2 FE34h 1Ah PWM module pulse width register 2 0000h PW3 FE36h 1Bh PWM module pulse width register 3 0000h PWMCONO b FF30h 98h PWM module control register O 0000h 143 229 Register set ST10F276 144 229
91. 41 229 Register set ST10F276 142 229 Table 67 Special function registers ordered by address continued Name adaress address Description veils DP3 b FFC6h E3h Port 3 direction control register 0000h DP4 b FFCAh E5h Port 4 direction control register 00h DP6 b FFCEh E7h Port 6 direction control register 00h DP7 b FFD2h E9h Port 7 direction control register 00h DP8 b FFD6h EBh Port 8 direction control register 00h DPPO FEOOh 00h CPU data page pointer O register 10 bit 0000h DPP1 FEO2h 01h CPU data page pointer 1 register 10 bit 0001h DPP2 FEO4h 02h CPU data page pointer 2 register 10 bit 0002h DPP3 FEO6h 03h CPU data page pointer 3 register 10 bit 0003h EMUCON FEOAh 05h Emulation control register XXh EXICON b F1COh E EOh External interrupt control register 0000h EXISEL b F1DAh E EDh External interrupt source selection register 0000h IDCHIP F07Ch E 3Eh Device identifier register n is the device revision 114nh IDMANUF FO7Eh E 3Fh Manufacturer identifier register 0403h IDMEM FO7Ah E 3Dh On chip memory identifier register 30D0h IDPROG F078h E 3Ch Programming voltage identifier register 0040h IDXO b FFO8h 84h MAC unit address pointer 0 0000h IDX1 b FFOAh 85h MAC unit address pointer 1 0000h MAH FE5Eh 2Fh MAC unit accumulator High word 0000h MAL FE5Ch 2Eh MAC unit accumulator Low word 0000h MCW b FFDCh E
92. 500 ns 500 ns gt lt gt lt D RSTF l After Filter 7 13 4 TCL P0 15 13 X not transparent transparent not tX P0 12 2 X transparent not t X PO 1 0 X not transparent not t X l i i 3 8 TCL 8TCL i i gt lt ALE 102448 TCL i RST i i At this time RSTF is sampled LOW so it is LONG reset RSTOUT RPD 1 2004A Discharge P Vpro gt 2 5V Asynchronous Reset not entered Notes 1 If during the reset condition RSTIN low RPD voltage drops below the threshold voltage about 2 5V for 5V operation the asynchronous reset is then immediately entered 2 Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter refer to Section 21 1 3 3to 8 TCL depending on clock source selection Software reset A software reset sequence can be triggered at any time by the protected SRST software reset instruction This instruction can be deliberately executed within a program e g to leave bootstrap loader mode or on a hardware trap that reveals system failure On execution of the SRST instruction the internal reset sequence is started The microcontroller behavior is the same as for a synchronous short reset except that only bits P0 12 PO 8 are latched at the end of the reset sequence while previously latched bits PO 7 PO 2 are cleared that is written at 1 A Software reset is always taken as synchronous
93. 7 0068 19 200 0 9 1 4 0044 0045 9 600 0 2 0 6 OOCF 00DO 9 600 0 9 0 2 0089 008A 4 800 0 2 0 296 019F 01A0 4 800 0 4 0 296 0114 0115 2 400 0 2 0 0 0340 0341 2 400 0 1 0 2 022A 015B 1200 0 196 0 096 0681 0682 1200 0 1 0 1 0456 0457 600 0 0 0 0 0D04 0DO5 600 0 1 0 0 08AD 08AE 300 0 0 0 096 1A09 140A 300 0 096 0 096 115B 115C 245 0 0 0 0 1FE2 1FE3 163 0 0 0 0 1FF2 1FF3 Note The deviation errors given in the Table 52 and Table 53 are rounded To avoid deviation errors use a Baud rate crystal providing a multiple of the ASCO sampling frequency 14 3 ASCx in synchronous mode In synchronous mode data is transmitted or received synchronously to a shift clock which is generated by the ST10F276 Half duplex communication up to 8M Baud at 40 MHz of fepy is possible in this mode Table 54 ASC synchronous baud rates by reload value and deviation errors fcpy 40 MHz SOBRS 0 fcpy 40 MHz SOBRS 1 fcpy 40 MHz Baud Rate Baud Deviation Error Helene TANS Baud Rate Baud Deviation Error PEDRE ae hex hex 5 000 000 0 0 0 0 0000 0000 3 333 333 0 0 0 0 0000 0000 112 000 1 5 0 8 002B 002C 112 000 2 6 0 8 001C 001D 56 000 0 3 0 8 0058 0059 56 000 0 9 0 8 003A 003B 38 400 0 2 0 6 0081 0082 38 400 0 9 0 2 0055 0056 19 200 0 2 0 2 0103 0104 19 200 0 4
94. 7 to RPOH 5 bits are loaded only during a long hardware reset As pull up resistors are active on each Port POH pins during reset RPOH default value is FFh EXICON F1COh EOh ESFR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7ES EXIGES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXIOES RW RW RW RW RW RW RW RW 170 229 ky ST10F276 Register set Table 80 EXIxES bit description Bit Function 00 Fast external interrupts disabled Standard mode EXxIN pin not taken in account for entering exiting Power Down mode 01 Interrupt on positive edge rising Enter Power Down mode if EXiIN 0 exit if EXxIN 1 referred as high active EXIxES level x 7 0 10 Interrupt on negative edge falling Enter Power Down mode if EXiIN 1 exit if EXxIN 0 referred as low active level 11 Interrupt on any edge rising or falling Always enter Power Down mode exit if EXxIN level changed EXISEL F1DAh EDh ESFR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7SS EXI6SS EXI5SS EXIASS EXI3SS EXI2SS EXI1SS EXIOSS RW RW RW RW RW RW RW RW Table 81 EXISEL Bit Function External Interrupt x Source Selection x 7 0 00 Input from associated Port 2
95. B Bank 0 Flash 8 BOF8 0x0005 0000 0x0005 FFFF 64 KB Bank 0 Flash 9 BOF9 0x0006 0000 0x0006 FFFF 64 KB Bank 1 Flash 0 B1FO0 0x0007 0000 0x0007 FFFF 64 KB Bank 1 Flash 1 B1F1 0x0008 0000 0x0008 FFFF 64 KB Bank 2 Flash 0 B2F0 0x0009 0000 0x0009 FFFF 64 KB B2 Bank 2 Flash 1 B2F1 0x000A 0000 0x000A FFFF 64 KB Bank 2 Flash 2 B2F2 0x000B 0000 0x000B FFFF 64 KB ace BS Bank 3 Flash 0 B3F0 0x000C 0000 0x000C FFFF 64 KB Bank 3 Flash 1 B3F1 Ox000D 0000 0x000D FFFF 64 KB ky 25 229 Internal Flash memory ST10F276 Table 4 Flash modules sectorization write operations or with roms1 1 Bank Description Addresses Size oai Bank 0 Test Flash BOTF 0x0000 0000 0x0000 1FFF 8KB Bank 0 Flash 0 BOFO 0x0001 0000 0x0001 1FFF 8KB Bank 0 Flash 1 BOF1 0x0001 2000 0x0001 3FFF 8KB Bank 0 Flash 2 BOF2 0x0001 4000 0x0001 5FFF 8KB Bank 0 Flash 3 BOF3 0x0001 6000 0x0001 7FFF 8KB BO Bank 0 Flash 4 BOF4 0x0001 8000 0x0001 FFFF 32 KB Bank 0 Flash 5 BOF5 0x0002 0000 0x0002 FFFF 64 KB 32 bit I BUS Bank 0 Flash 6 BOF6 0x0003 0000 0x0003 FFFF 64 KB Bank 0 Flash 7 BOF7 0x0004 0000 0x0004 FFFF 64 KB Bank 0 Flash 8 BOF8 0x0005 0000 0x0005 FFFF 64 KB Bank 0 Flash 9 BOF9 0x0006 0000 0x0006 FFFF 64 KB Bank 1 Flash 0 B1FO0 0x0007 0000 0x0007 FFFF 64 KB 2 Bank 1 Flash 1 B1F1 0x0008 0000 0x0008 FFFF 64 K
96. B Bank 2 Flash 0 B2F0 0x0009 0000 0x0009 FFFF 64 KB B2 Bank 2 Flash 1 B2F1 0x000A 0000 0x000A FFFF 64 KB Bank 2 Flash 2 B2F2 0x000B 0000 0x000B FFFF 64 KB ae Bank 3 Flash 0 B3F0 0x000C 0000 0x000C FFFF 64 KB is Bank 3 Flash 1 B3F1 0x000D 0000 0x000D FFFF 64 KB The table above refers to the configuration when bit ROMS1 of SYSCON register is set When Bootstrap mode is entered Test Flash is seen and available for code fetches address 00 0000h User Flash is only available for read and write accesses Write accesses must be made with addresses starting in segment 1 from 01 0000h whatever ROMS 1 bit in SYSCON value Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value In Bootstrap mode by default ROMS1 0 so the first 32KBytes of IFlash are mapped in segment 0 Example In default configuration to program address 0 user must put the value 01 0000h in the FARL and FARH registers but to verify the content of the address 0 a read to 00 0000h must be performed Table 5 shows the control register interface composition this set of registers can be addressed by the CPU 26 229 ST10F276 Internal Flash memory Table 5 Control register interface Bank Description Addresses Size HIM bus size FCR1 0 Flash control registers 1 0 0x000E 0000 0x000E 0007 8 byte FDR1 0 Flash data registers 1 0
97. B P4 5 WaitDominantBit wait for end of stuff bit WaitRecessiveBit JNB P4 5 WaitRecessiveBit wait for 1st dominant bit Stuff bit CMPI1R1 5 Test if 5th stuff bit detected JMPR cc_NE WaitDominantBit No go back to count more BCLR PWMCON 0 Stop timer here the 5th stuff bit is detected PTO 29 Bit Time 25D and 4R Therefore the maximum error at the detection of the communication on CAN pin is 1 not taken 1 taken jumps 1 taken jump 1 bit set 6 6 CPU clock cycles The error at the detection for the 5 recessive bit is 1 taken jump 1 not taken jump 1 compare 1 bit clear 4 6 CPU cycles In the worst case the induced error is 6 CPU clock cycles so the polling could induce an error of 6 timer ticks Error induced by the baud rate calculation The content of the timer PTO counter corresponds to 29 bit times resulting in the following equation PTO 58 x BRP 1 X 1 Tseg1 Tseg2 where BRP Tseg1 and Tseg2 are the field of the CAN Bit Timing register The CAN protocol specification recommends to implement a bit time composed of at least 8 time quanta tq This recommendation is applied here Moreover the maximum bit time length is 25 tq To ensure precision the aim is to have the smallest Bit Rate Prescaler BRP and the maximum number of tq in a bit time This gives the following ranges for PTO according to BRP 8 lt 1 Tsegl Tseg2 x 25 464 x 1
98. BRP x PTO x 1450 x 1 BRP ky 61 229 Bootstrap loader ST10F276 62 229 Table 32 BRP and PTO values BRP PTO min PTO max Comments 0 464 1450 1 1451 2900 2 2901 4350 3 4351 5800 4 5801 7250 5 7251 8700 43 20416 63800 44 20880 65250 45 21344 66700 Possible timer overflow 63 X X The error coming from the measurement of the 29 bit is e 6 PTO It is maximal for the smallest BRP value and the smallest number of ticks in PTO Therefore 1 Max 1 29 To improve precision the aim is to have the smallest BRP so that the time quantum is the smallest possible Thus an error on the calculation of time quanta in a bit time is minimal In order to do so the value of PTO is divided into ranges of 1450 ticks In the algorithm PTO is divided by 1451 and the result is BRP The calculated BRP value is then used to divide PTO in order to have the value of 7 Tseg1 Tseg2 A table is made to set the values for Tseg1 and Tseg2 according to the value of 1 Tseg Tseg2 These values of Tseg1 and Tseg2 are chosen in order to reach a sample point between 70 and 80 of the bit time During the calculation of 1 Tseg1 Tseg2 an error es can be introduced by the division This error is of 1 time quantum maximum To compensate for any possible error on bit rate the Re Synchronization Jump Width is fixed to 2 time quanta ST10F276 Bootstrap loader
99. C unit architecture r GPR Pointers IDXO Pointer IDX1 Pointer QRO GPR Offset Register QR1 GPR Offset Register QXO IDX Offset Register QX1 IDX Offset Register Repeat Unit Interrupt Controller ST10 CPU Control Unit Operand 1 Operand 2 16x16 signed unsigned Multiplier Concatenation Sign Extend Scaler Oh 08000h 40 40 40 40 Flags MAE 8 bit Left Right Shifter ST10F276 Central processing unit CPU 6 2 Instruction set summary The Table 38 lists the instructions of the ST10F276 The detailed description of each instruction can be found in the ST10 Family Programming Manual Table 38 Standard instruction set summary Mnemonic Description Bytes ADD B Add word byte operands 2 4 ADDC B Add word byte operands with Carry 2 4 SUB B Subtract word byte operands 2 4 SUBC B Subtract word byte operands with Carry 2 4 MUL U Un Signed multiply direct GPR by direct GPR 16 16 bit 2 DIV U Un Signed divide register MDL by direct GPR 16 16 bit 2 DIVL U Un Signed long divide reg MD by direct GPR 32 16 bit 2 CPL B Complement direct word byte GPR 2 NEG B Negate direct word byte GPR 2 AND B Bit wise AND word byte operands 2 4 OR B Bit wise OR word byte operands 2 4 XOR B Bit wise XOR
100. C24h XPWM module period register 2 0000h XPP3 EC26h XPWM module period register 3 0000h XPTO EC10h XPWM module up down counter 0 0000h XPT1 EC12h XPWM module up down counter 1 0000h XPT2 EC14h XPWM module up down counter 2 0000h 156 229 ST10F276 Register set a Table 69 X Registers ordered by name continued Physical ar Name address Description Reset value XPT3 EC16h XPWM module up down counter 3 0000h XPWO EC30h XPWM module pulse width register 0 0000h XPW1 EC32h XPWM module pulse width register 1 0000h XPW2 EC34h XPWM module pulse width register 2 0000h XPW3 EC36h XPWM module pulse width register 3 0000h XPWMCONO ECOOh XPWM module control register 0 0000h XPWMCONOCLR ECO8h id module clear control reg O write 0000h XPWMCONOSET ECO6h ia module set control register O write 0000h XPWMCON 1 ECO2h XPWM module control register 1 0000h XPWMCONICLR ECOCh Aa module clear control reg O write 0000h XPWMCON1SET ECOAh i module set control register O write 0000h XPWMPORT EC80h XPWM module port control register 0000h XS1BG E906h XASC baud rate generator reload register 0000h XS1CON E900h XASC control register 0000h XS1CONCLR E904h XASC clear control register write only 0000h XS1CONSET E902h XASC set control register write only 0000h XS1PORT E980h XASC port control register 0000h XS1RBUF E90Ah XASC receive buffer register 0
101. CAN transceivers 05 100 Figure 22 Connection to two different CAN buses e g for gateway application 101 Figure 23 Connection to one CAN bus with internal Parallel Mode enabled 101 Figure 24 Asynchronous power on RESET EA 1 000 0c eee eee 107 Figure 25 Asynchronous power on RESET EA 0 20 000 eee ee 108 Figure 26 Asynchronous hardware RESET EA 1 0 000 c eee eee 109 Figure 27 Asynchronous hardware RESET EA 0 00 0c eee eee 110 Figure 28 Synchronous short long hardware RESET EA 1 0000 c eee eee 113 Figure 29 Synchronous short long hardware RESET EA 0 0000 c eee eee 114 Figure 30 Synchronous long hardware RESET EA 1 0 000 c eee eee 115 Figure 31 Synchronous long hardware RESET EA 0 000 c eee eee 116 Figure 32 SW WDT unidirectional RESET EA 1 0 117 Figure 33 SW WDT unidirectional RESET EA 0 0 0 0 eee 118 Figure 34 SW WDT bidirectional RESET EA 1 0 000 cee eee 120 Figure 35 SW WDT bidirectional RESET EA 0 00006 c eee 121 Figure 36 SW WDT bidirectional RESET EA 0 followed by a HW RESET 122 Figure 37 Minimum external reset circuitry 0 2 llle 123 Figure 38 System reset circuit liii rh 124 Figure 39 Internal simplified reset circuitry llli 124 Figure 40 Example of software or watchdog bidirection
102. CAPCOM register 17 0000h CC18 FE64h 32h CAPCOM register 18 0000h CC19 FE66h 33h CAPCOM register 19 0000h CC20 FE68h 34h CAPCOM register 20 0000h CC21 FE6Ah 35h CAPCOM register 21 0000h CC22 FE6Ch 36h CAPCOM register 22 0000h CC23 FE6Eh 37h CAPCOM register 23 0000h CC24 FE70h 38h CAPCOM register 24 0000h CC25 FE72h 39h CAPCOM register 25 0000h CC26 FE74h 3Ah CAPCOM register 26 0000h CC27 FE76h 3Bh CAPCOM register 27 0000h CC28 FE78h 3Ch CAPCOM register 28 0000h CC29 FE7Ah 3Dh CAPCOM register 29 0000h CC30 FE7Ch 3Eh CAPCOM register 30 0000h CC31 FE7Eh 3Fh CAPCOM register 31 0000h CCO FE80h 40h CAPCOM register 0 0000h CC1 FE82h 41h CAPCOM register 1 0000h CC2 FE84h 42h CAPCOM register 2 0000h CC3 FE86h 43h CAPCOM register 3 0000h CC4 FE88h 44h CAPCOM register 4 0000h CC5 FE8Ah 45h CAPCOM register 5 0000h CC6 FE8Ch 46h CAPCOM register 6 0000h CC7 FE8Eh 47h CAPCOM register 7 0000h CC8 FE90h 48h CAPCOM register 8 0000h CC9 FE92h 49h CAPCOM register 9 0000h CC10 FE94h 4Ah CAPCOM register 10 0000h 149 229 Register set ST10F276 Table 68 Special function registers ordered by address continued Name duress addross Description velie CC11 FE96h 4Bh CAPCOM register 11 0000h CC12 FE98h 4Ch CAPCOM register 12 0000h CC13 FE9Ah 4Dh CAPCOM register 13 0000h CC14 FE9Ch 4Eh CAPCOM register 14 0000h CC15 FE9Eh 4Fh CAPCOM register 15 0000h
103. Ch CAPCOM Register 13 CC13IR CC1SIE CC13INT 00 0074h 1Dh CAPCOM Register 14 CC14IR CC14IE CC14INT 00 0078h 1Eh CAPCOM Register 15 CC15IR CC15IE CC15INT 00 007Ch 1Fh CAPCOM Register 16 CC16IR CC16IE CC16INT 00 00COh 30h CAPCOM Register 17 CC17IR CC17IE CC17INT 00 00C4h 31h CAPCOM Register 18 CC18IR CC18IE CC18INT 00 00C8h 32h CAPCOM Register 19 CC19IR CC19IE CC19INT 00 00CCh 33h CAPCOM Register 20 CC20IR CC20IE CC20INT 00 00DOh 34h CAPCOM Register 21 CC21IR CC21IE CC21INT 00 00D4h 35h CAPCOM Register 22 CC22IR CC22lE CC22INT 00 00D8h 36h CAPCOM Register 23 CC23IR CC23IE CC23INT 00 00DCh 37h CAPCOM Register 24 CC24IR CC24IE CC24INT 00 00E0h 38h CAPCOM Register 25 CC25IR CC25IE CC25INT 00 00E4h 39h CAPCOM Register 26 CC26IR CC26IE CC26INT 00 00E8h 3Ah CAPCOM Register 27 CC27IR CC27IE CC27INT 00 00ECh 3Bh CAPCOM Register 28 CC28IR CC28IE CC28INT 00 00FOh 3Ch CAPCOM Register 29 CC29IR CC29IE CC29INT 00 0110h 44h CAPCOM Register 30 CC30IR CC30IE CC30INT 00 0114h 45h CAPCOM Register 31 CC31IR CC31IE CC31INT 00 0118h 46h CAPCOM Timer 0 TOIR TOIE TOINT 00 0080h 20h CAPCOM Timer 1 T1IR THE T1INT 00 0084h 21h CAPCOM Timer 7 T7IR T7IE T7INT 00 00F4h 3Dh CAPCOM Timer 8 T8IR T8IE T8INT 00 00F8h 3Eh GPT1 Timer 2 T2IR T2IE T2INT 00 0088h 22h GPT1 Timer 3 T3IR TSIE T3INT 00 008Ch 23h GPT1 Timer 4 T4IR TAIE TAINT 00 0090h 24h GPT2 Timer 5 T5IR T5IE T5INT 00 0094h 25h ky ST10F276 Interrupt system 8 1 Table 40 Interrupt sources conti
104. Eh MAC unit control word 0000h MDC b FFOEh 87h CPU multiply divide control register 0000h MDH FEOCh 06h CPU multiply divide register High word 0000h MDL FEOEh 07h CPU multiply divide register Low word 0000h MRW b FFDAh EDh MAC unit repeat word 0000h MSW b FFDEh EFh MAC unit status word 0200h ODP2 b F1C2h E E1h Port2 open drain control register 0000h ODP3 b F1C6h E E3h Port3 open drain control register 0000h ODP4 b F1CAh E E5h Port4 open drain control register 00h ODP6 b F1CEh E E7h Port6 open drain control register 00h ODP7 b FiD2h E E9h Port7 open drain control register 00h ODP8 b FiD6h E EBh Port8 open drain control register 00h ONES b FF1Eh 8Fh Constant value 1 s register read only FFFFh POH b FFO2h 81h PortO high register upper half of PORTO 00h ST10F276 Register set Table 67 Special function registers ordered by address continued Name address address Description value POL b FFOOh 80h PortO low register lower half of PORTO 00h P1H b FFO6h 83h Port1 high register upper half of PORT1 00h P1L b FFO4h 82h Port1 low register lower half of PORT1 00h P2 b FFCOh EOh Port 2 register 0000h P3 b FFC4h E2h Port 3 register 0000h P4 b FFC8h E4h Port 4 register 8 bit 00h P5 b FFA2h Dih Port 5 register read only XXXXh P5DIDIS b FFA4h D
105. F5h CPU general purpose word register R5 UUUUh R6 CP 1 F6h CPU general purpose word register R6 UUUUh R7 CP 1 F7h CPU general purpose word register R7 UUUUh R8 CP 1 F8h CPU general purpose word register R8 UUUUh R9 CP 1 F9h CPU general purpose word register R9 UUUUh R10 CP 20 FAh CPU general purpose word register R10 UUUUh R11 CP 22 FBh CPU general purpose word register R11 UUUUh R12 CP 24 FCh CPU general purpose word register R12 UUUUh R13 CP 26 FDh CPU general purpose word register R13 UUUUh R14 CP 28 FEh CPU general purpose word register R14 UUUUh R15 CP 30 FFh CPU general purpose word register R15 UUUUh The first 8 GPRs R7 RO may also be accessed bytewise Other than with SFRs writing to a GPR byte does not affect the other byte of the respective GPR The respective halves of the byte accessible registers have special names Table 66 General purpose registers GPRs bytewise addressing Physical 8 bit T Reset Mame address address Description value RLO CP 0 FOh CPU general purpose byte register RLO UUh RHO CP 1 F1h CPU general purpose byte register RHO UUh RL1 CP 2 F2h CPU general purpose byte register RL1 UUh RH1 CP 3 F3h CPU general purpose byte register RH1 UUh RL2 CP 4 F4h CPU general purpose byte register RL2 UUh RH2 CP 5 F5h CPU general purpose byte register RH2 UUh 137 229
106. FF74h BAh SSC receive interrupt control register 00h SSCTB FOBOh E 58h SSC transmit buffer write only 0000h SSCTIC b FF72h B9h SSC transmit interrupt control register 00h STKOV FE14h OAh CPU stack overflow pointer register FAOOh STKUN FE16h OBh CPU stack underflow pointer register FCOOh SYSCONb FF12h 89h CPU system configuration register OxxOh TO FE5Oh 28h CAPCOM timer 0 register 0000h TO1CON b FF50h A8h CAPCOM timer 0 and timer 1 control register 0000h TOIC b FF9Ch CEh CAPCOM timer 0 interrupt control register 00h TOREL FE54h 2Ah CAPCOM timer 0 reload register 0000h T1 FE52h 29h CAPCOM timer 1 register 0000h T1IC b FF9Eh CFh CAPCOM timer 1 interrupt control register 00h T1REL FE56h 2Bh CAPCOM timer 1 reload register 0000h 4 ST10F276 Register set Table 67 Special function registers ordered by address continued Name dares address Description ves T2 FE40h 20h GPT1 timer 2 register 0000h T2CON b FF40h AOh GPT1 timer 2 control register 0000h T21C b FF60h BOh GPT1 timer 2 interrupt control register 00h T3 FE42h 21h GPT1 timer 3 register 0000h T3CON b FF42h Ath GPT1 timer 3 control register 0000h T3IC b FF62h Bih GPT1 timer 3 interrupt control register 00h T4 FE44h 22h GPT1 timer 4 register 0000h T4CON b FF44h A2h GPT1 timer 4 control register 0000h T4IC b FF64h B2h GPT
107. FLASH W3P 1 0 These bits if programmed at 0 disable any write access to the sectors of Bank 3 XFLASH Flash non volatile write protection register low FNVWPIRL 0x0E DFB4 NVR Delivery value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WOP9WOP8WOP7WOPeWOPSWOPAWOPSWOP2WOP 1WOPO RW RW RW RW RW RW RW RW RW RW Table 21 Flash non volatile write protection I register low Bit Function Write Protection Bank 0 Sectors 9 0 IFLASH WOP 9 0 These bits if programmed at 0 disable any write access to the sectors of Bank 0 IFLASH Flash non volatile write protection register high FNVWPIRH 0x0E DFB6 NVR Delivery value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved W1P1W1P0 RW RW Table 22 Flash non volatile write protection register high Bit Function Write Protection Bank 1 Sectors 1 0 IFLASH W1P 1 0 These bits if programmed at 0 disable any write access to the sectors of Bank 1 IFLASH ST10F276 Internal Flash memory 4 5 6 Flash non volatile access protection register 0 Due to ST10 architecture the XFLASH is seen as external memory this made impossible to access protect it from real external memory or internal RAM FNVAPRO 0x0E DFB8 NVR Delivery value ACFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DBGP ACCP R
108. Flash memory ST10F276 4 5 8 4 5 9 40 229 Flash non volatile access protection register 1 high FNVAPR1H 0x0E DFBE NVR Delivery value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9 PEN8 PEN7 PENG PENS PEN4 PENS PEN2 PEN1 PENO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 25 Flash non volatile access protection register 1 high Bit Function Protections Enable 15 0 PEN15 0 If bit PENx is programmed at 0 and bit PDSx 1 is erased at 1 the action of bit ACCP is enabled again Bit PENx can be programmed at 0 only if bit PDSx has already been programmed at 0 Access protection The Flash modules have one level of access protection access to data both in Reading and Writing if bit ACCP of FNVAPRO is programmed at 0 the IFlash module become access protected data in the IFlash module can be read written only if the current execution is from the IFlash module itself Protection can be permanently disabled by programming bit PDSO of FNVAPR1H in order to analyze rejects Allowing PDSO bit programming only when ACCP bit is programmed guarantees that only an execution from the Flash itself can disable the protections Protection can be permanently enabled again by programming bit PENO of FNVAPR1L The action to disable and enable again Access Protections in a permanent
109. N bit set Context pointer CP FA004 Register STKUN FA004 Stack pointer SP FA404 Register STKOV FC00 Register BUSCONO acc to startup config XPERCON 002Dy XRAM1 2 XFlash CAN1 enabled 1 In Bootstrap modes standard or alternate ROMEN bit 10 of SYSCON is always set regardless of EA pin level BYTDIS bit 9 of SYSCON is set according to data bus width selection via PortO configuration 2 BUSCONDO is initialized with 0000h external bus disabled if pin EA is high during reset If pin EA is low during reset BUSACTO bit 10 and ALECTLO bit 9 are set enabling the external bus with lengthened ALE signal BTYP field bit 7 and 6 is set according to PortO configuration Even if the internal IFLASH is enabled a code cannot be executed from it As the XFlash is needed XPERCON register is configured by the ABM loader code and bit XPEN of SYSCON is set However as long as the EINIT instruction is not executed and it is not in the bootstrap loader code the settings can be modified To do this perform the following steps e Copyin DPRAM a function that will disable the XPeripherals by clearing XPEN in SYSCON register enabled the needed XPeripherals by writing the correct value in XPERCON register set XPEN bit in SYSCON return to calling address e Call the function from XFlash The changing of the XPERCON value cannot be executed from the XFlash because the XFlash is disabled by the clearing of X
110. OWDDIS bit 4 of SYSCON register When the OWD is enabled the PLL runs at its free running frequency and it increments the watchdog counter On each transition of external clock the watchdog counter is cleared If an external clock failure occurs then the watchdog counter overflows after 16 PLL clock cycles The CPU clock signal is switched to the PLL free running clock signal and the oscillator watchdog Interrupt Request is flagged The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin Only a hardware reset or bidirectional Software Watchdog reset can switch the CPU clock source back to direct clock input When the OWD is disabled the CPU clock is always the external oscillator clock in Direct Drive or Prescaler Operation and the PLL is switched off to decrease consumption supply current Phase locked loop PLL For all other combinations of pins P0 15 13 POH 7 5 during reset the on chip phase locked loop is enabled and it provides the CPU clock see Table 95 The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0 15 13 fcpy fytaL X F With every F th transition of fxta the PLL circuit synchronizes the CPU clock to the input clock This synchronization is done smoothly so the CPU clock frequency does not change abruptly 197 229 Electrical characteristics ST10F276 23 8 8 198 229 Due to this adaptation t
111. PEN bit in SYSCON Watchdog As for standard boot the Watchdog timer remains disabled during Alternate Boot Mode In case a Watchdog reset occurs a software reset is generated See note from Section 5 2 7 concerning software reset Exiting alternate boot mode Once the ABM mode is entered it can be exited only with a software or hardware reset See note from Section 5 2 7 concerning software reset ky ST10F276 Bootstrap loader 5 6 7 Alternate boot user software If the rules described previously are respected that is mapping of variables disabling of interrupts exit conditions predefined vectors in Block 0 of Bank 2 Watchdog usage then users can write the software they want to execute in this mode starting from 09 0000h 5 6 8 User alternate mode signature integrity check The behavior of the Alternate Boot Mode is based on the computing of a signature between the content of two memory locations and a comparison with a reference signature This requires that users who use Alternate Boot have reserved and programmed the Flash memory locations according to User mode signature 00 0000h memory address of operandod for the signature computing 00 1FFCh memory address of operand1 for the signature computing 00 1FFEh memory address for the signature reference Alternate mode signature 09 0000h memory address of operandod for the signature computing 09 1FFCh memory address of operand for the signature computing 09
112. PORTO latched configuration for the different reset events PORTO Ei E e E v o X Pin is sampled o d o o o Uo olol dlg Pini amp sg 23 t 3 228 8 Pin is not sampled 8 3 9 Clo 5 52 x lt o o t0 o o Q 3 9 z S ac tlel S 5 6 lt p o o rto N Z 29 ron ow mye Sample event I IT IT I r r ri rm dj d a d d Z EERIE ER E ERIE EE E IERIE IR Software Reset IXIX XXX X X j 1 1 5 Watchdog Reset b IXIXIXIX X XiX 1 1 1 1 Synchronous Short Hardware Reset IXIXIXIXIXIXXIXXIX XIX x Synchronous Long Hardware Reset XXX X X XX XIXIX XXIX xX xX xX Asynchronous Hardware Reset XXX X X XX XXIX XXIX xXx Asynchronous Power On Reset XXX X X XX XXIX XXIX xX xX xX 128 229 ky ST10F276 System reset Figure 42 PORTO bits latched into the different registers after reset PORTO H7 H6 H5 H4 H3 H2 H1 HO L7 L6 L5 L4 L3 L2 L1 LO T T T T T T T CLKCFG SALSEL CSSEL WRC BUSTYP BSL Res ADP EMU L L I L L L L RPOH CLKCFG SALSEL CSSEL WRC Bootstrap Loader Internal Control Logic v v v Clock Port 4 Port 6 Generator Logic Logic EA VSTBY POL POL 7 Ld l SYSCON y BUSCONO ROMEN BYTDIS WRCFG horn a BTYP L 10 9 8 7 10 9 7 6 129 229 Power reduction modes ST10F276 20 Note 20 1 20 2 130 229
113. RNAL CIRCUIT INTERNAL CIRCUIT SCHEME V us Channel Sampling Source Filter Current Limiter election quer TOt ven aee PED POS EOS UE fer Po mes cms men e et om det mm i o o o o l Rs H RF Ho Ri 4 Rsw Rap SS a e co co n 1 VA T Ce i Cet Cp Cs n I lI H I Rs Source impedance Re Filter resistance Cr Filter capacitance RL Current limiter resistance Rsw Channel selection switch impedance Rap Sampling switch impedance Cp Pin capacitance two contributions CP1 and CP2 Cs Sampling capacitance 189 229 Electrical characteristics ST10F276 Input leakage and external circuit The series resistor utilized to limit the current to a pin see R in Figure 47 in combination with a large source impedance can lead to a degradation of A D converter accuracy when input leakage is present Data about maximum input leakage current at each pin is provided in the datasheet Electri cal Characteristics section Input leakage is greatest at high operating temperatures and in general decreases by one half for each 10 C decrease in temperature Considering that for a 10 bit A D converter one count is about 5mV assuming Varer 5V an input leakage of 100nA acting though an R 50kQ of external resistance leads to an error of exactly one count bmV if the resistance were 100kQ the error would become two counts Eventual additional leakage due to external clamping diodes must also be taken into acc
114. SACTO bit 10 and ALECTLO bit 9 are set enabling the external bus with lengthened ALE signal BTYP field bit 7 and 6 is set according to PortO configuration Other than after a normal reset the watchdog timer is disabled so the bootstrap loading sequence is not time limited Pin TxDO is configured as output so the ST10F276 can return the acknowledge byte Even if the internal IFLASH is enabled a code cannot be executed from it Loading the start up code After sending the acknowledge byte the BSL enters a loop to receive 32 bytes via ASCO These bytes are stored sequentially into locations 00 FA40 through 00 FA5F of the IRAM allowing up to 16 instructions to be placed into the RAM area To execute the loaded code the BSL then jumps to location 00 FA40H that is the first loaded instruction The bootstrap loading sequence is now terminated however the ST10F276 remains in BSL mode The initially loaded routine will most probably load additional code or data as an average application is likely to require substantially more than 16 instructions This second receive loop may directly use the pre initialized interface ASCO to receive data and store it in arbitrary user defined locations This second level of loaded code may be e the final application code e another more sophisticated loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data e acode sequence to change the system conf
115. STIN Memory mapping The ST10F276 has the same memory mapping for standard boot mode and for alternate boot mode e Test Flash Mapped from 00 0000h The Standard Bootstrap Loader can be started by executing a jump to the address of this routine JMPS 00 xxxx address to be defined User Flash The User Flash is divided in two parts The IFLASH visible only for memory reads and memory writes no code fetch and the XFLASH visible for any ST10 access memory read memory write and code fetch e All ST10F276 XRAM and Xperipherals modules can be accessed if enabled in XPERCON register The alternate boot mode can be used to reprogram the whole content of the ST10F276 User Flash except Block 0 in Bank 2 where the alternate boot is mapped into Interrupts The ST10 interrupt vector table is always mapped from address 00 0000h As a consequence interrupts are not allowed in Alternate Boot Mode all maskable and nonmaskable interrupts must be disabled 65 229 Bootstrap loader ST10F276 5 6 4 5 6 5 Note 5 6 6 Note 66 229 ST10 configuration in alternate boot mode When the ST10F276 enters BSL mode via CAN the configuration shown in Table 35 is automatically set values that deviate from the normal reset values are marked in bold Table 35 ST10 configuration in alternate boot mode Function or register Access Notes Watchdog timer Disabled Register SYSCON 0404H XPE
116. T1 timer input frequencies resolutions and periods at 64 MHz Timer Input Selection T2l T31 TAI fcpu 64 MHz 000b 001b 010b 011b 100b 101b 110b 111b Pie sealer 8 16 32 64 128 256 512 1024 factor Input Freq 8MHz 4MHz 2MHz 1 kHz 500 kHz 250 kHz 128 kHz 64 kHz Resolution 125ns 250ns 0 5us 1 0us 2 0us 4 0us 8 0us 16 0us Period 8 2ms 16 4ms 32 8ms 65 5ms 131 1ms 262 1ms 524 3ms 1 049s maximum Figure 17 Block diagram of GPT1 T2EUD _ QUID Interrupt GPT1 Timer T2 Request CPU Clock T2 Mode it T2IN O Control Pelad Capture VAN CPU Clock 2n n 3 10 T3 g Mode GPT1 Timer T3 TON Control uot T3EUD Capture me T4 Reload Interrupt TAIN 5 Mode Request CPU Clock Control 2n n 3 10 gt GPT1 Timer T4 gt Interrupt Request T4EUD _ U D 85 229 General purpose timer unit ST10F276 10 2 86 229 GPT2 The GPT2 module provides precise event control and time measurement It includes two timers T5 T6 and a capture reload register CAPREL Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals The coun
117. Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 ky GPT2 timer input frequencies resolutions and periods at 64 MHz 86 PWM unit frequencies and resolutions at 40 MHz CPU clock 4 88 PWM unit frequencies and resolutions at 65 MHz CPU clock 04 88 ASC asynchronous baud rates by reload value and deviation errors CPU 40 MHz 94 ASC asynchronous baud rates by reload value and deviation errors CPU 64 MHz 95 ASC synchronous baud rates by reload value and deviation errors fCPU 40 MHz 95 ASC synchronous baud rates by reload value and deviation errors CPU 64 MHz 96 Synchronous baud rate and reload values CPU 40 MHZ 20005 97 Synchronous baud rate and reload values ICPU 64 MHZ 20005 97 WDTREL reload value CPU 40 MHz 0 000 nh 103 WDTREL reload value CPU 64 MHZ 2 0000 ee 103 Reset event definition 0 0 eee 104 Reset eve
118. The only exception could be the Real Time Clock if opportunely programmed and one of the two oscillator circuits as a consequence either the main or the 32 kHz on chip oscillator When Real Time Clock module is used when the device is in Power Down mode a reference clock is needed In this case two possible configurations may be selected by the user application according to the desired level of power reduction e A 32 kHz crystal is connected to the on chip low power oscillator pins XTAL3 XTAL4 and running In this case the main oscillator is stopped when Power Down mode is entered while the Real Time Clock continue counting using 32 kHz clock signal as reference The presence of a running low power oscillator is detected after the Power on this clock is immediately assumed if present or as soon as it is detected as reference for the Real Time Clock counter and it will be maintained forever unless specifically disabled via software e Only the main oscillator is running XTAL1 XTAL2 pins In this case the main oscillator is not stopped when Power Down is entered and the Real Time Clock continue counting using the main oscillator clock signal as reference There are two different operating Power Down modes protected mode and interruptible mode ky ST10F276 Power reduction modes Note 20 2 1 20 2 2 20 3 Before entering Power Down mode by executing the instruction PWRDN bit VREGOFF in XMISC register
119. USCONA b FF1Ah 8Dh Bus configuration register 4 0000h ZEROS b FF1Ch 8Eh Constant value 0 s register read only 0000h 150 229 ST10F276 Register set Table 68 Special function registers ordered by address continued Name quress address Description value ONES b FF1Eh 8Fh Constant value 1 s register read only FFFFh T78CON b FF20h 90h CAPCOM timer 7 and 8 control register 0000h CCM4 b FF22h 91h CAPCOM mode control register 4 0000h CCM5 b FF24h 92h CAPCOM mode control register 5 0000h CCM6 b FF26h 93h CAPCOM mode control register 6 0000h CCM7 b FF28h 94h CAPCOM mode control register 7 0000h PWMCONO b FF30h 98h PWM module control register O 0000h PWMCON1 b FF32h 99h PWM module control register 1 0000h T2CON b FF40h AOh GPT1 timer 2 control register 0000h T3CON b FF42h Ath GPT1 timer 3 control register 0000h T4CON b FF44h A2h GPT1 timer 4 control register 0000h T5CON b FF46h A3h GPT2 timer 5 control register 0000h T6CON b FF48h A4h GPT2 timer 6 control register 0000h TO1CON b FF50h A8h CAPCOM timer 0 and timer 1 control register 0000h CCMO b FF52h A9h CAPCOM mode control register O 0000h CCM1 b FF54h AAh CAPCOM mode control register 1 0000h CCM2 b FF56h ABh CAPCOM mode control register 2 0000h CCM3 b FF58h ACh CAPCOM mode control register 3 0000h T21C b FF60h BOh GPT1 timer 2 interrupt control register
120. W RW Table 23 Flash non volatile access protection register 0 Bit Function Access Protection ACCP This bit if programmed at 0 disables any access read write to data mapped inside IFlash Module address space unless the current instruction is fetched from one of the two Flash modules Debug Protection This bit if erased at 1 allows to by pass all the protections using the Debug features DBGP through the Test Interface If programmed at 0 on the contrary all the debug features the Test Interface and all the Flash Test Modes are disabled Even STMicroelectronics will not be able to access the device to run any eventual failure analysis 4 5 7 Flash non volatile access protection register 1 low FNVAPRI1L 0x0E DFBC NVR Delivery value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PDS9 PDS8 PDS7 PDS6 PDS5 PDS4 PDS3 PDS2 PDS1 PDSO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 24 Flash non volatile access protection register 1 low Bit Function Protections Disable 15 0 If bit PDSx is programmed at 0 and bit PENx is erased at 1 the action of bit ACCP is PDS 15 0 disabled Bit PDSO can be programmed at 0 only if bits DBGP and ACCP have already been programmed at 0 Bit PDSx can be programmed at 0 only if bit PENx 1 has already been programmed at O 39 229 Internal
121. WDTCON each time before the watchdog timer is serviced The Table 58 and Table 59 show the watchdog time range for 40 MHz and 64 MHz CPU clock respectively Table 58 WDTREL reload value fcpy 40 MHz Prescaler for fcp 40 MHz Reload value in WDTREL 2 WDTIN 0 128 WDTIN 1 FFh 12 8us 819 2us 00h 3 277ms 209 7ms Table 59 WDTREL reload value fcpy 64 MHz Prescaler for fcp 64 MHz Reload value in WDTREL 2 WDTIN 0 128 WDTIN 1 FFh 8us 512us 00h 2 048ms 131 1ms 103 229 System reset ST10F276 19 19 1 104 229 System reset System reset initializes the MCU in a predefined state There are six ways to activate a reset state The system start up configuration is different for each case as shown in Table 60 Table 60 Reset event definition RPD e Reset Source Flag Status Conditions Power on reset PONR Low Power on Asynchronous Hardware reset Low tRSTIN gt 1 Synchronous Long Hardware LHWR tasriN gt 1032 12 TCL max 4 TCL High reset 500ns tastin gt max 4 TCL 500ns Sy chtenote Shon Hardware dieu High tasty 1032 12 TCL max 4 TCL reset 500ns Watchdog Timer reset WDTR 3 WDT overflow Software reset SWR 3 SRST instruction execution 1 RSTIN pulse should be longer than 500ns Filter and than settling time for configuration of Porto 2 See next Section 19 1 fo
122. XEMUS EB7Ch XBUS Reset value xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XEMU3 15 0 Ww 175 229 Electrical characteristics ST10F276 23 23 1 Note 23 2 176 229 Electrical characteristics Absolute maximum ratings Table 86 Absolute maximum ratings Symbol Parameter Value Unit Vpp Voltage on Vpp pins with respect to ground Vas Vstpy Voltage on Vergy pin with respect to ground Vss dete Vangr Voltage on Varer pin with respect to ground Vss 0 3 to Vpp 0 3 V Vacnp Voltage on Vagnp pin with respect to ground Vss Vss Vio Voltage on any pin with respect to ground Vss 0 5 to Vpp 0 5 lov Input current on any pin during overload condition t10 Itov Absolute sum of all input currents during overload condition 75 Tst Storage temperature 65 to 150 C ESD ESD susceptibility human body model 2000 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability During overload conditions Viy gt Vpp or Vin lt Vss the voltage on pins with respect to ground Vss must not exceed the values defined by the Absolute Maximum Ratings
123. able 42 Trap priorities n Trap Trap Vector Trap Trap Exception Condition Flag Vector Location Number Priority Reset Functions Hardware Reset RESET 00 0000h 00h III Software Reset RESET 00 0000h 00h Hi Watchdog Timer Overflow RESET 00 0000h 00h Ill Class A Hardware Traps Non Maskable Interrupt NMI NMITRAP 00 0008h 02h II Stack Overflow STKOF STOTRAP 00 0010h 04h I Stack Underflow STKUF STUTRAP 00 0018h 06h I Class B Hardware Traps Undefined Opcode UNDOPC BTRAP 00 0028h OAh l MAC Interruption MACTRP BTRAP 00 0028h OAh l Protected Instruction Fault PRTFLT BTRAP 00 0028h OAh l Illegal word Operand Access ILLOPA BTRAP 00 0028h OAh l Illegal Instruction Access ILLINA BTRAP 00 0028h OAh l Illegal External Bus Access ILLBUS BTRAP 00 0028h OAh l Reserved 002Ch 003Ch OBh OFh Any Current Software Traps Any TRAP Instruction 0090n O dei 00h 7Fh CPU in steps of 4h Priority Note AIl the class B traps have the same trap number and vector and the same lower priority compare to the class A traps and to the resets Each class A traps has a dedicated trap number and vector They are prioritized in the second priority level The resets have the highest priority level and the same trap number The PSW ILVL CPU priority is forced to the highest level 15 when these exceptions are serviced 81 229 Capture compare CAPCOM units ST10F276 9 82 229 Capture compare CAPCOM units The ST10F276 has t
124. al reset EA 1 00 0000 125 Figure 41 Example of software or watchdog bidirectional reset EA 0 20 0005 126 Figure 42 PORTO bits latched into the different registers after reset 0000000 129 Figure 43 External RC circuitry on RPD pin 0 00 eee 131 Figure 44 Port2 test mode structure 2 eee 182 Figure 45 Supply current versus the operating frequency RUN and IDLE modes 182 Figure 46 A D conversion characteristic lille 188 Figure 47 A D converter input pins scheme 0 000 eee sere 189 Figure 48 Charge sharing timing diagram during sampling phase 00 0 eae 190 ky 11 229 List of figures ST10F276 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 12 229 Anti aliasing filter and conversion rate l i eee 192 Input output waveforms llle hr ras 194 Float waveforms isses la eu egy dae ex a y he RR dr iR d RR Rd 194 Generation mechanisms for the CPU clock 00 00 cece eee 195 ST10F276 PLL jitter cete se lerem Rey xa agde ae eger aee 200 Crystal oscillator and resonator connection diagram 0000 cece eee eee 202 32 kHz crystal oscillator connection diagram 20
125. al reset enable 0 RSTIN pin is an input pin only SW Reset or WDT Reset have no effect on this BDRSTEN pin 1 RSTIN pin is a bidirectional pin This pin is pulled low during internal reset sequence XTAL1 signal The PLL is turned off to reduce power supply current Oscillator watchdog disable control 0 Oscillator Watchdog OWD is enabled If PLL is bypassed the OWD monitors OWDDIS XTAL1 activity If there is no activity on XTAL1 for at least 1 us the CPU clock is switched automatically to PL s base frequency from 750 kHz to 3 MHz 1 OWD is disabled If the PLL is bypassed the CPU clock is always driven by Power down mode configuration control 0 Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low otherwise the instruction has no effect To exit Power Down Mode PWDCFG an external reset must occur by asserting the RSTIN pin 1 Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast external interrupt EXxIN pins are in their inactive level Exiting this mode can be done by asserting one enabled EXxIN pin or with external reset Chip select configuration control CSCFG 0 Latched Chip Select lines CSx changes 1 TCL after rising edge of ALE 1 Unlatched Chip Select lines CSx changes with rising edge of ALE 167 229 Register set ST10F276 Table 77 SYSCON de
126. all not exceed 1mA in case of both dynamic and static injection 7 The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channels with the overload current within the different specified ranges for both positive and negative injection current 8 Referto scheme shown in Figure 47 Conversion timing control When a conversion starts first the capacitances of the converter are loaded via the respec tive analog input pin to the current analog input voltage The time to load the capacitances is referred to as sample time Next the sampled voltage is converted in several successive steps into a digital value which corresponds to the 10 bit resolution of the ADC During these steps the internal capacitances are repeatedly charged and discharged via the Varner pin The current that must be drawn from the sources for sampling and changing charges depends on the duration of each step because the capacitors must reach their final voltage level within the given time at least with a certain approximation However the maximum cur rent that a source can deliver depends on its internal resistance The time that the two different actions take during conversion sampling and converting can be programmed within a certain range in the ST10F276 relative to the CPU clock The abso lute time consumed by the different conversion steps is therefore independent from the gen eral speed of the controller
127. an trigger a fast external interrupt via EXISEL register of port 2 and wake up the ST10 chip when running power down mode Using the RTCOFF bit of RTCCON register the user may switch off the clock oscillator when entering the power down mode The last function implemented in the RTC is to switch off the main on chip oscillator and the 32 kHz on chip oscillator if the ST10 enters the Power Down mode so that the chip can be fully switched off if RTC is disabled At power on and after Reset phase if the presence of a 32 kHz oscillation on XTAL3 XTALA pins is detected then the RTC counter is driven by this low frequency reference clock when Power Down mode is entered the RTC can either be stopped or left running and in both the cases the main oscillator is turned off reducing the power consumption of the device to the minimum required to keep on running the RTC counter and relative reference oscillator This is valid also if Stand by mode is entered switching off the main supply Vpp since both the RTC and the low power oscillator 32 kHz are biased by the Vstpy Vice versa when at power on and after Reset the 32 kHz is not present the main oscillator drives the RTC counter and since it is powered by the main power supply it cannot be maintained running in Stand by mode while in Power Down mode the main oscillator is maintained running to provide the reference to the RTC module if not disabled ST10F276 Watchdog timer 18
128. and Data for Program operations FARH L and FDR1H L FDROH L and Write Operation Error flags FERH L All registers are accessible with 8 and 16 bit instructions since mapped on ST10 XBUS Before accessing the XFlash module and consequently also the Flash register to be used for program erasing operations bit XFLASHEN in XPERCON register and bit XPEN in SYSCON register shall be set The 4 Banks have their own dedicated sense amplifiers so that any Bank can be read while any other Bank is written However simultaneous write operations write means either Program or Erase on different Banks are forbidden when there is a write operation on going Program or Erase anywhere in the Flash no other write operation can be performed During a Flash write operation any attempt to read the bank under modification will output invalid data software trap 009Bh This means that the Flash Bank is not fetchable when a write operation is active the write operation commands must be executed from another 27 229 Internal Flash memory ST10F276 Bank or from the other module or again from another memory internal RAM or external memory Note During a Write operation when bit LOCK of FCR0O is set it is forbidden to write into the Flash Control Registers 4 3 1 Power supply drop If during a write operation the internal low voltage supply drops below a certain internal voltage threshold any write operation running is suddenly interrupted
129. arge partitioning and consequent voltage drop error between the external and the internal capacitance in case an RC filter is necessary the external capacitance must be greater than 10nF to minimize the accuracy impact Overrun error detection protection is controlled by the ADDAT register Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete or the next conversion is suspended until the previous result has been read For applications which require less than 16 8 analog input channels the remaining channel inputs can be used as digital input port pins The A D converter of the ST10F276 supports different conversion modes e Single channel single conversion The analog level of the selected channel is sampled once and converted The result of the conversion is stored in the ADDAT register e Single channel continuous conversion The analog level of the selected channel is repeatedly sampled and converted The result of the conversion is stored in the ADDAT register Auto scan single conversion The analog level of the selected channels are sampled once and converted After each conversion the result is stored in the ADDAT register The data can be transferred to the RAM by interrupt software management or using the powerful Peripheral Event Controller PEC data transfer e Auto scan continuous conversion The analog leve
130. as been selected for capture mode the current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negative or both a positive and a negative external signal transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers When a match occurs between the timer value and the value in a capture compare register specific actions will be taken based on the selected compare mode The input frequencies frx for the timer input selector Tx are determined as a function of the CPU clocks The timer input frequencies resolution and periods which result from the selected pre scaler option in TxI when using a 40 MHz and 64 MHz CPU clock are listed in the Table 44 and Table 45 respectively The numbers for the timer periods are based on a reload value of 0000h Note that some numbers may be rounded to 3 significant figures ST10F276 Capture compare CAPCOM units Table 43 Compare modes Compare Modes Function Mode 0 Interrupt only compare
131. asked through the enable bits allowing an effective software management also in absence of the possibility to serve the related interrupt request a periodic polling of the flag bits may be implemented inside the user application Figure 16 X Interrupt basic structure 7 0 egrj XIRxSEL 7 0 x 0 1 2 3 IT Source 70 IT Source 6r3 IT Source 5 IT Source 43 IT Source 32 IT Source 20 IT Source 1r IT Source 0r3 WO f f Emawerzoj XIRxSEL 15 8 x 0 1 2 3 15 8 PxiC XPxiR x 0 1 2 3 The Table 41 summarizes the mapping of the different interrupt sources which shares the four X interrupt vectors Table 41 X Interrupt detailed mapping XPOINT XP1INT XP2INT XP3INT CANI Interrupt X X CAN2 Interrupt X X I2C Receive X x x 12C Transmit x x x 12C Error X SSC1 Receive X X x SSC1 Transmit X X X SSC1 Error X ASC1 Receive X x x ASC1 Transmit X x X ASC1 Transmit Buffer X X X ST10F276 Interrupt system Table 41 X Interrupt detailed mapping continued XPOINT XP1INT XP2INT XP3INT ASC1 Error X PLL Unlock OWD x PWM1 Channel 3 0 x x 8 2 Exception and error traps list Table 42 shows all of the possible exceptions or error conditions that can arise during run time T
132. ast significant byte Data2 IDCHIP most significant byte For the ST10F276 IDCHIP 114Xh Two behaviors can be distinguished in ST10 acknowledging to the host If the host is behaving according to the CAN protocol as at the beginning the ST10 CAN is not configured the host is alone on the CAN network and does not receive an acknowledge It automatically resends the zero frame As soon as the ST10 CAN is configured it acknowledges the zero frame The acknowledge frame with identifier OxE6 is configured but the Transmit Request is not set The host can request this frame to be sent and therefore obtains the IDCHIP by sending a remote frame Hint As the IDCHIP is sent in the acknowledge frame Flash programming software now can immediately identify the exact type of device to be programmed ST10F276 Bootstrap loader 5 4 3 5 4 4 ST10 configuration in CAN BSL When the ST10F276 enters BSL mode via CAN the configuration shown in Table 31 is automatically set values that deviate from the normal reset values are marked in bold Table 31 ST10 configuration in CAN BSL Function or register Access Notes Watchdog timer Disabled Register SYSCON 0404 XPEN bit set Context pointer CP FA004 Register STKUN FA00j Stack pointer SP FA40y Register STKOV FCOO Register BUSCONO na m CAN1 Status Control register 0000 Initialized only if Bootstrap via CAN CANI Bit timing
133. ate functions 132 1338 P1H 4 CC241O CAPCOM2 CC24 capture input P1H 5 CC25IO CAPCOM2 CC25 capture input 134 P1H 6 CC26lO CAPCOM2 CC26 capture input 135 P1H 7 CC271O CAPCOM2 CC27 capture input 21 229 Pin data ST10F276 Table 1 Pin description continued Symbol Pin Type Function XTAL1 138 XTAL1 Main oscillator amplifier circuit and or external clock input XTAL2 137 O XTAL2 Main oscillator amplifier circuit output To clock the device from an external source drive XTAL1 while leaving XTAL2 unconnected Minimum and maximum high low and rise fall times specified in the AC Characteristics must be observed XTAL3 143 XTAL3 32 kHz oscillator amplifier circuit input XTAL4 144 O XTAL4 32 kHz oscillator amplifier circuit output When 32 kHz oscillator amplifier is not used to avoid spurious consumption XTALS shall be tied to ground while XTAL4 shall be left open Besides bit OFF32 in RTCCON register shall be set 32 kHz oscillator can only be driven by an external crystal and not by a different clock source Reset Input with CMOS Schmitt Trigger characteristics A low level at this pin for a specified duration while the oscillator is running resets the ST10F276 An RSTIN 140 internal pull up resistor permits power on reset using only a capacitor connected to Vss In bidirectional reset mode
134. ayer 35 FR4 board 2 layers signals 2 layers power Based on thermal characteristics of the package and with reference to the power consumption figures provided in the next tables and diagrams the following product classification can be proposed In any case the exact power consumption of the device inside the application must be computed according to different working conditions thermal profiles real thermal resistance of the system including printed circuit board or other substrata and I O activity 177 229 Electrical characteristics ST10F276 Table 89 Package characteristics Package Operating temperature CPU frequency range Die 1 64 MHz PQFP 144 40 4125C LQFP 144 1 40 MHz LQFP 144 40 105 C 1 48 MHz 23 4 Parameter interpretation The parameters listed in the following tables represent the characteristics of the ST10F276 and its demands on the system Where the ST10F276 logic provides signals with their respective timing characteristics the symbol CC Controller Characteristics is included in the Symbol column Where the external system must provide signals with their respective timing characteristics to the ST10F276 the symbol SR System Requirement is included in the Symbol column 23 5 DC characteristics Vpp 5V 10 Vss OV Ta 40 to 125 C Table 90 DC characteristics Limit values
135. bit 9 of SYSCON is set according to data bus width selection via PortO configuration 2 BUSCONO is initialized with 0000h external bus disabled if pin EA is high during reset If pin EA is low during reset BUSACTO bit 10 and ALECTLO bit 9 are set enabling the external bus with lengthened ALE signal BTYP field bit 7 and 6 is set according to PortO configuration x ST10F276 Bootstrap loader Figure 5 ST10F276 new standard bootstrap loader program flow Start timer T6 UARTO RxD 1 Stop timer T6 Initialize UART Send acknowledge Address FA40h aed m Address SORBUF Address Address 1 CAN RxD 0 CAN BOOT v litch on CAN1 RxD Stop timer PTO Clear timer PTO Address FA60h Stop timer PTO Initialize CAN Address FA40h UART BOOT Message received Address MO15 dataO Address Address 1 Address FACOh CAN BOOT Jump to address FA40h Other than after a normal reset the watchdog timer is disabled so the bootstrap loading sequence is not time limited Depending on the selected serial link UARTO or CAN1 pin TxDO or CAN1 TxD is configured as output so the ST10F276 can return the acknowledge byte Even if the internal IFLASH is enabled a code cannot be executed from it 49 229 Bootstrap loader ST10F276 5 2 3 5 2 4 Note 50 229 B
136. bits are reset as well for this reason it is definitively meaningful reading FER register content only when LOCK bit and all BSY bits are cleared FER OxE 0014h FCR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WPF RESERISEQER reserved 10ER PGER ERER ERR RC RC RC RC RC RC RC Table 17 Flash error register Bit Function Write error This bit is automatically set when an error occurs during a Flash write operation or ERR when a bad write operation setup is done Once the error has been discovered and understood ERR bit must be software reset Erase error This bit is automatically set when an erase error occurs during a Flash write operation ERER This error is due to a real failure of a Flash cell that can no more be erased This kind of error is fatal and the sector where it occurred must be discarded This bit has to be software reset Program error This bit is automatically set when a program error occurs during a Flash write PGER operation This error is due to a real failure of a Flash cell that can no more be programmed The word where this error occurred must be discarded This bit has to be software reset 1 over 0 error This bit is automatically set when trying to program at 1 bits previously set at O this 10ER does not happen when programming the protection bits This error is not due to a failure of the Flash cell bu
137. ccessed XSSC enable bit 0 Accesses to the on chip XSSC are disabled external access performed XSSCEN Address range 00 E800h 00 E8FFh is directed to external memory only if CAN1EN CAN2EN XRTCEN XASCEN XI2CEN XPWMEN and XMISCEN are 0 also 1 The on chip XSSC is enabled and can be accessed IC enable bit 0 Accesses to the on chip 1 C are disabled external access performed Address XI2CEN range 00 EA00h 00 EAFFh is directed to external memory only if CAN1EN CAN2EN XRTCEN XASCEN XSSCEN XPWMEN and XMISCEN are 0 also 1 The on chip I C is enabled and can be accessed XBUS additional features enable bit 0 Accesses to the Additional Miscellaneous Features is disabled Address range XMISCEN 00 EBOOh OO EBFFh is directed to external memory only if CAN1EN CAN2EN XRTCEN XASCEN XSSCEN XPWMEN and XI2CEN are 0 also 1 The Additional Features are enabled and can be accessed When CAN1 CAN2 RTC XASC XSSC I C XPWM and the XBUS Additional Features are all disabled via XPERCON setting then any access in the address range 00 E800h 00 EFFFh is directed to external memory interface using the BUSCONXx register corresponding to the address matching ADDRSELx register All pins used for X Peripherals can be used as General Purpose I O whenever the related module is not enabled 173 229 Register set ST10F276 Note 22 10 1 Note 174 229 The d
138. ce of Tmax and Tmin where Tmax is the maximum time difference between N 1 clock rising edges and Tmin is the minimum time difference between N 1 clock rising edges Here N should be kept sufficiently large to have the long term jitter For N 1 this becomes the single period jitter Jitter at the PLL output is caused by e Jitter in the input clock e Noisein the PLL loop Jitter in the input clock PLL acts like a low pass filter for any jitter in the input clock Input Clock jitter with the frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency jitter frequency PLL bandwidth is attenuated at 20dB decade Noise in the PLL loop This condition again is attributed to the following sources Device noise of the circuit in the PLL e Noise in supply and substrate Device noise of the circuit in the PLL Long term jitter is inversely proportional to the bandwidth of the PLL The wider the loop bandwidth the lower the jitter due to noise in the loop Moreover long term jitter is practically independent of the multiplication factor The most noise sensitive circuit in the PLL circuit is definitely the VCO Voltage Controlled Oscillator There are two main sources of noise Thermal random noise frequency independent thus practically white noise and flicker low frequency noise 1 f For the frequency characteristics of the VCO circuitry the effect of the thermal noise results in a 1 f regio
139. ci word register onto system stack and call absolute 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH POP Push pop direct word register onto from system stack 2 SCXT Push direct word register onto system stack and update register 4 with word operand RET Return from intra segment subroutine 2 RETS Return from inter segment subroutine 2 RETP Return from intra segment subroutine and pop direct word register 2 from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode supposes NMI pin being low 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End of Initialization on RSTOUT pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP R Begin EXTended Page and Register sequence 2 4 EXTS R Begin EXTended Segment and Register sequence 2 4 NOP Null operation 2 74 229 ST10F276 Central processing unit CPU 6 3 MAC coprocessor specific instructions The Table 39 lists the MAC instructions of the ST10F276 The detailed description of each instruction can be found in the ST10 Family Programming Manual Note that all MAC instructions are encoded on 4 bytes Table 39 MAC instruction set summary Mnemonic Description CoABS Absolute Value of the Accumulator CoADD 2 Addition CoASHR rnd Accumulator Arithmetic Shift Right amp Optional
140. ck Embedded memory size has been significantly increased both Flash and RAM PLL multiplication factors have been adapted to new frequency range A D Converter is not fully compatible versus ST10F269 timing and programming model Formula for the convertion time is still valid while the sampling phase programming model is different Besides additional 8 channels are available on P1L pins as alternate function the accuracy reachable with these extra channels is reduced with respect to the standard Port5 channels External Memory bus potential limitations on maximum speed and maximum capacitance load could be introduced under evaluation ST10F276 will probably not be able to address an external memory at 64MHz with O wait states under evaluation XPERCON register bit mapping modified according to new peripherals implementation not fully compatible with ST10F269 Bondout chip for emulation ST10R201 cannot achieve more than 50MHz at room temperature so no real time emulation possible at maximum speed Input section characteristics are different The threshold programmability is extended to all port pins additional XPICON register it is possible to select standard TTL with up to 500mV of hysteresis and standard CMOS with up to 800mV of hysteresis Output transition is not programmable CAN module is enhanced ST10F276 implements two C CAN modules so the programming model is slightly different Besides the possibility
141. ck though an external clock source 3 The maximum depends on the duty cycle of the external clock signal When 64 MHz is used 50 duty cycle shall be granted low phase high phase 7 8ns when 32 MHz is selected a 25 duty cycle can be accepted minimum phase high or low again equal to 7 8ns Prescaler operation When pins P0 15 13 POH 7 5 equal 001 during reset the CPU clock is derived from the internal oscillator input clock signal by a 2 1 prescaler The frequency of fcpy is half the frequency of fy 4 and the high and low time of fcpy that is the duration of an individual TCL is defined by the period of the input clock fy The timings listed in the AC Characteristics that refer to TCL can therefore be calculated using the period of fA for any TCL Note that if the bit OWDDIS in SYSCON register is cleared the PLL runs on its free running frequency and delivers the clock signal for the Oscillator Watchdog If bit OWDDIS is set then the PLL is switched off Direct drive When pins P0 15 13 POH 7 5 equal 011 during reset the on chip phase locked loop is disabled the on chip oscillator amplifier is bypassed and the CPU clock is directly driven by the input clock signal on XTAL 1 pin The frequency of the CPU clock fcpy directly follows the frequency of fa so the high and low time of fcp j that is the duration of an individual TCL is defined by the duty cycle of the input clock fy ky ST1
142. control register 00h CC18IC b F164h E B2h CAPCOM register 18 interrupt control register 00h CC19IC b F166h E B3h CAPCOM register 19 interrupt control register 00h CC20IC b F168h E B4h CAPCOM register 20 interrupt control register 00h CC21IC b Fi6Ah E B5h CAPCOM register 21 interrupt control register 00h CC221C b F16Ch E B6h CAPCOM register 22 interrupt control register 00h CC23IC b Fi6Eh E B7h CAPCOM register 23 interrupt control register 00h CC24IC b Fi70h E B8h CAPCOM register 24 interrupt control register 00h CC25IC b Fi72h E B9h CAPCOM register 25 interrupt control register 00h CC26IC b Fi74h E BAh CAPCOM register 26 interrupt control register 00h CC27IC b Fi76h E BBh CAPCOM register 27 interrupt control register 00h CC28IC b F178h E BCh CAPCOM register 28 interrupt control register 00h T7IC b F17Ah E BDh CAPCOM timer 7 interrupt control register 00h T8IC b F17Ch E BEh CAPCOM timer 8 interrupt control register 00h PWMIC b Fi7Eh E BFh PWM module interrupt control register 00h CC29IC b F184h E C2h CAPCOM register 29 interrupt control register 00h XPOIC b F186h E C3h See Section 8 1 00h CC30IC b F18Ch E C6h CAPCOM register 30 interrupt control register 00h XP1IC b Fi8Eh E C7h See Section 8 1 00h CC311C b F194h E CAh CAPCOM register 31 interrupt control register 00h XP2IC b F196h E CBh See Section 8 1 00h SOTBIC b Fi9Ch E CEh oe 0 transmit buffer inte
143. d I7 of PORTO latched at the end of the reset sequence 2 BUSCONO is initialized with OOOOh if EA pin is high during reset If EA pin is low during reset bit BUSACTO and ALECTRLO are set 1 and bit field BTYP is loaded with the bus configuration selected via PORTO RPOH F108h 84h ESFR Reset value XXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKSEL SALSEL CSSEL WRC R R R R Table 79 RPOH description Bit Function Write configuration control WRC 2 0 Pin WR acts as WRL pin BHE acts as WRH 4 Pins WR and BHE retain their normal function Chip select line selection number of active CS outputs 0 0 3 CS lines CS2 CS0 CSSEL 0 1 2 CS lines CS1 CS0 1 0 No CS line at all 11 5 CS lines CS4 CS0O Default without pull downs Segment address line selection number of active segment address outputs 00 4 bit segment address A19 A16 SALSEL 01 No segment address lines at all 10 8 bit segment address A23 A16 11 2 bit segment address A17 A16 Default without pull downs System clock selection 000 fopy 16 x fosc 7001 fopu 0 5x fosc 7010 fopu 10x fosc CLKSEL Q11 fopy fosc 100 fopu 5x fosc 101 fopy 8 X fosc 110 fopy 3 x fosc 111 fopu 4x fosc RPOH is a read only register These bits are set according to Port 0 configuration during any reset sequence 3 RPOH
144. d R are defined Some conditions discussed in the previous paragraphs have been used to size the component the others must now be verified The relation which allows to minimize the accuracy error introduced by the switched capacitance equivalent resistance is in this case REq pc 10MQ So the error due to the voltage partitioning between the real resistive path and Cg is less 193 229 Electrical characteristics ST10F276 23 8 23 8 1 194 229 then half a count considering the worst case when V4 5V Re RE R R R v S F L SW AD 3smy LSB A REG 2 The other conditions to verify are if the time constants of the transients are really and significantly shorter than the sampling period duration Ts t4 Rsw Rap Cg 2 8ns lt lt Tg 1us 10 52 10R Cs Cp4 Cp4 7 290ns lt Ts tus For a complete set of parameters characterizing the ST10F276 A D converter equivalent circuit refer to A D Converter Characteristics table at page 185 AC characteristics Test waveforms Figure 50 Input output waveforms 2 4V Test Points 0 4V AC inputs during testing are driven at 2 4V for a logic 1 and 0 4V for a logic 0 Timing measurements are made at V min for a logic 1 and Vij max for a logic O Figure 51 Float waveforms Vou 01V Vi oap 0 1V Vi oAD Timing Reference Vi oAD 0 1V Points VoL 0 1V VoL For timing purposes a port pin is
145. d READY READY Running cycle 1 al wait state dL MUX Tri state 1 em NSN 41 D WR a ps leto hs csi a Synchronous m Sue Bis R ces ae READY 7 NN 3 f e 09854 Asynchronous tss ise tss sees 1 t60 4 p gt lt lt gt lt gt lt gt READY 7 3 n X 3 7727777 I ety 5 lt 4 6 Cycle as programmed including MCTC wait states Example shows 0 MCTC WS 2 The leading edge of the respective command depends on RW delay READY sampled HIGH at this sampling point generates a READY controlled wait state READY sampled LOW at this sampling point terminates the currently running bus cycle 4 READY may be deactivated in response to the trailing rising edge of the corresponding command RD or WR 5 If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT for example because CLKOUT is not enabled it must fulfill t37 in order to be safely synchronized This is guaranteed if READY is removed in response to the command see Note 4 6 Multiplexed bus modes have a MUX wait state added after a bus cycle and an additional MTTC wait state may be inserted here For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles for a demultiplexed bus without MTTC wait state this delay is zero 7 The next external bus cycle may start here 219 229 Electrical characteristics ST10F276
146. d embedded low power voltage regulator is in charge to provide the 1 8V for the RAM the low voltage section of the 32kHz oscillator and the Real Time Clock module when not disabled It is allowed to exceed the upper limit up to 6V for a very short period of time during the global life of the device and exceed the lower limit down to 4V when RTC and 32kHz on chip oscillator are not used e Asecond SSC mapped on the XBUS is added SSC of ST10F269 becomes here SSCO while the new one is referred as XSSC or simply SSC1 Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic SSC and the new XSSC Asecond ASC mapped on the XBUS is added ASCO of ST10F269 remains ASCO while the new one is referred as XASC or simply as ASC1 Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic ASC and the new XASC e Asecond PWM mapped on the XBUS is added PWM of ST10F269 becomes here PWMO while the new one is referred as XPWM or simply as PWM1 Note that some 13 229 Introduction ST10F276 14 229 restrictions and functional differences due to the XBUS peculiarities are present between the classic PWM and the new XPWM An l C interface on the XBUS is added see X I C or simply l C interface CLKOUT function can output either the CPU clock like in ST10F269 or a software programmable prescaled value of the CPU clo
147. d in 10 sectors Bank 0 contains also a reserved sector named test Flash Bank 1 contains 128 Kbyte of program memory or parameter divided in 2 sectors 64 Kbyte each The XFLASH module is composed by 2 banks as well Bank 2 contains 192 Kbyte of Program Memory divided in 3 sectors Bank 3 contains 128 Kbyte of program memory or parameter divided in 2 sectors 64 Kbyte each Addresses from OxOE 0000 to OxOE FFFF are reserved for the control register interface and other internal service memory space used by the Flash program erase controller The following tables show the memory mapping of the Flash when it is accessed in read mode Table 3 and when accessed in write or erase mode Table 2 note that with this second mapping the first three banks are remapped into code segment 1 same as obtained when setting bit ROMS1 in SYSCON register Table 3 Flash modules sectorization read operations Bank Description Addresses Size urn Bank 0 Flash 0 BOFO 0x0000 0000 0x0000 1FFF 8 KB Bank 0 Flash 1 BOF1 0x0000 2000 0x0000 3FFF 8 KB Bank 0 Flash 2 BOF2 0x0000 4000 0x0000 5FFF 8 KB Bank 0 Flash 3 BOF3 0x0000 6000 0x0000 7FFF 8 KB 35 Bank 0 Flash 4 BOF4 0x0001 8000 0x0001 FFFF 32 KB Bank 0 Flash 5 BOF5 0x0002 0000 0x0002 FFFF 64 KB Bank 0 Flash 6 BOF6 0x00030000 0x0008FFFF e 4KB Ait BUS Bank 0 Flash 7 BOF7 0x0004 0000 0x0004 FFFF 64 K
148. d mask 0000h CAN1IF1M1 EF14h CAN1 IF1 mask 1 FFFFh CAN1IF1M2 EF16h CAN1 IF1 mask 2 FFFFh CAN1IF1A1 EF18h CAN1 IF1 arbitration 1 0000h CAN1IF1A2 EF1Ah CAN1 IF1 arbitration 2 0000h CAN1IF1MC EF1Ch CAN1 IF1 message control 0000h CAN1IF1DA1 EF1Eh CAN1 IF1 data A 1 0000h CAN1IF1DA2 EF20h CAN1 IF1 data A 2 0000h CAN1IF1DB1 EF22h CAN1 IF1 data B 1 0000h CAN1IF1DB2 EF24h CAN1 IF1 data B 2 0000h 161 229 Register set ST10F276 162 229 Table 70 X registers ordered by address continued Physical Name address Description Reset value CAN1IF2CR EF40h CAN1 IF2 command request 0001h CAN1IF2CM EF42h CAN1 IF2 command mask 0000h CAN1IF2M1 EF44h CAN1 IF2 mask 1 FFFFh CAN1IF2M2 EF46h CAN1 IF2 mask 2 FFFFh CAN1IF2A1 EF48h CAN1 IF2 arbitration 1 0000h CAN1IF2A2 EF4Ah CAN1 IF2 arbitration 2 0000h CAN1IF2MC EF4Ch CAN1 IF2 message control 0000h CAN1IF2DA1 EF4Eh CAN1 IF2 data A 1 0000h CAN1IF2DA2 EF50h CAN1 IF2 data A 2 0000h CAN1IF2DB1 EF52h CAN1 IF2 data B 1 0000h CAN1IF2DB2 EF54h CAN1 IF2 data B 2 0000h CAN1TR1 EF80h CAN1 transmission request 1 0000h CAN1TR2 EF82h CAN1 transmission request 2 0000h CAN1ND1 EF90h CAN1 new data 1 0000h CAN1ND2 EF92h CAN1 new data 2 0000h CAN1IP1 EFAOh CAN1 interrupt pending 1 0000h CAN1IP2 EFA2h CAN1 interrupt pending 2 0000h CAN1MV1 EFBOh CAN1 message valid 1 0000h CAN1MV2 EFB2h CAN1 message valid 2 0000h
149. ded in two banks that can be read and modified independently one of the other one bank can be read while another bank is under modification Figure 4 Flash modules structure IFLASH Module I Control section XFLASH Module X Bank 1 128 Kbyte HV and Ref Bank 3 128 Kbyte program memory generator program memory Bank 0 384 Kbyte d program memory Bank 2 192 Kbyte Program erase program memory T 8 Kbyte test Flash controller I BUS interface X BUS interface The write operations of the 4 banks are managed by an embedded Flash program erase controller FPEC The high voltages needed for program erase operations are internally generated The data bus is 32 bit wide Due to ST10 core architecture limitation only the first 512 Kbytes are accessed at 32 bit internal Flash bus see I BUS while the remaining 320 Kbytes are accessed at 16 bit see X BUS Functional description Structure The following table shows the address space reserved to the Flash module Table 2 Flash modules absolute mapping Description Addresses Size IFLASH sectors 0x00 0000 to 0x08 FFFF 512 Kbyte XFLASH sectors 0x09 0000 to OxOD FFFF 320 Kbyte a and Flash internal reserved OxOE 0000 to OxOE FFFF 64 Kbyte ST10F276 Internal Flash memory 4 2 2 Modules structure The IFLASH module is composed by 2 banks Bank 0 contains 384 Kbyte of program memory divide
150. drawn while the respective signal line remains inactive The minimum current must be drawn in order to drive the respective signal line active The power supply current is a function of the operating frequency fcpy is expressed in MHz This dependency is illustrated in the Figure 45 below This parameter is tested at Vppmax and at maximum CPU clock frequency with all outputs disconnected and all inputs at Vj or Viu RSTIN pin at ViHimin This implies I O current is not considered The device is doing the following Fetching code from IRAM and XRAM1 accessing in read and write to both XRAM modules Watchdog Timer is enabled and regularly serviced RTC is running with main oscillator clock as reference generating a tick interrupts every 192 clock cycles Four channels of XPWM are running waves period 2 2 5 3 and 4 CPU clock cycles No output toggling Five General Purpose Timers are running in timer mode with prescaler equal to 8 T2 T3 T4 T5 T6 ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5 All interrupts generated by XPWM RTC Timers and ADC are not serviced The power supply current is a function of the operating frequency fcpy is expressed in MHz This dependency is illustrated in the Figure 45 below This parameter is tested at Vonmax and at maximum CPU clock frequency with all outputs disconnected and all inputs at Vij or Vj RSTIN pin at ViHimin This implies I O current is not considered Th
151. ds stable Va but does not need stable system clock since an internal dedicated oscillator is used Warning Itis recommended to provide the external hardware with a current limitation circuitry This is necessary to avoid permanent damages of the device during the power on transient when the capacitance on V4g pin is charged For the on chip voltage regulator functionality 10nF are 105 229 System reset ST10F276 Note 106 229 sufficient anyway a maximum of 100nF on V4g pin should not generate problems of over current higher value is allowed if current is limited by the external hardware External current limitation is anyway recommended also to avoid risks of damage in case of temporary short between V4g and ground the internal 1 8V drivers are sized to drive currents of several tens of Ampere so the current shall be limited by the external hardware The limit of current is imposed by power dissipation considerations Refer to Electrical Characteristics Section In next Figures 24 and 25 Asynchronous Power on timing diagrams are reported respectively with boot from internal or external memory highlighting the reset phase extension introduced by the embedded FLASH module when selected Never power the device without keeping RSTIN pin grounded the device could enter in unpredictable states risking also permanent damages ST10F276 System reset Figure 24 Asynchronous power on RESET EA 1 lt
152. e XPW1 EC32h XPWM module pulse width register 1 0000h XPW2 EC34h XPWM module pulse width register 2 0000h XPW3 EC36h XPWM module pulse width register 3 0000h XPWMPORT EC80h XPWM module port control register 0000h RTCCON EDOOH RTC control register 000Xh RTCPL EDO6h RTC prescaler register low byte XXXXh RTCPH EDO8h RTC prescaler register high byte XXXXh RTCDL EDOAh RTC divider counter low byte XXXXh RTCDH EDOCh RTC divider counter high byte XXXXh RTCL EDOEh RTC programmable counter low byte XXXXh RTCH ED10h RTC programmable counter high byte XXXXh RTCAL ED12h RTC alarm register low byte XXXXh RTCAH ED14h RTC alarm register high byte XXXXh CAN2CR EEO0h CAN2 CAN control register 0001h CAN2SR EEO2h CAN2 status register 0000h CAN2EC EE04h CAN2 error counter 0000h CAN2BTR EEO6h CAN2 bit timing register 2301h CAN2IR EEO8h CAN2 interrupt register 0000h CAN2TR EEOAh CAN2 test register 00x0h CAN2BRPER EEOCh CAN2 BRP extension register 0000h CAN2IF1CR EE10h CAN2 IF1 command request 0001h CAN2IF1CM EE12h CAN2 IF1 command mask 0000h CAN2IF1M1 EE14h CAN2 IF1 mask 1 FFFFh CAN2IF1M2 EE16h CAN2 IF1 mask 2 FFFFh CAN2IF1A1 EE18h CAN2 IF1 arbitration 1 0000h CAN2IF1A2 EE1Ah CAN2 IF1 arbitration 2 0000h CAN2IF1MC EE1Ch CAN2 IF1 message control 0000h CAN2IF1DA1 EE1Eh CAN2 IF1 data A 1 0000h CAN2IF1DA2 EE20h CAN2 IF1 data A2 0000h CAN2IF1DB1 EE22h CAN2 IF1 data B 1 0000h CAN2IF1DB2 EE24h CAN2 IF1 data B2 0000h CAN2IF2CR EE40h CAN2 IF2 command reque
153. e 64 MHz can be applied with an external clock source only when Direct Drive mode is selected In this case the oscillator amplifier is bypassed so it does not limit the input frequency 3 The input clock signal must reach the defined levels Vi and Vis Figure 56 External clock drive XTAL1 t ViLo tosc When Direct Drive is selected an external clock source can be used to drive XTAL1 The maximum frequency of the external clock source depends on the duty cycle When 64 MHz is used 50 duty cycle is granted low phase high phase 7 8ns when for instance 32 MHz is used a 25 duty cycle can be accepted minimum phase high or low again equal to 7 8ns Memory cycle variables The tables below use three variables which are derived from the BUSCONXx registers and represent the special characteristics of the programmed memory cycle The following table describes how these variables are computed Table 103 Memory cycle variables Symbol Description Values ta ALE extension TCL x ALECTL tc Memory cycle time wait states 2TCL x 15 MCTC te Memory tri state time 2TCL x 1 MTTC ST10F276 Electrical characteristics 23 8 17 External memory bus timing In the next sections the External Memory Bus timings are described The given values are computed for a maximum CPU clock of 40 MHz It is evident that when higher CPU clock frequency is used up to 64 MHz
154. e deviation Fp in percent between host baud rate and ST10F276 baud rate can be calculated using the formula below Function Fg does not consider the tolerances of oscillators and other devices supporting the serial communication This baud rate deviation is a nonlinear function depending on the CPU clock and the baud rate of the host The maxima of the function Fg increases with the host baud rate due to the smaller baud rate prescaler factors and the implied higher quantization error see Figure 10 Figure 10 Baud rate deviation between host and ST10F276 Brow Buigh Buost D The minimum baud rate B ow in Figure 10 is determined by the maximum count capacity of timer T6 when measuring the zero byte that is it depends on the CPU clock Using the maximum T6 count 216 in the formula the minimum baud rate is calculated The lowest ky ST10F276 Bootstrap loader 5 4 5 4 1 standard baud rate in this case would be 1200 baud Baud rates below B ow would cause T6 to overflow In this case ASCO cannot be initialized properly The maximum baud rate Bigh in Figure 10 is the highest baud rate where the deviation still does not exceed the limit that is all baud rates between B pw and Bhign are below the deviation limit The maximum standard baud rate that fulfills this requirement is 19200 baud Higher baud rates however may be used as long as the actual deviation does not exceed the limi
155. e device is doing the following Fetching code from all sectors of both IFlash and XFlash accessing in read few fetches and write to XRAM Watchdog Timer is enabled and regularly serviced RTC is running with main oscillator clock as reference generating a tick interrupts every 192 clock cycles Four channels of XPWM are running waves period 2 2 5 3 and 4 CPU clock cycles No output toggling Five General Purpose Timers are running in timer mode with prescaler equal to 8 T2 T3 T4 T5 T6 ADC is in Auto Scan Continuous Conversion mode on all 16 channels of Port5 All interrupts generated by XPWM RTC Timers and ADC are not serviced The Idle mode supply current is a function of the operating frequency fcpy is expressed in MHz This dependency is illustrated in the Figure 44 below These parameters are tested and at maximum CPU clock with all outputs disconnected and all inputs at Vij or Viu RSTIN pin at ViHimin This parameter is tested including leakage currents All inputs including pins configured as inputs at 0 to 0 1V or at Vpp 0 1V to Vpp Varer OV all outputs including pins configured as outputs disconnected Furthermore the Main Voltage Regulator is assumed off In case it is not additional 1mA shall be assumed 181 229 ST10F276 Electrical characteristics 182 229 Figure 44 Port2 test mode structure 20 P2 0 Output CCOIO Buffer Clock Input Alternate Data I
156. e end of a erase operation if no errors are detected Bank 3 2 status XFLASH During any erase operation these bits are automatically modified and give the status B 3 2 8 of the 2 Banks B3 B2 The meaning of BxS bit for bank x is given in the next Table 10 These bits are automatically reset at the end of a erase operation if no errors are detected SMOD 1 IFLASH selected Bank 1 IFLASH sector 1 0 status During any erase operation these bits are automatically set and give the status of the B1F 1 0 2 sectors of bank 1 B1F1 B1F0 The meaning of B1Fy bit for sector y of bank 1 is given by the next Table 10 These bits are automatically reset at the end of a erase operation if no errors are detected Bank 1 0 status IFLASH During any erase operation these bits are automatically modified and give the status B 1 0 S_ of the 2 banks B1 BO The meaning of BxS bit for bank x is given in the next Table 10 These bits are automatically reset at the end of a erase operation if no errors are detected During any erase operation these bits are automatically set and give the status of the 2 sectors of Bank 1 B1F1 B1F0 The meaning of B1Fy bit for sector y of bank 1 is given by the next Table 10 These bits are automatically reset at the end of a erase operation if no errors are detected 32 229 ky ST10F276 Internal Flash memory Table 10 Banks BxS and sectors BxFy status bits meaning
157. e value of the capacitance shall be big enough to maintain the voltage on RPD pin sufficient high along the duration of the internal reset sequence For a Software or Watchdog reset events an active synchronous reset is completed regardless of the RPD status It is important to highlight that the signal that makes RPD status transparent under reset is the internal RSTF after the noise filter ST10F276 System reset Figure 28 Synchronous short long hardware RESET EA 1 4 TCL 12 TCL 1032 TCL i RSTF After Filter P0 15 13 P0 12 2 PO 1 0 IBUS CS Internal FLARST n this time RSTF is sampled HIGH or LOW so itis SHORT or LONG reset RSTOUT 2 2001A Discharge Fr Vpro gt 2 5V Asynchronous Reset not entered Notes 1 RSTIN assertion can be released there Refer also to Section 21 1 for details on minimum pulse duration 2 If during the reset condition RSTIN low RPD voltage drops below the threshold voltage about 2 5V for 5V operation the asynchronous reset is then immediately entered 3 RSTIN pin is pulled low if bit BDRSTEN bit 3 of SYSCON register was previously set by software Bit BDRSTEN is cleared after reset 4 Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter refer to Section 21 1 113 229 System reset ST10F276
158. ecification range that is at least 4 5V This is a constraint for the application hardware external voltage regulator the RSTIN pin assertion shall be extended to guarantee the voltage regulator stabilization A second constraint is imposed by the embedded FLASH When booting from internal memory starting from RSTIN releasing it needs a maximum of 1ms for its initialization before that the internal reset RST signal is not released so the CPU does not start code execution in internal memory This is not true if external memory is used pin EA held low during reset phase In this case once RSTIN pin is released and after few CPU clock Filter delay plus 3 8 TCL the internal reset signal RST is released as well so the code execution can start immediately after Obviously an eventual access to the data in internal Flash is forbidden before its initialization phase is completed an eventual access during starting phase will return FFFFh just at the beginning while later OO9Bh an illegal opcode trap can be generated At Power on the RSTIN pin shall be tied low for a minimum time that includes also the start up time of the main oscillator tstyp 1ms for resonator 10ms for crystal and PLL synchronization time tpsyp 200us this means that if the internal FLASH is used the RSTIN pin could be released before the main oscillator and PLL are stable to recover some time in the start up phase FLASH initialization only nee
159. ectors or Banks to erase 3 Thelast instruction is used to start the write operation by setting the start bit WMS in the FCRO Once selected but not yet started one operation can be canceled by resetting the operation selection bit A summary of the available Flash Module Write Operations are shown in the following Table 27 Table 27 Flash write operations Operation Select bit Address and Data Start bit FARL FARH Word Program 32 bit WPG FDROL FDROH WMS FARL FARH Double Word Program 64 bit DWPG FDROL FDROH WMS FDR1L FDR1H Sector Erase SER FCR1L FCR1H WMS ky ST10F276 Internal Flash memory Table 27 Flash write operations continued Operation Select bit Address and Data Start bit Set Protection SPR FDROL FDROH WMS Program Erase Suspend SUSP None None ky 45 229 Bootstrap loader ST10F276 5 5 1 46 229 Bootstrap loader ST10F276 implements innovative boot capabilities in order to support a user defined bootstrap see Alternate bootstrap loader support bootstrap via UART or bootstrap via CAN for the standard bootstrap Selection among user code standard or alternate bootstrap The selection among user code standard bootstrap or alternate bootstrap is made by special combinations on PortOL 5 4 during the time the reset configuration is latched from Porto The alternate boot mode is triggered with a special combination set on PortOL 5
160. ed the register XPEREMU must be written with the same content of XPERCON This is mandatory in order to allow a correct emulation of the new set of features introduced on XBUS for the new ST10 generation The following instructions must be added inside the initialization routine if SYSCON XPEN amp amp XPERCON amp 0x07D3 then XPEREMU XPERCON Of course XPEREMU must be programmed after XPERCON and after SYSCON in this way the final configuration for X Peripherals is stored in XPEREMU and used for the emulation hardware setup XPEREMU EB7Eh XBUS Reset value xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XMISC XI2C XSSC XASC XPWM XFLAS XRTC XRAM2 XRAM1 CAN2 CAN1 EN EN EN EN EN HEN EN EN EN EN EN RW RW RW RW RW RW RW RW RW RW RW The bit meaning is exactly the same as in XPERCON ky ST10F276 Register set 22 11 Emulation dedicated registers Four additional registers are implemented for emulation purposes only Similarly to XPEREMU they are write only registers XEMUO EB76h XBUS Reset value xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XEMUO 15 0 Ww XEMU1 EB78h XBUS Reset value xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XEMU1 15 0 Ww XEMU2 EB7Ah XBUS Reset value xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XEMU2 15 0 w
161. ed by the internal pull down device then the device is forced in an asynchronous reset This mechanism insures recovery from very catastrophic failure Figure 37 Minimum external reset circuitry External Hardware C1 lt lt a Hardware Reset b For Power up Reset and Interruptible Power Down mode ST10F276 The minimum reset circuit of Figure 37 is not adequate when the RSTIN pin is driven from the ST10F276 itself during software or watchdog triggered resets because of the capacitor C1 that will keep the voltage on RSTIN pin above Vi after the end of the internal reset sequence and thus will trigger an asynchronous reset sequence Figure 38 shows an example of a reset circuit In this example R1 C1 external circuit is only used to generate power up or manual reset and RO CO circuit on RPD is used for power up reset and to exit from Power Down mode Diode D1 creates a wired OR gate connection to the reset pin and may be replaced by open collector Schmitt trigger buffer Diode D2 provides a faster cycle time for repetitive power on resets R2 is an optional pull up for faster recovery and correct biasing of TTL Open Collector drivers 123 229 System reset ST10F276 Figure 38 System reset circuit Vpp Vpp R2 External Hardware D2 R1 RSTIN E X Vop D1
162. ee E L WrCSx E i l l l is h l a tag 217 229 Electrical characteristics ST10F276 23 8 20 218 229 CLKOUT and READY Vpp BV 1096 Vgs OV TA 40 to 125 C C 50pF Table 106 CLKOUT and READY Fcpu 40 MHz Variable CPU clock Symbol Parameter TCL 12 5ns 1 2 TCL 1 to 64 MHz Min Max Min Max tog CC CLKOUT cycle time 25 25 2TCL 2TCL 159 CC CLKOUT high time 9 TCL 3 5 t34 CC CLKOUT low time 10 TCL 2 5 155 CC CLKOUT rise time t33 CC CLKOUT fall time CLKOUT rising edge to t34 cc ALE falling edge 2 ta 8 ta 24 tA 84 ta Synchronous READY los SR setup time to CLKOUT M M Synchronous READY te SR hold time after CLKOUT e t4 SR Asynchronous READY 35 E 2TCL 10 _ low time Asynchronous READY by SR setup time 7 d t Asynchronous READY t9oSR hold time Async READY hold time after RD WR high teo SR Demultiplexed 0 2ta TC te 0 2ta tC tr Bus Unit ns 1 These timings are given for characterization purposes only in order to assure recognition at a specific clock edge 2 Demultiplexed bus is the worst case For multiplexed bus 2TCLs must be added to the maximum values This adds even more time for deactivating READY 2t and t refer to the next following bus cycle and tr refers to the current bus cycle ST10F276 Electrical characteristics Figure 65 CLKOUT an
163. efault XPER selection after Reset is such that CAN1 is enabled CAN2 is disabled XRAM1 2 Kbyte XRAM is enabled and XRAM2 64 Kbyte XRAM is disabled all the other X Peripherals are disabled after Reset Register XPERCON cannot be changed after the global enabling of X Peripherals that is after setting of bit XPEN in SYSCON register In Emulation mode all the X Peripherals are enabled XPERCON bits are all set The bondout chip determines whether or not to redirect an access to external memory or to XBUS Reserved bits of XPERCON register are always written to 0 Table 85 below summarizes the Segment 8 mapping that depends upon the EA pin status during reset as well as the SYSCON bit XPEN and XPERCON bits XRAM2EN and XFLASHEN registers user programmed values Table 85 Segment 8 address range mapping E XPEN XRAM2EN XFLASHEN Segment 8 0 0 x x External memory 0 1 0 0 External memory 0 1 1 X Reserved 0 1 x 1 Reserved 1 X X X IFlash B1F1 The symbol x in the table above stands for do not care XPERCON and XPEREMU registers As already mentioned the XPERCON register must be programmed to enable the single XBUS modules separately The XPERCON is a read write ESFR register the XPEREMU register is a write only register mapped on XBUS memory space address EB7Eh Once the XPEN bit of SYSCON register is set and at least one of the X peripherals except memories is activat
164. eference clock and PLL input can be restored only by a hardware reset or by a bidirectional software or watchdog reset event that forces the RSTIN pin low The external RC circuit on RSTIN pin must be the right size in order to extend the duration of the low pulse to grant the PLL to be locked before the level at RSTIN pin is recognized high Bidirectional reset internally drives RSTIN pin low for just 1024 TCL definitely not sufficient to get the PLL locked starting from free running mode Conditions Vpp 5V 1096 TA 40 125 C Table 97 PLL lock unlock timing Value Symbol Parameter Conditions Unit Min Max Tpsup PLL Start up time Stable Vpp and reference clock 300 us TeK PLL Lock in time Stable Vpp and reference clock 250 starting from free running mode Single Period Jitter 1 6 sigma time period variation Tor cycle to cycle 2 TCL peak to peak ee F200 ps F PLL free running Multiplication factors 3 4 250 2000 kHz tes frequency Multiplication factors 5 8 10 16 500 4000 1 Not 100 tested guaranteed by design characterization Main oscillator specifications Conditions Vpp 5V 10 Ty 40 125 C Table 98 Main oscillator specifications Value Symbol Parameter Conditions Unit Min Typ Max Om Oscillator transconductance 8 17 35 mAN Vosc Oscillation amplitude Peak to peak Vpp 0 4
165. emory 4 4 3 Flash control register 1 low The Flash control register 1 low FCR1L together with Flash control register 1 high FCR1H is used to select the sectors to erase or during any write operation to monitor the status of each sector of the module selected by SMOD bit of FCROH First diagram shows FCR1L meaning when SMOD 0 the second one when SMOD 1 FCR1L OxOE 0004 SMOD 0 FCR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved B2F2 B2F1 B2F0 RS RS RS FCR1L OxOE 0004 SMOD 1 FCR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BOF9 BOF8 BOF7 BOF6 BOF5 BOF4 BOF3 BOF2 BOF1 BOFO RS RS RS RS RS RS RS RS RS RS Table 8 Flash control register 1 low Bit Function SMOD 0 XFLASH selected B2F 2 0 Bank 2 XFLASH sector 2 0 status These bits must be set during a Sector Erase operation to select the sectors to erase in bank 2 Besides during any erase operation these bits are automatically set and give the status of the 3 sectors of bank 2 B2F2 B2F0 The meaning of B2Fy bit for sector y of bank 2 is given by the next Table 10 These bits are automatically reset at the end of a write operation if no errors are detected SMOD 1 IFLASH selected BOF 9 0 Bank 0 IFLASH sector 9 0 status These bits must be set during a Sector Erase operation to select the sectors to era
166. ems where more than 64 Kbytes of memory are to be access directly In addition CAN1 CAN2 and I C lines are provided e Port5is used as analog input channels of the A D converter or as timer control signals Port6 provides optional bus arbitration signals BREQ HLDA HOLD and chip select signals and the SSC1 lines If the alternate output function of a pin is to be used the direction of this pin must be programmed for output DPx y 1 except for some signals that are used directly after reset and are configured automatically Otherwise the pin remains in the high impedance state and is not effected by the alternate output function The respective port latch should hold a ky ST10F276 Parallel ports 1 because its output is ANDed with the alternate output data except for PWM output signals If the alternate input function of a pin is used the direction of the pin must be programmed for input DPx yz 0 if an external device is driving the pin The input direction is the default after reset If no external device is connected to the pin however one can also set the direction for this pin to output In this case the pin reflects the state of the port output latch Thus the alternate input function reads the value stored in the port output latch This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch On most of the port lines
167. entire characteristic It is a combination of the offset gain and integral linearity errors The different errors may compensate each other depending on the relative sign of the offset and gain errors Refer to Figure 46 see TUE Figure 46 A D conversion characteristic Offset error OFS Gain error GE 3FF 3 3FE 3FD 3FC 3FB 3FA Bisector characteristic Digital out 007 HEX 1 Ex mple of an actual transfer curve A 2 The ideal transfer curve 006 A 3 Differential Nonlinearity Error DNL n Pi n d 4 Integral Nonlinearity Error INL 005 pad eee 5 Center of a step of the actual transfer curve 6 Quantization Error 1 2 LSB 904 7 Total Unadjusted Error TUE 003 I 002 I I Li 2 3 4 5 6 7 4 1018 1020 1022 1024 001 000 L 1 VAIN LSBIDEAL lt gt Offset error OFS LSBIDEAL VAREF 1024 ST10F276 Electrical characteristics 23 7 4 23 7 5 Analog reference pins The accuracy of the A D converter depends on the accuracy of its analog reference A noise in the reference results in proportionate error in a conversion A low pass filter on the A D converter reference source supplied through pins Varer and Vaawp is recommended in order to clean the signal minimizing the noise A simple capacitive bypassing may be suffi cient in most cases in presence of high RF noise energy inductors or ferrite beads may be necessary In
168. er Minimum limit allowed for t319 is 125ns corresponding to 8Mbaud 224 229 ST10F276 Electrical characteristics Figure 69 SSC slave timing 1 tay tere tsiz tote The phase and polarity of shift and latch edge of SCLK is programmable This figure uses the leading clock edge as shift edge drawn in bold with latch on trailing edge SSCPH Ob idle clock line is low leading clock edge is low to high transition SSCPO Ob 2 The bit timing is repeated for all bits to be transmitted or received 225 229 Package information ST10F276 24 226 229 144 pin plastic quad flat package Package information 30 95 31 20 31 45 1 219 27 90 28 00 28 10 1 098 22 75 0 65 30 95 31 20 31 45 1 219 27 90 28 00 28 10 1 098 22 75 0 65 0 80 0 95 0 026 0 031 OUTLINE AND MECHANICAL DATA PQFP144 0 10mm 7 004 Seating Plane PQFP144 ST10F276 Package information Figure 71 144 pin low profile quad flat package 10x10 0 08 mm a 003 in p Seating Plane mm i
169. ernal decoding of test modes The test mode decoding logic is located inside the ST10F276 Bus Controller The decoding is as follows e Alternate Boot Mode decoding POL 5 amp POL 4 e Standard Bootstrap decoding POL 5 amp POL 4 e Normal operation POL 5 amp POL 4 The other configurations select ST internal test modes Example In the following example Alternate Boot Mode works as follows Onrising edge of RSTIN pin the reset configuration is latched e f Bootstrap Loader mode is not enabled POL 5 4 11 ST10F276 hardware proceeds with a standard hardware reset procedure e f standard Bootstrap Loader is enabled POL 5 4 10 the standard ST10 Bootstrap Loader is enabled and a variable is cleared to indicate that ABM is not enabled e f Alternate Boot Mode is selected POL 5 4 01 then depending on signatures integrity checks a predefined reset sequence is activated Selective boot mode The selective boot is a subcase of the Alternate Boot Mode When none of the signatures are correct instead of executing the standard bootstrap loader triggered by POL 4 low at reset an additional check is made Address 001 FFCh is read again with the following behavior e If value is 0000h or FFFFh a jump is performed to the standard bootstrap loader e Otherwise A High byte is disregarded Low byte bits select which communication channel is enabled ST10F276 Bootstrap loader
170. eset value 005h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XMISC XI2C XSSC XASC XPWM XFLAS XRTC XRAM2XRAM1 CAN2 CAN1 EN EN EN EN EN HEN EN EN EN EN EN Table 84 RW RW RW RW RW RW RW RW RW RW RW ESFR description Bit CAN1EN Function CAN1 enable bit 0 Accesses to the on chip CAN1 XPeripheral and its functions are disabled P4 5 and P4 6 pins can be used as general purpose l Os but address range 00 ECOOh 00 EFFFh is directed to external memory only if CAN2EN XRTCEN XASCEN XSSCEN XI2CEN XPWMEN an XMISCEN are 0 also 1 The on chip CAN1 XPeripheral is enabled and can be accessed CAN2EN CAN enable bit 0 Accesses to the on chip CAN XPeripheral and its functions are disabled P4 4 and P4 7 pins can be used as general purpose I Os but address range 00 ECOOh 00 EFFFh is directed to external memory only if CAN1EN XRTCEN XASCEN XSSCEN XI2CEN XPWMEN and XMISCEN are 0 also 1 The on chip CAN2 XPeripheral is enabled and can be accessed XRAM1EN XRAM1 enable bit 0 Accesses to the on chip 2 Kbyte XRAM are disabled Address range 00 E000h 00 E7FFh is directed to external memory 1 The on chip 2 Kbyte XRAM is enabled and can be accessed XRAM2EN XRAM2 enable bit 0 Accesses to the on chip 64 Kbyte XRAM are disabled external access performed Address range OF 0000h 0F FFFFh is directed to exter
171. espectively for each sector of the XFLASH Module see X and IFLASH module see lI The other three Registers FNVAPRO and FNVAPR1L H are used to store the Access Protection fuses common to both Flash modules even though with some limitations Flash non volatile write protection X register low FNVWPXRL 0x0E DFBO NVR Delivery value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W2PPR reserved W2P2W2P1W2PO0 RW RW RW RW Table 19 Flash non volatile write protection X register low Bit Function Write Protection Bank 2 sectors 2 0 XFLASH W2P 2 0 These bits if programmed at 0 disable any write access to the sectors of Bank 2 XFLASH Write Protection Bank 2 Non Volatile cells This bit if programmed at 0 disables any write access to the Non Volatile cells of Bank W2PPR 2 Since these Non Volatile cells are dedicated to Protection registers once W2PPR bit is set the configuration of protection setting is frozen and can only be modified executing a Temporary Write Unprotection operation 37 229 Internal Flash memory ST10F276 4 5 3 4 5 4 4 5 5 38 229 Flash non volatile write protection X register high FNVWPXRH 0x0E DF B2 NVR Delivery value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved W3P1WSPO RW RW Table 20 Flash non volatile write protection X register high Bit Function Write Protection Bank 3 Sectors 1 0 X
172. fficiently held low by the external hardware to inject a Long Hardware reset After this occurrence the initialization routine is not able to recognize a Software or Watchdog bidirectional reset event since a different source is flagged inside WDTCON register This phenomenon does not occur when internal FLASH is selected during reset EA 1 since the initialization of the FLASH itself extend the internal reset duration well beyond the filter delay Next Figures 34 35 and 36 summarize the timing for Software and Watchdog Timer Bidirectional reset events In particular Figure 36 shows the degeneration into Hardware reset 119 229 System reset ST10F276 Figure 34 SW WDT bidirectional RESET EA 1 After Filter P0 15 13 not transparent P0 12 8 transparent P0 7 2 P0 1 0 not transparent not t Y i lt 2 TCL 7 TCL IBUS CS f i Internal 1024 TCL FLARST i RSTOUT 120 229 ST10F276 System reset Figure 35 SW WDT bidirectional RESET EA 0 After Filter P0 15 13 P0 12 8 PO 7 2 PO 1 0 RSTOUT transparent D kg not transparent not transparent 1024 TCL 2 2 At this time RSTF is sampled HIGH so SW or WDT Reset is flagged in WDTCON 121 229 S
173. from XRAM No Yes Yes Yes Yes No Fetching from External No Yes Yes Yes Yes No Memory Write protection The Flash modules have one level of Write Protections each Sector of each Bank of each Flash Module can be Software Write Protected by programming at 0 the related bit WyPx of FNVWPXRH L FNVWPIRH L registers Temporary unprotection Bits WyPx of FNVWPXRH L FNVWPIRH L can be temporary unprotected by executing the Set Protection operation and writing 1 into these bits Bit ACCP can be temporary unprotected by executing the Set Protection operation and writing 1 into these bits but only if these write instructions are executed from the Flash Modules To restore the write and access protection bits it is necessary to reset the microcontroller or to execute a Set Protection operation and write O into the desired bits It is not necessary to temporary unprotect an access protected Flash in order to update the code it is in fact sufficient to execute the updating instructions from another Flash Bank In reality when a temporary unprotection operation is executed the corresponding volatile register is written to 1 while the non volatile registers bits previously written to O for a protection set operation will continue to maintain the O For this reason the User software must be in charge to track the current protection status for instance using a specific RAM area it is not possible to deduce it by reading t
174. g edge 16 5 fe ONE ns with RW delay ats Data float after RD toy SR rising edge no RW 4 tp TCL 8 5 t 2t ns delay 1 too CC Data valid to WR 10 4 tc 2TCL 15 tc ns t CC Data hold after WR 4 te TCL 8 5 tp ns ALE rising edge after tog cc RD WR g g 10 te 10 te ns Address Unlatched CS t CC hold after RD WR F ots ns togn CC Address Unlatched CS _ sate 7 igi 7 T hold after WRH 212 229 ST10F276 Electrical characteristics Table 105 Demultiplexed bus continued Fcpu 40 MHz Variable CPU clock Symbol Parameter TCL 12 5ns 1 2 TCL 1 to 64 MHz G Min Max Min Max ALE falling edge to t3g cc Latched CS 4 ta 6 t4 4 t4 6 t4 ns Latched CS low to t393 SR Valid Data In 16 5 tc 2t4 3TCL 21 tc 2t4 ns Latched CS hold after t CC RD WR 2 t TCL 10 5 te ns Address setup to tg2 CC RACS WrCS 14 4 2t 2TCL 114 2t4 ns with RW delay Address setup to 1g CC RACS WrCS 2 2t TCL 10 5 2t4 ns no RW delay RdCS to Valid Data In tag SR with RW delay 4 lc 2TCL 21 tc ns RdCS to Valid Data In t4 SR no RW delay 16 5 tc 3TCL 21 tc ns RdCS WrCS low time tag CC with RW delay 15 5 te 2TCL 9 5 tc ns RdCS WrCS low time tag CC no RW delay 28 tc STCL 9 5 tc ns tgo CC Data val
175. gister Bit Function Wait state setting These three bits are the binary coding of the number of wait states introduced by the XFLASH interface through the XBUS internal READY signal Default value after reset WS 3 0 is 1111 that is the up to 15 wait states are set The following recommendations for the ST10F276 are hereafter reported For fopy gt 40MHz1 Wait StateWS 3 0 0001 For fcpy 40MHz0 Wait StateWS 3 0 0000 36 229 ST10F276 Internal Flash memory 4 5 4 5 1 4 5 2 Protection strategy The protection bits are stored in Non Volatile Flash cells inside XFLASH module that are read once at reset and stored in 7 Volatile registers Before they are read from the Non Volatile cells all the available protections are forced active during reset The protections can be programmed using the Set Protection operation see Flash Control Registers paragraph that can be executed from all the internal or external memories except from the Flash Bank B2 Two kind of protections are available write protections to avoid unwanted writings and access protections to avoid piracy In next paragraphs all different level of protections are shown and architecture limitations are highlighted as well Protection registers The 7 Non Volatile Protection Registers are one time programmable for the user Four registers FNVWPXRL H FNVWPIRL H are used to store the Write Protection fuses r
176. gister 0000h CAN1TR EFOAh CAN1 Test register 00x0h CAN1TR1 EF80h CAN1 Transmission request 1 0000h CAN1TR2 EF82h CAN1 Transmission request 2 0000h CAN2BRPER EEOCh CAN2 BRP extension register 0000h CAN2BTR EEO6h CAN2 Bit timing register 2301h CAN2CR EEO0h CAN2 CAN control register 0001h CAN2EC EEO4h CAN2 Error counter 0000h CAN2IF1A1 EE18h CAN2 IF1 arbitration 1 0000h CAN2IF1A2 EE1Ah CAN2 IF1 arbitration 2 0000h CAN2IF1CM EE12h CAN2 IF1 command mask 0000h CAN2IF1CR EE10h CAN2 IF1 command request 0001h CAN2IF1DA1 EE1Eh CAN2 IF1 data A 1 0000h CAN2IF1DA2 EE20h CAN2 IF1 data A2 0000h CAN2IF1DB1 EE22h CAN2 IF1 data B 1 0000h CAN2IF1DB2 EE24h CAN2 IF1 data B2 0000h CAN2IF1M1 EE14h CAN2 IF1 mask 1 FFFFh CAN2IF1M2 EE16h CAN2 IF1 mask 2 FFFFh CAN2IF1MC EE1Ch CAN2 IF1 message control 0000h CAN2IF2A1 EE48h CAN2 IF2 arbitration 1 0000h CAN2IF2A2 EE4Ah CAN2 IF2 arbitration 2 0000h 154 229 ky ST10F276 Register set Table 69 X Registers ordered by name continued Physical Name address Description Reset value CAN2IF2CM EE42h CAN2 IF2 command mask 0000h CAN2IF2CR EE40h CAN2 IF2 command request 0001h CAN2IF2DA1 EE4Eh CAN2 IF2 data A 1 0000h CAN2IF2DA2 EE50h CAN2 IF2 data A 2 0000h CAN2IF2DB1 EE52h CAN2 IF2 data B 1 0000h CAN2IF2DB2 EE54h CAN2 IF2 data B 2 0000h CAN2IF2M1 EE44h CAN2
177. h 64 MHz CPU clock and lt SSCBRP gt set to 8h or with 48 MHz CPU clock and SSCBR set to 2h When 40 MHz CPU clock is used the maximum baud rate cannot be higher than 6 6Mbaud lt SSCBR gt 2h due to the limited granularity of lt SSCBR gt Value 1h for lt SSCBR gt may be used only with CPU clock equal to or lower than 32 MHz after checking that timings are in line with the target slave 2 Formula for SSC Clock Cycle time o 4 TCL x SSCBR 1 Were SSCBRS represents the content of the SSC baud rate register taken as unsigned 16 bit integer Minimum limit allowed for tg99 is 125ns corresponding to 8Mbaud 222 229 ST10F276 Electrical characteristics Figure 68 SSC master timing tg07 taog t307 tg08 lt gt lt lt gt gt 1 The phase and polarity of shift and latch edge of SCLK is programmable This figure uses the leading clock edge as shift edge drawn in bold with latch on trailing edge SSCPH Ob idle clock line is low leading clock edge is low to high transition SSCPO Ob 2 The bit timing is repeated for all bits to be transmitted or received 223 229 Electrical characteristics ST10F276 Slave mode Vpp 5V 10 Vss OV Ta 40 to 125 C C 50pF Table 109 Slave mode Max baud rate 6 6 MBd GFcpy 40 MHz Variable baud rate lt SSCBR gt 0001h Symb
178. h base addresses differing in address bit A8 separate chip select for each CAN module Refer to Chapter 4 Internal Flash memory e The CANI transmit line CAN1_TxD is the alternate function of the Port P4 6 pin and the receive line CAN1_RxD is the alternate function of the Port P4 5 pin e The CAN transmit line CAN2 TxD is the alternate function of the Port P4 7 pin and the receive line CAN2_RxD is the alternate function of the Port P4 4 pin e Interrupt request lines of the CAN1 and CAN2 modules are connected to the XBUS interrupt lines together with other X Peripherals sharing the four vectors e The CAN modules must be selected with corresponding CANXxEN bit of XPERCON register before the bit XPEN of SYSCON register is set e The reset default configuration is CAN1 enabled CAN2 disabled If one or both CAN modules is used Port 4 cannot be programmed to output all 8 segment address lines Thus only four segment address lines can be used reducing the external memory space to 5 Mbytes 1 Mbyte per CS line Configuration support It is possible that both CAN controllers are working on the same CAN bus supporting together up to 64 message objects In this configuration both receive signals and both transmit signals are linked together when using the same CAN transceiver This configuration is especially supported by providing open drain outputs for the CAN1_Txd and CAN2 TxD signals The open drain function is controlled with
179. hange the Xperipherals selections through a specific code Software aspects As the CAN1 is needed XPERCON register is configured by the bootstrap loader code and bit XPEN of SYSCON is set However as long as the EINIT instruction is not executed and it is not in the bootstrap loader code the settings can be modified To do this perform the following steps e Disable the XPeripherals by clearing XPEN in SYSCON register Attention If this part of the code is located in XRAM it will be disabled e Enable the needed XPeripherals by writing the correct value in XPERCON register e Set XPEN bit in SYSCON ST10F276 Bootstrap loader 5 5 2 5 6 5 6 1 5 6 2 Note 5 6 3 Hardware aspects Although the new bootstrap loader is designed to be compatible with the old bootstrap loader there are a few hardware requirements for the new bootstrap loader as summarized in Table 34 Table 34 Hardware topics summary Actual bootstrap loader New bootstrap loader Comments P4 5 cannot be used as user output TT D CAN DE SEd AS OUTPUT in BSL mode but only as CAN1_RxD BSL mode or input or address segments Level on CAN1_RxD can Level on CAN1_RxD must be stable External pull up on P4 5 change during boot Step 2 at 1 during boot Step 2 needed Alternate boot mode ABM Activation Alternate boot is activated with the combination 01 on PortOL 5 4 at the rising edge of R
180. he non volatile register content a temporary unprotection cannot be detected 41 229 Internal Flash memory ST10F276 4 6 Write operation examples In the following examples for each kind of Flash write operation are presented Word program Example 32 bit Word Program of data OXAAAAAAAA at address 0x0C5554 in XFLASH Module FCROH 0x2000 Set WPG in FCROH FARL 0x5554 Load Add in FARL FARH 0x000C Load Add in FARH FDROL OxAAAA Load Data in FDROL FDROH OxAAAA Load Data in FDROH FCROH 0x8000 Operation start Double word program Example Double Word Program 64 bit of data Ox55AA55AA at address 0x095558 and data OxAA55AA55 at address 0x09555C in IFLASH Module FCROH 0x1080 Set DWPG SMOD FARL 0x5558 Load Add in FARL FARH 0x0009 Load Add in FARH FDROL 0x55AA Load Data in FDROL FDROH 0x55AA Load Data in FDROH FDR1L 0xAA55 Load Data in FDR1L FDR1H 0xAA55 Load Data in FDR1H FCROH 0x8000 Operation start Double Word Program is always performed on the Double Word aligned on a even Word bit ADD2 of FARL is ignored Sector erase Example Sector Erase of sectors B3F1 and B3F0 of Bank 3 in XFLASH Module FCROH 0x0800 Set SER in FCROH FCR1H 0x0003 Set B3F1 B3F0 FCROH 0x8000 Operation start Suspend and resume Word Program Double Word Program and Sector Erase
181. iation Error Reload Value hex hex 1 250 000 0 0 0 0 0000 0000 833 333 0 0 0 0 0000 0000 112 000 1 5 7 0 000A 000B 112 000 6 3 7 0 0006 0007 56 000 1 5 3 0 0015 0016 56 000 6 396 0 8 000D 000E 38 400 1 7 1 4 001F 0020 38 400 3 3 1 4 0014 0015 19 200 0 2 1 496 0040 0041 19 200 0 9 1 496 002A 002B 9 600 0 2 0 6 0081 0082 9 600 0 9 0 2 0055 0056 4 800 0 2 0 2 0103 0104 4 800 0 4 0 2 00AC 00AD 2 400 0 2 0 0 0207 0208 2 400 0 1 0 2 015A 015B 1200 0 1 0 0 0410 0411 1 200 0 1 0 1 02B5 02B6 600 0 0 0 0 0822 0823 600 0 1 0 0 056B 056C 300 0 0 0 0 1045 1046 300 0 0 0 0 OAD8 OAD9 153 0 0 0 0 1FE8 1FE9 102 0 0 0 0 1FE8 1FE9 94 229 ky ST10F276 Serial channels Table 53 ASC asynchronous baud rates by reload value and deviation errors fcpy 64 MHz SOBRS 0 fcpy 64 MHz SOBRS 1 fcpy 64 MHz Baud Rate Baud Deviation Error ncc m Baud Rate Baud Deviation Error i 2 000 000 0 0 0 0 0000 0000 1 333 333 0 0 0 0 0000 0000 112 000 1 5 7 0 0010 0011 112 000 6 3 7 096 000A 000B 56 000 1 5 3 0 0022 0023 56 000 6 3 0 8 0016 0017 38 400 1 7 1 4 0033 0034 38 400 3 3 1 4 0021 0022 19 200 0 2 1 4 006
182. id to WrCS 10 4 tc 2TCL 15 tc ns ts SR Data hold after RACS 0 0 ns ts3 SR Data loat ahar PACS 16 5 te 2TCL 8 5 t ns with RW delay Data float after RdCS tes SR no RW delay 4 tp TCL 8 5 tp ns Address hold after RdCS WrCS tg CC Data hold after WrCS 24 tr TCL 10 5 t ns tes CC 8 5 te 854 tr ns 1 RW delay and t refer to the next following bus cycle 2 Read data is latched with the same clock edge that triggers the address change and the rising RD edge Therefore address changes which occur before the end of RD have no impact on read cycles The following figures Figure 57to Figure 64 present the different configurations of external memory cycle 213 229 Electrical characteristics ST10F276 Figure 61 Demultiplexed bus with without read write delay and normal ALE l CLKOUT ANASA Neu N ANAN l al tie gt n lo ALE i l i i CSx A23 A16 A15 A0 P1 Address BHE l l l l lig Read cycle i Data Bus P0 Data In K gt D15 D8 D7 DO CE ppm o 4 Un latched CSx t414 t TCU 210 5 tg l i l EN m tso t loo 1g gt lt l tis gt E t21 gt i l RD l l l l l l Write cycle l l i i D15 D8 D7 DO l La lao l i i La loo gt t Cei I l t ol WR cee ae RERUM WPL pre r l WRH l t l
183. ie pda 57 5 4 2 Entering the CAN bootstrap loader llli eese 58 5 4 8 ST10 configuration in CAN BSL 21 eee 59 5 4 4 Loading the start up code via CAN 0000 eee eee eee 59 5 4 5 Choosing the baud rate for the BSL via CAN 005 60 5 4 6 Computing the baud rate error 2 ees 63 5 4 7 Bootstrap via CAN ssssssseee eee 63 5 5 Comparing the old and the new bootstrap loader 64 5 5 1 Software aspects 0 0 cee ees 64 5 5 2 Hardware aspects 0c eee ree 65 ky 3 229 Contents ST10F276 5 6 X Alternate boot mode ABM 00 0c eee eee 65 5 6 1 Activation m 65 5 6 2 Memory mapping isaac sirrin soniri RR IRI III 65 5 6 3 Interr pts eeu ec uer ep eke See ERE Hx a m FERE ER 65 5 6 4 ST10 configuration in alternate boot mode 0000 eae 66 5 6 5 Watchdog cgo sss ak Ee E EEG 4 uere EP ex qa ee Eq EE 66 5 6 6 Exiting alternate boot mode 0 2 eee ees 66 5 6 7 Alternate boot user software 00 cece eee eee 67 5 6 8 User alternate mode signature integrity check 67 5 6 9 Alternate boot user software aspects 00 e cee eee eee 67 5 6 10 EMUCON register 0 000 tee 67 5 6 11 Internal decoding of test modes naana 68 5 6 12 Example iioi Vide Maw ihe ve ida ee hee E aa chm Eq 68 5 7 Selective boot moUdB 22i o4 EOS Red rc dc ca ed eee aed 68
184. iguration and enable the bus interface to store the received data into external memory 55 229 Bootstrap loader ST10F276 5 3 5 Note 56 229 This process may go through several iterations or may directly execute the final application In all cases the ST10F276 still runs in BSL mode that is with the watchdog timer disabled and limited access to the internal Flash area All code fetches from the internal IFLASH area 01 0000 08 FFFF are redirected to the special Test Flash Data read operations access the internal Flash of the ST10F276 Choosing the baud rate for the BSL via UART The calculation of the serial baud rate for ASCO from the length of the first zero byte that is received allows the operation of the bootstrap loader of the ST10F276 with a wide range of baud rates However the upper and lower limits must be kept to ensure proper data transfer NER ST10F276 32 SOBRL 1 The ST10F276 uses timer T6 to measure the length of the initial zero byte The quantization uncertainty of this measurement implies the first deviation from the real baud rate the next deviation is implied by the computation of the SOBRL reload value from the timer contents The formula below shows the association T6 36 72 SOBRL For a correct data transfer from the host to the ST10F276 the maximum deviation between the internal initialized baud rate for ASCO and the real baud rate of the host should be below 2 5 Th
185. in and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2006 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Ti 229 229
186. in ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock ts depend on programming and can be taken from Table 94 5 This parameter includes the sample time ts the time for determining the digital result and the time to load the result register with the conversion result Values for the conversion clock tcc depend on programming and can be taken from next Table 94 a 185 229 Electrical characteristics ST10F276 23 7 1 186 229 6 DNL INL OFS and TUE are tested at Varer 5 0V Vagnp OV Vpp 5 0V It is guaranteed by design characterization for all other voltages within the defined voltage range LSB has a value of Vaper 1024 For Port5 channels the specified TUE 2LSB is also guaranteed with an overload condition see loy specification occurring on a maximum of 2 not selected analog input pins of Port5 and the absolute sum of input overload currents on all Port5 analog input pins does not exceed 10 mA For Port1 channels the specified TUE is guaranteed when no overload condition is applied to Port1 pins When an overload condition occurs on a maximum of 2 not selected analog input pins of Port1 and the input positive overload current on all analog input pins does not exceed 10 mA either dynamic or static injection the specified TUE is degraded 7LSB To obtain the same accuracy the negative injection current on Porti pins sh
187. ined memory location in Test Flash controlled by ST e Alternate boot mode Jump to address 09 0000h e Selective bootstrap loader Jump to a predefined location in Test Flash controlled by ST and check which communication channel is selected User code Make a software reset and jump to 00 0000h ST10F276 Bootstrap loader Table 28 ST10F276 boot mode selection P0 5 P0 4 ST10 decoding 1 1 User mode User Flash mapped at 00 0000h 1 0 Standard bootstrap loader User Flash mapped from 00 0000h code fetches redirected to Test Flash at 00 0000h 0 1 Alternate boot mode Flash mapping depends on signatures integrity check 0 0 Reserved 5 2 Standard bootstrap loader The built in bootstrap loader of the ST10F276 provides a mechanism to load the startup program which is executed after reset via the serial interface In this case no external ROM memory or an internal ROM is required for the initialization code starting at location 00 0000 The bootstrap loader moves code data into the IRAM but it is also possible to transfer data via the serial interface into an external RAM using a second level loader routine ROM memory internal or external is not necessary However it may be used to provide lookup tables or may provide core code that is a set of general purpose subroutines such as for I O operations number crunching or system initialization The Bootstrap Loader can load e the complete ap
188. ister 2 0000h PP3 FOSEh E 1Fh PWM module period register 3 0000h T7 F050h E 28h CAPCOM timer 7 register 0000h T8 F052h E 29h CAPCOM timer 8 register 0000h T7REL F054h E 2Ah CAPCOM timer 7 reload register 0000h T8REL Fo56h E 2Bh CAPCOM timer 8 reload register 0000h IDPROG F078h E 3Ch Programming voltage identifier register 0040h IDMEM FO7Ah E 3Dh On chip memory identifier register 30D0h IDCHIP FO7Ch E 3Eh Device identifier register n is the device revision 114nh IDMANUF FO7Eh E 3Fh Manufacturer identifier register 0403h ky ST10F276 Register set Table 68 Special function registers ordered by address continued Name harees addross Description value ADDAT2 FOAOh E 50h A D converter 2 result register 0000h SSCTB FOBOh E 58h SSC transmit buffer write only 0000h SSCRB FOB2h E 59h SSC receive buffer read only XXXXh SSCBR FOB4h E 5Ah SSC baud rate register 0000h DPOL b Fi00h E 80h POL direction control register 00h DPOH b Fi02h E 81h POH direction control register 00h DP1L b F104h E 82h P1L direction control register 00h DP1H b F106h E 83h P1H direction control register 00h RPOH b F108h E 84h System start up configuration register read only XXh CC16IC b F160h E BOh CAPCOM register 16 interrupt control register 00h CC171C b Fi6 2h E Bth CAPCOM register 17 interrupt
189. it field name xplanation of bit field name Description of the functions controlled by this bit field A byte register is displayed as REG NAME A16h A8h SFR ESFR XBUS Reset value h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 std bithw bit bit field bit field Elements REG NAME This register s name A16h A8h Long 16 bit address Short 8 bit address SFR ESFR XBUS Register space SFR ESFR or XBUS Register Register contents after reset 0 1 defined X undefined undefined X after power up U unchanged hwbit Bit that is set cleared by hardware is written in bold ST10F276 Register set 22 2 General purpose registers GPRs The GPRs form the register bank that the CPU works with This register bank may be located anywhere within the internal RAM via the Context Pointer CP Due to the addressing mechanism GPR banks reside only within the internal RAM All GPRs are bit addressable Table 65 General purpose registers GPRs Name Physical An Description oed address ss value RO CP FOh CPU general purpose word register RO UUUUh R1 CP Fih CPU general purpose word register R1 UUUUh R2 CP F2h CPU general purpose word register R2 UUUUh R3 CP F3h CPU general purpose word register R3 UUUUh R4 CP 4 8 F4h CPU general purpose word register R4 UUUUh R5 CP 1
190. it is integrated on chip An automatic self calibration adjusts the A D converter module to process parameter variations at each reset event The sample time for loading the capacitors and the conversion time is programmable and can be adjusted to the external circuitry The ST10F273E has 1648 multiplexed input channels on Port 5 and Port 1 The selection between Port 5 and Port 1 is made via a bit in a XBus register Refer to the User Manual for a detailed description A different accuracy is guaranteed Total Unadjusted Error on Port 5 and Port 1 analog channels with higher restrictions when overload conditions occur in particular Port 5 channels are more accurate than the Port 1 ones Refer to Electrical Characteristic section for details The A D converter input bandwidth is limited by the achievable accuracy supposing a maximum error of 0 5LSB 2mV impacting the global TUE TUE depends also on other causes in worst case of temperature and process the maximum frequency for a sine wave analog signal is around 7 5 kHz Of course to reduce the effect of the input signal variation on the accuracy down to 0 05LSB the maximum input frequency of the sine wave shall be reduced to 800 Hz If static signal is applied during sampling phase series resistance shall not be greater than 20kQ this taking into account eventual input leakage It is suggested to not connect any capacitance on analog input pins in order to reduce the effect of ch
191. l Then the ST10F276 is immediately after the input filter delay forced in reset default state It pulls low RSTOUT pin it cancels pending internal hold states if any it aborts all internal external bus cycles it switches buses data address and control signals and I O pin drivers to high impedance it pulls high PortO pins If an asynchronous reset occurs during a read or write phase in internal memories the content of the memory itself could be corrupted to avoid this synchronous reset usage is strongly recommended Power on reset The asynchronous reset must be used during the power on of the device Depending on crystal or resonator frequency the on chip oscillator needs about 1ms to 10ms to stabilize Refer to Electrical Characteristics Section with an already stable Vpp The logic of the ST10F276 does not need a stabilized clock signal to detect an asynchronous reset so it is suitable for power on conditions To ensure a proper reset sequence the RSTIN pin and the RPD pin must be held at low level until the device clock signal is stabilized and the system configuration value on Porto is settled At Power on it is important to respect some additional constraints introduced by the start up phase of the different embedded modules In particular the on chip voltage regulator needs at least 1ms to stabilize the internal 1 8V for the core logic this time is computed from when the external reference Vpp becomes stable inside sp
192. l 50 250 kQ lawH Read Write inactive current 7 vg 2 4 V 40 law Read Write active current 68 Vout 0 4V 500 lALEL ALE inactive current 9 7 Vout 0 4V 20 lALEH ALE active current 8 Vout 24V 300 Port 6 inactive current uA IPeH Pe 4 0 6 Vout 2 4 V c 40 lPeL Port 6 active current P6 4 0 9 8 Voyy 0 4V 500 leon 9 Vin 2 0V 10 PORTO configuration current 6 leo Vin 0 8V 100 Pin capacitance 4 6 Co Cc digital inputs outputs iQ pF Run mode power supply current E E loot execution from internal RAM 20 2fcpu mA Run mode power supply current loce 4 19 execution from internal 20 1 8fopy mA Flash lip Idle mode supply current 1 20 0 6fcpu mA Power Down supply current 12 Ipp1 RTC off oscillators off TA 25 C 1 mA main voltage regulator off Power Down supply current 12 Ipp2 RTC on main oscillator on Ta 25 C 8 mA main voltage regulator off Power down supply current 12 Ipp3 RTC on 32 kHz oscillator on Ta 25 C 1 1 mA main voltage regulator off Stand by supply current 12 Ta Ty 25 C 250 uA Isp1 RTC off Oscillators off VDD off VSTBY on Vstpy 5 5V 500 uA Ta Tj 125 C Stand by supply current 12 nc 250C 250 uA Ispe RTC on 32 kHz Oscillator on main VDD off VSTBY on Vstpy 5 5V 500 uA Ta 125 C L 4 12 Ga Stand by supply current B B 25 m 180 229 VDD transient condition
193. l of the selected channels are repeatedly sampled and converted The result of the conversion is stored in the ADDAT ky ST10F276 A D converter register The data can be transferred to the RAM by interrupt software management or using the PEC data transfer e Waitfor ADDAT read mode When using continuous modes in order to avoid to overwrite the result of the current conversion by the next one the ADWR bit of ADCON control register must be activated Then until the ADDAT register is read the new result is stored in a temporary buffer and the conversion is on hold e Channel injection mode When using continuous modes a selected channel can be converted in between without changing the current operating mode The 10 bit data of the conversion are stored in ADRES field of ADDAT2 The current continuous mode remains active after the single conversion is completed A full calibration sequence is performed after a reset This full calibration lasts up to 40 630 CPU clock cycles During this time the busy flag ADBSY is set to indicate the operation It compensates the capacitance mismatch so the calibration procedure does not need any update during normal operation No conversion can be performed during this time the bit ADBSY shall be polled to verify when the calibration is over and the module is able to start a convertion Ti 93 229 Serial channels ST10F276 14 Serial channels Serial communication with other
194. l parameters and on a hypothesis on the characteris tics of the analog signal to be sampled ST10F276 Electrical characteristics 23 7 6 Example of external network sizing The following hypothesis is formulated in order to proceed with designing the external net work on A D converter input pins Analog signal source bandwidth fo 10 kHz Conversion rate fc 25 kHz Sampling time Ts ius Pininput capacitance Cp 5pF Pin input routing capacitance Cpo 1pF Sampling capacitance Cs 4pF Maximum input current injection lij 3mA Maximum analog source voltage Vay 12V Analog source impedance Rs 1000 Channel switch resistance Rsw 5000 Sampling switch resistance Rap 2000 1 Supposing to design the filter with the pole exactly at the maximum frequency of the signal the time constant of the filter is RoC 1 GEF 2ni 15 9us 2 Using the relation between Cp and Cg and taking some margin 4000 instead of 2048 it is possible to define Cp Cp 4000 16nF 3 Asaconsequence of Step 1 and 2 RC can be chosen Re L 9950 1kQ 2TfgCE 4 Considering the current injection limitation and supposing that the source can go up to 12V the total series resistance can be defined as V Rg Re Ri 4kQ INJ from which is now simple to define the value of R_ v R a Rp Rg 2 9kQ INJ Now the three elements of the external circuit RE Cp an
195. latile access protection reg 0 ACFFh ENVAPRIL 0x000E DFBC dnd nonvolatile access protection reg 1 FFFFh FNVAPR1H 0x000E DEBE os nonvolatile access protection reg 1 FFFFh XFICR OxOOOE E000 XFlash interface control register 000Fh 164 229 ky ST10F276 Register set 22 9 Identification registers The ST10F276 have four Identification registers mapped in ESFR space These registers contain the manufacturer identifier the chip identifier with revision number the internal Flash and size identifier the programming voltage description IDMANUF F07Eh 3Fh ESFR Reset value 0403h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MANUF 0 0 0 1 1 R Table 73 MANUF description Bit Function Manufacturer identifier MANUF M 020h STMicroelectronics manufacturer JTAG worldwide normalization IDCHIP FO7Ch 3Eh ESFR Reset value 114xh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDCHIP REVID R R Table 74 IDCHIP description Bit Function Device identifier IDCHIP M 114h ST10F276 Identifier 276 REVID Device IS VISION identifier Xh According to revision number IDMEM F07Ah 3Dh ESFR Reset value 30DOh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MEMTYP MEMSIZE R R 165 229 Register set ST10F276 Note 166 229 Table 75 IDMEM description Bit Function Internal memory size MEMSIZE Internal Memory size is
196. le Not 100 tested guaranteed by design characterization Table 92 Data retention characteristics Data retention time Number of program erase average ambient temperature 60 C cycles 40 C lt TA x 125 C 832 Kbyte 64 Kbyte code store EEPROM emulation 0 100 gt 20 years gt 20 years 1000 gt 20 years 10000 10 years 100000 1 year 1 Two 64 Kbyte Flash Sectors may be typically used to emulate up to 4 8 or 16 Kbytes of EEPROM Therefore in case of an emulation of a 16 Kbyte EEPROM 100000 Flash Program Erase cycles are equivalent to 800000 EEPROM Program Erase cycles For an efficient use of the Read While Write feature and or EEPROM Emulation please refer to dedicated Application Note document AN2061 EEPROM Emulation with ST10F2xx Contact your local field service local sales person or STMicroelectronics representative to obtain a copy of such a guideline document 184 229 ST10F276 Electrical characteristics 23 7 A D converter characteristics Vpp 5V 1096 Vgs OV Ta 40 to 125 C 4 5V Varer Vpp Vss lt VAGND lt Vss 0 2V Table 93 A D converter characteristics Limit values Symbol Parameter Test condition Unit Min Max VangrSR Analog reference voltage 4 5 Vpp VaGNp9H Analog ground voltage Vss Vss 0 2 V Vain SR Analog Input voltage VAGND VanEF Running mode 5 mA langp CC
197. llator u mge Normal run 8 17 30 Vosc32__ Oscillation amplitude 9 Peak to peak 0 5 1 0 2 4 Vav3e Oscillation voltage level Sine wave middle 0 7 0 9 1 2 tstyp32__ Oscillator start up time Stable Vpp 1 5 s 1 At power on a high current biasing is applied for faster oscillation start up Once the oscillation is started the current biasing is reduced to lower the power consumption of the system 2 Not 100 tested guaranteed by design characterization ST10F276 Electrical characteristics 23 8 15 Figure 55 32 kHz crystal oscillator connection diagram ST10F276 Crystal t F3 m CA Ca Table 101 Minimum values of negative resistance module Ca 6pF CA 12pF Ca 15pF Ca 18pF Ca 22pF CA 27pF Ca 33pF 32 kHz 150 kQ 120 kQ 90 kW The given values of C4 do not include the stray capacitance of the package and of the printed circuit board The negative resistance values are calculated assuming additional 5pF to the values in the table The crystal shunt capacitance Co the package and the stray capacitance between XTAL3 and XTAL4 pins is globally assumed equal to 4pF The external resistance between XTAL3 and XTALA is not necessary since already present on the silicon Warning Direct driving on XTALS pin is not supported Always use a 32 kHz crystal oscillator External clock drive XTAL 1 When Direct Drive configuration is
198. mci External lt Reset Source 7 RO 7 Open Drain Inverter RPD __ zm C0 ST10F276 ZZ Figure 39 Internal simplified reset circuitry EINIT Instruction Clr a RSTOUT Set Reset State Machine Clock Vpp m Trigger SRST instruction nternal tchd rfl Reset sabe MSIE J RSTIN Signal Clr 124 229 BDRSTEN Reset Sequence _ 512 CPU Clock Cycles Asynchronous Reset From to Exit Powerdown Circuit ZZ g w Weak Pulldown 200pA ST10F276 System reset 19 8 Reset application examples Next two timing diagrams Figure 40 and Figure 41 provides additional examples of bidirectional internal reset events Software and Watchdog including in particular the external capacitances charge and discharge transients refer also to Figure 38 for the external circuit scheme Figure 40 Example of software or watchdog bidirectional reset EA 1 X E S 5 S ui 4 eA le i la Leia lk et a tee ner S gt x lt T 2 A i E 9 9 S oO D c t en Q O o Q Q Q L4 c amp E o o o o g o9 E E E S S S a a a 2 2 2 E x X x Q 4 BOR oil liane ac cs a eene r UMM amp 1 4 amp z R a E e o e t Vy Lr ee S als a pats 5 2 ad i2 EV E S amp E eir 1 R4 V 2 A f 5 T t 2 Eu o gs a S a g S 5
199. me and date for the system e Cyclic time based interrupt on Port2 external interrupts every RTC basic clock tick and after n RTC basic clock ticks n is programmable if enabled e 58 bit timer for long term measurement e Capability to exit the ST10 chip from Power down mode if PWDCFG of SYSCON set after a programmed delay The real time clock is based on two main blocks of counters The first block is a prescaler which generates a basic reference clock for example a 1 second period This basic reference clock is coming out of a 20 bit DIVIDER This 20 bit counter is driven by an input clock derived from the on chip CPU clock pre divided by a 1 64 fixed counter This 20 bit counter is loaded at each basic reference clock period with the value of the 20 bit PRESCALER register The value of the 20 bit RTCP register determines the period of the basic reference clock A timed interrupt request RTCSI may be sent on each basic reference clock period The second block of the RTC is a 32 bit counter that may be initialized with the current system time This counter is driven with the basic reference clock signal In order to provide an alarm function the contents of the counter is compared with a 32 bit alarm register The alarm register may be loaded with a reference date An alarm interrupt request RTCAI may be generated when the value of the counter matches the alarm register The timed RTCSI and the alarm RTCAI interrupt requests c
200. microcontrollers microprocessors terminals or external peripheral components is provided by up to four serial interfaces two asynchronous synchronous serial channels ASCO and ASC1 and two high speed synchronous serial channel SSCO and SSC1 Dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning For transmission reception and erroneous reception separate interrupt vectors are provided for ASCO and SSCO serial channel A more complex mechanism of interrupt sources multiplexing is implemented for ASC1 and SSC1 XBUS mapped 14 1 Asynchronous synchronous serial interfaces The asynchronous synchronous serial interfaces ASCO and ASC1 provides serial communication between the ST10F276 and other microcontrollers microprocessors or external peripherals 14 2 ASCx in asynchronous mode In asynchronous mode 8 or 9 bit data transfer parity generation and the number of stop bits can be selected Parity framing and overrun error detection is provided to increase the reliability of data transfers Transmission and reception of data is double buffered Full duplex communication up to 2M Bauds at 64 MHz of fcpy is supported in this mode Table 52 ASC asynchronous baud rates by reload value and deviation errors fcpy 40 MHz SOBRS 0 fcpy 40 MHz SOBRS 1 fcpy 40 MHz Baud Rate Baud Deviation Error Reload Value Baud Rate Baud Dev
201. must be set Leaving the main voltage regulator active during Power Down may lead to unexpected behavior ex CPU wake up and power consumption higher than what specified Protected power down mode This mode is selected when PWDCFG bit 5 of SYSCON register is cleared The Protected Power Down mode is only activated if the NMI pin is pulled low when executing PWRDN instruction this means that the PWRD instruction belongs to the NMI software routine This mode is only deactivated with an external hardware reset on RSTIN pin Interruptible power down mode This mode is selected when PWDCFG bit 5 of SYSCON register is set The Interruptible Power Down mode is only activated if all the enabled Fast External Interrupt pins are in their inactive level This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt request applied to one of the Fast External Interrupt pins or with an interrupt generated by the Real Time Clock or with an interrupt generated by the activity on CAN s and IC module interfaces To allow the internal PLL and clock to stabilize the RSTIN pin must be held low according the recommendations described in Chapter 19 System reset An external RC circuit must be connected to RPD pin as shown in the Figure 43 Figure 43 External RC circuitry on RPD pin V ST10F276 29 RO 220k minimum RPD 3 d CO 7 1uF Typical To exit Power Down m
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203. n be selected instead of the standard TTL thresholds for all the pins These CMOS thresholds are defined above the TTL thresholds and feature a higher hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds The Port Input Control registers PICON and XPICON are used to select these thresholds for each Byte of the indicated ports this means the 8 bit ports POL POH P1L P1H P4 P7 and P8 are controlled by one bit each while ports P2 P3 and P5 are controlled by two bits each All options for individual direction and output mode control are available for each pin independent of the selected input threshold Alternate port functions Each port line has one associated programmable alternate input or output function e PORTO and PORT1 may be used as address and data lines when accessing external memory Besides PORT1 provides also Input capture lines 8 additional analog input channels to the A D converter Port2 Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAPCOM units and or with the outputs of the PWMO module of the PWM1 module and of the ASC1 Port 2 is also used for fast external interrupt inputs and for timer 7 input e Port3 includes the alternate functions of timers serial interfaces the optional bus control signal BHE and the system clock output CLKOUT e Port 4 outputs the additional segment address bit A23 A16 in syst
204. n in the output noise spectrum while the flicker noise in a 1 89 Assuming a noiseless PLL input and supposing that the VCO is dominated by its 1 f noise the R M S value of the accumulated jitter is proportional to the square root of N where N is the number of clock 199 229 Electrical characteristics ST10F276 200 229 periods within the considered time interval On the contrary assuming again a noiseless PLL input and supposing that the VCO is dominated by its 1 f noise the R M S value of the accumulated jitter is proportional to N where N is the number of clock periods within the considered time interval The jitter in the PLL loop can be modelized as dominated by the i1 f noise for N smaller than a certain value depending on the PLL output frequency and on the bandwidth characteristics of loop Above this first value the jitter becomes dominated by the i1 f noise component Lastly for N greater than a second value of N a saturation effect is evident so the jitter does not grow anymore when considering a longer time interval jitter stable increasing the number of clock periods N The PLL loop acts as a high pass filter for any noise in the loop with cutoff frequency equal to the bandwidth of the PLL The saturation value corresponds to what has been called self referred long term jitter of the PLL In Figure 53 the maximum jitter trend versus the number of clock periods N for some typical CPU frequencies is shown The cu
205. n operating conditions concerning the usage of A D converter refer to Section 23 7 Power considerations The average chip junction temperature Tj in degrees Celsius is calculated using the following equation Ty Ta Pp x Oya 1 Where Ta is the Ambient Temperature in C Oya is the Package Junction to Ambient Thermal Resistance in C W Pp is the sum of Piyt and Pio Pp Pint Pro Pint is the product of lpp and Vpp expressed in Watt This is the Chip Internal Power Pyo represents the Power Dissipation on Input and Output Pins user determined Most often in applications Pyo Pint which may be ignored On the other hand Pyo may be significant if the device is configured to continuously drive external modules and or memories An approximate relationship between Pp and Ty if Pio is neglected is given by Pp K Tj 273 C 2 Therefore solving equations 1 and 2 K Pp x Ta 273 C Oj x Pp 3 Where K is a constant for the particular part which may be determined from equation 3 by measuring Pp at equilibrium for a known T Using this value of K the values of Pp and Ty are obtained by solving equations 1 and 2 iteratively for any value of Ty Table 88 Thermal characteristics Symbol Description Value typical Unit Thermal resistance junction ambient PQFP 144 28 x 28 x 3 4 mm 0 65 mm pitch 30 OJA LQFP 144 20 x 20 mm 0 5 mm pitch 40 C W LQFP 144 20 x 20 mm 0 5 mm pitch on four l
206. nal memory only if XFLASHEN is 0 also 1 The on chip 64 Kbyte XRAM is enabled and can be accessed 172 229 ST10F276 Register set Table 84 ESFR description continued Bit Function RTC enable 0 Accesses to the on chip RTC module are disabled external access performed XRTCEN Address range 00 EDOOh OO EDFF is directed to external memory only if CAN1EN CAN2EN XASCEN XSSCEN XI2CEN XPWMEN and XMISCEN are 0 also 1 The on chip RTC module is enabled and can be accessed XPWM enable 0 Accesses to the on chip XPWM module are disabled external access XPWMEN performed Address range 00 ECO0h 00 ECFF is directed to external memory only if CAN1EN CAN2EN XASCEN XSSCEN XI2CEN XRTCEN and XMISCEN are 0 also 1 The on chip XPWM module is enabled and can be accessed XFlash enable bit 0 Accesses to the on chip XFlash and Flash registers are disabled external XFLASHEN access performed Address range 09 0000h 0E FFFFh is directed to external memory only if XRAMZ2EN is 0 also 1 The on chip XFlash is enabled and can be accessed XASC enable bit 0 Accesses to the on chip XASC are disabled external access performed XASCEN Address range 00 E900h 00 E9FFh is directed to external memory only if CAN1EN CAN2EN XRTCEN XASCEN XI2CEN XPWMEN and XMISCEN are 0 also 1 The on chip XASC is enabled and can be a
207. nches Dim Min Typ Max Min Typ Max A 1 60 0 063 A1 0 05 0 15 10 002 0 006 A2 1 35 1 40 1 45 0 053 0 057 b 0 17 0 22 0 27 0 007 0 011 0 09 0 20 10 004 0 008 21 80 22 00 22 20 0 858 0 867 0 874 D1 19 80 20 00 20 20 0 780 0 787 0 795 D3 17 50 0 689 E 21 80 22 00 22 20 0 858 0 867 0 874 E1 19 80 20 00 20 20 0 780 0 787 0 795 E3 17 50 0 689 e 0 50 0 020 o 3 5 7 o 3 5 7 L 0 45 0 60 0 75 0 018 0 024 0 030 L1 1 00 0 039 Number of Pins N 144 T Values in inches are converted from mm and rounded to 3 decimal digits 227 229 Revision history ST10F276 25 228 229 Revision history Table 110 Document revision history Date 02 June 2006 Revision 1 Initial release Changes ST10F276 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herei
208. nchronous mode 0 0 e eee 94 14 8 ASOxin synchronous mode 0 00 eee ee 95 14 4 High speed synchronous serial interfaces 0 0 0005 96 15 2C interface 25 65d bub bce Reser seensecdesdoenedtasaseesiedane 98 16 CAN MOQUICS 6 6 cnccsncccedenwewebeswndseaweed EE cue iin 99 16 1 Configuration support ssas 0c eee 99 16 2 CAN bus configurations 2 1 2 008s Rr ie ERE RR een beens 100 17 Real time clock 4k monnaie OR te hese RR ee Rb ees 102 18 Watchdog timer uoce dos beds teeta eee x9 SOR e na ca 103 19 System reset isses kae d RR WR Rae ds ae RE RERUM PEE 104 19 1 Input filter iiis mud RERO Rede icem de ice Ree 104 19 2 Asynchronous reset 222 394 RRRR I E REDRRE REPE Rd ru Fade abd ord 105 19 3 Synchronous reset warm reset 00200 110 19 4 Software reset ais cancasadkdaavee ranged ROGCRGURGORACE UR RU RO RR RAS 116 19 5 Watchdog timer reset ioc coset RRREER REIR RE bow eee eee eae 117 19 6 Bidirectional reset urea ae WE RRERRERERXEWR SR RU ERG RR EIE 118 19 7 Reset CIFCUILTY uineis duo XE REN AR ERR REED eed 122 19 8 Reset application examples 0 0 00 ee 125 19 9 Reset summary sss e E RECRERRRRGE3SERSERGU ERA ER ER ae EXER E RUE 127 20 Power reduction modes 2 00 c cece eee eee eens 130 201 WIG MOJE sioda aaa a a auarettedals eh die eaeee e ie 130 20 2 Power down mode x2ssex uoeec ca E aaeeea 130 ky 5 229 Contents ST10F276 20 2 1 Protected po
209. ng bit 3 BDRSTEN in SYSCON register It only can be enabled during the initialization routine before EINIT instruction is completed When enabled the open drain of the RSTIN pin is activated pulling down the reset signal for the duration of the internal reset sequence synchronous asynchronous hardware synchronous software and synchronous watchdog timer resets At the end of the internal reset sequence the pull down is released and e Aftera Short Synchronous Bidirectional Hardware Reset if RSTF is sampled low 8 TCL periods after the internal reset sequence completion refer to Figure 28 and Figure 29 the Short Reset becomes a Long Reset On the contrary if RSTF is sampled high the device simply exits reset state e After a Software or Watchdog Bidirectional Reset the device exits from reset If RSTF remains still low for at least 4 TCL periods minimum time to recognize a Short Hardware reset after the reset exiting refer to Figure 34 and Figure 35 the Software or Watchdog Reset become a Short Hardware Reset On the contrary if RSTF remains low for less than 4 TCL the device simply exits reset state ky ST10F276 System reset Note The Bidirectional reset is not effective in case RPD is held low when a Software or Watchdog reset event occurs On the contrary if a Software or Watchdog Bidirectional reset event is active and RPD becomes low the RSTIN pin is immediately released while the internal reset se
210. no longer floating when VLoap changes of 100mV occur It begins to float when a 100mV change from the loaded Voy Vo level occurs lop loL 20mA ST10F276 Electrical characteristics 23 8 2 Definition of internal timing The internal operation of the ST10F276 is controlled by the internal CPU clock fcpy Both edges of the CPU clock can trigger internal for example pipeline or external for example bus cycles operations The specification of the external timing AC Characteristics therefore depends on the time between two consecutive edges of the CPU clock called TCL The CPU clock signal can be generated by different mechanisms The duration of TCL and its variation and also the derived external timing depends on the mechanism used to generate fcpy This influence must be regarded when calculating the timings for the ST10F276 The example for PLL operation shown in Figure 52 refers to a PLL factor of 4 The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0 15 13 POH 7 5 Figure 52 Generation mechanisms for the CPU clock Phase locked loop operation fxrAL e IIl TCL TCL Direct clock drive ha LE LE LE LILI LI LI LU Ld fopu TCL TCL Prescaler operation ha LILI LILI LI LI LI LI LU fopu i TCL TCL
211. nonvolatile protection X Reg Low FFFFh XFICR OxOOOE E000 XFlash interface control register 000Fh 163 229 Register set ST10F276 22 8 Flash registers ordered by address The following table lists by order of their physical addresses all FLASH control registers which are implemented in the ST10F276 Note that as they are physically mapped on the X Bus these registers are not bit addressable Table 72 FLASH registers ordered by address Name Physical Description Reset value address FCROL OxOOOE 0000 Flash control register 0 Low 0000h FCROH OxOOOE 0002 Flash control register 0 High 0000h FCR1L OxOOOE 0004 Flash control register 1 Low 0000h FCR1H OxOOOE 0006 Flash control register 1 High 0000h FDROL OxOOOE 0008 Flash data register 0 Low FFFFh FDROH OxOOOE 000A Flash data register 0 High FFFFh FDR1L OxOOOE 000C Flash data register 1 Low FFFFh FDR1H OxOOOE OOOE Flash data register 1 High FFFFh FARL OxOOOE 0010 Flash address register Low 0000h FARH OxOOOE 0012 Flash address register High 0000h FER OxOOOE 0014 Flash error register 0000h FNVWPXRL Ox000E DFBO Flash nonvolatile protection X reg Low FFFFh FNVWPXRH Ox000E DFB2 Flash nonvolatile protection X reg High FFFFh FNVWPIRL Ox000E DFB4 Flash nonvolatile protection reg Low FFFFh FNVWPIRH Ox000E DFB6 Flash nonvolatile protection reg High FFFFh FNVAPRO OxOO0E DFB8 Flash nonvo
212. nput Fast External Interrupt Input Test Mode Hu ek Flash Sense Amplifier and Column Decoder For Port2 complete structure refer also to Figure 44 Figure 45 Supply current versus the operating frequency RUN and IDLE modes 150 100 fopu MHz ST10F276 Electrical characteristics 23 6 Flash characteristics Vpp 5V 1096 Vss OV Table 91 Flash characteristics Typical Maximum Parameter Ta 25 C Ta 125 C Unit Notes 0 cycles 0 cycles 100k cycles Word program 32 bit 35 80 290 us Double word program _ 64 bit 2 60 150 570 us Bank 0 program 384K 29 74 28 0 uH double word program Bank 1 program 128K 10 25 9 3 _ double word program Bank 2 program 192k 15 37 14 0 _ double word program Bank 3 program 128k 1 0 25 93 s double word program 0 6 0 9 1 0 not preprogrammed t K Sector erase 8K 05 08 09 S preprogrammed 1 1 2 0 2 7 not preprogrammed t 2K Sector erase 32K 08 18 2 5 S preprogrammed 1 7 3 7 5 1 not preprogrammed t 4K Sector erase 64K 13 33 47 S preprogrammed 20 2 not preprogrammed Bank 0 erase 384K 9 oe oo s siad 5 8 17 7 26 1 preprogrammed t Bank 1 erase 128K 3 3 0 7 0 9 8 s not preprogrammed 2 2 6 2 9 0 preprogrammed 14 t Bank 2 erase 192K 9 hi M 2 S nou prenrogremiosd 3 1 9 1 13 3 preprogrammed
213. nt sss ede goes a tee prem SEP a a eee VUE bbe P Rode 127 PORTO latched configuration for the different reset events 00000 0a 128 Power reduction modes summary 0 00 eee eee eae 134 BI pL 136 General purpose registers GPRS 00 00 cette 137 General purpose registers GPRs bytewise addressing 000 cena 137 Special function registers ordered by address 0 00 c cee eee eee eee 139 Special function registers ordered by address 0 00 c cece eee eee 146 X Registers ordered by name 1 tees 153 X registers ordered by address 0 cece eee 158 Flash registers ordered by name 0 0 cee eee 163 FLASH registers ordered by address 0 000 cece tee eee 164 MANUF description ro iosa aeaieie eee eae 165 IDCHIP description 0 00 cette 165 IDMEM description 0 20 00 cc teeta 166 IDPROG description a an anaua aaa 166 SYSCON description seia misrasi a a ara aa aaa a a ad nee 167 BUSCON4 description aaaea 169 RPOM descriptio ac eireas berane pere eo a E GUT a Seeger eai deeds 170 EXIxES bit description 0 0 0 0 000 ree 171 EXISE DELE 171 EXIxSS and port 2 pin configurations liliis 171 SFR area description praa eaaa a a ree 172 ESFR description iu ees ca ak Re ences iode bos dto aba ee Relea RC A 172 Segment 8 address range mapping 0 0 174 Absolute maximum ratings lllsleeee re 176
214. nterrupted by standard interrupt or by PEC interrupts X Peripheral interrupt The limited number of X Bus interrupt lines of the present ST10 architecture imposes some constraints on the implementation of the new functionality In particular the additional X Peripherals SSC1 ASC1 IC PWM1 and RTC need some resources to implement interrupt and PEC transfer capabilities For this reason a multiplexed structure for the interrupt management is proposed In the next Figure 16 the principle is explained through a simple diagram which shows the basic structure replicated for each of the four X interrupt available vectors XPOINT XP1INT XP2INT and XPSINT It is based on a set of 16 bit registers XIRXSEL x 0 1 2 3 divided in two portions each e Byte High XIRxSEL 15 8 Interrupt Enable bits e Byte Low XIRxSEL 7 0 Interrupt Flag bits When different sources submit an interrupt request the enable bits Byte High of XIRXSEL register define a mask which controls which sources will be associated with the unique 79 229 Interrupt system ST10F276 80 229 available vector If more than one source is enabled to issue the request the service routine will have to take care to identify the real event to be serviced This can easily be done by checking the flag bits Byte Low of XIRxSEL register Note that the flag bits can also provide information about events which are not currently serviced by the interrupt controller since m
215. ntrol register 0 low continued Bit Function Flash registers access locked When this bit is set it means that the access to the Flash Control Registers FCROH FCR1H L FDROH L FDR1H L FARH L and FER is locked by the FPEC any read access to the registers will output invalid data software trap OO9Bh and any write LOCK access will be ineffective LOCK bit is automatically set when the Flash bit WMS is set This is the only bit the user can always access to detect the status of the Flash once it is found low the rest of FCROL and all the other Flash registers are accessible by the user as well Note that FER content can be read when LOCK is low but its content is updated only when also BSY bits are reset Bank 1 0 Busy IFLASH These bits indicate that a write operation is running in the corresponding Bank of IFLASH They are automatically set when bit WMS is set When these bits are set BSY 1 0 every read access to the corresponding Bank will output invalid data software trap 009Bh while every write access to the Bank will be ignored At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the Bank returns to read mode After a Program or Erase Resume these bits are automatically set again Flash control register 0 high The Flash control register O high FCROH together with the Flash control register 0 Low FCROL is used to enable and to monitor all the write
216. nued Source of Interrupt or Request Enable Interrupt Vector Trap PEC Service Request Flag Flag Vector Location Number IGPI2 Tmer T lR Tee Tent O00098h 26h GPT2 CAPREL Register CRIR CRIE CRINT 00 009Ch 27h A D Conversion Complete ADCIR ADCIE ADCINT 00 00A0h 28h A D Overrun Error ADEIR ADEIE ADEINT 00 00A4h 29h ASCO Transmit SOTIR SOTIE SOTINT 00 00A8h 2Ah ASCO Transmit Buffer SOTBIR SOTBIE SOTBINT 00 011Ch 47h ASCO Receive SORIR SORIE SORINT 00 00ACh 2Bh ASCO Error SOEIR SOEIE SOEINT 00 00BOh 2Ch SSC Transmit SCTIR SCTIE SCTINT 00 00B4h 2Dh SSC Receive SCRIR SCRIE SCRINT 00 00B8h 2Eh SSC Error SCEIR SCEIE SCEINT 00 00BCh 2Fh PWM Channel 0 3 PWMIR PWMIE PWMINT 00 00FCh 3Fh See Paragraph 8 1 XPOIR XPOIE XPOINT 00 0100h 40h See Paragraph 8 1 XP1IR XP1IE XP1INT 00 0104h 41h See Paragraph 8 1 XP2IR XP2IE XP2INT 00 0108h 42h See Paragraph 8 1 XPSIR XPSIE XP3INT 00 010Ch 43h Hardware traps are exceptions or error conditions that arise during run time They cause immediate non maskable system reaction similar to a standard interrupt service branching to a dedicated vector table location The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register TFR Except when another higher prioritized trap service is in progress a hardware trap will interrupt any other program execution Hardware trap services cannot not be i
217. o the input clock the frequency of fcpy is constantly adjusted so it is locked to fyta The slight variation causes a jitter of fepy which also effects the duration of individual TCLs The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances The real minimum value for TCL depends on the jitter of the PLL The PLL tunes fcpy to keep it locked on fyz4 The relative deviation of TCL is the maximum when it is referred to one TCL period This is especially important for bus cycles using wait states and e g for the operation of timers serial interfaces etc For all slower operations and longer periods such as for example pulse train generation or measurement lower baud rates the deviation caused by the PLL jitter is negligible Refer to next Section 23 8 9 PLL Jitter for more details Voltage controlled oscillator The ST10F276 implements a PLL which combines different levels of frequency dividers with a Voltage Controlled Oscillator VCO working as frequency multiplier The following table presents a detailed summary of the internal settings and VCO frequency Table 96 Internal PLL divider mechanism P0 15 13 XTAL Input PEL Output CPU frequency POH 7 5 frequency prescaler Multiply by Divide by prescaler fcpy fxrAL X F 1 1 1 4to8MHz FxraL 4 64 4 x FxTAL x4 1 1 0 RT F
218. oad values and the resulting bit times for 40 MHz and 64 MHz CPU clock respectively The maximum is anyway limited to 8Mbaud Table 56 Synchronous baud rate and reload values fcp 40 MHz Baud Rate Bit Time Reload Value Reserved 0000h bm used only with fcpy 32 MHz or u 0001h 6 6M Baud 150ns 0002h 5M Baud 200ns 0003h 2 5M Baud 400ns 0007h 1M Baud ius 0013h 100K Baud 10us 00C7h 10K Baud 100us 07CFh 1K Baud ims 4E1Fh 306 Baud 3 26ms FF4Eh Table 57 Synchronous baud rate and reload values fcpy 64 MHz Baud Rate Bit Time Reload Value Reserved 0000h sdb used only with fopy 32 MHz or u 0001h on used only with fcpu 48 MHz or u 0002h 8M Baud 125ns 0003h 4M Baud 250ns 0007h 1M Baud ius 001Fh 100K Baud 10us 013Fh 10K Baud 100us OC7Fh 1K Baud ims 7CFFh 489 Baud 2 04ms FF9Eh 97 229 I2C interface ST10F276 15 98 229 I2C interface The integrated I C Bus Module handles the transmission and reception of frames over the two line SDA SCL in accordance with the I2C Bus specification The IC Module can operate in slave mode in master mode or in multi master mode It can receive and transmit data using 7 bit or 10 bit addressing Data can be transferred at speeds up to 400 Kbit s both Standard and Fast I C bus modes are supported The module can generate three different types of interrupt e Requests related to bus events like sta
219. ode with an external interrupt an EXxIN x 7 0 pin has to be asserted for at least 40ns Stand by mode In Stand by mode it is possible to turn off the main Vpp provided that Vergy is available through the dedicated pin of the ST10F276 To enter Stand by mode it is mandatory to held the device under reset once the device is under reset the RAM is disabled see XRAM2EN bit of XPERCON register and its digital interface is frozen in order to avoid any kind of data corruption A dedicated embedded low power voltage regulator is implemented to generate the internal low voltage supply about 1 65V in Stand by mode to bias all those circuits that shall remain active the portion of XRAM 16Kbytes for ST10F273E the RTC counters and 32 kHz on chip oscillator amplifier 131 229 Power reduction modes ST10F276 20 3 1 132 229 In normal running mode that is when main Vpp is on the Vstgy pin can be tied to Vas during reset to exercise the EA functionality associated with the same pin the voltage supply for the circuitries which are usually biased with Vergy see in particular the 32 kHz oscillator used in conjunction with Real Time Clock module is granted by the active main It must be noted that Stand by Mode can generate problems associated with the usage of different power supplies in CMOS systems particular attention must be paid when the ST10F276 I O lines are interfaced with other external CMOS integrated circuits if Vp
220. of either the PEC source or destination pointer An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode When this counter reaches zero a standard interrupt is performed to the corresponding source related vector location PEC services are very well suited to perform the transmission or the reception of blocks of data The ST10F276 has 8 PEC channels each of them offers such fast interrupt driven data transfer capabilities An interrupt control register which contains an interrupt request flag an interrupt enable flag and an interrupt priority bit field is dedicated to each existing interrupt source Thanks to its related register each source can be programmed to one of sixteen interrupt priority levels Once starting to be processed by the CPU an interrupt service can only be interrupted by a higher prioritized service request For the standard interrupt processing each of the possible interrupt sources has a dedicated vector location Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number Fast external interrupt inputs are provided to service external interrupts with high precision requirements These fast interrupt inputs feature programmable edge detection rising edge falling edge or both edges Fast external interrupts may also have interrupt sources selected from other peripheral
221. of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set by software Note that this bit is always cleared on power on or after a reset sequence ky ST10F276 System reset Note Short and long synchronous reset Once the first maximum 16 TCL are elapsed 4 12TCL the internal reset sequence starts It is 1024 TCL cycles long at the end of it and after other 8TCL the level of RSTIN is sampled after the filter see RSTF in the drawings if it is already at high level only Short Reset is flagged Refer to Chapter 19 System reset for details on reset flags if it is recognized still low the Long reset is flagged as well The major difference between Long and Short reset is that during the Long reset also P0 15 13 become transparent so it is possible to change the clock options Warning In case of a short pulse on RSTIN pin and when Bidirectional reset is enabled the RSTIN pin is held low by the internal circuitry At the end of the 1024 TCL cycles the RTSIN pin is released but due to the presence of the input analog filter the internal input reset signal RSTF in the drawings is released later from 50 to 500ns This delay is in parallel with the additional 8 TCL at the end of which the internal input reset line RSTF is sampled to decide if the reset event is Short or Long In particular e lIf8TCL gt 500ns Fcpu lt 8 MHz the reset event is always recognized as
222. oise environment Figure 21 Connection to single CAN bus via common CAN transceivers XMISC CANPAR 0 CAN Transceiver CAN H o 4 CAN L 0 c dL OA OD Open Drain Output ST10F276 CAN modules Multiple CAN bus The ST10F276 provides two CAN interfaces to support such kind of bus configuration as shown in Figure 22 Figure 22 Connection to two different CAN buses e g for gateway application XMISC CANPAR 0 Oo CAN bus 1 CAN bus 2 Parallel Mode In addition to previous configurations a parallel mode is supported This is shown in Figure 23 Figure 23 Connection to one CAN bus with internal Parallel Mode enabled XMISC CANPAR 1 Both CAN enabled CAN Transceiver CAN_H CAN_L 1 P4 4 and P4 7 when not used as CAN functions can be used as general purpose I O while they cannot be used as external bus address lines CAN bus 101 229 Real time clock ST10F276 17 102 229 Real time clock The Real Time Clock is an independent timer in which the clock is derived directly from the clock oscillator on XTAL1 main oscillator input or XTAL3 input 32 kHz low power oscillator so that it can be kept on running even in Idle or Power down mode if enabled to Registers access is implemented onto the XBUS This module is designed with the following characteristics e Generation of the current ti
223. ol Parameter lt SSCBR gt 0002h FFFFh Unit Min Max Min Max tsi0 sr SSC clock cycle time 150 150 8TCL 262144 TCL t3141 sr SSC clock high time 63 1310 2 12 t312 sr 9SC clock low time t313 sr SSC clock rise time i 10 t344 sr SSC clock fall time B B tis c lus data valid after shift 55 2TCL 30 Write data hold after shift ts1i6 cc edge 0 0 Read data setup time before ns t317p sR latch edge phase error 62 4TCL 12 detection on SSCPEN 1 Read data hold time after ts318p sa latch edge phase error 87 6TCL 12 detection on SSCPEN 1 Read data setup time before 1434 sr latch edge phase error 6 6 detection off SSCPEN 0 Read data hold time after t3ig sr latch edge phase error 31 2TCL 6 detection off SSCPEN 0 1 Maximum baud rate is in reality 8Mbaud that can be reached with 64 MHz CPU clock and lt SSCBR gt set to 3h or with 48 MHz CPU clock and SSCBR set to 2h When 40 MHz CPU clock is used the maximum baud rate cannot be higher than 6 6Mbaud lt SSCBR gt 2h due to the limited granularity of lt SSCBR gt Value 1h for lt SSCBR gt may be used only with CPU clock lower than 32 MHz after checking that timings are in line with the target master 2 Formula for SSC Clock Cycle time 1310 4TCL lt SSCBR gt 1 Where SSCBR represents the content of the SSC baud rate register taken as unsigned 16 bit integ
224. on support On chip PLL with 4 to 12 MHz oscillator m interrupt Direct or prescaled clock input 8 channel peripheral event controller for m Realtime clock and 32 kHz on chip oscillator single cycle interrupt driven data transfer Upto 111 lO li 16 priority level interrupt system with 56 E eps ui genera purpose nes sources sampling rate down to 15 6ns Individually programmable as input output a Jas or special function Programmable threshold hysteresis Two multi functional general purpose timer units with 5 timers m idle power down and stand by modes m Two 16 channel capture compare units m Single voltage supply 5V 10 embedded regulator for 1 8 V core supply Order Codes Part Number Package undi Iflash Xflash RAM Temperature range C ST10F276Z25Q3 PQFP144 64 MHz 512KB 320KB 68KB 40 125 ST10F276Z5T3 LQFP144 40 MHz 512KB 320KB 68KB 40 125 June 2006 Rev 1 1 229 www st com Contents ST10F276 Contents 1 introduction spar 13 2 ik ee ee Np ME o i Reda dao dei d Moda ape 16 3 Functional description llllleeeeeeees 23 4 Internal Flash memory een nn 24 4 1 Overview Arr TUI 24 4 2 Functional description 00 c cece ee 24 4 2 1 ped dq DET 24 4 2 2 Modules structure 1 0 eee ree 25 4 2 3 Low power mode 1 ee mr 27 A3 Write operation cess venti vaca dearth ive si eewmei vats hee sees 27 4 3 1 Power supply drop ceres a ranan SEARE EEEE
225. ontrol register 00h CC5 FE8Ah 45h CAPCOM register 5 0000h CC5IC b FF82h Cih CAPCOM register 5 interrupt control register 00h CC6 FE8Ch 46h CAPCOM register 6 0000h CC6IC b FF84h C2h CAPCOM register 6 interrupt control register 00h CC7 FE8Eh 47h CAPCOM register 7 0000h CC7IC b FF86h C3h CAPCOM register 7 interrupt control register 00h CC8 FE90h 48h CAPCOM register 8 0000h CC8IC b FF88h C4h CAPCOM register 8 interrupt control register 00h CC9 FE92h 49h CAPCOM register 9 0000h CC9IC b FF8Ah C5h CAPCOM register 9 interrupt control register 00h CCMO b FF52h A9h CAPCOM mode control register 0 0000h CCM1 b FF54h AAh CAPCOM mode control register 1 0000h CCM2 b FF56h ABh CAPCOM mode control register 2 0000h CCM3 b FF58h ACh CAPCOM mode control register 3 0000h CCM4 b FF22h 91h CAPCOM mode control register 4 0000h CCM5 b FF24h 92h CAPCOM mode control register 5 0000h CCM6 b FF26h 93h CAPCOM mode control register 6 0000h CCM7 b FF28h 94h CAPCOM mode control register 7 0000h CP FE10h 08h CPU context pointer register FCOOh CRIC b FF6Ah B5h GPT2 CAPREL interrupt control register 00h CSP FEO8h 04h CPU code segment pointer register read only 0000h DPOH b F102h E 81h POH direction control register 00h DPOL b F100h E 80h POL direction control register 00h DP1H b F106h E 83h P1H direction control register 00h DP1L b F104h E 82h P1L direction control register 00h DP2 b FFC2h Eth Port 2 direction control register 0000h 1
226. ooting steps As Figure 6 shows booting ST10F276 with the boot loader code occurs in a minimum of four steps 1 The ST10F276 is reset with POL 4 low 2 The internal new bootstrap code runs on the ST10 and a first level user code is downloaded from the external device via the selected serial link UARTO or CAN1 The bootstrap code is contained in the ST10F276 Test Flash and is automatically run when ST10F276 is reset with POL 4 low After loading a preselected number of bytes ST10F276 begins executing the downloaded program 3 The first level user code runs on ST10F276 Typically this first level user code is another loader that downloads the application software into the ST10F276 4 The loaded application software is now running Figure 6 Booting steps for ST10F276 o Step 1 External device gt s ST10F276 Entering bootstrap E Download Step 2 External device inet level user code Ee sor God s z ST10F276 Loading first level user code Run bootstrap code from Test Flash Download Application Step 3 External device _ s ST10F276 Loading the application Run first level code and exiting BSL from DPRAM FA40h ES Step 4 External device 3 x ST10F276 Run application code Hardware to activate BSL The hardware that activates the BSL during reset may be a simple pull down resistor on POL 4 for systems that use this featu
227. operations word program 32 bit double word program 64 bit and set protection Flash address register low FARL 0x0E 0010 FCR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 reserved RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 15 Flash address register low Bit Function Address 15 2 These bits must be written with the address of the Flash location to program in the following operations word program 32 bit and double word program 64 bit In double word program bit ADD2 must be written to 0 ADD 15 2 ST10F276 Internal Flash memory 4 4 10 4 4 11 Flash address register high FARH 0x0E 0012 FCR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ADD20 ADD19 ADD18 ADD17 ADD16 RW RW RW RW RW Table 16 Flash address register high Bit Function Address 20 16 ADD 20 16 These bits must be written with the address of the Flash location to program in the following operations word program and double word program Flash error register Flash error register as well as all the other Flash registers can be properly read only once LOCK bit of register FCROL is low Nevertheless its content is updated when also BSY
228. ount in computing the total leakage affecting the A D converter measurements Another contribution to the total leakage is represented by the charge sharing effects with the sam pling capacitance Cs being substantially a switched capacitance with a frequency equal to the conversion rate of a single channel maximum when fixed channel continuous conver sion mode is selected it can be seen as a resistive path to ground For instance assuming a conversion rate of 250 kHz with Cs equal to 4pF a resistance of 1MQ is obtained Req 1 fcCs where fc represents the conversion rate at the considered channel To minimize the error induced by the voltage partitioning between this resistance sampled voltage on Cg and the sum of Rs Re Rj Row Rap the external circuit must be designed to respect the following relation Rg RetR t Rew t v A REQ R AD LSB The formula above places constraints on external network design in particular on resistive path A second aspect involving the capacitance network must be considered Assuming the three capacitances Cg Cp and Cp are initially charged at the source voltage VA refer to the equivalent circuit shown in Figure 47 when the sampling phase is started A D switch close a charge sharing phenomena is installed Figure 48 Charge sharing timing diagram during sampling phase Vcs Voltage Transient on Cg AV lt 0 5 LSB U lt Rsw t Rap Cs lt lt Ts T2 Ry Cs
229. ount input 43 P5 14 TAEUD GPT1 timer T4 external up down control input 44 P5 15 T2EUD GPT1 timer T2 external up down control input 16 bit bidirectional I O port bit wise programmable for input or output via 47 54 direction bit Programming an I O pin as input forces the corresponding output 57 64 l O driver to high impedance state Port 2 outputs can be configured as push pull or open drain drivers The input threshold of Port 2 is selectable TTL or CMOS The following Port 2 pins have alternate functions 47 VO P2 0 CCOIlO CAPCOM CCO capture input compare output P2 0 P2 7 54 VO P27 CC7IO CAPCOM CC7 capture input compare output P2 8 P2 15 57 VO P28 CC8lO CAPCOM CC8 capture input compare output l EXOIN Fast external interrupt O input 64 VO P2 15 CC15IO CAPCOM CC15 capture input compare output l EX7IN Fast external interrupt 7 input l T7IN CAPCOW2 timer T7 count input 18 229 ky ST10F276 Pin data Table 1 Pin description continued Symbol Pin Type Function P3 0 P3 5 P3 6 P3 13 P3 15 15 bit P3 14 is missing bidirectional I O port bit wise programmable for input or 65 70 l O output via direction bit Programming an I O pin as input forces the 73 80 lO corresponding output driver to high impedance state Port 3 outputs can be 81 l O configured as push pull or open drain drivers The input threshold of Port 3 is selectable TTL or CMOS
230. p of ST10F276 becomes for example in Stand by Mode lower than the output level forced by the I O lines of these external integrated circuits the ST10F276 could be directly powered through the inherent diode existing on ST10F276 output driver circuitry The same is valid for ST10F276 interfaced to active inactive communication buses during Stand by mode current injection can be generated through the inherent diode Furthermore the sequence of turning on off of the different voltage could be critical for the system not only for the ST10F276 device The device Stand by mode current lergy may vary while Vpp to Vstpy and vice versa transition occurs some current flows between Vpp and Vsrpgy pins System noise on both Vpp and Vstpy can contribute to increase this phenomenon Entering stand by mode As already said to enter Stand by Mode XRAMZ2EN bit in the XPERCON Register must be cleared this allows to freeze immediately the RAM interface avoiding any data corruption As a consequence of a RESET event the RAM Power Supply is switched to the internal low voltage supply Vigsp derived from Vstpy through the low power voltage regulator The RAM interface will remain frozen until the bit XRAM2EN is set again by software initialization routine at next exit from main Vpp power on reset sequence Since V4g is falling down as a consequence of Vpp turning off it can happen that the XRAMO2EN bit is no longer able to guarantee its content logic
231. pin EXIxSS 01 Input from alternate source 10 Input from Port 2 pin ORed with alternate source 11 Input from Port 2 pin ANDed with alternate source Table 82 EXIxSS and port 2 pin configurations EXIxSS Port 2 pin Alternate source 0 P2 8 CAN1 RxD 1 P2 9 CAN2 RxD SCL 2 P2 10 RTCSI Second 3 P2 11 RTCAI Alarm 4 7 P2 12 15 Not used zero XP3IC F19Eh CFh ESFR Reset value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XPSIR XP3IE XP3ILVL GLVL RW RW RW RW Note 1 XP3IC register has the same bit field as xxIC interrupt registers xxIC yyyyh zzh SFR area Reset value 00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XXIR xxlE ILVL GLVL RW RW RW RW ky 171 229 Register set ST10F276 Table 83 SFR area description Bit GLVL Function Group level Defines the internal order for simultaneous requests of the same priority 8 Highest group priority 0 Lowest group priority ILVL Interrupt priority level Defines the priority level for the arbitration of requests Fh Highest priority level Oh Lowest priority level xxIE Interrupt enable control bit individually enables disables a specific source 0 Interrupt request is disabled 1 Interrupt request is enabled xxIR Interrupt request flag 0 No request pending 1 This source has raised an interrupt request XPERCON F024h 12h ESFR R
232. plication software into ROMless systems e temporary software into complete systems for testing or calibration e aprogramming routine for Flash devices The BSL mechanism may be used for standard system start up as well as for only special occasions like system maintenance firmware update or end of line programming or testing 5 2 1 Entering the standard bootstrap loader As with the old ST10 bootstrap mode the ST10F276 enters BSL mode if pin POL 4 is sampled low at the end of a hardware reset In this case the built in bootstrap loader is activated independently of the selected bus mode The bootstrap loader code is stored in a special Test Flash no part of the standard Flash memory area is required for this After entering BSL mode and the respective initialization the ST10F276 scans the RxDO line and the CAN1 RxD line to receive either a valid dominant bit from the CAN interface or a start condition from the UART line Start condition on UART RxD The ST10F276 starts the standard bootstrap loader This bootstrap loader is identical to other ST10 devices Examples ST10F269 ST10F168 See paragraph 5 3 for details Valid dominant bit on CAN1 RxD The ST10F276 starts bootstrapping via CAN1 the bootstrapping method is new and is described in the next paragraph 5 4 The following Figure 5 shows the program flow of the new bootstrap loader It clearly illustrates how the new functionalities are implemented e UART UART has priori
233. portant that the external hardware maintains a stable ground level on RSTIN pin without any glitch in order to avoid spurious exiting from reset status with unstable power supply Exiting stand by mode After the system has entered the Stand by Mode the procedure to exit this mode consists of a standard Power on sequence with the only difference that the RAM is already powered through V4asg internal reference derived from Verpgy pin external voltage It is recommended to held the device under RESET RSTIN pin forced low until external Vpp voltage pin is stable Even though at the very beginning of the power on phase the device is maintained under reset by the internal low voltage detector circuit implemented inside the main voltage regulator till the internal V4g becomes higher than about 1 0V there is no warranty that the device stays under reset status if RSTIN is at high level during power ramp up So it is important the external hardware is able to guarantee a stable ground level on RSTIN along the power on phase without any temporary glitch The external hardware shall be responsible to drive low the RSTIN pin until the Vpp is stable even though the internal LVD is active Once the internal Reset signal goes low the RAM still frozen power supply is switched to the main V 4g At this time everything becomes stable and the execution of the initialization routines can start XRAMZ2EN bit can be set enabling the
234. programmable for input or output via direction bit Programming an I O pin as input forces the corresponding output driver to high impedance state The input threshold of Port 0 is selectable TTL or CMOS In case of an external bus configuration PORTO serves as the address A and as the address data AD bus in multiplexed bus modes and as the data D bus in demultiplexed bus modes Demultiplexed bus modes Data path width 8 bit 16 bi POL O POL 7 DO D7 DO D7 POH 0O POH 7 1 0 D8 D15 Multiplexed bus modes Data path width 8 bit 16 bi POL O POL 7 ADO AD7 ADO AD7 POH O POH 7 A8 A15 AD8 AD15 P1L O P1L 7 P1H 0 P1H 7 118 125 128 135 1 0 Two 8 bit bidirectional I O ports P1L and P1H bit wise programmable for input or output via direction bit Programming an I O pin as input forces the corresponding output driver to high impedance state PORT1 is used as the 16 bit address bus A in demultiplexed bus modes if at least BUSCONXx is configured such the demultiplexed mode is selected the pis of PORT1 are not available for general purpose l O function The input threshold of Port 1 is selectable TTL or CMOS The pins of P1L also serve as the additional up to 8 analog input channels for the A D converter where P1L x equals ANy Analog input channel y where y x 16 This additional function have higher priority on demultiplexed bus function The following PORT1 pins have altern
235. put output Timing characteristics of the external bus interface memory cycle time memory tri state time length of ALE and read write delay are programmable giving the choice of a wide range of memories and external peripherals Up to four independent address windows may be defined using register pairs ADDRSELx BUSCONx to access different resources and bus characteristics These address windows are arranged hierarchically where BUSCON4 overrides BUSCONS and BUSCON overrides BUSCON1 All accesses to locations not covered by these four address windows are controlled by BUSCONO Up to five external CS signals four windows plus default can be generated in order to save external glue logic Access to very slow memories is supported by a Ready function A HOLD HLDA protocol is available for bus arbitration which shares external resources with other bus masters The bus arbitration is enabled by setting bit HLDEN in register PSW After setting HLDEN once pins P6 7 P6 5 BREQ HLDA HOLD are automatically controlled by the EBC In master mode default after reset the HLDA pin is an output By setting bit DP6 7 to 1 the slave mode is selected where pin HLDA is switched to input This directly connects the slave controller to another master controller without glue logic For applications which require less external memory space the address space can be restricted to 1 Mbyte 256 Kbytes or to 64 Kbytes Port 4 out
236. puts all eight address lines if an address space of 16M Bytes is used otherwise four two or no address lines Chip select timing can be made programmable By default after reset the CSx lines change half a CPU clock cycle after the rising edge of ALE With the CSCFG bit set in the SYSCON register the CSx lines change with the rising edge of ALE The active level of the READY pin can be set by bit RDYPOL in the BUSCONXx registers When the READY function is enabled for a specific address window each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register ST10F276 Interrupt system 8 Interrupt system The interrupt response time for internal program execution is from 78ns to 187 5ns at 64 MHz CPU clock The ST10F276 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller PEC In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed just one cycle is stolen from the current CPU activity to perform a PEC service A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment
237. quence is completed regardless of RPD status change 1024 TCL The bidirectional reset function is disabled by any reset sequence bit BDRSTEN of SYSCON is cleared To be activated again it must be enabled during the initialization routine WDTCON flags Similarly to what already highlighted in the previous section when discussing about Short reset and the degeneration into Long reset similar situations may occur when Bidirectional reset is enabled The presence of the internal filter on RSTIN pin introduces a delay when RSTIN is released the internal signal after the filter see RSTF in the drawings is delayed So it remains still active low for a while It means that depending on the internal clock speed a short reset may be recognized as a long reset the WDTCON flags are set accordingly Besides when either Software or Watchdog bidirectional reset events occur again when the RSTIN pin is released at the end of the internal reset sequence the RSTF internal signal after the filter remains low for a while and depending on the clock frequency it is recognized high or low 8TCL after the completion of the internal sequence the level of RSTF signal is sampled and if recognized still low a Hardware reset sequence starts and WDTCON will flag this last event masking the previous one Software or Watchdog reset Typically a Short Hardware reset is recognized unless the RSTIN pin and consequently internal signal RSTF is su
238. r more details on minimum reset pulse duration 3 The RPD status has no influence unless Bidirectional Reset is activated bit BDRSTEN in SYSCON RPD low inhibits the Bidirectional reset on SW and WDT reset events that is RSTIN is not activated refer to Sections 19 4 19 5 and 19 6 Input filter On RSTIN input pin an on chip RC filter is implemented It is sized to filter all the spikes shorter than 50ns On the other side a valid pulse shall be longer than 500ns to grant that ST10 recognizes a reset command In between 50ns and 500ns a pulse can either be filtered or recognized as valid depending on the operating conditions and process variations For this reason all minimum durations mentioned in this Chapter for the different kind of reset events shall be carefully evaluated taking into account of the above requirements In particular for Short Hardware Reset where only 4 TCL is specified as minimum input reset pulse duration the operating frequency is a key factor Examples e Fora CPU clock of 64 MHz 4 TCL is 31 25ns so it would be filtered In this case the minimum becomes the one imposed by the filter that is 500ns e Fora CPU clock of 4 MHz 4 TCL is 500ns In this case the minimum from the formula is coherent with the limit imposed by the filter ST10F276 System reset 19 2 Note Note Asynchronous reset An asynchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at low leve
239. rap loader 5 2 7 Note 5 2 8 5 3 5 3 1 Exiting bootstrap loader mode To execute a program in normal mode the BSL mode must first be terminated The ST10F276 exits BSL mode at a software reset level on POL 4 is ignored or a hardware reset POL 4 must be high in this case After the reset the ST10F276 starts executing from location 00 0000 of the internal Flash User Flash or the external memory as programmed via pin EA If a bidirectional Software Reset is executed and external memory boot is selected EA 0 a degeneration of the Software Reset event into a Hardware Reset can occur refer to section for details This implies that POL 4 becomes transparent so to exit from Bootstrap mode it would be necessary to release pin POL 4 it is no longer ignored Hardware requirements Although the new bootstrap loader is designed to be compatible with the old bootstrap loader there are a few hardware requirements relative to the new bootstrap loader External Bus configuration Must have four or less segment address lines keep CAN I Os available Usage of CAN pins P4 5 and P4 6 Even in bootstrap via UART P4 5 CAN1 RxD can be used as Port input but not as output The pin P4 6 CAN1_TxD can be used as input or output Level on UART RxD and CAN1 RxD during the bootstrap phase see Figure 6 Step 2 Must be 1 external pull ups recommended Standard bootstrap with UART RS232 or K Line Fea
240. ration 1 0000h CAN1IF1A2 EF1Ah CAN1 IF1 arbitration 2 0000h CAN1IF1CM EF12h CAN1 IF1 command mask 0000h CAN1IF1CR EF10h CAN1 IF1 command request 0001h CAN1IF1DA1 EF1Eh CAN1 IF1 data A 1 0000h CAN1IF1DA2 EF20h CAN1 IF1 data A 2 0000h CAN1IF1DB1 EF22h CAN1 IF1 data B 1 0000h CAN1IF1DB2 EF24h CAN1 IF1 data B 2 0000h CAN1IF1M1 EF14h CAN1 IF1 mask 1 FFFFh CAN1IF1M2 EF16h CAN1 IF1 mask 2 FFFFh CAN1IF1MC EF1Ch CAN1 IF1 message control 0000h CAN1IF2A1 EF48h CAN1 IF2 arbitration 1 0000h CAN1IF2A2 EF4Ah CAN1 IF2 arbitration 2 0000h CAN1IF2CM EF42h CAN1 IF2 command mask 0000h CAN1IF2CR EF40h CAN1 IF2 command request 0001h CAN1IF2DA1 EF4Eh CAN1 IF2 data A 1 0000h 153 229 Register set ST10F276 Table 69 X Registers ordered by name continued Name dedii Description Reset value CAN1IF2DA2 EF50h CAN1 IF2 data A 2 0000h CAN1IF2DB1 EF52h CAN1 IF2 data B 1 0000h CAN1IF2DB2 EF54h CAN1 IF2 data B 2 0000h CAN1IF2M1 EF44h CAN1 IF2 mask 1 FFFFh CAN1IF2M2 EF46h CAN1 IF2 mask 2 FFFFh CAN1IF2MC EF4Ch CAN1 IF2 message control 0000h CAN1IP1 EFAOh CAN1 interrupt pending 1 0000h CAN1IP2 EFA2h CAN1 interrupt pending 2 0000h CAN1IR EFO8h CAN1 interrupt register 0000h CAN1MV1 EFBOh CAN1 Message valid 1 0000h CAN1MV2 EFB2h CAN1 Message valid 2 0000h CAN1ND1 EF90h CAN1 New data 1 0000h CAN1ND2 EF92h CAN1 New data 2 0000h CAN1SR EFO2h CAN1 Status re
241. rator reload register 0000h XS1TBUF E908h XASC transmit buffer register 0000h XS1RBUF E90Ah XASC receive buffer register 0000h XS1PORT E980h XASC port control register 0000h I2CCR EAOOh 12C control register 0000h I2CSR1 EA02h I2C status register 1 0000h I2CSR2 EA04h I2C status register 2 0000h I2CCCR1 EAO06h I2C clock control register 1 0000h I2COAR1 EA08h I2C own address register 1 0000h I2COAR2 EAOAh I2C own address register 2 0000h I2CDR EAOCh I2C data register 0000h I2CCCR2 EAOEh 12C clock control register 2 0000h XCLKOUTDIV EBO2h CLKOUT divider control register 00h XIROSEL EB10h X Interrupt O selection register 0000h XIROSET EB12h X Interrupt O set register write only 0000h XIROCLR EB14h X Interrupt O clear register write only 0000h XIR1SEL EB20h X Interrupt 1 selection register 0000h XIR1SET EB22h X Interrupt 1 set register write only 0000h XIR1CLR EB24h X Interrupt 1 clear register write only 0000h 158 229 ky ST10F276 Register set Table 70 X registers ordered by address continued Name ee Description Reset value XPICON EB26h indutus port input threshold control 00h XIR2SEL EB30h X Interrupt 2 selection register 0000h XIR2SET EB32h X Interrupt 2 set register write only 0000h XIR2CLR EB34h X Interrupt 2 clear register write only 0000h XP1DIDIS EB36h Port 1 digital disable register 0000h XIRS3SEL EB40h X Inter
242. re at every hardware reset For systems that use the bootstrap loader only temporarily it may be preferable to use a switchable solution via jumper or an external signal CAN alternate function on Port4 lines is not activated if the user has selected eight address segments Port4 pins have three functions I O port address segment and CAN Boot via CAN requires that four or less address segments are selected ST10F276 Bootstrap loader Figure 7 Hardware provisions to activate the BSL T External signal b ra p ur po MM Normal boot l Q BSL 1 RpoL 4 RpoLA4 8kQ max 8kQ max BS a I E Circuit 2 P777 Circuit 1 77 5 2 5 Memory configuration in bootstrap loader mode The configuration that is the accessibility of the ST10F276 s memory areas after reset in Bootstrap Loader mode differs from the standard case Pin EA is evaluated when BSL mode is selected to enable or to not enable the external bus e f EA 1 the external bus is disabled BUSACTO 0 in BUSCONO register e If EA O the external bus is enabled BUSACTO 1 in BUSCONO register Moreover while in BSL mode accesses to the internal IFLASH area are partially redirected e Allcode accesses are made from the special Test Flash seen in the range 00 0000h to 00 01FFFh User IFLASH is only available for read and write accesses Test Flash cannot be read
243. register 24 0000h CC24IC b F170h E B8h CAPCOM register 24 interrupt control register 00h CC25 FE72h 39h CAPCOM register 25 0000h CC25IC b F172h E B9h CAPCOM register 25 interrupt control register 00h CC26 FE74h 3Ah CAPCOM register 26 0000h CC26IC b F174h E BAh CAPCOM register 26 interrupt control register 00h CC27 FE76h 3Bh CAPCOM register 27 0000h CC271C b F176h E BBh CAPCOM register 27 interrupt control register 00h CC28 FE78h 3Ch CAPCOM register 28 0000h CC28IC b F178h E BCh CAPCOM register 28 interrupt control register 00h CC29 FE7Ah 3Dh CAPCOM register 29 0000h CC29IC b F184h E C2h CAPCOM register 29 interrupt control register 00h CC2IC b FF7Ch BEh CAPCOM register 2 interrupt control register 00h 140 229 ST10F276 Register set Table 67 Special function registers ordered by address continued Name address address Description value CC3 FE86h 43h CAPCOM register 3 0000h CC30 FE7Ch 3Eh CAPCOM register 30 0000h CC30IC b F18Ch E C6h CAPCOM register 30 interrupt control register 00h CC31 FE7Eh 3Fh CAPCOM register 31 0000h CC31IC b F194h E CAh CAPCOM register 31 interrupt control register 00h CC3IC b FF7Eh BFh CAPCOM register 3 interrupt control register 00h CC4 FE88h 44h CAPCOM register 4 0000h CCAIC b FF80h Coh CAPCOM register 4 interrupt c
244. register acc to 0 frame Initialized only if Bootstrap via CAN XPERCON 042Dy XRAM1 2 XFlash CAN1 and XMISC enabled P4 6 CAN1_TxD T Initialized only if Bootstrap via CAN DP4 6 T Initialized only if Bootstrap via CAN 1 In Bootstrap modes standard or alternate ROMEN bit 10 of SYSCON is always set regardless of EA pin level BYTDIS bit 9 of SYSCON is set according to data bus width selection via PortO configuration 2 BUSCONO is initialized with 0000h external bus disabled if pin EA is high during reset If pin EA is low during reset BUSACTO bit 10 and ALECTLO bit 9 are set enabling the external bus with lengthened ALE signal BTYP field bit 7 and 6 is set according to PortO configuration Other than after a normal reset the watchdog timer is disabled so the bootstrap loading sequence is not time limited Pin CAN1_TxD1 is configured as output so the ST10F276 can return the identification frame Even if the internal IFLASH is enabled a code cannot be executed from it Loading the start up code via CAN After sending the acknowledge byte the BSL enters a loop to receive 128 bytes via CAN1 Hint The number of bytes loaded when booting via the CAN interface has been extended to 128 bytes to allow the reconfiguration of the CAN Bit Timing Register with the best timings synchronization window This can be achieved by the following sequence of instructions ReconfigureBaud rate MOV R1 041h MOV DPP3 0EF00h R1 P
245. responding baud rate factor with respect to the current CPU clock initializes the serial interface ASCO accordingly and switches pin TxDO to output Using this baud rate an acknowledge byte is returned to the host that provides the loaded data The acknowledge byte is D5h for the ST10F276 ST10F276 Bootstrap loader 5 3 3 5 3 4 ST10 Configuration in UART BSL RS232 or K Line When the ST10F276 enters BSL mode on UART the configuration shown in Table 30 is automatically set values that deviate from the normal reset values are marked in bold Table 30 ST10 configuration in UART BSL mode RS232 or K line Function or register Access Notes Watchdog timer Disabled Register SYSCON 04004 Context Pointer CP FA004 Register STKUN FA004 Stack Pointer SP FA40y Register STKOV FCOO Register BUSCONO acc to startup config Register SOCON 80114 Initialized only if Bootstrap via UART Register SOBG acc to 00 byte Initialized only if Bootstrap via UART P3 10 TXDO T Initialized only if Bootstrap via UART DP3 10 T Initialized only if Bootstrap via UART 1 In Bootstrap modes standard or alternate ROMEN bit 10 of SYSCON is always set regardless of EA pin level BYTDIS bit 9 of SYSCON is set according to data bus width selection via PortO configuration 2 BUSCONO is initialized with 0000h external bus disabled if pin EA is high during reset If pin EA is low during reset BU
246. ription is cse grobe gene a eee bye e hace ee jeg gd 17 Flash modules absolute mapping 1 1 2 2 0 00 cee eh 24 Flash modules sectorization read operations sasana esee 25 Flash modules sectorization write operations or with roms12 1 suuu 26 Control register interface liess 27 Flash control register O low lisse eee 28 Flash control register O high 29 Flash control register 11ow llle RI 31 Flash control register 1 high 32 Banks BxS and sectors BxFy status bits meaning llis 33 Flash data register 0 low lille I 33 Flash data register O high 0 Rn 33 Flash data register 1 low 2 2 0 ce eee 34 Flash data register 1 high 00 eee ee 34 Flash address register low 0 0 2 0 tees 34 Flash address register high 0 0 cee eee 35 Flash error register 2 2 eee eee 35 XFlash interface control register 2 2 llle 36 Flash non volatile write protection X register low 0 0 llle 37 Flash non volatile write protection X register high 0 00 eee eee 38 Flash non volatile write protection register low l l 38 Flash non volatile write protection register high 0 00 eee eee eee 38 Flash non volatile access protection register 0 liliis 39 Flash non volatile access protection register 1 low 0 0 00 eee eee 39 Flash non volatile access protection register 1 high
247. rrupt control 00h XP3IC b F19Eh E CFh See Section 8 1 00h 147 229 Register set ST10F276 148 229 Table 68 Special function registers ordered by address continued Name duress addross Description velie EXICON b FiCOh E E0h External interrupt control register 0000h ODP2 b F1C2h E Eth Port2 open drain control register 0000h PICON b FiC4h E E2h Port input threshold control register 00h ODP3 b FiC6h E E3h Port3 open drain control register 0000h ODP4 b FiCAh E E5h Port4 open drain control register 00h ODP6 b FICEh E E7h Port6 open drain control register 00h ODP7 b FiD2h E E9h Port7 open drain control register 00h ODP8 b F1D6h E EBh Port8 open drain control register 00h EXISEL b F1DAh E EDh External interrupt source selection register 0000h DPPO FEOOh 00h CPU data page pointer O register 10 bit 0000h DPP1 FEO2h 01h CPU data page pointer 1 register 10 bit 0001h DPP2 FEO4h 02h CPU data page pointer 2 register 10 bit 0002h DPP3 FEO6h 03h CPU data page pointer 3 register 10 bit 0003h CSP FEO8h 04h CPU code segment pointer register read only 0000h EMUCON FEOAh 05h Emulation control register XXh MDH FEOCh 06h CPU multiply divide register High word 0000h MDL FEOEh 07h CPU multiply divide register Low word 0000h CP FE10h 08h CPU context pointer register FCOOh SP FE12h
248. rs control bits A write operation to a port pin configured as an input causes the value to be written into the port output latch while a read operation returns the latched state of the pin itself A read modify write operation reads the value of the pin modifies it and writes it back to the output latch Writing to a pin configured as an output DPx y 1 causes the output latch and the pin to have the written value since the output buffer is enabled Reading this pin returns the value of the output latch A read modify write operation reads the value of the output latch modifies it and writes it back to the output latch thus also modifying the level at the pin I O lines support an alternate function which is detailed in the following description of each port 89 229 Parallel ports ST10F276 12 2 12 2 1 12 2 2 12 3 90 229 l O s special features Open drain mode Some of the I O ports of ST10F276 support the open drain capability This programmable feature may be used with an external pull up resistor in order to get an AND wired logical function This feature is implemented for ports P2 P3 P4 P6 P7 and P8 see respective sections and is controlled through the respective Open Drain Control Registers ODPx Input threshold control The standard inputs of the ST10F276 determine the status of input signals according to TTL levels In order to accept and recognize noisy signals CMOS input thresholds ca
249. rt or stop events arbitration lost etc e Requests related to data transmission e Requests related to data reception These requests are issued to the interrupt controller by three different lines and identified as Error Transmit and Receive interrupt lines When the IC module is enabled by setting bit XI2CEN in XPERCON register pins P4 4 and P4 7 where SCL and SDA are respectively mapped as alternate functions are automatically configured as bidirectional open drain the value of the external pull up resistor depends on the application P4 DP4 and ODP4 cannot influence the pin configuration When the I C cell is disabled clearing bit XIPCEN P4 4 and P4 7 pins are standard I O controlled by P4 DP4 and ODPA The speed of the I C interface may be selected between Standard mode 0 to 100 kHz and Fast I C mode 100 to 400 kHz ST10F276 CAN modules 16 Note 16 1 CAN modules The two integrated CAN modules CAN1 and CAN are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2 0 part B active It is based on the C CAN specification Each on chip CAN module can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers Because of duplication of the CAN controllers the following adjustments are to be considered e Same internal register addresses of both CAN controllers but wit
250. rupt 3 selection register 0000h XIR3SET EB42h Me set selection register 0000h XIR3CLR EBA4h DNA clear selection register 0000h XMISC EB46h XBUS miscellaneous features register 0000h XEMUO EB76h XBUS emulation register O write only XXXXh XEMU1 EB78h XBUS emulation register 1 write only XXXXh XEMU2 EB7Ah XBUS emulation register 2 write only XXXXh XEMUS EB7Ch XBUS emulation register 3 write only XXXXh XPEREMU EB7Eh XPERCON copy for emulation write only XXXXh XPWMCONO ECOOh XPWM module control register 0 0000h XPWMCON 1 ECO2h XPWM module control register 1 0000h XPOLAR ECO4h XPWM module channel polarity register 0000h XPWMCONOSET ECO6h RA a set control register 0 0000h XPWMCONOCLR ECO8h m aa aoe 0000h XPWMCON1SET ECOAh uS set control register 0 0000h XPWMCONICLR ECOCh PA aad cigar control reg D 0000h XPTO EC10h XPWM module up down counter 0 0000h XPT1 EC12h XPWM module up down counter 1 0000h XPT2 EC14h XPWM module up down Counter 2 0000h XPT3 EC16h XPWM module up down counter 3 0000h XPPO EC20h XPWM module period register 0 0000h XPP1 EC22h XPWM module period register 1 0000h XPP2 EC24h XPWM module period register 2 0000h XPP3 EC26h XPWM module period register 3 0000h XPWO EC30h XPWM module pulse width register 0 0000h 159 229 Register set ST10F276 Table 70 X registers ordered by address continued Name ee Description Reset valu
251. rves represent the very worst case computed taking into account all corners of temperature power supply and process variations the real jitter is always measured well below the given worst case values Noise in supply and substrate Digital supply noise adds determining elements to PLL output jitter independent of the multiplication factor Its effect is strongly reduced thanks to particular care used in the physical implementation and integration of the PLL module inside the device In any case the contribution of digital noise to global jitter is widely taken into account in the curves provided in Figure 53 Figure 53 ST10F276 PLL jitter 24MHz 32MHz 40MHz Jitter ns 0 200 400 600 800 1000 1200 1400 N CPU clock periods ST10F276 Electrical characteristics 23 8 12 Note 23 8 13 PLL lock unlock During normal operation if the PLL is unlocked for any reason an interrupt request to the CPU is generated and the reference clock oscillator is automatically disconnected from the PLL input In this way the PLL goes into free running mode providing the system with a backup clock signal free running frequency Ftree This feature allows to recover from a crystal failure occurrence without risking to go into an undefined configuration The system is provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe mode The path between the r
252. s for example the CANx controller receive signals CANx_RxD and IC serial clock signal can be used to interrupt the system Table 40 shows all the available ST10F276 interrupt sources and the corresponding hardware related interrupt flags vectors vector locations and trap interrupt numbers Table 40 Interrupt sources Source of Interrupt or Request Enable Interrupt Vector Trap PEC Service Request Flag Flag Vector Location Number CAPCOM Registero CCOIR CCOIE CCOINT ooo04h 10h CAPCOM Register 1 CC1IR CC1IE CC1INT 00 0044h 11h CAPCOM Register 2 CC2IR CC2IE CC2INT 00 0048h 12h CAPCOM Register 3 CCSIR CCSIE CC3INT 00 004Ch 13h CAPCOM Register 4 CCAIR CCAIE CCAINT 00 0050h 14h CAPCOM Register 5 CC5IR CCBIE CC5INT 00 0054h 15h 77 229 Interrupt system ST10F276 78 229 Table 40 Interrupt sources continued Source of Interrupt or Request Enable Interrupt Vector Trap PEC Service Request Flag Flag Vector Location Number CAPCOM Register 6 CC6IR CC6IE CC6INT 00 0058h 16h CAPCOM Register 7 CC7IR CC7IE CC7INT 00 005Ch 17h CAPCOM Register 8 CC8IR CC8IE CC8INT 00 0060h 18h CAPCOM Register 9 CC9IR CC9IE CC9INT 00 0064h 19h CAPCOM Register 10 CC10IR CC10IE CC10INT 00 0068h 1Ah CAPCOM Register 11 CC11IR CC11IE CC11INT 00 006Ch 1Bh CAPCOM Register 12 CC12IR CC12lE CC121NT 00 0070h 1
253. s User IFLASH access internal FLASH area As long as ST10F276 is in BSL the user s software should not try to execute code from the internal IFlash as the fetches are redirected to the Test Flash Loading the start up code After the serial link initialization sequence see following chapters the BSL enters a loop to receive 32 bytes boot via UART or 128 bytes boot via CAN These bytes are stored sequentially into ST10F276 Dual Port RAM from location 00 FA40h To execute the loaded code the BSL then jumps to location 00 FA40h The bootstrap sequence running from the Test Flash is now terminated however the microcontroller remains in BSL mode Most probably the initially loaded routine being the first level user code will load additional code and data This first level user code may use the pre initialized interface UART or CAN to receive data and a second level of code and store it in arbitrary user defined locations This second level of code may be e the final application code e another more sophisticated loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data e acode sequence to change the system configuration and enable the bus interface to store the received data into external memory In all cases the ST10F276 still runs in BSL mode that is with the watchdog timer disabled and limited access to the internal IFLASH area ST10F276 Bootst
254. s configured to output the acknowledge of the bootstrap with the standard identifier E6h a DLC of 3 and DataO D5h Data1 and 2 IDCHIP e The MO is configured to receive messages with the standard identifier 5h Its acceptance mask is set to ensure that all bits match The DLC received is not checked The ST10 expects only 1 byte of data at a time No other message is sent by the ST10F276 after the acknowledge The CAN boot waits for 128 bytes of data instead of 32 bytes see UART boot This is done to allow the User to reconfigure the CAN bit rate as soon as possible 63 229 Bootstrap loader ST10F276 5 5 5 5 1 64 229 Comparing the old and the new bootstrap loader The following tables summarizes the differences between the old ST10 boot via UART only bootstrap and the new one boot via UART or CAN Table 33 Software topics summary Old bootstrap loader New bootstrap loader Comments Uses only 32 bytes in Dual Port RAM from 00 FA40h Uses up to 128 bytes in Dual Port RAM from 00 FA40h For compatibility between boot via UART and boot via CAN1 please avoid loading the application software in the 00 FA60h 00 FABFh range Loads 32 bytes from UART Loads 32 bytes from UART boot via UART mode Same files can be used for boot via UART User selected Xperipherals can be enabled during boot Step 3 or Step 4 Xperipherals selection is fixed User can c
255. scription continued Bit Function Write configuration control inverted copy of WRC bit of RPOH WRCFG 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH System clock output enable CLKOUT CLKEN 0 CLKOUT disabled pin may be used for general purpose I O 1 CLKOUT enabled pin outputs the system clock signal or a prescaled value of system clock according to XCLKOUTDIV register setting Disable enable control for pin BHE set according to data bus width BYTDIS 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose I O Internal memory enable set according to pin EA during reset 0 Internal memory disabled Accesses to the IFlash Memory area use the ROMEN external bus 1 Internal memory enabled Segmentation disable enable control SGTDIS 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored Internal memory mapping ROMS1 0 Internal memory area mapped to segment 0 00 0000h 00 7FFFh 1 Internal memory area mapped to segment 1 01 0000h 01 7FFFh STKSZ System stack size Selects the size of the system stack in the internal IRAM from 32 to 1024 words 168 229
256. se in bank 0 Besides during any erase operation these bits are automatically set and give the status of the 10 sectors of bank 0 BOF9 BOFO The meaning of BOFy bit for sector y of bank 0 is given by the next Table 10 These bits are automatically reset at the end of a Write operation if no errors are detected 31 229 Internal Flash memory ST10F276 4 4 4 Flash control register 1 high The Flash control register 1 high FCR1H together with Flash control register 1 low FCR1L is used to select the sectors to erase or during any write operation to monitor the status of each sector and each bank of the module selected by SMOD bit of FCROH First diagram shows FCR1H meaning when SMOD 0 the second one when SMOD 1 FCR1H 0x0E 0006 SMOD 0 FCR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved B3S B2S reserved BSF1 B3FO0 RS RS RS RS FCR1H 0x0E 0006 SMOD 1 FCR Reset value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved B1S BOS reserved B1F1 B1FO0 RS RS RS RS Table 9 Flash control register 1 high Bit Function SMOD 0 XFLASH selected Bank 3 XFLASH sector 1 0 status During any erase operation these bits are automatically set and give the status of the B3F 1 0 2 sectors of bank 3 B3F1 B3F0 The meaning of B3Fy bit for sector y of bank 1 is given by the next Table 10 These bits are automatically reset at th
257. selected during reset it is possible to drive the CPU clock directly from the XTAL1 pin without particular restrictions on the maximum frequency since the on chip oscillator amplifier is bypassed The speed limit is imposed by internal logic that targets a maximum CPU frequency of 64 MHz In all other clock configurations Direct Drive with Prescaler or PLL usage the on chip oscillator amplifier is not bypassed so it determines the input clock speed limit Then an external clock source can be used but limited in the range of frequencies defined for the usage of crystal and resonator refer also to Table 95 on page 196 External clock drive timing conditions Vpp 5V 10 Vss OV T4 40 to 125 C 203 229 Electrical characteristics ST10F276 Note 23 8 16 204 229 Table 102 External clock drive timing Direct drive Diet dne with PLL usage fcpu Ef prescaler fopy fxra x F Symbol Parameter CPU REAL fcpu fxraL 2 Eee Unit Min Max Min Max Min Max toscSR XTAL1 period 15 625 83 3 250 83 3 250 t SR High time 6 3 6 t SR Low time 9 ns t SR Rise time 2 2 2 t SR Fall time 1 The minimum value for the XTAL1 signal period is considered as the theoretical minimum The real minimum value depends on the duty cycle of the input clock signal 2 4 12 MHz is the input frequency range when using an external clock sourc
258. sequence Even if BREQ is activated earlier the regain sequence is initiated by HOLD going high Please note that HOLD may also be deactivated without the ST10F276 requesting the bus 2 The next ST10F276 driven bus cycle may start here 221 229 Electrical characteristics ST10F276 23 8 22 High speed synchronous serial interface SSC timing modes Master mode Vpp 5V 10 Vss OV Ta 40 to 125 C C 50pF Table 108 Master mode Max baud rate 6 6MBd Fepy 40 MHz Variable baud rate lt SSCBR gt 0001h Symbol Parameter lt SSCBR gt 0002h FFFFh Unit Min Max Min Max tso00 ce SSC clock cycle time 150 150 8TCL 262144TCL t301 cc SSC clock high time 63 1390 2 12 t302 cc SSC clock low time t303 cc SSC clock rise time m 10 tso cc SSC clock fall time B 7 Write data valid after shift tz05 cc edge 15 15 Write data hold after shift tso cc ag ge 2 2 Read data setup time before latch edge phase ns lev 58 eror detection on s a SSCPEN 1 Read data hold time after tgogp sr latch edge phase error 50 4TCL detection on SSCPEN 1 Read data setup time before latch edge phase error detection off SSCPEN 0 t307 sR 25 2TCL Read data hold time after ts sr latch edge phase error 0 0 detection off SSCPEN 0 1 Maximum baud rate is in reality 8Mbaud that can be reached wit
259. set Value depends on different triggered reset event The XPnIC Interrupt Control Registers control interrupt requests from integrated X Bus peripherals Some software controlled interrupt requests may be generated by setting the XPnIR bits of XPnIC register of the unused X Peripheral nodes Special function registers ordered by address The following table lists by order of their physical addresses all SFRs which are implemented in the ST10F276 Bit addressable SFRs are marked with the letter b in column Name SFRs within the Extended SFR Space ESFRs are marked with the letter E in column Physical Address Table 68 Special function registers ordered by address Name duress address Description vee QX0 Foooh E 00h MAC unit offset register XO 0000h QX1 Fo02h E Oth MAC unit offset register X1 0000h QRO F004h E 02h MAC unit offset register RO 0000h QR1 FOO6h E 03h MAC unit offset register R1 0000h XADRS3 FO1Ch E OEh XPER address select register 3 800Bh XPERCON F024h E 12h XPER configuration register 05h PTO FO30h E 18h PWM module up down counter 0 0000h PT1 FO32h E 19h PWM module up down counter 1 0000h PT2 FO34h E 1Ah PWM module up down counter 2 0000h PTS FO36h E 1Bh PWM module up down counter 3 0000h PPO FO38h E 1Ch PWM module period register 0 0000h PP1 FOSAh E 1Dh PWM module period register 1 0000h PP2 FO3Ch E 1Eh PWM module period reg
260. st 0001h CAN2IF2CM EE42h CAN2 IF2 command mask 0000h CAN2IF2M1 EE44h CAN2 IF2 mask 1 FFFFh 160 229 ky ST10F276 Register set Table 70 X registers ordered by address continued Physical Name address Description Reset value CAN2IF2M2 EE46h CAN2 IF2 mask 2 FFFFh CAN2IF2A1 EE48h CAN2 IF2 arbitration 1 0000h CAN2IF2A2 EE4Ah CAN2 IF2 arbitration 2 0000h CAN2IF2MC EE4Ch CAN2 IF2 message control 0000h CAN2IF2DA1 EE4Eh CAN2 IF2 data A 1 0000h CAN2IF2DA2 EE50h CAN2 IF2 data A2 0000h CAN2IF2DB1 EE52h CAN2 IF2 data B 1 0000h CAN2IF2DB2 EE54h CAN2 IF2 data B 2 0000h CAN2TR1 EE80h CAN2 transmission request 1 0000h CAN2TR2 EE82h CAN2 transmission request 2 0000h CAN2ND1 EE90h CAN2 new data 1 0000h CAN2ND2 EE92h CAN2 new data 2 0000h CAN2IP1 EEAOh CAN2 interrupt pending 1 0000h CAN2IP2 EEA2h CAN2 interrupt pending 2 0000h CAN2MV1 EEBOh CAN2 message valid 1 0000h CAN2MV2 EEB2h CAN2 message valid 2 0000h CAN1CR EFOOh CAN1 CAN control register 0001h CAN1SR EFO2h CAN1 status register 0000h CAN1EC EFO4h CAN1 error counter 0000h CAN1BTR EFO6h CAN1 bit timing register 2301h CAN1IR EFO8h CAN1 interrupt register 0000h CAN1TR EFOAh CAN1 test register 00x0h CAN1BRPER EFOCh CAN1 BRP extension register 0000h CAN1IF1CR EF10h CAN1 IF1 command request 0001h CAN1IF1CM EF12h CAN1 IF1 comman
261. standard system start up as well as for only special occasions like system maintenance firmware update or end of line programming or testing Entering the CAN bootstrap loader The ST10F276 enters BSL mode if pin POL 4 is sampled low at the end of a hardware reset In this case the built in bootstrap loader is activated independently of the selected bus mode The bootstrap loader code is stored in a special Test Flash no part of the standard mask ROM or Flash memory area is required for this After entering BSL mode and the respective initialization the ST10F276 scans the CAN1_TXxD line to receive the following initialization frame Standard identifier Oh DLC Oh As all the bits to be transmitted are dominant bits a succession of 5 dominant bits and 1 stuff bit on the CAN network is used From the duration of this frame it calculates the corresponding baud rate factor with respect to the current CPU clock initializes the CAN1 interface accordingly switches pin CAN1_TxD to output and enables the CAN1 interface to take part in the network communication Using this baud rate a Message Object is configured in order to send an acknowledge frame The ST10F276 will not send this Message Object but the host can request it by sending a remote frame The acknowledge frame is the following for the ST10F276 Standard identifier E6h DLC 3h Data0 D5h that is generic acknowledge of the ST10 devices Data1 IDCHIP le
262. t A certain baud rate marked I in Figure 10 may for example violate the deviation limit while an even higher baud rate marked II in Figure 10 stays well below it This depends on the host interface Standard bootstrap with CAN Features The bootstrap via CAN has the same overall behavior as the bootstrap via UART e Same bootstrapping steps e Same bootstrap method Analyze the timing of a predefined frame send back an acknowledge frame BUT only on request load a fixed number of bytes and run e Same functionalities Boot with different crystals and PLL ratios Figure 11 CAN bootstrap loader sequence 128bytes L 9 nt Boot ROM Test Flash BSL routine 4 user software 1 BSL initialization time gt 1ms fCPU 40 MHz 2 Zero frame CAN message standard ID 0 DLC 0 sent by host 3 CAN message standard ID E6h DLC 3 DataO D5h Data1 Data2 IDCHIP_low high sent by ST10F276 on request 4 128 bytes of code data sent by host 5 Caution CAN1 TxD is only driven a certain time after reception of the zero byte 1 3ms fCPU 40 MHz 6 Internal Boot ROM Test Flash The Bootstrap Loader can load e thecomplete application software into ROM less systems e temporary software into complete systems for testing or calibration e aprogramming routine for Flash devices 57 229 Bootstrap loader ST10F276 5 4 2 Note 58 229 The BSL mechanism may be used for
263. t even when fixed channel continuous conversion mode is selected fastest conversion rate at a specific channel In conclusion it is evident that the 191 229 Electrical characteristics ST10F276 192 229 time constant of the filter R C is definitely much higher than the sampling time Ts so the charge level on Cs cannot be modified by the analog signal source during the time in which the sampling switch is closed Figure 49 Anti aliasing filter and conversion rate Analog source bandwidth V4 TC x 2 RFCF Conversion rate vs filter pole Noise fe fg Anti aliasing Filtering Condition 2 10 fC Nyquist fo f Anti aliasing filter fe RC Filter pole Sampled signal spectrum fc conversion Rate fr f fo fc f The considerations above lead to impose new constraints to the external circuit to reduce the accuracy error due to the voltage drop on Cg from the two charge balance equations above it is simple to derive the following relation between the ideal and real sampled volt age on Ca V C C p1 Cp2 C C p2 Cr C C A i p2 Cp Cg A2 P1 From this formula in the worst case when V4 is maximum that is for instance 5V assum ing to accept a maximum error of half a count 2 44mV it is immediately evident that a constraint is on Cr value Cp gt 204865 The next section provides an example of how to design the external network based on some reasonable values for the interna
264. t direction up down for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin TXEUD Concatenation of the timers is supported via the output toggle latch T6OTL of timer T6 which changes its state on each timer overflow underflow The state of this latch may be used to clock timer T5 or it may be output on a port pin T6OUT The overflow underflow of timer T6 can additionally be used to clock the CAPCOM timers TO or T1 and to cause a reload from the CAPREL register The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin CAPIN and timer T5 may optionally be cleared after the capture procedure This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead The capture trigger timer T5 to CAPREL may also be generated upon transitions of GPT1 timer T3 inputs T3IN and or T3EUD This is advantageous when T3 operates in Incremental Interface Mode Table 48 and Table 49 list the timer input frequencies resolution and periods for each pre scaler option at 40MHz and 64MHz CPU clock respectively Table 48 GPT2 timer input frequencies resolutions and periods at 40 MHz Timer Input Selection T5I T6l fcru 40MHz 000b 001b 010b 011b 100b 101b 110b 111b Prerscaler 4 8 16 32 64 128 256 512 factor 1 25 312 5 156 25 78 125 Input Freq
265. t only flags that the desired data has not been written This bit has to be software reset 35 229 Internal Flash memory ST10F276 Table 17 Flash error register continued Bit Function Sequence error SEQER This bit is automatically set when the control registers FCR1H L FCROH L FARH L FDR1H L FDROH L are not correctly filled to execute a valid write operation in this case no write operation is executed This bit has to be software reset Resume error RESER This bit is automatically set when a suspended program or erase operation is not resumed correctly due to a protocol error In this case the suspended operation is aborted This bit has to be software reset Write protection flag This bit is automatically set when trying to program or erase in a sector write WPF protected In case of multiple sector erase the not protected sectors are erased while the protected sectors are not erased and bit WPF is set This bit has to be software reset 4 4 12 XFlash interface control register This register is used to configure the XFLASH interface behaviour on the XBUS It allows to set the number of wait states introduced on the XBUS before the internal READY signal is given to the ST10 bus master XFICR OxE E000h XBUS Reset value 000Fh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WS3 WS2 WS1 WSO RW RW RW RW Table 18 XFlash interface control re
266. t sequence This pull up will charge any capacitor connected on RPD pin The simplest way to reset the ST10F276 is to insert a capacitor C1 between RSTIN pin and Vas and a capacitor between RPD pin and Vss CO with a pull up resistor RO between RPD pin and Vpp The input RSTIN provides an internal pull up device equalling a resistor of 50k to 250kO the minimum reset time must be determined by the lowest value Select C1 that produce a sufficient discharge time to permit the internal or external oscillator and or internal PLL and the on chip voltage regulator to stabilize ky ST10F276 System reset To ensure correct power up reset with controlled supply current consumption specially if clock signal requires a long period of time to stabilize an asynchronous hardware reset is required during power up For this reason it is recommended to connect the external RO CO circuit shown in Figure 37 to the RPD pin On power up the logical low level on RPD pin forces an asynchronous hardware reset when RSTIN is asserted low The external pull up RO will then charge the capacitor CO Note that an internal pull down device on RPD pin is turned on when RSTIN pin is low and causes the external capacitor CO to begin discharging at a typical rate of 100 200uA With this mechanism after power up reset short low pulses applied on RSTIN produce synchronous hardware reset If RSTIN is asserted longer than the time needed for CO to be discharg
267. te XXXXh RTCPH EDO8h RTC Prescaler register high byte XXXXh RTCPL EDO6h RTC Prescaler register low byte XXXXh XCLKOUTDIV EBO2h CLKOUT Divider control register 00h XEMUO EB76h XBUS Emulation register O write only XXXXh XEMU1 EB78h XBUS Emulation register 1 write only XXXXh XEMU2 EB7Ah XBUS Emulation register 2 write only XXXXh XEMUS EB7Ch XBUS Emulation register 3 write only XXXXh XIROCLR EB14h X Interrupt O clear register write only 0000h XIROSEL EB10h X Interrupt O selection register 0000h XIROSET EB12h X Interrupt 0 set register write only 0000h XIR1CLR EB24h X Interrupt 1 clear register write only 0000h XIR1SEL EB20h X Interrupt 1 selection register 0000h XIR1SET EB22h X Interrupt 1 set register write only 0000h XIR2CLR EB34h X Interrupt 2 clear register write only 0000h XIR2SEL EB30h X Interrupt 2 selection register 0000h XIR2SET EB32h X Interrupt 2 set register write only 0000h XIR3CLR EBA4h P d 3 clear selection register write 0000h XIR3SEL EB40h X Interrupt 3 selection register 0000h XIR3SET EB42h ort dee 3 set selection register write 0000h XMISC EB46h XBUS miscellaneous features register 0000h XP1DIDIS EB36h Port 1 digital disable register 0000h XPEREMU EB7Eh XPERCON copy for emulation write only XXXXh XPICON EB26h maed port input threshold control QOh XPOLAR ECO4h XPWM module channel polarity register 0000h XPPO EC20h XPWM module period register 0 0000h XPP1 EC22h XPWM module period register 1 0000h XPP2 E
268. ter 0000h P4 b FFC8h E4h Port 4 register 8 bit 00h DP4 b FFCAh E5h Port 4 direction control register 00h Pe b FFCCh E6h Port 6 register 8 bit 00h DP6 b FFCEh E7h Port 6 direction control register 00h P7 b FFDOh E8h Port 7 register 8 bit 00h DP7 b FFD2h E9h Port 7 direction control register 00h 152 229 ST10F276 Register set 22 5 Note Table 68 Special function registers ordered by address continued Name address address Description value P8 b FFD4h EAh Port 8 register 8 bit 00h DP8 b FFD6h EBh Port 8 direction control register 00h MRW b FFDAh EDh MAC unit repeat word 0000h MCW b FFDCh EEh MAC unit control word 0000h MSW b FFDEh EFh MAC unit status word 0200h X registers sorted by name The following table lists by order of their names all X Bus registers which are implemented in the ST10F276 Although also physically mapped on X Bus memory space the Flash control registers are listed in a separate section The X registers are not bit addressable Table 69 X Registers ordered by name Name Physical Description Reset value address CAN1BRPER EFOCh CAN1 BRP extension register 0000h CAN1BTR EFO6h CAN1 Bit timing register 2301h CAN1CR EFOOh CAN1 CAN control register 0001h CAN1EC EFO4h CAN1 Error counter 0000h CANI1IF1A1 EF18h CAN1 IF1 arbit
269. the ODP4 register for port P4 in this way it is possible to connect together P4 4 with P4 5 receive lines and P4 6 with P4 7 transmit lines configured to be configured as Open Drain The user is also allowed to map internally both CAN modules on the same pins P4 5 and P4 6 In this way P4 4 and P4 7 may be used either as general purpose I O lines or used for I C interface This is possible by setting bit CANPAR of XMISC register To access this register it is necessary to set bit XMISCEN of XPERCON register and bit XPEN of SYSCON register 99 229 CAN modules ST10F276 16 2 100 229 CAN bus configurations Depending on application CAN bus configuration may be one single bus with a single or multiple interfaces or a multiple bus with a single or multiple interfaces The ST10F276 is able to support these two cases Single CAN bus The single CAN Bus multiple interfaces configuration may be implemented using two CAN transceivers as shown in Figure 20 Figure 20 Connection to single CAN bus via separate CAN transceivers XMISC CANPAR 0 CAN CAN Transceiver Transceiver CAN H Nb CAN g mee c ros The ST10F276 also supports single CAN Bus multiple dual interfaces using the open drain option of the CANx TxD output as shown in Figure 21 Thanks to the OR Wired Connection only one transceiver is required In this case the design of the application must take in account the wire length and the n
270. the user software is responsible for setting the proper direction when using an alternate input or output function of a pin This is done by setting or clearing the direction control bit DPx y of the pin before enabling the alternate function There are port lines however where the direction of the port line is switched automatically For instance in the multiplexed external bus modes of PORTO the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data Obviously this cannot be done through instructions In these cases the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output There is one basic structure for all port lines with only an alternate input function Port lines with only an alternate output function however have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode All port lines that are not used for these alternate functions may be used as general purpose I O lines 91 229 A D converter ST10F276 13 92 229 A D converter A 10 bit A D converter with 16 8 multiplexed input channels and a sample and hold circu
271. there is no influence on Software Reset behavior with RPD status In case Bidirectional Reset is selected a Software Reset event pulls RSTIN pin low this occurs only if RPD is high if RPD is low RSTIN pin is not pulled low even though Bidirectional Reset is selected ky ST10F276 System reset Refer to next Figures 32 and 33for unidirectional SW reset timing and to Figures 34 35 and 36 for bidirectional 19 5 Watchdog timer reset When the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence Unlike hardware and software resets the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY or if READY is sampled active low after the programmed wait states When READY is sampled inactive high after the programmed wait states the running external bus cycle is aborted Then the internal reset sequence is started Bit PO 12 P0 8 are latched at the end of the reset sequence and bit PO 7 P0 2 are cleared that is written at 1 A Watchdog reset is always taken as synchronous there is no influence on Watchdog Reset behavior with RPD status In case Bidirectional Reset is selected a Watchdog Reset event pulls RSTIN pin low this occurs only if RPD is high if RPD is low RSTIN pin is not pulled low even though Bidirectional Reset is selected Refer to next Figures 32 and 33for
272. tion Data input 31 16 DIN 31 16 These bits must be written with the data to program the Flash with the following operations word program 32 bit double word program 64 bit and set protection 4 4 7 Flash data register 1 low FDR1L OxOE 000C FCR Reset value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DINO RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 33 229 Internal Flash memory ST10F276 4 4 8 4 4 9 34 229 Table 13 Flash data register 1 low Bit Function Data Input 15 0 DIN 15 0 These bits must be written with the Data to program the Flash with the following operations Word Program 32 bit Double Word Program 64 bit and Set Protection Flash data register 1 high FDR1H 0x0E 000E FCR Reset value FFFFh 15 14 13 12 11 10 9 8 7 6 5 4 38 2 1 0 DIN31 DIN30 DIN29 DIN28 DIN27 DIN26 DIN25 DIN24 DIN23 DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Table 14 Flash data register 1 high Bit Function Data input 31 16 DIN 31 16 These bits must be written with the data to program the Flash with the following
273. tion start Example 3 Disable in a permanent way Access and Debug Protection FCROH 0x0100 Set SPR in FARL OxDFBC Load Add of FARH FDROL OxFFFE 0x000E Load Add of Load Data OxDFB8 Load Add of register FNVAPRO in FARL 0x000E Load Add of register FNVAPRO in FARH Data in FDROL FCROH register FNVAPRIL in FARL register FNVAPRIL in FARH in FDROL for clearing PDSO0 FCROH 0x8000 Operation start Example 4 Enable again in a permanent way Access and Debug Protection after having disabled them FCROH 0x0100 Set SPR in FCROH FARL FARH FDROH FCROH OxFFFE Load 1 0x8000 Operation start Data in FDROH for clearing Pl OxDFBC Load Add register FNVAPR1H in FARL 0x000E Load Add register FNVAPR1H in FAR H ENO Disable and re enable of Access and Debug Protection in a permanent way as shown by examples 3 and 4 can be done for a maximum of 16 times Write operation summary In general each write operation is started through a sequence of 3 steps 1 The first instruction is used to select the desired operation by setting its corresponding selection bit in the Flash Control Register 0 This instruction is also used to select in which Flash Module to apply the Write Operation by setting resetting bit SMOD 2 The second step is the definition of the Address and Data for programming or the S
274. to map in parallel the two CAN modules is added on P4 5 P4 6 On chip main oscillator input frequency range has been reshaped reducing it from 1 25MHz down to 4 12MHz This is a high performance oscillator amplifier providing a very high negative resistance and wide oscillation amplitude when this on chip amplifier is used as reference for Real Time Clock module the Power down consumption is dominated by the consumption of the oscillator amplifier itself A metal option is added to offer a low power oscillator amplifier working in the range of 4 8MHz this will allow a power consumption reduction when Real Time Clock is running in Power Down mode using as reference the on chip main oscillator clock A second on chip oscillator amplifier circuit 82kHz is implemented for low power modes it can be used to provide the reference to the Real Time Clock counter either in Power Down or Stand by mode Pin XTAL3 and XTAL4 replace a couple of Vpp Vss pins of ST10F269 Possibility to re program internal XBUS chip select window characteristics XRAM2 and XFLASH address window is added ST10F276 Introduction Figure 1 Logic symbol Vis Voo Vss RSTIN RSTOUT VAREF VAGND NMI EA Vstpy READY ALE RD WR WRL ST10F276 Port 5 16 bit o 7O a O od od od N LU o 91 1 oo o 029 OF oO O43 og o9 aN op O sS o ov O ER N 15 229 Pin data ST10F276
275. to select the Sector Erase operation in the Flash modules The Sector Erase operation allows to erase all the Flash locations to OxFF From 1 to all the sectors of the same Bank excluded Test Flash for Bank BO can be selected to be erased through bits BxFy of FCR1H L registers before starting the execution by setting bit WMS It is not necessary to pre program the sectors to 0x00 because this is done automatically SER bit is automatically reset at the end of the Sector Erase operation DWPG Double word program This bit must be set to select the Double Word 64 bits Program operation in the Flash modules The Double Word Program operation allows to program Os in place of 1s The Flash Address in which to program aligned with even words must be written in the FARH L registers while the 2 Flash Data to be programmed must be written in the FDROH L registers even word and FDR1H L registers odd word before starting the execution by setting bit WMS DWPG bit is automatically reset at the end of the Double Word Program operation WPG Word program This bit must be set to select the Word 32 bits Program operation in the Flash modules The Word Program operation allows to program Os in place of 1s The Flash Address to be programmed must be written in the FARH L registers while the Flash Data to be programmed must be written in the FDROH L registers before starting the execution by setting bit WMS WPG bit is automatically reset at the
276. too gt I WR DM N 74 WRL j l exes li5 WRH I lis gt 209 229 Electrical characteristics ST10F276 210 229 Figure 59 Multiplexed bus with without R W delay normal ALE R W CS MUT YS A SH t AE I l l l5 gt lt tig tos l ALE l l i i l 1 T l l I l N A23 A16 i by MEME AE A15 A8 l Address BHE i l l l l j l l l I i i tig i l 1 rte gt Read cycle P gt rt Address Data Address Data In gt gt Address Bus PO i l l i l l l i ety ox lt __ _teo RdCSx i ur gt i i lg at l e 49 1 gt tug re Meet gt l l l l I l l Write cycle l taz i l l56 gt Address Data WrCSx NN NL l pem Clas Lf i re tag gt l X ST10F276 Electrical characteristics a Figure 60 Multiplexed bus with without R W delay extended ALE R W CS TESI Nea SF NC Uc oL l l i l i Mb n ti o yy ALE N A a l i lt 14 i T iz gt l A23 A16 l A15 A8 l Address I 4 BHE l l l l tsa 4 l l l I i I l Read cycle m te x t i Address Data j l i l l l i i to t44 gt t i leti m m _t 3 gt lt tas l Ia lio l l lus l l MER IN l l RdCSx perce l i Le tys l gt l f l i faz
277. trol register 00h CC7IC b FF86h C3h CAPCOM register 7 interrupt control register 00h CC8IC b FF88h C4h CAPCOM register 8 interrupt control register 00h CC9IC b FF8Ah C5h CAPCOM register 9 interrupt control register 00h CC10IC b FF8Ch C6h CAPCOM register 10 interrupt control register 00h CC11IC b FF8Eh C7h CAPCOM register 11 interrupt control register 00h CC12IC b FF90h C8h CAPCOM register 12 interrupt control register 00h CC13IC b FF92h C9h CAPCOM register 13 interrupt control register 00h CC14IC b FF94h CAh CAPCOM register 14 interrupt control register 00h CC15IC b FF96h CBh CAPCOM register 15 interrupt control register 00h ADCIC b FF98h CCh e d end of conversion interrupt control 00h ADEIC b FF9Ah CDh Br DM overrun error interrupt control 00h TOIC b FF9Ch CEh CAPCOM timer 0 interrupt control register 00h T1IC b FF9Eh CFh CAPCOM timer 1 interrupt control register 00h ADCON b FFAOh DOh A D converter control register 0000h P5 b FFA2h D1h Port 5 register read only XXXXh P5DIDIS b FFA4h D2h Port 5 digital disable register 0000h TFR b FFACh D6h Trap flag register 0000h WDTCONb FFAEh D7h Watchdog timer control register 00xxh SOCON b FFBOh D8h Serial channel 0 control register 0000h SSCCONb FFB2h D9h SSC control register 0000h P2 b FFCOh EOh Port 2 register 0000h DP2 b FFC2h Eth Port 2 direction control register 0000h P3 b FFC4h E2h Port 3 register 0000h DP3 b FFC6h E3h Port 3 direction control regis
278. tures ST10F276 bootstrap via UART has the same overall behavior as the old ST10 bootstrap via UART e Same bootstrapping steps e Same bootstrap method Analyze the timing of a predefined byte send back an acknowledge byte load a fixed number of bytes and run e Same functionalities Boot with different crystals and PLL ratios 53 229 Bootstrap loader ST10F276 5 3 2 54 229 Figure 9 UART bootstrap loader sequence 32 bytes 6 Int Boot ROM Test Flash BSL routine user software 1 BSL initialization time gt 1ms fCPU 40 MHz 2 Zero byte 1 start bit eight 0 data bits 1 stop bit sent by host 3 Acknowledge byte sent by ST10F276 4 32 bytes of code data sent by host 5 Caution TxDO is only driven a certain time after reception of the zero byte 1 3ms fCPU 40 MHz 6 Internal Boot ROM Test Flash Entering bootstrap via UART The ST10F276 enters BSL mode if pin POL 4 is sampled low at the end of a hardware reset In this case the built in bootstrap loader is activated independently of the selected bus mode The bootstrap loader code is stored in a special Test Flash no part of the standard mask ROM or Flash memory area is required for this After entering BSL mode and the respective initialization the ST10F276 scans the RxDO line to receive a zero byte that is 1 start bit eight 0 data bits and 1 stop bit From the duration of this zero byte it calculates the cor
279. ty over CAN after a falling edge on CAN1_RxD until the first valid rising edge on CAN1_RxD CAN Pulses on CAN1_RxD shorter than 20 CPU cycles are filtered ky 47 229 Bootstrap loader ST10F276 5 2 2 48 229 ST10 configuration in BSL When the ST10F276 has entered BSL mode the configuration shown in Table 29 is automatically set values that deviate from the normal reset values are marked in bold Table 29 ST10 configuration in BSL mode Function or register Access Notes Watchdog Timer Disabled Register SYSCON 0404 ee Context Pointer CP FAOOY Register STKUN FCOO Stack Pointer SP FA40 Register STKOV FAOO Register BUSCONO acc to startup config Register SOCON 80114 Initialized only if Bootstrap via UART Register SOBG acc to 00 byte Initialized only if Bootstrap via UART P3 10 TXDO T Initialized only if Bootstrap via UART DP3 10 T Initialized only if Bootstrap via UART SANT Status Contal 00004 Initialized only if Bootstrap via CAN Register CAN1 Bit Timing Register acc to 0 frame Initialized only if Bootstrap via CAN XRAM1 2 XFlash CAN1 and XMISC XPERCON 042D4 enabled Initialized only if Bootstrap via CAN P4 6 CAN1_TxD T Initialized only if Bootstrap via CAN DP4 6 T Initialized only if Bootstrap via CAN 1 In Bootstrap modes standard or alternate ROMEN bit 10 of SYSCON is always set regardless of EA pin level BYTDIS
280. unidirectional SW reset timing and to Figures 34 35 and 36 for bidirectional Figure 32 SW WDT unidirectional RESET EA 1 RSTIN 2TCL P0 15 13 X not transparent X P0 12 8 X transparent not t X PO 7 2 P0 1 0 K nottransparent nett 7TCL IBUS CS i Internal sims FLARST i 1024 TCL lt RST RSTOUT 117 229 System reset ST10F276 19 6 118 229 Figure 33 SW WDT unidirectional RESET EA 0 P0 15 13 X not transparent X P0 12 8 X transparent not t PO 7 2 Y not transparent i X Porto KC metWansparemt Ret 1024 TCL RSTOUT Bidirectional reset As shown in the previous sections the RSTOUT pin is driven active low level at the beginning of any reset sequence synchronous asynchronous hardware software and watchdog timer resets RSTOUT pin stays active low beyond the end of the initialization routine until the protected EINIT instruction End of Initialization is completed The Bidirectional Reset function is useful when external devices require a reset signal but cannot be connected to RSTOUT pin because RSTOUT signal lasts during initialization It is for instance the case of external memory running initialization routine before the execution of EINIT instruction Bidirectional reset function is enabled by setti
281. unit CPU 6 Central processing unit CPU The CPU includes a 4 stage instruction pipeline a 16 bit arithmetic and logic unit ALU and dedicated SFRs Additional hardware has been added for a separate multiply and divide unit a bit mask generator and a barrel shifter Most of the ST10F276 s instructions can be executed in one instruction cycle which requires 31 25ns at 64 MHz CPU clock For example shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted Multiple cycle instructions have been optimized branches are carried out in 2 cycles 16 x 16 bit multiplication in 5 cycles and a 32 16 bit division in 10 cycles The jump cache reduces the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle The CPU uses a bank of 16 word registers to run the current context This bank of General Purpose Registers GPR is physically stored within the on chip Internal RAM IRAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU The number of register banks is only restricted by the available Internal RAM space For easy parameter passing a register bank may overlap others A system stack of up to 2048 bytes is provided as a storage for temporary data The system stack is allocated in the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two separate
282. up to four PWM output signals each using edge aligned or centre aligned PWM In addition the PWM modules can generate PWM burst signals and single shot outputs The Table 50 and Table 51 show the PWM frequencies for different resolutions The level of the output signals is selectable and the PWM modules can generate interrupt requests Figure 19 Block diagram of PWM module Clock 1 Clock 2 Input Control User readable writeable register PPx Period Register A Comparator Match A T PTx a R o 16 bit Up Down Counter un Up Down Clear Control v Comparator Match Output Control e A Enable Shadow Register A PWx Pulse Width Register Write Control POUTx Table 50 PWM unit frequencies and resolutions at 40 MHz CPU clock Mode 0 Resolution 8 bit 10 bit 12 bit 14 bit 16 bit CPU Clock 1 25ns 156 25 kHz 39 1 kHz 9 77 kHz 2 44Hz 610Hz CPU 1 6us 2 44 kHz 610Hz 152 6Hz 38 15Hz 9 54Hz Clock 64 Mode 1 Resolution 8 bit 10 bit 12 bit 14 bit 16 bit CPU Clock 1 25ns 78 12 kHz 19 53 kHz 4 88 kHz 1 22 kHz 305 2Hz CRU 1 6us 1 22 kHz 305 17Hz 76 29Hz 19 07Hz 4 77Hz Clock 64 Table 51 PWM unit frequencies and resolutions at 64 MHz CPU clock Mode 0 Resolution 8 bit 10 bit 12 bit 14 bit 16 bit CPU Clock 1 15 6ns 250 kHz 62 5 kHz 15 63 kHz 3 91Hz 977H
283. ut CAN in Init enable Configuration Change MOV R1 01600h MOV DPP3 0EF06h R1 1MBaud at Fcpu 20 MHz These 128 bytes are stored sequentially into locations 00 FA40 through OO FABF of the IRAM allowing up to 64 instructions to be placed into the RAM area To execute the loaded code the BSL then jumps to location 00 FA40 that is the first loaded instruction The bootstrap loading sequence is now terminated however the ST10F276 remains in BSL 59 229 Bootstrap loader ST10F276 5 4 5 60 229 mode Most probably the initially loaded routine will load additional code or data as an average application is likely to require substantially more than 64 instructions This second receive loop may directly use the pre initialized CAN interface to receive data and store it in arbitrary user defined locations This second level of loaded code may be e the final application code e another more sophisticated loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data acode sequence to change the system configuration and enable the bus interface to store the received data into external memory This process may go through several iterations or may directly execute the final application In all cases the ST10F276 still runs in BSL mode that is with the watchdog timer disabled and limited access to the internal Flash area All code fetches from the internal Flash area 0170000
284. ut hysteresis READY TTL only 3 400 700 VHYSA4CC Input hysteresis RPD 3 500 1500 Output low voltage V CC P6 7 0 ALE RD WR WRL lo 8 mA B 0 4 BE BHE WRH CLKOUT RSTIN lo 1 mA 0 05 RSTOUT Output low voltage V CC P0 15 0 P1 15 0 P2 15 0 loti 2 4 mA 0 4 Obl P3 15 13 0 P4 7 0 P7 7 0 loL1 0 5 mA 0 05 P8 7 0 loe 85 uA Vpp VoL2 CC Output low voltage RPD loi 80 uA 0 5 Vpp loi 60 uA 0 3 Vpp V Output high voltage 2 B Vou CC P6 7 0 ALE RD WA WAL i diis M DD od 7 BHE WRH CLKOUT RSTOUT 9H DUT Output high voltage 7 cc PO 15 0 P1 15 0 P2 15 0 loH1 4mMA Vpp 0 8 E OH1 P3 15 13 0 P4 7 0 P7 7 0 lon1 7 0 5 mA Vpp 0 08 P8 7 0 lone 2mA 0 Vou CC Output high voltage RPD loue 2 750 uA 0 3 Vpp B lone 150 uA 0 5 Vpp lozi CC Input leakage current P5 15 0 0 2 Input leakage current _ _ loz21 CC ait except P5 15 0 P2 0 RPD 209 u 3 1 0 loza CC Input leakage current P2 0 05 loza CC Inputleakage current RPD 3 0 lovi SR Overload current all except P2 0 9 5 mA ky 179 229 Electrical characteristics ST10F276 Table 90 DC characteristics continued Limit values Symbol Parameter Test Condition Unit Min Max lloy2 SR Overload current P2 0 4 5 mA ov2 4 Rast CC RSTIN pull up resistor 100 kQ nomina
285. utputs can be configured as push pull or open drain drivers In case of an external bus configuration Port 4 can be used to output the segment address lines 85 P4 0 A16 Segment address line 86 P4 1 A17 Segment address line 87 P4 2 A18 Segment address line 88 P4 3 A19 Segment address line 89 P4 4 A20 Segment address line CAN2 RxD CAN 2 receive data input SCL I C Interface serial clock 90 P4 5 A21 Segment address line CAN1 RxD CAN1 receive data input CAN2 RxD CAN2 receive data input 91 A22 CAN1_TxD P4 6 Segment address line CAN1 transmit data output CAN2 TxD CAN2 transmit data output 92 P4 7 A23 Most significant segment address line CAN2_TxD CAN2 transmit data output SDA I C Interface serial data 95 96 External memory read strobe RD is activated for every external instruction or data read access External memory write strobe In WR mode this pin is activated for every external data write access In WRL mode this pin is activated for low byte data write accesses on a 16 bit bus and for every data write access on an 8 bit bus See WRCFG in the SYSCON register for mode selection READY READY 97 Ready input The active level is programmable When the ready function is enabled the selected inactive level at this pin during an external memory access will force the insertion of waitstate
286. ware logic and application circuitry are described in Reset circuitry chapter and Figures 37 38 and 39 It occurs when RSTIN is low and RPD is detected or becomes low as well 108 229 ST10F276 System reset Figure 26 Asynchronous hardware RESET EA 1 1 lt 2TCL RPD 1 250ns 1 i us 500 ng i RSTIN 250ns 500ns i E es 3 4 TCL i After Filter l P0 15 13 not transparent K transparent nott not tX P0 12 2 not transparent X transparent i not t X PO 1 0 not transparent i not t X f l ZTCL IBUS CS i internal internal STE FLARST i RST gt A Latching point of Porto for system start up configuration Note 1 Longer than Porto settling time PLL synchronization if needed that is PO 15 13 changed Longer than 500ns to take into account of Input Filter on RSTIN pin a 109 229 System reset ST10F276 19 3 110 229 Figure 27 Asynchronous hardware RESET EA 0 3 8 TCL RSTF After Filter P0 15 13 not transparent X transparent P0 12 2 not transparent X transparent PO 1 0 i not transparent Latching point of Porto in System start up configuration Note 1 Longer than PortO settling time
287. way can be executed a maximum of 16 times Trying to write into the access protected Flash from internal RAM will be unsuccessful Trying to read into the access protected Flash from internal RAM will output a dummy data When the Flash module is protected in access also the data access through PEC of a peripheral is forbidden To read write data in PEC mode from to a protected Bank first it is necessary to temporary unprotect the Flash module Due to ST10 architecture the XFLASH is seen as external memory this makes impossible to access protect it from real external memory or internal RAM In the following table a summary of all levels of possible Access protection is reported in particular supposing to enable all possible access protections when fetching from a memory as listed in the first column what is possible and what is not possible to do see column headers is shown in the table Table 26 Summary of access protection level Read IFLASH Read XFLASH Read FLASH Write FLASH dump to Fdump to Registers Registers IFLASH XFLASH g g Fetching from IFLASH Yes Yes Yes Yes Yes Yes Fetching from XFLASH No Yes Yes Yes Yes No Fetching from IRAM No Yes Yes Yes Yes No ky ST10F276 Internal Flash memory 4 5 10 4 5 11 Table 26 Summary of access protection level Read IFLASH Read XFLASH Read FLASH Write FLASH Jump to ump to Registers Registers IFLASH XFLASH ae 9 Fetching
288. wer down mode 0 cee ee 131 20 2 2 Interruptible power down mode 000 e eee eee 131 20 3 Stand by mode iia stance Mhe8e kee nig hones owas Saba See red 131 20 3 1 Entering stand by mode 0 ee 132 20 3 2 Exiting stand by mode 0 eee 133 20 3 3 Real time clock and stand by mode 00 e eee eee 133 20 3 4 Power reduction modes summary 0 00 0 cee eee eee 134 21 Programmable output clock divider 135 22 Register Set usua dad dox o eee CECR Galas Be kee CER EROR 136 22 1 Register description format 00 ee 136 22 2 General purpose registers GPRS 0 0 c eee eee 137 22 3 Special function registers ordered by name 139 22 4 Special function registers ordered by address 146 225 X registers sorted by name 2c ses 153 22 6 X registers ordered by address 0 eee eee ee 158 22 7 Flash registers ordered by name ce eee eee 163 22 8 Flash registers ordered by address 0 0 eee eee eee 164 22 9 Identification registers 2 00 c eee ee 165 22 10 System configuration registers liliis 167 22 10 14 XPERCON and XPEREMU registers 0 000e eee 174 22 11 Emulation dedicated registers 0 cee ee 175 23 Electrical characteristics 2 0c cece eee eee 176 23 1 Absolute maximum ratings
289. wo 16 channel CAPCOM units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 125ns at 64 MHz CPU clock The CAPCOM units are typically used to handle high speed I O tasks such as pulse and waveform generation pulse width modulation PMW Digital to Analog D A conversion software timing or time recording relative to external events Four 16 bit timers TO T1 T7 T8 with reload registers provide two independent time bases for the capture compare register array The input clock for the timers is programmable to several prescaled values of the internal system clock or may be derived from an overflow underflow of timer T6 in module GPT2 This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements In addition external count inputs for CAPCOM timers TO and T7 allow event scheduling for the capture compare registers relative to external events Each of the two capture compare register arrays contain 16 dual purpose capture compare registers each of which may be individually allocated to either CAPCOM timer TO or T1 T7 or T8 respectively and programmed for capture or compare functions Each of the 32 registers has one associated port pin which serves as an input pin for triggering the capture function or as an output pin to indicate the occurrence of a compare event When a capture compare register h
290. xraL 4 48 4 FXTAL x3 1 0 1 4to8MHz Fyqu 4 64 2 FxrAL x8 1 0 0 6 4to12 MHz Fyqy 4 40 2 FXTAL x 5 0 1 1 1to64 MHz PLL bypassed i FXTAL x 1 0 1 O0 4t064 MHz Fyqa 2 40 2 FxraL x 10 0 0 1 4to 12MHz PLL bypassed Fpl 2 FxraL 2 0 0 0 4MHz FyraL 2 64 2 FXTAL x 16 The PLL input frequency range is limited to 1 to 3 5 MHz while the VCO oscillation range is 64 to 128 MHz The CPU clock frequency range when PLL is used is 16 to 64 MHz Example 1 Fyra 4 MHz P0 15 13 110 multiplication by 3 PLL input frequency 1 MHz VCO frequency 48 MHz PLL output frequency 12 MHz VCO frequency divided by 4 Fepu 12 MHz no effect of output prescaler ST10F276 Electrical characteristics 23 8 9 23 8 10 23 8 11 Example 2 Fyra 8 MHz P0 15 13 100 multiplication by 5 PLL input frequency 2 MHz VCO frequency 80 MHz PLL output frequency 40 MHz VCO frequency divided by 2 Fepy 40 MHz no effect of output prescaler PLL Jitter Two kinds of PLL jitter are defined e Self referred single period jitter Also called Period Jitter it can be defined as the difference of the Tmax and Tmin where Tmax is the maximum time period of the PLL output clock and Tmin is the minimum time period of the PLL output clock e Self referred long term jitter Also called N period jitter it can be defined as the differen
291. ystem reset ST10F276 19 7 122 229 Figure 36 SW WDT bidirectional RESET EA 0 followed by a HW RESET RSTIN 250ns 250ns lt 500 ns i lt 500 ns 4 p T RSTF a _ ai F After Filter i 7 P0 15 13 XK nottransparent X P0 12 8 X transparent not t X X PO 7 2 X not transparent i K xX PO 1 0 X not transparent not t X X 8TCL ALE i i 1024 TCL lt gt RST e A i At this time RSTF is sampled LOW RSTOUT so HW Reset is entered Reset circuitry Internal reset circuitry is described in Figure 39 The RSTIN pin provides an internal pull up resistor of 50kQ to 250kQ The minimum reset time must be calculated using the lowest value It also provides a programmable BDRSTEN bit of SYSCON register pull down to output internal reset state signal synchronous reset watchdog timer reset or software reset This bidirectional reset function is useful in applications where external devices require a reset signal but cannot be connected to RSTOUT pin This is the case of an external memory running codes before EINIT end of initialization instruction is executed RSTOUT pin is pulled high only when EINIT is executed The RPD pin provides an internal weak pull down resistor which discharges external capacitor at a typical rate of 200uA If bit PWDCFG of SYSCON register is set an internal pull up resistor is activated at the end of the rese
292. z GPU 1 0us 3 91 kHz 976 6Hz 244 1Hz 61 01Hz 15 26Hz Clock 64 Mode 1 Resolution 8 bit 10 bit 12 bit 14 bit 16 bit CPU Clock 1 15 6ns 125 kHz 31 25 kHz 7 81 kHz 1 95 kHz 488 3Hz di 1 0us 1 95 kHz 488 28Hz 122 07Hz 30 52Hz 7 63Hz Clock 64 ky ST10F276 Parallel ports 12 12 1 Parallel ports Introduction The ST10F276 MCU provides up to 111 I O lines with programmable features These capabilities bring very flexible adaptation of this MCU to wide range of applications ST10F276 has nine groups of I O lines gathered as follows e PortO is a two time 8 bit port named POL Low as less significant byte and POH high as most significant byte Port 1 is a two time 8 bit port named P1L and P1H Port 2 is a 16 bit port Port 3 is a 15 bit port P3 14 line is not implemented Port 4 is a 8 bit port Port 5 is a 16 bit port input only Port 6 Port 7 and Port 8 are 8 bit ports These ports may be used as general purpose bidirectional input or output software controlled with dedicated registers For example the output drivers of six of the ports 2 3 4 6 7 8 can be configured bit wise for push pull or open drain operation using ODPx registers The input threshold levels are programmable TTL CMOS for all the ports The logic level of a pin is clocked into the input latch once per state time regardless whether the port is configured for input or output The threshold is selected with PICON and XPICON registe

ST10F276

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