Single Event Upsets Simulation Tool (SST) User Manual
Contents
1. regsub ns runningtime sample if Ssample gt 3030 echo ERROR SEU is inserted in a past time 3030 else 3030 sample set run expr 3030 sample run run ns define signal path set wire firtb dut reg_next 5 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 3030ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value set runningtime getactivecursortime regsub ns runningtime sample if Ssample gt 3125 echo ERROR SEU is inserted in a past time 3125 else 3125 sample set run expr 3125 sample run run ns define signal path set wire firtb dut reg 5 examine current value set wire_checked_val exa wire flip one bit of the wire 17 Universidad Antonio de Nebrija e SEU Configuration Of x Manual Option E Bit Upset 3 Instances Option L Filter Sega Number Number Option SS _ Filter pattern 5 Number Time Option Start time 4000 Woo i window length o window unit Restore M File Namef wif est_restore wlf SEUs in the same slots of time Yes reg_next 5 4us 4us Both SEUs are considered like one set wire_upset_val exec perl S SST_bit_flip pl wire2. run 1000 ns define signal path set wire firtb dut reg 4 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire to wire_upset_val 2000ns 15 Universidad Antonio de Nebrija force deposit wire wire_upset_val j else echo Unable to upset wire Undef value run all 16 Universidad Antonio de Nebrija Inject SEUs from a RESTORED simulation RANDOM SEU Configuration Manual Option E Instances Option D Filter pattern jut Number Number Option E Filter pattern ss Number Time Option 3000 Time Unit Start time Restore est_restore wlf File Namef wlf SEUs at different time slots Force Name Time No reg 1 Ons No reg 2 Ons No reg 3 Ons No reg 4 Ons Yes reg 5 3 125us No reg 6 Ons No reg 7 Ons No reg 8 Ons No reg_next 1 Ons No reg_next 2 Ons No reg_next 3 Ons No reg_next 4 Ons reg_next 5 3 03us No reg_next 6 Ons No reg_next 7 Ons No reg_next 8 Ons No reg_salida Ons No reg_salida_next Ons SST DO Macro generated by SST_upset_generator pl onbreak abort 1 echo Reloaded a Simulation from Initial State noview wave vsim restore file_name_restore 2 wires forced onbreak abort 1 echo Starting SEU simulation set runningtime getactivecursortime
3. delta 2 reference_compare firtb dut reg 01110010 10111010 11100011 11101110 00000011 10010000 00101000 11100110 sim firtb dut reg 01110010 10111000 11100011 11101110 00000011 10010000 00101000 11100110 Diff number 11 From time 90050 ns delta 2 to time 90150 ns delta 2 reference_compare firtb dut reg 2 10111010 sim firtb dut reg 2 10111000 Diff number 12 From time 90050 ns delta 2 to time 90150 ns delta 2 reference_compare firtb dut reg 2 1 1 sim firtb dut reg 2 1 0 Diff number 13 From time 90050 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_salida 9 1 sim firtb dut reg_salida 9 0 Diff number 14 From time 90050 ns delta 2 to time 90150 ns delta 2 reference_compare firtb dut reg_next 10001000 01110010 10111010 11100011 11101110 00000011 10010000 00101000 sim firtb dut reg_next 10001000 01110010 10111000 11100011 11101110 00000011 10010000 00101000 Diff number 15 From time 90050 ns delta 2 to time 90150 ns delta 2 reference_compare firtb dut reg_next 3 10111010 sim firtb dut reg_next 3 10111000 Diff number 16 From time 90050 ns delta 2 to time 90150 ns delta 2 wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 1148985ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 2195 ns define signal path set wire fir
4. else echo Unable to upset wire Undef value run all status Universidad Antonio de Nebrija Inject SEUs from an initial state and save the simulation SST DO EU Configuration Manual Option Macro generated by SST_upset_generator pl 6 wires forced Bit Upset a onbreak abort 1 Instances Option echo Starting SEU simulation plus checkpoint noview wave a add wave sim signals Filter pattern jut O Number la A run 1120 ns Humber anuon define signal path B set wire firtb dut reg_salida Filter salida Number E examine current value set wire_checked_val exa wire Mane gee flip one bit of the wire Start time 2000 Time Unit Eg set wire_upset_val exec perl S SST_bit_flip pl s wire_checked_val bit_in_m Window length Z window unit LIEI if Swire_upset_val undefined Checkpoint echo Forcing wire to wire_upset_val 2180ns a wire wire_upset_val a itestl Signal TT echo Unable to upset wire Undef value Time MN Time unit FS run 105 ns define signal path set wire firtb dut reg_salida examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire to wire_upset_val 2285ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 295 ns define signal pat
5. be done by filtering their names using patterns introduced via the command line interface The patterns should be perl like regular expressions e Number It is the number of instances to be selected Number option These options are used to set the amount of signals that will be evaluated It has 3 switches e Not fixed The number of inputs and signals is calculated using a parameter defined in SST_config tcl e Filter The selection of signals will be done by filtering their names using patterns introduced via the command line interface The patterns should be perl like regular expressions e Number It is the number of signals to be evaluated Time option This option is used to schedule the evaluation process Given a starting time value zero if omitted and a simulation window the script will randomly set a time value between the specified limits for each forced signal Respect to the other tree options Checkpoint Restore Comparison they are functionalities that have been upgraded to add the simulation options from the SST The multiple combinations of these options with the injection campaigns show a widely range of utilities for the designer In the next pages we will show some examples of these operations 12 Universidad Antonio de Nebrija Save a simulation without SEUs or SETs GOLDEN SIMULATION x SEU Configuration SST DO Manual Option Macro generated by SST_upset_generator pl i onbre
6. set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 4085ns ae wire wire_upset_val echo Unable to upset wire Undef value Comparison echo Comparing i dataset open reference_compare wlf ICCO jce_compare wif regsub wif reference_compare wlf sample Report Name log txt compare start hide sample sim compare add r sample firtb dut compare info write log txt status Info Reported log txt Sample Report LOG TXT Total signals compared 8 Total primary differences 10 Total secondary differences 12 Number of primary signals with differences 9 Diff number 1 From time 4015 ns delta 2 to time 4050 ns delta 2 reference_compare firtb dut reg 01010010 01100000 01110100 10000011 11110001 00010110 01001000 10101111 sim firtb dut reg 01010010 01100000 01110100 10000011 11010001 00010110 01001000 10101111 Diff number 2 From time 4015 ns delta 2 to time 4050 ns delta 2 reference_compare firtb dut reg 5 11110001 sim firtb dut reg 5 11010001 Diff number 3 From time 4015 ns delta 2 to time 4050 ns delta 2 reference_compare firtb dut reg 5 5 1 sim firtb dut reg 5 5 0 Diff number 4 From time 4015 ns delta 2 to time 4050 ns delta 2 23 Universidad Antonio de Nebrija reference_compare firtb dut reg_salida_next 00010100111
7. sim firtb dut reg_salida_next 00010000111 Diff number 5 From time 4015 ns delta 2 to time 4050 ns delta 2 reference_compare firtb dut reg_salida_next 5 1 sim firtb dut reg_salida_next 5 0 Diff number 6 From time 4015 ns delta 2 to time 4050 ns delta 2 reference_compare firtb dut reg_next 10010011 01010010 01100000 01110100 10000011 11110001 00010110 SEU Configuration ir Instances Option E Filter Somat Number Number Option E Filter Number Time Option Start time fo Time Unit Window length 2000 0 unit Comparison OA reference_comp Report Name log txt Comparing reference_compare wlf opened as dataset reference_compare 1 Created 8 comparisons Computing waveform differences from time 0 ns to 1919735 ns Found 684 differences LOG TXT Total signals compared 8 Total primary differences 156 Total secondary differences 150 Number of primary signals with differences 32 Diff number 1 From time 89965 ns delta 2 to time 90050 ns delta 2 reference_compare firtb dut reg 10111010 11100011 11101110 00000011 10010000 00101000 11100110 10011110 SST DO Macro generated by SST_upset_generator pl 10 wires forced onbreak abort 1 echo Starting SEU simulation run 47485 ns define signal path set wire firtb dut reg 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_v
8. 00011 11101110 00000011 10010000 Diff number 23 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_next 4 10111010 sim firtb dut reg_next 4 10111000 Diff number 24 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_salida_next 11101000000 sim firtb dut reg_salida_next 11100111110 Diff number 25 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_salida_next 4 1 sim firtb dut reg_salida_next 4 0 Diff number 26 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_salida_next 6 0 sim firtb dut reg_salida_next 6 1 Diff number 27 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_salida_next 7 0 sim firtb dut reg_salida_next 7 1 Diff number 28 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_salida_next 8 0 sim firtb dut reg_salida_next 8 1 Diff number 29 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_salida_next 9 0 sim firtb dut reg_salida_next 9 1 Diff number 30 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_next 4 1 1 sim firtb dut reg_next 4 1 0 Diff number 31 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_salida_next 5 0 sim firtb
9. 0110 10011110 Diff number 2 From time 89965 ns delta 2 to time 90050 ns delta 2 reference_compare firtb dut reg 1 10111010 sim firtb dut reg 1 10111000 Diff number 3 From time 89965 ns delta 2 to time 90050 ns delta 2 reference_compare firtb dut reg 1 1 1 sim firtb dut reg 1 1 0 Diff number 4 From time 89965 ns delta 2 to time 90050 ns delta 2 reference_compare firtb dut reg_salida_next 11011001010 sim firtb dut reg_salida_next 11011001000 Diff number 5 From time 89965 ns delta 2 to time 90150 ns delta 2 reference_compare firtb dut reg_salida_next 9 1 sim firtb dut reg_salida_next 9 0 Diff number 6 From time 89965 ns delta 2 to time 90050 ns delta 2 reference_compare firtb dut reg_next 01110010 10111010 11100011 11101110 00000011 10010000 00101000 11100110 sim firtb dut reg_next 01110010 10111000 11100011 11101110 00000011 10010000 00101000 11100110 Diff number 7 From time 89965 ns delta 2 to time 90050 ns delta 2 reference_compare firtb dut reg_next 2 10111010 sim firtb dut reg_next 2 10111000 Diff number 8 From time 89965 ns delta 2 to time 90050 ns delta 2 reference_compare firtb dut reg_next 2 1 1 sim firtb dut reg_next 2 1 0 Diff number 9 From time 90050 ns delta 2 to time 90150 ns delta 2 reference_compare firtb dut reg_salida 11011001010 sim firtb dut reg_salida 11011001000 Diff number 10 From time 90050 ns delta 2 to time 90150 ns
10. E Universidad sy Antonio de Nebrija Single Event Upsets Simulation Tool SST User Manual Computer Architecture and Technology Group Universidad Antonio de Nebrija Ref TR 2006Nov 001 Madrid November 3 2006 Universidad Antonio de Nebrija Table of Contents 1 SCOPE 2 TERMS AND ACRONYMS 3 OVERVIEW 4 INSTALLATION 5 DIRECTORY STRUCTURE 5 1 5 2 Files supplied by the user Files generated by the tool 6 RUNNING THE TOOL 6 1 6 2 6 3 6 4 6 5 6 6 6 7 Choose Version Setup Some Parameters Load the Test Bench of the DUT in the simulator Gather the information about the design Select the wires that will be upset Others Funtionalities Run a simulation introducing the upsets Universidad Antonio de Nebrija 1 SCOPE The purpose of this document is to describe how the new release of the Single Event Upsets Simulation Tool SST shall be used with the most recent updates and upgrade works 2 TERMS AND ACRONYMS DUT Design Under Test GUI Graphical User Interface SEU Single Event Upset SET Single Event Transient SST Single Event Upset Simulation Tool 3 OVERVIEW The SEUs Simulation Tool consists of a set of Perl and Tcl scripts that used in conjunction with a Design Under Test and a Test Bench allows the user to upset bit flip any register or internal signal in a controlled and effective way The scripts can be invoked using the Graphical
11. SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire to wire_upset_val 2970ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value if time_checkpoint 0 set var list compare wlf restore wlf set file_name_compare join file_name_checkpoint compare wilf _ set file_name_restore join file_name_checkpoint restore wlf _ checkpoint file_name_restore dataset save sim file_name_compare status else run time_checkpoint t_u set var list compare wlf restore wlf set file_name_compare join file_name_checkpoint compare wilf _ set file_name_restore join file_name_checkpoint restore wlf _ checkpoint file_name_restore dataset save sim file_name_compare status 20 Universidad Antonio de Nebrija Fault Injection Campaign at unreachable past time ET Configuration Manual Option Instances Option L Filter Somat Number h Number Option L Filter Sos O o Number p Time Option 2000 Time Unit Start time Window length fioo window unit Checkpoint v ape test Tuan Time fo Tine Unit ps Starting simulation Starting SEU simulation plus checkpoint ERROR SEU is inserted in a past time SST DO Macro generated by SST_upset_generator pl 2 wires forced onbreak abort 1 echo Starting SEU simulation plus checkpoint noview wave add w
12. User Interface provided with the tool The current version of the SST works with Modelsim 6 1b Any simulator supporting the force command could be easily added in the future For any comment regarding this document question suggestion mistake detection please contact Oscar Ruano at oruano Onebrija es 4 INSTALLATION Prior to copying the SST files into your computer make sure that your system has Perl installed It can be downloaded for free from http www perl com download csp The following two actions have to be performed before running the tool Extract all the SST files into the same directory installation for example C SSTOI The folder in which the scripts are finally placed should be added both to your path environment variable and to the DOPATH environment variable Figures 1 2 Universidad Antonio de Nebrija Propiedades del sistema _ Restaurar sistema _ Actualizaciones autom ticas Variables de entorno Modificar la variable del sistema Nombre de variable Path BoPS BIN WIN32 AMET Ec ARCHIV 1 Valor de variable Variables del sistema Variable Valor i oe Windows_NT C PERL BIN C ARCHIV 1 BORLAND COM EXE BAT CMD VBS VBE J5 PROCESSOR_A x86 Nueva Modificar Eliminar Figure 1 Propiedades del sistema LM_LICENSE_FILE PATH TEMP TMP C flexlm icense dat C Modeltech_5 8 win32 C Mo
13. _checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 3125ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value SST DO Macro generated by SST_upset_generator pl onbreak abort 1 echo Reloaded a Simulation from Initial State noview wave vsim restore file_name_restore 2 wires forced onbreak abort 1 echo Starting SEU simulation set runningtime getactivecursortime regsub ns runningtime sample if Ssample gt 4000 echo ERROR SEU is inserted in a past time 4000 else 4000 sample set run expr 4000 sample run run ns define signal path set wire firtb dut reg_next 5 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 4000ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value define signal path set wire firtb dut reg_next 5 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 4000ns force deposit wire wire_upset_val
14. ak abort 1 nI echo Starting GOLDEN simulation Bit Upset a add wave sim firtb dut 7 restart f Instances Option run 1000ns 5 set var list compare wlf restore wlf Filter patter zy set file_name_compare join testi compare wlf _ gill eel dais mu set file_name_restore join testi restore wlf _ Number Option checkpoint file_name_restore E dataset save sim file_name_compare status Filter pater O OE Sz Time Option This golden simulation record 1000 ns for example to make a comparison later Start time p ite Unit ns Window length o window uni Checkpoint v Time Time Unk Prs 13 Universidad Antonio de Nebrija Restore a previous saved simulation ready to inject SEUs or simply run more cycles SST DO Manual Option Macro generated by SST_upset_generator pl onbreak abort 1 Bit Upset echo Reloaded a Simulation from Initial State vsim restore file_name_restore Instances Option status E Filter patter MMMM Number Number Option Filter pattern haa Number Time Option Start time fo Time Unit Window length o window unit TJ SEU Configuration Restore File Name wlf 14 Universidad Antonio de Nebrija Inject SEUs from a previous RESTORED simulation MANUAL SEU C Lo 520 Configuration O ES Checkpoint m File Name Time Comparation Reference File wif Log File Tim
15. al exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 47485ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 376645 ns define signal path set wire firtb dut reg 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 424130ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 131960 ns define signal path set wire firtb dut reg_next 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 556090ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 592895 ns define signal path set wire firtb dut reg 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl 24 Universidad Antonio de Nebrija sim firtb dut reg 10111000 11100011 11101110 00000011 10010000 00101000 1110
16. ave sim signals echo ERROR SEU is inserted in a past time 21 Universidad Comparison Antonio de Nebrija fu SEU Configuration Manual Option m a Instances Option E Filter pattern Number Option Time Option Start time Comparation EA test2_compare v Log File log txt Number Filter patter MOMIA Number 22 SST DO Macro generated by SST_upset_generator pl onbreak abort 1 echo Comparing dataset open oscar_compare wlf regsub wlf oscar_compare wlf sample compare start hide sample sim compare add r sample firtb dut compare run compare info all primaryonly signals secondaryonly summary write xxx 20 50 status Universidad Antonio de Nebrija SST DO Macro generated by SST_upset_generator pl 2 wires forced onbreak abort 1 echo Starting SEU simulation run 4015 ns define signal path set wire firtb dut reg 5 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 4015ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 70 ns define signal path set wire firtb dut reg 5 examine current value set wire_checked_val exa wire flip one bit of the wire
17. ction of the wires that are going to be upset has to be done by clicking in the Configuration SEU Configuration GUI menu button and filling the entry boxes and check buttons of the interface window Figure 10 shows the SEU Configuration window RA SEU Configuration BAR Manual Option F Bit Upset k Instances Option a Filter pattern e Number Number Option _ Filter pattern O O Number Time Option Start time o IGG Unit ns Window length o window unit Eg Checkpoint E File Name Sigrials MN Time BMW Time Uni Restore File Name wf PO Comparison a Reference File wif l Report Name Figure 10 Bit Upset This option indicates the bit number into a bus signal If you do not fill it the upset will be inserted randomly Manual option The script just reads all_instances dat and the Input files which have been edited by the user and prepares the evaluation of the selected signals at the specified time values This option excludes the rest of fault injection Instances Option and Number Options Instances option This option is used to set the amount of instances to be selected in all_instances dat It has 3 switches 11 Universidad Antonio de Nebrija e Read The user has selected the instances by manually editing the file all_instances dat The script will read the file as an input e Filter The selection of instances will
18. d_val exa wire flip one bit of the wire Restore set wire_upset_val exec perl S SST_bit_flip pl cd wire_checked_val bit_in_m if wire_upset_val undefined File Namef wl echo Forcing wire wire_checked_val to wire_upset_val 2000280ns Comparison force deposit wire wire_upset_val else echo Unable to upset wire Undef value OA fence_compare m Report Name kuku txt set runningtime getactivecursortime regsub ns runningtime sample puts traza sample if sample gt 2001230 puts ERROR SEU is being inserted at past time SEU 2001230 vs NOW runningtime else 2001230 sample set run expr 2001230 sample run run ns define signal path set wire firtb dut reg 5 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 2001230ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value 28 Universidad Antonio de Nebrija Y SEU Configuration Manual Option i Bit Upset Instances Option Filter Seog Number Number Option E Filter Aeg O o Number Time Option Start time 0000 Wo i Restore File Namel wif nce_restore wif Comparison AA ence_compare m Report Name kuku
19. deltech_ C Documents and Settings Oscar Confi C Documents and Settings Oscar Confi Variables del sistema Nueva Modificar Al Eliminar Variable PROCESSOR_A Valor Windows_NT C PERL BIN C ARCHIV 1 BORLAND COM EXE BAT CMD VBS VBE JS x86 Figure 2 Nueva Modificar Eliminar 5 DIRETORY STRUCTURE a Files supplied by the user HDL testbench_files b Files generated by the tool SST control_files all_wires_parser log all_instances dat SST_perl_package pm SST wire_files In this folder we can find all the wire files hierarchy dat sst do Universidad e Antonio de Nebrija ka E 6 RUNNING THE TOOL To invoke the GUI type do SST_gui tcL in the Modelsim command line interface The following window appears Figure 3 Graphical User Interface main window 6 1 Choose Version The main idea of this option consists in integrating both versions into the same package Compatible with ModelSim 6 1 Compatible Modelsim 5 8 This allows the user changing the version depending on the simulator release In this document we will only refer to the last update performed around version 6 1 For the version compatible with Modelsim 5 8 please consult the related documents E A Universidad amp amp Antonio de Nebrija Figure 4 Unive
20. dut reg_salida_next 5 1 j else echo Unable to upset wire Undef value run 84230 ns define signal path set wire firtb dut reg 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 1692380ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 227355 ns define signal path set wire firtb dut reg 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 1919735ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value echo Comparing dataset open file_name_gold regsub wlf file_name_gold sample compare start hide sample sim compare add r sample firtb dut compare run compare info write file_name_summary status 26 Universidad Antonio de Nebrija Diff number 32 From time 90250 ns delta 2 to time 90350 ns delta 2 reference_compare firtb dut reg_salida 11101000000 sim firtb dut reg_salida 11100111110 Diff number 33 From time 90250 ns delta 2 to time 90350 ns delta 2 refe
21. e _unit This variable holds the unit used as a reference for the creation of upsets This reference value will be used when one of the input units of the t switch of the SST_upset_generator script is missing The value of this variable should be the same as the VHDL simulation step resolution of our simulation Forces with a smaller unit will not be allowed Figure 8 Universidad Antonio de Nebrija 6 3 Load the Test Bench of the DUT in the simulator Prior to start executing the SST it is necessary to load the test bench that checks the correct functionality of the DUT into Modelsim 6 1 Universidad e Antonio de Nebrija UE 6 4 Gather the information about the design In order to let the SST know about the design to be tested basically its hierarchy and the number and type of signals found in each module the user will have to click in the Tasks Load Design menu button of the GUI Figure 9 Ral SST lt C Datos Doctorado SAAN DUT FIR gt Version Configuration Tasks Preferences Help Load Design Run Simulation EE La zz y E f Figure 9 It is in this moment when the structure mentioned before Files generated by the tool 1s created SST wire_files SST control_files 10 Universidad Antonio de Nebrija 6 5 Select the wires that will be upset Once the information about the design has been collected the sele
22. es for SEUs are relative to the initial state For instance 1000 reg6 and 2000 reg4 ns respect to the simulation restored represent a SEU in 2000ns for reg6 and 3000 ns for reg4 in absolute times Correct the Transcript message firtb dut reg 6 01110001 01110101 Forcing firtb dut reg 6 to 01110101 1000ns gt 2000ns firtb dut reg 4 11110001 11110101 Forcing firtb dut reg 4 to 11110101 2000ns gt 3000ns current state nN all_instances dat Force File name wires Instance full path No firtb 4 firtb Yes dut 18 firtb dut dut internal Force Name Time No reg_salida Ons No reg_salida_next Ons No reg_next 1 Ons No reg_next 2 Ons No reg_next 3 Ons No reg_next 4 Ons No reg_next 5 Ons No reg_next 6 Ons No reg_next 7 Ons No reg_next 8 Ons No reg 1 Ons No reg 2 Ons No reg 3 Ons Yes reg 4 2000ns No reg 5 Ons Yes reg 6 1000ns No reg 7 Ons No reg 8 Ons SST DO Macro generated by SST_upset_generator pl 2 wires forced onbreak abort 1 echo Starting SEU simulation run 1000 ns define signal path set wire firtb dut reg 6 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire to wire_upset_val 1000ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value
23. h set wire firtb dut reg_salida examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire to wire_upset_val 2580ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 15 ns define signal path set wire firtb dut reg_salida examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire to wire_upset_val 2595ns esti_restore wl 19 Universidad Antonio de Nebrija force deposit wire wire_upset_val j else echo Unable to upset wire Undef value run 75 ns define signal path set wire firtb dut reg_salida_next examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire to wire_upset_val 2670ns force deposit wire wire_upset_val j else echo Unable to upset wire Undef value run 300 ns define signal path set wire firtb dut reg_salida_next examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S
24. m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 1608150ns force deposit wire wire_upset_val 23 Universidad Antonio de Nebrija reference_compare firtb dut reg_salida_next 11110011110 sim firtb dut reg_salida_next 11110011100 Diff number 17 From time 90050 ns delta 2 to time 90150 ns delta 2 reference_compare firtb dut reg_next 3 1 1 sim firtb dut reg_next 3 1 0 Diff number 18 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_salida 11110011110 sim firtb dut reg_salida 11110011100 Diff number 19 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg 10001000 01110010 10111010 11100011 11101110 00000011 10010000 00101000 sim firtb dut reg 10001000 01110010 10111000 11100011 11101110 00000011 10010000 00101000 Diff number 20 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg 3 10111010 sim firtb dut reg 3 10111000 Diff number 21 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg 3 1 1 sim firtb dut reg 3 1 0 Diff number 22 From time 90150 ns delta 2 to time 90250 ns delta 2 reference_compare firtb dut reg_next 11000011 10001000 01110010 10111010 11100011 11101110 00000011 10010000 sim firtb dut reg_next 11000011 10001000 01110010 10111000 111
25. ningtime sample puts traza sample if Ssample gt 2001945 puts ERROR SEU is being inserted at past time SEU 2001945 vs NOW runningtime else 2001945 sample set run expr 2001945 sample run run ns 29 Universidad Antonio de Nebrija define signal path set wire firtb dut reg 5 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 2001945ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value set runningtime getactivecursortime regsub ns runningtime sample puts traza sample if Ssample gt 2002785 puts ERROR SEU is being inserted at past time SEU 2002785 vs NOW runningtime j else 2002785 sample set run expr 2002785 sample run run ns define signal path set wire firtb dut reg_next 5 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 2002785ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value echo Comparing dataset open file_name_gold
26. regsub wlf file_name_gold sample compare start hide sample sim compare add r sample firtb dut compare run compare info write file_name_summary status 30
27. rence_compare firtb dut reg_salida 5 0 sim firtb dut reg_salida 5 1 Diff number 34 From time 90250 ns delta 2 to time 90350 ns delta 2 reference_compare firtb dut reg_salida 9 0 sim firtb dut reg_salida 9 1 Diff number 35 From time 90250 ns delta 2 to time 90350 ns delta 2 reference_compare firtb dut reg 11000011 10001000 01110010 10111010 11100011 11101110 00000011 10010000 sim firtb dut reg 11000011 10001000 01110010 10111000 11100011 11101110 00000011 10010000 Diff number 36 From time 90250 ns delta 2 to time 90350 ns delta 2 reference_compare firtb dut reg 4 10111010 sim firtb dut reg 4 10111000 Diff number 37 From time 90250 ns delta 2 to time 90350 ns AAA E 27 Universidad Antonio de Nebrija Restore Fault Injection Campaign Compare SST DO Macro generated by SST_upset_generator pl y SEU Configuration onbreak abort 1 echo Reloaded a Simulation from Initial State noview wave vsim restore file_name_restore 6 wires forced onbreak abort 1 echo Starting SEU simulation set runningtime getactivecursortime regsub ns runningtime sample puts traza sample if sample gt 2000280 puts ERROR SEU is being inserted at past time SEU 2000280 vs NOW runningtime else 2000280 sample set run expr 2000280 sample run run ns define signal path set wire firtb dut reg 5 examine current value set wire_checke
28. rsidad Antonio de Nebrija 6 2 Setup Some Parameters This window Figure 5 is used to configure some parameters via GUI that they are needed in order to setup the tool For instance you can modify the type of signals filtered by the SST with the mask parameter Another example of this is the smallest time distance between two SEUs or SETs filling the reference step iy Setting Up File Extension Mask Reference Unit Reference Step 0 o y Figure 6 Figure 5 Universidad Antonio de Nebrija For more information about these parameters or switches use the following option Figure 7 r Help Contents Welcome Menu FAQs About SST Figure 7 and it will show a brief description for these parameters on the Modelsim Transcript screen Figure 8 TRANSCRIPT WINDOW HELP OPTION wire_files_ext This variable holds the name of the wire files extension The type of wire is selected using wire_mask Use a meaningfull extension for each type of selected wire ie out if the outputs were selected wire_mask This variable holds the decimal value of the mask used to select the type of wire we are interested in Please update the following binary layout used to obtain the decimal number you need every time you change the value of the mask Mask MSB LSB lt internal inouts outputs inputs gt referenc
29. tb dut reg_next 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 1151180ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 29115 ns define signal path set wire firtb dut reg 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 1180295ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 20750 ns define signal path set wire firtb dut reg_next 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if Swire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 1201045ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value run 407105 ns define signal path set wire firtb dut reg 1 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_
30. txt set runningtime getactivecursortime regsub ns runningtime sample puts traza sample if sample gt 2001295 puts ERROR SEU is being inserted at past time SEU 2001295 vs NOW runningtime else 2001295 sample set run expr 2001295 sample run run ns define signal path set wire firtb dut reg 5 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 2001295ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value set runningtime getactivecursortime regsub ns runningtime sample puts traza sample if Ssample gt 2001425 puts ERROR SEU is being inserted at past time SEU 2001425 vs NOW runningtime else 2001425 sample set run expr 2001425 sample run run ns define signal path set wire firtb dut reg 5 examine current value set wire_checked_val exa wire flip one bit of the wire set wire_upset_val exec perl S SST_bit_flip pl wire_checked_val bit_in_m if wire_upset_val undefined echo Forcing wire wire_checked_val to wire_upset_val 2001425ns force deposit wire wire_upset_val else echo Unable to upset wire Undef value set runningtime getactivecursortime regsub ns run
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