Errata sheet - STMicroelectronics
Contents
1. 0 0 00 e eee 34 2 17 1 Comparators propagation delay is longer than expected for input steps higher than 200 MV 0 eee 34 2 17 2 Comparators output cannot be configured in open drain 34 2 17 3 COMP1 and COMP2 configuration lost with software reset 35 2 18 LPTIM peripheral limitations 0 0 0 0 0 cee ees 35 4 38 DoclD026121 Rev 3 ky STM32L4x6xx Contents 2 18 1 Low power timer 1 LPTIM1 outputs cannot be configured in Open drain 00000 tees 35 2 19 LPUART peripheral limitations 0 000020 2 eee eee 35 2 19 1 Low power UART1 LPUART1 outputs cannot be configured in opem diaiN osc Seance ances ahaa hte AA gu Gens dana ae eh ies BSH ge ak WUE eae vad 35 2 20 AES peripheral limitations 0 0 0 2 ee eee 36 2 20 1 Burst read or write accesses are not supported by the AES 36 2 20 2 AES does not support Load multiple 22245 36 3 REVISION history ws wersdaee te eke wees eee eeaaw eRe bee sd eters ean 37 ky DoclD026121 Rev 3 5 38 List of tables STM32L4x6xx List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 6 38 Device identification 00000 1 Device SUMMA 1 eae 1 Cortex M4 FPU core limitations and impact on microcontroller behavior 8 Summary of silicon limitation 0 0 0 aaaea 9 COMP characteristics nnana aaa aeaa teens 34 Document revisio2. Description When all the conditions listed below are gathered e QUADSPI is used in indirect mode e QUADSPI clock is AHB 2 PRESCALER 0x01 in the QUADSPI_CR e QUADSPI is in quad mode DMODE 0b11 in the QUADSPI_CCR e QUADSPI is in DDR mode DDRM 0b1 in the QUADSPI_CCR An extra data is incorrectly written in the FIFO when a data is read at the same time that the FIFO gets full at the end of a read transfer Workaround One of the two workarounds listed below can be done e Read out the extra data until the BUSY flag goes low and discard it e Request an abort after reading out all the correct received data from FIFO in order to flush FIFO and have the busy low Abort will keep the last register configuration set the ABORT bit in the QUADSPI_ CR ADC peripheral limitations Injected queue of context is not available in case of JQM 0 Description The queue mechanism is not functional when JQM 0 The effective queue length is equal to 1 stage a new context written before the previous context s consumption will lead to a queue overflow and will be ignored Consequently the ADC must be stopped before programming the JSQR register Workaround None DoclD026121 Rev 3 21 38 STM32L4x6xx silicon limitations STM32L4x6xx 2 4 2 2 4 3 2 4 4 22 38 ADC triggers from EXTI require external interrupt management Description When the ADC external trigger for regular or injected channel selects the EXTI lin
3. Section 2 4 5 Burst read or write accesses are not supported by the ADC Section 2 6 1 12C Fast mode Plus drive is not available on all SDA SCL I Os and Section 2 6 2 Wrong behavior related with MCU Stop mode when wakeup from Stop mode by 12C peripheral is disabled Added Section 2 1 14 Full JTAG configuration without NJTRST pin cannot be used Section 2 6 4 Spurious Bus Error detection in master mode Section 2 6 5 12C3 analog filters requires that both PCO PC1 or both PG7 PG8 are configured as I2C3 alternate function and Section 2 20 AES peripheral limitations Updated Table 4 Summary of silicon limitation Added Section 2 1 15 MSIRDY flag issue preventing entry in low power mode Section 2 16 2 Calibration procedure does not work in PGA mode and Section 2 17 3 COMP1 and COMP2 configuration lost with software reset Updated Section 2 1 1 Write operation in the Flash memory while it is not ready Flash memory in power down is not correctly handled Section 2 1 12 MSI at high frequency ranges cannot be used as wakeup from Stop 0 clock source Section 2 2 4 Read burst access of 9 words or more is not supported by FMC and Section 2 12 4 SWP SUSPENDED mode not supported when STM32L4 is in Stop 0 or Stop 1 mode DoclD026121 Rev 3 37 38 STM32L4x6xx IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifica
4. wr STM32L4x6xx Sf i life augmented Errata sheet STM32L476xx STM32L486xx device limitations Silicon identification This errata sheet applies to revisions 3 and 4 of the STMicroelectronics STM32L476xx and STM32L486xx products The STM32L4x6xx family features an ARM 32 bit Cortex M4 core Section 2 gives a detailed description of the product silicon limitations The full list of part numbers is shown in Table 2 The products are identifiable by the revision code marked below the order code on the device package as shown in Table 1 Table 1 Device identification Sales type Revision code marked on the device 1 The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device see the reference manual RM0351 for details on how to find the revision code 2 Refer to datasheet for details on how to identify the revision code according to the packages Table 2 Device summary Reference Part numbers STM32L476RC STM32L476VC STM32L476JE STM32L476ME STM32L476QE STM32L476xx STM32L476RE STM32L476VE STM32L476ZE STM32L476JG STM32L476MG STM32L476QG STM32L476RG STM32L476VG STM32L476ZG STM32L486xx STM32L486JG STM32L486QG STM32L486RG STM32L486VG STM32L486ZG December 2015 DoclD026121 Rev 3 1 38 www st com Contents STM32L4x6xx Contents 1 ARM 32 bit Cortex M4 FPU core limitations 0 5 8 1 1 Cortex M4 FPU core interrupte
5. STM32L4 cannot enter Stop 0 or Stop 1 mode if SWPMI is activated and is in SUSPENDED state Workaround Deactivate the SWP bus before requesting entry in Stop 0 or Stop 1 mode Refer to the SWPMI section in the product reference manual for the deactivation procedure SWPMI_IO transceiver bypass mode is not functional Description When the internal SWPMI transceiver is bypassed by setting the SWP_TBYP bit in the SWPMI_OR register SWPMI1_RX mapped on PB14 is forced in output mode instead of input mode Workaround None The internal transceiver must be used RTC peripheral limitations Spurious tamper detection when disabling the tamper channel Description If the tamper detection is configured for detection on falling edge event TAMPFLT 00 and TAMPxTRG 1 and if the tamper event detection is disabled when the tamper pin is at high level a false tamper event is detected DoclD026121 Rev 3 ky STM32L4x6xx STM32L4x6xx silicon limitations 2 14 2 14 1 2 14 2 2 14 3 3 Workaround The false tamper event detection cannot be avoided but the backup registers erase can be avoided by setting TAMPxNOERASE bit before clearing TAMPxE bit The two bits must be written in two separate RTC_TAMPCR write accesses USART limitations Start bit detected too soon when sampling for NACK signal from the smartcard Description In the 1507816 when a character parity error is incorrect the Smartcard receiver should transmi
6. The CRC is calculated even if the response to a command does not contain any CRC field As a consequence after the SDIO command O_SEND_OP_COND CMD5 is sent the CCRCFAIL bit of the SDMMC_STA register is set Workaround The CCRCFAIL bit in the SDMMC_STA register shall be ignored by the software CCRCFAIL must be cleared by setting CCRCFAILC bit of the SDMMC_ICR register after reception of the response to the CMD5 command Clock division per 255 is not possible Description When CLKDIV divide factor in SDMMC_CLKCR register is equal to 255 the SDMMC_CK clock output is not provided Workaround Do not use CLKDIV value equals to 255 use clock divider factors from 0 to 254 Wait for response bits 10 configuration does not work correctly Description The Wait for response bits configuration 10 WAITRESP in the SDMMC_CMD register does not work correctly When WAITRESP bits are programmed to 10 Command Path State Machine CPSM waits for a non existing response Workaround Do not use WAITRESP value equal to 10 when sending a command without a response Use WAITRESP value equal to 00 to indicate to SDMMC CPSM that no response is expected MMC stream write of less than 8 bytes does not work correctly When SDMWC host starts a stream write WRITE_DAT_UNTIL_STOP CMD20 the number of bytes to transfer is not known by the card The card will write data from the host until a STOP_TRANSMISSION CMD12 com
7. 0 6 V or when VDDUSB gt VDD 0 6 V or when Vicp gt Vpp 0 6 V the I Os listed below must not be used as e general purpose output push pull or open drain e alternate function output push pull or open drain An unexpected leakage occurs between the respective supply voltage VDDA or VDDUSB or VLCD and VDD and the output state can be lost These I Os can be used in input mode e analog mode e alternate function input or analog mode DoclD026121 Rev 3 13 38 STM32L4x6xx silicon limitations STM32L4x6xx 14 38 When Vppa gt Vpp 0 6 V the concerned I Os are PAO PA1 PA2 PA3 PA4 PAS PA6 PA7 PBO PB1 PB2 PB3 PB4 PB5 PB6 PB7 PCO PC1 PC2 PC3 PC4 PC5 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 When Vppusp gt Vpop 0 6 V the concerned I Os are PAQ PA10 PA11 PA12 When Vicp gt Vpp 0 6 V the concerned I Os are PA PA2 PA3 PA6 PA7 PA8 PAY PA10 PA15 PBO PB1 PB3 PB4 PB5 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PCO PC1 PC2 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC 11 PC12 PD2 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PEO PE1 PE2 PES Workaround None Bootloader SPI and CAN interfaces are not supported Description The bootloader does not support yet SPI and CAN interfaces Workaround None SRAM2 read access while the SRAM2 hardware erase is ongoing is not correctly supported Description
8. Description The DAC is not functional when Vppa is lower than 2 7 V and APB1 frequency is higher than 40 MHz Workaround When Vppa lt 2 7 V the APB1 frequency must be reduced below 40 MHz thanks to RCC prescalers DoclD026121 Rev 3 ky STM32L4x6xx STM32L4x6xx silicon limitations 2 15 4 2 16 2 16 1 3 DAC characteristics can be degraded depending on the current sunk on DAC output Description Resistor value between DAC outputs and I O PA4 or PAS is greater than expected 80hm typical as shown in Figure 2 As a consequence the DAC characteristics can be impacted depending on the current sunk on DAC output Figure 2 Parasitic resistor on DAC output DAC Parasitic resistor 8 Ohm DAC output PAD PA4 or PA5 MS38220V1 Workaround None OPAMP limitations OPAMP characteristics can be degraded depending on the current sunk on OPAMP output Description Resistor value between OPAMP outputs and I O PA3 or PBO is greater than expected 8 ohm typical as shown in Figure 3 As a consequence the OPAMP characteristics can be impacted depending on the current sunk on the output Figure 3 Parasitic resistor on OPAMP output OPAMPx Parasitic resistor 8 Ohm OPAMP output PAD PA3 or PBO MS38219V1 Workaround None DoclD026121 Rev 3 33 38 STM32L4x6xx silicon limitations STM32L4x6xx 2 16 2 2 17 2 17 1 2 17 2
9. cannot be used when the ADC2 and ADC3 requests are selected on DMA2 channels 4 and 5 22 2 4 4 Wrong ADC conversion results when delay between calibration and first conversion or between 2 consecutive conversions is too long 22 2 4 5 Burst read or write accesses are not supported by the ADC 23 DFSDM peripheral limitations 0 000000 cee eee 23 2 5 1 RDATACH 2 0 status bits are not implemented 23 2 5 2 New regular channel selection taken into account at the end of an injected conversion when a regular conversion is pending 23 2 5 3 DFSDM triggers from timers can be missed in specific conditions 23 2 5 4 DFSDM triggers from EXTI require external interrupt management 24 I2C peripheral limitations 2 0 02 ce es 24 2 6 1 12C Fast mode Plus drive is not available on all SDA SCL I Os 24 2 6 2 Wrong behavior related with MCU Stop mode when wakeup from Stop mode by I2C peripheral is disabled 24 2 6 3 Wrong data sampling when data set up time tSU DAT is smaller than one IZCCLK period 2020s 25 2 6 4 Spurious Bus Error detection in master mode 05 25 2 6 5 I2C3 analog filters requires that both PCO PC1 or both PG7 PG8 are configured as I2C3 alternate function 25 SDMMC peripheral limitations 0 000000 eee 26 2 7 1 Wrong CCRCFAIL status after a response without CRC is received 26 2
10. cede adn wie a alae A acme ee ad ws deals Mae a 17 2 1 13 PLL may not lock if VCO is below 96 MHz and temperature is Below OFO soars ak ales are eo ae Soha pee wk Beaks than Gad anh ae oe AUD 17 2 1 14 Full JTAG configuration without NJUTRST pin cannot be used 17 2 1 15 MSIRDY flag issue preventing entry in low power mode 17 2 2 FMC peripheral limitations 00 0000 eee eee eens 19 2 2 1 Dummy read cycles inserted when reading synchronous memories 19 2 2 2 Data corruption during burst read from FMC synchronous memory 19 2 2 3 FMC bank switching to asynchronous bank for write 19 2 2 4 Read burst access of 9 words or more is not supported by FMC 20 2 3 QUADSPI peripheral limitations 2 2002 20 2 3 1 QUADSPI_BK1_101 is always an input when the command is sent in dual or quad SPI mode 000 00 cee eee eee 20 2 38 DoclD026121 Rev 3 ky STM32L4x6xx Contents 3 2 4 2 5 2 6 2 7 2 8 2 9 2 3 2 Hard fault is not generated in case of out of range memory mapped ACCESS a ae a N a a E E REA E E eee 21 2 3 3 Extra data written in the FIFO at the end of a read transfer 21 ADC peripheral limitations 2 000002 ee eee 21 2 4 1 Injected queue of context is not available in case of JQM 0 21 2 4 2 ADC triggers from EXTI require external interrupt management 22 2 4 3 DMA2 channels 2 and 3 respectively
11. is always an input when the command is sent in dual or quad SPI mode Description The 101 is staying as an input instead of changing to output to drive the command when this last is on 2 or 4 lines and there is no address no data and no alternate byte in the frame or they exist on 1 line Therefore it is not possible to use dual quad mode for the command phase This bug affects Numonyx s dual quad instruction mode Workaround The dual quad instruction mode of Micron or Numonyx flashes is working fine when user does not send only a command in the frame For example the write enable command can be avoided by writing directly the status register of the flash instead Otherwise the application can reset the flash through the reset pin if it exists to disable the duad quad instruction mode before each time it needs to send a frame which contains only the command phase DoclD026121 Rev 3 ky STM32L4x6xx STM32L4x6xx silicon limitations 2 3 2 2 3 3 2 4 2 4 1 3 Hard fault is not generated in case of out of range memory mapped access Description A hard fault is not generated when the Cortex CPU executes an instruction which reads from an out of range memory mapped address Consequently the CPU effectively skips the instruction the destination register is not modified and continues executing without giving a hard fault Workaround None Extra data written in the FIFO at the end of a read transfer
12. mode 2 0 0200 eee 30 2 12 5 SWPMI_IO transceiver bypass mode is not functional 30 2 13 RTC peripheral limitations 0 000 ee 30 2 13 1 Spurious tamper detection when disabling the tamper channel 30 2 14 USART limitations 2 0 0 0 0 0 0c eee eee 31 2 14 1 Start bit detected too soon when sampling for NACK signal from the smartcard 2000 31 2 14 2 Break request can prevent the Transmission Complete flag TC from being Set 0 eee 31 2 14 3 nRTS is active while REorUE 0 220055 31 2 15 DAC peripheral limitations 0 0020 ees 32 2 15 1 PA4 and PAS must be configured in analog mode when DAC1_OUT1 or DAC1_OUT2 respectively is connected to OPAMP input 32 2 15 2 PA4 and PA5 can t be used in output mode when DAC1_OUT1 or DAC1_OUT2 respectively is connected to on chip peripherals 32 2 15 3 DAC cannot be used at low VDDA if APB1 frequency is higher than AOM esser Secs toast des ect agen A a e meade cece Gok hes oe as 32 2 15 4 DAC characteristics can be degraded depending on the current sunk on DAC OUTPUT wena fea eres Ae eres eee eee d He needed han as 33 2 16 OPAMP limitations 0 0 0 0 0 eee eee 33 2 16 1 OPAMP characteristics can be degraded depending on the current sunk on OPAMP output 2 0 000 cee 33 2 16 2 Calibration procedure does not work in PGA mode 34 2 17 COMP peripheral limitations
13. output when VDDA gt VDD N p 0 6 V or VDDUSB gt VDD 0 6 V or VLCD gt VDD 0 6 V Section 2 1 4 Bootloader SPI and CAN interfaces are not supported N Section 2 1 5 SRAM2 read access while the SRAM2 hardware erase is N N ongoing is not correctly supported Section 2 1 6 Extra consumption when VDDA is below 0 7 V A Section 2 1 7 System clock is stopped during few us when switching between N 7 Low power run and Run modes Section 2 1 Section 2 1 8 PHO PH1 is controlled by the GPIOH registers when HSE is p p System limitations enabled Section 2 1 9 PWR_CR4 register write access may not be completed if a A A Low power mode is entered just after the write operation Section 2 1 10 HSI user trim is limited on some samples N N Section 2 1 11 Option byte loading can fail if MSI frequency is greater than 8 A A MHz Section 2 1 12 MSI at high frequency ranges cannot be used as wakeup from P i Stop 0 clock source Section 2 1 13 PLL may not lock if VCO is below 96 MHz and temperature is A A below 0 C Section 2 1 14 Full JTAG configuration without NJTRST pin cannot be used A Section 2 1 14 Full JTAG configuration without NJTRST pin cannot be used A A Section 2 1 15 MSIRDY flag issue preventing entry in low power mode A Section 2 2 1 Dummy read cycles inserted when reading synchronous N N memories Section 2 2 FMC Section 2 2 2 Data corruption during burst read from FMC synchronous i A A peripheral memory limitations
14. switching the MSI frequency to the higher frequency or use Stop 1 or Stop 2 instead of Stop 0 PLL may not lock if VCO is below 96 MHz and temperature is below 0 C Description The VCO minimum value should be 64 MHz When the VCO is below 96 MHz and the temperature is below 0 C the PLL may never lock Workaround Program the PLL with VCO at 96 MHz or above Full JTAG configuration without NJTRST pin cannot be used Description When using the JTAG debug port in debug mode the connection with the debugger is lost if the NUTRST pin PB4 is used as a GPIO Only the 4 wire JTAG port configuration is impacted Workaround Use the SWD debug port instead of the full 4 wire JTAG port MSIRDY flag issue preventing entry in low power mode Description If the MSI clock is stopped when it is running at high frequency 24 MHz or above the MSIRDY MSI ready flag can stay at value 1 instead of 0 Once this flag remains set while the MSI clock is OFF entry in Stop 0 Stop 1 Stop 2 Standby and Shutdown modes is no longer possible the product is blocked in the low power mode entry phase DoclD026121 Rev 3 17 38 STM32L4x6xx silicon limitations STM32L4x6xx 18 38 The following factors increase the probability to have this issue a high MSI frequency a low Vpp external supply a high temperature Workaround The MSI clock can run at any frequency if both conditions below are met a the system clock is MSI or PLL f
15. the BERR flag can be wrongly raised in the status register This will generate a spurious Bus Error interrupt if the interrupt is enabled A bus error detection has no effect on the transfer in master mode therefore the 12C transfer can continue normally Workaround If a bus error interrupt is generated in master mode the BERR flag must be cleared by software No other action is required and the on going transfer can be handled normally I2C3 analog filters requires that both PC0 PC1 or both PG7 PG8 are configured as I2C3 alternate function Description I2C3 analog filters can be enabled for PCO and or PC1 only if both lOs are configured in I2C3 Alternate Function mode For example if you use PCO for clock and PB4 for data PCO filter can be enabled only if PC1 is configured in 12C3 Alternate Function mode too I2C3 filter can be enabled for PG7 and or PG8 only if both lOs are configured in I2C3 Alternate Function mode For example if you use PG7 for clock and PC1 for data PG7 filter can be enabled only if PG8 is configured in I2C3 Alternate Function mode too DoclD026121 Rev 3 25 38 STM32L4x6xx silicon limitations STM32L4x6xx 2 7 2 7 1 2 7 2 2 7 3 2 7 4 26 38 Workaround Use both PCO PC1 as I2C3 alternate functions or use both PG7 PG8 as I2C3 alternate functions if the analog filter is needed SDMWNC peripheral limitations Wrong CCRCFAIL status after a response without CRC is received Description
16. 2 3 2 3 1 20 38 Read burst access of 9 words or more is not supported by FMC Description CPU read burst access equal to or more than 9 registers to FMC returns corrupted data starting from the 9t read word These bursts can only be generated by Cortex M4 CPU and not by the other masters i e not by DMA This issue occurs when the stack is remapped on the external memory on the FMC and POP operations are performed with 9 or more registers This also occurs when LDM VLDM operations are used with 9 or more registers Workaround Stack must be located in the internal SRAM IAR EWARM EWARM compiler does not generate LDM VLDM operations with more than 8 registers except when the setjmp or longjmp functions of C Library are explicitly used in the source code Keil MDK ARM Starting from version 5 06 ARM Compiler implements a patch which limits the number of registers with LDM VLDM operations Starting from version 5 16 MDK ARM includes ARM compiler with this patch addressing the hardware limitations of the STM32L4 FMC burst reads Tasking TASKING compiler starting from version v5 2r1 does not generate LDM instructions with more than 8 registers except when the setjmp or longjmp functions of C Library are explicitly used in the source code It generates POP instructions with 9 registers In assembly written code LDM VLDM operations must be limited to 8 registers QUADSPI peripheral limitations QUADSPI_BK1_101
17. 34 38 Calibration procedure does not work in PGA mode Description During the offset calibration procedure when the PGA mode is selected by setting OPAMODE 10 CALOUT signal is not reliable resulting trim bit found in procedure is wrong Workaround Use the PGA disable or internal follower mode OPAMODE 00 01 or 11 during the calibration procedure COMP peripheral limitations Comparators propagation delay is longer than expected for input steps higher than 200 mV Description Table 5 summarizes the comparators propagation delay values The propagation delay for steps higher than 200 mV is out of targeted specification Table 5 COMP characteristics Symbol Parameter Conditions Min Typ Max Unit V 227V 55 80 High speed mode DUA ns Vpopa lt 2 7V 65 100 Propagation delay Vooi 27y 0 55 0 9 for 200 mV step with Medium mode 100 mV overdrive Vpopoa lt 27 V 0 65 1 0 m tp Vopa22 7V 5 12 Ultralow power mode _ _ _ _ VDDA lt 2 7V 5 12 Propagation delay High speed mode 0 1 1 0 for step gt 200 mV with 100 mV overdrive on Medium mode 2 HS positive inputs Ultralow power mode 8 24 1 Data guaranteed by design not tested in production unless otherwise specified Workaround None Comparators output cannot be configured in open drain Description Comparators output are always forced in push pull mode whatever the
18. 7 2 Clock division per 255 is not possible 2 200005 26 2 7 3 Wait for response bits 10 configuration does not work correctly 26 2 7 4 MMC stream write of less than 8 bytes does not work correctly 26 bxCAN peripheral limitations 0 0000 27 2 8 1 bxCAN time triggered mode not supported 27 OTG_FS peripheral limitations 02000 eee eee 27 2 9 1 Suspend mode robustness marginality after receiving corrupted packet from HOSt 2 0a4ad wieder ae neia ede ed ha ee dade dear 27 2 9 2 Bits OTG_FS_GLPMCFG 6 2 are not write protected in Device mode 28 2 9 3 L1 exit with simultaneous Device initiated and Host initiated Resume results in minimum Device wake up time of 3ms 28 DoclD026121 Rev 3 3 38 Contents STM32L4x6xx 2 10 LCD peripheral limitations 00 002 28 2 10 1 LCD segments 23 and 24 alternate function cannot be configured independently 22 62 068 0s knee ee bebe eee eee eee 28 2 11 SPllimitations 0 0000000 es 29 2 11 1 BSY bit may stay high at the end of a data transfer at slave mode 29 2 12 SWPMI peripheral limitations 0000000 eee 29 2 12 1 SUSPENDED mode entry delayed 0 0 0 ce eee eee 29 2 12 2 SUSPENDED mode never entered 0000020 eee 29 2 12 3 SRF flagnotset osastaan ea a dees 30 2 12 4 SWP SUSPENDED mode not supported when STM32L4 is in Stop 0 or Stop 1
19. GPIO output type configuration bit value DocID026121 Rev 3 ky STM32L4x6xx STM32L4x6xx silicon limitations 2 17 3 2 18 2 18 1 2 19 2 19 1 3 Workaround None COMP1 and COMP2 configuration lost with software reset Description The Comparators 1 and 2 control and status registers COMP1_CSR and COMP2_CSR should be protected from software changes when the LOCK bit is set Therefore these registers should be reset only by a system reset However it is possible to reset these registers by setting SYSCFGRST in the RCC_APB2RSTR Workaround None LPTIM peripheral limitations Low power timer 1 LPTIM1 outputs cannot be configured in open drain Description LPTIM1 outputs are always forced in push pull mode whatever the GPIO output type configuration bit value Workaround None LPUART peripheral limitations Low power UART1 LPUART 1 outputs cannot be configured in open drain Description LPUART1 outputs are always forced in push pull mode whatever the GPIO output type configuration bit value Workaround None DoclD026121 Rev 3 35 38 STM32L4x6xx silicon limitations STM32L4x6xx 2 20 2 20 1 2 20 2 36 38 AES peripheral limitations Burst read or write accesses are not supported by the AES Description The AES only supports non sequential read write accesses AES registers read and write accesses using Load Store multiple instruction LDM STM are not support
20. If a read access is done in the SRAM2 while a SRAM2 hardware erase operation is on going the read access is stalled as long as the erase operation is not completed and the read value is not 0x0 but the latest value previously read from SRAM2 Workaround None Extra consumption when Vppa is below 0 7 V Description If Vppa is tied to ground or is below 0 7 V an unexpected leakage from I O to ground is present on PA3 and PBO DoclD026121 Rev 3 3 STM32L4x6xx STM32L4x6xx silicon limitations 2 1 10 3 Workaround None System clock is stopped during few us when switching between Low power run and Run modes Description When switching from Low power run to Run mode or when switching from Run mode to Low power run mode the System clock SYSCLK is stopped as long as the regulator is not ready few us Workaround None PHO PH1 is controlled by the GPIOH registers when HSE is enabled Description The PHO and PH1 GPIO configuration is not bypassed when the HSE is enabled The oscillator can stop if the I Os are not configured in analog mode Workaround PHO and PH1 must be configured in analog mode reset value when HSE is enabled PWR_CR4 register write access may not be completed if a Low power mode is entered just after the write operation Description PWR_CR4 write access should insert 3 APB1 wait states but it does not Consequently if a low power mode is entered just after writing into this re
21. L low as long as the MCU remains in Stop mode suspending all I C bus activity during that time This may occur when the MCU enters Stop mode during the address phase of an C bus transaction in low period of SCL This failure may occur in slave mode of the 12C peripheral or in master mode of the I2C peripheral used in multi master C bus environment Its probability depends on the timing DoclD026121 Rev 3 ky STM32L4x6xx STM32L4x6xx silicon limitations 2 6 3 2 6 4 2 6 5 3 Workaround Disable the I2C peripheral PE 0 before entering Stop mode and re enable it in Run mode Wrong data sampling when data set up time tsy par is smaller than one I2CCLK period Description The 12C bus specification and user manual specify a minimum data set up time tsy pat at e 250 ns in Standard mode e 100 ns in Fast mode e 50 ns in Fast mode Plus The I2C SDA line is not correctly sampled when tsu par is smaller than one I2CCLK I2C clock period the previous SDA value is sampled instead of the current one This can result in a wrong slave address reception a wrong received data byte or a wrong received acknowledge bit Workaround Increase the I2CCLK frequency to get I2CCLK period smaller than the transmitter minimum data set up time Or if it is possible increase the transmitter minimum data set up time Spurious Bus Error detection in master mode Description In master mode a bus error can be detected by mistake so
22. O used for nRTS as an alternate function after setting the UE and RE bits DAC peripheral limitations PA4 and PA5 must be configured in analog mode when DAC1_OUT1 or DAC1_OUT2 respectively is connected to OPAMP input Description When the DAC outputs are connected only to on chip peripherals the DAC1_OUTx I Os PA4 or PAS should be available for any other functions In case the DAC1_OUT1 is used as OPAMP 1 input PA4 must be configured in analog mode to allow the connection As a consequence PA4 cannot be used for GPIO or alternate functions but can still be used as ADC input Workaround None PA4 and PAS can t be used in output mode when DAC1_OUT 1 or DAC1_OUT2 respectively is connected to on chip peripherals Description When the DAC outputs are connected only to on chip peripherals the DAC1_OUTx I Os PA4 or PAS should be available for any other functions In case the DAC1_OUT1 is configured for on chip peripherals connection only PA4 output buffer remains disable As a consequence PA4 cannot be used in output mode GPIO or alternate function but can still be used in input or analog mode In case the DAC1_OUT2 is configured for on chip peripherals connection only PA5 output buffer remains disable As a consequence PA5 cannot be usedi n output mode GPIO or alternate function but can still be used in input or analog mode Workaround None DAC cannot be used at low Vppa if APB1 frequency is higher than 40 MHz
23. SUSPENDED mode entry delayed Description When activating the SWPMI by setting the SWPEN bit in SWPMI_CR register the SWPMI will rise the SWPMI_IO to 1 8V send a short transition sequence and 14 idle bits before switching to SUSPENDED mode As a consequence the SRF flag is set and the SUSP flag is cleared in SWPMI_ISR register Workaround None SUSPENDED mode never entered Description When activating the SWPMI by setting the SWPEN bit in SWPMI_CR register the SWPMI will generate the following sequence in loop rise the SWPIO send a short transition sequence and 14 idle bits As a consequence SWP stays in ACTIVATED state and never switch to SUSPENDED state DoclD026121 Rev 3 29 38 STM32L4x6xx silicon limitations STM32L4x6xx 2 12 3 2 12 4 2 12 5 2 13 2 13 1 30 38 Workaround Keep SWPMI1SEL bit cleared in RCC_CCIPR register to select PCLK1 as SWPMI clock source and configure the PCLK1 prescaler to feed the SWPMI with a clock frequency below or equal to 8 MHz SRF flag not set Description If the SWPMI1SEL bit is set in RCC_CCIPR register to select HSI as SWPMI clock source when receiving a resume by slave the SRF flag may not be set Nevertheless the SWPMI is switching correctly from SUSPENDED to ACTIVATED when receiving a RESUME by slave Therefore frame reception is not impacted Workaround None SWP SUSPENDED mode not supported when STM32L4 is in Stop 0 or Stop 1 mode Description
24. Section 2 2 3 FMC bank switching to asynchronous bank for write Section 2 2 4 Read burst access of 9 words or more is not supported by FMC P ky DoclD026121 Rev 3 9 38 STM32L4x6xx silicon limitations STM32L4x6xx Table 4 Summary of silicon limitation continued Section Limitation Rev 3 Rev 4 Section 2 3 1 QUADSPI_BK1_IO1 is always an input when the command is p P Section 2 3 sent in dual or quad SPI mode QUADSPI 7 A eripheral Section 2 3 2 Hard fault is not generated in case of out of range memory N N ee mapped access imitations Section 2 3 3 Extra data written in the FIFO at the end of a read transfer Section 2 4 1 Injected queue of context is not available in case of JQM 0 N Section 2 4 2 ADC triggers from EXTI require external interrupt management Section 2 4 ADC Section 2 4 3 DMA2 channels 2 and 3 respectively cannot be used when P P peripheral the ADC2 and ADC3 requests are selected on DMA2 channels 4 and 5 limitati OEE Section 2 4 4 Wrong ADC conversion results when delay between calibration N N and first conversion or between 2 consecutive conversions is too long Section 2 4 5 Burst read or write accesses are not supported by the ADC Section 2 5 1 RDATACH 2 0 status bits are not implemented N N Section 2 5 2 New regular channel selection taken into account at the end of N N samen 2 5 an injected conversion when a regular conversion is
25. TM32L4x6xx STM32L4x6xx silicon limitations 2 1 2 1 1 3 System limitations Write operation in the Flash memory while it is not ready Flash memory in power down is not correctly handled Description If the Flash memory is read while it is not ready after a power down state i e after Stop mode or when it was put in power down by means of SLEEP_PD or RUN_PD bits in the FLASH_ACR register the AHB bus is normally stalled until the Flash memory is ready and can provide the correct data However this mechanism is not supported in case of a write operation in normal programming mode the Flash memory read which is automatically performed before the programming in order to check that the address is virgin is incorrect Consequently the write operation is skipped Workaround The user must wait until the Flash memory is ready before performing a write operation this is done by reading first an address of the Flash memory not present in the cache The configuration of the I Os not available in WLCSP package can be modified by software Description Unbonded I Os in WLCSP package can be configured by software This can lead to an extra consumption if they are floating with Schmitt trigger ON Workaround Configure all unbonded I Os as analog input or as output push pull O state Some I Os must not be used as output when Vppa gt Vpp 0 6 V or VppusB gt VDD 0 6 Vor Vicp gt VDD 0 6 V Description When VDDA gt VDp
26. ay between two consecutive ADC conversions is higher than 1 ms the result of the second conversion might be incorrect The same issue occurs when the delay between the calibration and the first conversion is higher than 1 ms Workaround When the delay between two ADC conversions is higher than the above limit perform two ADC consecutive conversions in single scan or continuous mode the first is a dummy conversion of any ADC channel This conversion should not be taken into account by the application 3 DoclD026121 Rev 3 STM32L4x6xx STM32L4x6xx silicon limitations 2 4 5 2 5 2 5 1 2 5 2 2 5 3 3 Burst read or write accesses are not supported by the ADC Description The ADC does not support LDM STM LDRD and STRD instructions for successive multiple data read and write accesses to a contiguous address block Workaround Prevent compilers from generating LDM STM LDRD and STRD instructions In general this can be achieved organizing the source code to avoid consecutive read or write accesses to neighboring addresses in lower to higher order In cases where consecutive read or write accesses to neighboring addresses cannot be avoided order the source code so that it accesses higher address first DFSDM peripheral limitations RDATACH 2 0 status bits are not implemented Description RDATACH 2 0 Regular channel most recently converted status bits are not implemented in the DFSDM data register for
27. d loads to stack pointer can cause erroneous behavior 0 00 eee eee 8 2 STM32L4x6xx silicon limitations 0 0c cece eee eee 9 2 1 System limitations sic sbkes Robbed et Bee eed ne Mane Teena Reseed 13 2 1 1 Write operation in the Flash memory while it is not ready Flash memory in power down is not correctly handled 13 2 1 2 The configuration of the I Os not available in WLCSP package can be modified by software 0 0 cee eee 13 2 1 3 Some I Os must not be used as output when VDDA gt VDD 0 6 V or VDDUSB gt VDD 0 6 V or VLCD gt VDD 0 6 V 13 2 1 4 Bootloader SPI and CAN interfaces are not supported 14 2 1 5 SRAM2 read access while the SRAM2 hardware erase is ongoing is not correctly supported 000000 eee 14 2 1 6 Extra consumption when VDDA is below 0 7 V 14 2 1 7 System clock is stopped during few us when switching between Low power run and Run modes 2020000 cece eeee 15 2 1 8 PHO PH1 is controlled by the GPIOH registers when HSE is enabled 15 2 1 9 PWR_CR4 register write access may not be completed if a Low power mode is entered just after the write operation 15 2 1 10 HSI user trim is limited on some samples 22 55 15 2 1 11 Option byte loading can fail if MSI frequency is greater than 8 MHz 16 2 1 12 MSI at high frequency ranges cannot be used as wakeup from Stop 0 CIOCK SOUCO a tik
28. de when Section 2 15 DAC DAC1_OUT1 or DAC1_OUT2 respectively is connected to on chip N peripheral peripherals limitations Section 2 15 3 DAC cannot be used at low VDDA if APB1 frequency is higher p R than 40 MHz Section 2 15 4 DAC characteristics can be degraded depending on the N 7 current sunk on DAC output Section 2 16 Section 2 16 1 OPAMP characteristics can be degraded depending on the N OPAMP current sunk on OPAMP output limitations Section 2 16 2 Calibration procedure does not work in PGA mode A A Section 2 17 1 Comparators propagation delay is longer than expected for N N Section 2 17 input steps higher than 200 mV sa narai Section 2 17 2 Comparators output cannot be configured in open drain Section 2 17 3 COMP1 and COMP2 configuration lost with software reset Kys DoclD026121 Rev 3 11 38 STM32L4x6xx silicon limitations STM32L4x6xx Table 4 Summary of silicon limitation continued Section Limitation Rev 3 Rev 4 Section 2 18 s LPTIM peripheral Section 2 18 1 Low power timer 1 LPTIM1 outputs cannot be configured in N N limitations Section 2 19 LPUART Section 2 19 1 Low power UART1 LPUART1 outputs cannot be configured N N peripheral limitations Section 2 20 AES Section 2 20 1 Burst read or write accesses are not supported by the AES A A peripheral limitations Section 2 20 2 AES does not support Load multiple A A 12 38 DocID026121 Rev 3 3 S
29. e 11 or EXTI line 15 it is required to configure and enable the line as an interrupt source in the EXTI and NVIC peripherals Workaround Configure the EXTI line as an interrupt source in the EXTI and enable the interrupt line in the NVIC The EXTI interrupt flag must be cleared in the interrupt subroutine in order to allow new trigger event detection DMA2 channels 2 and 3 respectively cannot be used when the ADC2 and ADC3 requests are selected on DMA2 channels 4 and 5 Description When the DMA2 channel 4 is used for the ADC2 requests C4S 0000 in the DMA2_CSELR register it is also needed to select request 0 for DMA2 channel 2 C2S 0000 in the DMA2_CSELR register The consequence is that the DMA2 channel 2 cannot be used by another peripheral When the DMA2 channel 5 is used for the ADC3 requests C5S 0000 in the DMA2_CSELR register it is also needed to select request 0 for DMA2 channel 3 C3S 0000 in the DMA2_CSELR register The consequence is that the DMA2 channel 3 cannot be used by another peripheral Workaround Select the DMA1 channel 2 for the ADC2 DMA requests or use other available mapping for the peripherals mapped on DMA2 channel 2 Select the DMA1 channel 3 for the ADC3 DMA requests or use other available mapping for the peripherals mapped on DMA2 channel 3 Wrong ADC conversion results when delay between calibration and first conversion or between 2 consecutive conversions is too long Description When the del
30. ed LDRD STRD are not supported neither Workaround If LDM STM LDRD and STRD instructions are generated by the compiler to access AES registers by reordering the software code by accessing higher memory address register to lower memory address register compiler will not create multiple data instructions AES does not support Load multiple Description The AES does not support LDM STM LDRD and STRD instructions for successive multiple data read and write accesses to a contiguous address block Workaround The workaround consists in preventing compilers from generating LDM STM LDRD and STRD instructions In general this can be achieved organizing the source code in a way that avoids consecutive read or write accesses to neighboring addresses in lower to higher order In cases where consecutive read or write accesses to neighboring addresses cannot be avoided the source code must be ordered to access higher address first 3 DocID026121 Rev 3 STM32L4x6xx Revision history 3 3 Revision history Table 6 Document revision history Date 29 May 2015 Revision 1 Changes Initial release 25 Sep 2015 03 Dec 2015 Updated Table 2 Device summary and Table 4 Summary of silicon limitation Updated Section 2 1 2 The configuration of the I Os not available in WLCSP package can be modified by software Section 2 2 4 Read burst access of 9 words or more is not supported by FMC
31. ed by MSI when requesting entry in low power mode b the wakeup clock is MSI If the system clock is any other clock than MSI lower the MSI frequency to 16 MHz or less and add a short delay loop 200 ns minimum before stopping MSI by software This will ensure that the MSIRDY flag be really 0 before requesting entry in low power mode If the system clock is MSI and the wakeup clock is not MSI lower the MSI frequency to 16 MHz or less and add a short delay loop 200 ns minimum before requesting entry in low power mode If the system clock is PLL fed by MSI and the wakeup clock is not MSI the MSI frequency used as PLL input should not exceed 16 MHz In other words do not use the PLL fed by MSI as system clock with MSI at high frequency 24 MHz or above divided by PLLM ensuring the PLL input is between 4 and 16 MHz 3 DocID026121 Rev 3 STM32L4x6xx STM32L4x6xx silicon limitations 2 2 2 2 1 2 2 2 2 2 3 3 FMC peripheral limitations Dummy read cycles inserted when reading synchronous memories Description When performing a burst read access to a synchronous memory two dummy read accesses are performed at the end of the burst cycle whatever the type of AHB burst access However the extra data values which are read are not used by the FMC and there is no functional failure Workaround None Data corruption during burst read from FMC synchronous memory Description A burst read from static m
32. emory can be corrupted if all the following conditions are met e One FMC bank is configured in synchronous mode with WAITEN bit enabled while another FMC bank is used with WAITEN bit disabled e A read burst transaction is ongoing from static synchronous memory with wait feature enabled e The synchronous memory asserts the wait signal during the ongoing burst read e The read burst transaction is followed by an access to an FMC banks for which the WAITEN bit is disabled in the FMC_BCRx register Workaround 1 Set the WAITEN bit on all FMC static banks even if it is not used by the memory 2 Set the same WAIT polarity on all static banks 3 Enable the internal pull up on PD6 in order to set to ready the FMC_NWAIT input when the synchronous memory is de selected and the other FMC bank without wait feature is selected FMC bank switching to asynchronous bank for write Description When switching from one of the FMC banks in read transaction to another asynchronous bank for write the FMC could hang in one of the following conditions e one FMC bank is enabled with BUSTURN timing gt 0 e asecond FMC bank is enabled in asynchronous multiplexed or not multiplexed mode with BUSTURN 0 e aread from the first bank followed by a write transaction on the second bank Workaround Use BUSTURN 0 or different from 0 for used banks DoclD026121 Rev 3 19 38 STM32L4x6xx silicon limitations STM32L4x6xx 2 2 4
33. figure and enable the line as an interrupt source in the EXTI and NVIC peripherals Workaround Configure the EXTI line as an interrupt source in the EXTI and enable the interrupt line in the NVIC The EXTI interrupt flag must be cleared in the interrupt subroutine in order to allow new trigger event detection I2C peripheral limitations I2C Fast mode Plus drive is not available on all SDA SCL I Os Description Only PB6 7 8 9 13 14 PC0 1 and PG7 8 a can effectively be configured in 12C Fm driving mode Setting 12C1_FMP I12C2_ FMP and I2C3_FMP in the SYSCFG_CFGR1 register has no effect on PB10 PB11 PFO PF1 PG13 PG14 When using the I O without 20 mA Fm drive it is still possible to reach 1 MHz Fm speed with limited bus load Workaround None Wrong behavior related with MCU Stop mode when wakeup from Stop mode by I2C peripheral is disabled Description When wakeup from Stop mode by 2C peripheral is disabled WUPEN 0 and the MCU enters Stop mode while a transaction is on going on the I C bus the following wrong operations may occur 1 BUSY flag may be wrongly set when the MCU exits Stop mode This prevents from initiating a transfer in master mode as the START condition cannot be sent when BUSY is set This failure may occur in master mode of the I2C peripheral used in multi master C bus environment 2 If I C bus clock stretching is enabled in I2C peripheral NOSTRETCH 0 the 12C peripheral may pull SC
34. gister the PWR_CR4 register may not be updated before the low power mode is entered This can occur in particular when the APB1 clock is prescaled Workaround PWR_CR4 register must be read after the write operation to ensure that the write is done before entering the low power mode HSI user trim is limited on some samples Description The HSI user trimming step is typically e 0 3 of frequency when the trimming code is not a multiple of 64 e 7 of frequency when the trimming code is a multiple of 64 As shown in Figure 7 the HSI user trimming allows to add or to subtract up to 16 steps compared to the factory trim value DoclD026121 Rev 3 15 38 STM32L4x6xx silicon limitations STM32L4x6xx If the HSI factory trim value is close to a multiple of 64 with only 16 steps for positive or for negative correction it is not possible to compensate the 7 drop when the code is a multiple of 64 Consequently the user trim correction must not jump over the codes multiple of 64 which can limit the user correction either in positive or in negative direction Figure 1 HSI oscillator trimming characteristics HSI16 frequency Calibration range 16 MHz Obxx111117 5 So z x a 2 O Calibration values HSICAL 16 HSICAL 31 MS37339V2 Workaround None 2 1 11 Option byte loading can fail if MSI frequency is greater than 8 MHz Description The option byte loading
35. mand is received DoclD026121 Rev 3 ky STM32L4x6xx STM32L4x6xx silicon limitations 2 8 2 8 1 2 9 2 9 1 3 The WAITPEND bit 9 of SDMMC_CMD register is set to synchronize the sending of the STOP_TRANSMISSION CMD12 command with the data flow When WAITPEND is set the transmission of this command stays pending until 50 data bits including STOP bit remain to transmit For a stream write of less than 8 bytes the STOP_TRANSMISSION CMD12 command should be started before the data transfer starts Instead of this the data write and the command sending are started simultaneously It implies that when less than 8 bytes have to be transmitted 8 DATALENGTH bytes are programmed to OxFF in the card after the last byte programmed where DATALENGTH is the number of data bytes to be trasferred Workaround Do not use stream write WRITE_DAT_UNTIL_STOP CMD20 with a DATALENGTH less then 8 bytes Use set block length SET_BLOCKLEN CMD16 followed by single block write command WRITE_BLOCK CMD24 instead of stream write CMD20 with desired block length bxCAN peripheral limitations bxCAN time triggered mode not supported Description The time triggered communication mode described in the reference manual is not supported and so time stamp values are not available TTCM bit must be kept cleared in the CAN_MCR register time triggered communication mode disabled Workaround None OTG_FS peripheral limitati
36. n history 0 2 0 0 00 cece tees 37 DoclD026121 Rev 3 3 STM32L4x6xx List of figures List of figures Figure 1 HSI oscillator trimming characteristics 0 0 c ee eae 16 Figure 2 Parasitic resistor on DAC output 00 000000000 eee 33 Figure 3 Parasitic resistor on OPAMP output 2 0 0 00000 02 2 cee eee eee 33 3 DocID026121 Rev 3 7 38 ARM 32 bit Cortex M4 FPU core limitations STM32L4x6xx 1 1 8 38 ARM 32 bit Cortex M4 FPU core limitations An errata notice of the STM32L4x6xx core is available from the following web address http infocenter arm com All the described limitations are minor and related to the revision r0p1 v1 of the Cortex M4 FPU core Table 3 summarizes these limitations and their implications on the behavior of STM32L4x6xx devices Table 3 Cortex M4 FPU core limitations and impact on microcontroller behavior ARM ID ARM category ARM summary of errata Impact 752419 Cat 2 Interrupted loads to SP can cause erroneous behavior Minor Cortex M4 FPU core interrupted loads to stack pointer can cause erroneous behavior Description An interrupt occurring during the data phase of a single word load to the stack pointer SP R13 can cause an erroneous behavior of the device In addition returning from the interrupt results in the load instruction being executed with an additional time For all the instructions performi
37. ng an update of the base register the base register is erroneously updated on each execution resulting in the stack pointer being loaded from an incorrect memory location The instructions affected by this limitation are the following e LDR SP Rn imm e LDR SP Rn imm e LDR SP Rn imm e LDR SP Rn e LDR SP Rn Rm Workaround As of today no compiler generates these particular instructions This limitation can only occur with hand written assembly code Both issues can be solved by replacing the direct load to the stack pointer by an intermediate load to a general purpose register followed by a move to the stack pointer Example Replace LDR SP RO by LDR R2 RO MOV SP R2 3 DocID026121 Rev 3 STM32L4x6xx STM32L4x6xx silicon limitations 2 STM32L4x6xx silicon limitations Table 4 gives quick references to all documented limitations Legend for Table 4 A workaround available N no workaround available P partial workaround available and grayed fixed Table 4 Summary of silicon limitation Section Limitation Rev 3 Rev 4 Section 2 1 1 Write operation in the Flash memory while it is not ready Flash A A memory in power down is not correctly handled Section 2 1 2 The configuration of the I Os not available in WLCSP package A A can be modified by software Section 2 1 3 Some I Os must not be used as
38. o output LCD_SEG23 PC6 is also configured as alternate function LCD and output LCD_SEG24 As a consequence when PC5 is used for LCD PC6 cannot be used for another purpose than LCD In addition in order to use PC6 as LCD alternate function it is required to configure PC5 as LCD alternate function DoclD026121 Rev 3 ky STM32L4x6xx STM32L4x6xx silicon limitations 2 11 2 11 1 2 12 2 12 1 2 12 2 3 Workaround When the LCD is used use both PC5 and PC6 as LCD segments or use none of them SPI limitations BSY bit may stay high at the end of a data transfer at slave mode Description In slave mode BSY bit is not reliable to handle the end of data frame transaction due to some bad synchronization between the CPU clock and external SCK clock provided by master Sporadically the BSY bit is not cleared at the end of a data frame transfer As a consequence it is not recommended to rely on BSY bit before entering low power mode or modifying the SPI configuration Workaround To ensure BSY bit flag is always reset at the end of a frame communication disable the SPI by software before the communication is finished by following sequence e write last data to data register to transmit the data e poll TXE till it becomes high to ensure the data transfer has started e disable SPI by clearing SPE while the last data transfer is still on going e poll the BSY bit till it becomes low SWPMI peripheral limitations
39. ons Suspend mode robustness marginality after receiving corrupted packet from Host Description Once the early suspend interrupt is set after 3 ms of USB idleness the corrupted packet with missing EOP unexpectedly sent by the Host stops the suspend timer and when the bus becomes idle again suspend early suspend interrupts are no more generated No error flag is set and it is not possible to issue remote wake up to the Host Device restarts operate normally only upon reception of next EOP from Host Workaround If such scenario is believed possible implement a timeout check started once early suspend interrupt is detected If within next 4 ms there is no suspend resume early suspend or SOF DoclD026121 Rev 3 27 38 STM32L4x6xx silicon limitations STM32L4x6xx 2 9 2 2 9 3 2 10 2 10 1 28 38 detected it means that the suspend timer is blocked and need to be recovered by reinitializing the USB peripheral by a soft reset CSRST bit in OTG_FS_GRSTCTL After that when the USB system is eventually woken up from the Suspend mode either by Host or by Device generated remote wake up it is necessary to generate a soft disconnect amp re connect as the enumeration status is lost by the soft reset Bits OTG_FS_GLPMCFG 6 2 are not write protected in Device mode Description Bits OTG_FS _GLPMCFG 6 2 are not write protected in Device mode as expected but could be modified by application software In Device mode the co
40. operation can fail if the MSI clock is ON with a frequency equal or greater than 8 MHz before performing an option byte loading by setting OBL_LAUNCH bit in the FLASH _CR register Some options and engineering bytes values can be corrupted Workaround If MSI is ON at a frequency equal or higher than 8MHZ It is mandatory to reduce MSI frequency to 4 MHz or less before launching the Option Byte loading operation by setting the OBL_LAUNCH bit in the FLASH_CR register 3 16 38 DoclD026121 Rev 3 STM32L4x6xx STM32L4x6xx silicon limitations 2 1 12 2 1 13 2 1 14 2 1 15 3 MSI at high frequency ranges cannot be used as wakeup from Stop 0 clock source Description When Vpp gt 3 V the MSI startup frequency overshoot is higher than expected and can be higher than the maximum allowed product frequency Therefore it is not possible to select the MSI at 48 or at 32 MHz as wakeup clock source when exiting Stop 0 in Range 1 because the frequency reached during the overshoot is too high compared to the flash wait states configuration For the same reason it is not possible to select the MSI at 24 16 or 8 MHz as wakeup clock source when exiting Stop 0 in Range 2 The MSI in all ranges can be used to exit Stop 1 or Stop 2 modes because the main regulator wakeup delay is used to avoid the clock propagation and the regulator wakeup time is greater than the MSI overshoot duration Workaround Wait for 6 us after exiting Stop 0 before
41. pending peripheral Section 2 5 3 DFSDM triggers from timers can be missed in specific A A limitations conditions Section 2 5 4 DFSDM triggers from EXTI require external interrupt P 7 management Section 2 6 1 12C Fast mode Plus drive is not available on all SDA SCL I Os N N Section 2 6 2 Wrong behavior related with MCU Stop mode when wakeup A A from Stop mode by I2C peripheral is disabled Section 202C Section 2 6 3 Wrong data sampling when data set up time tSU DAT is peripheral i P P eae smaller than one I2CCLK period limitations Section 2 6 4 Spurious Bus Error detection in master mode A A Section 2 6 5 12C3 analog filters requires that both PCO PC1 or both A A PG7 PG8 are configured as I12C3 alternate function Section 2 7 1 Wrong CCRCFAIL status after a response without CRC is A A received Section 2 7 SDMMC Section 2 7 2 Clock division per 255 is not possible N N peripheral Section 2 7 3 Wait for response bits 10 configuration does not work limitations correctly A A Section 2 7 4 MMC stream write of less than 8 bytes does not work correctly A A Section 2 8 bxCAN peripheral Section 2 8 1 bxCAN time triggered mode not supported N N limitations 10 38 DoclD026121 Rev 3 ky STM32L4x6xx STM32L4x6xx silicon limitations Table 4 Summary of silicon limitation continued Section Limitation Rev 3 Rev 4 Section 2 9 1 Suspend mode robustne
42. re updates the fields with the values received in the LPM Token When some read modify write access is performed to OTG_FS_GLPMCFG register during the time of LPM token exchange the application software could over write the values written by OTG_FS core with the old value Workaround Program the LPMACK bit in OTG_FS_GLPMCFG register to NYET response before updating OTG_FS_GLPMCFG register while USB transfers are in progress Set the LPMACK bit back to ACK response when updating is finished L1 exit with simultaneous Device initiated and Host initiated Resume results in minimum Device wake up time of 3 ms Description When the device application initiates the remote wakeup by setting the RWUSIG bit in OTG_FS_DCTL register while the host is initiating resume at the same time further LPM tokens sent by the Host within next 3 ms are ignored the device does not enter L1 on any LPM token acknowledgment If the host has sent an LPM token during these 3 ms and is acknowledged by the device core then host enters L1 whereas device does not enter L1 Instead the device enters normal Suspend mode due to 3 ms of bus inactivity Workaround Program the LPMACK bit in OTG_FS_GLPMCFG register to NYET response before initiating remote wakeup and set it back to ACK only after 3 ms LCD peripheral limitations LCD segments 23 and 24 alternate function cannot be configured independently Description When PC5 is configured as alternate function LCD t
43. ss marginality after receiving A A Section 2 9 corrupted packet from Host OTG_FS Section 2 9 2 Bits OTG_FS_GLPMCFG 6 2 are not write protected in P P peripheral Device mode iniia Section 2 9 3 L1 exit with simultaneous Device initiated and Host initiated P P Resume results in minimum Device wake up time of 3 ms poiri ag EHn Section 2 10 1 LCD segments 23 and 24 alternate function cannot be P P ee ions configured independently Section 2 11 SPI Section 2 11 1 BSY bit may stay high at the end of a data transfer at slave A A limitations mode Section 2 12 1 SUSPENDED mode entry delayed N Section 2 12 2 SUSPENDED mode never entered esa ee heral Section 2 12 3 SRF flag not set N limitations Section 2 12 4 SWP SUSPENDED mode not supported when STM32L4 is in N N Stop 0 or Stop 1 mode Section 2 12 5 SWPMI_IO transceiver bypass mode is not functional N N Section 2 13 RTC peripheral Section 2 13 1 Spurious tamper detection when disabling the tamper channel P P limitations Section 2 14 1 Start bit detected too soon when sampling for NACK signal N N from the smartcard Section 2 14 5 ay ede Section 2 14 2 Break request can prevent the Transmission Complete flag USART limitations TC from being set A A Section 2 14 3 nRTS is active while RE or UE 0 A A Section 2 15 1 PA4 and PA5 must be configured in analog mode when N 5 DAC1_OUT1 or DAC1_OUT2 respectively is connected to OPAMP input Section 2 15 2 PA4 and PA5 can t be used in output mo
44. t a NACK error signal at 10 5 0 2 etu after the character START bit falling edge In this case the USART transmitter should be able to detect correctly the NACK signal by sampling at 11 0 0 2 etu after the character START bit falling edge The USART peripheral used in Smartcard mode doesn t respect the 11 0 2 etu timing and when the NACK falling edge arrives at 10 68 etu or later the USART might misinterpret this transition as a START bit even if the NACK is correctly detected Workaround None Break request can prevent the Transmission Complete flag TC from being set Description After the end of transmission of a data D1 the Transmission Complete TC flag will not be set in the following conditions CTS hardware flow control is enabled D1 is being transmitted e abreak transfer is requested before the end of D1 transfer e nCTS is de asserted before the end of transfer of D1 Workaround If the application needs to detect the end of transfer of the data the break request should be done after making sure that the TC flag is set nRTS is active while RE or UE 0 Description The nRTS line is driven low as soon as the RTSE bit is set and even if the USART is disabled UE 0 or if the receiver is disabled RE 0 i e not ready to receive data DoclD026121 Rev 3 31 38 STM32L4x6xx silicon limitations STM32L4x6xx 2 15 2 15 1 2 15 2 2 15 3 32 38 Workaround Configure the I
45. the regular channel DFSDMx_RDATAR Workaround None These bits will be implemented in next silicon release New regular channel selection taken into account at the end of an injected conversion when a regular conversion is pending Description When a regular channel conversion is on going and is interrupted by an injected channel conversion if the regular channel is changed on the fly during the injected channel conversion the new regular channel selection is taken into account at the end of the injected conversion Workaround None do not change the regular channel selection on the fly when regular continuous conversions are requested DFSDM triggers from timers can be missed in specific conditions Description Triggers from timers to DFSDM can be missed when all the conditions listed below occur e the DFSDM clock is the APB2 clock PCLK2 DFSDMSEL 0 in the RCC_CCIPR register e the DFSDM is triggered by TIM3_TRGO TIM4_TRGO TIM6_TRGO or TIM7_TRGO e the APB2 frequency is smaller than the APB1 frequency DoclD026121 Rev 3 23 38 STM32L4x6xx silicon limitations STM32L4x6xx 2 5 4 2 6 2 6 1 Note 2 6 2 24 38 Workaround Select the System clock as DFSDM clock DFSDMSEL 1 in the RCC_CCIPR register DFSDM triggers from EXTI require external interrupt management Description When the DFSDM external trigger for regular or injected channel selects the EXTI line 11 or EXTI line 15 it is required to con
46. tions and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved 3 38 38 DoclD026121 Rev 3
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