OS21 for ST40 - STMicroelectronics
Contents
1. Table 5 Document revision history continued Date Revision Changes Throughout Added Context section to each of the functions Interrupts chapter Changed description of interrupts mask in the Masking interrupts section Caches and memory areas chapter Added cache status flags tto Aug 02 F Table 6 Corrected typing errors in Table 7 Inthecache enable data and cache enable instruction functions changed the names of the assigned bits to upper case Updated cache status function Board support package chapter Added footnote for ST40GX1 Evaluation board In the BSP code section added bsp_terminate and changed the description of bsp_shutdown Interrupts chapter Added a new function interrupt_mask_all and added cross references to it Updated the functions interrupt_mask and interrupt_unmask Removed references to 7750 Aug 02 E Exceptions chapter Changed description of default behavior in last paragraph of overview Board support package chapter Updated the location of the BSPs for ST40 platforms Throughout Added bsp to the start of timeslice_frequency_hz and May 02 D peripheral_bus_clock_frequency_hz Board support package chapter Changed board names to product names Interrupts chapter Changed description of ST40 GRP 7750 SCI 1 and ST40_GRP_7750_SCIF in the ST40 interrupt source names table May 02 C Caches and memory areas chapter Added note to caches and memory overview Floating point sup2. 4 1 TIMES HII IAA A a AE 5 1 1 Timers overview 5 1 2 Input clock frequency 5 1 3 OST tick dilrafiDET ute AA dedico NE Red ah awa 5 14 ST40timerassignments 5 2 Floating point support iss das ses EE Ma RAS EE EE EEN Rd RR NE Ne na ewe 7 2 1 Floating point overview 7 3 Register context mnn 8 3 1 Registers overview EES ER EERS ed EE SEK ER EE RE EERDER EER RR Ee 8 4 ROSES ME ER EE un 9 4 1 Resets overview 9 4 2 Reset APT summary ease 9 4 3 LIStOPTUNCHONS AAA IIIA pe DEA DERE DERE WE DE a dede 10 5 Constructors and destructors 11 5 1 Multiple constructors and destructors 11 6 Board support package 12 6 1 Board support package overview 12 6 2 BSP interrupt system description 12 6 2 1 Interrupt names 12 6 2 2 Interrupt groups IA nere bee oda ed eee ru RE new 13 2 23 7358673 ky OS21 ST40 Contents 6 2 3 Interrupttables 13 6 2 4 INTC base address
3. 18 6 2 5 INTC2 base address 18 6 2 6 ILC base address AA IA eee 18 6 2 7 Interrupt system initializationflags 18 7 REVISION ISI Ya wi suras rra 20 ky 7358673 3 23 Preface OS21 ST40 Preface Document identification and control Each book carries a unigue identifier of the form ADCS nnnnnnnx where nnnnnnn is the document number and x is the revision Whenever making comments on a document the complete identification ADCS nnnnnnnx should be quoted Conventions used in this guide 4 23 General notation The notation in this document uses the following conventions sample code keyboard input and file names variables and code variables code comments screens windows and dialog boxes instructions Hardware notation The following conventions are used for hardware notation e REGISTER NAMES and FIELD NAMES e PIN NAMES and SIGNAL NAMES Software notation Syntax definitions are presented in a modified Backus Naur Form BNF Briefly 1 Terminal strings of the language that is strings not built up by rules of the language are printed in teletype font For example void 2 Nonterminal strings of the language that is strings built up by rules of the language are printed in italic teletype font For example name 3 lfanonterminal string of the language starts with a nonitalicized part it is equivalent to the same nonte
4. Board support package OS21 ST40 16 23 Since 0821 MY GROUP 3 belongs to the INTC2 this interrupt can be found in bit two of the appropriate INTC2 registers interrupt table entry t bsp interrupt table This describes the set of interrupts that arrive at the INTC It comprises a list of interrupt table entry t types For example interrupt table entry t bsp interrupt table mag A IA IA AA AA AA IAS IAS IA III AS eS eS M A A IA IA AA IA AA IA IAS IIO ee eS M AA IA IA A IA A IA IA Ie eS eS amp OS21 IN amp OS21 INI amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 INI amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN amp OS21 IN TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE TE
5. How to access the DMA interrupt in user code extern interrupt name t OS21 INTERRUPT DMA 0 7358673 ST OS21 ST40 Board support package The interrupt handle function takes an interrupt name t parameter and returns a handle to the given interrupt 6 2 2 Interrupt groups On the ST40 there is a concept of interrupt groups An interrupt group consists of one or more interrupts whose priority level is shared The priority of all interrupts within the group is the same and is controlled by the appropriate interrupt controller A type is provided by OS21 called interrupt group t Each interrupt group is assigned a unique name interrupt group t which allows it to be identified in the BSP interrupt tables The BSP need only contain those interrupt groups that are used by either OS21 or the application code If any interrupt groups are missing a linker error occurs If interrupt groups are declared in the BSP but are subsequently not used this does no harm other than use memory For example Interrupt group 23 on the INTC2 interrupt group t 0821 GRP INTC2 23 5322 6 2 3 Interrupt tables These tables are expected by the OS21 platform specific interrupt API implementation code and describe the interrupt system For the ST40 three tables are reguired One is for the interrupt table another is for the interrupt group table and the other is for an optional interrupt level controller The complete specification for the i
6. 8 ya ILC 13 amp OS21 GRP INTC2 22 OS21 CTRL INTC2 2 6 8 ILC 14 amp OS21 GRP INTC2 23 OS21 CTRL INTC2 2 7 2 ILC 15 E unsigned int bsp_interrupt_group_table_entries This specifies the number of entries in bsp group interrupt table ltis usually set as follows unsigned int bsp interrupt group table entries sizeof bsp interrupt group table sizeof interrupt group table entry t Interrupt table An entry in the interrupt table ed typedef struct interrupt table entry s interrupt name t namep interrupt group t groupp unsigned short intevt unsigned short bitpos interrupt table entry t This table describes all the interrupts in the system namep is a pointer to the name of the interrupt groupp is a pointer to the name of the interrupt group to which the interrupt belongs intevt is the code that is placed in the INTEVT register by the ST40 when the interrupt is asserted bitpos is only used when the interrupt belongs to the INTC2 In this case this gives the bit position of this interrupt within the INTC2 For example interrupt name t OS21 MY INTERRUPT 21 interrupt table entry t my interrupt amp OS21 MY INTERRUPT amp OS21 MY GROUP 3 0x1240 2 This describes an interrupt called 0821 MY INTERRUPT which belongs to the interrupt group OS21 MY GROUP 3 This generates an INTEVT code of 0x1240 when it is asserted 7358673 15 23
7. T ILC 13 amp OS21 GRP INTC2 21 0x1680 20 T ILC 14 amp OS21 GRP INTC2 22 0x1700 24 T ILC 15 amp OS21 GRP INTC2 23 0x1780 28 7358673 OO OO OO OO CO EE WA OS21 ST40 Board support package Note 7 unsigned int bsp interrupt table entries This specifies the number of entries in bsp interrupt table It is usually set as follows unsigned int bsp interrupt table entries sizeof bsp interrupt table sizeof interrupt table entry t ILC table ILC modes typedef enum OS21 ILC NO TRIGGER 0 OS21 ILC TRIGGER HIGH LEVEL OS21 ILC TRIGGER LOW LEVEL OS21 ILC TRIGGER RISING EDGE OS21 ILC TRIGGER FALLING EDGE OS21 ILC TRIGGER ANY EDGE OS21 ILC NO TRIGGER 1 OS21 ILC NO TRIGGER 2 OS21 ILC TRIGGER MAX ilc mode t An entry in the ILC table typedef struct ilc table entry s interrupt name t namep unsigned int input 16 unsigned int output 16 ilc_mode_t mode ilc table entry t This describes interrupts that are routed through an interrupt level controller namep is a pointer to the name of the interrupt input is the number of the input into the ILC that the interrupt arrives on output is the number of the output to which the interrupt is routed mode describes how the interrupt is triggered This table allows OS21 to locate the appropriate state in the INTC2 which maps t
8. TMU EE EE ass 5 ILC base address 18 EE EE 5 ILCtable 17 EE EET 5 initialization flags 18 TMUZ2 mm e nn 5 AWA 5 determining speed 5 WwW interrupt groups IA aa RENNER 13 interrupt level controller 13 17 MEER GO UINGE doe a ee vat diae dett 9 interruptnames 12 interrupt system 12 interrupt system initialization flags 18 interrupt tables 13 L linker error 12 M manual reset 9 O OS21 kernel building er P AWA 7 OS21 tick duration WWW 5 R register contekt 8 22 23 7358673 Rev O ky OS21 ST40 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No lic
9. OS21 GRP INTC2 0 0821 CTRL INTC2 0 0 10 PIO O amp OS21 GRP INTC2 1 0821 CTRL INTC2 0 1 5 TTXT DMAC amp OS21 GRP INTC2 2 OS21 CTRL INTC2 0 2 5 DMAC amp OS21 GRP INTC2 3 OS21 CTRL INTC2 0 3 10 ES PIO 1 amp OS21 GRP INTC2 4 OS21 CTRL INTC2 0 4 0 NOT CONNECTED amp 0S21_ GRP INTC2 5 OS21 CTRL INTC2 0 5 0 NOT CONNECTED amp O0S21 GRP INTC2 6 OS21 CTRL INTC2 0 6 0 NOT CONNECTED amp OS21 GRP INTC2 7 OS21 CTRL INTC2 0 7 0 NOT CONNECTED amp OS21 GRP INTC2 8 0S21 CTRL INTC2 1 0 13 ILC O amp OS21 GRP INTC2 9 OS21 CTRL INTC2 1 1 7 ILC 1 amp OS21 GRP INTC2 10 OS21 CTRL INTC2 1 2 13 ILC 2 amp OS21 GRP INTC2 11 OS21 CTRL INTC2 1 3 8 ILC 3 amp OS21 GRP INTC2 12 OS21 CTRL INTC2 1 4 14 ILC 4 amp OS21 GRP INTC2 13 OS21 CTRL INTC2 1 5 9 ILC 5 amp OS21 GRP INTC2 14 OS21 CTRL INTC2 1 6 6 ILC 6 amp OS21 GRP INTC2 15 OS21 CTRL INTC2 1 7 5 ILC 7 amp OS21 GRP INTC2 16 OS21 CTRL INTC2 2 0 9 ILC 8 amp OS21 GRP INTC2 17 OS21 CTRL INTC2 2 1 9 ILC 9 amp OS21 GRP INTC2 18 OS21 CTRL INTC2 2 2 4 ILC 10 amp OS21 GRP INTC2 19 OS21 CTRL INTC2 2 3 7 ILC 11 amp OS21 GRP INTC2 20 OS21 CTRL INTC2 2 4 8 ILC 12 amp OS21 GRP INTC2 21 OS21 CTRL INTC2 2 5
10. NONE 0 0 10 amp OS21 GRP IRL ENCODED 9 OS21 CTRL NONE 0 0 9 amp OS21 GRP IRL ENCODED 8 OS21 CTRL NONE 0 0 8 amp OS21 GRP IRL ENCODED 7 OS21 CTRL NONE 0 0 7 amp OS21 GRP IRL ENCODED 6 OS21 CTRL NONE 0 0 6 amp OS21 GRP IRL ENCODED 5 OS21 CTRL NONE 0 0 5 amp OS21 GRP IRL ENCODED 4 OS21 CTRL NONE 0 0 4 amp OS21 GRP IRL ENCODED 3 OS21 CTRL NONE 0 0 3 amp OS21 GRP IRL ENCODED 2 OS21 CTRL NONE 0 0 2 amp O0S21 GRP IRL ENCODED 1 OS21 CTRL NONE 0 0 1 amp O0S21 GRP INTC 0 OS21 CTRL INTC 0 0 4 RTC amp OS21 GRP INTC 1 OS21 CTRL INTC 0 1 15 TMU 2 amp OS21 GRP INTC 2 OS21 CTRL INTC 0 2 15 TMU 1 amp OS21 GRP INTC 3 OS21 CTRL INTC 0 3 15 TMU O amp OS21 GRP INTC 4 OS21 CTRL INTC 1 0 0 NOT CONNECTED amp OS21 GRP INTC 5 OS21 CTRL INTC 1 1 14 SCIF 1 amp O0S21 GRP INTC 6 OS21 CTRL INTC 1 2 0 NOT CONNECTED amp O0S21 GRP INTC 7 OS21 CTRL INTC 1 3 15 WDT amp O0S21 GRP INTC 8 OS21 CTRL INTC 2 0 15 HUDI amp OS21 GRP INTC 9 OS21 CTRL INTC 2 1 14 SCIF 2 amp O0S21 GRP INTC 10 OS21 CTRL INTC 2 2 0 NOT CONNECTED amp OS21 GRP INTC 11 OS21 CTRL INTC 2 3 0 NOT CONNECTED 14 23 7358673 ky OS21 ST40 Board support package 7 amp
11. OS21 MY GROUP 2 22 interrupt group table entry t my interrupt group 2 amp OS21 MY GROUP 2 OS21 CTRL INTC 1 3 14 hn This describes an interrupt group called 0821 MY GROUP 2 which is routed to the interrupt controller INTC It is controlled by bit set 3 on register set 1 and its default priority is 14 interrupt group t OS21 MY GROUP 3 23 interrupt group table entry t my interrupt group 3 amp OS21 MY GROUP 3 OS21 CTRL INTC2 2 7 2 hi This describes an interrupt group called 0821 MY GROUP 3 which is routed to the second interrupt controller INTC2 It is controlled by bit set 7 on register set 2 and its default priority is 2 interrupt group table entry t bsp interrupt group table This describes the complete set of interrupt groups for a given system It comprises a list of interrupt group table entry t types For example interrupt group table entry t bsp interrupt group table amp OS21 GRP NMI OS21 CTRL NONE 0 0 0 amp OS21 GRP IRL ENCODED 15 OS21 CTRL NONE 0 0 15 amp OS21 GRP IRL ENCODED 14 OS21 CTRL NONE 0 0 14 amp OS21 GRP IRL ENCODED 13 OS21 CTRL NONE 0 0 13 amp 0S21 GRP IRL ENCODED 12 OS21 CTRL NONE 0 0 12 amp OS21 GRP IRL ENCODED 11 OS21 CTRL NONE 0 0 11 amp OS21 GRP IRL ENCODED 10 OS21 CTRL
12. STMicroelectronics OS21 for ST40 User manual 7358673 Rev O November 2009 BLANK ky User manual OS21 for ST40 Introduction The API defined in the OS21 User manual ADCS 7358306 encapsulates the generic facilities offered by OS21 on all target platforms However each processor implements certain features in different ways and some processors offer facilities worthy of their own specific API ST40 specific features are documented in this manual All ST40 specific APIs can be accessed by a single include include lt os21 st40 h gt This include file is automatically included from os21 h when sh ___ is defined The SH4 GCC compiler always defines sh therefore tinclude lt os21 h gt is normally all that is necessary to include both the generic OS21 API and the ST40 specific API ST40 specifics Default system stack size on ST40 If no size is specified for the system stack when kernel initialize is called OS21 assumes a default stack size of 32 Kbytes Note The debug kernel always checks for a minimum stack size of 16 Kbytes for OS21 November 2009 7358673 Rev O 1 23 www st com Contents OS21 ST40 Contents Introduction ees dee at en aa a BE RE SEE 1 ST40 specifics 1 Prelat oud eed ie RR ea ees oa ee ed EE EE HE 4 Document identification and control 4 Conventions usedinihisguide
13. TE TE TE TE TE TE TE TE TE TE TE TE PAA A AA A AAA AA AAA DA VPA AA AAA AAA AAA AAA DA PAA ADA AAA A AAA AAA DA RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT D DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT DT 1 T NMI amp 0S21 GRP NMI 0x01C0 0 IRL ENC 15 60821 GRP IRL ENCODED 15 0x0200 IRL ENC 14 60821 GRP IRL ENCODED 14 0x0220 IRL ENC 13 60821 GRP IRL ENCODED 13 0x0240 IRL ENC 12 60821 GRP IRL ENCODED 12 0x0260 IRL ENC 11 60821 GRP IRL ENCODED 11 0x0280 IRL ENC 10 60821 GRP IRL ENCODED 10 0x02A0 T IRL ENC 9 60821 GRP IRL ENCODED 9 0x02C0 0 T IRL ENC 8 amp OS21 GRP IRL ENCODED 8 0x02E0 0 IRL ENC 7 60821 GRP IRL ENCODED 7 0x0300 0 IRL ENC 6 amp OS21 GRP IRL ENCODED 6 0x0320 0 T IRL ENC 5 amp OS21 GRP IRL ENCODED 5 0x0340 0 IRL ENC 4 amp OS21 GRP IRL ENCODED 4 0x0360 0 IRL ENC 3 amp OS21 GRP IRL ENCODED 3 0x0380 0 T IRL ENC 2 amp OS21 GRP IRL ENCODED 2 0
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15. ets OS21 ST40 4 3 List of functions reset cpu Performs a manual reset of the CPU Definition include lt os21 st40 h gt void reset cpu void Arguments None Returns None Errors None Context Callable from task or system context Description This function performs an immediate manual reset of the CPU Note On the ST40 CPU reset is not driven off chip so external devices are not reset by this mechanism However all on chip peripherals are reset reset_reason Definition Arguments Returns Errors Context Description 10 23 Queries the cause of the last reset seen by the CPU include lt os21 st40 h gt reset reason t reset reason void None The cause of the last CPU reset None Callable from task or system context Returns the reason for the last CPU reset Possible values are give in Table 4 Table 4 reset reason t values reset reason t value Description POWER ON RESET Last reset was a power on MANUAL RESET Last reset was a manual reset 7358673 ST OS21 ST40 Constructors and destructors 5 5 1 Constructors and destructors OS21 supports a mechanism that allows pairs of user defined kernel constructor and destructor functions to be installed A constructor function is called automatically by kernel start as its final operation A destructor function is called by the kernel by its atexit handler If the constructor function returns OS21 FAILURE kernel
16. loating point support Floating point overview The ST40 processor has a highly efficient FPU but it has a large register state which makes a significant contribution to the context data which has to be saved and restored by OS21 GCC normally uses the FPU to optimize operations like integer divide on the ST40 This behavior can be disabled with the GCC option m4 nofpu By default OS21 preserves the full FPU state of the FPU on context switch If you only use the FPU via standard GCC C C code only bank 0 FPU registers are used This means that OS21 is unnecessarily preserving FPU bank 1 registers Building the OS21 kernel with the option DCONF FPU SINGLE BANK makes a kernel which only saves bank 0 FPU registers This results in correspondingly faster context switches at the expense of not being able to use FPU bank 1 registers This should not be a problem unless you are using custom written FPU code or libraries Building the OS21 kernel with the option DCONF NO FPU makes a kernel which does not perform any FPU saves or restore on context switch and hence provides the fastest possible context switches When using the DCONF NO FPU option both the kernel and all application code must be compiled with the m4 nofpu option The version of OS21 which is linked in when the mruntime 0s21 and m4 nofpu options are given has precisely this behavior 7358673 7 23 Register context OS21 ST40 3 Register context 3 1 Registers overvie
17. nt bsp ilc table entries This variable specifies the number of entries in bsp ilc table lt is usually set as follows unsigned int bsp ilc table entries sizeof bsp ilc table sizeof ilc table entry t If an ILC is not present on a given target bsp ilc table and bsp ilc table entries must be removed INTC base address This tells OS21 the base address of the first interrupt controller INTC For example void bsp intc base address void OxFFD00000 INTC2 base address This tells OS21 the base address of the second interrupt controller INTC2 For example void bsp intc2 base address void OxFE080000 If INTC2 does not exist remove this line ILC base address This tells OS21 the base address of the ILC memory mapped registers For example void bsp ilc base address void 0x18300000 If no ILC is present remove this line Interrupt system initialization flags interrupt init flags t bsp interrupt init flags This is a combination of flags which is used to control how OS21 initializes the interrupt subsystem Multiple flags can be combined by logically ORing the appropriate flags The following sections describe the valid flags for ST40 Nonmaskable interrupt trigger mode The interrupt controller INTC on the ST40 can be programmed so the nonmaskable interrupt NMI generates an interrupt either on the rising edge or the falling edge of the NMI 7358673 ST OS21 ST40 B
18. nterrupt level controller programming On multiple CPU systems more than one CPU shares access to the interrupt level controller ILC However only one CPU should take responsibility for programming the ILC at start up time normally the master of the system The following flags tell OS21 whether it should program the ILC as a master or program the ILC as a slave If none of these flags are specified OS21 defaults to being an ILC master If both of these flags are specified OS21 defaults to being an ILC slave OS21 ILC MASTER This tells OS21 that this CPU is responsible for the programming of the interrupt level controller When OS21 initializes the interrupt subsystem it programs the ILC as given in the table OS21 ILC SLAVE This tells OS21 that this CPU is not responsible for the programming of the interrupt level controller When OS21 initializes the interrupt subsystem it does not program the ILC as given in the table ky 7358673 19 23 Revision history OS21 ST40 7 20 23 Revision history Table 5 Document revision history Date 1 Oct 2009 Revision O Changes Changes made to Section 6 2 BSP interrupt system description on page 12 10 Nov 2008 N Added Chapter 5 Constructors and destructors on page 11 12 Nov 2007 Moved the generic elements of the board support package to the OS21 User manual ADCS 7358306 15 May 2007 Moved cache API functions to OS21 User man
19. nterrupt system BSP is described below Interrupt group table An entry in the interrupt group table WA typedef struct interrupt group table entry s interrupt group t groupp unsigned int controller 4 unsigned int reg set 4 unsigned int bit set 4 unsigned int pri 4 interrupt group table entry t This describes the interrupt groups to OS21 It indicates which interrupt controller is responsible for each interrupt group and information for programming the interrupt group groupp is a pointer to the name of the interrupt group controller specifies the interrupt controller that the interrupt arrives on OS21 CTRL NONE OS21 CTRL INTC and OS21 CTRL INTC2 are supported on the ST40 reg set is the number of the resister set that the interrupt group can be found on within the given interrupt controller bit set is the bit number within this register set This table allows OS21 to locate an appropiate bit in the interrupt group which maps to the named interrupt group pri is the default priority for the given interrupt group For example ky 7358673 13 23 Board support package OS21 ST40 interrupt group t OS21 MY GROUP 1 21 interrupt group table entry t my interrupt group 1 amp OS21 MY GROUP 1 OS21 CTRL NONE 0 0 7 IE This describes an interrupt group called 0821 MY GROUP 1 which is not routed to any interrupt controller and has a default priority of 7 interrupt group t
20. o the named interrupt Output 0 of the ILC must map to 0821 INTERRUPT ILC 0 in the interrupt table and so on This enables OS21 to locate the appropriate state in the interrupt table that the ILC interrupt maps to For example interrupt name t OS21 MY INTERRUPT 21 ilc table entry t my interrupt amp OS21 MY INTERRUPT 1 15 OS21 ILC TRIGGER RISING EDGE This describes an interrupt called 0821 MY INTERRUPT which is routed into input 1 of the ILC and out on output 15 Line 15 out of the ILC is asserted on the rising edge of input 1 ilc table entry t bsp ilc table 7358673 17 23 Board support package OS21 ST40 Note 6 2 4 6 2 5 6 2 6 6 2 7 18 23 This describes the set of interrupts that arrive at the ILC lt comprises a list of ilc table entry t types For example ilc table entry t bsp ilc tablell amp OS21 INTERRUPT PIO 0 0 0 OS21 ILC TRIGGER HIGH LEVEL amp OS21 INTERRUPT SSC 0 7 1 OS21 ILC TRIGGER HIGH LEVEL amp OS21 INTERRUPT DMA 0 24 10 0821 ILC TRIGGER HIGH LEVEL YA 0821 INTERRUPT DMA 1 25 10 0821 ILC TRIGGER HIGH LEVEL 0821 INTERRUPT DMA 2 26 10 0821 ILC TRIGGER HIGH LEVEL 40821 INTERRUPT DMA 3 27 10 0821 ILC TRIGGER HIGH LEVEL L YA 60521 INTERRUPT DMA 4 28 10 OS21 ILC TRIGGER HIGH LEVEL amp OS21 INTERRUPT DMA ERR 29 10 OS21 ILC TRIGGER HIGH LEVE YA ram aa a EA eM ee ji unsigned i
21. oard support package signal The following flags tell OS21 how to configure INTC in this respect If none of these flags are specified OS21 defaults to triggering on the falling edge If both are specified OS21 defaults to triggering on the rising edge OS21 INTC NMI RISING EDGE This tells OS21 to program the INTC so that an NMI is generated on the rising edge of the NMI signal when it transitions to the high state OS21 INTC NMI FALLING EDGE This tells OS21 to program the INTC so that an NMI is generated on the falling edge of the NMI signal when it transitions to the low state IRL configuration mode The interrupt controller INTC on the ST40 can accomodate four external interrupt request lines IRL These can be configured either as four separate interrupt lines giving four interrupt sources or as a binary encoding of 15 different interrupts by using each of the four interrupt lines as a binary bit The following flags tell OS21 how the INTC should be configured in this respect If neither of these flags are specified OS21 defaults to four separate IRL lines If both flags are specified OS21 defaults to the encoding mechanism OS21 INTC IRL LEVEL ENCODED This tells OS21 to program the INTC so that it treats the four IRL lines as a level encoding of 15 different interrupts OS21 INTC IRL INDIVIDUAL This tells OS21 to program the INTC so that it treats the four IRL lines as four separate interrupt request lines I
22. port chapter Amended text in overview Board support package chapter Added two functions to BSP code section Introduction chapter Added the ST40 specifics section Interrupts chapter Added the task context interrupt information section Amended description of the flags parameter in the Feb 02 B Initializing the interrupt handling subsystem section Amended the description of the interrupt_init_controller function Caches and memory areas chapter Amended the table containing the macros defined in st40_cache h Board support package chapter Amended the BSP code section Nov 01 A Initial release ST 7358673 21 23 Index OS21 ST40 Index B GSOIS ir ER resume eee EER RO Tu RE RR 9 Backus Naur Form 4 HIE aa a base address 18 BNF See Backus naur Form S BSP ST40 interrupt system 12 specifics 1 interrupttables 12 system stack size 1 timer assignments 5 F system stack size 1 floating point support 7 IM A 9 PPU diea EE OT EDGE GR dd 7 T G task context registers 8 GOG kre his a a a aa GEO ed Pee 7 iimeout unge RS Lo 6 timer assignments 5 global context registers 8 UMES irrita aretes 5 timeslice timer 5
23. ption The BSP is responsible for describing the interrupt system to OS21 This coupled with the platform specific interrupt code implements OS21 s generic interrupt API On the ST40 this comprises the following elements e interrupt names interrupt groups interrupt tables INTC base address INTC2 base address ILC base address interrupt system initialization flags Interrupt names A type is provided by OS21 called interrupt name t Each interrupt is assigned a unique name interrupt name t which allows it to be identified both in the BSP interrupt tables that follow and in the interrupt API The BSP need only contain those interrupts that are used by other OS21 or the application code If any interrupts are missing a linker error occurs If interrupts are declared in the BSP but are subsequently not used this does no harm other than use memory For example Define a DMA interrupt in the BSP interrupt name t OS21 INTERRUPT DMA 0 21 Header files are provided with OS21 which complement the interrupt description in the BSP By including the appropriate header file all the relevant external interrupt name t declarations are obtained These header files are included in the ST40 specific include area and are named after the specific chip For example include lt os21 st40 stm8000 h gt or include lt os21 st40 st40gx1 h gt User code is also free to declare only those interrupt names that it requires For example
24. r to yield a tick which is approximately 10 microseconds 1 4 ST40 timer assignments OS21 uses all three ST40 TMU timers as shown in Table 7 Table 1 ST40 timer assignments Timer name OS21 usage TMUO System timer TMU1 Timeslice timer TMU2 Timeout timer The system timer is left free running and is used by time now to return the system time On ST40 the system time osclock_t is a 64 bit value OS21 maintains the top 32 bits of the 64 bit time using an interrupt handler which is called each time the 32 bit timer reaches zero The lower 32 bits of the system time are the value in the system timer The timeslice timer is programmed to run for the timeslice period before generating an interrupt and reloading This is used to drive timeslice events into the task scheduler Note When profiling the application is built with the pg flag this timer is used for PC sampling as well as timeslicing In this case it is programmed to yield approximately 16384 interrupts per second OS21 ensures that the frequency of timeslice events into the scheduler remains unchanged ky 7358673 5 23 Timers OS21 ST40 The timeout timer is programmed on demand to interrupt when the reguired number of ticks has elapsed When multiple timeouts are reguested OS21 orders which timeout should occur next and programs the timeout timer appropriately 6 23 7358673 ky 0S21 ST40 Floating point support 2 2 1 Note F
25. rminal string without that nonitalicized part For example vspace name 4 Each phrase definition is built up using a double colon and an equals sign to separate the two sides 5 Alternatives are separated by vertical bars 6 Optional sequences are enclosed in square brackets and 7 Items which may be repeated appear in braces and 7358673 ST OS21 ST40 Timers 1 Timers 1 1 Timers overview The ST40 has three independent timer units TMUs Each is capable of running as a free running auto reload 32 bit counter with interrupt on underflow Each can be programmed to count either the RTC 16 kHz or some fraction of the input clock The greatest accuracy is obtained by counting based on a large fraction of the input clock and running that clock ata high frequency 1 2 Input clock frequency The precise speed of the input clock is determined by the end user it is a function of the board design and boot software OS21 is not responsible for setting the input speed therefore it has to be made aware of what it is This is done with the Board Support Package BSP using a function called bsp timer input clock frequency hz Full details of this function can be found in the OS21 User manual ADCS 7358306 chapter 16 1 3 OS21 tick duration OS21 establishes the period of one tick when it boots Based on the input clock frequency it selects an appropriate diviso
26. start stops processing and triggers a kernel panic Install a constructor function by using the following macro OS21 CONSTRUCTOR func and a destructor function with the following macro OS21 DESTRUCTOR func where unc is the name of the constructor or destructor function to be installed This function must have the following prototype int func void The return value of the function must be either 0821 SUCCESS OF OS21 FAILURE The macros for the OS21 constructor and destructor are defined in os21 st40 h Multiple constructors and destructors Multiple constructors and destructors can be installed The constructor functions are called in the same order in which they have been installed The OS21 kernel calls the destructor functions in the reverse order to the order in which they are installed acting on the premise that each destructor undoes the effects of the corresponding constructor 7358673 11 23 Board support package OS21 ST40 6 6 1 6 2 6 2 1 12 23 Board support package Board support package overview OS21 Board Support Packages BSPs are supplied for all supoorted platforms both as pre built libraries and accompanying sources The generic features of BSPs can be found in the OS21 User manual ADCS 7358306 chapter 16 This section describes the platform specific features of the BSP For the ST40 this consists only of the interrupt system description BSP interrupt system descri
27. th in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky 7358673 Rev O 23 23
28. ual ADCS 7358306 as these are now generic 22 Jan 2007 Moved to new template Chapter 1 Caches and memory areas on page 5 Updated for virtual memory 32 bit support Chapter 6 Board support package on page 12 Timer input freg updated Jun 06 Throughout Updated function context information Caches and memory areas chapter Updated I cache and D cache descriptions and explained non portable code for ST40 core variants Exceptions chapter Removed chapter Sep 03 Board support package chapter Updated BSP interrupt system description Interrupt tables and Interrupt system initialization flags Jul 03 May 03 Floating point support chapter Chapter has been rewritten Board support package chapter Updated BSP data Timer input frequency Throughout Changed bsp peripheral bus clock frequency hz to bsp timer input clock frequency hz bsp timeslice frequency hz to bsp timeslice frequency hz and peripheral bus clock to input clock Updated references to interrupts Introduction chapter Added note to ST40 specifics Interrupts chapter Removed chapter Caches and memory areas chapter Updated cache enable data function description Added note to cache invalidate data all Timers chapter Chapter has been rewritten Resets chapter Updated examples in Overview Board support package chapter Chapter has been rewritten g 7358673 OS21 ST40 Revision history
29. w The following registers are saved as part of each task s context RO to R7 bank 0 registers R8 to R15 SR GBR MACL MACH PR PC FPRO_BANKO to FPR15_BANKO FPRO BANKI to FPR15 BANKI FPSCR FPUL The following registers are not saved since they form part of the global context for the system e VBR e DBR 8 23 7358673 ky OS21 ST40 Resets 4 Resets 4 1 Resets overview 4 2 A reset can occur because of a power on or because of a manual reset Manual resets are typically due to programming errors Examples include the watchdog timer expiring or a program requested manual reset OS21 does not provide a mechanism for passing more specific data across resets This is a board design issue for instance data could be placed in NVRAM to signal the precise reason for a requested reset OS21 provides an API for requesting the CPU to be reset and also for determining the cause of the last reset power on reset or manual reset Reset API summary Table 2 and Table 3 provide an overview of the reset API The reset API is obtained by including the header file lt os21 st40 h gt Table 2 Functions defined in os21 st40 reset h Function Description reset cpu Performs a manual reset of the CPU reset reason Returns the reason for the last CPU reset Table 3 Types defined in os21 st40 reset h Type Description reset reason t The cause of the last CPU reset 7358673 9 23 Res
30. x03A0 0 T IRL ENC 1 amp OS21 GRP IRL ENCODED 1 0x03C0 0 HUDI UDI amp 0S21 GRP INTC 8 0x0600 0 TIMER 0 60821 GRP INTC 3 0x0400 0 TIMER 1 60821 GRP INTC 2 0x0420 0 TIMER 2 60821 GRP INTC 1 0x0440 0 TMU 2 TICPI 60821 GRP INTC 1 0x0460 0 T RTC ATI amp OS21 GRP INTC 0 0x0480 0 T RTC PRI amp OS21 GRP INTC 0 0x04A0 0 RTC CUI amp OS21 GRP INTC 0 0x04C0 0 SCIF 1 ERI amp OS21 GRP INTC 9 0x04E0 O SCIF 1 RXI 60821 GRP INTC 9 0x0500 O SCIF 1 BRI amp OS21 GRP INTC 9 0x0520 0 SCIF 1 TXI 0821 GRP INTC 9 0x0540 0 SCIF 2 ERI amp OS21 GRP INTC 5 0x0700 0 SCIF 2 RXI 60821 GRP INTC 5 0x0720 0 SCIF 2 BRI amp OS21 GRP INTC 5 0x0740 0 SCIF 2 TXI amp OS21 GRP INTC 5 0x0760 0 WDT ITI amp OS21 GRP INTC 7 0x0560 0 PT ILC 0 amp OS21 GRP INTC2 8 0x1000 0 l ILC 1 0821 GRP INTC2 9 0x1080 4 T ILC 2 amp OS21 GRP INTC2 10 0x1100 8 T ILC 3 0821 GRP INTC2 11 0x1180 12 T ILC 4 amp OS21 GRP INTC2 12 0x1200 16 T ILC 5 amp OS21 GRP INTC2 13 0x1280 20 T ILC 6 amp OS21 GRP INTC2 14 0x1300 24 T ILC 7 amp OS21 GRP INTC2 15 0x1380 28 T ILC 8 amp OS21 GRP INTC2 16 0x1400 0 T ILC 9 amp OS21 GRP INTC2 17 0x1480 4 T ILC 10 amp OS21 GRP INTC2 18 0x1500 8 T ILC 11 amp OS21 GRP INTC2 19 0x1580 12 T ILC 12 amp OS21 GRP INTC2 20 0x1600 16
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