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20F050P00 E1 User Manual - Diamond Point International
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1. 56 Memory map processor VIEW sins sas ceca e dy eee e RR ee EDEA 58 Address for PCI css stems beum nes sea e gedaan sa 58 Dedicated interrupt line 59 Interrupt numbering assigned by 59 DMB P 59 Onboard POLDdevie8S suo d dace dabo pa doe ed d 60 16 Getting Started 1 Getting Started This chapter gives an overview of the board and some hints for first installation in a system 1 1 Maps of the Board Figure 1 Map of the board front panel view With FPGA F50P Standard 8HP USB 1 USB 0 LAN 0 lt e o N e Note can be implemented as an option with an onboard MEN Mikro Elektronik GmbH 17 20F050P00 E1 2009 11 20 Getting Started USB 0 E USB 1 wl UART to USB LAN 0 8 ERN Heat Sink n 5 8 p MEN Mikro Elektronik GmbH 18 20F050P00 E1 2009 11 20 wv Getting Started 1 2 Integrating the Board into a System If you need electrical isolation between shield rack or enclosure and digital ground you need to use guide rails without a shield strip in your CompactPCI rack for the slot where the F50P is inserted You can use the following check list when installing the board in a system for the first time and with minimum configuration Power down the s
2. DRAM ok i Relocating Secondary MENMON valid MENMON D or d pressed DRAM not working v necu MainState Full Mode y FullStartup UN S Init heap in DRAM StartupPrologue J MainState MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 Figure 4 MENMON State diagram main state MENMON Main State E Y Init A N Init on chip MMBIOS devs PCI autoconfig init FPGA load Init further MMBIOS devs US for user abort No user intervention Y Selftest SETUP Jl Screen Menu do start network servers Screen oriented Main menu I s pressed N ES Perform self tests User abort or degraded mode User abort or Self test error and stignfault false Z Check for user abort Touch pressed outside setup do touch calibration TouchCalib No user intervention aa Auto Update Check do check for update media Execute Auto update dialog when suitable medium found Leave dialog after 5 iP E Booting mmstartup empty Jump to bootstrapper No user intervention n Execute mmstartup string E Y Y MenmonCli a D entry start network servers do process command lin
3. 1 The actual disks can be selected through command USBDP see also page 57 MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 MENMON 3 6 4 System Parameters System parameters are parameters stored in EEPROM Some parameters are automatically detected by MENMON such as CPU type and frequency The parameters can be modified through the EE xxx command via the command line 3 6 4 4 Physical Storage of Parameters Most parameters are stored in the 1024 byte serial EEPROM on the F50P If required you can configure MENMON to store some strings in boot Flash rather than in EEPROM 3 6 4 2 Start up with Faulty EEPROM If a faulty EEPROM is detected i e the checksum of the EEPROM section is wrong the system parameters will use defaults The behavior is the same if the EEPROM is blank The default baud rate is 9600 3 6 4 3 F50P System Parameters Note Parameters marked by Yes in section Parameter String are part of the MENMON parameter string Table 22 MENMON F50P system parameters Autodetected parameters Parameter JP Parameter User alias Description Standard Default String Access ccbclkhz CCB clock frequency decimal Hz Yes Read only clun MENMON controller unit number that Yes Read only MENMON used as the boot device hexadecimal cons Selected console Set to name of first Yes Read only selected console cpu CPU type as ASCII string e g Yes
4. Note The F50P s J2 connector type complies with the PICMG 2 30 CompactPCI PlusIO standard Note The signal mnemonics in the above table correspond to the PICMG 2 30 CompactPCI PlusIO standard and therefore do not show the F50P internal interface numbering Please see Chapter Table 7 Pin assignment of rear I O connector J2 I O options Ethernet USB SATA on page 33 for the board internal numbering MEN Mikro Elektronik GmbH 32 20F050P00 E1 2009 11 20 Functional Description The following table shows all options for non FPGA controlled interfaces For this reason only those pins are marked for FPGA I O that cannot be used for other functions See Table 8 Pin assignment of rear I O connector J2 I O options maximum FPGA control on page 34 for the assignment of the maximum number of FPGA controlled pins Table 7 Pin assignment of rear connector J2 options Ethernet USB SATA F E D C B A 7 22 GND GAO GA1 GA2 GAS3 GA4 GND 21 GND GND CLK6 GND 20 GND GND CLK5 GND 19 GND GND GND 18 GND GND CORRER 17 GND GND 16 GND GND 15 GND GND 14 GND GND 13 GND GND 12 GND GND 11 GND GND 10 GND GND 9 GND GND 8 GND SATA2_RX GND 7 GND SATA2 RX SATA2_TX GND 6 GND SATA1_RX SATA2_TX GND 5 GND SATA1_RX SATA1_TX GND 4 GND 011 SATA1_TX USB GND 3 GND GNT4 REQ4 GNT3 GND 2 GND REQ3 GNT2
5. 42 3 5 Diagnostic Tests rors esi a ts rr EE REI E cama qaa vanes 43 SN MENS IO TP 43 3 5 2 SDRAM SRAM and FRAM 44 5 93 I1BEPRONL oom eed IP qi SMS 45 Soe piti bp Pais 46 3 5 Hardware Monitor lest ioo Re Re 46 99 07 dco Uu 47 3 6 MENMON Configuration and Organization 48 5 0 Consoles cet as qae qe q da 48 3 6 2 MENMON Memory 49 3 6 3 MENMON BIOS Logical Units 50 3 004 System Parametets sec ces PE ur per XA pr 51 3 7 MENMON Commands s rmm RR RR p 56 4 Organization of the Board 58 Memory Mappings m ineto DTE RE 58 4 2 Interrupt Handling 4 5 6 sese eae mares 59 4 3 SMB DEVICES oscar op erp eps E C LE pP 59 44 Onboard PCLDeVviGes 4 ui oun rcd pd hasta ken usos 60 5 ADDeDUIX cessione e epp tesa edes eco o die 61 5 I Literature and Web Resources s E RES P hs 61 5 14 PowerPC reas er n RR RE RE RE RIA 61 IIL SAAS Libano 61 ILS 61 S4 HORE TERRAE Set eae 2 61 2 15 sCompaciPCl pP ba oats aks 61 5 1 0 CompactPCI PlusIO scusa bh RR RE 62 5 2 Finding out the Board s Article Number Revision and Serial Number62 MEN Mikro Ele
6. cnt Move copy memory MS from to val Search pattern in memory MT opts start end lt runs gt Memory test NBOOT lt opts gt Boot from network NDL lt opts gt Update Flash from network NETSTAT Show current state of networking parameters PCI PCI probe PCIC lt dev gt lt addr gt lt bus gt lt func gt lt val gt PCI config register change PCID dev lt bus gt lt func gt PCI config register dump PCIR List PCI resources PCI VPD lt devNo gt lt busNo gt capld PCI Vital Product Data dump PFLASH D lt O gt S lt A gt Program Flash PGM XXX args Media copy tool PING host lt opts gt Network connectivity test RELOC Relocate MM to RAM RST Cause an instant system reset RTC xxx lt arg gt Real time clock commands S lt addr gt Single step user program SERDL passwd Update Flash using YModem protocol SETUP Open interactive Setup menu UNZIP src size lt opt gt lt dest gt lt size gt Unzip memory zipped by gzip USB lt bus gt Init USB controller and devices on a USB bus USBT lt bus gt lt p1 gt lt p5 gt Shows the USB device tree USBDP lt bus p1 p5 gt d lt x gt Display modify USB device path MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 Organization of
7. 2009 11 20 Technical Data Technical Data CPU PowerPC PowerQUICC MPC8548 MPC8548E MPC8543 or MPC8543E 800MHz up to 1 5GHz Please see Configuration Options for available standard versions e500 PowerPC core with MMU and double precision embedded scalar and vector floating point APU Integrated Northbridge and Southbridge Memory e 2x32KB L1 data and instruction cache 512KB 256KB L2 cache integrated in MPC8548 MPC8543 Up to 2GB SDRAM system memory Soldered DDR2 with or without ECC Up to 300 MHz memory bus frequency depending on CPU Up to 16GB soldered Flash disk SSD solid state disk Up to 32MB additional DDR2 SDRAM FPGA controlled e g for video data 16MB boot Flash 2MB non volatile SRAM With GoldCap backup 128 non volatile FRAM Serial EEPROM 4kbits for factory settings Mass Storage Parallel IDE PATA Up to 16GB soldered ATA Flash disk SSD solid state disk Serial ATA SATA Up to two ports via rear J2 Transfer rates up to 150MB s 1 5 Gbits s Via PCI to SATA bridge See Interface Configuration Matrix showing possible I O combinations Graphics FPGA controlled optional e VGA connector prepared at front panel USB host Five USB 2 0 host ports One series connector at front panel Four ports via rear I O J2 ORCI and EHCI implementation Data rates up to 480Mbits s MEN Mikro Elektronik GmbH 3 20F050P00 E1 2009 11
8. 20F050P00 E1 2009 11 20 Functional Description 2 10 CompactPCI Interface The F50P is a 3U CompactPCI system slot board It implements a 32 bit PCI interface to the CompactPCI backplane which uses a 3 3 V signaling voltage It also tolerates 5 V The CompactPCI bus connects to the MPC8548 MPC8543 processor via a PCI Express x1 link and a PCIe to PCI bridge The pin assignment of connector J1 as defined in the CompactPCI specification will not be repeated here 2 11 Rear I O CompactPCI PluslO The F50P provides great flexibility for routing functions to rear I O An optional onboard FPGA allows to implement customized functions on rear I O connector J2 of the board with a total available pin count of 64 pins Different combinations of interfaces controlled by the CPU and the FPGA are possible The standard version of the F50P is compliant to the PICMG 2 30 CompactPCI PlusIO standard It supports the pin assignment defined by PICMG 2 30 with 2 SATA and 4 USB interfaces at the J2 connector The four USB ports are always routed to the J2 connector Please note that the rear I O Ethernet interfaces of the F50P are not compliant to the CompactPCI PlusIO standard The Ethernet transformers for the rear Ethernet ports are not located on the F50P but must be placed on a rear I O board or on the backplane This means that it is possible to route up to three Ethernet channels to rear I O but additional transformers need to be implemented
9. none CLUN O0xFF first available Ether net OxFF Read write gcon CLUN of graphics device to display boot logo CLUN 0x00 disable CLUNZOXxF F Autoselect first avail able graphics console AUTO Read write hdp HTTP server TCP port decimal 0 don t start telnet server 1 use default port 23 else TCP port for telnet server Read write tdp Telnet server TCP port decimal 0 don t start HTTP server 1 use default port 80 else TCP port for HTTP server Read write MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 MENMON 3 6 2 MENMON Memory Map 3 6 21 MENMON Memory Address Mapping Table 18 MENMON Address map full featured mode Address Space Size Description 0x 0000 0000 0000 1400 5KB Exception vectors 0x 0000 3000 0000 3FFF 4 MENMON parameter string Ox 0000 4200 0000 42FF 256 bytes VxWorks bootline Ox 0000 4300 OOFF FFFF Nearly Free 16 MB 0100 0000 O1DF FFFF 2 MB Heap2 Ox 0000 FFFF 1MB Text Reloc Ox O1FO 0000 O1F1 FFFF 128 Stack Ox 01 2 0000 01 4 FFFF 128 Stack for user programs and operating system boot Ox 5 0000 FFFF 640 KB Ox 0000 FFFF 64KB Not touched for OS post mor tem buffer i e VxWorks WindView or MDIS debugs requires ECC to be turned off
10. 2 1 1 If implemented Table 23 MENMON F50P system parameters Production data Parameter e Parameter User alias Description Standard Default String Access brd Board name Yes Read only brdmod Board model mm Yes Read only brdrev Board revision xx yy zz Yes Read only prodat Board production date MM DD YYYY Yes Read only repdat Board last repair date MM DD YYYY Yes Read only sernbr Board serial number Yes Read only MEN Mikro Elektronik GmbH 52 Table 24 MENMON F50P system parameters MENMON persistent parameters MENMON Parameter BT Parameter User alias Description Standard Default String Access bsadr bs Bootstrapper address Used when 0 No Read write command was called without argu ments hexadecimal 32 bits cbr baud Baudrate of all UART consoles dec 9600 Yes Read write conO con3 CLUN of console 0 3 hex see Chap OxFF auto No Read write ter 3 6 1 Consoles on page 48 eccsth ECC single bit error threshold 32 No Read write ecl CLUN of attached network interface OxFF No Read write hex gcon CLUN of graphics screen hex see OxFF auto No Read write Chapter 3 6 1 Consoles on page 48 hdp HTTP server TCP port decimal 1 No Read write kerpar Linux Kernel Parameters 399 chars Empty string No Read write max Part of VxWorks bootline if usefl 400 chars max if useflpar 1 Idlogodis Disable loa
11. BOOTP lt opts gt Obtain IP config via BOOTP C BWLLNAX lt gt lt val gt Change memory CHAM lt clun gt Dump FPGA Chameleon table CONS Show active consoles CONS ACT lt clun1 gt lt clun2 gt Test console configuration CONS BAUD lt baud gt Change baud rate instantly without storing CONS GX lt clun gt Test graphics console D lt addr gt lt cnt gt Dump memory DBOOT lt clun gt lt dlun gt lt opts gt Boot from disk DCACHE OFF ON Enable disable data cache DIAG lt which gt VTF Run diagnostic tests DSKRD lt args gt Read blocks from RAW disk DSKWR args Write blocks to RAW disk EE xxx lt arg gt Persistent system parameter commands EER xxx lt arg gt Raw serial EEPROM commands ERASE D O lt S gt Erase Flash sectors Fl lt from gt lt to gt lt val gt Fill memory byte GO lt addr gt Jump to user program H Print help HELP I lt D gt List board information ICACHE OFF ON Enable disable instruction cache IOI Scan for BIOS devices LM81 Show current voltage and temperature val ues LOGO Display MENMON start up text screen LS lt clun gt lt dlun gt lt opts gt List files partitions on device MEN Mikro Elektronik GmbH 56 20F050P00 E1 2009 11 20 MENMON Command Description MC lt addr1 gt addr2 cnt Compare memory MII lt clun gt lt reg gt val Ethernet MII register command MO from to
12. O PCle I O space Ox 0000 FCOO 7FFF Ox 8000 FFFF I O I O space 1 PCD not available for MPC8543 MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 4 2 Organization of the Board Interrupt Handling Interrupt handling is done via the 12 external interrupt lines of the CPU IRQ 11 0 While the IRQ lines 8 to 10 are used as PCI interrupt lines see Table 31 Interrupt numbering assigned by MENMON on page 59 the Ethernet function unit interrupt is routed to a dedicated interrupt line The mapping is as follows Table 30 Dedicated interrupt line assignment MPC854X IRQ Input Function IRQO Ethernet Table 31 Interrupt numbering assigned by MENMON Mire IRQ PCI eise Function MEMO IRQ0 PCle_INTA OxFO IRQ1 PCle_INTB FPGA OxF1 IRQ2 PCle INTC OxF2 IRQ3 PCle_INTD OxF3 IRQ8 PCI_INTA SATA 0x8 IRQ9 PCI_INTB 1st USB Controller 0x9 USBO0 2 IRQ10 PCI INTC 2nd USB Controller USB3 4 5 4 3 SMB Devices Table 32 SMB devices Bus Address Function 0x0 Ox5E LM81 hardware monitor OxA2 Real time clock 0xA8 CPU EEPROM 0xD2 Clock generator 0 1 0 ID EEPROM MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 Organization of the Board 4 4 Onboard PCI Devices Table 33 Onboard PCI devices Interface Bus Device Vendor ID Device ID Funct
13. SYSEN GND 1 GND REQ2 GNT1 1 GND MEN Mikro Elektronik GmbH 33 20F050P00 E1 2009 11 20 Functional Description Table 8 Pin assignment of rear connector J2 options maximum FPGA control F E D C B A 7 22 GND GAO GA1 GA2 GA3 GA4 GND 21 GND GND CLK6 GND 20 GND GND CLK5 GND 19 GND GND GND GND 18 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND FEDCBAZ GNT3 SYSEN REQ1 NOU Q DN C z MEN Mikro Elektronik GmbH 34 20F050P00 E1 2009 11 20 Table 9 Signal mnemonics of rear connector J2 Functional Description MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 Signal Direction Function Power GND Ground VIO in 3 3 V V I O supply voltage 3 3V in 3 3V supply voltage optional 5V in 5V supply voltage optional CompactPCI CLK 6 1 out Clocks 1 to 6 GA 4 0 in Geographic addressing signals 0 to 4 GNT 6 1 out Grant 1 to 6 REQ 6 1 in Request 1 to 6 SYSEN in System slot identification Functional Description 2 12 Reset Button and Status LED The F50P has a reset button and one status LED at the front panel The reset button is recessed within the front panel and requires a tool e g paper clip to be pressed preventing the button from being inadvertently activated The yellow status LED shows b
14. and burst access On each pass this test first fills the entire memory starting with the lowest address with the selected pattern using the selected access mode and then verifies the entire block This test 15 destructive Checks address lines data lines All control signals All SDRAM cells 3 5 3 EEPROM Table 13 MENMON Diagnostic tests EEPROM Test Name Description Availability EEPROM I C access Magic nibble check Always Groups POST AUTO ENDLESS This test reads the first EEPROM cell over SMB and checks if bits 3 0 of this cell contain the magic nibble OxE MEN Mikro Elektronik GmbH 45 20F050P00 E1 2009 11 20 MENMON 3 5 4 USB Table 14 MENMON Diagnostic tests USB Test Name Description Availability USBO USB5 USB device access sector 0 Always access Groups NONAUTO ENDLESS The test performs a sector 0 read from the Flash disk without verifying the content of the sector Checks USB control lines Data Data Basic USB transfer Does not check RQ signals Partition table or file system on disk 3 5 5 Hardware Monitor Test Table 15 MENMON Diagnostic tests hardware monitor Test Name Description Availability LM81 LM81 basic access test Always Groups POST AUTO MEN Mikro Elektronik GmbH 46 20F050P00 E1 2009 11 20 MENMON 3 5 6 RTC Table 16 MENMON Diagnostic t
15. functions are implemented through the FPGA With regard to the FPGA resources such as available logic elements or pins it is not possible to grant all possible combinations of FPGA IP cores You can find an overview and descriptions of all available FPGA IP cores on X MEN s website Table 8 Pin assignment of rear connector J2 I O options maximum FPGA control on page 34 gives the I O pins available for custom FPGA functions 64 pins MEN Mikro Elektronik GmbH 3l 20F050P00 E1 2009 11 20 I P S Y SA s Functional Description 2 11 2 Standard and Possible Pin Assignments Table 6 Pin assignment of rear connector J2 standard board version PICMG 2 30 PluslO compatible F E D C B A 7 22 GND GAO GA1 GA2 4 GND 21 GND GND CLK6 GND 20 GND GND CLK5 GND 19 GND GND GND GND 18 GND GND oe 17 GND GNT6 REQ6 GND 16 GND GND GND 15 GND GNT5 REQ5 GND 14 GND GND 13 GND GND 12 GND GND 11 GND 5 GND 10 GND GND 9 GND GND 8 GND SATA2_RX GND 7 GND SATA2 RX SATA2 TX GND 6 GND SATA1 RX SATA2 TX GND 5 GND SATA1 RX SATA1 TX GND 4 GND SATA1 TX USB3 VIO GND 3 GND GNT4 REQ4 GNT3 GND CLK4 GND 2 GND REQ3 GNT2 SYSEN CLK3 CLK2 GND 1 GND REQ2 GNT1 REQ1 GND CLK1 GND
16. then and the pinout will not be compliant with PICMG 2 30 CompactPCI PlusIO MEN offers a rear I O transition module on which the two SATA and four USB interfaces from the J2 connector can be accessed the CT12 Please note that because of the fixed PICMG 2 30 J2 pin assignment of CT12 only PICMG 2 30 compliant versions of F50P should be used with the CT12 Otherwise signals that have a different function on the F50P may interfere with the CT12 signals The Interface Configuration Matrix shows an overview of all varieties that are pos sible Chapter 2 11 2 Standard and Possible Pin Assignments on page 32 gives the standard pin assignment along with possible signal routings For further information on the CT12 rear transition module see MEN s web site In any case please contact our sales team for specially configured board ver sions This chapter only summarizes the board s options MEN Mikro Elektronik GmbH 30 20F050P00 E1 2009 11 20 Functional Description 2 11 1 User Defined I O from Onboard FPGA The F50P provides the option to include an onboard FPGA The component is a powerful Altera Arria GX AGX35C device and is connected to the CPU via a fast serial PCI Express x1 link It permits to configure the board s rear I O according to your needs without any hardware modifications Please note that a J2 pin assignment compliant with the PICMG 2 30 CompactPCI PlusIO standard is not possible when customized
17. 0x 0200 0000 End of RAM Free or download area 3 6 2 2 Boot Flash Memory Map Table 19 MENMON Boot Flash memory map Flash Offset CPU Address Size Description Ox 00 0000 0x FF00 0000 14 MB Available to user 128 KB DE 0000 0000 128 KB System parameter section in boot Flash if useflpar system parameter is set to 1 Ox EO 0000 FFEO 0000 1 Secondary MENMON Ox FO 0000 FFFO 0000 1 Primary MENMON MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 MENMON 3 6 3 MENMON BIOS Logical Units The following table shows fixed assigned CLUNs All other CLUNs are used dynamically Table 20 MENMON Controller Logical Units CLUNs CLUN Description 0x02 ETHERO Ethernet 0 0x03 ETHER1 Ethernet 1 LAN 1 0x04 ETHER2 Ethernet 2 LAN 2 0x06 USB USB controller 0x08 UART to USB COM MPC854X DUART channel 0 TOUCH Reserved for touch console 0x10 SATAO SATA port 0 routed to SSD Flash 0x11 SATA1 SATA port 1 0x12 SATA2 SATA port 2 0 2 All other devices dynamically detected on PCI or FPGA devices 0x40 Telnet console 0x41 HTTP monitor console Table 21 MENMON Device Logical Units DLUNs CLUN DLUN pos None Description 0x06 0x00 USB USB controller 0x10 0x00 SATAO Disk at SATA port 0 onboard SSD Flash 0x11 0x00 SATA1 Disk at SATA port 1 0x12 0x00 SATA2 Disk at SATA port 2
18. 20 Technical Data USB client One USB client port on series A connector at front panel Via UART to USB converter Data rates up to 115 2kbits s 16 byte transmit receive buffer Handshake lines none Ethernet Up to three 10 100 1000Base T Ethernet channels with MPC8548 E two channels with MPC8543 E Two RJ45 connectors at front panel Two front panel LEDs for channels for LAN link activity status and connec tion speed All three possible also via rear I O J2 Note requires additional Ethernet transformers on rear I O board or backplane See Interface Configuration Matrix showing possible I O combinations User defined I O FPGA controlled optional Up to 64 lines Connection via rear I O J2 See Interface Configuration Matrix showing possible I O combinations Front Connections Standard One USB 2 0 host Series A One USB client Series A Two Ethernet RJ45 Rear I O Four USB 2 0 Up to three 1000Base T Ethernet Up to two SATA Up to 64 I O lines with optional FPGA Reduces Ethernet SATA interfaces See Interface Configuration Matrix showing possible I O combinations Standard version compatible with PICMG 2 30 CompactPCI PlusIO Four USB 2 0 Two SATA FPGA The FPGA offers the possibility to add customized I O functionality See Config uration Options Standard FPGA not assembled Miscellaneous Real time clock with GoldCap backup Temperature sensor power
19. 20F050PO00 E1 2009 11 20 F50P 3U PluslO MPC8548 SBC Configuration example 8 HP with heat sink unmounted User Manual man mikro elektronik gmbh n rnberg F50P CompactPCI PluslO MPC8548 SBC F50P 3U CompactPCIG PluslO MPC8548 SBC The F50P is a versatile rugged PowerPC based single board computer for embedded applications It is controlled by an MPC8548 or optionally an MPC8543 PowerPC processor alternatively with encryption unit with clock frequencies between 800 MHz and 1 5 GHz The SBC is equipped with ECC controlled soldered on DDR2 RAM for data storage with up to 16 GB of solid state Flash disk for program storage as well as industrial FRAM and SRAM The board provides up to three Gigabit Ethernet channels six USB ports up to two SATA interfaces and up to 64 user definable I O lines controlled by an optional onboard FPGA These interfaces can be combined in many variations and are available at the front or at the rear using the board s J2 connector The J2 pin assignment and connector type are in compliance with the PICMG 2 30 CompactPCI PlusIO standard the migration path towards CompactPCI Plus Two USB and two RJ45 Ethernet connectors are already provided at the front panel and space is left for an optional VGA connector The large FPGA on the F50P allows to add additional user defined functions such as graphics touch serial interfaces fieldbus co
20. 548 3E or without an integrated security engine with XOR acceleration Table 1 Processor core options on F50P Processor Type Core Frequency L2 Cache Encryption Unit Ethernet Ports MPC8548 1 GHz 1 2 GHz 1 33 GHz 512 KB No 3 1 5 GHz MPC8548E 1 GHz 1 2 GHz 1 33 GHz or 512 KB Yes 3 1 5 GHz MPC8543 800 MHz or 1 GHz 256 KB No 2 MPC8543E 800 MHz or 1 GHz 256 KB Yes 2 AN MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 2 4 2 Thermal Considerations The F50P generates around 17 W of power dissipation when operated at 1 33 GHz A suitable heat sink is provided to meet thermal requirements Please note that if you use any other heat sink than that supplied by MEN or no heat sink at all warranty on functionality and reliability of the F50P may cease If you have any questions or problems regarding thermal behavior please contact MEN Functional Description 2 5 Bus Structure 2 5 1 Host to PCl Bridge The integrated host to PCI bridge is used as host bridge and memory controller for the PowerPC processor All transactions of the PowerPC to the PCI bus are controlled by the host bridge The FRAM SRAM and boot Flash are connected to the local memory bus of the integrated host to PCI bridge The PCI interface is PCI bus Rev 2 2 compliant and supports all bus commands and transactions Master and target operations are possible Only big endian operation is supported 2 5 2 Local PC
21. AM et The provides great flexibility for routing functions to rear i Additional Flash p 9 d 9 Please refer to Configuration for more information MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 Configuration Options Configuration Options CPU Several PowerQUICC III types with different clock frequencies MPC8548 or MPC8548E 1 GHz 1 2 GHz 1 33 GHz or 1 5 GHz MPC8543 or MPC8543E 800 MHz or 1 GHz Memory System RAM 512MB 1 GB or 2 GB With or without ECC Flash Disk 2 GB 4 6 GB 8 GB 12 GB or 16 GB FRAM OKBor 128 KB Additional SDRAM OMB or 32MB With optional FPGA See Interface Configuration Matrix showing possible combinations VGA at front with optional FPGA Ethernet Up to two channels at front Up to three channels at rear Only two channels total with MPC8543 SATA Up to two channels at rear Up to 64 user defined I O lines With optional FPGA see below Reduces number of Ethernet S ATA channels FPGA The optional onboard FPGA offers the possibility to implement customized I O functionality e FPGA Altera Arria GX AGX35C 33 520 logic elements 1 348 416 total memory bits Connected to CPU via PCI Express x1 link Connection Available pin count 64 pins Functions available via rear I O J2 connector Please note that the FPGA expands the board s width by 4 HP to 12 HP See also F
22. ENMON M Module M Modules SA Adapter SA Adapters UBox USM and the MBIOS logo are trademarks of MEN Mikro Elektronik GmbH is a registered trademark of MEN Micro Inc and SBS Technologies Inc MEN Mikro Elektronik ESMexpress MIPIOS and the MEN logo are registered trademarks of MEN Mikro Elektronik GmbH Altera amp Arria Avalon Cyclone Nios and Quartus are registered trademarks of Altera Corp Freescale and PowerQUICC are trademarks of Freescale Semiconductor Inc PowerPC is a registered trademark of IBM Corp Green Hills amp and INTEGRITY QO are registered trademarks of Green Hills Software Inc OS 9 OS 9000 and SoftStax amp are registered trademarks of RadiSys Microware Communications Software Division Inc FasTrak and Hawk are trademarks of RadiSys Microware Communications Software Division Inc RadiSys is a registered trademark of RadiSys Corporation PCI Express and PCIe are registered trademarks of PCI SIG QNX is a registered trademark of QNX Ltd Tornado and VxWorks are registered trademarks of Wind River Systems Inc All other products or services mentioned in this publication are identified by the trademarks service marks or product names as designated by the companies who market those products The trademarks and registered trademarks are held by the companies producing them Inquiries concerning such trademarks should be made directly to those compa
23. Ethernet connector 1 3 2 6 4 7 5 8 Checks Connection between CPU and LAN controller Connection between LAN controller and PHY Connection between PHY and physical connector Does not check nterrupt line All LAN speeds 3 5 2 SDRAM SRAM and FRAM Table 12 MENMON Diagnostic tests SDRAM SRAM and FRAM Test Name Description Availability SDRAM Quick SDRAM connection test Always Groups POST AUTO SDRAM X Full SDRAM test Always Groups NONAUTO ENDLESS SRAM Quick SRAM test F50P is known to have Groups POST AUTO SRAM SRAM X Full SRAM test Groups NONAUTO ENDLESS Quick test F50P is known to have Groups POST AUTO FRAM FRAM X Full FRAM test Groups NONAUTO ENDLESS 44 20F050P00 E1 2009 11 20 MENMON 3 5 2 1 Quick RAM Test This quick test checks most of the connections to the RAM chips but does not test all RAM cells It executes very quickly within milliseconds This test is non destructive saves restores original RAM content Checks address lines data lines Byte enable signals ndirectly checks clock and other control signals Does not check SDRAM cells Burst mode 3 5 2 2 Extended RAM Test This full featured memory test allows to test all RAM cells Depending on the size of the SDRAM this test can take up to one minute It tests 8 16 or 32 bit access each with random pattern and single
24. I Buses Two local PCI buses are controlled by the integrated host to PCI bridge One is connected to the PCI to USB bridge and runs at 33 MHz The other connects the PCI to SATA bridge and operates at 66 MHz Board versions with the MPC8543 processor only have one local PCI bus operating at 33 MHz The I O voltage is fixed to 3 3V The data width is 32 bits 2 5 3 Local PCI Express Connections A PCI Express x1 link connects the PowerPC processor with the CompactPCI bus via a PCIe to PCI bridge and with the optional FPGA MEN Mikro Elektronik GmbH 23 20F050P00 E1 2009 11 20 Functional Description 2 6 Memory 2 6 1 DRAM System Memory The board provides up to 2 GB onboard soldered DDR2 double data rate SDRAM on nine memory components incl ECC The memory bus is 72 bits wide and operates at up to 300 MHz physical depending on the processor type Depending on the board version SDRAM may have ECC error correcting code ECC memory provides greater data accuracy and system uptime by protecting against soft errors in computer memory 2 6 2 FRAM The board has up to 128 KB non volatile FRAM memory connected to the local bus of the CPU The FRAM does not need a back up voltage for data retention 2 6 3 SRAM The board has up to 2 MB non volatile SRAM memory connected to the local bus of the CPU For data retention during power off the SRAM is supplied with a back up voltage by a GoldCap 2 6 4 Boot Flash The
25. Read only MPC8548E cpuclkhz CPU core clock frequency decimal Hz Yes Read only dlun MENMON device unit number that Yes Read only MENMON used as the boot device hexadecimal flashO Flash size decimal kilobytes Yes Read only FRAM size decimal kilobytes Yes Read only immr Physical address of CCSR register Yes Read only block memo RAM size decimal kilobytes Yes Read only mem1 Size of SRAM decimal kilobytes Yes Read only memclkhz Memory clock frequency decimal Hz Yes Read only MEN Mikro ElektronikGmbH ene eee 5 1 20F050P00 E1 2009 11 20 MENMON 20F050P00 E1 2009 11 20 Parameter X Parameter User alias Description Standard Default String Access mm Info whether primary or secondary Yes Read only MENMON has been used for booting either smm or pmm mmst Status of diagnostic tests as a string Yes Read only 0 1 2 MAC address of Ethernet interface Yes Read only 0 n Format e g 00112233445566 Set automatically according to serial number of the board pciclkhz PCI bus clock frequency system input Yes Read only clock decimal Hz rststat Reset status code as a string see Yes Read only Chapter 3 6 4 4 Reset Cause Param eter rststat on page 55 usbdp USB boot device path in format Yes Read only bus 1st port no last port no e g 00 gt 02 gt 01 for USB bus 0 port no 1 2 port no
26. Works start up script Empty string No Read write tn netname Host name of this machine Empty string No Read write unitnum VxWorks boot device unit number deci 0 No Read write mal 3 6 4 4 Reset Cause Parameter rsistat The following rststat values are possible When MENMON starts up it determines the reset cause and sets system parameter rststat accordingly Table 26 MENMON Reset causes through system parameter rststat rststat Value Description cbrst Board was reset using the reset button pwon Power On swrst Board was reset by software by means of the board s reset con troller wdog Board was reset by watchdog timer unit MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 MENMON 3 7 MENMON Commands The following table gives all MENMON commands that can be entered on the F50P MENMON prompt You can call this list also using the H command Table 27 MENMON Command reference Command Description lt reg gt val Display modify registers in debugger model ACT lt addr gt lt size gt Execute a HWACT script ARP Dump network stack ARP table B DC no lt addr gt Set display clear breakpoints BIOS_DBG masks net cons Set MENMON BIOS or network debug level lt clun gt set debug console BO lt addr gt lt opts gt Call OS bootstrapper
27. ability rating of 94V 0 by UL recognized manu facturers MEN Mikro Elektronik GmbH 5 20F050P00 E1 2009 11 20 Technical Data EMC Tested according to EN 55022 radio disturbance IEC1000 4 2 ESD and IEC1000 4 4 burst BIOS MENMONTM Software Support Linux VxWorks QNX on request support of the FPU is currently not provided by QNX INTEGRITY 9 Green Hills Software OS 9 on request T e For more information on supported operating system versions and drivers see online data sheet MEN Mikro Elektronik GmbH 6 20F050P00 E1 2009 11 20 Block Diagram Block Diagram System Boot SDRAM EE FRAM SRAM DDR2 EEPRON renin 2C l U l i Rear I O connector PowerPC MPC8548 or ER I i Options MPC854 eme O0 000Base TI oR Ethemet A 10 100 1000Base T R Ethemet R only with 0 1 2 3 10 100 1000Base T 14 MPC8548 Ethernet 7 USB UART o USB client SATA 4 and or PCI to USB o mM up to 64 user defined I O 5 ports ER from FPGA N MPC8543 i 8548 SCR 1 ME 5 5 zu ple amp ENSE VGA with optional _ ES a 9 FPGA 1 FPGA i option adds 4 HP 5 up to 64 user lines up to 64 B m tr EN mmm an e Teen REN ee RE TIP PS Option Busless SDR
28. are printed in italics bold Bold type is used for emphasis monospace A monospaced font type is used for hexadecimal numbers listings C function descriptions or wherever appropriate Hexadecimal numbers are preceded by Ox hyperlink Hyperlinks are printed in blue color The globe will show you where hyperlinks lead directly to the Internet so you can look for the latest information online IRQ Signal names followed by or preceded by a slash indicate that this signal is either active low or that it becomes active at a falling edge in out Signal directions in signal mnemonics tables generally refer to the corresponding board or component in meaning to the board or component out meaning coming from it Vertical lines on the outer margin signal technical changes to the previous issue of the document MEN Mikro Elektronik GmbH 11 20F050P00 E1 2009 11 20 About this Document Legal Information MEN Mikro Elektronik reserves the right to make changes without further notice to any products herein MEN makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does MEN assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters in
29. arge ESD can damage components To protect the board and other components against damage from static electricity you should follow some precautions whenever you work on your computer Power down and unplug your computer system when working on the inside Hold components by the edges and try not to touch the IC chips leads or cir cuitry Use a grounded wrist strap before handling computer components Place components on a grounded antistatic pad or on the bag that came with the component whenever the components are separated from the system Store the board only in its original ESD protected packaging Retain the original packaging in case you need to return the board to MEN for repair MEN Mikro Elektronik GmbH 10 20F050P00 E1 2009 11 20 About this Document About this Document AN This user manual describes the hardware functions of the board connection of peripheral devices and integration into a system It also provides additional information for special applications and configurations of the board The manual does not include detailed information on individual components data sheets etc A list of literature is given in the appendix History Issue Comments Date E1 First issue 2009 11 20 Conventions This sign marks important notes or warnings concerning proper functionality of the product described in this document You should read them in any case italics Folder file and function names
30. ase 5 standards Since it is also cheaper it is the preferable solution for cost sensitive applications Cables in the 10Base T system connect with RJ45 connectors A star topology is common with 12 or more computers connected directly to a hub or concentrator The 10Base T system operates at 10 Mbits s and uses baseband transmission methods MEN Mikro Elektronik GmbH 28 20F050P00 E1 2009 11 20 Functional Description 2 9 5 100Base T The 100Base T networking standard supports data transfer rates up to 100 Mbits s 100Base T is actually based on the older Ethernet standard Because it is 10 times faster than Ethernet it is often referred to as Fast Ethernet Officially the 100Base T standard is IEEE 802 3u There are several different cabling schemes that can be used with 100Base T e g 100Base TX with two pairs of high quality twisted pair wires 2 9 6 1000Base T 1000Base T is a specification for Gigabit Ethernet over copper wire IEEE 802 3ab The standard defines 1 Gbit s data transfer over distances of up to 100 meters using four pairs of CAT 5 balanced copper cabling and a 5 level coding scheme Because many companies already use CAT 5 cabling 1000Base T can be easily implemented Other 1000Base T benefits include compatibility with existing network protocols i e IP IPX AppleTalk existing applications Network Operating Systems network management platforms and applications MEN Mikro Elektronik GmbH 29
31. board has 16 MB of onboard Flash It is controlled by the CPU Flash memory contains the boot software for the MENMON operating system bootstrapper and application software The MENMON sectors are software protected against illegal write transactions through a password in the serial download function of MENMON cf Chapter 3 4 1 Update via the Serial Console using SERDL on page 41 2 6 5 Solid State Flash Disk The board includes up to 16 GB soldered NAND Flash disk A solid state disk SSD is a data storage device that uses solid state memory to store persistent data An SSD behaves like a conventional hard disk drive On F50P it has a PATA interface connected to a SATA to PATA bridge and controlled by one SATA channel See also Chapter 2 7 Mass Storage Serial ATA SATA SSD on page 25 With no moving parts a solid state disk is more robust effectively eliminating the risk of mechanical failure and usually enjoys reduced seek time and latency by removing mechanical delays associated with a conventional hard disk drive MEN Mikro Elektronik GmbH 24 20F050P00 E1 2009 11 20 Functional Description 2 7 Mass Storage Serial ATA SATA SSD The F50P provides three serial ATA channels through a PCI to SATA converter that is connected to the PowerPC processor via a dedicated 66 MHz PCI bus On board versions with the MPC8543 processor PCI to S ATA shares one 33 MHz PCI bus with PCI to USB The SATA interfaces support 1 5 Gbi
32. cluding Typicals must be validated for each customer application by customer s technical experts MEN does not convey any license under its patent rights nor the rights of others Unless agreed otherwise MEN products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the MEN product could create a situation where personal injury or death may occur Should Buyer purchase or use MEN products for any such unintended or unauthorized application Buyer shall indemnify and hold MEN and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that MEN was negligent regarding the design or manufacture of the part Unless agreed otherwise the products of MEN Mikro Elektronik are not suited for use in nuclear reactors or for application in medical appliances used for therapeutical purposes Application of MEN products in such plants is only possible after the user has precisely specified the operation environment and after MEN Mikro Elektronik has consequently adapted and released the product ESM ESMini MDIS MDIS4 M
33. d into System 19 1 3 Installing Operating System Software 20 1 4 Installing Driver Software 20 2 Functional Description esee e rh o 21 24 Power SUPPLY 144025 oaa 21 2 2 Board SUPETVISION 21 2 5 Reak Mime pi rd ari E SE 21 24 PROCESSOP CORES Rada 27 2 4 1 E TU D I 22 2 4 3 Thermal Considerations aaa Y 22 AS BUS e uu decoro botes pem ea e xot dis 23 25 Host to PCI Bridge seme ses P pansa 23 292 Local PCI pne Ru Ex 23 2 5 3 Local PCI Bxpress Connections 23 2 0 Memory rh Ro asec 24 2 6 1 DRAM System 24 262 FRAM aa Dod Daciae aguda 24 20 9 SRAM Ebrei d obere Pd RE 24 2634 Sash opa pda e OE Eae d Sie dvd dis 24 2 6 5 Solid State Flash Disk llle 24 2 7 Mass Storage Serial SATA SSD 25 2 8 USB IMr ICES DEOR 26 2 8 1 Front Panel Connection Etus 26 2 8 2 Rear I O Connection CompactPCI PlusIO 26 2 9 Ethernet Interfa68S i oue dae tem aee
34. d of boot logo bool 0 No Read write mmstartup Start up string Empty string No Read write startup 256 chars max if useflpar 0 512 chars if useflpar 1 nobanner Disable ASCII banner on start up 0 No Read write noecc Do not use ECC even if board supports 0 No Read write it bool 0 1 3 Speed setting for Ethernet interface AUTO Yes Read write 0 3 Possible values AUTO 10HD 10FD 100HD 100FD 1000 stdis Disable POST bool 0 No Read write stdis XXX Disable POST test with name XXX 0 No Read write bool stdis ether Internal ETHERO 1 2 loopback stdis fram FRAM test stdis_sram SRAM test stdis touch Touch controller test stignfault Ignore POST failure continue boot 1 No Read write bool stwait Time in 1 10 seconds to stay at least in 30 No Read write SELFTEST state decimal 0 Continue as soon as POST has fin ished MEN Mikro Elektronik GmbH 53 20F050P00 E1 2009 11 20 MENMON reset the system after MENMON has passed control to operating system decimal in 1 10 s If 0 MENMON disables the watchdog timer before starting the operating sys tem Note The F50P watchdog supports only the following values 0 Disable watchdog timer 11 Short time out 1 12 seconds 260 Long time out 26 0 seconds Parameter Parameter User alias Description Standard Default String Access tap Telnet server TCP port d
35. e User abort or Boot failure p MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 MENMON 3 2 Interacting with MENMON To interact with MENMON you can use the following consoles UART to USB COM via UART to USB interface Touch panel TFT interface if present Telnet via network connection HTTP monpage via network connection The default setting of the COM ports is 9600 baud 8 data bits no parity and one stop bit 3 2 1 Entering the Setup Menu Command Line During normal boot you can abort the booting process in different ways during the self test depending on your console With a touch panel press the Setup button to enter the Setup Menu With a text console press the s key to enter the Setup Menu With a text console press ESC to enter the command line By default the self test is not left until 3 seconds have elapsed measured from the beginning of the self test even if the actual test has finished earlier to give the user a chance to abort booting and enter the Setup Menu You can modify the self test wait time through MENMON system parameter stwait see stwait 3 3 Configuring MENMON for Automatic Boot You can configure how MENMON boots the operating system either through the Setup Menu or through the command line In the Basic Setup Menu you can select the boot sequence for the bootable devices on the F50P The selected sequence is stored in system param
36. ecimal 1 No Read write tries Number of network tries 20 No Read write tto Minimum timeout between network 0 No Read write retries decimal in seconds u00 u15 User parameters hex 16 bits 0x0000 No Read write updcdis Disable auto update check bool 0 No Read write useflpar Store kerpar and mmstartup parame 0 No Read write ters in boot Flash rather than in EEPROM bool vmode Vesa Video Mode for graphics console 0x0101 No Read write hex wat Time after which watchdog timer shall O disabled No Read write If FRAM is implemented 2 If SRAM is implemented MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 Table 25 MENMON F50P system parameters VxWorks bootline parameters MENMON ipe Description Standard Default cca Patel s bf bootfile Boot file name 127 chars max Empty string No Read write bootdev VxWorks boot device name Empty string No Read write e netip IP address subnet mask e g Empty string No Read write 192 1 1 28 ffffff00 g netgw IP address of default gateway Empty string No Read write h nethost Host IP address used when booting Empty string No Read write over NBOOT TFTP hostname VxWorks name of boot host Empty string No Read write netaddr Access the IP address part of netip No Read write parameter netsm Access the subnet mask part of netip No Read write parameter procnum VxWorks processor number decimal 0 No Read write S Vx
37. econdary MENMON for MEN MPC8548 Family XM50 1 7 c 2007 2008 MEN Mikro Elektronik GmbH Nuremberg MENMON 2nd Edition Created 12 2008 10 45 08 PU Board XM50 03 Serial Number 4 CPU 8548 CPU MEM 1386 198 MHz HW Revision 00 00 00 396 50 Miz Sic pele x4 DDR2 SDRAM 512 MB ECC on 3 0 3 8 FRAM SRAM 128 2048 kB FLASH 16 MB Reset Cause Power On Produced Last repair Carrier Board F503 00 Rev 00 01 00 Serial 3 XXE Note Don t power off the F50P now otherwise the USB to UART interface on the host computer will be disconnected Observe the installation instructions for the respective software 1 3 Installing Operating System Software The board supports Linux VxWorks and INTEGRITY By default no operating system is installed on the board Please refer to the respective manufacturers documentation on how to install operating system software You can find any software available on MEN s website d 1 4 Installing Driver Software For a detailed description on how to install driver software please refer to the respective documentation Youcan find any driver software available for download on MEN s website MEN Mikro Elektronik GmbH 20 20F050P00 E1 2009 11 20 Functional Description 2 Functional Description The following describ
38. election 3 4 4 Automatic Update Check MENMON s automatic update check looks for some special files on an external medium connected to the first USB port USBO However the F50P implementation does not support program update here but can boot from the external medium The file that is searched for has a name stored in system parameter bf or bootfile or if this is empty BOOTFILE If this file is found it is assumed that the external medium is supposed to be booted from To allow MENMON to locate this file it must be in the root directory of a DOS FS This works on unpartitioned media or on drives with one partition MENMON does not automatically start the boot but presents the following menu to the user Detected an update capable external medium gt Ignore continue boot Boot from external medium If there is no user input for 5 seconds after the menu appears booting continues MEN Mikro Elektronik GmbH 41 20F050P00 E1 2009 11 20 MENMON 3 4 5 Updating MENMON Code gt Updates of MENMON are available for download from MEN s website MENMON s integrated Flash update functions allow you to do updates yourself However you need to take care and follow the instructions given here Otherwise you may make your board inoperable In any case read the following instructions carefully Please be aware that you do MENMON updates at your own risk After an incorrect update your CPU board may not be able t
39. es for 10 100Base T 2 9 2 Rear I O Connection All of the three Ethernet channels can alternatively be routed to the J2 rear I O connector By default no Ethernet is led to connector J2 See Chapter 2 11 Rear I O CompactPCI PlusIO on page 30 for more information and possible J2 rear I O pin assignments 2 9 3 General Ethernet is a local area network LAN protocol that uses a bus or star topology and supports data transfer rates of 100 Mbits s and more The Ethernet specification served as the basis for the IEEE 802 3 standard which specifies the physical and lower software layers Ethernet is one of the most widely implemented LAN standards Ethernet networks provide high speed data exchange in areas that require economical connection to a local communication medium carrying bursty traffic at high peak data rates A classic Ethernet system consists of a backbone cable and connecting hardware e g transceivers which links the controllers of the individual stations via transceiver transmitter receiver cables to this backbone cable and thus permits communication between the stations 2 9 4 10Base T 10Base T is one of several adaptations of the Ethernet IEEE 802 3 standard for Local Area Networks LANs The 10Base T standard also called Twisted Pair Ethernet uses a twisted pair cable with maximum lengths of 100 meters The cable is thinner and more flexible than the coaxial cable used for the 10Base 2 or 10B
40. es the individual functions of the board and their configuration on the board There is no detailed description of the individual controller chips and the CPU They can be obtained from the data sheets or data books of the semiconductor manufacturer concerned Chapter 5 1 Literature and Web Resources on page 61 2 1 Power Supply The board is supplied via CompactPCI connector J1 with 5 V 43 3 V and 12 V All other required voltages are generated on the board The F50P may also be operated as a stand alone card without the CompactPCI bus In this case power is also supplied via the J1 connector Three voltages are needed 5 V 43 3 V and 12 V 2 2 Board Supervision The board features a temperature sensor and voltage monitor A voltage monitor supervises all used voltages and holds the CPU in reset condition until all supply voltages are within their nominal values In addition the board contains a PLD watchdog that must be triggered After configuration the CPU serves the PLD watchdog The watchdog timeout is automatically set to 1 12 s after the first trigger pulse by the CPU The watchdog can be enabled or disabled through MENMON and can be triggered by a software application This function is normally supported by the board support package see BSP documentation 2 3 Real Time Clock The board includes an 8581 real time clock Interrupt generation of the RTC is not supported For data retention during power off the RTC i
41. ests RTC Test Name Description Availability RTC Quick presence test of RTC Always Groups POST AUTO RTC X Extended test of RTC Always Groups NONAUTO ENDLESS 3 5 6 1 RTC Test This is a quick presence test of the real time clock RTC and is executed on POST Checks Presence of RTC PC access Does not check If RTC is running RTC backup voltage 3 5 6 2 Extended RTC Test Checks Presence e g PC access e RTC is running Does not check RTC backup voltage MEN Mikro Elektronik GmbH 47 20F050P00 E1 2009 11 20 3 6 3 6 1 Consoles MENMON Configuration and Organization MENMON You can select the active consoles by means of system parameters con0 con3 and configure the console through parameters ecl gcon hdp and tdp MENMON commands CONS xxx also give access to the console settings see Chapter 3 7 MENMON Commands page 56 Table 17 MENMON System parameters for console selection and configuration Parameter alias Description Default User Access cbr baud Baud rate of all UART consoles decimal default 9600 baud 8n1 9600 Read write cono con3 CLUN of console 0 3 CLUN 0 x00 disable CLUN 0xFF Autoselect next avail able console conO is implicitly the debug console cono 08 UART to USB COM cont 00 none con2 00 none con3 00 none Read write ecl CLUN of attached network inter face hex CLUN 0x00
42. eter mmstartup as a string of MENMON commands For example if the user selects Int CF Ether None the mmstartup string will be set to DBOOT 0 NBOOT TFTP You can view and modify this string directly using the Expert Setup Menu option Startup string or through the command line command EE MMSTARTUP See also MENMON 2nd Edition User Manual for further details MEN Mikro Elektronik GmbH 40 20F050P00 E1 2009 11 20 MENMON 3 4 Updating Boot Flash 3 4 1 Update via the Serial Console using SERDL You can use command SERDL to update program data using the serial console The following table shows the F50P locations Table 10 MENMON Program update files and locations File Name Password for Extension Typical File Name SERDL Location SMM 14XM50 00 01 02 5 MENMON Secondary MENMON Fxxx MYFILE F000 Starting at sector xxx in boot Flash Exx Starting at byte xx in EEPROM 3 4 2 Update from Network using NDL You can use the network download command NDL to download the update files from a TFTP server in network The file name extensions locations and passwords are the same as for the SERDL command 3 4 3 Update via Program Update Menu MENMON scans an external medium connected to the first USB port USBO for files named 4XM50 SMM The Program Update Menu will then give a list of all files on this medium conforming with this name pattern for s
43. igure 1 Map of the board front panel view on page 17 Youcan find more information on our web page User I O in FPGA P x MEN Mikro Elektronik GmbH 8 20F050P00 E1 2009 11 20 Configuration Options Cooling concept 40 70 C on 8 HP with heat sink without FPGA for convection cooling e Conduction cooled variety F50C also available for 40 85 C Please note that some of these options may only be available for large volumes Please ask our sales staff for more information Interface Configuration Matrix FPGA I O pins No FPGA 29 38 47 56 33 42 51 60 37 46 55 64 Front I O No VGA VGA routed to FPGA 2 USB 2 USB 2 USB 2ETH 1ETH 2ETH E 2ETH 2 R 1ETH 2ETH Rear 1 0 2ETH 2ETH P 3ETH 2ETH 1ETH z 3ETH 2ETH 1ETH 2SATA 2SATA 2SATA 25 2SATA 2SATA 25 2SATA 1 SATA 1 SATA 1 SATA 1 SATA 4 USB 4 USB 4 USB Form factor 8 12 HP 8 12 HP 12HP The standard configuration is compatible with the PICMG 2 30 CompactPCI PluslO specification The standard configuration is highlighted in bold blue in the table For available standard configurations see online data sheet MEN Mikro Elektronik GmbH 9 20F050P00 E1 2009 11 20 Product Safety Product Safety A Electrostatic Discharge ESD Computer boards and components contain electrostatic sensitive devices Electrostatic disch
44. ilability ETHERO Ethernet 0 1 2 LAN 0 1 2 internal Always ETHER1 loopback test except ETHER with an ETHER Groups POST AUTO MPC8543 processor ETHERO X Ethernet 0 1 2 LAN 0 1 2 external Always ETHER1 X loopback test except ETHER with an ETHER2_X Groups NONAUTO ENDLESS MPC8543 processor 3 5 1 1 Ethernet Internal Loopback Test The test configures the network interface for loopback mode on PHY verifies that the interface s ROM has a good checksum verifies that the MAC address is valid not OXFFFFFF sends 10 frames with 0x400 bytes payload each verifies that frames are correctly received on the same interface If the network interface to test is the currently activated interface for the MENMON network stack the interface is detached from the network stack during test and reactivated after test Checks Connection between CPU and LAN controller Connection between LAN controller and PHY Does not check Connection between PHY and physical connector nterrupt line All LAN speeds MEN Mikro Elektronik GmbH 43 20F050P00 E1 2009 11 20 MENMON 3 5 1 2 Ethernet External Loopback Test This test is the same as the Ethernet Internal Loopback Test but requires an external loopback connector Before sending frames the link state is monitored If it is not ok within 2 seconds the test fails Note A loopback connector makes a connection between the following pins of the 8 pin
45. ion Interrupt PCI 0x00 0x00 0x1057 0 0013 PCI host bridge in MPC854X 0x10 0x1095 0x3114 SATA PCI_INTA IRQ8 PCI2 0x01 0x00 0x1057 0 0013 PCI host bridge in MPC854X 0x11 0x1033 0x0035 1st USB Controller USB0 2 PCI_INTB IRQ9 0x12 0x00E0 2nd USB Controller USB3 4 5 PCI INTC IRQ10 PCle 0x02 0x00 0x1957 0x0013 PCle bridge in MPC854X 0x03 0x00 0 1208 0x0404 PCle switch for CompactPCI 0x04 0x01 Ox12D8 0x0404 bus 0x02 0x03 0x05 0x00 0x1A88 0 4045 FPGA if implemented PCle INTB IRQ 1 0x06 0x00 0 1208 110 PCle bridge CompactPCI bus MEN Mikro Elektronik GmbH 60 20F050P00 E1 2009 11 20 Appendix 5 Appendix 51 Literature and Web Resources e F50P data sheet with up to date information and documentation www men de products 02F050P html 5 1 1 PowerPC MPC8548 MPC8548E PowerQUICC II Integrated Processor Family Reference Manual MPC8548ERM 2007 Freescale Semiconductor Inc www freescale com 5 1 2 SATA e Serial ATA International Organization SATA IO www serialata org 5 1 3 USB USB Universal Serial Bus Specification Revision 1 0 1996 Compaq Digital Equip ment Corporation IBM PC Company Intel Microsoft NEC Northern Telecom www usb org 5 1 4 Ethernet ANSI IEEE 802 3 1996 Information Technology Telecommunications and Information Exchange between Systems Local and Metropolitan Area Net wor
46. ks Specific Requirements Part 3 Carrier Sense Multiple Access with Col lision Detection CSMA CD Access Method and Physical Layer Specifications 1996 IEEE www ieee org Charles Spurgeon s Ethernet Web Site Extensive information about Ethernet IEEE 802 3 local area network LAN technology www ethermanage com ethernet InterOperability Laboratory University of New Hampshire This page covers general Ethernet technology www iol unh edu services testing ethernet training 5 1 5 CompactPCl e CompactPCI Specification PICMG 2 0 R3 0 1999 PCI Industrial Computers Manufacturers Group PICMG www picmg org PCI Local Bus Specification Revision 2 2 1995 PCI Special Interest Group P O Box 14070 Portland OR 97214 USA www pcisig com MEN Mikro Elektronik GmbH 61 20F050P00 E1 2009 11 20 Appendix 5 1 6 CompactPCI PluslO CompactPCI PlusIO Specification PICMG 2 30 R1 0 2009 PCI Industrial Computers Manufacturers Group PICMG www picmg org Introduction to CompactPCI PlusIO on Wikipedia en wikipedia org wiki CompactPCI_PlusIO 5 2 Finding out the Board s Article Number Revision and Serial Number MEN user documentation may describe several different models and or hardware revisions of the F50P You can find information on the article number the board revision and the serial number on two labels attached to the board Article number Gives the board s family and model This is also MEN s order i
47. ktronik GmbH 20F050P00 E1 2009 11 20 Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 Map of the board front panel view 17 Map of the board top 18 MENMON State diagram Degraded Mode Full Mode 38 MENMON State diagram main state 39 Label giving the board s article number revision and serial number 62 Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 MEN Mikro Elektronik GmbH 20F050P00 E1 2009 11 20 Processor core options on u uu ti toe dex ex e pes dpa ea 22 Pin assignment of USB front panel connectors 26 Signal mnemonics of USB front panel connectors 26 Pin assignment and status LEDs of Ethernet front panel connectors 27 Signal mnemonics of Ethernet front panel connectors 28 Pin assignment of rear I O connector J2 standard board version PICMG 2 30 PlusIO compatible rm e 32 Pin assignment of rear I O connector J2 I O o
48. n assignment of USB front panel connectors 1 45V 2 USB D 3 USB 4 GND Table 3 Signal mnemonics of USB front panel connectors Signal Direction Function 5V USB 0 out 5 V power supply USB 1 in Output for host port USB 0 Input for client port USB 1 GND Digital ground USB_D USB_D in out USB lines differential pair 2 8 2 Rear I O Connection CompactPCI PluslO Up to four USB interfaces are accessible via rear I O in compliance with the PICMG 2 30 CompactPCI PlusIO standard See Chapter 2 11 Rear I O CompactPCI PlusIO on page 30 for J2 rear I O pin assignments MEN Mikro Elektronik GmbH 26 20F050P00 E1 2009 11 20 Functional Description 2 9 Ethernet Interfaces The F50P has up to three Ethernet interfaces controlled by the CPU AII channels support up to 1000 Mbits s and full duplex operation LAN 0 and LAN 1 are accessible at the front panel while LAN 2 is available as an option at the J2 rear I O connector As an option even all three Ethernet channels can be made available via J2 rear I O The rear Ethernet interfaces are not compliant with PICMG 2 30 CompactPCI PlusIO Please note that LAN 2 is not available on board versions with the MPC8543 processor The unique MAC address is set at the factory and should not be changed Any attempt to change this address may create node or bus contention and thereby render the board inoperable The MAC addresses
49. ng number To be complete it must have 9 characters Revision number Gives the hardware revision of the board Serial number Unique identification assigned during production If you need support you should communicate these numbers to MEN Figure 5 Label giving the board s article number revision and serial number Complete article number Article No O 02FO50P00 I Serial No 000001 Serial number man Rev 00 00 00 Revision number MEN Mikro Elektronik GmbH 62 20F050P00 E1 2009 11 20
50. nies All other brand or product names are trademarks or registered trademarks of their respective holders Information in this document has been carefully checked and is believed to be accurate as of the date of publication however no responsibility is assumed for inaccuracies MEN Mikro Elektronik accepts no liability for consequential or incidental damages arising from the use of its products and reserves the right to make changes on the products herein without notice to improve reliability function or design MEN Mikro Elektronik does not assume any liability arising out of the application or use of the products described in this document Copyright 2009 MEN Mikro Elektronik GmbH All rights reserved s Please recycle France USA MEN Mikro Elektronik GmbH MEN Mikro Elektronik SA MEN Micro Inc Neuwieder Stra e 5 7 18 rue Ren Cassin 24 North Main Street 90411 Nuremberg ZA de la Ch telaine Ambler PA 19002 Phone 49 911 99 33 5 0 74240 Gaillard Phone 215 542 9575 Fax 49 911 99 33 5 901 E mail info men de www men de Phone 33 0 450 955 312 Fax 33 0 450 955 211 E mail info men france fr www men france fr Fax 215 542 9577 E mail sales menmicro com www menmicro com MEN Mikro Elektronik GmbH 12 20F050P00 E1 2009 11 20 Contents Contents T Getting Started u u ans is si PEIUS dle 17 Ll Maps Or the Boatd 4232922539 Sages 17 1 2 Integrating the Boar
51. ntrollers binary I O etc for the needs of the individual application in an extremely flexible way Before boot up of the system the FPGA is loaded from boot Flash Updates of the FPGA contents can be made inside the boot Flash during operation If the FPGA is assembled the card needs an extra 4 HP in front panel space Equipped with a PCI bridge chip the F50P offers a full CompactPCI interface system slot functionality for reliable system expansion Apart from that the F50P can also be used as a busless stand alone board with power supply from the backplane Being designed for operation in a conduction or convection cooled environment the F50P provides flexibility also in its cooling concept Its firmly plugged on CPU module is embedded in a covered frame This ensures EMC protection and allows efficient conductive cooling for the F50C model which is also available by standard For air cooling the F50P version comes with a tailor made heat sink on top of the cover requiring an 8 HP front panel for an extended temperature range of 40 to 70 C The soldered components on the F50P withstand shock and vibration and the board design is optimized for conformal coating The F50P comes with MENMON support This firmware BIOS can be used for bootstrapping operating systems from disk Flash or network for hardware testing or for debugging applications without running any operating system MEN Mikro Elektronik GmbH 2 20F050P00 E1
52. o boot Do the following to update MENMON Unzip the downloaded file e g 14xm50 00_01_02 zip into a temporary direc tory Power on your F50P Connect a terminal emulation program with the UART to USB port of your F50P and set the terminal emulation program to 9600 baud 8 data bits 1 stop bit no parity no handshaking if you haven t changed the target baud rate on your own Reset the F50P by pressing the reset button or through software e g reboot command under VxWorks Press ESC immediately after resetting the F50P In your terminal emulation program you should see the MenMon gt prompt Enter SERDL MENMON to update the secondary MENMON You should now see a C character appear every 3 seconds In your terminal emulation program start a YModem download of file 14xm50 00 01 02 smm for example with Windows Hyperterm select Trans fer gt Send File with protocol YModem When the download is completed reset F50P 1 You can change the baud rate at runtime using command cons baud See Table 27 MENMON Command reference page 56 If you want to accelerate file transfer you can select a higher baud rate in MENMON and then set the terminal emulation program accordingly MEN Mikro Elektronik GmbH 42 20F050P00 E1 2009 11 20 MENMON 3 5 Diagnostic Tests 3 5 1 Ethernet Table 11 MENMON Diagnostic tests Ethernet Test Name Description Ava
53. oard status messages If the onboard FPGA is implemented the LED lights up as soon as the FPGA was initialized If no FPGA is implemented on the board the LED has no function MEN Mikro Elektronik GmbH 36 20F050P00 E1 2009 11 20 MENMON 3 MENMON 3 1 General MENMON is the CPU board firmware that is invoked when the system is powered on The basic tasks of MENMON are Initialize the CPU and its peripherals PCI PCle auto configuration Perform self test Provide debug diagnostic features on MENMON command line Interaction with the user via touch panel TFT display if supported through FPGA Boot operating system Update firmware or operating system The following description only includes board specific features For a general description and in depth details on MENMON please refer to the 2nd Edition User Manual MEN Mikro Elektronik GmbH 37 20F050P00 E1 2009 11 20 3 1 1 State Diagram MENMON Figure 3 MENMON State diagram Degraded Mode Full Mode 7 Degraded Mode s Earlylnit b x do CPU early init Check if secondary MENMON valid 27 Secondary MENMON not valid or abort pin set Y DegradedStartup E StartupPrologue N Determine clocks controller init SYSPARAM init Init early MMBIOS dev Check for D pressed Parse SO DIMM SPD Init DRAM Check for d pressed Quick DRAM test Se
54. on F50P are LAN 0 0x 00 CO 3A 87 xx xx 1 0x 00 CO 3A 88 xx xx LAN 2 0x 00 CO 3A 89 xx xx where 00 CO 3A is the MEN vendor code 87 88 and 89 are the MEN product codes and xx xx is the hexadecimal serial number of the product which depends on your board e g 00 2A for serial number 000042 PP 2 9 1 Front Panel Connection Two standard RJ45 connectors for ports LAN 0 and LAN 1 are available at the front panel There are also two status LEDs for each channel at the front panel The pin assignment corresponds to the Ethernet specification IEEE802 3 Connector types Modular 8 8 pin mounting jack according to FCC68 Mating connector Modular 8 8 pin plug according to FCC68 Table 4 Pin assignment and status LEDs of Ethernet front panel connectors 1000Base T 10 100Base T 1 BI_DA TX Blinks whenever there is 1 3 2 BI DA TX transmit or receive activity 3 BI_DB RX Ni 4 BI_DC sh 5 BI_DC I On 1000Base T link 2 4 6 BI DB RX Off 10 100Base T link e 7 BI DD x 8 BI_DD MEN Mikro Elektronik GmbH 27 20F050P00 E1 2009 11 20 Functional Description Table 5 Signal mnemonics of Ethernet front panel connectors Signal Direction Function BI_Dx in out Differential pairs of data lines for 1000Base T RX in Differential pair of receive data lines for 10 100Base T TX out Differential pair of transmit data lin
55. ptions Ethernet USB S A Oaea Pando 33 Pin assignment of rear I O connector J2 I O options maximum FPGA oi T 34 Signal mnemonics of rear I O connector 2 35 MENMON Program update files and locations 41 MENMON Diagnostic tests Ethernet 43 MENMON Diagnostic tests SDRAM SRAM and FRAM 44 MENMON Diagnostic tests EEPROM 45 MENMON Diagnostic tests 5 46 MENMON Diagnostic tests hardware monitor 46 MENMON Diagnostic tests RTC 47 MENMON System parameters for console selection and concura 21 2 2 32 D ku sq aska DUE o EUER 48 MENMON Address map full featured 49 MENMON Boot Flash memory map 49 MENMON Controller Logical Units 50 MENMON Device Logical Units DLUNS 50 MENMON F50P system parameters Autodetected parameters 51 MENMON F50P system parameters Production data 52 MENMON F50P system parameters MENMON persistent jouent cM E UE 23 MENMON F50P system parameters VxWorks bootline parameters auta Q ES chore Su sss 55 MENMON Reset causes through system parameter rststat 55 MENMON Command
56. s supplied by a GoldCap A control flag indicates a back up power fail condition In this case the contents of the RTC cannot be expected to be valid A message will be displayed on the MENMON console in this case MEN Mikro Elektronik GmbH 21 20F050P00 E1 2009 11 20 Functional Description 2 4 Processor Core The board is equipped with the MPC8548 or MPC8543 processor which includes a 32 bit PowerPC e500 core the integrated host to PCI bridge Ethernet controllers and UARTs 2 4 1 The 8548 3 family of processors integrates an e500v2 processor core built on Power Architecture technology with system logic required for networking telecommunications and wireless infrastructure applications The MPC8548 3 is a member of the PowerQUICC III family of devices that combine system level support for industry standard interfaces with processors that implement the embedded category of the Power Architecture technology General The MPC8548 3 offers a double precision floating point auxiliary processing unit APU up to 512 KB of level 2 cache up to four integrated 10 100 1Gbits s enhanced three speed Ethernet controllers with TCP IP acceleration and classification capabilities a DDR DDR2 SDRAM memory controller a programmable interrupt controller two controllers a four channel DMA controller a general purpose I O port and dual universal asynchronous receiver transmitters DUART The MPC8548 3 is available with MPC8
57. supervision and watchdog Status LED at the front Reset button MEN Mikro Elektronik GmbH 4 20F050P00 2009 11 20 Technical Data Bus e Compliance with CompactPCI Core Specification PICMG 2 0 R3 0 System slot 32 bit 32 MHz PCIeG to PCI bridge V I O 3 3V 5V tolerant Busless Operation Board can be supplied with 5 V 3 3V and 12 V from backplane all other volt ages are generated on the board Backplane J1 connector used only for power supply Electrical Specifications Supply voltage power consumption 5V 3 5 800mA approx 3 3V 3 5 350mA approx 12V 5 5 1A approx Mechanical Specifications Dimensions conforming to CompactPCI specification for 3U boards Front panel 8HP without FPGA 12HP with FPGA See also Figure 1 Map of the board front panel view on page 17 Weight 626g Environmental Specifications Temperature range operation 40 70 screened Airflow min 1 0m s Conduction cooled variety F50C also available Temperature range storage 40 85 C Relative humidity operation max 95 non condensing Relative humidity storage max 9596 non condensing Altitude 300m to 3 000m Shock 15g 11ms Bump 10g 16ms Vibration sinusoidal 1g 10 150Hz Conformal coating on request MTBF 162 822h 40 C according to IEC TR 62380 RDF 2000 Safety PCB manufactured with a flamm
58. the Board Organization of the Board To install software on the board or to develop low level software it is essential to be familiar with the board s address and interrupt organization 4 1 Memory Mappings Table 28 Memory map processor view CPU Address Range Size Description 0000 0000 End of RAM 512 1024 SDRAM 2048 MB 0x 8000 0000 DFFF FFFF 1536 MB PCle Memory Space Ox E000 0000 E7FF FFFF 128 MB Memory Space Ox E800 0000 EFFF FFFF 128 MB PCI2 Memory Space Ox F000 0000 F00F 0000 128 MB CCSR Ox F200 0000 F200 3FFF Config PLD Ox F300 0000 F301 FFFF FRAM opt Ox F400 0000 FFFF SRAM opt Ox FBOO 0000 FBFF FFFF 16 PCIe ISA Space Ox 0000 7FFF 32 KB I O Space Ox FF00 0000 FFFF FFFF 16 MB Flash Table 29 Address mapping for PCI CPU Address Range Interface Mapped to PCI Space Description Ox 8000 0000 9FFF FFFF PCIe 0x 8000 0000 9FFF FFFF PCle memory space MEM prefetchable BARs Ox A000 0000 DFFF FFFF PCIe Ox A000 0000 DFFF FFFF PCle memory space MEM non prefetchable BARs Ox E000 0000 E7FF FFFF PCI E000 0000 E7FF FFFF PCI1 memory space MEM Ox E700 0000 EFFF FFFF Ox E700 0000 EFFF FFFF PCI2 memory space MEM Ox FBOO 0000 FBFE FFFF PCle 0x 0000 0000 00FE FFFF PCle ISA memory ISA Ox FBFF 8000 FBFF FFFF PCle Ox 0000 7FFF I
59. ts s One SATA channel is used for the SSD solid state Flash disk See also Chapter 2 6 5 Solid State Flash Disk on page 24 The other two SATA channels are led to the rear I O J2 connector The pin assignment is in compliance with the PICMG 2 30 CompactPCI PlusIO standard See Chapter 2 11 Rear I O CompactPCI PlusIO on page 30 for J2 rear I O pin assignments MEN Mikro Elektronik GmbH 25 20F050P00 E1 2009 11 20 Functional Description 2 8 USB Interfaces The F50P provides five USB 2 0 host ports with OHCI EHCI implementation and one USB client port One host port USB 0 and the client port UART to USB USB 1 led to the front panel Up to four host ports are available via rear on connector J2 The host ports are controlled via PCI to USB bridges from the PowerPC processor while the client port is driven by a UART to USB converter The UART to USB interface supports data rates up to 115 2 kbits s It has no handshake lines In connection with USB to UART driver software it can be used as a COM interface and is supported by MENMON as a console device 2 8 1 Front Panel Connection One host port USB 0 and the client port UART to USB USB 1 are accessible at the front panel Connector types 4 pin USB Series A receptacle according to Universal Serial Bus Specification Revision 1 0 Mating connector 4 pin USB Series A plug according to Universal Serial Bus Specification Revi sion 1 0 Table 2 Pi
60. ue a d e ERR 27 2 9 1 Front Panel Connection 27 292 Rear VO Connection sssr u oper Re RR RP 28 210 9 Generals tia asd ed daria pida 28 2 9 4 oed oen gota dot par d 28 2 9 5 TOOBSSE Roi ERE DP ERES 29 290 I000B3Se T iusso ease GA pick a ues 29 2 10 CompactPCI Interface iss eis Rr m ee 30 2 11 Rear UO CompactPCl PluslO i n u RE RR DUO PRA 30 2 11 1 User Defined I O from Onboard FPGA 31 2 11 2 Standard and Possible Pin Assignments 32 2 12 Reset Button and Status LED 0000 nes 36 MEN Mikro Elektronik GmbH 13 20F050P00 E1 2009 11 20 Contents 3 MENNION rasa RO 37 General etes 37 2l State oro eg dades p 38 3 2 Interacting with MENMON 40 3 2 1 Entering the Setup Menu Command Line 40 3 3 Configuring MENMON for Automatic Boot 40 24 Updating Boot Mash I b toad sent xr 41 3 4 Update via the Serial Console using SERDL 41 3 4 2 Update from Network using NDL 41 3 4 3 Update via Program Update 41 344 Automatic Update Check 41 3 4 5 Updating MENMON
61. ystem M Remove all boards from the CompactPCI system Insert the F50P into the system slot of your CompactPCI system making sure that the CompactPCI connectors are properly aligned Note The system slot of every CompactPCI system is marked by a triangle on the backplane and or at the front panel It also has red guide rails You should generally use a host computer for first operation typically under Linux or Windows Install a USB to UART driver on your host computer You can use a Windows driver provided by MEN article number 13T005 70 third party or go to the FTDI web site www ftdichip com FTDrivers htm and download a driver there Connect your host computer to the front panel USB 1 port of the F50P UART to USB interface To do this you need a suitable USB cable type A to A Power up the system Start up a terminal program on your host computer e g HyperTerm under Win dows and open a terminal connection Set your terminal connection to the following protocol 9600 baud data transmission rate 8 data bits 1 stop bit No parity MEN Mikro Elektronik GmbH 19 20F050P00 E1 2009 11 20 Getting Started When the terminal connection is made press Enter Now you can use the MEN MON BIOS firmware see detailed description in Chapter 3 MENMON on page 37 If you enter command LOGO on the MENMON prompt the terminal dis plays a message similar to the following S
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