ALExIS User Guide (3/13)
Contents
1. JEROFLEX Aeroflex Leon Experimenter s Interface System ALEXIS User Guide March 25 2013 Aeroflex Systems Group 4350 Centennial Blvd Colorado Springs CO 80907 Table 1 Specification Revision History Approved Change Summary hode NNN 4 1 1 DCO ON 4 1 2 ACTOS ALE IS ON SS 4 1 3 AMEXIS Chassis Major Compole ils cq odas bx degebat a a a a 5 1 4 Ferrer 6 INTOM LQ EE EE tA ad 7 2 1 NN NT 7 2 2 LEON SPR SPSS 8 20 MS A O MM ME M AN M E D Rede 8 2 4 AB sale a at en Att 8 2 5 opace WIFe MIMS NT 9 2 6 ANNA A ee 9 2 7 Mer ol sii 9 2 8 USB General PUrDose LE Ai i MD 9 2 9 LEON General Purpose D Oo re 10 2 10 PS LEON SDE DUS POR ee NS 10 2 11 ENERE EE NER EA 11 2 12 ANA Re 12 2 13 Clock Su EE aida do kt e 12 2 14 EP 12 2 13 AnalogstosDieital COHVOFUeEuo a a a a a a 13 2 16 MESEN 14 2 17 A en 14 2 18 AHB Memo Mappila av 15 Mezzanine NET vrede 18 3 1 XILINX EX100 and Mezzanine CAM as 18 SEN NNN PP 20 4 1 Tola 20 4 2 Downloading software to the target Syse 20 4 3 REEVES MO aries Ride iceoets rash N p M coil OU DEL teal cse battu tA EE 20 4 4 WW Or de NR t m i i au ease scadteateuitens 21 4 5 eee 24 Avy Triks DS 25 4 6 BO dene POT a a it 25 1 1 1 2 Introduction Scope This document describes the ALEXIS design implemented for the Aeroflex UT699 LEON3 FT pro cessor The UT7000 Top Box design is intended to familiarize users with the Aeroflex UT699 proces sor as well as allow custom expansion based on2. Typing ALExISspw01 will open grspw 1 for TX and grspw 0 for RX Below is what will be printed out when the load button is pushed on the ALEXIS touch screen with the spacewire DMK s being ran 0x80000200 0x80000300 amba init irgctrli amba init gptimer Loading lan str Loading l1850 9L f90 D0xX20000300 4 2 0x3100 200 00 are NN Configure Adapter Problem muxDevLoad failed for device entry 0 OCCAN registered occan 1 to major 10 Q8 Oxfff20000 irq 4 OCCAN registered occan 0 to major 10 8 Oxfff20100 irg 5 Adding 6773 symbols for standalone wdbCommDevinit Could not find device greth unit 0 Loading lan str wdbCommDevInit Could not find a device to use wdbConfig error configuring WDB communication interface 1711711111111111111111111111111 III TT 1711111111111111111111111 CPU Gaisler SPARC LEON Memory Size Ox7fd000 BSP version 2 0 9 Crested Jan 16 24012 09 23 13 ED amp R Policy Mode Deployed WDB Comm Type WDB COMM END WDB Agent configuration failed gt lkup ALEXIS ALEXISSpwl3 ALExISspw01 ALExISspw23 ALExISs 0x40030a98 0x40030a20 value 0 0x0 ALExISspw13 Opened grspw l for RX grspw 3 link status 0x5 grspw l link status 0x5 read 16 bytes Message data 0x22 0x41 Ox4c 0x45 0x78 0x49 0x53 Ox4d Ox4f 0x0 ALEXIS SPW DEMO value 0 0x0 gt ALExISspw02 Opened grspw 2 Opened grspw 0 for RX I x a
3. The rtems shell demo that is loaded into PROM and then loaded into SRAM the load button is pushed on the ALEXIS touch screen To view the shell window connect to the UART mini USB Port on ALEXIS to a PC with a communication window running at 38400 BAUD At start up the software will initialize the drive manager and networking then print out the bus topology of the system and the PCI configurations then finally initialize the file system In the shell window help drvmgr and pci can be type to display more information about the com mands available to the user There is a user command that has been added type help user for details on the command The command spw01 will transmit from dev grspwo to dev grspwl This command creates two RTEMS tasks the transmission task is called TXSP and the receiver task is named RXSP These two tasks open the device spw0 and spw1 checks the initial configurations then sets the spacewire regis ters accordingly to what is in the system Then the tasks try and bring the link up between SpWO and SpWI Once the link is established between the ports the TXSP task will send 13 packets each one byte in length The message that is sent is ALExIS SPWO once this data is sent the receiver task will be waiting to get this data and it will be printed out to the shell window Once the message is received the tasks are deleted There is a similar tasks using dev grspw2 to dev grspw3 that command i
4. kernel window connect to the UART mini USB Port help user GAISLER LEONS3FT GAISLER AHBUART GAISLER AHBJTAG GAISLER PCIFBRG GAISLER DMACTRL GAISLER ETHMAC GAISLER SPW GAISLER SPW GAISLER SPW GAISLER SPW GAISLER FIMCIRL GAISLER APBMST GAISLER LEON3DSU GAISLER CANAHB GAISLER CANAHB GALSLER APBUARI GAISLER IROMP GALS LER GPTLMER GAIS LER_CLEGATE ESA PCIARB GAISLER GPIQ GAISLER AHBSTAT Ver 1 0 FRC dev console DEL ZULL help user commands added into shell to list commands on ALEXIS to a PC with a communication window running at 38400 BAUD The supported hardware 1s summarized in the list below for documentation about a specific core s driver please see the LEON VxWorks 6 7 Driver Manual LEON3 e MMU e FPU hardware MUL DIV and software MUL DIV support Interrupt controller e UART console terminal driver 22 e Timer unit e General Purpose I O GRGPIO e 10 100 Ethernet networking GRETH e SpaceWire GRSPW non DMA CAN 2 0 OCCAN PCI support GRPCI PCIF At start up the software will initialize the drive manager and networking then finally initialize the file system In the shell window Ikup ALEXIS this will print out the list of DMK s downloadable kernel mod ules that were added to the Kernel Image for the ALEXIS system lkup ALExIS ALExISspw13 0x40030a98 text ALExISspwOl 0x40030a20 text ALExISspw23 0x40030a48 text ALExISspw02 0x40030a70 text
5. of UT699 LEON 3FT e One 192 pin mezzanine card expansion connector e Two open 3U cPCI slots for user expansion boards 1 3 ALExIS Chassis Major Components Figure 1 ALEXIS Spare Slots Power Slice Diagram Figure 2 ALEXIS Video Controller and Single Board Computer Slice Diagram Touch Screen Display swivels to allow use from front or side of ALEXIS chassis ALLxIS Figure 3 ALEXIS Video and Touch Screen Display Diagram Load Run Demo Mode Load Load RTEMs 0 S Touch Screen Load Buttons Load Load VxWorks 0 8 Load Load Linux 0 5 1 4 Reference documents e N A 2 1 Architecture Overview The UT7000 Aeroflex ALEXIS design consists of the Leon 3FTprocessor and a set of IP cores con nected through the AMBA AHB APB buses N U JTAG PHY 4x LVDS Mez LEON 3 SOC A SNE GE IEEE jA q Serial JTAG Ethernet paceWire Multi core LEON3 DSU3 Dbg Link Dbg Link MAC Links CAN 2 0 Processor AMBA AHB AMBA APB AHB Memory AHB APB Controller Controller Bridge UART IrqCtrl I O port fo mum A KER a eee ee ee eee eee ERE ES gt el 32 bits memory bus 16 bit NVMEM SRAM SDRAM RS422 WDOG 6 bit I O port Figure 4 LEON3 SOC Block Diagram The design is centered around the AMBA Advanced High Speed bus AHB to which the LEON 3 processor and other high bandwidth devices are connected External memory is accessed through a combined PROM IO SRAM SDRAM memory controller The o
6. ANIRX gt CAN2RX gt 4 Q5H090 lt CANITX lt CAN2TX QSH090 i2 5V 19 4 1 4 2 4 3 20 Software development Tool chains The LEON3 processor is supported by several software tool chains e Bare C cross compiler system BCC e RTEMS cross compiler system RCC Snapgear embedded linux e eCos real time kernel e VxWorks 6 5 6 7 e ThreadX e Nucleus All these tool chains and associated documentation can be downloaded from www gaisler com Downloading software to the target system LEON3 has an on chip debug support unit DSU which greatly simplifies the debugging of software on a target system The DSU provides full access to all processor registers and system memory and also includes instruction and data trace buffers Downloading and debugging of software 1s done using the GRMON debug monitor a tool that runs on the host computer and communicates with the target through either serial or JTAG interfaces Please refer to the GRMON User s Manual for a description of the GRMON operations RTEMS demo The RTEMS tool chain RCC contains a driver for the spacewire core in the LEON3 SOC design The operation of the driver is described in the RTEMS SPARC BSP Manual A sample spacewire application is provided with the SOC design in software rtems shell The sample application is a rtems shell that can be used like any other shell Documentation on how the rtems shell works please refer to shell pdf
7. Core Mapping Once GRMON is online and the screen above displayed in the DOS window typing the info sys command will provide the AHB map and associated interrupt assignments of the UT699 s core ele ments An example system information screen is shown in Figure 8 HA 41 til Hi H2 H1 43 41 dda Hi H5 H1 H6 41 HY 41 He H1 H9 Hi AR H1 Hi Hi H2 ki H6 H1 til Hi 2 18 453 BA Hic 14 Hi6 duni ALF ALF ALF ALF H54 HAAG i4 Hi z Hic 15 Gaisler Research LEON3FT SPARC U8 Processor ver AxB ahh master H Gaisler Research AHE Debug UART ver Oxf ahb master 1 apb 66007660 320000806 haud rate 115204 ahh frequency 67 68 Gaisler Research AHB Debug JTAG TAP ver AxB ahb master 2 Gaisler Research Fast 32 bit PCI Bridge ver xD ahb master d ir ahb cBABABAB FF FABABA ahh fffHHHHH FEEZANAN apb 8HHBHdHBH S8HBHB5 HH Gaisler Research PCI AHB DMA controller tver Hxk ahb master 4 apb 8HHBH5HH 8RAHANREAN Gaisler Research GH Ethernet MAL ver xA gt ahb master 5 irq 14 apb 8HHBHeHH SHBHBF HB Deuice index deuH Gaisler Research GHSPU Spacewire Link ahh master 6 irq 16 apb 8HHBHaBHH SHBHBhHH Gaisler Research GHSPU Spacewire Link ahh master 7 irq 11 apb 8HHBHhHH SHBHBCcHH Gaisler Research GHSPU Spacewire Link ahb master 8 irg 12 apb 8HHBHcHH SHBHBdHH Gaisler Research GHSPU Spacewire
8. Link ahb master 9 irg 13 apb SABABABA G ABeBB Gaisler Research FT Memory Controller ahh HBHHBHHHH 24000000 ahh 2HHBHHBH 18000000 ahh 46606060 SHBEHBHHH apb 8HHBHHBH 8RHANIAN 32 bit prom HxHWHBHBHHH 32 bit static ram 1 16384 kbyte B 640000000 32 bit sdram 1 64 Mbyte B Ax6kB0000004 col 9 cas 2 ref 7 8 us Gaisler Research MAHE APB Bridge ver HxHB ahh 8HHBHHBH 8 R1ARHAN Gaisler Research LEONS Debug Support Unit ver fxi ahh 7HHBHHBHH abWHBHBHHH AHE trace 128 lines 32 hit hus stack pointer Hx4HFFFFFA CPUHH win 8 hubp 4 itrace 128 U8 mul div srnmu lddel 2 GRFPU icache 2 4 kbyte 32 hute line lru dcache 2 4 kbyte 16 hute line lru d Research OG CAM controller tver x1 gt ir ahb fff 20008 FFF21 00H COFES Gaisler Research Generic APB UART ver x1 gt irg z il 5 ab rn a Figure 8 ALExIS UT699 Core Information List rn MI 15 5 n F n F n F n F 215 AHB Memory Mapping The ALEXIS Development System offers the user access to 8Mbytes of Non Volatile NV memory storage This section will explain how the 4 onboard NV memories are interfaced to the Xilinx B Vir tex 4 V4 FPGA and the LEON 3FT processor These connections within the ALEXIS chassis should be noted by the user and ensure proper memory interface If when a user is developing code for the V4 connections listed in this section should not be modified Mod
9. N Core V d a 497950 I O Voltage a 97950 FE T 3 202400 VE ISRAM Core Volt 789130 LEON Core Volt 2 497950 I O Voltage 2 497950 Pda T 3 202400 v4 Cor SRAM Co LEON Co TO Volts 3 3v Bos Es Board Volt E L 1 D Im AI A 24
10. al Assignments Signal Name Signal Name Signal Name Signal Name Signal Name Signal Name Signal Name Row Z Row Row B Row C Row D Row E Row F 22 GND hd GAS GAZ GAL GAD GND 2 GND CLES IND Rsv RSV RSV GHD 20 GND CLES GHD RSV GND RSV GND 19 GND GND GND RSV RSV RSV GND 18 GND BRSVPZA18 EERSVFP2E18 BRSVP2CIS GND BESVPZEIS GND 17 SND BESVP2A17 GND PEST RECO GNT6s GND 16 GND BESVP2A16 BRSVP2B16 DEG GND BESVP2EIS GND 15 GND BRSVP2A15 GND FAL REQS SNTE GND 14 SND AD 35 AD 34 AD 33 GND 13 GND User GND MATO AD 37 12 GND AD 41 ATD 40 GND ILGHD VO AD 44 10 SND AT 47 GND 9 GND Vio AD 51 8 GND AD 54 GND 7 GND VON AD S amp 6 GHO Use Users GMD 5 GHD CIBE S VEL CIBE 4 A 4 GND Vio BRSVP2B4 CIBE 7 it GND CIBE 6 GND 3 GHD CLEA GND CNT S REOS GNT4E CNT 2 GND CLEK2 CLES SYSEN GNT 4 KEQS amp GND 1 SHD CLE1 GHD REO 1 GNT1 amp EEQ2 GHD Analog to Digital Converter The POC board implements a 16 channel A D for housekeeping and user defined applications The top six channels 11 16 monitor local board voltages Ch11 5V Ch12 3 3V Ch13 LV2 5V Ch14 Leon 2 5V Ch15 1 8V Ch16 1 2V for general health monitoring of the pertinent voltage sources used on the POC The A D channels are continuously monitored by the LX100 FPGA and the values stored in the Leon s I O space mapped starting at address 0x21000018h each A D channel occupies one section of the 32 bit data field for each address location See secti
11. application requirements Requirements The following hardware and software components are required in order to use and customize the Aer oflex UT699 ALEXIS design e PC work station running Windows XP PRO with Cygwin e Aeroflex board with JTAG programming cable e Xilinx ISE Development software WebPack or Regular Edition For new users to UT699 software development the following tools are recommended e BCC Bare C LEON Cross compiler e RCCRIEMSERG32 LEON Cross compiler system e GRMON LEON3 Target Debug Tool Set Available from Gaisler Aeroflex Aeroflex ALExIS Overview The Aeroflex ALEXIS was developed by the Systems Engineering Group at Aeroflex Colorado Springs and provides a flexible development platform for customers wanting to develop software that will work on the Aeroflex UT699 Standard Product and have a path to flight The Aeroflex UT7000 ALEXIS has the following features e An Aeroflex UT699 LEON 3 FT standard product e Xilinx Virtex 4 LX100 FPGA support FPGA allows custom unique designs to be implemented by customer without the need of hardware modification to the board e 8 Mbytes NV memory storage e 64 MB SDRAM e 16 Mbytes Fast SRAM e One USB UART interface e Two ECSS E 50 12A standard SpaceWire ports with hardware support for RMAP protocol e Two ECSS E 50 12A standard SpaceWire ports e One 10T 100 Mbit s Ethernet port e One 33MHZ 22 bit standard cPCI Interface e JTAG interface for programming and debug
12. ble 2 Modified P5 SpW connector pin out Description ES CT 1777 jum EST s mrasm mors p ws mw Oooo NOTE Do not plug in Space Wire instruments that are expecting a typical pin out as listed in sec tion 2 5 SpaceWire Links into ALExIS P5 connector DAMAGE may occur The DSU I F card should be plugged into P5 on the ALExIS Development System using the modified SpaceWire cable attached to the card The JTAG DSU on LEON is accessed through I F card The user can set logic level of the DSU Break and DSU enable signals allowing debug operations using GRMON Pro Mezzanine Board Layout XILINX TAG I F The push button switch SW2 is connected to DSU and JTAG reset The two position switch SW3 LEON DSU break and DSU enable Position I of SW3 is connected to DSUBRE and position 2 con nects to DSUEN Resistors RI and R2 are IK pull ups to 3 3V provided to hold DSUBRE and DSUEN high when positions 1 and 2 on SW3 are not engaged Ethernet An Ethernet MAC can be enabled The MAC supports 10 100 Mbit operation is half or full duplex The front panel contains one standard Ethernet RJ45 I F connector 2 12 2 13 2 14 Pin 12 CAN 2 0 Two CAN 2 0 interfaces can be enabled This interface 1s based on the CAN core from Opencores with some additional improvements The CAN interfaces are available through the mezzanine inter face connector Clock generation The UT7000 SBC implements a selectable 33MHz an
13. d 66MHz base clock set used for the cPCI 33MHz and the LEON FPGA 66MHz Further information on the clock setup and modification of frequencies is discussed later in the Board Clock section CompactPCI Interface The SBC board implements a 33MHz 32 bit cPCI standard bus interface cPCI PI Connector Signal Assignments Signal Name Signal Name Signal Name Signal Name Signal Name Signal Name Signal Name Row Z Row Row B Row C Row D Row E Row F 15 GND 5v EEC64 EN UW hilt 4 3 SV GMD 24 GND AD 1 5v MITO ADO ACE 64 GND 23 GND 5 3W AD 4 ATD 3 Sy AT 2 GND 22 GND ADI GHD 3 3W AD 6 AD 5 GND 2 GND 3 3 AD 9 ATD 8 M SEN GIBED je GND 20 GND AT 12 GND VO AD 11 AT 10 GND 19 GND 3 5V AD 15 AD 14 GHD AD 13 GMD 18 GND SERRA GND 33W PAR CEE 1 GND 17 GND 3 3 SDONE SBOR GHD PERR GND 16 GND DEV SEL GND VDO STOPH LOCK GND 15 GND 3 3 FRAME EDYA GND TED Y GND 14 XEF KEY KEY KEY KEY KEY KEY 13 XEF KEY RAY RAY RAY EET REY 12 XEF KEY REEF EEY EEY EEY EEY 11 GND AD 18 AD 17 AD 16 GHD CIBE 2 JH GMD 10 GND AD 21 GND 3 30 AD 20 ATY19 GND 9 GHD CIBE 3 IDSEL AD 23 GND AT 22 GND 8 GND AD 26 GHD MITO AD 25 AD 24 GMD 7 GND AD 30 AD 29 AD 28 GND AD 27 GND 6 GND REOQ amp GND 3 3 CLE AD 31 GND 5 GND BRSVWP1A5 BRSVPIBS RST GND OGONT GND 4 OND BESVP1Ad GND VITO INTP INTS GND 3 GND INTA INTE INTC 5v INTD GND 2 GND TCE 5v TMS TDO TDI GND 1 GND SV 12V TESTA 12V SV GHD Pin 2 15 cPCI P2 Connector Sign
14. d Linux systems The LEON port of SnapGear on the ALEXIS systems supports the MMU configuration V8 mul div instructions and the floating point unit FPU The version of the Linux kernel being used is uCLinux 2 6 21 Below is a list of supported hardware e LEONG with MMU FPU MUL DIV e Non standard page size larger that 4K Bytes e APBUART e GPTIMER e GRETH 10 100 and Gbit e GRPCI e GRETH over PCI The Linux kernel that is loaded into PROM and then loaded into SDRAM when the load button is pushed on the ALEXIS touch screen To view the kernel window connect to the UART mini USB Port on ALEXIS to a PC with a communication window running at 38400 BAUD 25 4 5 1 Linux boot Screen Once the user presses the Load Linux button on the touchscreen the ALEXIS system will load and boot the Linux kernel The expected output for the ls input command displayed in the terminal win dow is shown below qrlib apbuart 3 driver si grlib aphuart system Frequency trtval at MMIGO OxS0O000100 irg 4 is a Leon Testing fifo size for UART port 0 got 6 bytes RAMDISE driver initialized 16 RAM disks of 4096E loop 1 ed max G devices RAMDISE Compressed image found at block O WES Mounted root iromfs filesystem readonly Freeing unused kernel memory 124k freed init started BusyBox v1 8 3 2011 09 27 16 02 09 starting pid 14 tty mount mounting tmpfs on var tmp failed Invalid ifconfig socket Function no
15. e of the GRLIB plug amp play system USB General Purpose I F The internal LEON UART is connected to a standard mini USB connector through a standard USB bus transceiver The UART can be used as a general purpose serial I O port Single Board Computer Front Panel Layout Space Wire Ports LEON Debug Port Ethernet Port UART mini USB Port USER LED s 2 9 2 10 10 LEON General Purpose I O A general purpose I O port GPIO is provided in the design The port is 16 bits wide and each bit can be dynamically configured as input or output The GPIO can also generate interrupts from external devices The 16 bit GPIO port is connected to the LX100 FPGA allowing the user to define the func tion amp interface controlling each pin LEON GPIO I F to LX100 Pin out GPIOO IO L1P 10 GPIO1 IO LIN 10 GPIO2 IO L2P 10 GPIO3 IO L2N 10 GPIO4 IO L3P 10 GPIO5 IO L3N 10 GPIO6 IO L4P 10 GPIO IO LAN VREF 10 GPIO8 IO L5P 10 GPIO9 IO L5N 10 GPIO10 IO L6P 10 GPIO11 IO L6N 10 GPIO12 IO L7P 10 GPIO13 IO L7N 10 GPIO14 lO L8P CC LC 10 GPIO15 lO L8N CC LC 10 P5 LEON Debug Port The modified P5 micro DB9 connector is wired to allow the user access to the LEON JTAG Debug Support Unit DSU and the system reset momentary push button using the ALEXIS debug Interface POD supplied with the ALEXIS system In order to use the P5 interface POD the user must supply the standard XILINX programming pod and associated ribbon cable 2 11 11 Ta
16. ectors AHB status register ROMSN 1 0 OEN WRITEN IOSN MEMORY CONTROLLER RAMSN 4 0 RAMOEN 4 0 RWEN 3 0 MBEN 3 0 SDCLK SDCSN 1 0 SDRASN SDCASN SDDQMI3 0 A 27 0 D 31 0 Figure 6 PROM IO SRAM SDRAM Memory controller The AHB status register captures error responses on the AHB bus and lock the failed address and active master These values allows the software to recover from error events in the system 2 5 2 6 2 7 2 8 Space Wire links The ALEXIS design is configured with four SpaceWire links Each link is controlled separately through the APB bus and transfers received and transmitted data through DMA transfer on AHB Two of the SpaceWire links can also optionally be configured with RMAP support in hardware All four of the Space Wire Ports are connected to the front panel with micro D 9 pin connectors Space Wire Front Panel IF Pin out Silkscreen Typical Space Wire Links CHA CHD P1 P4 TxData TxData TxStrobe TxStrobe RxStrobe RxStrobe RxData RxData Timer unit The timer unit consists of a common scaler and up to 7 individual timers The timers can work in perl odical or on shot mode One of the timers can optionally be configured as a watchdog Interrupt controller The interrupt controller handles up to 15 interrupts in two priority levels The interrupt are automati cally assigned and routed to the controller through the us
17. l grspw 2 link status grspw 0 link status 0x5 read 16 bytes Message data 0x22 0x41 Ox4c 0x45 0x78 0x49 0x53 0x20 0x53 0x50 0x57 0x20 0x44 0x45 Ox4d Ox4f 0x0 ALEXIS SPW DEMO value 0 0x0 Opened grspw 0 for RX jorsow l link status 0x5 grspw 0 link status 0x5 read 16 bytes Message data 0x22 0x41 Ox4c 0x45 0x78 0x49 0x53 0x20 0x53 Ox4d 0x4f 0x0 ALEXIS SPW DEMO gt ALExISspw23 Opened grspw 3 for TX Development 5 Copyright Wind River pw02 0x40030a70 text VxWorks 6 7 KERNEL WIND version 2 12 Systems Inc 1984 2008 3 MMU BSP Processor 0 23 0x20 0x53 0x50 0x57 0x20 0x44 0x45 0x50 0x57 0x20 0x44 0x45 4 5 24 grspw 2 link status 0x5 read 16 bytes Message data 0x22 0x41 Oxdc 0x45 0x78 0x49 0x53 0x20 0x53 0x50 Ox57 0x20 0x44 0x45 xdd Ux4F 0x0 ALEXIS SPW DEMO value 0 0x0 gt grlibGrpciDev grlibGrpciDev 0x403414e0 value 1077205848 0x4034db58 X hwMemPool Dx 90 gt D VE drv name U null tyCo 0 hostpc grspw 0 grspw 1 grspw 2 MO O fb 4 grspw 3 10 occan l 10 bccan 0 LL vie 12 totsvr value 0 0x0 a Linux demo LINUX support for the LEON3 is provided through a special version of the SnapGear Embedded Linux distribution SnapGear Linux is a full source package containing kernel libraries and applica tion code for rapid development of embedde
18. n chip peripheral devices include four SpaceWire links Ethernet 10T 100 Mbit MAC dual CAN 2 0 interface serial and JTAG debug interfaces a UART interrupt controller timers and a 16 bit general purpose I O port The LEON 3 processor and associated IP cores are implemented using a fault tolerant FT architec ture The FT cores detects and removes SEU errors due to cosmic radiation and are particularly suit able for systems that operate in the space environment 2 2 2 3 2 4 LEON 3 SPARC V8 processor The ALExIS s UT699 design is based the LEON 3 SPARC V8 processor The processor core is con figured with a cache system consisting of 8Kbyte 2 way set associative Instruction and 4 Kbyte Data cache The LEON3 debug support unit DSU3 is a user port for downloading and debugging of pro grams through the serial or JTAG ports Memory interfaces 3 Port Register File Trace Buffer IEEE 754 FPU 7 Stage Co Processor Integer pipeline Debug port Debug support unit HW MUL DIV Interrupt port Interrupt controller D MMU AHB I F AMBA AHB Master 32 bit Figure 5 LEON 3 processor core block diagram The external memory is interfaced through a combined PROM IO SRAM SDRAM memory control ler core MCTRL The Aeroflex 3U ALExIS UT7000 provides 8 Mbytes of non volatile memory 64 Mbits SDRAM 16Mbytes Fast SRAM the SRAM and I O signals are available on the extension con n
19. on 4 6 LEON I O Space A D Value Register Layout Mot Used Mot Used Mot Used Mot Used Mot Used Mot Used Mot Used Mot Used 12 bit A D Value q H a Mot Used Mot Used Mot Used Mot Used Mot Used Mot Used Mot Used Mot Used 14 2 16 ALEXIS Cores The Aeroflex UT699 SBC design is partitioned into various core elements as shown in Figure 7 milinx cable Cable typerev JTAG chain UT6 9A Device ID E GRLIB build version 2564 initialising detected frequency Component LEON3FT SPARC US Processor AHB Debug UART AHE Debug JTAG TAP Fast 32 bit PCI Bridge PCI AHE DMA controller GR Ethernet MAC GRSPU Spacewire Link GRSPU Spacewire Link GHSPM Spacewire Link GHSPU Spacewire Link FT Memory Controller AHE APE Bridge LEON3 Debug Support Unit OG C N controller Generic APH UART Multi processor Interrupt Ctrl Modular Timer Unit Clock gating unit PCI Arhiter General purpose 20 port AHB status register Hx Vendor Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler Gais ler European Space Agency Gais ler Gais ler Research Research Research Research Research Research Research Research Research Research Research Research Research Research Research Research Research Research Research Research Figure 7 ALExIS UT699 Core List 2 17 AHB
20. s Spw23 Below is what should be printed out when the load button is pushed on the ALEXIS touch screen BUS TOPOLOGY DEV 0x400c1358 GRLIB AMBA PnP You can use the shell commands drvmgr and pci to find out more about the system Creating etc passwd and group with three usable accounts root pwd test pwd rtems NO PASSWORD Iype the command RTEMS SHELL 4 4 sea e se e e gt gt em pe gt gt gt gt gt gt gt gt gt DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV DEV F VxWorks demo The VxWorks BSP contains a drivers for the spacewire core in the LEON3 SOC design The opera tion of the driver is described in the Vx Works drivers manual The kernel that is stored in PROM on the ALEXIS system is compiled with gnuv8 SPARCv8 Hardware MUL DIV and compiled for a MMU The GNU GCC compiler was used because it produces faster integer and floating point code Ox400c1408 Ox400c1460 Ox400c14b8 Ox400c1510 0x400c1568 0x400c15c0 0x400c1618 0x400c1670 0x400c16c8 0x400c1720 0x400c1778 0x400c17d0 0x400c1828 0x400c18d8 0x400c1880 0x400c1930 0x400c1988 0x400c19e0 0x400c1a38 0x400c1a90 Ox400clae8 Ox400c1b40 it than DIAB The VxWorks kernel that is loaded into PROM and then loaded into SRAM when the load button is pushed on the ALEXIS touch screen To view the
21. t implementec ifconfig socket Function not implemented 36400 356400 size 1024 blocksize MDT argument socket Function not implemented socket Function not implemented starting pid 25 tty bin sh ls hin dew MAL 4 6 etc lib mnt shin trop home linuxre proc sys usr BCC demo program If the load button on the ALEXIS touch screen is pushed then a BCC demo program is loaded into SRAM This program takes the analog to digital information from the I O space on the UT699 and prints out the following voltages Ist 32 bit double word 0x21000018 1 2V V4 core power upper 16 bits and 1 8V SRAM core power Lower 16 bits MF take value seen in decimal 0 00061 to get voltage 2nd 32 bit double word 0x2100001C 2 5V LEON core power upper 16 bits and 2 5V board I O power Lower 16 bits MF take value seen in decimal 0 00061 to get voltage 3rd 32 bit double word a 0x21000020 3 3V board power upper 16 bits and 5 0V board power Lower 16 bits MF take value seen in decimal 0 00088 to get voltage for upper 16 bits 3 3V MF take value seen in decimal 0 00122 to get voltage for lower 16 bits 5 0V An example printout from the demo program and associated touchscreen button used to invoke the program are shown in Figure 9 26 Figure 9 ALEXIS Touch Screen Display and Demo Terminal Load Demo Button FB COM14 PuTTY Max 1 202310 SRAM Core xi 1 789130 LEO
22. ule decmem v ensures that the NV memory is read from and written to properly ALExIS has four 16 777 216 bit magneto resistive random access memory MRAM device organized as 16 1 048 576 words of 16 bits The LEON3 includes a 32 bit memory controller the NV memories are set up using a page configuration LEON3 Processor NV Memory Page Decode smem irsb al7 paqgel pagel idi decmem v LEON 3FT to SRAM Memory Interface ALEXIS has one UT8ER4M32 SRAM on board This SRAM is a high performance CMOS static RAM multi chip modules MCMs providing 16M Bytes of SRAM memory LEON3 Processor SRAM Memory Page Decode sramdec v Module sramdec v ensures that the MCM SRAM memorv is read from and written to properlv MCM SRAM Memory Interface ASBOD 17 18 3 Mezzanine Interface 3 1 XILINX LX100 and Mezzanine Connector The mezzanine connector provides 2 5V 3 3V and ground power through pins 181 182 186 2 5V 183 184 185 3 3V and 187 188 189 190 191 ground The Mezzanine connector interface to the LX100 is partitioned into three sections comprised of 2 5V I O s 3 3V 1 O s and the 0 2 5V A D ana log input channels the connector map pin out is as follows Mezzanine Connector Pin out Definition LX100 LX100 LX100 10119 QSHOS0 QSH090 Mezzanine Connector Pin out Definition LX100 121 123 125 127 129 131 133 135 137 139 143 145 147 151 153 37 4 R706 175 177 R O 179 C
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