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ADSP-218x DSP Instruction Set Reference

1. I specifies the I register Indirect Address Pointer ADDR Immediate jump address COND Condition ADSP 218x Instruction Set Reference 4 137 Program Flow Instructions SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e Index Register Selection Codes on page A 17 4 138 ADSP 218x Instruction Set Reference CALL SYNTAX CIF cond CALL 14 15 16 17 lt addr gt Permissible conds EQ NE GT GE LT LE NEG POS AV NOT AV AC NOTAC MV NOT MV NOT CE EXAMPLE IF AV CALL scale_down DESCRIPTION Test the optional condition and if true then perform the specified call If the condition is not true then perform a no operation Omitting the con dition performs the call unconditionally The CALL instruction is intended for calling subroutines CALL pushes the PC stack with the return address and causes program execution to continue at the effective address specified by the instruction The addressing modes available for the CALL instruc tion are direct or register indirect ADSP 218x Instruction Set Reference 4 139 Program Flow Instructions For direct addressing using an immediate address value or a label the program address is stored directly in the instruction word as a full 14 bit field For register indirect jumps the selected I register provides the address it is not post modified in this case If CALL is the
2. 4 98 ADSP 218x Instruction Set Reference SE Shifter Function 0100 ASHIFT HI 0101 ASHIFT HI OR 0110 ASHIFT LO 0111 ASHIFT LO OR Xop Shifter operand COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e Shifter Function Codes on page A 21 e X Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 99 Shifter Instructions Logical Shift SYNTAX IF cond SR SR OR LSHIFT xop HI gt LO Permissible xops Permissible conds SI AR EQ LE AC SRI MR2 NE NEG NOT AC SRO MRI GT POS MV MRO GE AV NOT MV LT NOT AV NOT CE EXAMPLES IF GE SR SR LSHIFT SI HI DESCRIPTION Test the optional condition and if true then perform the designated logi cal shift If the condition is not true then perform a no operation Omitting the condition performs the shift unconditionally The operation logically shifts the bits of the operand by the amount and direction speci fied in the shift code from the SE register Positive shift codes cause a left shift upshift and negative codes cause a right shift downshift The shift may be referenced to the upper half of the output field HI option or to the lower half LO option The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option For LSHIFT with a positive shift cod
3. ADSP 218x DSP Instruction Set Reference A 15 Opcode Mnemonics DV Divisor Codes for Slow Idle Instruction IDLE n Table A 9 Slow Idle Divisor Codes Code Divisor 0 0 0 Normal Idle instruction Divisor 0 0 0 0 Divisor 16 001 Divisor 32 010 Divisor 64 10 0 Divisor 128 FIC FI Condition Codes Table A 10 FI Condition Codes Code Description Condition 1 latched FI is 1 FLAG_IN 0 latched FI is 0 NOT FLAG IN FO Control Codes for Flag Output Pins FO FLO FL1 FL2 Table A 11 FO Condition Codes Code Description 0 0 No change 0 1 Toggle A 16 ADSP 218x DSP Instruction Set Reference Instruction Coding Table A 11 FO Condition Codes Code Description 1 0 Reset Led Set G Data Address Generator Codes Table A 12 DAG Selection Codes Code Address Generator 0 DAGI 1 DAG2 Index Register Codes Table A 13 Index Register Selection Codes Code G 0 G 1 0 0 10 14 0 1 Il I5 1 0 12 16 T T 13 17 ADSP 218x DSP Instruction Set Reference A 17 Opcode Mnemonics LP Loop Stack Pop Codes Table A 14 Loop Stack Pop Codes Code Description 0 No change 1 Pop M Modify Register Codes Table A 15 Modify Register Selection Codes Code G 0 G 1 0 0 MO M4 0 1 M1 M5 10 M2 M6 11 M3 M7
4. PD Dual Data Fetch Program Memory Destination Codes Table A 16 Program Memory Destination Codes Code Register 0 0 AYO 0 1 AY1 A 18 ADSP 218x DSP Instruction Set Reference Instruction Coding Table A 16 Program Memory Destination Codes Code Register 1 0 MY0 Tekil MY1 PP PC Stack Pop Codes Table A 17 PC Stack Pop Codes Code Description 0 No change 1 Pop REG Register Codes The following table gives the register codes for register groups RGP 0 1 2 and 3 Codes that are not assigned are reserved Table A 18 Register Selection Codes Code RGP 00 RGP 01 RGP 10 RGP 11 REGO REG1 REG2 REG3 0000 AXO I0 14 ASTAT 0001 AX1 Il I5 MSTAT 0010 MXO I2 16 SSTAT read only 0011 MX1 13 17 IMASK ADSP 218x DSP Instruction Set Reference A 19 Opcode Mnemonics Table A 18 Register Selection Codes Code RGP 00 RGP 01 RGP 10 RGP 11 REGO REG1 REG2 REG3 0100 AYO M0 M4 ICNTL 0101 AY1 M1 M5 CNTR 0110 MYO M2 MG SB 0111 MY1 M3 M7 PX 1000 SI LO L4 RXO 1001 SE L1 L5 TXO 1010 AR L2 L6 RX1 1011 MRO L3 L7 TXI 1100 MRI z IFC write only 1101 MR2 OWRCNTR write only 1110 SRO 1111 SR1 7 a S Jump Call Codes Table A 19 Jump and Call Codes Code Function 0 Jump 1
5. Xop Dreg I 4 188 ADSP 218x Instruction Set Reference Z Result register Dreg Destination register SF Shifter operation AMF ALU MAC operation Yop Y operand Xop X operand I Indirect address register M Modify register G Data Address Generator I and M registers must be from the same DAG as separated by the gray bar in the Syntax description SEE ALSO e DREG Selection Codes on page A 14 e ALU MAC Result Register Codes on page A 25 e Shifter Function Codes on page A 21 e DAG Selection Codes on page A 17 e Index Register Selection Codes on page A 17 e Modify Register Selection Codes on page A 18 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 e AME Function Codes on page A 10 ADSP 218x Instruction Set Reference 4 189 Multifunction Instructions Data and Program Memory Read SYNTAX AX0 DM 0 0 AYO PM 14 4 AX1 1 1 AY1 5 5 MXO 2 2 MYO 6 6 MX1 3 3 MY1 7 7 DESCRIPTION Perform the designated memory reads one from data memory and one from program memory Each read operation moves the contents of the memory location to the destination register For this double data fetch the destinations for data memory reads are the X registers in the ALU and the MAC and the destinations for program memory reads are the Y regis ters The addressing mode for this mem
6. If two off chip accesses are required such as the instruction fetch and one data fetch or data fetches from both program and data memory then one overhead cycle occurs In this case the program memory access occurs first followed by the data memory access If three off chip accesses are required such as the instruction fetch and data fetches from both program and data memory then two overhead cycles occur 4 192 ADSP 218x Instruction Set Reference The computation must be unconditional All ALU and MAC operations are permitted except the DIVS and DIVQ instructions The results of the computation must be written into the R register of the computational unit ALU results to AR MAC results to MR The fundamental principle governing multifunction instructions is that registers and memory are read at the beginning of the processor cycle and written at the end of the cycle The normal left to right order of clauses computation first memory reads second is intended to imply this In fact you may code this instruction with the order of clauses altered The assembler produces a warning but the results are identical at the opcode level If you turn off semantics checking in the assembler s switch the warning is not issued The same data register may be used as a source for the arithmetic opera tion and as a destination for the memory read The register supplies the value present at the beginning of the cycle and is written with the
7. Permissible registers dregs Instruction Type 6 dregs Instruction Type 7 16 bit load maximum 14 bit load AXO MXO SI SB CNTR AXI MXI SE PX OWRCNTR write only AYO MYO SRI ASTAT RXO AY1 MY1 SRO MSTAT RX1 AR MR2 IMASK TXO MRI ICNTL TX1 MRO 10 17 IFC write only MO0 M7 LO L7 EXAMPLES I0 data_buffer LO length data_buffer DESCRIPTION Move the data value specified to the destination location The data may be a constant or any symbol referenced by name or with the length operator The data value is contained in the instruction word with 16 bits for data register loads and up to 14 bits for other register loads The value is always 4 118 ADSP 218x Instruction Set Reference right justified in the destination location after the load bit 0 maps to bit 0 When a value of length less than the length of the destination is moved it is sign extended to the left to fill the destination width Note that whenever MR1 is loaded with data it is sign extended into MR2 For this instruction only the RX and TX registers may be loaded with a maximum of 14 bits of data although the registers themselves are 16 bits wide To load these registers with 16 bit data use the register to register move instruction or the data memory to register move instruction with direct addressing STATUS GENERATED No status bits affected INSTRUCTION FORMAT Load Register Immediate Instruction Type 6 23 22 21 20 19 18 17 16 15 14
8. TSTBIT n OF xop SETBIT n OF xop CLRBIT n OF xop TGLBIT n OF xop Permissible conds EQ LE AC NE NEG NOT AC GT POS MV GE AV NOT MV LT NOT AV NOTCE Permissible n values 0 LSB 0 1 2 3 4 5 6 7 EXAMPLES AF TSTBI AR TGLBI 8 9 10 11 12 13 14 15 5 OF AR 13 OF AXO The instruction will display in the debugger as AR AXO XOR 8192 which is the equivalent of the instruction AR TGLBIT 13 OF AXO DESCRIPTION Test the optional condition and if true then perform the specified bit operation If the condition is not true then perform a no operation Omit ting the condition performs the operation unconditionally These operations cannot be used in multifunction instructions These operations are defined as follows 4 46 ADSP 218x Instruction Set Reference The AS Instruction Set TSTBIT is an AND operation with a 1 in the selected bit SETBIT is an OR operation with a 1 in the selected bit CLRBIT is an AND operation with a 0 in the selected bit GLBIT is an XOR operation with a 1 in the selected bit AT status bits are affected by these instructions The following instructions could be used for example to test a bit and branch accordingly AF TSTBIT 5 OF AR IF NE JUMP set xJump to set if bit 5 of AR is set STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV
9. ADSP 218x Instruction Set Reference 4 185 Multifunction Instructions Permissible dregs AXO MX0 SI AX1 MX1 SE AYO MYO SRO AY1 MY1 SRI AR MRO MRI MR2 DESCRIPTION Perform the designated arithmetic operation and data transfer The write operation moves the contents of the source to the specified memory loca tion The addressing mode when combining an arithmetic operation with a memory write is register indirect with post modify For linear i e non circular indirect addressing the L register corre sponding to the I register used must be set to zero The contents of the source are always right justified in the destination register The computa tion must be unconditional All ALU MAC and Shifter operations are permitted except Shift Immediate and ALU DIVS and DIVQ instructions The fundamental principle governing multifunction instructions is that registers and memory are read at the beginning of the processor cycle and written at the end of the cycle 4 186 ADSP 218x Instruction Set Reference STATUS GENERATED See Table 4 11 on page 4 31 for register notation All status bits are affected in the same way as for the single function ver sions of the selected arithmetic operation lt ALU gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ x x x x AZ Set if result equals zero Cleared otherwise AN Set if result is negative Cleared otherwise AV Set if an overflow is generated Cleared
10. MOVE Read and Write Instructions Move instructions shown in Table 4 6 move data to and from data regis ters and external memory Registers are divided into two groups referred to as reg which includes almost all registers and dreg or data registers which is a subset Only the program counter PC and the ALU and MAC feedback registers AF and MF are not accessible Table 4 6 Move Instructions reg reg reg DM lt address gt dreg DM 0 0 3 1 1 2 2 3 3 4 4 5 5 6 6 7 7 DM 0 0 dreg 1 1 lt data gt 2 2 3 3 4 4 5 5 6 6 7 7 DM lt address gt reg ADSP 218x Instruction Set Reference 4 21 MOVE Read and Write Instructions Table 4 6 Move Instructions Contd reg lt data gt dreg PM ND oO bB PM I4 M4 15 M5 16 M6 17 M7 Table 4 7 shows how registers are grouped These registers are read and ND oO A written via their register names Table 4 7 Processor Registers reg and dreg reg registers dreg Data Registers SB PX 10 17 MO M7 LO L7 CNTR ASTAT MSTAT SSTAT IMASK ICNTL IFC TXO0 TX1 RXO RX1 AXO AX1 AYO AY1 AR MX0 MX1 MYO MY1 MRO MRI MR2 SI SE SRO SRI 4 22 ADSP 218x Instruction Set Reference Instruction Set Program Flow Control Program flow control on the ADSP 218x family processors is simple but po
11. MR MXO MYO UU Use fractional mode Multiply low words ADSP 218x Instruction Set Reference 4 75 MAC Instructions AR PASS MRO MRO MRI Right shift by 16 R1 MR2 R MR MXI MYO SU SRO AR Multiply middle words R MR MXO MY1 US AR PASS MRO MRO MRI Right shift by 16 R1 MR2 R MR MX1 MY1 SS SRI AR Multiply high word DESCRIPTION Test the optional condition and if true then multiply the two source operands and store in the destination location If the condition is not true perform a no operation Omitting the condition performs the multiplica tion unconditionally The operands are contained in the data registers specified in the instruction When MF is the destination operand only bits 31 16 of the product are stored in MF The data format selection field following the two operands specifies whether each respective operand is in Signed S or Unsigned U format The xop is specified first and yop is second If the xop xop operation is used the data format selection field must be UU SS or RND only There is no default one of the data formats must be specified If RND Round is specified the MAC multiplies the two source operands rounds the result to the most significant 24 bits or rounds bits 31 16 to 16 bits if there is no overflow from the multiply and stores the result in the destination register The two m
12. STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ _ a AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Set if operand 0x8000 Cleared otherwise AC Set if operand equals zero Cleared otherwise 4 54 ADSP 218x Instruction Set Reference Instruction Set INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF 10101 for yop operation AMF 11001 for xop operation Note that xop is a special case of yop xop with yop specified to be 0 Z Destination register Yop Y operand Xop X operand COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e ALU MAC Result Register Codes on page A 25 e AMF Function Codes on page A 10 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 55 ALU Instructions NOT SYNTAX IF cond JAR NOT xop AF yop Permissible xops Permissible yops Permissible conds AXO MR2 AYO EQ LE AC AX1 MRI AY1 NE NEG NOT AC AR MRO AF GT POS MV SR1 0 GE AV NOT MV SRO IT NOTAV NOTCE EXAMPLE IF NE AF
13. The PX register is an 8 bit register that allows data transfers between the 16 bit DMD bus and the 24 bit PMD bus In a transfer between program memory and a 16 bit register PX provides or receives the lower eight bits implicitly Timer The TPERIOD TCOUNT and TSCALE hold the timer period count and scale factor values respectively These registers are memory mapped at loca tions 0x3FFD Ox3FFC and 0x3FFB respectively Serial Ports SPORTO and SPORT 1 each have receive RX transmit TX and control registers The control registers are memory mapped registers at locations Ox3FEF through 0x3FFA in data memory SPORTO also has registers for controlling its multichannel functions Each SPORT control register con tains bits that control frame synchronization companding word length and in SPORTO multichannel options The SCLKDIV register for each SPORT determines the frequency of the internally generated serial clock 2 8 ADSP 218x Instruction Set Reference Programming Model and the RFSDIV register determines the frequency of the internally gener ated receive frame sync signal for each SPORT The autobuffer registers control autobuffering in each SPORT Programming a SPORT consists of writing to its control register and depending on the modes selected writing to its SCLKDIV and or RFSDIV registers as well The following example code programs SPORTO for 8 bit u law companding with normal framing and an internally generate
14. on page 4 112 e Logical Shift Immediate on page 4 114 4 2 ADSP 218x Instruction Set Reference Move Instruction Set Instructions Register Move on page 4 116 Load Register Immediate on page 4 118 Data Memory Read Direct Address on page 4 121 Data Memory Read Indirect Address on page 4 123 Program Memory Read Indirect Address on page 4 125 Data Memory Write Direct Address on page 4 127 Data Memory Write Indirect Address on page 4 129 Program Memory Write Indirect Address on page 4 132 IO Space Read Write on page 4 134 Program Flow Instructions JUMP on page 4 136 CALL on page 4 139 JUMP or CALL on Flag In Pin on page 4 141 Modify Flag Out Pin on page 4 143 RTS Return from Subroutine on page 4 145 RTI Return from Interrupt on page 4 147 Do Until on page 4 149 Idle on page 4 153 ADSP 218x Instruction Set Reference 4 3 Quick List Of Instructions MISC Instructions Stack Control on page 4 155 Program Memory Overlay Register Update on page 4 165 Data Memory Overlay Register Update on page 4 168 Mode Control on page 4 161 Modify Address Register on page 4 171 No Operation on page 4 173 Interrupt Enable and Disable on page 4 164 Multifunction Instructions Computation with Memory Read on page 4 174 Computation with Register to Regist
15. INSTRUCTION FORMAT Mode Control Instruction Type 18 23 22 21 20 19 18 17 16 15 14 13 12 11 1098 7 6 5 4 3 2 10 0 0 0 0 1 1 0 0 ITI MM AS OL IBR SR GM 10 0 TI Timer Enable MM Multiplier Placement AS AR Saturation Mode Control OL ALU Overflow Latch Mode Control BR Bit Reverse Mode Control SR Secondary Register Bank Mode GM GO Mode SEE ALSO e Mode Control Codes on page A 6 ADSP 218x Instruction Set Reference 4 163 MISC Instructions Interrupt Enable and Disable SYNTAX ENA INTS DIS INTS DESCRIPTION Interrupts are enabled by default at reset Executing the DIS INTS instruc tion causes all interrupts including the power down interrupt to be masked without changing the contents of the IMASK register Executing the ENA INTS instruction allows all unmasked interrupts to be serviced again Note that disabling interrupts does not affect serial port autobuffer ing or ADSP 218x DMA transfers IDMA or BDMA These oper ations will continue normally whether or not interrupts are enabled STATUS GENERATED No status bits affected INSTRUCTION FORMAT DIS INTS Instruction Type 26 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 01 0 0 0 0 0 0 00 0001000000 ENA INTS Instruction Type 26 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 6 5 4 3 2 1 O0 0 0 0 0 0 1 0 0 0 0 0 0 O 0 0001100000 4 164 ADSP 218x Instruction Set Refer
16. Instruction Set MAC Clear SYNTAX Il a IF cond IMR MF Permissible conds EQ NE GT GE LT LE NEG POS AV NOT AV AC NOTAC MV NOT MV NOT CE EXAMPLE IF GT MR 0 DESCRIPTION Test the optional condition and if true then set the specified register to zero If the condition is not true perform a no operation Omitting the condition performs the clear unconditionally The entire 40 bit MR or 16 bit MF register is cleared to zero ADSP 218x Instruction Set Reference 4 91 MAC Instructions STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ 0 _ MV Always cleared INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 1 1 10 0 0 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF 00100 for Clear operation Note that this instruction is a special case of xop yop with yop set to zero Destination register COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e ALU MAC Result Register Codes on page A 25 e AMF Function Codes on page A 10 4 92 ADSP 218x Instruction Set Reference MAC Transfer MR SYNTAX IF cond MR MR MF Permissible conds EQ NE GT LE NEG POS AC NOT AC MV EXAMPL
17. NOT AXO DESCRIPTION Test the optional condition and if true then perform the logical comple ment ones complement of the source operand and store in the destination location If the condition is not true then perform a no oper ation Omitting the condition performs the complement operation unconditionally The source operand is contained in the data register specified in the instruction STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise 4 56 ADSP 218x Instruction Set Reference Instruction Set AV Always cleared AC Always cleared INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 JCOND AMF specifies the ALU or MAC operation in this case AMF 10100 for NOT yop operation AMF 11011 for NOT xop operation Z Destination register Yop Y operand Xop X operand COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e ALU MAC Result Register Codes on page A 25 e AMF Function Codes on page A 10 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 57 A
18. Software Examples 14 gt C of WO 15 gt S of WO CNTR bfly count MYO C MX0 x1 MY1 S MX1 y1 DM 10 MO0 MR x1 S AX0 x0 MR x1 C yl S AYO x1 C yl1 S AR y0 Ly1 C x1 S Check for bit growth yl y0 Ly1 C x1 S AR x0 Ex1 C yl1 S Check for bit x1 x0 x1 C AR x0 Lx1 C yl S MXO next x1 MYO next C xi xf 1 1 xf ih R zi zy ur ai 4 nr F a 17 5 xi Check for bit growth x0 x0 x1 C yl1 S J AR y0 y1 C x1 S Check for bit growth y0 y0 y1 C x1 S IO gt 1st x0 in next group 11 gt 1st xl in next group I2 gt 1st yO in next group 13 gt 1st yl in next group Compensate for bit growth SI DM bflys_per_group SR ASHIFT SI BY 1 L0O DM node_space SRO node_space node_space 2 s xi a z RI E if xI ADSP 218x Instruction Set Reference 3 19 Radix 2 Decimation in Time FFT stage_loop DM bflys_per_group SRO bflys_per_group bflys_per_group 2 LAST STAGE dense x 10 inplacereal I1 inplacereal nover2 I2 inplaceimag 13 inplaceimagtnover2 CNTR nover2 M2 DM node_space M4 1 14 twid_real 15 twid_imag MYO PM 14 M4 MXO DM 1I1 M0 MYO C MX0 x1 MY1 PM 15 M4 MX1 DM 13 M0 MY1 S MX1 yl DO bfly_lp UNTIL CE MR MXO MY1 SS AXO0 DM 1I0 MO MR MR M
19. 16 17 lt addr gt Permissible conds EQ NE GT GE LT LE NEG POS AV NOT AV AC NOTAC MV NOT MV NOT CE EXAMPLE IF NOT CE JUMP top_loop CNTR is decremented DESCRIPTION Test the optional condition and if true perform the specified jump If the condition is not true then perform a no operation Omitting the condi tion performs the jump unconditionally The JUMP instruction causes program execution to continue at the effective address specified by the instruction The addressing mode may be direct or register indirect 4 136 ADSP 218x Instruction Set Reference For direct addressing using an immediate address value or a label the program address is stored directly in the instruction word as a full 14 bit field For register indirect jumps the selected I register provides the address it is not post modified in this case If JUMP is the last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled If NOT CE is used as the condition execution of the JUMP instruction decrements the processor s counter CNTR register STATUS GENERATED No status bits affected INSTRUCTION FORMAT Conditional JUMP Direct Instruction Type 10 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 1 1 0 ADDR COND Conditional JUMP Indirect Instruction Type 19 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O 0 0 0 0 1 O0 1 10 0 0 0 0 0 0 0 0 0 COND
20. DM IO MO is a legal version of this multifunction instruction and is not flagged by the assembler Reversing the order of clauses as in 2 AXO DM I0 MO AR AXO AYO results in an assembler warning but assembles and executes exactly as the first form of the instruction Note that reading example 2 from left to right may suggest that the data memory value is loaded into AX0 and then used in the computation all in the same cycle In fact this is not possible The left to right logic of example 1 suggests the operation of the instruc tion more closely Regardless of the apparent logic of reading the instruction from left to right the read first write second operation of the processor determines what actually happens Using the same register as a destination in both clauses however produces an indeterminate result and should not be done The assembler issues a warning unless semantics checking is turned off Regardless of whether or not the warning is produced however this practice is not supported 4 176 ADSP 218x Instruction Set Reference The following therefore is illegal and not supported even though assem bler semantics checking produces only a warning 3 AR AXO AYO AR DM 10 MO JI legal STATUS GENERATED See Table 4 11 on page 4 31 for register notation All status bits are affected in the same way as for the single function ver sions of the selected arithmetic operation lt ALU g
21. K X is an RxS matrix Y is an SxT matrix Z is an RxT matrix 3 12 ADSP 218x Instruction Set Reference FF F FF F Altered Regis TOAS a bey TA Computation Time S 8 XT Kf SECTION CODE progra Software Examples Calling Parameters I1 gt Z buffer in data memory Ll 0 I2 gt X stored by rows in data memory L2 0 I6 gt Y stored by rows in program memory L6 0 MO 1 Ml S M4 1 M5 T LO L4 L5 0 SE Appropriate scale value CNTR Return Values Z Buffer fi GLOBAL s pmn s pmm 15 16 CNTR M5 element_loop column_loop DM I1 MO SRI row_loop MODIFY I2 M1 led by rows ters I5 MR MX0 MYO SR 4 XR 2 2 cycles DO row_loop UNTIL CE Pe 15 start of N DO column_loop UNTIL CE RTS 10 12 Set 10 to current X row 14 15 Set 14 to current Y col CNTR M1 MR 0 MXO DM I0O MO MYO PM 14 M5 Get 1st data DO element_loop UNTIL CE MR MR MXO MYO SS MXO DM IO MO MYO PM 14 M5 SR ASHIFT MRI CHI MYO DM 15 M4 Update I5 SR SR OR LSHIFT MRO LO Finish Shift Save Output Update I2 to next X row xI Ki xi xy K PA mh zi ADSP 218x Instruction Set Reference 3 13 Radix 2 Decimation in Time FFT Radix 2 Decimation in Time FFT The FFT program includes three subroutines The first subroutine scram bles the input data placing the data in bit reversed address
22. The quotient bit generated on each execution of DIVS and DIVQ is the AQ bit which is written to the ASTAT register at the end of each cycle The final remainder produced by this algorithm and left over in the AF register is not valid and must be corrected if it is needed For more information consult the section Division Exceptions on page 4 70 of this manual STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ _ _ _ _ _ _ _ AQ Loaded with the bit value equal to the AQ bit computed on each cycle from execution of the DIVS or DIVQ instruction INSTRUCTION FORMAT DIVQ Instruction Type 23 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 Xop 0 0 0 0 0 0 0 0 DIVQ Instruction Type 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 0 0 0 Yop Xop 0 0 0 0 0 0 0 0 Xop X operand Yop Y operand 4 66 ADSP 218x Instruction Set Reference Instruction Set DIVISION THEORY The ADSP 218x family processors instruction set contains two instruc tions for implementing a non restoring divide algorithm These instructions take as their operands twos complement or unsigned num bers and in sixteen cycles produce a truncated quotient of sixteen bits For most numbers and applications these primitives produce the correct results However there are
23. Then the data is written into the data buffer Because of the automatic circular buffer addressing the new data overwrites the oldest sample The N most recent samples are always in the buffer The third instruction of the routine MR 0 MYO PM 14 M4 MXO DM 10 M0 clears the multiplier result register MR and fetches the first two operands This instruction accesses both program and data mem ory but still executes in a single cycle because of the processor s architecture The counter register CNTR directs the loop to be performed taps 1 times The convolution label identifies the loop itself consisting of only two instructions one instruction setting up the loop DO UNTIL and one instruction nested in the loop The MAC instruction multiplies and accu mulates the previous set of operands while fetching the next ones from each memory This instruction also accesses both memories The final result is written back to the SPORTO transmit data register TX0 to be sent to the communicating device 2 16 ADSP 218x Instruction Set Reference Programming Model Hardware Overlays and Software Issues Hardware overlay pages can be used for both program execution and data storage Switching between hardware overlay memory pages can be done in a single processor cycle with no effect latencies The following examples show the assembly instructions for managing different program memory hardware overlay regions pmovlay ax0 pmovlay
24. pops these stacks The Mode Control instruction enables and disables processor modes of operation bit reversal on DAG latching ALU overflow saturating the ALU result register choosing the primary or secondary register set GO mode for continued operation during bus grant multiplier shift mode for fractional or integer arithmetic and timer enabling A single ENA or DIS can be followed by any number of mode identifiers separated by commas ENA and DIS can also be repeated All seven modes can be enabled disabled or changed in a single instruction The MODIFY instruction modifies the address pointer in the I register selected with the value in the selected M register without performing any actual memory access As always the I and M registers must be from the same DAG any of 10 13 may be used only with one from M0 M3 and the same for 14 17 and M4 M7 If circular buffering is in use modulus logic applies See the ADSP 218x DSP Hardware Reference Manual Chapter 4 Data Address Generators for more information The FO Flag Out FLO FL1 and FL2 pins can each be set cleared or tog gled This instruction provides a control structure for multiprocessor communication 4 26 ADSP 218x Instruction Set Reference Instruction Set Table 4 10 Miscellaneous Instructions OP oe STS POP CNTR POP PC POP LOOP POP ENA BIT_REV ie AV_LATCH AR_SAT SEC_REG G_MODE M_MODE TI
25. 12 11109 8 7 6 5 4 3 2 10 0 0 1 1 RGP DATA REG Type 8 ALU MAC with Internal Data Register Move 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 1 0 1 Z AMF Yop Xop Dreg dest Dreg source Generate ALU Status NONE lt ALU gt 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 1 0 1 0 AMF Yop Xop I o1 ALU codes only Type 9 Conditional ALU MAC xop yop 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 IZ AMF Yop Xop 0 0 0 0 COND xop xop 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 0 0 1 0 0 Z AMF 0 0 Xop 0 0 0 1 COND xop AND OR XOR constant 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 0 0 1 0 0 Z AMF YY Xop CC BO COND ADSP 218x DSP Instruction Set Reference A 3 Opcode Definitions BO CC and YY specify the constant according the table shown at the end of this appendix PASS constant constant 0 1 1 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 0 0 1 0 0 Z AMF YY Xop CC BO COND Type 10 Conditional Jump Immediate Address 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 0 1 1 S ADDR COND Type 11 Do Until 23 22 21 20 19 18 17 1
26. 14 M4 15 M5 16 M6 17 M7 SI SE SRI SRO MX1 PM I6 M5 DESCRIPTION The Program Memory Read Indirect instruction moves the contents of the program memory location to the destination register The addressing mode is register indirect with post modify For linear i e non circular indirect addressing the L register corresponding to the register used must be set to zero The 16 most significant bits of the Program Memory Data bus PMD 3 g are loaded into the destination register with bit PMD lining up with bit 0 of the destination register right justification If the destination register is less than 16 bits wide the most significant bits are dropped Bits PMD7 are always loaded into the PX register You may ignore these bits or read them out on a subsequent cycle ADSP 218x Instruction Set Reference 4 125 Move Instructions STATUS GENERATED No status bits affected INSTRUCTION FORMAT ALU MAC operation with Data Memory Read Instruction Type 4 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 0 1 0 0 AMF 0 0 0 0 0 DREG I M AMF specifies the ALU or MAC operation to be performed in parallel with the Data Memory Read In this case AMF 00000 indicating a no opera tion for the ALU MAC function To choose a data register refer to the table DREG Selection Codes on page A 14 I specifies the indirect address pointer I register M specifies the
27. 21 Block Floating Point Scaling Subroutine ss 3 22 ii ADSP 218x Instruction Set Reference CONTENTS INSTRUCTION SET eke List Ol RDS mao mamenauus 4 1 AR PP ON aici corte ene 4 1 DS DO manon 4 2 Shifter ASE end ENE SNESE 4 2 Moye DAMON en da 4 3 Program Flow Dostru ctions csenamneniiinbakisirciniinkpiiakiiriih 4 3 MISC UE cariene oa a an 4 4 inion DRE rss 4 4 Che cha miens 4 5 MR ee SiR aroaren nN R 4 7 ALU MAC with Data and Program Memory Read 00004 4 7 Data and Program Memory Read doses 4 8 Campuratien with Memory Read icceniemnameeie 4 9 Computaton With Memory Write teste 4 9 Computation with Data Register Move issus 4 10 ALU MAC Oc Shifter Instructions isccciccsssececneaccsncsereasenancsecseuwasts 4 14 REU GTO a ia E A 4 14 MAC GOUD chess cat snntsdamiantraatincianinabiiiaul nasi tiaudnel bibaueanbinaisauans 4 17 SIE OOUT ro n on eens 4 19 MOVE Reed and Wine RON needs 4 21 Programa Flow Control mamans 4 23 Miscellaneous Insee nine isa 4 26 Exoa Cyce ON eine 4 28 ADSP 218x Instruction Set Reference iii CONTENTS Multiple Of Chip Memory ACCESSES rssimnmenseneneendanes 4 28 homo non din 4 28 SPORT Antobuftering aad DMA mens 4 29 Instruction Ser Synta soea eoe N 4 29 Punctuation and Multifunction Instructions 4 29 Syntax Notation Faample sise sensor 4 30 Statis Rezistor NOR ccc eens 4 31 RO 4 32 Add Add e CAF nee 4 32 Subtract X Y Subtract X Y with Borrow esssee
28. 4 180 ADSP 218x Instruction Set Reference The fundamental principle governing multifunction instructions is that registers and memory are read at the beginning of the processor cycle and written at the end of the cycle The normal left to right order of clauses computation first register transfer second is intended to imply this In fact you may code this instruction with the order of clauses reversed The assembler produces a warning but the results are identical at the opcode level If you turn off semantics checking in the assembler s switch the warning is not issued Because of the read first write second characteristic of the processor using the same register as source in one clause and a destination in the other is legal The register supplies the value present at the beginning of the cycle and is written with the new value at the end of the cycle For example 1 AR AXO AYO AXO MRI is a legal version of this multifunction instruction and is not flagged by the assembler Reversing the order of clauses as in 2 AXO MRI AR AXO AYO results in an assembler warning but assembles and executes exactly as the first form of the instruction Note that reading example 2 from left to right may suggest that the MR1 register value is loaded into AX0 and then AXO is used in the computation all in the same cycle In fact this is not possible The left to right logic of example 1 suggests the operation of the ins
29. B EXPADJ AR DM I3 M2 AR AYO DM 1I1 M0 group_Ip AY1 DM 13 M0 CALL bfp_adj NAFnNDNAYEVnA LS pS ete ses STAGES 2 TO N 1 DO stage_loop UNTIL CE Compute all stages in FFT I0 inplacereal IO gt x0 in Ist grp of stage I2 inplaceimag I2 gt y0 in 1st grp of stage SI DM groups SR ASHIFT SI BY 1 LO groups 2 DM groups SRO groups groups 2 CNTR SRO CNTR group counter M4 SRO M4 twiddle factor modifier M2 DM node_space M2 node space modifier 11 10 MODIFY I1 M2 Il gt y0 of Ist grp in stage MODIFY I3 M2 I3 gt yl of 1st grp in stage 3 18 ADSP 218x Instruction Set Reference DO group_loop UNTIL CE I4 twid_ real 15 twid_imag CNTR DM bflys_per_group MYO PM 14 M4 MXO DM I1 M0 MY1 PM 15 M4 MX1 DM 13 M0 DO bfly_loop UNTIL CE bfly_loop group_loop MR MXO MY1 SS AX0 MR MR MX1XMYO CRND M AYO MRI AR AXI AY R AX1 AY1 n gt MODIFY IO M2 MODIFY I1 M2 MODIFY I2 M2 MODIFY I3 M2 CALL bfp_adj SB EXPADJ AR DM I3 M1 AR AR AX0 AYO MX1 DM 13 MO MY1 PM 15 M4 MXi next yl MYl next S SB EXPADJ AR DM I1 M1 AR AR AX0 AY0 MXO DM 11 MO0 MYO PM T4 M4 SB EXPADJ AR DM IO M1 AR B EXPADJ AR DM I2 MI AR 1 1 1 1 1 AX1 DM 12 M0 MR y1 C x1 S AX1 y0 AYI MRI MR MXO MYOCSS AY1 y1 C x1 0 S MR x1 C R MR MX1 MY1 RND
30. CONTENTS CONTENTS INTRODUCTION POD E an een nea Re Ed et 1 1 idee moisi 1 1 Comente IEW drr A 1 2 Derclopment TON de 1 3 For More Information About Analog Products esseere 1 6 Por Techno Customer SUPPO disons 1 7 Ty eas New in This ML aan mice 1 7 Related Documents secrackcssscasucaosinctcasnsinirseliel niiamcinealineimndaadin 1 8 ROOTS cts cadaarccuassalacadnaegalen leaner gidanigaaaai aus oc mis 1 9 PROGRAMMING MODEL CS E E E E E E E T 2 1 Dars Address Genetit eee a 2 4 POSE ooon E apoa 2 5 Coreen Vie intended 2 7 it Be aii oe eee ee ek 2 8 ADSP 218x Instruction Set Reference i CONTENTS TEL smash 2 8 LPO nana neo E 2 8 Memory Interlace e SPORT Enables ssretianine 2 10 Program Eene senn ed RS 2 12 Example Program Setup Routine Discussion ssseesceecceeee 2 14 Example Program Interrupt Routine Discussion 0004 2 15 Hardware Overlays and Software Issues sorcnnnninisossinineiai 2 17 Libraries and Oreta inre 2 18 Den and verl ays a 2 18 Loop Hardware and Overlays ne tiens 2 20 SOFTWARE EXAMPLES AO a na T 3 1 System Development Process ins en edesinns 3 3 Single Precision Fir Transversal Filter nsnssniotoisiusranininiiaisi 3 6 ost eel Dis UR TIEF te 3 8 Sine AD TOR ANR sior ina deanstende 3 10 Single Precision Matrix PACS manne 3 12 Rates Decimation im Time FET neue 3 14 Mam Module dissident dit iin 3 14 DIT FFT Subroutine itunes 3 16 Bie Reverse SUDIOWUNE 4 c4ncinacntciieenaueieiieennatinnin 3
31. Call A 20 ADSP 218x DSP Instruction Set Reference SF Shifter Function Codes Table A 20 Shifter Function Codes Instruction Coding Code Function 0 0 0 LSHIFT HI 000 LSHIFT HI OR 001 LSHIFT LO 001 LSHIFT LO OR 0 0 ASHIFT HI 0 0 ASHIFT HI OR 0 1 ASHIFT LO 0 1 ASHIFT LO OR 0 0 NORM HI 0 0 NORM HI OR 01 NORM LO 01 NORM LO OR 0 EXP HD 0 EXP HIX 1 EXP LO 1 Derive Block Exponent ADSP 218x DSP Instruction Set Reference A 21 Opcode Mnemonics SPP Status Stack Push Pop Codes Table A 21 Status Stack Push and Pop Codes Code Description 0 0 No change 0 1 No change 1 0 Push 11 Pop T Return Type Codes Table A 22 Return Type Codes Code Return Type 0 Return from subroutine 1 Return from interrupt TERM Termination Codes for DO UNTIL Table 1 23 DO UNTIL Termination Codes Code Description Condition 0000 Not Equal NE 0001 Equal EQ 0010 kesta drequal LE A 22 ADSP 218x DSP Instruction Set Reference Instruction Coding Table 1 23 DO UNTIL Termination Codes Code Description Condition 0011 Greater than GT 0100 Greater than or equal GE 0 0 1 Less than LT 0 1 0 NOT ALU Overflow NOT AV 0 11 ALU Overflow AV 000 Not ALU Carry NOT AC 001 AL
32. Codes on page A 24 ADSP 218x Instruction Set Reference 4 105 Shifter Instructions Derive Exponent SYNTAX IF cond SE EXP xop CHI LO HIX Permissible xops Permissible conds SI AR EQ LE AC SRI MR2 NE NEG NOT AC SRO MRI GT POS MV MRO GE AV NOT MV LT NOT AV NOT CE EXAMPLES Conditional derive exponent IF GT SE EXP MRI HI Normalize 32 bit data to one sign bit to get the best precision during arithmetic calculations SE SE SR SR First determine the exponent of the 32 bit register SR EXP SRI HI EXP SRO LO Second normalize to one sign bit NORM SRI HI SI SRO SR OR NORM SI LO 4 106 ADSP 218x Instruction Set Reference Do your calculations Last shift data back to original weight SR ASHIFT SRI HI SI SRO SR SR OR LSHIFT SI LO DESCRIPTION Test the optional condition and if true perform the designated exponent operation If the condition is not true then perform a no operation Omit ting the condition performs the exponent operation unconditionally The EXP operation derives the effective exponent of the input operand to prepare for the normalization operation NORM EXP supplies the source operand to the exponent detector which generates a shift code from the number of leading sign bits in the input operand The shift code stored in SE at the completion of the EXP instruction is the effective exponent of the input va
33. For linear i e non circular indirect addressing the L register corresponding to the I register used must be ADSP 218x Instruction Set Reference 4 123 Move Instructions set to zero The contents of the source are always right justified in the des tination register after the read bit 0 maps to bit 0 STATUS GENERATED No status bits affected INSTRUCTION FORMAT ALU MAC operation with Data Memory Read Instruction Type 4 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 1 G 10 0 AMF 0 0 0 0 0 DREG I M AMF specifies the ALU or MAC operation to be performed in parallel with the Data Memory Read In this case AMF 00000 indicating a no opera tion for the ALU MAC function To choose a data register refer to the table DREG Selection Codes on page A 14 G specifies which Data Address Generator the I and M registers are selected from These registers must be from the same DAG as separated by the gray bar above specifies the indirect address pointer I register M specifies the modify register M register SEE ALSO e DAG Selection Codes on page A 17 e Index Register Selection Codes on page A 17 e Modify Register Selection Codes on page A 18 4 124 ADSP 218x Instruction Set Reference Program Memory Read Indirect Address SYNTAX dreg PM Permissible dregs AXO MXO AXI MXI AYO MYO AYI MYI AR MR2 MRI MRO EXAMPLE
34. If memory access times require or contention for off chip memory occurs overhead cycles will be required but all instructions can otherwise execute in a single cycle In addition to JUMP and CALL the instruction set s control instructions support conditional execution of most calculations and a DO UNTIL loop ADSP 218x Instruction Set Reference 4 5 Overview ing instruction Return from interrupt RTI and return from subroutine RTS are also provided The IDLE instruction is provided for idling the processor until an interrupt occurs IDLE puts the processor into a low power state while waiting for interrupts Two addressing modes are supported for memory fetches Direct address ing uses immediate address values indirect addressing uses the I registers of the two data address generators DAGs The 24 bit instruction word allows a high degree of parallelism in per forming operations The instruction set allows for single cycle execution of any of the following combinations e Any ALU MAC or Shifter operation conditional or non condi tional e Any register to register move e Any data memory read or write e A computation with any data register to data register move e A computation with any memory read or write e A computation with a read from two memories The instruction set allows maximum flexibility It provides moves from any register to any other register and from most registers to from mem ory In additi
35. If the condition is not true then perform a no operation Omit ting the condition performs the exponent operation unconditionally The Block Exponent Adjust operation when performed on a series of num bers derives the effective exponent of the number largest in magnitude This exponent can then be associated with all of the numbers in a block floating point representation The Block Exponent Adjust circuitry applies the input operand to the exponent detector to derive its effective exponent The input must be a signed twos complement number The exponent detector operates in HI mode see the EXP instruction above At the start of a block the SB register should be initialized to 16 to set SB to its minimum value On each execution of the EXPADJ instruction the effective exponent of each operand is compared to the current contents of 4 110 ADSP 218x Instruction Set Reference the SB register If the new exponent is greater than the current SB value it is written to the SB register updating it Therefore at the end of the block the SB register will contain the largest exponent found EXPADJ is only an inspection operation no actual shifting takes place since the true exponent is not known until all the numbers in the block have been checked However the numbers can be shifted at a later time after the true exponent has been derived Extended overflowed numbers and the lower halves of double precision numbers can not be processe
36. Instruction Type 3 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 1 0 0 D RGP ADDR REG Load Non data Register Immediate Instruction Type 7 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 0 0 1 1 RGP DATA REG Load Non data Register Immediate Instruction Type 17 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 0 0 O 0 JDST SRC DEST SOURCE RGP RGP REG REG To choose the source register group SRC RGP and the source register SOURCE REG refer to the table Register Selection Codes on page A 19 To choose the destination register group DST RGP and the destination register DEST REG refer to the table Register Selection Codes on page A 19 ADSP 218x Instruction Set Reference 4 167 MISC Instructions Data Memory Overlay Register Update SYNTAX DMOVLAY lt data gt reg DMOVLAY data lt constant gt Permissible dregs Permissible regs AXO MX0 SI SB CNTR AXI MXI SE PX OWRCNTR write only AYO MYO SRI ASTAT RXO AYI MYI SRO MSTAT RXI AR MR2 IMASK TXO MRI ICNTL TXI MRO 10 17 IFC write only MO M7 PMOVLAY LO L7 4 168 ADSP 218x Instruction Set Reference Permissible constants 1 2 ADSP 2184 and ADSP 2186 processors only 0 1 2 ADSP 2181 ADSP 2183 and ADSP 2185 processors only 0 1 2 4 5 ADSP 2187 processors only 0 1 2 4 5 6 7 ADSP 2189 processors only 0 1 2 4 5
37. Internal registers hold data addresses control information or status infor mation For example AX0 stores an ALU operand data 14 stores a DAG2 pointer address ASTAT contains status flags from arithmetic oper ations fields in the wait state register control the number of wait states for different zones of external memory There are two types of accesses for registers The first type of access is made to dedicated registers such as MX0 and IMASK These registers can be read and written explicitly in assembly language For example MX0 1234 IMASK OXF The second type of access is made to memory mapped registers such as the system control register wait state control register timer registers and SPORT registers These registers are accessed by reading and writing the corresponding data memory locations For example the following code ADSP 218x Instruction Set Reference 2 1 Overview clears the Wait State Control Register which is mapped to data memory location 0x3FFE AX0 0 DM OxX3FFE AX0 In this example AX0 is used to hold the constant 0 because there is no instruction to write an immediate data value to memory using an immedi ate address 2 2 ADSP 218x Instruction Set Reference Programming Model The ADSP 218x registers are shown in Figure 2 1 The registers are grouped by function data address generators DAGs program sequencer computational units ALU MAC and shifter bus exchange PX mem o
38. MAC operation as in our example The computational part of this multifunction instruction may be any unconditional ALU instruction except division or any MAC instruction except saturation Certain other restrictions apply the next X operand must be loaded into MX0 from data memory and the new Y operand must be loaded into MYO from program memory internal and external memory are identical at the level of the instruction set The result of the computa tion must go to the result register MR or AR not to the feedback register MF or AF Data and Program Memory Read This variation of a multifunction instruction is a special case of the multi function instruction described above in which the computation is omitted It executes only the dual operand fetch as shown below AXO DM I2 M0 AYO PM 14 M6 In this example we have used the ALU input registers as the destination As with the previous multifunction instruction X operands must come from data memory and Y operands from program memory internal or external memory in either case for the processors with on chip memory 4 8 ADSP 218x Instruction Set Reference Instruction Set Computation with Memory Read If a single memory read is performed instead of the dual memory read of the previous two multifunction instructions a wider range of computa tions can be executed The legal computations include all ALU operations except division all MAC operations and all Shifter operat
39. MV AQ AS AC AV AN AZ _ _ x AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Set if an arithmetic overflow occurs Cleared otherwise AC Set if a carry is generated Cleared otherwise INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF 11010 for yop xop C 1 AMF 11001 for yop xop Note that xop 1 is a special case of yop xop C 1 with yop 0 Z Destination register Yop Y operand Xop X operand COND Condition xop constant Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 1 0 0 Z AMF YY Xop CC BO COND ADSP 218x Instruction Set Reference 4 41 ALU Instructions AMF specifies the ALU or MAC operation in this case AMF 11010 for constant xop C 1 AMF 11001 for constant xop 2 Destination register COND Condition Xop X operand BO CC and YY specify the constant SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e BO CC and YY ALU MAC Constant Codes on page A 25 e ALU MAC Result Register Codes on page A 25 e AMF Functi
40. MX1 MY1 SS MX1 DM I3 M3 MR x 1st coeff Get 2nd coeff CNTR 3 DO approx UNTIL CE xf ne Xi x7 ai 7 ADSP 218x Instruction Set Reference 3 11 Single Precision Matrix Multiply MR MR MX1 MF SS MF AR MF RND MF x3 xf x approx MX1 DM 13 M3 Get coeff C D E MR MR MX1 MF SS SR ASHIFT MR1 BY 3 HI Convert to 1 15 fmt SR SR OR LSHIFT MRO BY 3 LO AR PASS SRI IF LT AR PASS AYO Saturate if needed AF PASS AXO IF LT AR AR Negate output if needed RTS Single Precision Matrix Multiply The routine presented in this section multiplies two input matrices X and Y X is an RxS R rows S columns matrix stored in data memory Y is an SxT S rows T columns matrix stored in program memory The output Z is an RxT R rows T columns matrix written to data memory The matrix multiply routine is shown in Listing 3 4 It requires that you initialize a number of registers as listed in the Calling Parameters section of the initial comment SE must contain the value necessary to shift the result of each multiplication into the desired format For example SE would be set to zero to obtain a matrix of 1 31 values from the multiplica tion of two matrices of 1 15 values Listing 3 4 Single Precision Matrix Multiply X Single Precision Matrix Multiplication K S Z i j YLLXG k X Y k j i 0 to R j 0 to T k 0
41. O Z AMF 0 0 Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation In this case AMF 11111 for ABS xop operation Z Destination register Xop X operand COND Condition ADSP 218x Instruction Set Reference 4 59 ALU Instructions SEE ALSO IF Condition Codes Table 4 9 on page 4 25 Status Condition Codes on page A 12 ALU MAC Result Register Codes on page A 25 AMF Function Codes on page A 10 X Operand Codes on page A 24 4 60 ADSP 218x Instruction Set Reference Instruction Set Increment SYNTAX IF cond ie F yop 1 AF Permissible yops Permissible conds AYO AX0 EQ LE AC AY1 AX1 NE NEG NOT AC AF MRO GT POS MV AR MRI GE AV NOT MV SRO MR2 LT NOT AV NOT CE SRI EXAMPLE IF GT AF AF 1 DESCRIPTION Test the optional condition and if true then increment the source oper and by 0x0001 and store in the destination location If the condition is not true then perform a no operation Omitting the condition performs the increment operation unconditionally The source operand is contained in the data register specified in the instruction STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ _ Jao _ _ x x x x AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise ADSP 218x Instruction Set Reference 4 61 ALU Instructions AV Set if an overflow is generate
42. Reference 2 17 Hardware Overlays and Software Issues main pmovlay 4 switch to PM overlay 4 call Ovl4Function call overlay function pmovlay 5 return from overlay 4 amp goto overlay 5 call Ovl5Function call overlay function Libraries and Overlays Because the program sequencer works independently from the program memory overlay register PMOVLAY program modules that run within an overlay page have no direct access to any program modules resident in other overlay pages This means that all the required libraries and sub functions must be placed either in the same page as the calling func tion or in the fixed memory non overlay area Place libraries that are used by multiple modules located in different pages in the fixed program mem ory region as well Unfortunately for some applications there is a limited amount of fixed program memory In this case the linker places parts of the library in different overlay pages to help balance the memory usage in the system Interrupts and Overlays The interrupt vector table occupies program memory addresses 0x0000 through 0x002f When an unmasked interrupt is raised ASTAT MSTAT and IMASK are pushed onto the status stack in this specific order The current value of the program counter which contains the address of the next instruction is placed onto the PC stack This allows the program execution to continue with the next instruction of the main program after
43. SE If however the upper half was all sign bits then EXP in the LO mode totals the number of leading sign bits in the double preci sion word and stores the resulting shift code in SE STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ SS Set by the MSB of the input for an EXP operation in the HI or HIX mode with AV 0 Set by the MSB inverted in the HIX mode with AV 1 Not affected by operations in the LO mode INSTRUCTION FORMAT Conditional Shift operation Instruction Type 16 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 O SF Xop 0 0 0 0 COND SF Shifter Function 1100 EXP HI 1101 EXP HIX 1110 EXP LO 4 108 ADSP 218x Instruction Set Reference Xop Shifter operand COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e Shifter Function Codes on page A 21 e X Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 109 Shifter Instructions Block Exponent Adjust SYNTAX IF cond SB EXPADJ xop Permissible xops Permissible conds SI AR EQ LE AC SRI MR2 NE NEG NOT AC SRO MRI GT POS MV MRO GE AV NOT MV LT NOT AV NOT CE EXAMPLES IF GT SB EXPADJ SI DESCRIPTION Test the optional condition and if true perform the designated exponent operation
44. Scrambled input data in inplacereal tered Registers 10 T4 M0 M4 AY1 Altered Memory inplacereal N 1024 mod_value 0x0010 Initialize constants inputreal inplacereal scramble 14 inputreal T4 gt sequentially ordered data I0 inplacereal I0 gt scrambled data M4 1 MO mod_value MO modifier for reversing N Bits A 1 K 7 ADSP 218x Instruction Set Reference 3 21 Radix 2 Decimation in Time FFT brev L4 0 LO 0 CNTR N ENA BIT_REV Enable bit reversed outputs on DAGI DO brev UNTIL CE AY1 DM I4 M4 Read sequentially ordered data DMCIO MO AYI Write data in bit reversed location DIS BIT_REV Disable bit reverse RTS Return to calling program Block Floating Point Scaling Subroutine The bfp_adj routine checks the FFT output data for bit growth and scales the entire set of data if necessary This check prevents data overflow for each stage in the FFT The routine shown in Listing 3 8 uses the expo nent detection capability of the shifter Listing 3 SECT Ca Radi Re inp A TQ A defi EXTE Be 8 Radix 2 Block Floating Point Scaling Routine ON CODE program ling Parameters ix 2 DIT FFT stage results in inplacereal and inplaceimag turn Parameters acereal and inplaceimag adjusted for bit growth tered Registers 1 AX0 AY0 AR MXO MYO MR CNTR tered Memory inplacereal inplaceim
45. The ADSP 218x processors support the xop xop squaring operation However both xops must be in the same register This option allows sin gle cycle X and XX instructions The data format selection field must be UU SS or RND only There is no default for the data format selection field one of the data formats must be specified The squaring instruction cannot be used in a multifunction instruction 4 88 ADSP 218x Instruction Set Reference Instruction Set STATUS GENERATED ASTAT MV 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ Set on MAC overflow if any of upper 9 bits of MR are not all one or zero Cleared otherwise INSTRUCTION FORMAT xop xop Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 1 Z AMF 0 0 Xop 0 0 0 1 COND AMF specifies the ALU or MAC operation In this case AMF Function Data Format X Operand 01000 MR xop xop SS Signed 01011 MR xop xop UU Unsigned 00010 MR xop xop RND Signed Z Destination register Xop X operand COND Condition ADSP 218x Instruction Set Reference 4 89 MAC Instructions SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e ALU MAC Result Register Codes on page A 25 e X Operand Codes on page A 24 e AMF Function Codes on page A 10 4 90 ADSP 218x Instruction Set Reference
46. This routine accepts input values in 1 15 format The coefficients which are initialized in data memory in 4 12 format have been adjusted to reflect an input value scaled to the maximum range allowed by this format On this scale 180 7 radians equals the maximum positive value 0x7FFF while 180 7 radians equals the maximum negative value 0x8000 The routine shown in Listing 3 3 first adjusts the input angle to its equiv alent in the first quadrant The sine of the modified angle is calculated by multiplying increasing powers of the angle by the appropriate coefficients The result is adjusted if necessary to compensate for the modifications made to the original input value 3 10 ADSP 218x Instruction Set Reference Software Examples Listing 3 3 Sine Approximation 1 Sine Approximation Y Sin x X Calling Parameters x AXO x in scaled 1 15 format M3 1 5 L3 0 Return Values ki AR y in 1 15 format ss Altered Registers AYO AF AR MY1 MX1 MF MR SR 13 z Computation Time X 25 cycles K SECTION DATA datal VAR sin_coeff 5 0x3240 0x0053 OxAACC Ox08B7 Ox1CCE SECTION CODE program GLOBAL sin sin 13 sin_coeff Pointer to coeff buffer AY0 0x4000 AR AXO Copy x AF AX0 AND AYO Check 2nd or 4th Quad IF NE AR AX0 If yes negate AYO 0X7FFF AR AR AND AYO Remove sign bit MY1 AR Copy x MF AR MY1 RND MX1 DM I3 M3 MF x 2 Get 1st coeff MR
47. a single instruction This instruction does not directly alter the flow of your pro gram it is provided to signal external devices Note that the F0 pin is specified by FLAG_OUT in the instruction syntax The following flag outputs are present on the ADSP 218x processor F0 FLO FL1 FL2 STATUS GENERATED No status bits affected ADSP 218x Instruction Set Reference 4 143 Program Flow Instructions INSTRUCTION FORMAT Flag Out Mode Control Instruction Type 28 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 FO FO COND PRE FL2 FLI FLO FLAG OUT FO Operation to perform on flag COND Condition code output pin SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e FO Condition Codes on page A 16 4 144 ADSP 218x Instruction Set Reference RTS Return from Subroutine SYNTAX CIF cond RTS Permissible conds EQ NE GT GE LT LE NEG POS AV NOT AV AC NOTAC MV NOT MV NOT CE EXAMPLE IF LE RTS DESCRIPTION Test the optional condition and if true then perform the specified return If the condition is not true then perform a no operation Omitting the condition performs the return unconditionally RTS executes a program return from a subroutine The address on top of the PC stack is popped and is used as the return address The PC stack is the only stack popped If RTS is the
48. destination of all shifting operations is the Shifter Result register SR The destination of exponent detection instructions is SE or B as shown in Table 4 5 In this example SI the Shifter Input register is the operand The amount and direction of the shift is controlled by the signed value in the SE register in all shift operations except an immediate shift Positive values cause left shifts negative values cause right shifts The optional SR OR modifier logically ORs the result with the current con tents of the SR register this allows you to construct a 32 bit value in SR from two 16 bit pieces NORM is the operator and HI is the modifier that determines whether the shift is relative to the HI or LO 16 bit half of SR If SR OR is omitted the result is passed directly into SR ADSP 218x Instruction Set Reference 4 19 ALU MAC amp Shifter Instructions Table 4 5 gives a summary list of all Shifter instructions In this list con dition stands for all the possible conditions that can be tested Table 4 5 Shifter Instructions IF cond SR SR OR ASHIFT xop IHI LO IF cond SR SR OR LSHIFT xop HI LO CIF cond SR SR OR NORM xop H I LO IF cond SE EXP xop H LO HIX IF cond SB EXPADJ xop SR SR OR ASHIFT xop BY lt exp gt HI J LO SR SR OR LSHIFT xop BY lt exp gt HI K LO 4 20 ADSP 218x Instruction Set Reference Instruction Set
49. immediate address value TERM specifies the termination condition as shown below TERM Syntax Condition Tested 0000 NE Not Equal to Zero 0001 EQ Equal Zero 0010 LE Less Than or Equal to Zero 0011 GT Greater Than Zero 0100 GE Greater Than or Equal to Zero 0101 LT Less Than Zero 0110 NOT AV Not ALU Overflow 0111 AV ALU Overflow 1000 NOT AC Not ALU Carry 1001 AC ALU Carry 1010 POS X Input Sign Positive 1011 NEG X Input Sign Negative ADSP 218x Instruction Set Reference 4 151 Program Flow Instructions TERM Syntax Condition Tested 1100 NOT MV Not MAC Overflow 1101 MV MAC Overflow 1110 CE Counter Expired 1111 FOREVER Always 4 152 ADSP 218x Instruction Set Reference Idle SYNTAX IDLE IDLE n slow idle DESCRIPTION IDLE causes the processor to wait indefinitely in a low power state waiting for interrupts When an interrupt occurs it is serviced and execution con tinues with the instruction following IDLE Typically this next instruction will be a JUMP back to IDLE implementing a low power standby loop Note the restrictions on JUMP or IDLE as the last instruction in a DO UNTIL loop detailed in the ADSP 218x DSP Hardware Reference Manual Chapter 3 Program Control IDLE n is a special version of IDLE that slows the processor s internal clock signal to further reduce power consumption The red
50. is not necessary in a real system Variables one location buffers named groups bflys_per_group node_space and blk_exponent are declared last 3 14 ADSP 218x Instruction Set Reference Software Examples The real parts cosine values of the twiddle factors are stored in the buffer twid_real This buffer is initialized from the file twid_real dat Like wise twid_imag dat values initialize the twid_imag buffer that stores the sine values of the twiddle factors In an actual system the hardware would be set up to initialize these memory locations The variable called groups is initialized to N_div_2 The variables bflys_per_group and node_space are each initialized to 2 because there are two butterflies per group in the second stage of the FFT The blk_exponent variable is initialized to zero This exponent value is updated when the output data is scaled After the initializations are complete two subroutines are called The first subroutine places the input sequence in bit reversed order The second performs the FFT and calls the block floating point scaling routine Listing 3 5 Main Module Radix 2 DIT FFT SECTION CODE program itdefine N 1024 define N_div_2 512 For 2048 points SECTION DATA data VAR padding 4 0 0 0 0 VAR inputreal N inputreal dat VAR inputimag N inputimag dat GLOBAL inputreal inputimag VAR inplacereal N VAR inplaceimag N inputimag dat GLOBAL inplac
51. last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled STATUS GENERATED No status bits affected ADSP 218x Instruction Set Reference 4 145 Program Flow Instructions INSTRUCTION FORMAT Conditional Return Instruction Type 20 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0000101 0 0 0 0 0 0 0 0 0 0 0 0 0 COND COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 4 146 ADSP 218x Instruction Set Reference RTI Return from Interrupt SYNTAX CIF cond RTI Permissible conds EQ NE GT GE LT LE NEG POS AV NOT AV AC NOTAC MV NOT MV NOT CE EXAMPLE IF MV RTI DESCRIPTION Test the optional condition and if true then perform the specified return If the condition is not true then perform a no operation Omitting the condition performs the return unconditionally RTI executes a program return from an interrupt service routine The address on top of the PC stack is popped and is used as the return address The value on top of the status stack is also popped and is loaded into the arithmetic status ASTAT mode status MSTAT and the interrupt mask IMASK registers If RTI is the last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled STATUS GENERATED No status bits affected ADSP 218x Instruction Set Referen
52. modify register M register SEE ALSO e Index Register Selection Codes on page A 17 e Modify Register Selection Codes on page A 18 4 126 ADSP 218x Instruction Set Reference Data Memory Write Direct Address SYNTAX DM lt addr gt reg Permissible registers AX0 MX0 SI SB CNTR AXI MXI SE PX RXO AYO Myo SRI ASTAT RX1 AY1 MY1 SRO MSTAT TXO AR MR2 10 I7 SSTAT read only TX1 MRI MO M7 IMASK MRO LO L7 ICNTL EXAMPLE DM cntl_port0 AR DESCRIPTION Moves the contents of the source register to the data memory location specified in the instruction word The addressing mode is direct address ing designated by an immediate address value or by a label The data memory address is stored directly in the instruction word as a full 14 bit field Whenever a register that is less than 16 bits in length is written to memory the value written is either sign extended to the left if the source is a signed value or zero filled to the left if the source is an unsigned value The unsigned registers which are zero filled to the left are 10 through 17 LO through L7 CNTR PX ASTAT MSTAT SSTAT IMASK and ICNTL All other registers are sign extended to the left The contents of the source are always right justified in the destination location after the write bit 0 maps to bit 0 ADSP 218x Instruction Set Reference 4 127 Move Instructions Note that whenever MR1 is loaded with data it is sign extended
53. notation 4 31 Subroutine modules and comment information table 3 2 Subtract X Y Subtract X Y with borrow 4 35 Subtract Y X Subtract Y X with borrow 4 39 System status SSTAT register 2 6 4 117 4 127 4 157 T Termination Codes for DO UNTIL A 22 Timer Registers TCOUNT 2 8 TPERIOD 2 8 TSCALE 2 8 Tools 1 3 TOPPCSTACK instruction 2 6 4 156 4 158 Transmit TX register 2 8 2 16 4 119 Type 1 ALU MAC with Data and Program Memory Read A 2 Type 10 Conditional Jump Immediate Address A 4 I 6 ADSP 218x DSP Instruction Set Reference Type 11 Do Until A 4 Type 12 Shift with Data Memory Read Write A 4 Type 13 Shift with Program Memory Read Write A 4 Type 14 Shift with Internal Data Register Move A 4 Type 15 Shift Immediate A 5 Type 16 Conditional Shift A 5 Type 17 Internal Data Move A 5 Type 18 Mode Control A 6 Type 19 Conditional Jump Indirect Address A 6 Type 2 Data Memory Write Immediate Data A 2 Type 20 Conditional Return A 6 Type 21 Modify Address Register A 7 Type 22 Reserved A 7 Type 23 DIVQ A 7 Type 24 INDEX DIVS A 7 Type 25 Saturate MR A 7 Type 26 Stack Control A 7 Type 27 Call or Jump on Flag In A 8 Type 28 Modify Flag Out A 8 Type 29 I O Memory Space Read Write A 8 Type 3 Read Write Data Memory Immediate Address A 2 Type 30 No Operation NOP A 8 Type 31 Idle A 8 Idle n Slow Idle A 9 Type 4 ALU MAC with Data Memory Read Write A 2 Type 5 ALU MAC
54. numerator ar denominator ADSP 218x Instruction Set Reference 4 71 ALU Instructions outputs ar corrected quotient intermediate scratch registers mrO af KJ signed_div mrO ar ar abs ar save copy of denominator make it positive divs ayl ar diva ar divq ar divq ar divq ar divq ar divq ar divq ar divq ar divq ar divq ar divq ar divq ar divq ar divq ar divq ar ar ay0 af pass mr0 place output in ar get sign of denominator if LT ar ay0 if neg place inverted output in ar FESS SEE ALSO e X Operand Codes on page A 24 e Y Operand Codes on page A 24 4 72 ADSP 218x Instruction Set Reference Instruction Set Generate ALU Status Only NONE SYNTAX NONE lt ALU gt lt ALU gt may be any unconditional ALU operation except DIVS or DIVQ EXAMPLES NONE AXO AYO NONE PASS SRO DESCRIPTION Perform the designated ALU operation generate the ASTAT status flags then discard the result value This instruction allows the testing of register values without disturbing the contents of the AR or AF registers Note that the following ALU operations of the ADSP 218x proces sors are exceptions ADD xop constant SUBTRACT X Y xop constant SUBTRACT Y X xop constant AND OR XOR xop constant PASS constant 0 1 1 TSTBIT SETBIT CLRBIT TGLBIT STATUS GENERATED See Table 4 11 on
55. numerator and a 16 bit denominator yielding a 16 bit quotient executes in 16 cycles Higher precision divides are also possible The division can be either signed or unsigned but both the numerator and denominator must be the same both signed or unsigned The pro grammer sets up the divide by sorting the upper half of the numerator in any permissible yop AY1 or AF the lower half of the numerator in AYO and the denominator in any permissible xop The divide operation is then executed with the divide primitives DIVS and DIVQ Repeated execution of DIVO implements a non restoring conditional add subtract division algo rithm At the conclusion of the divide operation the quotient will be in AYO To implement a signed divide first execute the DIVS instruction once which computes the sign of the quotient Then execute the DIVQ instruc tion for as many times as there are bits remaining in the quotient e g for a signed single precision divide execute DIVS once and DIVQ 15 times ADSP 218x Instruction Set Reference 4 65 ALU Instructions To implement an unsigned divide first place the upper half of the numer ator in AF then set the AQ bit to zero by manually clearing it in the Arithmetic Status Register ASTAT This indicates that the sign of the quo tient is positive Then execute the DIVQ instruction for as many times as there are bits in the quotient e g for an unsigned single precision divide execute DIVQ 16 times
56. otherwise AC Set if a carry is generated Cleared otherwise AS Affected only when executing the Absolute Value operation ABS Set if the source operand is negative lt MAC gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ MV Set if the accumulated product overflows the lower order 32 bits of the MR register Cleared otherwise ADSP 218x Instruction Set Reference 4 187 Multifunction Instructions lt SHIFT gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ SS Affected only when executing the EXP operation set if the source operand is negative Cleared if the number is positive INSTRUCTION FORMAT ALU MAC operation with Data Memory Write Instruction Type 4 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 1 G 1 Z AMF Yop Xop Dreg I M ALU MAC operation with Program Memory Write Instruction Type 5 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 0 1 1 Z AMF Yop Xop Dreg I Shift operation with Data Memory Write Instruction Type 12 M 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 1 0 O 1 G 1 JSF Xop Dreg I M Shift operation with Program Memory Write Instruction Type 13 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 1 JSF
57. pin 4 143 Modify register codes A 18 Move instructions 4 116 Overview 4 21 Summary of move instructions 4 3 Summary of syntax table 4 21 Multifunction instructions 4 174 Overview 4 7 Summary of instructions 4 4 Summary of valid combinations table 4 11 Multiplier feedback MF register 2 7 4 90 Multiplier input MX and MY registers 2 1 2 7 4 74 22 4 74 4 82 4 116 4 134 4 159 4 175 4 193 Multiplier result MR register 2 7 2 16 4 106 4 117 4 119 4 128 4 129 4 159 4 162 4 178 4 181 4 183 4 187 4 193 4 194 Multiply 4 74 with cumulative add 4 78 with cumulative subtract 4 82 I 4 ADSP 218x DSP Instruction Set Reference N Negate 4 53 No operation 4 173 NONE 4 72 A 3 Normalize 4 103 NOT 4 17 4 19 4 23 4 55 Notation 1 9 O Opcode definitions A 2 Opcode mnemonics A 10 Output formats 4 67 Overlays 2 17 OWRCNTR 2 6 P PASS 4 15 4 48 4 72 PC stack 4 156 PMOVLAY Register Update Instruction 4 165 POP 4 155 POP CNTR instruction 2 7 4 27 4 155 POP LOOP instruction 2 7 4 27 4 155 POP STS instruction 2 7 4 156 4 157 Processor registers reg and dreg table 4 22 Program Example 2 12 Interrupt routine discussion 2 15 Overview 2 1 Setup routine discussion 2 14 INDEX Program flow instructions 4 136 Summary of instructions table 4 24 Summary of program flow instructions 4 3 Program memory Bus exchange PX register 2 8 4 116 4 125 4 133 Destination codes A 18 Overlay P
58. pm pm_data var circ init24 coefficient taps coeff dat C section pm Interrupts start j FETS 0x0000 Reset vector np 3 a 5 Fin ct 5 c 4 rti 0x0004 IRQ2 PE ce P ae 0x0008 IRQL1 Et rti 0x000c IRQLO PES 0x0010 SPORTO Transmit i rti rti 0x0014 SPORTO Receive ris 0x0018 IRQE ECTS Ox001c BDMA ti rti 0x0020 SPORTI Transmit or IRQI1 rti Ox0024 SPORT1 Receive or IRQO e e SS Scere SoS SS Ke SS Fa n SS SS a Sy de Le ee ct s ct 2 12 ADSP 218x Instruction Set Reference Programming Model Pols ROIS ROIS PETs 0x0028 Timer rti rti rti rti Ox002c Power Down non maskable D section pm pm_code main 10 length data_buffer setup circular buffer length 14 length coefficient setup circular buffer m0 1 modify 1 for increment m4 1 through buffers i0 data_buffer point to start of buffer i4 coefficient point to start of buffer ax0 0 cntr length data_buffer initialize loop counter do clear until ce clear dm i0 m0 ax0 clear data buffer setup divide value for 8KHz RFS E ax0 0x00c0 dm SportO_Rfsdiv ax0 1 5385 MHz internal serial clock ax0 0x000c dm SportO_Sclkdiv ax0 multichannel disabled internally generated sclk receive f
59. rou tine is entered Any POP pops the value on the top of the designated stack and decrements the same stack pointer to point to the next lowest location in the stack POP STS causes the arithmetic status ASTAT mode status MSTAT and interrupt mask IMASK to be popped into these same registers This also happens automatically whenever a return from interrupt RTI is executed POP CNTR causes the counter stack to be popped into the down counter When the loop stack or PC stack is popped with POP LOOP or POP PC respectively the information is lost Returning from an interrupt RTI or subroutine RTS also pops the PC stack automatically 4 156 ADSP 218x Instruction Set Reference STATUS GENERATED See Table 4 11 on page 4 31 for register notation SSTAT PSE CSE SSE SSO LSE 7 6 5 4 3 2 1 0 LSO LSE SSO SSE CSO CSE PSO PSE PC Stack Empty set if a pop results in an empty program counter stack cleared otherwise Counter Stack Empty set if a pop results in an empty counter stack cleared otherwise Status Stack Empty for PUSH STS this bit is always cleared indicating status stack not empty For POP STS SSE is set if the pop results in an empty status stack cleared otherwise Status Stack Overflow for PUSH STS set if the status stack overflows oth erwise not affected Loop Stack Empty set if a pop results in an empty loop stack cleared oth erwise Note that once any Stack Overflow occur
60. than or equal LE A 12 ADSP 218x DSP Instruction Set Reference Instruction Coding Table A 4 Status Condition Codes Code Description Condition 0 0 0 Less than LT 0101 Greater than or equal GE 0 1 0 ALU Overflow AV 0 P NOT ALU Overflow NOT AV 000 ALU Carry AC 001 Not ALU Carry NOT AC 0 10 X input sign negative NEG 011 X input sign positive POS 0 0 MAC Overflow MV 0 1 Not MAC Overflow NOT MV 10 Not counter expired NOT CE 11 Always true CP Counter Stack Pop Codes Table A 5 Counter Stack Pop Codes Code Description 0 No change 1 Pop ADSP 218x DSP Instruction Set Reference A 13 Opcode Mnemonics D Direction Codes Table A 6 Memory Access Direction Codes Code Description 0 Read 1 Write DD Double Data Fetch Data Memory Destination Codes Table A 7 Data Memory Destination Codes Code Register 0 0 AXO 01 AX1 1 0 MXO 1 1 MXI1 DREG Data Register Codes Table A 8 DREG Selection Codes Code Register 0 0 0 0 AXO 0001 AX1 0 0 1 0 MX0 A 14 ADSP 218x DSP Instruction Set Reference Instruction Coding Table A 8 DREG Selection Codes Code Register 0011 MxX1 0 0 0 AYO 0 0 1 AY1 0 1 0 MYO 0 11 MY1 00 0 SI 001 SE 010 AR 011 MRO 0 0 MRI 01 MR2 1 0 SRO 11 SRI
61. the inter rupt is serviced The ADSP 218x family s interrupt controller has no knowledge of the PMOVLAY and DMOVLAY registers Therefore the values of these registers must be saved or restored by the programmer in the interrupt service routine 2 18 ADSP 218x Instruction Set Reference Programming Model Whenever the interrupt service routine is located within the fixed program memory region no special context saving of the overlay registers is required However if you would like to place the ISR within an overlay page some additional instructions are needed to facilitate the saving or restoring of the PMOVLAY and DMOVLAY registers The interrupt vector table features only four instruction locations per interrupt Listing 2 2 is an example of a four instruction implementation that restores the PMOVLAY register after an interrupt Listing 2 3 PMOVLAY Register Restoration Interrupt Vector ax0 PMOVLAY save PMOVLAY value into ax0 Toppcstack ax0 push PMOVLAY value onto PC stack Jump My_ISR jump to interrupt subroutine Rts placeholder in vector table 4 locations total My_ISR is ISR code goes here jump I_Handler use instead of rti to restore PMOVLAY reg I_Handler this subroutine should reside in fixed PM ax0 Toppcstack pop PMOVLAY value into ax0 nop one cycle effect latency rti return from interrupt ADSP 218x Instruction Set Reference 2 19 Har
62. these manuals use the Help Topics command in the VisualDSP environment s Help menu and select the Online Manuals book From this Help topic you can open any of the manuals which are in Adobe Acrobat PDF format 1 8 ADSP 218x DSP Instruction Set Reference Conventions Introduction Throughout this manual you will find tables summarizing the syntax of the instruction groups Table 1 1 identifies the notation conventions that apply to all chapters Note that additional conventions which apply only to specific chapters may appear throughout this manual Table 1 1 Instruction set notation Notation Meaning UPPERCASE Explicit syntax assembler keyword The assembler is case insensitive A semicolon terminates an instruction line A comma separates multiple parallel instructions in the same instruction line single line comment multi line comment Tor indicate comments or remarks that explain program code but that the assembler ignores For more details see the Assembler Manual for ADSP 218x Family DSPs operands Some instruction operands are shown in lowercase letters These operands may take different values in assembly code For example the operand yop may be one of several registers AYO AY 1 or AF lt exp gt Denotes exponent shift value in Shift Immediate instruc tions must be an 8 bit signed integer constant lt data gt Denotes an immedia
63. value from memory at the end of the cycle For example 1 MR MR MXO MYO UU MXO DM IO MO MYO PM 14 M4 is a legal version of this multifunction instruction and is not flagged by the assembler Changing the order of clauses as in 2 MXO DM TO MO MYO PM I4 M4 MR MR MXO MYO CUU results in an assembler warning but assembles and executes exactly as the first form of the instruction Note that reading example 2 from left to right may suggest that the data memory value is loaded into MX0 and MYO and subsequently used in the computation all in the same cycle In fact this is not possible The left to right logic of example 1 suggests the operation of the instruction more closely Regardless of the apparent logic of reading the instruction from left to right the read first write second operation of the processor determines what actually happens ADSP 218x Instruction Set Reference 4 193 Multifunction Instructions STATUS GENERATED See Table 4 11 on page 4 31 for register notation All status bits are affected in the same way as for the single operation ver sion of the selected arithmetic operation lt ALU gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ z x x AZ Set if result equals zero Cleared otherwise AN Set if result is negative Cleared otherwise AV Set if an overflow is generated Cleared otherwise AC Set if a carry is generated Cleared otherwise AS Affected only
64. 0 01 01 bit 9 0400 10 10 01 bit 10 0800 10 11 01 bit 11 1000 11 00 01 bit 12 2000 11 01 01 bit 13 4000 11 10 01 bit 14 8000 11 11 01 bit 15 FFFE 00 00 11 bit 0 FFFD 00 01 11 bit 1 FFFB 00 10 11 bit 2 FFF7 00 11 11 bit 3 FFEF 01 00 11 bit 4 FFDF 01 01 11 bit 5 FFBF 01 10 11 bit 6 FF7F 01 11 11 bit 7 FEFF 10 00 11 bit 8 A 26 ADSP 218x DSP Instruction Set Reference Instruction Coding Table A 27 ALU MAC Constant Codes Constant YY CG BO Bit hex FDFF 10 01 11 bit 9 FBFF 10 10 11 bit 10 F7FF 10 11 11 bit 11 EFFF 11 00 11 bit 12 DFFF 11 01 11 bit 13 BFFF 11 10 11 bit 14 7FFF 11 11 11 bit 15 ADSP 218x DSP Instruction Set Reference A 27 Opcode Mnemonics A 28 ADSP 218x DSP Instruction Set Reference INDEX A Absolute value ABS 4 16 4 57 4 177 4 182 4 187 4 194 Add Add with carry 4 32 ALU feedback AF register 2 7 4 15 4 16 4 21 4 45 4 72 ALU input AX and AY registers 1 9 2 1 2 7 4 84 14 4 30 4 72 4 116 4 134 4 159 4 192 ALU instructions 4 32 Instruction syntax table 4 15 Overview 4 14 Summary of ALU instructions 4 1 ALU result AR register 2 7 4 8 4 9 4 10 4 14 4 66 4 72 4 78 4 82 4 97 4 116 4 162 4 176 4 181 ALU MAC with data and program memory read 4 192 AME ALU MAC function codes A 10 Arithmetic shift 4 97 Arithmetic shift immediate 4 112 Arithmetic status
65. 1 R SR1 R MX0 TIL CE Loop on 243 Scale 0 MYO PM 14 M4 SS MX1 DM 10 MO0 YOCSS MYO PM IA4 YO SS MXO DM IO YO SS MXO DM I0 X1 MR MR MXO MYO DM IO MO SRI SR ASHIFT MRI DM IO MO MX0 DM I0 M3 SR1 RTS Software Examples Il gt scaling factors for each biquad section L1 0 in the case of a single biquad number of biquad sections for multiple biquads I4 gt scaled biquad coefficients L4 5 x number of biquads 0 M 1 1 in the case of multiple biquads 0 in the case of a single biquad 1 length of delay line buffer All coefficients and data values are assumed to be in 1 15 format ce for each biquad factor for biquad MYO PM 14 M4 M4 MO MYO PM I4 M4 M1 MYO PM 14 M4 RND HI ADSP 218x Instruction Set Reference 3 9 Sine Approximation Sine Approximation The following formula approximates the sine of the input variable x in radians y x sin x 3 140625 4 0 02026367 5 325196 0 5446778 4 1 800293 Bj T T where 0 lt x lt 3 The approximation is a 5 order polynomial fit accurate for any value of x from 0 to 90 the first quadrant However because sin x sin x and sin x sin 180 x you can infer the sine of any angle from the sine of an angle in the first quadrant The routine that implements this sine approximation accurate to within two LSBs is shown in Listing 3 3
66. 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 1 0 0 DATA DREG DATA contains the immediate value to be loaded into the Data Register destination location The data is right justified in the field so the value loaded into an N bit destination register is contained in the lower order N bits of the DATA field To choose the data register DREG refer to the table DREG Selection Codes on page A 14 ADSP 218x Instruction Set Reference 4 119 Move Instructions Load Non Data Register Immediate Instruction Type 7 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 0 0 1 1 RGP DATA REG DATA contains the immediate value to be loaded into the Non Data Regis ter destination location The data is right justified in the field so the value loaded into an N bit destination register is contained in the lower order N bits of the DATA field To choose the source register group SRC RGP and the source register SOURCE REG refer to the table Register Selection Codes on page A 19 4 120 ADSP 218x Instruction Set Reference Data Memory Read Direct Address SYNTAX reg DM lt addr gt Permissible registers AX0 MX0 AXI MXI AYO MYO AY1 MY1 AR MR2 MRI MRO EXAMPLE SI DM ad_portod DESCRIPTION SI SE SRI SRO 10 17 MO M7 LO L7 SB PX ASTAT MSTAT IMASK ICNTL CNTR OWRCNTR write only IFC write only The Read instruction moves the content
67. 18x Instruction Set Reference Shift operation with Program Memory Read Instruction Type 13 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 0 0 0 1 0 0 O 1 0 SF Xop Dreg I M L3 Result register Dreg Destination register SF Shifter operation AMF ALU MAC operation Yop Y operand Xop X operand G Data Address Generator M Modify register SEE ALSO Indirect address register e DREG Selection Codes on page A 14 e ALU MAC Result Register Codes on page A 25 e Shifter Function Codes on page A 21 e DAG Selection Codes on page A 17 e Index Register Selection Codes on page A 17 e Modify Register Selection Codes on page A 18 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 e AMF Function Codes on page A 10 ADSP 218x Instruction Set Reference 4 179 Multifunction Instructions Computation with Register to Register Move SYNTAX lt ALU gt dreg dreg lt MAC gt lt SHIFT gt Permissible dregs AXO MX0 SI AX1 MxX1 SE AYO MY0 SRO AY1 MY1 SRI AR MRO MRI MR2 DESCRIPTION Perform the designated arithmetic operation and data transfer The con tents of the source are always right justified in the destination register after the read The computation must be unconditional All ALU MAC and Shifter operations are permitted except Shift Immediate and ALU DIVS and DIVQ instructions
68. 2 MRI MRO EXAMPLE PM 16 M5 AR DESCRIPTION The Program Memory Write Indirect instruction moves the contents of the source to the program memory location specified in the instruction word The addressing mode is register indirect with post modify For lin 4 132 ADSP 218x Instruction Set Reference ear i e non circular indirect addressing the L register corresponding to the I register used must be set to zero The 16 most significant bits of the Program Memory Data bus PMD 4 are loaded from the source regis ter with bit PMDg aligned with bit 0 of the source register right justification The 8 least significant bits of the Program Memory Data bus PMD7 are loaded from the PX register Whenever a source register of length less than 16 bits is written to memory the value written is sign extended to form a 16 bit value STATUS GENERATED No status bits affected INSTRUCTION FORMAT ALU MAC Operation with Program Memory Write Instruction Type 5 as shown below 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 1 O0 1 1 0 AMF 0 0 0 0 0 DREG I M AMF specifies the ALU or MAC operation to be performed in parallel with the Program Memory Write In this case AMF 00000 indicating a no operation for the ALU MAC function To choose a data register DREG refer to the table DREG Selection Codes on page A 14 I specifies the indirect address pointer 1 regist
69. 2 3 Overview Data Address Generators DAGI1 and DAG2 each have twelve 14 bit registers four index 1 regis ters for storing pointers four modify M registers for updating pointers and four length L registers for implementing circular buffers DAG1 addresses data memory only and has the capability of bit reversing its out puts DAG2 addresses both program and data memory and can provide addresses for indirect branching jumps and calls as well as for accessing data The following example is an indirect data memory read from the location pointed to by 10 Once the read is complete 10 is updated by MO AXO DM I0 MO The following example is an indirect program memory data write to the address pointed to by 14 with a post modify by M5 PM I4 M5 MR1 The following example is an example of an indirect jump JUMP 14 Always Initialize L Registers The ADSP 218x processors allow two addressing modes for data memory accesses direct and register indirect Indirect addressing is accomplished by loading an address into an I index register and specifying one of the available M modify registers The L registers are provided to facilitate wraparound addressing of circular data buffers A circular buffer is only implemented when an L register is set to a non zero value S For linear i e non circular indirect addressing the L register corre sponding to the I register used must be set to zero Do not assume that the L r
70. 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 1 1 10 0 0 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF 01000 for Transfer MR operation Note that this instruction is a special case of MR xop yop with yop set to zero Destination register COND Condition 4 94 ADSP 218x Instruction Set Reference SEE ALSO Instruction Set IF Condition Codes Table 4 9 on page 4 25 Status Condition Codes on page A 12 ALU MAC Result Register Codes on page A 25 AMF Function Codes on page A 10 ADSP 218x Instruction Set Reference 4 95 MAC Instructions Conditional MR Saturation SYNTAX IF MV SAT MR DESCRIPTION Test the MV MAC Overflow bit in the Arithmetic Status Register ASTAT and if set then saturate the lower order 32 bits of the 40 bit MR register if the MV is not set then perform a no operation Saturation of MR is executed with this instruction for one cycle only MAC saturation is not a continuous mode that is enabled or disabled The satu ration instruction is intended to be used at the completion of a series of multiply accumulate operations so that temporary overflows do not cause the accumulator to saturate The saturation result depends on the state of MV and on the sign of MR the MSB of MR2 The possible results after execution of the saturation instruc tion are shown in the table below MV_ MSB MR Conten
71. 4 13 12 11109 8 7 6 5 4 3 2 10 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Type 26 Stack Control 23 22 21 20 19 18 17 16 15 14 13 12 11109876543 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0000 0 0 Pp Lp Cp Spp ADSP 218x DSP Instruction Set Reference A 7 Opcode Definitions Type 27 Call or Jump on Flag In 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 Address Addr FIC S 12 LSBs 2 MSB s Type 28 Modify Flag Out 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6543210 0 0 0 0 0 0 1 0 0 0 0 0 FO FO FO FO COND FL2 FLI FLO FLAG OUT Type 29 1 0 Memory Space Read Write 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 D ADDR DREG Type 30 No Operation NOP 23 22 21 20 19 18 17 16 15 14 13 12 1110987654321 0 0 0 0 00 0 0 0 0 O 0 0 0 0 000000000 0 Type 31 Idle 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A 8 ADSP 218x DSP Instruction Set Reference Instruction Coding Type 31 Idle n Slow Idle 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 DV ADSP 218x DSP Instruction Set Reference A 9 Opcode Mnemonics Opcode Mnemonics AMF ALU MAC Function Codes N
72. 5 Since the program memory hardware overlay regions reside in address locations PM 0x2000 through 0x3fff programs are restricted to execute the pmovlay instruction from within the fixed program memory region located at addresses PM 0x0000 through 0x1FFF If a pmovlay instruction were to be executed from a program memory hardware overlay page the next instruction would be fetched and executed from the subsequent address of the new hardware overlay page In this sce nario there is no possibility to specify a well defined address of the target program memory overlay region Therefore the portion of your program that controls the management of the program memory overlay pages must reside within the fixed non overlay program memory region If the program flow requires execution from a module that resides in an overlay region it is good programming practice to have the calling func tion access the overlay module using a CALL instruction versus a JUMP instruction Executing a call instruction pushes the address of the subse quent address after the call instruction onto the program counter stack which will be the return address after the overlay module is completed Upon return from the overlay subroutine via the rts instruction program execution will resume with the instruction following the subroutine call The example below shows one application of switching between program memory overlay regions at runtime ADSP 218x Instruction Set
73. 6 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 1 O 1 Addr TERM Type 12 Shift with Data Memory Read Write 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 G D SF Xop Dreg Type 13 Shift with Program Memory Read Write 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 DSF Xop Dreg Type 14 Shift with Internal Data Register Move 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 O JSF Xop Dreg dest Dreg source A 4 ADSP 218x DSP Instruction Set Reference Instruction Coding Type 15 Shift Immediate 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 O 1 1 1 1 0 JSF Xop lt exp gt Type 16 Conditional Shift 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 O SF Xop 0 0 0 0 COND Type 17 Internal Data Move 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 0 0 1 1 0 1 0 0 O 0 JDST SRC DEST SOURCE RGP RGP REG REG ADSP 218x DSP Instruction Set Reference A 5 Opcode Definitions Type 18 Mode Control 23 22 21 20 19 18 17 16 15 14 13 12 11 1098 7 6 5 4 3 2 10 0 0 0 0 1 1 O0 0 TI MM AS O
74. 6 7 8 ADSP 2188 processor only EXAMPLE DMOVLAY 1 Write to dmovlay register Read from dmovlay register into ax0 register AXO DMOVLAY DMOVLAY PMOVLAY Write to DMOVLAY from PMOVLAY DM Ox0000 DMOVLAY Write DMOVLAY to data memory DESCRIPTION The DMOVLAY write instruction switches the context of the hardware data memory overlay region to the specific region specified by the permissible data value written to the DMOVLAY register The DMOVLAY read instruction moves the value from the DMOVLAY register into one of the permissible reg isters listed above ADSP 218x Instruction Set Reference 4 169 MISC Instructions STATUS GENERATED No status bits affected INSTRUCTION FORMAT Read Write Data Memory Immediate Address Instruction Type 3 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 1 0 0 D RGP ADDR REG Load Non data Register Immediate Instruction Type 7 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 1 1 RGP DATA REG Load Non data Register Immediate Instruction Type 17 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 0 0 1 1 0 1 0 0 0 0 DST SRC_ DEST SOURCE RGP RGP REG REG To choose the source register group SRC RGP and the source register SOURCE REG refer to the table Register Selection Codes on page A 19 To choose the destination regist
75. 91 8192 8193 16383 16384 16385 32766 32767 1 2 3 4 5 6 8 9 10 16 17 18 32 33 34 64 65 66 128 129 130 256 257 258 512 513 514 1024 1025 1026 2048 2049 2050 4096 4097 4098 8192 8193 8194 16384 16385 16386 32767 32768 EXAMPLES Conditional pass IF GE AR PASS AYO Unconditional pass AR PASS 0 AR PASS 8191 Single cycle register swap ADSP 218x Instruction Set Reference 4 49 ALU Instructions AR PASS AXO AXO AR Clip AXO by AYO AR SIGNCAXO MINCAXO AYO DIS AR_SAT Disable AF AYO AXO AR AX0 Check if X gt Y IF GT AR PASS AYO If yes saturate X By Y IF LT AF AXO AYO PRN Ce EXT SX Er Y IF LT AR AYO If X lt Y saturate X By Y DESCRIPTION E xI X E Test the optional condition and if true pass the source operand unmodi fied through the ALU block and store in the destination register If the condition is not true perform a no operation Omitting the condition per forms the PASS unconditionally The source operand is contained in the data register or constant specified in the instruction PASS 0 is one method of clearing AR PASS 0 can also be combined with memory reads and writes in a multifunction instruction to clear AR The PASS instruction performs the transfer to the AR or AF register and affects the
76. A 24 e Y Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 39 ALU Instructions Subtract Y X Subtract Y X with Borrow SYNTAX IF cond JAR yop xop AF xop C 1 2 xop C 1 xop constant xop constant C 1 Permissible xops Permissible yops Permissible status conditions AXO MR2 AYO EQ LE AC AXI MRI AY1 NE NEG NOT AC AR MRO AF GT POS MV SRI GE AV NOT MV SRO LT NOT AV NOT CE Permissible constants 0 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32767 2 3 5 9 17 33 65 129 257 513 1025 2049 4097 8193 16385 32768 EXAMPLE IF GT AR AYO AXO C 13 DESCRIPTION Test the optional condition and if true then perform the specified sub traction If the condition is not true then perform a no operation Omitting the condition performs the subtraction unconditionally The subtraction operation subtracts the second source operand from the first source operand and optionally adds the ALU Carry bit AC minus 1 0x0001 and stores the result in the destination register The C 1 quan tity effectively implements a borrow capability for multiprecision 4 40 ADSP 218x Instruction Set Reference Instruction Set subtractions The operands are contained in the data registers or constant specified in the instruction STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS
77. ADSP 218x DSP Instruction Set Reference First Edition February 2001 Part Number 82 002000 01 Analog Devices Inc Digital Signal Processor Division One Technology Way ANALOG Norwood Mass 02062 9106 DEVICES Copyright Information 1996 2001 Analog Devices Inc ALL RIGHTS RESERVED This document may not be reproduced in any form without prior express writ ten consent from Analog Devices Inc Printed in the USA Disclaimer Analog Devices Inc reserves the right to change this product without prior notice Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli cation or otherwise under the patent rights of Analog Devices Inc Trademark and Service Mark Notice The Analog Devices logo VisualDSP the VisualDSP logo EZ ICE and EZ LAB are registered trademarks and the White Mountain logo Apex ICE Mountain ICE Mountain ICE WS Summit ICE Trek ICE Vista ICE and The DSP Collaborative are trademarks of Analog Devices Inc Microsoft and Windows are registered trademarks and Windows NT is a trademark of Microsoft Corporation Adobe and Acrobat are registered trademarks of Adobe Corporation All other brand and product names are trademarks or service marks of their respective owners
78. AQ AS AC AV AN AZ _ _ k 0 0 AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Always cleared AC Always cleared INSTRUCTION FORMAT xop AND OR XOR constant Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 0 0 1 0 0 Z AMF YY Xop CC BO COND AMF specifies the ALU or MAC operation in this case ADSP 218x Instruction Set Reference 4 47 ALU Instructions AMF 10110 for AND operation AMF 11101 for OR operation AMF 11110 for XOR operation 2 Destination register COND Condition Xop X operand BO CC and YY specify the constant SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e BO CC and YY ALU MAC Constant Codes on page A 25 e ALU MAC Result Register Codes on page A 25 e X Operand Codes on page A 24 4 48 ADSP 218x Instruction Set Reference Clear PASS Instruction Set SYNTAX IF cond AR PASS xop AF yop constant Permissible xops Permissible yops Permissible conds AX0 MR2 AYO EQ LE AC AXI MRI AY1 NE NEG NOT AC AR MRO AF GT POS MV SRI GE AV NOT MV SRO LT NOT AV NOTCE Permissible constants 0 1 2 3 4 5 7 8 9 15 16 17 31 32 33 63 64 65 127 128 129 255 256 257 511 512 513 1023 1024 1025 2047 2048 2049 4095 4096 4097 81
79. ASTAT register 2 1 2 6 2 7 2 18 4 46 4 49 4 65 4 67 4 72 4 95 4 104 4 116 4 127 4 147 4 156 B Bit manipulation TSTBIT SETBIT CLRBIT TGLBIT 4 45 Bit reverse subroutine 3 21 Bitwise logic AND OR XOR 4 42 Block exponent adjust 4 110 C CALL instruction 2 17 4 5 4 23 4 139 4 141 Cascaded biquad IIR filter example 3 8 Clear 4 90 CLKOUT 2 9 4 153 Computation Units 2 7 With data register move 4 10 With memory read 4 9 4 174 With memory write 4 9 4 185 With register to register move 4 180 Condition codes A 12 Conditional instructions 1 2 Conditional MR saturation 4 95 Contact information 1 7 Conventions 1 9 ADSP 218x DSP Instruction Set Reference I 1 INDEX Counter CNTR register 2 5 2 7 2 16 4 23 4116 4 127 4 136 4 149 Counter stack pop codes A 13 Customer support 1 7 Cycle conditions 4 28 D DAG register DAG codes A 17 DAGI 2 3 2 4 4 11 4 26 DAG2 2 3 2 4 4 11 4 23 Use with Toppstack instruction 4 159 Data address generator 4 124 4 151 4 172 Data address generators 2 4 Data and program memory read 4 8 4 190 Data memory Destination codes A 14 DMOVLAY register restoration example 2 20 Overlay DMOVLAY register 2 20 Read direct address 4 121 Read indirect address 4 123 Write direct address 4 127 Write indirect address 4 129 Data register codes A 14 Decrement 4 62 Derive exponent 4 106 Development process 3 3 Development process figure 3 4 Development
80. ASTAT status flags for xop yop 1 0 1 only This instruction is different from a register move operation which does not affect any status flags The PASS constant operation using any constant other than 1 0 or 1 causes the ASTAT status flags to be undefined The PASS constant operation using any constant other than 1 0 or 1 may not be used in multifunction instructions 4 50 ADSP 218x Instruction Set Reference Instruction Set STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Always cleared AC Always cleared INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF 10000 for PASS yop AMF 10011 for PASS xop AMF 10001 for PASS 1 AMF 11000 for PASS 1 Note the following e PASS xop is a special case of xop yop with yop 0 e PASS 1 is a special case of xop 1 with yop 0 e PASS yop 1 isa special case of yop 1 with yop 0 Z Destination register Yop Y operand Xop X operand COND Condition ADSP 218x Instruction Set Reference 4 51 ALU Instructions Conditional ALU MAC operation In
81. DLOOP MR MR MXO MYO SS MXO DM IO MO MR MR MXO MYO SS DESCRIPTION Test the optional condition and if true then multiply the two source operands add the product to the present contents of the MR register and store the result in the destination location If the condition is not true then perform a no operation Omitting the condition performs the multi ply accumulate unconditionally The operands are contained in the data registers specified in the instruction When MF is the destination operand only bits 31 16 of the 40 bit result are stored in MF The ADSP 218x processors support the xop xop squaring operation Both xops must be in the same register This option allows single cycle X and LX instructions The data format selection field to the right of the two operands specifies whether each respective operand is in signed S or unsigned U format The xop is specified first and yop is second If the xop xop operation is used the data format selection field must be UU SS or RND only There is no default one of the data formats must be specified If RND Round is specified the MAC multiplies the two source operands adds the product to the current contents of the MR register rounds the result to the most significant 24 bits or rounds bits 31 16 to the nearest 16 bits if there is no overflow from the multiply accumulate and stores the result in the destination register The two multiplication ope
82. DSP 218x Digital Signal Processor DSP The syn tax descriptions for instructions that execute within the DSP s processor core include processing elements program sequencer and data address generators For architecture and design information on the DSP see the ADSP 218x DSP Hardware Reference Audience DSP system designers and programmers who are familiar with signal pro cessing concepts are the primary audience for this manual This manual assumes that the audience has a working knowledge of microcomputer technology and DSP related mathematics DSP system designers and programmers who are unfamiliar with signal processing can use this manual but should supplement this manual with other texts describing DSP techniques All readers particularly programmers should refer to the DSP s develop ment tools documentation for software development information For additional suggested reading see the section For More Information About Analog Products on page 1 6 ADSP 218x DSP Instruction Set Reference 1 1 Contents Overview Contents Overview The Instruction Set Reference is a four chapter book that describes the instructions syntax for the ADSP 218x DSP Chapter one provides introductory information including contacts at Ana log Devices an overview of the development tools related documentation and conventions Chapter two describes the computational units of the ADSP 218x DSP and provides a programming example w
83. ES RND GE AV NOT MV Conditional transfer MR IF EQ MF MR RND Load MR register MRO DM MRO_VAL MR1 DM MR1_VAL MR2 DM MR2_VAL MR MR IF MV SAT MR DESCRIPTION Instruction Set LT NOT AV NOT CE Update the MV flag Test the optional condition and if true then perform the MR transfer according to the description below If the condition is not true then per form a no operation Omitting the condition performs the transfer unconditionally ADSP 218x Instruction Set Reference 4 93 MAC Instructions Since RND is optional the MR MR instruction can be used to update the MV flag when the MR register is loaded by register moves This instruction actually performs a multiply accumulate specifying yop 0 as a multiplicand and adding the zero product to the contents of MR The MR register may be optionally rounded at the boundary between bits 15 and 16 of the result by specifying the RND option If MF is specified as the destination bits 31 16 of the result are stored in MF If MR is the desti nation the entire 40 bit result is stored in MR STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ _ _ _ MV Set on MAC overflow if any of upper 9 bits of MR are not one or zero Cleared otherwise INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21
84. L BR JSR GM 0 0 Table A 1 Mode Control Codes Mode Meaning Code Meaning SR Secondary register bank 1 1 Enable mode BR Bit reverse mode 1 0 Disable mode OL ALU overflow latch mode 0 1 No change AS AR register saturate mode 0 0 No change MM Alternate multiplier placement mode GM GO mode enable means exe cute internal code if possible TI Timer enable Type 19 Conditional Jump Indirect Address 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 I 0 S COND Type 20 Conditional Return 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 0000 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 T COND A 6 ADSP 218x DSP Instruction Set Reference Instruction Coding Type 21 Modify Address Register 23 22 21 20 19 18 17 16 15 14 13 12 111009876543 21 0 0 0 0 0 1 0 0 1 0 0 0 0 O 0 000001GI M Type 22 Reserved 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COND Type 23 DIVQ 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43210 0 0 0 0 0 1 1 1 0 0 0 1 0 Xop 0 0 0 0 0 0 0 Type 24 DIVS 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 0 0 0 1 1 0 0 0 0 Yop Xop 0 0 0 0 0 0 0 Type 25 Saturate MR 23 22 21 20 19 18 17 16 15 1
85. LU Instructions Absolute Value ABS SYNTAX IF cond J i j ABS xop AF Permissible xops Permissible conds AX0 MR2 EQ LE AC AXI MRI NE NEG NOT AC AR MRO GT POS MV SRI GE AV NOT MV SRO LT NOT AV NOT CE EXAMPLES Conditional instruction IF NEG AF ABS AXO Clip AXO by AYO AR sign AX0 min AX0 AY0 ENA AR SAT Enable AR ABS AXO Modify AS flag AF AYO AR Check if ABS X gt Y IF LT AR PASS AYO If yes saturate X by Y IF NEG AR AR JETT X lt 0 4 58 ADSP 218x Instruction Set Reference Instruction Set DESCRIPTION Test the optional condition and if true then take the absolute value of the source operand and store in the destination location If the condition is not true then perform a no operation Omitting the condition performs the absolute value operation unconditionally The source operand is con tained in the data register specified in the instruction STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ 0 x AZ Set if the result equals zero Cleared otherwise AN Set if xop is 0x8000 Cleared otherwise AV Set if xop is 0xX8000 Cleared otherwise AC Always cleared AS Set if the source operand is negative Cleared otherwise INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 0 0 1 0
86. M ADSP 2186M ADSP 2188M ADSP 2189M ADSP 2188N ADSP 2185N ADSP 2186N ADSP 2187N and ADSP 2189N and up to seven extra wait state cycles for all other ADSP 218x models may be added to the processor s access time for external memory Extra cycles inserted due to wait states are in addition to any cycles caused by multiple off chip accesses Wait state programming is described in the ADSP 218x DSP Hardware Reference Chapter 8 Memory Interface 4 28 ADSP 218x Instruction Set Reference Instruction Set Wait states and multiple off chip memory accesses are the two cases when an extra cycle is generated during instruction execution The following case SPORT autobuffering and DMA causes the insertion of extra cycles between instructions SPORT Autobuffering and DMA If serial port autobuffering or DMA is being used to transfer data words to or from internal memory then one memory access is stolen for each transfer The stolen memory access occurs only between complete instruc tions If extra cycles are required to execute any instruction for one of the two reasons above the processor waits until it is completed before steal ing the access cycle Instruction Set Syntax The following sections describe instruction set syntax and other notation conventions used in the reference page of each instruction Punctuation and Multifunction Instructions All instructions terminate with a semicolon A comma separates th
87. MAT Idle Instruction Type 31 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 0 0 0 0 0 0 1 O0 1 00000 0 0 0 0 0 0 0 0 0 0 Slow Idle Instruction Type 31 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 oO Z DV Clock divisor SEE ALSO e Slow Idle Divisor Codes on page A 16 4 154 ADSP 218x Instruction Set Reference MISC Instructions Stack Control SYNTAX PUSH STS POP CNTR POP PC POP LOOP POP EXAMPLE POP CNTR POP PC POP LOOP C style break instruction DO MYLOOP UNTIL FOREVER IF FLAG_IN JUMP MYLOOP 1 Leave the loop MYLOOP lt ANY INSTRUCTION gt POP PC POP LOOP Pop PC and loop stack The loop counter stack must be popped whenever a counter based loop is aborted in this way DESCRIPTION Stack Control pushes or pops the designated stack s The entire instruc tion executes in one cycle regardless of how many stacks are specified The PUSH STS Push Status Stack instruction increments the status stack pointer by one to point to the next available status stack location and ADSP 218x Instruction Set Reference 4 155 MISC Instructions pushes the arithmetic status ASTAT mode status MSTAT and interrupt mask register IMASK onto the processor s status stack Note that the PUSH STS operation is executed automatically whenever an interrupt service
88. MER MODIFY 0 0 Me 1 1 2 2 3 3 4 4 5 5 6 6 7 7 LIF cond SET FLAG_OUT peal RESET FLO TOGGLE FLI FL2 ENA JINTS a ADSP 218x Instruction Set Reference 4 27 Extra Cycle Conditions Extra Cycle Conditions All instructions execute in a single cycle except under certain conditions as explained below Multiple Off Chip Memory Accesses The data and address busses of the ADSP 218x processors are multiplexed off chip Because of this occurance the processors can perform only one off chip access per instruction in a single cycle If two off chip accesses are required such as the instruction fetch and one data fetch or data fetches from both program and data memory then one overhead cycle occurs In this case the program memory access occurs first followed by the data memory access If three off chip accesses are required the instruction fetch as well as data fetches from both program and data memory then two overhead cycles occur A multifunction instruction requires three items to be fetched from mem ory the instruction itself and two data words No extra cycle is needed to execute the instruction as long as only one of the fetches is from external memory This excludes external wait states or bus request holdoffs Two fetches must be from on chip memory either PM or DM Wait States All family processors allow the programming of wait states for external memory chips Up to 15 extra wait state cycles for the ADSP 2185
89. MOVLAY registers 2 18 2 20 PMOVLAY register restoration example 2 19 Read indirect address 4 125 Write indirect address 4 132 Program sequencer 2 5 Programming model overview 3 1 PUSH STS instruction 2 7 4 155 4 157 Push Pop codes A 22 R Radix 2 decimation in time FFT example 3 14 Receive RX register 2 8 2 16 4 119 Receive frame RFSDIV register 2 9 Register move 4 116 Registers Codes A 19 Table of Registers 2 3 ADSP 218x DSP Instruction Set Reference I 5 INDEX Return from interrupt RTI instruction 2 7 4 6 4 23 4 24 4 147 4 156 Return from subroutine RTS instruction 2 17 4 6 4 23 4 24 4 145 4 156 Return type codes A 22 S Serial clock SCLKDIV register 2 8 Serial port SPORT 2 8 4 29 SPORT autobuffering and DMA 4 29 SPORT enables 2 10 Shifter bit SB register 2 7 4 10 4 19 4 20 4 110 Shifter exponent SE register 2 8 4 19 4 98 4 100 4 159 Shifter function codes A 21 Shifter input SB register 4 100 4 103 4 110 4 121 4 159 Shifter input SI register 2 7 2 16 4 19 4 97 Shifter instructions 4 97 Summary of instructions 4 20 Summary of shifter instructions 4 3 Shifter result SR register 2 7 4 100 4 103 4 112 4 114 4 159 Signed division 4 66 Sine approximation example 3 10 Single precision matrix multiply 3 12 Squaring Instruction 4 86 Squaring operation 4 87 Stack control 4 155 Stack pop codes A 19 Stacks 2 6 Status bits 2 6 Status register
90. Ps C Compiler amp Library Manual for ADSP 218x Family DSPs Product Bulletin for VisualDSP and the ADSP 218x Family DSPs VisualDSP User s Manual for ADSP 218x Family DSPs Linker amp Utilities Manual for ADSP 218x Family DSPs These documents are included in the software distribution CD ROM and can be downloaded from our website at wuw analog com ADSP 218x Instruction Set Reference 3 3 System Development Process Figure 3 1 shows a flow chart of the system development process Linker Description File LDF Step 2 Code Generation Linker linker exe DXE Step 1 Architecture Description Generate Assembly Source DSP ASM and or Assembler DOJ EASM218x Generate C Source C Compiler cc218x VisualDSP Debugger debugapp Step 3 System Verification Hardware Evaluation EZ Kit Lite Target Verification EZ ICE Step 4 Software Verification ROM Production ELFSPL21 Figure 3 1 ADSP 218x DSP System Development Process The development process begins with the task of describing the system and generating source code You describe the system in the Linker Description File LDF and you generate source code in C and or assem bly language Describing the system in the LDF file includes providing information about the hardware environment and memory layout See the Linker amp Utilities Manual for ADSP 218x Family DSPs
91. TAX SR SR OR LSHIFT xop BY lt exp gt HI LO Permissible xops lt exp gt SI MRO Any constant between 128 and 127 SRI MRI SRO MR2 AR See the ADSP 218x DSP Hardware Reference Manual Chapter 2 Computational Units EXAMPLES Shift the MR register into SR by 5 arithmetically SR LSHIFT MRO BY 5 LO Shift right SR SR OR LSHIFT MRI BY 5 HI Shift right SR SR OR LSHIFT MR2 BY 16 5 HI LE SHTEE ett 7 DESCRIPTION Logically shifts the bits of the operand by the amount and direction speci fied by the constant in the exponent field Positive constants cause a left shift upshift negative constants cause a right shift downshift A posi tive constant must be entered without a sign The shift may be referenced to the upper half of the output field HI option or to the lower half LO option The shift output may be logically ORed with the contents of the SR register by selecting the SR OR option For LSHIFT with a positive shift constant the operand is shifted left The 32 bit output field is zero filled to the left and from the right Bits shifted out of the high order bit in the 32 bit destination field SR31 are dropped 4 114 ADSP 218x Instruction Set Reference For LSHIFT with a negative shift constant the operand is shifted right The 32 bit output field is zero filled from the left and to the right Bits shifted out of the low order bit are dropped To s
92. U Carry AC 010 X input sign positive POS 011 X input sign negative NEG 0 0 Not MAC Overflow NOT MV 0 1 MAC Overflow MV 10 Counter expired CE 11 Always FOREVER ADSP 218x DSP Instruction Set Reference A 23 Opcode Mnemonics X X Operand Codes Table A 24 X Operand Codes Code Register 0 0 0 X0 SI for shifter 001 X1 invalid for shifter 0 1 0 AR 011 MRO 0 0 MRI 0 1 MR2 1 0 SRO 1 1 SRI YY Operand Codes Table A 25 Y Operand Codes Code Register 0 0 YO 0 1 Y1 10 F feedback register 11 Zero YY A 24 ADSP 218x DSP Instruction Set Reference Instruction Coding See YY CC BO ALU MAC Constant Codes Type 9 on page A 25 Z ALU MAC Result Register Codes Table A 26 ALU MAC Result Register Codes Code Return Type 0 Result register 1 Feedback register YY CC BO ALU MAC Constant Codes Type 9 Table A 27 ALU MAC Constant Codes Constant YY CC BO Bit hex 0001 00 00 01 bit 0 0002 00 01 01 bit 1 0004 00 10 01 bit 2 0008 00 11 01 bit 3 0010 01 00 01 bit 4 0020 01 01 01 bit 5 0040 01 10 01 bit 6 0080 01 11 01 bit 7 ADSP 218x DSP Instruction Set Reference A 25 Opcode Mnemonics Table A 27 ALU MAC Constant Codes Constant YY CC BO Bit hex 0100 10 00 01 bit 8 0200 1
93. X1 MYOCRND AX1 DM I2 M0 AY1 M MR MR AY O M MR y1 C x1 S AX1 y0 R1 MR MXO MYO SS AY1 y1 C x1 S MR x1 C MX1 MY1 RND MR x1 C y1 S R1 AR AX1 AY AYO x1 C yl S AR y0 Ly1 C x1 S PADJ AR DM I3 MI AR Check for bit growth yl y0 y1 C x1 S 0 AYO MX1 DM 13 MO MY1 PM 15 M4 AR x0 x1 C yl1 S MXi next yl MYl next S PADJ AR DM I1 M1 AR Check for bit growt x1 x0 x1 C y1 S O AYO MXO DM I1 MO MYO PM 14 M4 AR x0 x1 C y1 S J MXO next x1 MYO next C PADJ AR DM I0 M1 AR Check for bit growth x0 x0 Lx1 C yl1 S J MR x1 S AX0 x0 Al mi KJ ue xI xy Ri PE x 4 xi xy TA Ji z xi i 3 20 ADSP 218x Instruction Set Reference bfly_lp Software Examples AR AX1 AY1 AR y0 Ly1 C x1 S SB EXPADJ AR DM I2 M1 AR 1 Check for bit growth CALL bfp_adj RISS Bit Reverse Subroutine The bit reversal routine called scramble puts the input data in bit reversed order so that the results will be in sequential order This rou tine uses the bit reverse capability of the ADSP 218x processors Listing 3 7 Bit Reverse Routine Scramble SECTION CODE program Calling Parameters K Sequentially ordered input data in inputreal A F OX OX F define define EXTERN GLOBAL scramble Return Values
94. Z AMF 0 0 Xop 0 0 0 1 COND AMF specifies the ALU or MAC operation in this case AMF FUNCTION Data Format X Operand 00100 xop xop SS Signed 00111 xop xop UU Unsigned 00001 xop xop RND Signed 2 Destination register COND Condition Xop X operand register SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e ALU MAC Result Register Codes on page A 25 e AMF Function Codes on page A 10 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 4 78 ADSP 218x Instruction Set Reference Multiply with Cumulative Add SYNTAX IF cond J MR MF Permissible xops MX0 MX1 MR2 MRI MRO EXAMPLES Conditional multiply with cumulative add AR SRI SRO MR xop Permissible yops MY0 MY1 MF yop xop SS SU US UU RND Permissible conds EQ NE GT GE LT IF GE MR MR MXO MY1 SS Unconditional MF SRO SRO SS LE NEG POS AV NOT AV Instruction Set AC NOT AC MV NOT MV NOT CE xop yop multiply with cumulative add xop yop 40 bit accumulation of 16 bit integer values ENA M_ MODE MR 0 MXO MYO 1 CNTR N 1 DM I0 MO Use integer mode Load first X ADSP 218x Instruction Set Reference 4 79 MAC Instructions DO ADDLOOP UNTIL CE AD
95. able 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ _ Jao _ _ x x x x AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise ADSP 218x Instruction Set Reference 4 63 ALU Instructions AV Set if an overflow is generated Cleared otherwise AC Set if a carry is generated Cleared otherwise INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0000 COND AMF specifies the ALU or MAC operation in this case AMF 11000 for yop 1 operation Note that the xop field is ignored for the decrement operation 2 Destination register Yop Y operand Xop X operand COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e ALU MAC Result Register Codes on page A 25 e AMF Function Codes on page A 10 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 4 64 ADSP 218x Instruction Set Reference Instruction Set Divide Primitives DIVS and DIVQ SYNTAX DIVS yop XOP DIVQ xop Permissible xops Permissible yops AX0 MR2 AY1 AX1 MRI AF AR MRO SRI SRO DESCRIPTION These instructions implement yop xop There are two divide primitives DIVS and DIVQ A single precision divide with a 32 bit
96. address of the last instruction of the loop The loop com pares the address value only This comparison is performed 2 20 ADSP 218x Instruction Set Reference Programming Model independently from the value of the PMOVLAY register Whenever the PMOVLAY register is updated to point to another overlay page while a loop in another overlay page is still active the loop comparator may detect an end of loop address and force the PC to branch to an undesired memory location In a real system design this scenario may happen when a loop within an overlay page is exited temporarily by an interrupt service routine that runs in a different overlay page Note The fixed memory region for program memory occupies addresses 0x0000 through 0x1fff the program memory overlay region occupies addresses 0x2000 through 0x3fff To avoid the improper execution of a loop e Place hardware loops either in the fixed program memory or in over lay pages Do not place loops whose loop bodies cross the boundary between program memory and an overlay page e Always place interrupt service routines in fixed program memory or in non overlay program memory e Avoid end of loop addresses in ISRs ADSP 218x Instruction Set Reference 2 21 Hardware Overlays and Software Issues 2 22 ADSP 218x Instruction Set Reference 3 SOFTWARE EXAMPLES Overview This chapter provides a brief summary of the development process that you use to create executable p
97. ag blk_exponent ne Ntimes 2048 RN inplacereal blk_exponent gin declaration GLOBAL bfp_adj 3 22 ADSP 218x Instruction Set Reference bfp_adj strt_shift shift_loop Software Examples AYO CNTR Check for last stage AR AYO 1 IF EQ RTS If last stage return AY0 2 AXO SB AR AX0 AYO Check for SB 2 IF EQ RTS IF SB 2 no bit growth return I0 inplacereal I0 read pointer Tl inplacereal Tl write pointer AYO 1 MYO 0x4000 Set MYO to shift 1 bit right AR AX0 AYO MXO DMC 1I0 M1 Check if SB 1 Get lst sample IF EQ JUMP strt_shift If SB 1 shift block data 1 bit AX0 2 Set AXO for block exponent update MY0 0x2000 Set MYO to shift 2 bits right CNTR Ntimes2 1 initialize loop counter DO shift_loop UNTIL CE Shift block of data MR MXO MYOCRND MXO DM 10 M1 MR shifted d MX0 next va DMC I1 M1 MR1 Unshifted d shifted d MR MXO MYOCRND Shift last data w AYO DM blk_exponent Update block expo and store last shifted sa DM I1 M1 MRI AR AYO AX0 DM b1k_exponent AR RTS a a a o p ta ue ta ta rd nent e ADSP 218x Instruction Set Reference 3 23 Radix 2 Decimation in Time FFT 3 24 ADSP 218x Instruction Set Reference 4 INSTRUCTION SET Quick List Of Instructions This
98. and is enclosed in square brackets to show this A complete list of the permissible xops and yops is given in the refer ence page for each instruction A complete list of conditions is given in Table 4 9 4 14 ADSP 218x Instruction Set Reference Instruction Set Table 4 3 ALU Instructions IF cond AR xop yop are yop C constant constant C IF cond AR xop yop he VOp eC ed Fe Ge constant 1 constant C 1 CIF cond AR yop xop AF XOp CI KOP EC aA xop constant xop constant C 1 IF cond AR xop AND yop AF OR constant XOR IF cond AR STBIT n OF xop AF SETBIT n OF xop CLRBIT n OF xop GLBIT n OF xop IF cond AR PASS xop AF yop constant ADSP 218x Instruction Set Reference 4 15 ALU MAC amp Shifter Instructions F cond AR xop AF yop F cond AR NOT XOP AF yop F cond AR ABS xop AF F cond AR yop Iz AF F cond AR yop Ns AF DIVS yop xop DIVQ xop ONE lt ALU gt 4 16 ADSP 218x Instruction Set Reference Instruction Set MAC Group Here is an example of one of the MAC instructions Multiply Accumulate IF NOT MV MR MR MXOxMYO UU The conditional expression IF NOT MV tests the MAC overflow bit If the condition is not true a NOP is executed The expression MR MR MXO MY0 is the multiply accumulate operation the mul
99. ata buffer 3 14 Inplacereal data buffer 3 14 Inputimag data buffer 3 14 Inputreal data buffer 3 14 Instruction set List of instructions 4 1 Notation table 1 9 Overview 4 5 Syntax 4 29 Integer division 4 68 Interrupt control ICNTL register 225 4117 4127 Interrupt enable and disable 4 164 Interrupt mask IMASK register 2 1 45 27 2 18 4 117 4 127 4 147 4 156 4 164 Interrupts 2 5 2 18 IO space read write 4 134 J JUMP instruction 2 17 4 136 4 153 JUMP or CALL on flag in pin 4 141 Jump Call codes A 20 ADSP 218x DSP Instruction Set Reference I 3 INDEX L Length L register 2 4 2 14 2 18 4 123 4 125 4 130 4 133 4 171 4 175 4 186 4 190 4 192 Load register immediate 4 118 Logical shift 4 100 Logical shift immediate 4 114 Loop counts 2 5 Loop hardware 2 20 Loop stack pop codes A 18 M MAC clear 4 90 MAC instructions 4 74 Overview 4 17 Summary of conditions table 4 18 Summary of MAC instructions 4 2 MAC transfer MR 4 92 Memory accesses off chip 4 28 Memory interface 2 10 Memory mapped registers 2 1 MISC instructions 4 155 Miscellaneous instructions Overview 4 26 Summary of instructions 4 4 Summary of instructions table 4 27 Mode bits 2 6 Mode control 4 161 Mode status MSTAT register 2 6 2 7 2 8 2 18 4 117 4 127 4 147 4 156 4 161 Bit table 4 162 Modify M register 2 4 2 14 4 8 4 26 4 124 4 126 4 131 4 171 4 189 Modify address register 4 171 Modify flag out
100. ause a left shift upshift and negative codes cause a right shift downshift The shift may be referenced to the upper half of the output field HI option or to the lower half LO option The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option For ASHIFT with a positive shift code i e positive value in SE the oper and is shifted left with a negative shift code i e negative value in SE the operand is shifted right The number of positions shifted is the count in the shift code The 32 bit output field is sign extended to the left the MSB of the input is replicated to the left and the output is zero filled from the right Bits shifted out of the high order bit in the 32 bit destina tion field SR31 are dropped Bits shifted out of the low order bit in the destination field SR are dropped To shift a double precision number the same shift code is used for both halves of the number On the first cycle the upper half of the number is shifted using an ASHIFT with the HI option on the following cycle the lower half of the number is shifted using an LSHIFT with the LO and OR options This prevents sign bit extension of the lower word s MSB STATUS GENERATED No status bits affected INSTRUCTION FORMAT Conditional Shift Operation Instruction Type 16 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 0 0 1 1 1 0 O SF Xop 0 0 0 0 COND
101. ause of this instruction up to the first comma says that MR the MAC result register gets the sum of its previous value plus the product of the current X and Y input registers of the MAC MX0 and MY0 both treated as signed SS In the second and third clauses of this multifunction instruction two new operands are fetched One is fetched from the data memory DM pointed to by index register zero 10 post modified by the value in MO and the other is fetched from the program memory location PM pointed to by 14 post modified by M5 in this instance Note that indirect memory address ing uses a syntax similar to array indexing with DAG registers providing ADSP 218x Instruction Set Reference 4 7 Multifunction Instructions the index values Any I register may be paired with any M register within the same DAG As discussed in the ADSP 218x DSP Hardware Reference Manual Chapter 2 Computational Units registers are read at the beginning of the cycle and written at the end of the cycle The operands present in the MX0 and MYO registers at the beginning of the instruction cycle are multiplied and added to the MAC result register MR The new operands fetched at the end of this same instruction overwrite the old operands after the multipli cation has taken place and are available for computation on the following cycle You may of course load any data registers in conjunction with the computation not just MAC registers with a
102. binations for Multifunction Instructions 4 10 ADSP 218x Instruction Set Reference Instruction Set on page 4 11 shows the legal combinations for multifunction instructions You may combine operations on the same row with each other Table 4 1 Summary of Valid Combinations for Multifunction Instructions Unconditional Computations Data Move Data Move DM DAG1 PM DAG2 None or any ALU except Division or MAC DM read PM read Any MAC DM read Any ALU except Division PM read Any Shift except Immediate DM write PM write Register to Register ADSP 218x Instruction Set Reference 4 11 Multifunction Instructions Table 4 2 Multifunction Instructions lt ALU gt Tt lt MAC gt t AXO AX1 MXO MX1 lt ALU gt lt MAC gt lt SHIFT gt May not be conditional instruction AXO DM AX1 MXO MX1 DM 110 MO Il MI 12 M2 13 M3 dreg DM PM 10 I1 I2 13 WwW MO FO ND oO ff ND oO ff MO M1 M2 M3 AYO AY MYO MY Ww ND oO ff ND oO ff AYO AY1 MYO MY1 PM 14 15 16 I7 PM SND Of M4 M5 M6 M7 4 12 ADSP 218x Instruction Set Reference Instruction Set DM 0 0 dreg lt ALU gt 1 1 lt MAC gt 2 2 lt SHIFT gt 3 3 4 4 5 5 6 6 7 7 PM 4 4 5 5 6 6 7 7 lt ALU gt dreg dreg l
103. ce 4 147 Program Flow Instructions INSTRUCTION FORMAT Conditional Return Instruction Type 20 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 COND COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 4 148 ADSP 218x Instruction Set Reference Do Uniil SYNTAX DO lt addr gt UNTIL term Permissible terms EQ NE GT GE LT FOREVER LE NEG POS AV NOT AV AC NOT AC MV NOT MV CE EXAMPLE DO Joop_label UNTIL CE CNTR is decremented each pass through loop DESCRIPTION DO UNTIL sets up looping circuitry for zero overhead looping The program loop begins at the program instruction immediately following the D0 instruction ends at the address designated in the instruction and repeats execution until the specified termination condition is met if one is speci fied or repeats in an infinite loop if none is specified The termination condition is tested during execution of the last instruction in the loop the status having been generated upon completion of the previous instruction The address lt addr gt of the last instruction in the loop is stored directly in the instruction word If CE is used for the termination condition the processor s counter CNTR register is decremented once for each pass through the loop When the DO instruction is executed the addres
104. certain situations where results produced will be off by one LSB This section documents these situations and presents alternatives for producing the correct results Computing a 16 bit fixed point quotient from two numbers is accom plished by 16 executions of the DIVQ instruction for unsigned numbers Signed division uses the DIVS instruction first followed by fifteen DIVQs Regardless of which division you perform both input operands must be of the same type signed or unsigned and produce a result of the same type These two instructions are used to implement a conditional add subtract non restoring division algorithm As its name implies the algorithm func tions by adding or subtracting the divisor to from the dividend The decision as to which operation is performed is based on the previously generated quotient bit Each add subtract operation produces a new par tial remainder which will be used in the next step The phrase non restoring refers to the fact that the final remainder is not correct With a restoring algorithm it is possible at any step to take the partial quotient multiply it by the divisor and add the partial remainder to recreate the dividend With this non restoring algorithm it is necessary to add two times the divisor to the partial remainder if the previously determined quotient bit is zero It is easier to compute the remainder using the multiplier than in the ALU Signed Division Signed division is acc
105. chapter is a complete reference for the instruction set of the ADSP 218x family The instruction set is organized by instruction group and within each group by individual instruction The list below shows all of the instructions and the reference page for each ALU Instructions Add Add with Carry on page 4 32 Subtract X Y Subtract X Y with Borrow on page 4 36 Subtract Y X Subtract Y X with Borrow on page 4 40 Bitwise Logic AND OR XOR on page 4 43 Bit Manipulation TSTBIT SETBIT CLRBIT TGLBIT on page 4 46 Clear PASS on page 4 49 Negate on page 4 54 NOT on page 4 56 Absolute Value ABS on page 4 58 Increment on page 4 61 ADSP 218x Instruction Set Reference 4 1 Quick List Of Instructions e Decrement on page 4 63 e Divide Primitives DIVS and DIVQ on page 4 65 e Generate ALU Status Only NONE on page 4 73 MAC Instructions e Multiply on page 4 75 e Multiply with Cumulative Add on page 4 79 e Multiply with Cumulative Subtract on page 4 83 e Squaring on page 4 87 e MAC Clear on page 4 91 e MAC Transfer MR on page 4 93 e Conditional MR Saturation on page 4 96 Shifter Instructions e Arithmetic Shift on page 4 97 e Logical Shift on page 4 100 e Normalize on page 4 103 e Derive Exponent on page 4 106 e Block Exponent Adjust on page 4 110 e Arithmetic Shift Immediate
106. cifies which Data Address Generator is selected The I and M registers specified must be from the same DAG separated by the gray bar above 1 specifies the I register depends on which DAG is selected by the G bit M specifies the M register depends on which DAG is selected by the 6 bit SEE ALSO e DAG Selection Codes on page A 17 e Index Register Selection Codes on page A 17 e Modify Register Selection Codes on page A 18 4 172 ADSP 218x Instruction Set Reference No Operation SYNTAX NOP DESCRIPTION No operation occurs for one cycle Execution continues with the instruc tion following the NOP instruction STATUS GENERATED No status bits affected INSTRUCTION FORMAT No operation Instruction Type 30 as shown below 23 22 21 20 19 18 17 16 15 14 13 12 1110987654321 0 0 0 0 0 00 0 0 0 O 0 00 0000000000 0 ADSP 218x Instruction Set Reference 4 173 Multifunction Instructions Multifunction Instructions Computation with Memory Read SYNTAX lt ALU gt lt MAC gt lt SHIFT gt dreg DM 10 I1 I2 13 14 15 16 I7 14 15 16 I7 MO M1 M2 M3 M4 M5 M6 M7 M4 M5 M6 M7 4 174 ADSP 218x Instruction Set Reference Permissible dregs AXO MX0 SI AX1 MX1 SE AYO MY0 SRO AY1 MY1 SRI AR MRO MRI MR2 DESCRIPTION Perform the designated arithmetic operation and data transfer The read operation moves the contents of t
107. ck The stack is pushed immediately in the same cycle Note that TOPPCSTACK may not be used as a register in any other instruction type 4 158 ADSP 218x Instruction Set Reference Because the PC stack width is 14 bits be sure that registers that are pushed onto the PC stack via the TOPPCSTACK reg instruction are 14 bits or less to order to avoid loss of data The 14 MSBs from a 16 bit register are written to the PC stack The upper 2 bits of the 16 bit value are discarded EXAMPLE AXO TOPPCSTACK pop PC stack into AXO NOP TOPPCSTACK I7 Use only the following registers in the TOPPCSTACK instruction ALU MAC and Shifter Registers DAG Registers push contents of I7 onto PC stack AXO MX0 SI AX1 MX1 SE AYO MYO SRI AY1 MY1 SRO AR MR2 MRI MRO MXO0 I0 I4 I1 I5 I2 16 13 17 MO M2 M3 M4 M5 M6 M7 LO L1 L2 L3 L4 LS L6 L7 There are several restrictions on the use of the special TOPPCSTACK instruc tions which are described in the ADSP 218x DSP Hardware Reference Manual Chapter 3 Program Control ADSP 218x Instruction Set Reference 4 159 MISC Instructions INSTRUCTION FORMAT TOPPCSTACK reg Internal Data Move Instruction Type 17 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 0 0 0 071 I SRC 1 1 1 1 SOURCE RGP REG To choose the sou
108. ction Computational Units The registers in the computational units store data The ALU and MAC require two inputs for most operations The AX0 AX1 MX0 and MX1 regis ters store X inputs and the AYO AY1 MYO and MY1 registers store Y inputs The AR and AF registers store ALU results AF can be fed back to the ALU Y input whereas AR can provide the X input of any computational unit Likewise the MRO MR1 MR2 and MF register store MAC results and can be fed back for other computations The 16 bit MRO and MR1 registers together with the 8 bit MR2 register can store a 40 bit multiply accumulate result The shifter can receive input from the ALU or MAC from its own result registers or from a dedicated shifter input S1 register It can store a 32 bit result in the SRO and SR1 registers The SB register stores the block ADSP 218x Instruction Set Reference 2 7 Overview exponent for block floating point operations The SE register holds the shift value for normalize and denormalize operations Registers in the computational units have secondary registers shown in Figure 2 1 as second set of registers behind the first set Secondary regis ters are useful for single cycle context switches The selection of these secondary registers is controlled by a bit in the MSTAT register the bit is set and cleared by these instructions ENA SEC_REG select secondary registers DIS SEC_REG select primary registers Bus Exchange
109. d Cleared otherwise AC Set if a carry is generated Cleared otherwise INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF 10001 for yop 1 operation Note that the xop field is ignored for the increment operation ri Destination register Yop Y operand Xop X operand COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e ALU MAC Result Register Codes on page A 25 e AMF Function Codes on page A 10 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 4 62 ADSP 218x Instruction Set Reference Instruction Set Decrement SYNTAX IF cond ie F yop 1 AF Permissible yops Permissible conds AYO AX0 EQ LE AC AY1 AXI1 NE NEG NOT AC AF MRO GT POS MV AR MRI GE AV NOT MV SRO MR2 LT NOT AV NOTCE SRI EXAMPLES IF EQ AR AY1 1 DESCRIPTION Test the optional condition and if true then decrement the source oper and by 0x0001 and store in the destination location If the condition is not true then perform a no operation Omitting the condition performs the decrement operation unconditionally The source operand is contained in the data register specified in the instruction STATUS GENERATED See T
110. d by type number Any instruction codes not shown are reserved for future use e Opcode Mnemonics on page A 10 This section is an alpha betic listing that describes the values for each opcode mnemonic ADSP 218x DSP Instruction Set Reference A 1 Opcode Definitions Opcode Definitions Type 1 ALU MAC with Data and Program Memory Read 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 1 1 IPD JDD AMF 0 0 0 0 0 PM DM DM DM I M JI M Type 2 Data Memory Write Immediate Data 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 0 0 1 G Data I M Type 3 Read Write Data Memory Immediate Address 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 1 0 0 D RGP ADDR REG Type 4 ALU MAC with Data Memory Read Write 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 JO 0 1 1 IG ID IZ AMF Yop Xop Dreg I M Type 5 ALU MAC with Program Memory Read Write 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 0 1 DIZ AMF Yop Xop Dreg I M Type 6 Load Data Register Immediate 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 0 0 DATA DREG A 2 ADSP 218x DSP Instruction Set Reference Instruction Coding Type 7 Load Non Data Register Immediate 23 22 21 20 19 18 17 16 15 14 13
111. d debug DSP projects You can create or modify source files or view listing or map files with the IDE Edi tor This powerful Editor is part of the IDE and includes multiple language syntax highlighting OLE drag and drop bookmarks and stan dard editing operations such as undo redo find replace copy paste cut and goto Also the IDE includes access to the C Compiler C Runtime Library Assembler Linker Loader Simulator and Splitter You specify options for these tools through Property Page dialogs Property Page dialogs are easy to use and make configuring changing and managing your projects simple These options control how the tools process inputs and generate outputs and have a one to one correspondence to the tools command line switches You can define these options once or modify them to meet changing development needs You can also access the tools from the oper ating system command line if you choose Greatly Reduced Debugging Time The Debugger has an easy to use common interface for all processor simulators and emulators available through Analog Devices and third parties or custom developments The Debugger has many features that greatly reduce debugging time You can view C source interspersed with the resulting Assembly code You can pro file execution of a range of instructions in a program set simulated watch points on hardware and software registers program and data memory and trace instruction execution and memo
112. d serial clock RFSDIV is set to 255 for 256 SCLK cycles between RFS assertions SCLKDIV is set to 2 resulting in an SCLK frequency that is 1 6 of the CLKIN frequency SI 0xB27 DM OX3FF6 SI SPORTO control register SI 2 DM Ox3FF5 SI SCLKDIV 2 SI 2555 DM Ox3FF4 S1 RFSDIV 255 ADSP 218x Instruction Set Reference 2 9 Overview Memory Interface amp SPORT Enables The system control register memory mapped at DM 0x3fff contains SPORTO and SPORT 1 enable bits bits 12 and 11 respectively as well as the SPORT1 configuration selection bit bit 10 On all ADSP 218x pro cessors the system control register also contains fields for external program memory wait states For the following processors the system control register contains the disable BMS bit which allows the external signal BMS to be disabled during byte memory accesses This feature can be used for example to allow the DSP to boot from an EPROM and then access a flash or other byte wide device at runtime via the CMS signal ADSP 2184 ADSP 2184L ADSP 2185M ADSP 2184N ADSP 2186 ADSP 2185L ADSP 2186M ADSP 2185N ADSP 2186L ADSP 2188M ADSP 2186N ADSP 2187L ADSP 2189 M ADSP 2187N ADSP 2188N ADSP 2189 N The wait state control register memory mapped at DM 0x3ffe contains fields that specify the number of wait states for external data memory and four banks of external I O memory space On the following processors bit 15 of the reg
113. d with the Block Exponent Adjust instruction STATUS GENERATED No status bits affected INSTRUCTION FORMAT Conditional Shift operation Instruction Type 16 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 O 1 1 1 O0 0 JSF Xop 0 0 0 0 J COND SF 1111 Xop Shifter operand COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e Shifter Function Codes on page A 21 e X Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 111 Shifter Instructions Arithmetic Shift Immediate SYNTAX SR SR OR ASHIFT xop BY lt exp gt HI LO Permissible xops lt exp gt SI MRO Any constant between 128 and 127 SRI MRI SRO MR2 AR See the ADSP 218x DSP Hardware Reference Manual Chapter 2 Computational Units EXAMPLES SR SR OR ASHIFT SRO BY 3 LO Do not use 3 DESCRIPTION Arithmetically shift the bits of the operand by the amount and direction specified by the constant in the exponent field Positive constants cause a left shift upshift and negative constants cause a right shift downshift A positive constant must be entered without a sign The shift may be referenced to the upper half of the output field HI option or to the lower half LO option The shift output may be logically ORed with the present contents of the SR register by selecting the SR OR option F
114. dition 4 34 ADSP 218x Instruction Set Reference Instruction Set xop constant Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 0 0 1 0 0 Z AMF YY Xop CC BO COND AMF specifies the ALU or MAC operation in this case AMF AMF Z Xop BO CC SEE ALSO 10010 for xop constant C 10011 for xop constant Destination register COND Condition X operand and YY specify the constant IF Condition Codes Table 4 9 on page 4 25 Status Condition Codes on page A 12 BO CC and YY ALU MAC Constant Codes on page A 25 AMF Function Codes on page A 10 ALU MAC Result Register Codes on page A 25 X Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 35 ALU Instructions Subtract X Y Subtract X Y with Borrow SYNTAX IF cond JAR xop yop AF yop C 1 FCs constant constant C 1 Permissible xops Permissible yops Permissible status conditions AX0 MR2 AYO EQ LE AC AXI MRI AY1 NE NEG NOT AC AR MRO AF GT POS MV SRI GE AV NOT MV SRO LT NOT AV NOT CE Permissible constants 0 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32767 2 3 5 9 17 33 65 129 257 513 1025 2049 4097 8193 16385 32768 EXAMPLE Conditional subtraction IF GE AR AXO AYO Subtraction of the
115. dware Overlays and Software Issues If the interrupt service routine also accesses alternate data memory overlay pages the DMOVLAY register must be saved and restored like the PMOVLAY register Listing 2 4 is an example of a DMOVLAY register restoration Listing 2 4 DMOVLAY Register Restoration Interrupt Vector jump I_Handler jump to interrupt handler ros unreachable instructions rtis used as placeholders to rti occupy all 4 locations of the vector I_Handler this subroutine should reside in fixed PM ax0 PMOVLAY save PMOVLAY value into ax0 dm save PMOVLY ax0 save PMOVLAY value to DM variable ax0 DMOVLAY save DMOVLAY value into ax0 dm save_DMOVLY ax0 save DMOVLAY value to DM variable PMOVLAY 5 isr is in PM page 5 DMOVLAY 4 isr accesses DM page 4 call My_ISR ax0 dm save_DMOVLY return from isr and restore DMOVLAY DMOVLAY ax0 restore DMOVLAY value ax0 dm save_PMOVLY restore saved PMOVLAY from memory PMOVLAY ax0 restore PMOVLAY value reas return from interrupt My_ISR Se ee oe isr code goes here FESS return to I_Handler instead of rti Loop Hardware and Overlays The loop hardware of the ADSP 218x family operates independent of the PMOVLAY register Once a DO UNTIL instruction has been executed the loop comparator compares the next address generated by the program sequencer to the
116. e Manual Chapter 2 Computational Units STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ a MV Set on MAC overflow if any of the upper 9 bits of MR are not all one or zero Cleared otherwise INSTRUCTION FORMAT xop x yop Conditional ALU MAC operation Instruction Type 9 p yop P yp 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 JCOND 4 84 ADSP 218x Instruction Set Reference Instruction Set AMF specifies the ALU or MAC operation in this case AMF FUNCTION Data Format X Operand Y Operand 01100 MR xop xop SS Signed Signed 01101 MR xop yop SU Signed Unsigned 01110 MR xop yop US Unsigned Signed 01111 MR xop yop UU Unsigned Unsigned 00011 MR xop yop RND Signed Signed Zs Destination register Yop Y operand register Xop X operand register COND Condition xop xop Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 1 0 0 Z AMF 0 0 Xop 0 0 0 1 J COND AMF specifies the ALU or MAC operation in this case AMF FUNCTION Data Format X Operand 01100 MR xop xop SS Signed 01111 MR xop xop UU Unsigned 00011 MR xop xop RND Signed 7 Destination regis
117. e clauses of a multifunction instruction but does not terminate it For exam ple the statements below in Example A comprise one multifunction instruction which can execute in a single cycle Example B shows two separate instructions requiring two instruction cycles ADSP 218x Instruction Set Reference 4 29 Instruction Set Syntax Example A One multifunction instruction a comma is used in multifunction instructions AXO DM I0 MO or AXO DM I0 MO AYO PM I4 M4 AYO PM I4 M4 Example B Two separate instructions a semicolon terminates an instruction AXO DM IO MO AYO PM I4 M4 Syntax Notation Example Here is an example of one instruction the ALU Add Add with Carry instruction IF cond JAR xop lyop AF C yop C The permissible conds xops and yops are given in a list The conditional IF clause is enclosed in square brackets indicating that it is optional The destination register for the add operation must be either AR or AF These are listed within parallel bars indicating that one of the two must be chosen Similarly the yop term may consist of a Y operand the carry bit or the sum of both One of these three terms must be used 4 30 ADSP 218x Instruction Set Reference Instruction Set Status Register Notation The following notation is used in the discussion of the effect each instruc tion has on the processors status registers Table 4 11 Stat
118. e the operand is shifted left the num bers of positions shifted is the count in the shift code The 32 bit output field is zero filled from the right Bits shifted out of the high order bit in the 32 bit destination field SR are dropped 4 100 ADSP 218x Instruction Set Reference For LSHIFT with a negative shift code the operand is shifted right the number of positions shifted is the count in the shift code The 32 bit out put field is zero filled from the left Bits shifted out of the low order bit in the destination field SRo are dropped To shift a double precision number the same shift code is used for both halves of the number On the first cycle the upper half of the number is shifted using the HI option on the following cycle the lower half of the number is shifted using the LO and OR options STATUS GENERATED No status bits affected INSTRUCTION FORMAT Conditional Shift operation Instruction Type 16 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 0 SF Xop 0 0 0 0 COND SE Shifter Function 0000 LSHIFT HI 0001 LSHIFT HI OR 0010 LSHIFT LO 0011 LSHIFT LO OR Xop Shifter operand COND Condition ADSP 218x Instruction Set Reference 4 101 Shifter Instructions SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e Shifter Function Codes on page A 21 e X Operand Codes on pag
119. e A 24 4 102 ADSP 218x Instruction Set Reference Normalize SYNTAX IF cond SR SR OR NORM xop HI i LO Permissible xops Permissible conds SI AR EQ LE AC SRI MR2 NE NEG NOT AC SRO MRI GT POS MV MRO GE AV NOT MV LT NOT AV NOT CE EXAMPLES Normalize instruction without condition SR NORM SI HI Clear the last bits of SRO as specified by SE SE DM NUM_OF_BITS even 0 is allowed SR NORM SRO LO shift to the right SR LSHIFT SRO LO shift back to left DESCRIPTION Test the optional condition and if true then perform the designated nor malization If the condition is not true then perform a no operation Omitting the condition performs the normalize unconditionally The operation arithmetically shifts the input operand to eliminate all but one of the sign bits NORM shifts the in the opposite direction of ASHIFT The amount of the shift comes from the SE register The SE register may be ADSP 218x Instruction Set Reference 4 103 Shifter Instructions loaded with the proper shift code to eliminate the redundant sign bits by using the Derive Exponent instruction the shift code loaded will be the negative of the quantity the number of sign bits minus one The shift may be referenced to the upper half of the output field HI option or to the lower half LO option The shift output may be logically ORed with the present contents of the SR register by selectin
120. e accumulated product overflows the lower order 32 bits of the MR register Cleared otherwise lt SHIFT gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ Affected only when executing the EXP operation set if the source operand is negative Cleared if the number is positive INSTRUCTION FORMAT ALU MAC operation with Data Register Move Instruction Type 8 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 1 O 1 Z AMF Yop Xop Dreg dest Dreg source Shift operation with Data Register Move Instruction Type 14 23 22 21 20 19 18 17 16 15 14 13 1211109 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 0 SF Xop Dreg dest Dreg source ADSP 218x Instruction Set Reference 4 183 Multifunction Instructions Z Result register Dreg SF Shifter operation AMF Yop Y operand Xop SEE ALSO Data register ALU MAC operation X operand e DREG Selection Codes on page A 14 e ALU MAC Result Register Codes on page A 25 e Shifter Function Codes on page A 21 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 e AMF Function Codes on page A 10 4 184 ADSP 218x Instruction Set Reference Computation with Memory Write SYNTAX I 12 13 14 I5 16 I7 I5 16 17 MO M1 M2 M3 M4 M5 M6 M7 M4 M5 M6 M7 dreg lt ALU gt lt MAC gt lt SHIFT gt
121. egister M Modify register SEE ALSO e Program Memory Destination Codes on page A 18 e Data Memory Destination Codes on page A 14 e Index Register Selection Codes on page A 17 e Modify Register Selection Codes on page A 18 ADSP 218x Instruction Set Reference 4 191 Multifunction Instructions ALU MAC with Data and Program Memory Read SYNTAX lt ALU gt AXO DMC 10 MO AYO J PMC 14 m4 lt MAC gt AX1 1 1 AY1 5 5 MXO 2 2 MYO 6 6 MX1 3 3 MY1 7 7 DESCRIPTION This instruction combines an ALU or a MAC operation with a data mem ory read and a program memory read The read operations move the contents of the memory location to the destination register For this dou ble data fetch the destinations for data memory reads are the X registers in the ALU and the MAC and the destinations for program memory reads are the Y registers The addressing mode is register indirect with post modify For linear i e non circular indirect addressing the L reg ister corresponding to the I register used must be set to zero The contents of the source are always right justified in the destination register after the read A multifunction instruction requires three items to be fetched from mem ory the instruction itself and two data words No extra cycle is needed to execute the instruction as long as only one of the fetches is from external memory
122. egisters are automatically initialized or may be ignored the 2 4 ADSP 218x Instruction Set Reference Programming Model I M and L registers contain random values following processor reset Your program must initialize the L registers corresponding to any I registers it uses Program Sequencer Registers associated with the program sequencer control subroutines loops and interrupts They also indicate status and select modes of operation Interrupts The ICNTL register controls interrupt nesting and external interrupt sensi tivity The IFC register which is 16 bits wide lets you force and clear interrupts in software The IMASK register which is 10 bits wide masks dis ables individual interrupts ADSP 218x processors support 12 interrupts two of which reset powerdown are non maskable The ADSP 2181 supports a global interrupt enable instruction ENA INTS and interrupt disable instruction DIS INTS Executing the disable inter rupt instruction causes all interrupts to be masked without changing the contents of the IMASK register Disabling interrupts does not affect serial port autobuffering which will operate normally whether or not interrupts are enabled The disable interrupt instruction masks all user interrupts including the powerdown interrupt The interrupt enable instruction allows all unmasked interrupts to be serviced again Loop Counts The CNTR register stores the count value for the currently executing lo
123. ence Program Memory Overlay Register Update SYNTAX PMOVLAY lt data gt reg PMOVLAY data lt constant gt Permissible dregs AXO AXI AYO AY1 AR MX0 MX1 MYO MY1 MR2 MRI MRO SI SE SRI SRO Permissible regs SB PX ASTAT MSTAT IMASK ICNTL 10 17 MO M7 LO L7 CNTR OWRCNTR write only RXO RX1 TXO TX1 IFC write only DMOVLAY ADSP 218x Instruction Set Reference 4 165 MISC Instructions Permissible constants 1 2 ADSP 2184 and ADSP 2186 processors only 0 1 2 ADSP 2181 ADSP 2183 and ADSP 2185 processors only 0 1 2 4 5 ADSP 2187 and ADSP 2189 processors only 0 1 2 4 5 6 7 ADSP 2188 processor only EXAMPLE PMOVLAY 5 Write to pmovlay register Read from pmovlay register into ax0 register AXO PMOVLAY PMOVLAY DMOVLAY Write to PMOVLAY from DMOVLAY PMOVLAY DM 0x1234 Write to PMOVLAY from data memory DESCRIPTION The PMOVLAY write instruction switches the context of the hardware pro gram memory overlay region to the specific region specified by the permissible data value written to the PMOVLAY register The PMOVLAY read instruction moves the value from the PMOVLAY register into one of the per missible registers listed above STATUS GENERATED No status bits affected 4 166 ADSP 218x Instruction Set Reference INSTRUCTION FORMAT Read Write Data Memory Immediate Address
124. er M specifies the modify register M register SEE ALSO e Index Register Selection Codes on page A 17 e Modify Register Selection Codes on page A 18 ADSP 218x Instruction Set Reference 4 133 Move Instructions IO Space Read Write SYNTAX 10 lt addr gt dreg 1 0 write dreg IO lt addr gt I O read lt addr gt is an 11 bit direct address value between 0 and 2047 Permissible dregs AXO MX0 SI AX1 MX1 SE AYO MYO SRI AY1 MY1 SRO AR MR2 MRI MRO EXAMPLES 10 23 AX0 MY1 10 2047 DESCRIPTION The I O space read and write instructions are used to access the ADSP 218x s I O memory space These instructions move data between the processor data registers and the I O memory space 4 134 ADSP 218x Instruction Set Reference STATUS GENERATED No status bits affected INSTRUCTION FORMAT I O Memory Space Read Write Instruction Type 29 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 D ADDR DREG ADDR contains the 11 bit direct address of the source or destination loca tion in I O Memory Space To choose a data register DREG refer to the table DREG Selection Codes on page A 14 D specifies the direction of the transfer 0 read 1 write ADSP 218x Instruction Set Reference 4 135 Program Flow Instructions Program Flow Instructions JUMP SYNTAX CIF cond JUMP 14 15
125. er Move on page 4 180 Computation with Memory Write on page 4 185 Data and Program Memory Read on page 4 190 ALU MAC with Data and Program Memory Read on page 4 192 4 4 ADSP 218x Instruction Set Reference Instruction Set Overview This chapter provides an overview and detailed reference for the instruc tion set of the ADSP 218x family of DSP microprocessors The instruction set is grouped into the following categories e Computational ALU MAC Shifter e Move e Program Flow e Multifunction e Miscellaneous The instruction set is tailored to the computation intensive algorithms common in DSP applications For example sustained single cycle multi plication accumulation operations are possible The instruction set provides full control of the processors three computational units the ALU MAC and Shifter Arithmetic instructions can process single preci sion 16 bit operands directly provisions for multiprecision operations are available The high level syntax of ADSP 218x family source code is both readable and efficient Unlike many assembly languages the ADSP 218x family instruction set uses an algebraic notation for arithmetic operations and for data moves resulting in highly readable source code There is no perfor mance penalty for this each program statement assembles into one 24 bit instruction which executes in a single cycle There are no multicycle instructions in the instruction set
126. er group DST RGP and the destination register DEST REG refer to the table Register Selection Codes on page A 19 4 170 ADSP 218x Instruction Set Reference Modify Address Register SYNTAX MODIFY I0 MO Il M1 12 M2 13 M3 14 M4 15 M5 16 M6 17 M7 EXAMPLE MODIFY I1 M1 DESCRIPTION Add the selected M register M to the selected I register I then process the modified address through the modulus logic with buffer length as determined by the L register corresponding to the selected I register Lm and store the resulting address pointer calculation in the selected 1 regis ter The I register is modified as if an indexed memory address were taking place but no actual memory data transfer occurs For linear i e non cir cular indirect addressing the L register corresponding to the I register used must be set to zero The selection of the I and M registers is constrained to registers within the same Data Address Generator selection of 10 13 in Data Address Genera tor 1 constrains selection of the M registers to MO M3 Similarly selection of 14 17 constrains the M registers to M4 M7 ADSP 218x Instruction Set Reference 4 171 MISC Instructions STATUS GENERATED No status bits affected INSTRUCTION FORMAT Modify Address Register Instruction Type 21 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543 21 0 0 0 0 0 1 0 0 1 0 0 O 0 0 0 0000 0 G I JM G spe
127. ereal inplaceimag VAR groups N_div_2 VAR bflys_per_group 2 VAR node_space 2 VAR blk_exponent 0 GLOBAL groups bflys_per_group node space blk_exponent ADSP 218x Instruction Set Reference 3 15 Radix 2 Decimation in Time FFT SECTION DATA data2 VAR twid_real N_div_2 twid_real dat VAR twid_imag N_div_2 twid_imag dat GLOBAL twid_real twid_imag SECTION CODE program EXTERN scramble fft_strt CALL scramble subroutine calls CALL F t_strt IDLE halt program DIT FFT Subroutine The radix 2 DIT FFT routine is shown in Listing 3 6 The constants N and 10g2N are the number of points and the number of stages in the FFT respectively To change the number of points in the FFT you modify these constants The first and last stages of the FFT are performed outside of the loop that executes all the other stages Treating the first and last stages individually allows them to execute faster In the first stage there is only one butterfly per group so the butterfly loop is unnecessary The twiddle factors are all either 1 or 0 making multiplications unnecessary In the last stage there is only one group Therefore the group loop is unnecessary and the setup operations for the next stage Listing 3 6 Radix 2 DIT FFT Routine Conditional Block Floating Point 1024 point DIT radix 2 FFT Block Floating Point Scaling SECTION CODE program 3 16 ADSP 218x In
128. g the SR OR option When the LO reference is selected the 32 bit output field is zero filled to the left Bits shifted out of the high order bit in the 32 bit destination field SR3 are dropped The 32 bit output field is zero filled from the right If the exponent of an overflowed ALU result was derived with the HIX modifier the 32 bit out put field is filled from left with the ALU Carry AC bit in the Arithmetic Status Register ASTAT during a NORM HI operation In this case SE 1 from the exponent detection on the overflowed ALU value a downshift occurs To normalize a double precision number the same shift code is used for both halves of the number On the first cycle the upper half of the num ber is shifted using the HI option on the following cycle the lower half of the number is shifted using the LO and OR options STATUS GENERATED No status bits affected INSTRUCTION FORMAT Conditional Shift operation Instruction Type 16 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 O SF Xop 0 0 0 0 COND 4 104 ADSP 218x Instruction Set Reference SF Shifter Function 1000 NORM HI 1001 NORM HI OR 1010 NORM LO 1011 NORM LO OR Xop Shifter operand COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e Shifter Function Codes on page A 21 e X Operand
129. he condition performs the multi ply subtract unconditionally The operands are contained in the data registers specified in the instruction When MF is the destination operand only bits 16 31 of the 40 bit result are stored in MF The ADSP 218x processors support the xop xop squaring operation Both xops must be in the same register This option allows single cycle X and XX instructions ADSP 218x Instruction Set Reference 4 83 MAC Instructions The data format selection field to the right of the two operands specifies whether each respective operand is in signed S or unsigned U format The xop is specified first and yop is second If the xop xop operation is used the data format selection field must be UU SS or RND only There is no default one of the data formats must be specified If RND Round is specified the MAC multiplies the two source operands subtracts the product from the current contents of the MR register rounds the result to the most significant 24 bits or rounds bits 31 16 to 16 bits if there is no overflow from the multiply accumulate and stores the result in the destination register The two multiplication operands xop and yop or xop and xop are considered to be in twos complement format The ADSP 218x processors support biased rounding mode as well as unbiased rounding For a discussion of biased vs unbiased rounding see the section Rounding Mode in the ADSP 218x DSP Hardware Referenc
130. he divisor Compare this value with the dividend and if they are off by more than the value of the divisor increase the quotient by one Unsigned Division Error Unsigned divisions can produce erroneous results if the divisor is greater than 0x7FFF You should not attempt to divide two unsigned numbers if the divisor has a one in the MSB If it is necessary to perform a such a division both operands should be shifted right one bit This will maintain the correct orientation of operands Shifting both operands may result in a one LSB error in the quotient This can be solved by multiplying the quotient by the original not shifted divisor Subtract this value from the original dividend to calculate the error If the error is greater than the divisor add one to the quotient if it is negative subtract one from the quotient Division Applications Each of the problems mentioned in Division Exceptions on page 4 70 can be compensated for in software Listing 4 1 shows the program sec tion divides This code can be used to divide two signed or unsigned numbers to produce the correct quotient or an error condition Note that the DIVQ instruction must be placed 15 or 16 times explicitly A hardware loop that executes DIVQ 15 or 16 times will not work correctly Listing 4 1 Division Routine Using DIVS amp DIVQ signed division algorithm with fix for negative division error inputs ayl 16 MSB of numerator ayO 16 LSB of
131. he source to the destination register The addressing mode when combining an arithmetic operation with a memory read is register indirect with post modify For linear i e non circular indirect addressing the L register corresponding to the I register used must be set to zero The contents of the source are always right justified in the destination register The computation must be unconditional All ALU MAC and Shifter operations are permitted except Shift Immediate and ALU DIVS and DIVQ instructions The fundamental principle governing multifunction instructions is that registers and memory are read at the beginning of the processor cycle and written at the end of the cycle The normal left to right order of clauses computation first memory read second is intended to imply this In fact you may code this instruction with the order of clauses reversed The assembler produces a warning but the results are identical at the ADSP 218x Instruction Set Reference 4 175 Multifunction Instructions opcode level If you turn off semantics checking in the assembler using the s switch the warning is not issued Because of the read first write second characteristic of the processor using the same register as source in one clause and a destination in the other is legal The register supplies the value present at the beginning of the cycle and is written with the new value at the end of the cycle For example 1 AR AXO AYO AXO
132. hift a double precision number the same shift constant is used for both parts of the number On the first cycle the upper half of the number is shifted using the HI option on the following cycle the lower half is shifted using the LO and OR options STATUS GENERATED No status bits affected INSTRUCTION FORMAT Shift Immediate Operation Instruction Type 15 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 O SF Xop lt exp gt SF Shifter Function 0000 LSHIFT HI 0001 LSHIFT HI OR 0010 LSHIFT LO 0011 LSHIFT LO OR Xop Shifter operand lt exp gt 8 bit signed shift value SEE ALSO e Shifter Function Codes on page A 21 e X Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 115 Move Instructions Move Instructions Register Move SYNTAX reg reg Permissible registers AX0 MXO SI SB CNTR AX1 MX1 SE PX OWRCNTR write only AYO MYO SRI ASTAT RXO AY1 MY1 SRO MSTAT RX1 AR MR2 10 17 SSTAT read only TXO MRI M0 M7 IMASK TX1 MRO L0 L7 ICNTL IFC write only EXAMPLES I7 AR DESCRIPTION Move the contents of the source to the destination location The contents of the source are always right justified in the destination location after the move When transferring a smaller register to a larger register e g an 8 bit reg ister to a 16 bit register the value stored in the destination is either sign ex
133. imulation allows you to debug the system and analyze performance before committing to a hardware prototype After fully simulating your system and software you can use an EZ ICE in circuit emulator in the prototype hardware to test circuitry timing and real time software execution The PROM splitter software tool el fps121 exe translates the DXE file into an industry standard file format fora PROM programmer Once you program the code in PROM devices and install an ADSP 218x processor into your prototype it is ready to run ADSP 218x Instruction Set Reference 3 5 Single Precision Fir Transversal Filter Single Precision Fir Transversal Filter An FIR transversal filter structure can be obtained directly from the equa tion for discrete time convolution N 1 y n hy n x n k k 0 In this equation x n and y n represent the input to and output from the filter at time n The output y n is formed as a weighted linear combina tion of the current and past input values of x x n k The weights h n are the transversal filter coefficients at time n In the equation x n k rep resents the past value of the input signal contained in the k 1 th tap of the transversal filter For example x n the present value of the input sig nal would correspond to the first tap while x n 42 would correspond to the forty third filter tap The subroutine that realizes the sum of products operation used in com puting the tran
134. into MR2 STATUS GENERATED No status bits affected INSTRUCTION FORMAT Data Memory Read Direct Address Instruction Type 3 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 1 0 0 1 RGP ADDR REG ADDR contains the direct address of the destination location in Data Memory To choose the source register group RGP and the source register REG refer to the table Register Selection Codes on page A 19 4 128 ADSP 218x Instruction Set Reference Data Memory Write Indirect Address SYNTAX DM dreg lt data gt SO e WOM FF ND A ND A data lt constant gt Permissible dregs AX0O MX0 SI AXI MXI SE AYO MYO SRI AY1 MY1 SRO AR MR2 MRI MRO EXAMPLE DM 12 MO MR ADSP 218x Instruction Set Reference 4 129 Move Instructions DESCRIPTION The Data Memory Write Indirect instruction moves the contents of the source to the data memory location specified in the instruction word The immediate data may be a constant The addressing mode is register indirect with post modify For linear i e non circular indirect addressing the L register corresponding to the I register used must be set to zero When a register of less than 16 bits is written to memory the value written is sign extended to form a 16 bit value The contents of the source are always right justified in the destina tion location after the write bit 0 maps to b
135. ion Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 ICOND AMF specifies the ALU or MAC operation in this case AMF 11100 for AND operation AMF 11101 for OR operation AMF 11110 for XOR operation Z Destination register Yop Y operand Xop X operand COND Condition xop AND OR XOR constant Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 1 0 0 Z AMF YY Xop CC BO COND 4 44 ADSP 218x Instruction Set Reference A AMF Instruction Set F specifies the ALU or MAC operation in this case AMF AMF Ee Xop 11100 for AND operation 11101 for OR operation 11110 for XOR operation Destination register COND Condition X operand BO CC and YY specify the constant SEE ALSO IF Condition Codes Table 4 9 on page 4 25 Status Condition Codes on page A 12 BO CC and YY ALU MAC Constant Codes on page A 25 ALU MAC Result Register Codes on page A 25 AMF Function Codes on page A 10 X Operand Codes on page A 24 Y Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 45 ALU Instructions Bit Manipulation TSTBIT SETBIT CLRBIT TGLBIT SYNTAX IF cond AR AF Permissible xops AXO MR2 AXI MRI AR MRO SRI SRO
136. ion Programming Interfaces API Third party products including runtime operating systems emulators high level language compilers mul tiprocessor hardware can interface seamlessly with VisualDSP thereby simplifying the tools integration task VisualDSP follows the COM API format Two API tools Target Wizard and API Tester are also available for use with the API set These tools help speed the time to market for vendor products Target Wizard builds the programming shell based on API features the vendor requires The API tester exercises the individual features independently of VisualDSP Third parties can use a subset of these APIs that meets their application needs The interfaces are fully sup ported and backward compatible Further details and ordering information are available in the VisualDSP Development Tools data sheet This data sheet can be requested from any Analog Devices sales office or distributor For More Information About Analog Products Analog Devices can be found on the internet at http www analog com Our Web pages provide information about the company and products including access to technical information and documentation product overviews and product announcements You may obtain additional information about Analog Devices and its products in any of the following ways e Visit our World Wide Web site at www analog com e FAX questions or requests for information to 1 781 461 3010 1 6 ADSP 218x DSP In
137. ions except SHIFT IMMEDIATE Computation must be unconditional An example of this kind of multifunction instruction is AR AXO AYO DM IO MO AXO Here an addition is performed in the ALU while a single operand is fetched from data memory The restrictions are similar to those for previ ous multifunction instructions The value of AX0 used as a source for the computation is the value at the beginning of the cycle The data read operation loads a new value into AX0 by the end of the cycle For this same reason the destination register AR in the example above cannot be the destination for the memory read Computation With Memory Write The computation with memory write instruction is similar in structure to the computation with memory read the order of the clauses in the instruction line however is reversed First the memory write is per formed then the computation as shown below DM IO MO AR AR AXO AYO Again the value of the source register for the memory write AR in this example is the value at the beginning of the instruction The computa tion loads a new value into the same register this is the value in AR at the end of this instruction Reversing the order of the clauses would imply that the result of the computation is written to memory when in fact the previous value of the register is what is written There is no requirement that the same register be used in this way although this will usually be the case in orde
138. ister the wait state mode select bit determines whether the assigned wait state value operates in a 1x or 2x 1 mode ADSP 2185M ADSP 2185N ADSP 2186M ADSP 2186N ADSP 2188M ADSP 2187N 2 10 ADSP 218x Instruction Set Reference Programming Model ADSP 2189M ADSP 2188N ADSP 2189N Other memory mapped registers control the IDMA port and byte mem ory DMA BDMA port for booting and runtime operations These registers can be used in many ways that includes selecting the byte mem ory page operating in data packing mode or forcing the boot from software ADSP 218x Instruction Set Reference 2 11 Program Example Program Example Listing 2 1 presents an example of an FIR filter program written for the ADSP 2181 followed by a discussion of each part of the program The program can also be executed on any other ADSP 218x processor with minor modifications This FIR filter program demonstrates much of the conceptual power of the ADSP 218x family architecture and instruction set Listing 2 1 Include File Constants Initialization ADSP 2181 FIR Filter Routine serial port O used for I 0 internally generated serial clock 40 000 MHz processor clock rate is divided to generate 1 5385 MHz serial clock serial clock divided to 8 kHz frame sampling rate ei A include lt def2181 h gt define taps 15 define taps less _one 14 B section dm dm_data var circ data_buffer taps dm data buffer section
139. it 0 STATUS GENERATED No status bits affected INSTRUCTION FORMAT ALU MAC operation with Data Memory Write Instruction Type 4 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 1 G 1 0 AMF 0 0 0 0 0 DREG I M Data Memory Write Immediate Data Instruction Type 2 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 1 G Data I M AMF specifies the ALU or MAC operation to be performed in parallel with the Data Memory Write In this case AMF 00000 indicating a no opera tion for the ALU MAC function Data represents the actual 16 bit value To choose a data register DREG refer to the table DREG Selection Codes on page A 14 4 130 ADSP 218x Instruction Set Reference G specifies which Data Address Generator DAG the I and M registers are selected from These registers must be from the same DAG as separated by the gray bar above I specifies the indirect address pointer 1 register M specifies the modify register M register SEE ALSO e DAG Selection Codes on page A 17 e Index Register Selection Codes on page A 17 e Modify Register Selection Codes on page A 18 ADSP 218x Instruction Set Reference 4 131 Move Instructions Program Memory Write Indirect Address SYNTAX PM 4 M4 dreg 5 5 6 6 7 7 Permissible dregs AX0 MX0 SI AX1 MX1 SE AYO MYO SRI AY1 MY1 SRO AR MR
140. ith discussion Chapter three describes the process to create executable programs for the ADSP 218x DSP It provides several software examples that can be used to create programs Chapter four presents information organized by the type of instruction Instruction types relate to the machine language opcode for the instruc tion On this DSP the opcodes categorize the instructions by the portions of the DSP architecture that execute the instructions Each reference page for an instruction shows the syntax of the instruction describes its function gives one or two assembly language examples and identifies fields of its opcode The instructions are also referred to by type ranging from 1 to 31 These types correspond to the opcodes that ADSP 218x DSPs recognize but are for reference only and have no bear ing on programming Some instructions have more than one syntactical form for example instruction Multiply on page 4 75 has many distinct forms Many instructions can be conditional These instructions are prefaced by IF cond for example IF EQ MR MXO MYO SS In a conditional instruction the execution of the entire instruction is based on the condition 1 2 ADSP 218x DSP Instruction Set Reference Introduction The following instructions groups are available for ADSP 218x DSP e Quick List Of Instructions on page 4 1 This section provides a a quick reference to all instructions e ALU Instructio
141. last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled STATUS GENERATED No status bits affected INSTRUCTION FORMAT Conditional JUMP Direct Instruction Type 10 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 0 0 0 1 1 1 JADDR COND Conditional JUMP Indirect Instruction Type 19 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 0 0 0 0 1 01 1 0 0 0 0 0 0 0 0 O0 JO 1 COND I specifies the I register Indirect Address Pointer ADDR Immediate jump address COND Condition SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e Index Register Selection Codes on page A 17 4 140 ADSP 218x Instruction Set Reference JUMP or CALL on Flag In Pin SYNTAX IF FLAG_IN JUMP lt addr gt NOT FLAG_IN CALL EXAMPLE IF FLAG_IN JUMP service_proc_three DESCRIPTION Test the condition of the FI pin of the processor and if set to one per form the specified jump or call If FI is zero then perform a no operation Omitting the flag in condition reduces the instruction to a standard JUMP or CALL The JUMP instruction causes program execution to continue at the address specified by the instruction The addressing mode for the JUMP on FI must be direct The CALL instruction is intended for calling subroutines CALL pushes the PC stack with the return address and causes program exec
142. low words AXO AR Add high words carry Copy result if required xi Ky E 7 s Test the optional condition and if true perform the specified addition If false then perform a no operation Omitting the condition performs the addition unconditionally The addition operation adds the first source operand to the second source operand along with the ALU carry bit AC if designated by the C notation using binary addition The result is stored in the destination register The operands are contained in the data regis ters or constant specified in the instruction ADSP 218x Instruction Set Reference 4 33 ALU Instructions STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ P _ AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Set if an arithmetic overflow occurs Cleared otherwise AC Set if a carry is generated Cleared otherwise INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF 10010 for yop C AMF 10011 for xop yop Note that xop C is a special case of xop yop C with yop 0 ri Destination register Yop Y operand Xop X operand COND Con
143. ls zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Set if an arithmetic overflow occurs Cleared otherwise AC Set if a carry is generated Cleared otherwise INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF 10110 for xop yop C 1 operation AMF 10111 for xop yop operation Note that xop C 1 isa special case of xop yop 1 with yop 0 Z Destination register Yop Y operand Xop X operand COND Condition xop constant Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF YY Xop CC BO JCOND 4 38 ADSP 218x Instruction Set Reference Instruction Set AMF specifies the ALU or MAC operation in this case AMF 10010 for xop constant C 1 AMF 10011 for xop constant Z Destination register COND Condition Xop X operand BO CC and YY specify the constant SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e BO CC and YY ALU MAC Constant Codes on page A 25 e ALU MAC Result Register Codes on page A 25 e AME Function Codes on page A 10 e X Operand Codes on page
144. lue The shift code depends on which exponent detector mode is used HI HIX LO In the HI mode the input is interpreted as a single precision signed num ber or as the upper half of a double precision signed number The exponent detector counts the number of leading sign bits in the source operand and stores the resulting shift code in SE The shift code will equal the negative of the number of redundant sign bits in the input In the HIX mode the input is interpreted as the result of an add or subtract which may have overflowed HIX is intended to handle shifting and nor malization of results from ALU operations The HIX mode examines the ALU Overflow bit AV in the Arithmetic Status Register if AV is set then the effective exponent of the input is 1 indicating that an ALU overflow occurred before the EXP operation and 1 is stored in SE If AV is not set then HIX performs exactly the same operations as the HI mode ADSP 218x Instruction Set Reference 4 107 Shifter Instructions In the LO mode the input is interpreted as the lower half of a double pre cision number In performing the EXP operation on a double precision number the higher half of the number must first be processed with EXP in the HI or HIX mode and then the lower half can be processed with EXP in the LO mode If the upper half contained a non sign bit then the correct shift code was generated in the HI or HIX operation and that is the code that is stored in
145. manual for details Generating source code requires creating code modules which can be written in either assembly language or C language These modules include 3 4 ADSP 218x Instruction Set Reference Software Examples a main program subroutines or data variable declarations The C mod ules are compiled by the C compiler cc218x exe Each code module is assembled separately by the assembler which produces an object file DOJ The DOJ file is input to the Linker 1inker exe along with the LDF file The linker links several object modules together to form an executable program DXE The linker reads the target hardware information from the LDF file to determine appropriate addresses for code and data You specify the segment your code or data belongs to in the assembly file You specify the location of the segment in the LDF file The linker places non relocatable code or data modules at the specified memory addresses provided the memory area has the correct attributes The linker selects addresses for relocatable object The linker generates a memory image file DXE containing a single executable program which may be loaded into a VisualDSP debugger session simulator or emulator for testing The simulator provides windows that display different portions of the hardware environment To replicate the target hardware the simulator configures memory according to the memory specification in the LDF file The resulting s
146. n 2 A Y n 1 A Y n 2 Higher order filters can be obtained by cascading several biquad sections with appropriate coefficients The biquad sections can be scaled separately and then cascaded in order to minimize the coefficient quantization and the recursive accumulation errors A subroutine that implements a high order filter is shown in Listing 3 2 A circular buffer in program memory contains the scaled biquad coeffi cients These coefficients are stored in the order By By By Ap and Ay for each biquad The individual biquad coefficient groups must be stored in the order that the biquads are cascaded Listing 3 2 Cascaded Biquad IIR Filter SECTION DATA datal var number_of_biquads SECTION CODE program FR Nth order cascaded biquad filter subroutine x Calling Parameters x SRi input X n I0 gt delay line buffer for X n 2 X n 1 3 8 ADSP 218x Instruction Set Reference M2 F F FF F FF F FF F FF F FF F FF FF OF OF GLOBAL biquad sections M2 M3 SE Y n 2 LO 0 r Il 1 3 Return Value SRI Y n 1 output sample Y n ADSP 218X biquad Altered Registers MXO MX1 MYO MR SR Computation Time with N even ADSP 218X 8 x N 2 5 cycles 8 x N 2 5 5 cycles CNTR number_of_biquads DO secti SE D MX0 ons U I1 M DM IO MR MXO MY 0 MR M MR M MR M DM I0 M0 R MX
147. n Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 1 0 0 Z AMF 0 0 Xop 0 0 0 1 COND AMF specifies the ALU or MAC operation in this case AMF FUNCTION Data Format X Operand 01000 MR xop xop SS Signed 01011 MR xop xop UU Unsigned 00010 MR xop xop RND Signed Zz Destination register COND Condition Xop X operand register SEE ALSO e IF Condition Codes Table 4 9 on page 4 25 e Status Condition Codes on page A 12 e ALU MAC Result Register Codes on page A 25 e AMF Function Codes on page A 10 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 4 82 ADSP 218x Instruction Set Reference Instruction Set Multiply with Cumulative Subtract SYNTAX IF cond JMR MR xop x yop SS MF xop GSU US UU RND Permissible xops Permissible yops Permissible conds MXO AR MYO EQ LE AC Mx1 SRI MY1 NE NEG NOT AC MR2 SRO MF GT POS MV MRI GE AV NOT MV MRO LT NOT AV NOT CE EXAMPLES IF LT MR MR MX1 MYO SU xop yop MR MR MXO MXO SS xop yop DESCRIPTION Test the optional condition and if true then multiply the two source operands subtract the product from the present contents of the MR regis ter and store the result in the destination location If the condition is not true perform a no operation Omitting t
148. n Table 4 9 Table 4 8 Program Flow Control Instructions CIF cond JUMP 14 15 16 17 lt address gt IF FLAG_IN JUMP lt address gt NOT FLAG_IN IF cond CALL 14 15 16 17 lt address gt LE FLAG_IN CALL lt address gt OT FLAG_IN LIF cond RTS LIF cond RTI DO lt address gt UNTIL termination IDLE n 4 24 ADSP 218x Instruction Set Reference Table 4 9 IF Status Condition Codes Instruction Set Syntax Status Condition True If EQ Equal Zero AZ 1 NE Not Equal Zero AZ 0 LT Less Than Zero AN XOR AV 1 GE Greater Than or Equal Zero AN XOR AV 0 LE Less Than or Equal Zero AN XOR AV OR AZ 1 GT Greater Than Zero AN XOR AV OR AZ 0 AC ALU Carry AC 1 NOT AC Not ALU Carry AC 0 AV ALU Overflow AV 1 OT AV Not ALU Overflow AV 0 V MAC Overflow MV 1 OT MV Not MAC Overflow MV 0 EG X Input Sign Negative AS 1 POS X Input Sign Positive AS 0 OT CE Not Counter Expired FLAG_IN FI pin Last sample of FI pin 1 OT FLAG_IN Not FI pin Last sample of FI pin 0 1 Only available on JUMP and CALL instructions ADSP 218x Instruction Set Reference 4 25 Miscellaneous Instructions Miscellaneous Instructions There are several miscellaneous instructions NOP is a no operation instruc tion The PUSH POP instructions allow you to explicitly control the status counter PC and loop stacks interrupt servicing automatically pushes and
149. negative value 17 AR AXO 17 AR AXO 17 32 Bit Substraction AX1 AX0 AX1 AX0 AY1 AYO DIS AR_SAT If not already disabled 4 36 ADSP 218x Instruction Set Reference Instruction Set AR AXO AYO Subtract low words AR AX1 AYI C 1 AXO AR Sub high words borrow AX1 AR Copy result if required Negate MR Register MR MR DIS AR_SAT If not already disabled AR MRO Negate low word AR MR1 C 1 MRO AR Negate middle word borrow AR MR2 C 1 MRI AR Negate high word minus borrow MR2 AR DESCRIPTION Test the optional condition and if true then perform the specified sub traction If the condition is not true then perform a no operation Omitting the condition performs the subtraction unconditionally The subtraction operation subtracts the second source operand from the first source operand and optionally adds the ALU Carry bit AC minus 1 0x0001 and stores the result in the destination register The C 1 quan tity effectively implements a borrow capability for multiprecision subtractions The operands are contained in the data registers or constant specified in the instruction ADSP 218x Instruction Set Reference 4 37 ALU Instructions STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ P _ AZ Set if the result equa
150. nes and top of loop addresses for loops PC stack handling is automatic for subroutine calls and interrupt handling In addition the PC stack can be manually pushed or popped using the PC Stack Control instructions TOPPCSTACK reg and reg TOPPCSTACK 2 6 ADSP 218x Instruction Set Reference Programming Model The loop stack is 18 bits wide 14 bits for the end of loop address and 4 bits for the termination condition code The loop stack is four locations deep It is automatically pushed during the execution of a DO UNTIL instruction It is popped automatically during a loop exit if the loop was nested The loop stack may be manually popped with the POP LOOP instruction The status stack which is automatically pushed when the processor ser vices an interrupt accommodates the interrupt mask IMASK mode status MSTAT and arithmetic status ASTAT registers The depth and width of the status stack varies with each processor since each of the processors has a different numbers of interrupts The status stack is automatically popped when the return from interrupt RTI instruction is executed The status stack can be pushed and popped manually with the PUSH STS and POP STS instructions The count stack is 14 bits wide and holds counter CNTR values for nested counter based loops This stack is pushed automatically with the current CNTR value when there is a write to CNTR The counter stack may be manu ally popped with the POP CNTR instru
151. ns on page 4 32 These instruction specify oper ations that occur in the DSP s ALU e MAC Instructions on page 4 75 These instructions specify operations that occur in the DSP s Multiply Accumulator e Shifter Instructions on page 4 97 These instructions specify operations that occur in the DSP s Shifter e Multifunction Instructions on page 4 174 These instructions specify parallel single cycle operations e Move Instructions on page 4 116 These instructions specify memory and register access operations e Program Flow Instructions on page 4 136 These instructions specify program sequencer operations Appendix A lists the instruction encoding fields by type number and defines opcode mnemonics as listed alphabetically Development Tools The ADSP 218x is supported by VisualDSP an easy to use program ming environment comprised of an Integrated Development Environment IDE and Debugger VisualDSP lets you manage projects from start to finish from within a single integrated interface Because the project development and debug environments are integrated you can move easily between editing building and debugging activities ADSP 218x DSP Instruction Set Reference 1 3 Development Tools Flexible Project Management The IDE provides flexible project manage ment for the development of DSP applications The IDE includes access to all the activities necessary to create an
152. o Operation Table A 2 AMF Function Codes Code Function Mnemonic 0 0 X Y RND 0 0 MR X Y RND 0 0 MR X Y RND 0 0 KEY SS Clear when y 0 0 0 X Y SU 0 0 Dae US 0 0 X Y UU 0 1 MR X Y SS 0 1 MR X Y SU 0 1 MR X Y US 0 1 MR X Y UU 0 1 MR X Y SS 0 1 MR X Y SU ADSP 218x DSP Instruction Set Reference Instruction Coding Table A 2 AMF Function Codes Code Function Mnemonic 0 1 1 1 0 MR X Y US 0 1 1 1 1 MR X Y UU Table A 3 ALU Function Codes Code Function 0 0 oO 0 Y Clear when y 0 0 0 0 at Y 1 PASS 1 when y 0 0 0 1 0 X V C COR RE X Y X when y 0 0 0 0 NOT Y 0 0 ik Y 0 1 0 X Y C 1 X C 1 when y 0 0 1 1 X Y 1 0 0 0 Y 1 PASS 1 when y 0 1 0 0 1 y X X when y 0 1 0 1 0 Y X C 1 X C 1wheny 0 ADSP 218x DSP Instruction Set Reference A 11 Opcode Mnemonics Table A 3 ALU Function Codes Code Function 0 1 1 NOT X 0 0 X AND Y 0 1 X ORY 1 0 X XOR Y 1 1 ABS X BO See YY CC BO ALU MAC Constant Codes Type 9 on page A 25 CC See YY CC BO ALU MAC Constant Codes Type 9 on page A 25 COND Status Condition Codes Table A 4 Status Condition Codes Code Description Condition 0000 Equal EQ 0001 Not equal NE 001 0 Greater than GT 0011 Less
153. omplished by first storing the 16 bit divisor in an Xop register AXO AX1 AR MR2 MR1 MRO SR1 or SRO The 32 bit dividend ADSP 218x Instruction Set Reference 4 67 ALU Instructions must be stored in two separate 16 bit registers The lower 16 bits must be stored in AYO while the upper 16 bits can be in either AY1 or AF The DIVS primitive is executed once with the proper operands ex DIVS AY1 AX0 to compute the sign of the quotient The sign bit of the quotient is determined by XORing exclusive or the sign bits of each operand The entire 32 bit dividend is shifted left one bit The lower fifteen bits of the dividend with the recently determined sign bit appended are stored in AYO while the lower fifteen bits of the upper word with the MSB of the lower word appended is stored in AF To complete the division 15 DIVQ instructions are executed Operation of the DIVQ primitive is described below Unsigned Division Computing an unsigned division is done like signed division except the first instruction is not a DIVS but another DIVQ The upper word of the dividend must be stored in AF and the AQ bit of the ASTAT register must be set to zero before the divide begins The DIVO instruction uses the AQ bit of the ASTAT register to determine if the dividend should be added to or subtracted from the partial remainder stored in AF and AYO If AQ is zero a subtract occurs A new value for AQ is determined by XORing the MSB of
154. on almost any ALU MAC or Shifter operation may be combined with any register to register move or with a register move to or from internal or external memory Because the multifunction instructions best illustrate the power of the processors architecture in the next section we begin with a discussion of this group of instructions 4 6 ADSP 218x Instruction Set Reference Instruction Set Multifunction Instructions Multifunction operations take advantage of the inherent parallelism of the ADSP 218x family architecture by providing combinations of data moves memory reads memory writes and computation all in a single cycle ALU MAC with Data and Program Memory Read Perhaps the single most common operation in DSP algorithms is the sum of products performed as follows e Fetch two operands such as a coefficient and data point e Multiply the operands and sum the result with previous products The ADSP 218x family processors can execute both data fetches and the multiplication accumulation in a single cycle Typically a loop of multi ply accumulates can be expressed in ADSP 218x source code in just two program lines Since the on chip program memory of the ADSP 218x processors is fast enough to provide an operand and the next instruction in a single cycle loops of this type can execute with sustained single cycle throughput An example of such an instruction is MR MR MXOxMYO SS MXO DM IO MO MYO PM 14 M5 The first cl
155. on Codes on page A 10 e X Operand Codes on page A 24 e Y Operand Codes on page A 24 4 42 ADSP 218x Instruction Set Reference Instruction Set Bitwise Logic AND OR XOR SYNTAX IF cond AR xop AND yop AF OR constant XOR Permissible xops Permissible yops Permissible conds AXO MR2 AYO EQ LE AC AX1 MRI AY1 NE NEG NOT AC AR MRO AF GT POS MV SRI GE AV NOT MV SRO LT NOT AV NOTCE Permissible constants 0 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32767 2 3 5 9 17 33 65 129 257 513 1025 2049 4097 8193 16385 32768 EXAMPLES AR AXO XOR AYO IF FLAG_IN AR MRO AND 8192 DESCRIPTION Test the optional condition and if true then perform the specified bitwise logical operation logical AND inclusive OR or exclusive OR If the condi tion is not true then perform a no operation Omitting the condition performs the logical operation unconditionally The operands are con tained in the data registers or constant specified in the instruction ADSP 218x Instruction Set Reference 4 43 ALU Instructions STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ _ _ _ L 0 0 AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise AV Always cleared AC Always cleared INSTRUCTION FORMAT Conditional ALU MAC operat
156. on resumes at the instruction following the IDLE instruction Once these setup instructions have been executed all further activity takes place in the interrupt service routine shown in Listing 2 2 Listing 2 2 Interrupt Routine fir start si rx0 read from sport0O dm i0 m0 si transfer data to buffer mr 0 my0 pm i4 m4 mx0 dm i0 m0 setup multiplier for loop cntr taps_less_one perform loop taps 1 times do convolution until convolution mr mr Ces x0 my0 ss my0 pm i4 m4 mx0 dm i0 m0 perform MAC and fetch next values mr mr if mv sat tx0 mrl rea mx0 my0 rnd Nth pass of loop with rounding of result mr write result to sportO tx return from interrupt Example Program Interrupt Routine Discussion This subroutine transfers the received data to the next location in the cir cular buffer overwriting the oldest sample All samples and coefficients are then multiplied and the products are accumulated to produce the next ADSP 218x Instruction Set Reference 2 15 Program Example output value The subroutine checks for overflow and saturates the output value to the appropriate full scale It then writes the result to the transmit section of SPORTO and returns The subroutine begins by reading a new sample from SPORT0 s receive data register RX0 into the SI register The choice of SI is of no particular significance
157. op The count stack allows the nesting of count based loops to four levels A write to CNTR pushes the current value onto the count stack before writing ADSP 218x Instruction Set Reference 2 5 Overview the new value The following example pushes the current value of CNTR on the count stack and then loads CNTR with 10 CNTR 10 OWRCNTR is a special syntax with which you can overwrite the count value for the current loop without pushing CNTR on the count stack OWRCNTR cannot be read i e used as a source register and must not be written in the last instruction of a DO UNTIL loop Status And Mode Bits The stack status SSTAT register contains full and empty flags for stacks The arithmetic status ASTAT register contains status flags for the compu tational units The mode status MSTAT register contains control bits for various options MSTAT contains 4 bits that control alternate register selec tion for the computational units bit reverse mode for DAG1 and overflow latch and saturation modes for the ALU MSTAT also has 3 bits to control the MAC result placement timer enable and Go mode enable Use the Mode Control instruction ENA or DIS to conveniently enable or disable processor modes Stacks The program sequencer contains four stacks that allow loop subroutine and interrupt nesting The PC stack is 14 bits wide and 16 locations deep It stores return addresses for subroutines and interrupt service routi
158. or ASHIFT with a positive shift constant the operand is shifted left with a negative shift constant the operand is shifted right The 32 bit output field is sign extended to the left the MSB of the input is replicated to the left and the output is zero filled from the right Bits shifted out of the high order bit in the 32 bit destination field SR are dropped Bits shifted out of the low order bit in the destination field SR are dropped 4 112 ADSP 218x Instruction Set Reference To shift a double precision number the same shift constant is used for both halves of the number On the first cycle the upper half of the num ber is shifted using an ASHIFT with the HI option on the following cycle the lower half is shifted using an LSHIFT with the LO and OR options This prevents sign bit extension of the lower word s MSB STATUS GENERATED No status bits affected INSTRUCTION FORMAT Shift Immediate operation Instruction Type 15 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 SF Xop lt exp gt SF Shifter Function 0100 ASHIFT HI 0101 ASHIFT HI OR 1110 ASHIFT LO 0111 ASHIFT LO OR Xop Shifter operand lt exp gt 8 bit signed shift value SEE ALSO e Shifter Function Codes on page A 21 e X Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 113 Shifter Instructions Logical Shift Immediate SYN
159. order so that the FFT output will be in the normal sequential order The next subrou tine computes the FFT The third subroutine scales the output data to maintain the block floating point data format The program is contained in four modules The main module declares and initializes data buffers and calls subroutines The other three modules con tain the FFT bit reversal and block floating point scaling subroutines The main module calls the FFT and bit reversal subroutines The FFT module calls the data scaling subroutine The FFT is performed in place that is the outputs are written to the same buffer that the inputs are read from Main Module The dit_fft_main module is shown in Listing 3 5 N is the number of points in the FFT in this example N 1024 and N_div_2 is used for speci fying the lengths of buffers To change the number of points in the FFT you change the value of these constants and the twiddle factors The data buffers twid_real and twid_imag in program memory hold the twiddle factor cosine and sine values The inplacereal inplaceimag inputreal and inputimag buffers in data memory store real and imaginary data values Sequentially ordered input data is stored in inputreal and inputimag This data is scrambled and written to inplacereal and inpla ceimag A four location buffer called padding is placed at the end of inplaceimag to allow data accesses to exceed the buffer length This buffer assists in debugging but
160. ory read is register indirect with post modify For linear i e non circular indirect addressing the L reg ister corresponding to the I register used must be set to zero The contents of the source are always right justified in the destination register A multifunction instruction requires three items to be fetched from mem ory the instruction itself and two data words No extra cycle is needed to execute the instruction as long as only one of the fetches is from external memory If two off chip accesses are required however the instruction fetch and one data fetch for example or data fetches from both program and data memory then one overhead cycle occurs In this case the program mem ory access occurs first then the data memory access If three off chip accesses are required the instruction fetch as well as data fetches from both program and data memory then two overhead cycles occur 4 190 ADSP 218x Instruction Set Reference STATUS GENERATED No status bits are affected INSTRUCTION FORMAT ALU MAC with Data amp Program Memory Read Instruction Type 1 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 10 1 1 IPD JDD AMF 0 0 0 0 0 PM DM DM DM I M I M AMF specifies the ALU or MAC function In this case AMF 00000 des ignating a no operation for the ALU or MAC function PD Program Destination register DD Data Destination register AMF ALU MAC operation Is Indirect address r
161. page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ _ _ AZ Set if the result equals zero Cleared otherwise AN Set if the result is negative Cleared otherwise ADSP 218x Instruction Set Reference 4 73 ALU Instructions AV Set if an arithmetic overflow occurs Cleared otherwise AC Set if carry is generated Cleared otherwise INSTRUCTION FORMAT Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 0 0 1 0 1 0 AMF ALU codes only 1 0 Yop Xop 1 0 1 O 1 0 1 0 AMF specifies the ALU or MAC operation only ALU operations allowed Xop X operand SEE ALso Yop Y operand AMF Function Codes on page A 10 X Operand Codes on page A 24 Y Operand Codes on page A 24 4 74 ADSP 218x Instruction Set Reference MAC Instructions Multiply SYNTAX IF cond Permissible xops MX0 MX1 MR2 MRI MRO EXAMPLES AR SRI SRO MR MF i xop Permissible yops MyY0 MY1 MF 0 yop xop EQ NE GT GE LT ESS SU US UU RND Permissible conds LE NEG POS AV NOT AV Conditional multiply xop yop IF EQ MR MXO MF UU Unconditional MF SRO SRO SS multiply xop yop Instruction Set AC NOT AC MV NOT MV NOT CE 32 bit multiply MR2 MR1 MRO SR1 SRO MX1 MXO MY1 MYO DIS M_MODE
162. placed at the reset vector address PM 0x0000 The first location is the reset vector instruction which jumps to main Interrupt vectors that are not used are filled with a return from interrupt instruction This is a preferred pro gramming practice rather than a necessity The SPORTO receive interrupt vector jumps to the interrupt service routine Section D main sets up the index 1 length L and modify M registers used to address the two circular buffers A non zero value for length acti vates the processor s modulus logic Each time the interrupt occurs the I register pointers advance one position through the buffers The clear loop sets all values in the data memory buffer to zero Section E sets up the processor s memory mapped control registers used in this system See Appendix B in the ADSP 218x Hardware Reference Man ual for control register initialization information 2 14 ADSP 218x Instruction Set Reference Programming Model SPORTO is set up to generate the serial clock internally at 1 5385 MHz based on a processor clock rate of 40 MHz The receive and transmit sig nals are both required The receive signal is generated internally at 8 kHz while the transmit signal comes from the external device communicating with the processor Finally SPORTO is enabled and the interrupts are enabled Now the IDLE instruction causes the processor to wait for interrupts After the return from interrupt instruction executi
163. r to pipeline operands to the computation ADSP 218x Instruction Set Reference 4 9 Multifunction Instructions The restrictions on computation operations are identical to those given above All ALU operations except division all MAC operations and all Shifter operations except SHIFT IMMEDIATE are legal Computations must be unconditional Computation with Data Register Move This final type of multifunction instruction performs a data register to data register move in parallel with a computation Most of the restrictions applying to the previous two instructions also apply to this instruction AR AXO AYO AXO MR2 Here an ALU addition operation occurs while a new value is loaded into AXO from MR2 As before the value of AX0 at the beginning of the instruc tion is the value used in the computation The move may be from or to all ALU MAC and Shifter input and output registers except the feedback registers AF and MF and SB In the example the data register move loads the AX0 register with the new value at the end of the cycle All ALU operations except division all MAC operations and all Shifter operations except SHIFT IMMEDIATE are legal Computation must be unconditional A complete list of data registers is given in Processor Registers reg and dreg on page 4 22 A complete list of the permissible xops and yops for computational operations is given in the reference page for each instruc tion Summary of Valid Com
164. rame sync required receive width 0 transmit frame sync required transmit width 0 external transmit frame sync internal receive frame sync u law companding 8 bit words ax0 0x69b 7 dm Sport0O_Ctrl_Reg ax0 ax0 0x1000 enable sport0O dm Sys_Ctrl_Reg ax0 icntl 0x00 disable interrupt nesting imask 0x0060 enable sportO rx and tx interrupts only mainloop ADSP 218x Instruction Set Reference 2 13 Program Example idle wait here for interrupt jump mainloop jump back to idle after rti Example Program Setup Routine Discussion The setup and main loop routine performs initialization and then loops on the IDLE instruction to wait until the receive interrupt from SPORTO occurs The filter is interrupt driven When the interrupt occurs control shifts to the interrupt service routine shown in Listing 2 2 Section A of the program declares two constants and includes a header file of definitions named def2181 h Section B of the program includes the assembler directives defining two circular buffers in on chip memory one in data memory RAM that is used to hold a delay line of samples and one in program memory RAM that is used to store coefficients for the filter The coefficients are actually loaded from an external file by the linker These values can be changed without reassembling only another linking is required Section C shows the setup of interrupts The first instruction is
165. rands xop and yop or xop and xop are considered to be in twos complement format All rounding is unbiased except on the ADSP 217x ADSP 218x and ADSP 21msp58 59 processors which offer a biased rounding mode For a discussion of biased vs unbiased rounding see the section Rounding Mode in the ADSP 218x DSP Hardware Reference Manual Chapter 2 Computational Units 4 80 ADSP 218x Instruction Set Reference Instruction Set STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ _ _ _ _ _ _ _ MV Set on MAC overflow if any of the upper 9 bits of MR are not all one or zero Cleared otherwise INSTRUCTION FORMAT xop yop Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 O0 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF FUNCTION Data Format X Operand Y Operand 01000 MR xop xop SS Signed Signed 01001 MR xop yop SU Signed Unsigned 01010 MR xop yop US Unsigned Signed 01011 MR xop yop UU Unsigned Unsigned 00010 MR xop yop RND Signed Signed Zi Destination register Yop Y operand register Xop X operand register COND Condition ADSP 218x Instruction Set Reference 4 81 MAC Instructions xop xop Conditional ALU MAC operatio
166. rce register group SRC RGP and the source register SOURCE REG refer to the table Register Selection Codes on page A 19 reg TOPPCSTACK Internal Data Move Instruction Type 17 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 0 0 0 0 DST 1 1 DEST 1 1 1 1 RGP REG To choose the destination register group DST RGP and the destination register DEST REG refer to the table Register Selection Codes on page A 19 4 160 ADSP 218x Instruction Set Reference Mode Control SYNTAX ENA BIT_REV PORE DIS AV_LATCH AR_SAT SEC_REG G_MODE M_MODE TIMER EXAMPLE DIS AR_SAT ENA M_MODE DESCRIPTION Enables ENA or disables D1S the designated processor mode The corre sponding mode status bit in the mode status register MSTAT is set for ENA mode and cleared for DIS mode At reset MSTAT is set to zero meaning that all modes are disabled Any number of modes can be changed in one cycle with this instruction Multiple ENA or DIS clauses must be separated by commas ADSP 218x Instruction Set Reference 4 161 MISC Instructions MSTAT Bits Description 0 SEC_REG Alternate Register Data Bank 1 BIT_REV Bit Reverse Mode on Address Generator 1 2 AV_LATCH ALU Overflow Status Latch Mode 3 AR_SAT ALU AR Register Saturation Mode 4 M_MODE MAC Result Placement Mode 5 TIMER Timer Enable 6 G_MODE Enables GO Mode The da
167. rograms for the ADSP 218x family proces sors The overview is followed by software examples that you can use as a guide when writing your own applications The software examples presented in this chapter are used for a variety of DSP operations The FIR filter and cascaded biquad IIR filter are general filter algorithms that can be tailored to many applications Matrix multi plication is used in image processing and other areas requiring vector operations The sine function is required for many scientific calculations The FFT fast Fourier transform has wide application in signal analysis Each of these examples is described in greater detail in Digital Signal Pro cessing Applications Using The ADSP 2100 Family Volumel available from our website at www analog com They are presented here to show some aspects of typical programs The FFT example is a complete program including a subroutine that per forms the FFT a main calling program that initializes registers and calls the FFT subroutine and an auxiliary routine Each of the other examples is shown as a subroutine in its own module The module starts with a SECTION assignment for data or code using the section name defined in the LDF file The subroutine can be called from a program in another module that declares the starting label of the subrou tine as an external symbol EXTERN This is the same label that is declared with the GLOBAL directive in the subroutine module This make
168. ry accesses These features enable you to correct coding errors identify bottlenecks and examine DSP per formance You can use the custom register option to select any combination of registers to view in a single window The Debugger can also generate inputs outputs and interrupts so you can simulate real world application conditions Software Development Tools The Software Development Tools which support the ADSP 218x Family allow you to develop applications that 1 4 ADSP 218x DSP Instruction Set Reference Introduction take full advantage of the DSP architecture including shared memory and memory overlays Software Development tools include C Compiler C Runtime Library DSP and Math Libraries Assembler Linker Loader Simulator and Splitter C Compiler amp Assembler The C Compiler generates efficient code that is optimized for both code density and execution time The C Compiler allows you to include Assembly language statements inline Because of this you can program in C and still use Assembly for time critical loops You can also use pretested Math DSP and C Runtime Library routines to help shorten your time to market The ADSP 218x Family Assembly lan guage is based on an algebraic syntax that is easy to learn program and debug The add instruction for example is written in the same manner as the actual equation using registers for variables for example AR AX0 AY 03 Linker amp Loader The Linker pro
169. ry interface timer SPORTs host interface and DMA interface Processor Core DATA ADDRESS GENERATORS DAG1 DAG2 DM addressing only DM and PM addressing Bit reverse capability Indirect branch capability TIMER MEMORY INTERFACE 0x3FFD TPERIOD System Control Register Wait States 4 4 DMOVLAY PMOVLAY Ox3FFF Ox3FFC TCOUNT Ox3FFB TSCALE Ox3FFE SPORT 0 RX0 TXO LOOP PC STACK STACK 4X 18 16X14 14 8 OWRCNTR SSTAT ONT 10 7 8 count LIMASK MSTAT ASTAT STACK n 4X14 STATUS STACK Multichannel enables 0x3FFA RX 31 16 0x3FF9 RX 15 0 0x3FF8 TX 31 16 0x3FF7 TX 15 0 SPORTO Control IDMA PORT Ox3FF6 Control MA PORT Ox3FF5 SCLKDIV PROGRAMMABLE FLAGS Ox3FF4 _RFSDIV Ox3FF3 Autobuffer Status Stack Depth 12 memory locations Width 25 bits IDMA Registers BDMA Registers IDMA Control Ox3FE4 Register BWCOUNT 0x3FE3 BDMA Control Tan I AF MR1 MRO l MF SHIFTER Programmable SPORT 1 Flag Registers 0x3FE2 BEAD PFTYPE 0x3FE1 BIAD RX1 TX1 PFDATA SPORT1 Control 0x3FF2 Control 0x3FF1 _SCLKDIV 0x3FF0 _RFSDIV 0x3FEF Autobuffer BUS EXCHANGE 8 PX Figure 2 1 ADSP 218x DSP Registers ADSP 218x Instruction Set Reference
170. s the corresponding stack over flow bit is set in SSTAT and this bit stays set indicating there has been loss of information Once set the stack overflow bit can only be cleared by resetting the processor INSTRUCTION FORMAT Stack Control Instruction Type 26 23 22 21 20 19 18 17 16 15 14 13 12 11109876543 2 1 0 000 00 1 0 0 00 0 0 0 0 0000 0 O Pp Lp Cp Spp ADSP 218x Instruction Set Reference 4 157 MISC Instructions Pp PC Stack Control LP Loop Stack Control Cp Counter Stack Control Spp Status Stack Control SEE ALSO e Mode Control Codes on page A 6 TOPPCSTACK A special version of the register to register Move instruction Type 17 is provided for reading and popping or writing and pushing the top value of the PC stack the normal POP PC instruction does not save the value popped from the stack To save this value into a register you must use the following special instruction reg TOPPCSTACK pop PC stack into reg toppcstack may also be lowercase The PC stack is also popped by this instruction after a one cycle delay An NOP should usually be placed after the special instruction to allow the pop to occur properly reg TOPPCSTACK NOP allow pop to occur correctly There us no standard PUSH PC stack instruction To push a specific value onto the PC stack therefore use the following special instruction TOPPCSTACK reg push reg contents onto PC sta
171. s of the data memory location to the destination register The addressing mode is direct addressing desig nated by an immediate address value or by a label The data memory address is stored directly in the instruction word as a full 14 bit field The contents of the source are always right justified in the destination register after the read bit 0 maps to bit 0 Note that whenever MR1 is loaded with data it is sign extended into MR2 STATUS GENERATED No status bits affected ADSP 218x Instruction Set Reference 4 121 Move Instructions INSTRUCTION FORMAT Data Memory Read Direct Address Instruction Type 3 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 RGP ADDR REG ADDR contains the direct address to the source location in Data Memory To choose the source register group RGP and the source register REG refer to the table Register Selection Codes on page A 19 4 122 ADSP 218x Instruction Set Reference Data Memory Read Indirect Address SYNTAX dreg DM Permissible dregs AXO MX0 AX1 MX1 AYO MYO AY1 MY1 AR MR2 MRI MRO EXAMPLE nm fF Mm F ND oO f ND oO f SI SE SRI SRO AYO DM 13 M1 DESCRIPTION The Data Memory Read Indirect instruction moves the contents of the data memory location to the destination register The addressing mode is register indirect with post modify
172. s of the last instruction is pushed onto the loop stack along with the termination condition and the current program counter value plus 1 is pushed onto the PC stack ADSP 218x Instruction Set Reference 4 149 Program Flow Instructions Any nesting of DO loops continues the process of pushing the loop and PC stacks up to the limit of the loop stack size 4 levels of loop nesting or of the PC stack size 16 levels for subroutines plus interrupts plus loops With either or both the loop or PC stacks full a further attempt to per form the DO instruction will set the appropriate stack overflow bit and will perform a no operation STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT Not affected SSTAT 7 6 5 4 3 2 1 0 LSO LSE SSO SSE CSO CSE PSO PSE 0 _ _ _ 0 LSO Loop Stack Overflow set if the loop stack overflows otherwise not affected LSE Loop Stack Empty always cleared indicating loop stack not empty PSO PC Stack Overflow set if the PC stack overflows otherwise not affected PSE PC Stack Empty always cleared indicating PC stack not empty 4 150 ADSP 218x Instruction Set Reference INSTRUCTION FORMAT Do Until Instruction Type 11 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 1 0 1 Addr TERM ADDR specifies the address of the last instruction in the loop In the Instruction Syntax this field may be a program label or an
173. s signed division by a negative number If you attempt to use a negative number as the divisor the quo tient generated may be one LSB less than the correct result The other case concerns unsigned division by a divisor greater than 0x7FFF If the divisor in an unsigned division exceeds 0x7FFF an invalid quotient will be generated Negative Divisor Error The quotient produced by a divide with a negative divisor will generally be one LSB less than the correct result The divide algorithm implemented on the ADSP 218x family does not correctly compensate for the twos complement format of a negative number causing this inaccuracy There is one case where this discrepancy does not occur If the result of the division operation should equal 0x8000 then it will be correctly repre sented and not be one LSB off There are several ways to correct for this error Before changing any code however you should determine if a one LSB error in your quotient is a significant problem In some cases the LSB is small enough to be insignif icant If you find it necessary to have exact results two solutions are possible One is to avoid division by negative numbers If your divisor is negative take its absolute value and invert the sign of the quotient after division This will produce the correct result 4 70 ADSP 218x Instruction Set Reference Instruction Set Another technique would be to check the result by multiplying the quo tient by t
174. s the sub ADSP 218x Instruction Set Reference 3 1 Overview routine callable from routines defined in other ASM files The last instruction in each subroutine is the RTS instruction which returns con trol to the calling program Each module is prefaced by a comment block that provides the informa tion shown in Table 3 1 Table 3 1 Subroutine Modules and Comment Information Module Comment Information Calling Parameters Register values that the calling program must set before calling the subroutine Return Values Registers that hold the results of the subroutine Altered Registers Register used by the subroutine The calling program must save them before calling the subroutine and restore them afterward in order to preserve their values Computation Time The number of instruction cycles needed to perform the subroutine 3 2 ADSP 218x Instruction Set Reference Software Examples System Development Process The ADSP 218x family of processors is supported by a complete set of development tools Programming aids and processor simulators facilitate software design and debug In circuit emulators and demonstration boards help in hardware prototyping Software development tools include a C Compiler C Runtime Library DSP and Math Libraries Assembler Linker Loader Simulator and Split ter These tools are described in detail in the following documents Assembler Manual for ADSP 218x Family DS
175. ss sucsisiseiveroiimn 4 132 IO Space Read Wie asnidinnnmnenssudioinlinenetaibanuadane 4 134 Program Flow Jastructions dissem 4 136 ADSP 218x Instruction Set Reference v CONTENTS TUMI enren a 4 136 CAC arenon A T 4 139 TUMP or CALL on Plessis 4 141 Modit Fhg Oar Tin sunicucniaiee 4 143 RTS Return fram Subroutine Lai indienne dust 4 145 RTI Return fom Interrupt asus 4 147 Do Ual orsa R 4 149 E E E E AE A A A O ati 4 153 SR Tee aara 4 155 Cle annee 4 155 TOPICS TA susistomanaduacenaiiassdss 4 158 Mode Cg PRE NO PT EE PT 4 161 Tawrrupt Enable and DR dre ndadtiness 4 164 Program Memory Overlay Register Update oscene 4 165 Data Memory Overlay Register Update sens 4 168 Madily Address PS RE ananas 4 171 No Operation sie ET TE Te 4 173 Moaltihaictian Instroctions ctissossibisissiniininisiie 4 174 Computation with Memory Read ends 4 174 Computation with Register to Register Move ossee 4 180 Computation with Memory Write statement 4 185 Data and Program Memory Read esencon 4 190 ALU MAC with Data and Program Memory Read 4 192 vi ADSP 218x Instruction Set Reference CONTENTS INSTRUCTION CODING AVES ne a de ees A 1 pier Cen areri rir E A 2 prode NEENOTNO sence ene nausea A 10 INDEX ADSP 218x Instruction Set Reference vii CONTENTS viii ADSP 218x Instruction Set Reference 1 INTRODUCTION Purpose The ADSP 218x DSP Instruction Set Reference provides assembly syntax information for the A
176. ssseecessesereseeee 4 35 Subtract Y X Subtract Y X with Borrow suisses 4 39 Brewis Loge AND OR XOR synsmabhiotakukiiesikeiiakisi 4 42 Bit Manipulation TSTBIT SETBIT CLRBIT TGLBIT 4 45 eare PAS r N S 4 48 D EE A E A AA A A 4 53 Rs ene 4 55 Absolute Vale ADS cessent 4 57 teint smooth 4 60 RON A eee ne 4 62 Divide Primitives DIYS apd DIVO manne 4 64 Generate ALU Stratus Only NONE nement 4 72 MAC SMS ann 4 74 Mubiply sionisme adaiiansodio 4 74 Multiply with Cumulative Add ide vus asetagetaolieet d s 4 78 iv ADSP 218x Instruction Set Reference CONTENTS Malte wick Cumulative SUR either 4 82 SONS ni on anus 4 86 MAG CEI a sue etienne 4 90 PP ME Te 4 92 Conditional MR Sale san minsnd unennlssneus 4 95 Shater Instructions sommation 4 97 RUNS ARR Se Seneca Seeley eae eee reat das 4 97 Loreal CURIE antoine 4 100 NGS scien ie 4 103 Deriye PDO neurone 4 106 Black Exponent Adjust sure nsani as oasaeageaa 4 110 Arthmetne Shit Dee issdaeulninsi nlsipiaesses 4 112 Lopical SIT LE ais cr manettes 4 114 More PONS uote 4 116 PGE momo 4 116 L ad Register bomediape ccna nn donnees 4 118 Data Memory Read Direct Address societe 4 121 Data Memory Read Indirect Address scciisscscacivsivorcrciaaanares 4 123 Program Memory Read Indirect Address eeeeeeeeeeeees 4 125 Data Memory Write Direct Address serrarirnrssirsaririssssrs 4 127 Data Memory Write Indirect Address dansent 4 129 Program Memory Write Indirect Addre
177. struction Set Reference F FF FF FF FF FF FF FF OK defi defi defi defi Software Examples Calling Parameters inplacereal real input data in scrambled order inplaceimag all zeroes real input assumed twid_real twiddle factor cosine values twid_imag twiddle factor sine values groups N 2 bflys_per_group 1 node_space 1 Return Values inplacereal real FFT results sequential order inplaceimag imag FFT results sequential order Altered Registers 10 11 12 13 14 15 L0 L1 L2 L3 L4 L5 MO M1 M2 M3 M4 M5 AX0 AX1 AY0 AY1 AR AF MXO MX1 MYO MY1 MR SB SE SR SI Altered Memory inplacereal inplaceimag groups node_space bflys_per_group blk_exponent ne log2N 10 ne N 1024 ne nover2 512 ne nover4 256 RN twid_real twid_imag RN inplacereal inplaceimag RN groups bflys_per_group node_space RN bfp_adj AL fft_strt Eis CNTR log2N 2 Initialize stage counter MO 0 M1 1 L1 0 L2 0 L3 0 LA LENGTH twid_real L5 LENGTH twid_imag ADSP 218x Instruction Set Reference 3 17 Radix 2 Decimation in Time FFT L6 0 SB 2 STAGE 1 I0 inplacereal Ti inplacereal 1 I2 inplaceimag 13 inplaceimag 1 M2 2 CNTR nover2 AXO DM 1I0 M0 AYO DM 11 M0 AY1 DM 13 M0 DO group_1p UNTIL CE R AXO AYO AX1 DM 12 M0 B EXPADJ AR DM IO M2 AR R AXO AYO B EXPADJ AR MCI1 M2 AR AR AX1 AY1 B EXPADJ AR DM I2 M2 AR R AX1 AY1 AXO DM 10 MO
178. struction Set Reference Introduction e Access the Computer Products Division File Transfer Protocol FTP site at ftp ftp analog comor ftp 137 71 23 21 or ftp ftp analog com For Technical or Customer Support You can reach our Customer Support group in the following ways e E mail questions to dsp support analog com dsptools sup port analog com or dsp europe analog com European customer support e Telex questions to 924491 TWX 710 394 6577 e Cable questions to ANALOG NORWOODMASS e Contact your local ADI sales office or an authorized ADI distributor e Send questions by mail to Analog Devices Inc DSP Division One Technology Way P O Box 9106 Norwood MA 02062 9106 USA What s New in This Manual This is the preliminary edition of the ADSP 218x DSP Instruction Set Ref erence Summaries of changes between editions will start with the next edition ADSP 218x DSP Instruction Set Reference 1 7 Related Documents Related Documents For more information about Analog Devices DSPs and development products see the following documents ADSP 218x DSP Hardware Reference Getting Started Guide for VisualDSP amp ADSP 218x Family DSPs VisualDSP User s Guide for ADSP 218x Family DSPs C Compiler amp Library Manual for ADSP 218x Family DSPs Assembler Manual for ADSP 218x Family DSPs Linker amp Utilities Manual for ADSP 218x Family DSPs All the manuals are included in the software distribution CD ROM To access
179. struction Type 9 PASS constant constant F 0 1 1 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 0 0 1 0 0 JZ AMF YY Xop CC BO JCOND AMF specifies the ALU or MAC operation in this case AMF 10000 for PASS yop AMF 10001 for PASS yop 1 AMF 11000 for PASS yop 1 Z Destination register COND Condition Xop X operand BO CC and YY specify the constant 4 52 ADSP 218x Instruction Set Reference SEE ALSO Instruction Set IF Condition Codes Table 4 9 on page 4 25 Status Condition Codes on page A 12 BO CC and YY ALU MAC Constant Codes on page A 25 ALU MAC Result Register Codes on page A 25 AMF Function Codes on page A 10 X Operand Codes on page A 24 Y Operand Codes on page A 24 ADSP 218x Instruction Set Reference 4 53 ALU Instructions Negate SYNTAX L IF cond AR xop AF yop Permissible xops Permissible yops Permissible conds AXO MR2 AYO EQ LE AC AX1 MRI AY1 NE NEG NOT AC AR MRO AF GT POS MV SRI GE AV NOT MV SRO LT NOT AV NOT CE EXAMPLES IF LT AR AYO DESCRIPTION Test the optional condition and if true then NEGATE the source operand and store in the destination location If the condition is not true then per form a no operation Omitting the condition performs the NEGATE operation unconditionally The source operand is contained in the data register specified in the instruction
180. sversal filter is shown in Listing 3 1 Listing 3 1 Single Precision FIR Transversal Filter SECTION CODE program 1 FIR Transversal Filter Subroutine Calling Parameters I0 gt Oldest input data value in delay line LO Filter length N 14 gt Beginning of filter coefficient table L4 Filter length N 1 M5 CNTR Filter length 1 N 1 Return Values Rl Sum of products rounded and saturated IO gt Oldest input data value in delay line 14 gt Beginning of filter coefficient table 3 6 ADSP 218x Instruction Set Reference A Co Al in F FF F FF F Software Examples tered Registers MXO MYO MR putation Time N 1 5 2 cycles coefficients and data values are assumed to be 1 15 format GLOBAL fir fir Sop MR 0 MXO DM IO M1 MYO PM 14 M5 DO sop UNTIL CE MR MR MXO MYO SS MXO DM IO M1 MYO PM I4 M5 MR MR MXO MYOC RND IF MV SAT MR RTS ADSP 218x Instruction Set Reference 3 7 Cascaded Biquad IIR Filter Cascaded Biquad IIR Filter A second order biquad IIR filter section is represented by the transfer function in the z domain H z Y z X z Bo B 7 B2772 ik 1 soya 152 7 where A A Bo By and B are coefficients that determine the desired impulse response of the system H z The corresponding difference equa tion for a biquad section is Y n By X n By X n 1 By X
181. t operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ E 2 x x AZ Set if result equals zero Cleared otherwise AN Set if result is negative Cleared otherwise AV Set if an overflow is generated Cleared otherwise AC Set if a carry is generated Cleared otherwise AS Affected only when executing the Absolute Value operation ABS Set if the source operand is negative lt MAC gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ ADSP 218x Instruction Set Reference 4 177 Multifunction Instructions MV Set if the accumulated product overflows the lower order 32 bits of the MR register Cleared otherwise lt SHIFT gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ SS Affected only when executing the EXP operation set if the source operand is negative Cleared if the number is positive INSTRUCTION FORMAT ALU MAC operation with Data Memory Read Instruction Type 4 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 1 1 IG 0 Z AMF Yop Xop Dreg I M ALU MAC operation with Program Memory Read Instruction Type 5 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 1 0 1 0 Z AMF Yop Xop Dreg I M Shift operation with Data Memory Read Instruction Type 12 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 G 0 JSF Xop Dreg I M 4 178 ADSP 2
182. t MAC gt lt SHIFT gt lt ALU gt Any ALU instructions except DIVS DIVQ lt MAC gt Any multiply accumulate instruction lt SHIFT gt Any shifter instruction except Shift Immediate May not be conditional instruction AR MR result registers must be used not AF MF feedback registers or NONE SEE ALSO e ALU MAC with Data and Program Memory Read on page 4 7 ADSP 218x Instruction Set Reference 4 13 ALU MAC amp Shifter Instructions ALU MAC amp Shifter Instructions This group of instructions performs computations All of these instruc tions can be executed conditionally except the ALU division instructions and the Shifter SHIFT IMMEDIATE instructions ALU Group The following is an example of one ALU instruction Add Add with Carry IF AC AR AX0 AYO C The optional conditional expression IF AC tests the ALU Carry bit AC if there is a carry from the previous instruction this instruction exe cutes otherwise a NOP occurs and execution continues with the next instruction The algebraic expression AR AX0 AY0 C means that the ALU result register AR gets the value of the ALU X input and Y input registers plus the value of the carry in bit Table 4 3 gives a summary list of all ALU instructions In this list condi tion stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the ALU The conditional clause is optional
183. ta register bank select bit SEC_REG determines which set of data registers is currently active 0 primary 1 secondary The bit reverse mode bit BIT_REV when set to 1 causes addresses gener ated by Data Address Generator 1 to be output in bit reversed order The ALU overflow latch mode bit AV_LATCH when set to 1 causes the AV bit in the arithmetic status register to stay set once an ALU overflow occurs In this mode if an ALU overflow occurs the AV bit will be set and will remain set even if subsequent ALU operations do not generate over flows The AV bit can only be cleared by writing a zero into it directly over the DMD bus The AR saturation mode bit AR_SAT when set to 1 causes the AR register to saturate if an ALU operation causes an overflow as described in the ADSP 218x DSP Hardware Reference Manual Chapter 2 Computational Units The MAC result placement mode M_MODE determines whether or not the left shift is made between the multiplier product and the MR register 4 162 ADSP 218x Instruction Set Reference Setting the Timer Enable bit TIMER starts the timer decrementing logic Clearing it halts the timer The GO mode G_MODE allows an ADSP 218x processor to continue exe cuting instructions from internal memory if possible during a bus grant The G0 mode allows the processor to run only if an external memory access is required does the processor halt waiting for the bus to be released
184. te data value lt addr gt Denotes an immediate address value to be encoded in the instruc tion The lt addr gt may be either an immediate value a constant or a program label lt reg gt Refers to any accessible register see the table Processor Reg isters reg and dreg on page 4 22 ADSP 218x DSP Instruction Set Reference 1 9 Conventions Table 1 1 Instruction set notation Cont d Notation Meaning brackets Refers to optional instruction extensions lt dreg gt Refers to any data register see the table Processor Registers reg and dreg on page 4 22 Ox Denotes number in hexadecimal format OxFFFF h Denotes number in hexadecimal format h FFFF b Denotes number in binary format b 0001000100010001 Immediate values such as lt exp gt lt data gt or lt addr gt may be a constant in decimal hexadecimal octal or binary format The default format is decimal 1 10 ADSP 218x DSP Instruction Set Reference 2 PROGRAMMING MODEL Overview From a programming standpoint the ADSP 218x processors consist of three computational units ALU MAC and Shifter two data address generators and a program sequencer plus on chip peripherals and mem ory that vary with each processor Almost all operations using these architectural components require one or more registers to store data to keep track of values such as pointers or to specify operating modes
185. tended to the left if the source is a signed value or zero filled to the left if the source is an unsigned value The unsigned registers which when used as the source cause the value stored in the destination to be zero filled to the left are 10 through 17 LO through L7 CNTR PX ASTAT 4 116 ADSP 218x Instruction Set Reference MSTAT SSTAT IMASK and ICNTL All other registers cause sign extension to the left When transferring a larger register to a smaller register e g a 16 bit regis ter to a 14 bit register the value stored in the destination is right justified bit 0 maps to bit 0 and the higher order bits are dropped Note that whenever MR1 is loaded with data it is sign extended into MR2 STATUS GENERATED No status bits affected INSTRUCTION FORMAT Internal Data Move Instruction Type 17 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 0 0 O 0 JDST SRC DEST SOURCE RGP RGP REG REG To choose the source register group SRC RGP and the source register SOURCE REG refer to the table Register Selection Codes on page A 19 To choose the destination register group DST RGP and the destination register DEST REG refer to the table Register Selection Codes on page A 19 ADSP 218x Instruction Set Reference 4 117 Move Instructions Load Register Immediate SYNTAX reg lt data gt dreg lt data gt data lt constant gt
186. ter COND Condition Xop X operand register ADSP 218x Instruction Set Reference 4 85 MAC Instructions SEE ALSO IF Condition Codes Table 4 9 on page 4 25 Status Condition Codes on page A 12 ALU MAC Result Register Codes on page A 25 AMF Function Codes on page A 10 X Operand Codes on page A 24 Y Operand Codes on page A 24 4 86 ADSP 218x Instruction Set Reference Instruction Set Squaring SYNTAX LIF cond MR MR xop xop SS MF UU RND IF cond MR MR xop xop SS MF UU RND IF cond MR xop xop SS MF UU RND Permissible xops MX0 AR MX1 SR1 MR2 SRO MRI MRO ADSP 218x Instruction Set Reference 4 87 MAC Instructions EXAMPLES IF NOT MV MR MR MXO MXO SS XX instruction IF NOT MV MR MR MXO MXO SS BX instruction MR AR AR UU X instruction DESCRIPTION Test the optional condition and if true then square the xop add the present contents of the MR register or subtract the squared result from the MR register and store the result in the destination location If the condi tion is not true then perform a no operation Omitting the condition performs the multiply accumulate unconditionally The xop is contained in the data register specified in the instruction When MF is the destination operand only bits 31 16 of the 40 bit result are stored in MF RESTRICTIONS
187. the divisor with the MSB of the divi dend The 32 bit dividend is shifted left one bit and the inverted value of AQ is moved into the LSB Output Formats As in multiplication the format of a division result is based on the format of the input operands The division logic has been designed to work most efficiently with fully fractional numbers those most commonly used in fixed point DSP applications A signed fully fractional number uses one bit before the binary point as the sign with fifteen or thirty one in dou ble precision bits to the right for magnitude 4 68 ADSP 218x Instruction Set Reference Instruction Set If the dividend is in M N format M bits before the binary point N bits after and the divisor is O P format the quotient s format will be M O 1 N P 1 As you can see dividing a 1 31 number by a 1 15 number will produce a quotient whose format is 1 1 1 31 15 1 or 1 15 Before dividing two numbers you must ensure that the format of the quotient will be valid For example if you attempted to divide a 32 0 number by a 1 15 number the result would attempt to be in 32 1 1 0 15 1 or 32 16 format This cannot be represented in a 16 bit register In addition to proper output format you must ensure that a divide over flow does not occur Even if a division of two numbers produces a legal output format it is possible that the number will overflow and be unable to fit within the constraints of the o
188. tiplier result register MR gets the value of itself plus the product of the X and Y input registers selected The modifier in parentheses UU treats the operands as unsigned There can be only one such modifier selected from the available set The modi fier SS means both are signed while US and SU mean that either the first or second operand is signed RND means to round the implicitly signed result ADSP 218x Instruction Set Reference 4 17 ALU MAC amp Shifter Instructions Table 4 4 gives a summary list of all MAC instructions In this list condi tion stands for all the possible conditions that can be tested and xop and yop stand for the registers that can be specified as input for the MAC A complete list of the permissible xops and yops is given in the reference page for each instructions Table 4 4 MAC Instructions LIF cond MR MF LIF cond MR MF LIF cond MR MF LIF cond MR MF LIF cond MR MF IF MV SAT MR xop yop SS 3 xop SU US UU RND MR xop xop SU US UU yop SS MR xop yop SS ys xop SU US UU RND MR RND 4 18 ADSP 218x Instruction Set Reference Instruction Set Shifter Group Here is an example of one of the Shifter instruction Normalize IF NOT CE SR SR OR NORM SI CHI The conditional expression IF NOT CE tests the not counter expired condition If the condition is false a NOP is executed The
189. tools 1 3 Direction codes A 14 Disable DIS instruction 2 5 2 6 4 26 4 27 4 161 Interrupt Disable 4 164 Division Applications 4 70 Code example 4 70 Divide primitives DIVS and DIVQ 4 64 Exceptions 4 69 Integer 4 68 Negative divisor error 4 69 Routine using DIVS amp DIVQ 4 70 Signed 4 66 Theory 4 66 Unsigned 4 67 Unsigned division error 4 70 Divisor codes for slow idle instruction A 16 DMOVLAY Register Update Instruction 4 168 DO UNTIL instruction 2 6 4 5 4 149 DO UNTIL termination codes A 22 E Enable ENA instruction 2 5 2 6 4 26 4 27 4 161 4 164 Interrupt Enable 4 164 Examples Bit reverse subroutine 3 21 I 2 ADSP 218x DSP Instruction Set Reference DMOVLAY register restoration 2 20 UR filter 3 8 PMOVLAY register restoration 2 19 Radix 2 decimation in time FFT 3 14 Sine approximation 3 10 Single precision FIR transversal filter 3 6 Single precision matrix multiply 3 12 F FI condition codes A 16 FI pin 4 23 4 25 4 141 FIR transversal filter example 3 6 FO control codes for flag output pins A 16 FO pin 4 26 4 143 G Generate ALU status 4 72 A 3 H Hardware overlays 2 17 I IDLE instruction 2 14 2 15 4 6 4 23 4 153 IF Condition codes table 4 25 IIR filter 3 8 INDEX Increment 4 60 Index I register 2 1 2 4 2 14 4 6 4 8 4 26 4 123 4 127 4 130 4 171 4 175 4 186 4 190 Index register codes A 17 Indirect addressing 2 4 Indirect jumps 2 4 Inplaceimag d
190. truction more closely Regardless of the apparent logic of reading the instruction from left to right the read first write second operation of the processor determines what actually happens Using the same register as a destination in both clauses however produces an indeterminate result and should not be done The assembler issues a warning unless semantics checking is turned off Regardless of whether or not the warning is produced however this practice is not supported ADSP 218x Instruction Set Reference 4 181 Multifunction Instructions The following therefore is illegal and not supported even though assem bler semantics checking produces only a warning 3 AR AXO AYO AR MR1 IT legal STATUS GENERATED See Table 4 11 on page 4 31 for register notation All status bits are affected in the same way as for the single function ver sions of the selected arithmetic operation lt ALU gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ 3 x x x x x AZ Set if result equals zero Cleared otherwise AN Set if result is negative Cleared otherwise AV Set if an overflow is generated Cleared otherwise AC Set if a carry is generated Cleared otherwise AS Affected only when executing the Absolute Value operation ABS Set if the source operand is negative 4 182 ADSP 218x Instruction Set Reference lt MAC gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ MV Set if th
191. ts after Saturation of MR2 0 0 No change 0 1 No change 1 0 00000000 0111111111111111 1111111111111111 1 1 11111111 1000000000000000 0000000000000000 STATUS GENERATED No status bits affected 4 96 ADSP 218x Instruction Set Reference Instruction Set INSTRUCTION FORMAT Saturate MR operation Instruction Type 25 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADSP 218x Instruction Set Reference 4 97 MAC Instructions 4 98 ADSP 218x Instruction Set Reference Shifter Instructions Arithmetic Shift SYNTAX IF cond SR SR OR ASHIFT dba i LO Permissible xops Permissible conds SI AR EQ LE AC SRI MR2 NE NEG NOT AC SRO MRI GT POS MV MRO GE AV NOT MV LT NOT AV NOT CE EXAMPLES Conditional arithmetic shift IF LT SR SR OR ASHIFT SI LO Shift the content of SR arithmetically right by SE SE 2 SR ASHIFT SRI HI SI SRO SR SR OR LSHIFT SI LO DESCRIPTION Test the optional condition and if true then perform the designated arithmetic shift If the condition is not true then perform a no operation Omitting the condition performs the shift unconditionally The operation arithmetically shifts the bits of the operand by the amount and direction ADSP 218x Instruction Set Reference 4 97 Shifter Instructions specified in the shift code from the SE register Positive shift codes c
192. uced clock fre quency a programmable fraction of the normal clock rate is specified by a selectable divisor 7 given in the instruction 7 16 32 64 or 128 The instruction leaves the processor fully functional but operating at the slower rate during execution of the IDLE n instruction While it is in this state the processor s other internal clock signals such as SCLK CLK OUT and the timer clock are reduced by the same ratio When the IDLE n instruction is used it slows the processor s internal clock and thus its response time to incoming interrupts the 1 cycle response time of the standard IDLE state is increased by the clock divi sor When an enabled interrupt is received the ADSP 218x will remain in the IDLE state for up to a maximum of 7 CLKIN cycles where 7 16 32 64 or 128 before resuming normal operation When the IDLE n instruction is used in systems that have an externally generated serial clock the serial clock rate may be faster than the proces sor s reduced internal clock rate Under these conditions interrupts must ADSP 218x Instruction Set Reference 4 153 Program Flow Instructions not be generated at a faster rate than can be serviced due to the additional time the processor takes to come out of the IDLE state a maximum of 7 CLKIN cycles Serial port autobuffering continues during IDLE without affecting the idle state STATUS GENERATED No status bits affected INSTRUCTION FOR
193. ultiplication operands xop and yop or xop and xop are considered to be in twos complement format Rounding can be either biased or unbiased For a discussion of biased vs unbiased rounding see the section Rounding Mode in the ADSP 218x DSP Hardware Reference Manual Chapter 2 Computational Units 4 76 ADSP 218x Instruction Set Reference Instruction Set STATUS GENERATED See Table 4 11 on page 4 31 for register notation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ _ _ _ _ _ MV Set on MAC overflow if any of the upper 9 bits of MR are not all one or zero Cleared otherwise INSTRUCTION FORMAT xop yop Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 10 0 0 1 0 0 Z AMF Yop Xop 0 0 0 0 COND AMF specifies the ALU or MAC operation in this case AMF FUNCTION Data Format X Operand Y Operand 00100 xop xop SS Signed Signed 00101 xop yop SU Signed Unsigned 00110 xop yop US Unsigned Signed 00111 xop yop UU Unsigned Unsigned 00001 xop yop RND Signed Signed 2 Destination register Yop Y operand Xop X operand COND Condition ADSP 218x Instruction Set Reference 4 77 MAC Instructions xop xop Conditional ALU MAC operation Instruction Type 9 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 0 1 0 0
194. us Register Notation Notation Meaning An asterisk indicates a bit in the status word that is changed by the execution of the instruction A dash indicates that a bit is not affected by the instruction 0 or 1 Indicates that a bit is unconditionally cleared or set For example the status word ASTAT is shown below ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ 0 2 Here the MV bit is updated and the AV bit is cleared ADSP 218x Instruction Set Reference 4 31 ALU Instructions ALU Instructions Add Add with Carry SYNTAX IF cond JAR xop yop AF PoE yop C constant constant C Permissible xops Permissible yops Permissible conds AXO MR2 AYO EQ LE AC AXI MRI AY1 NE NEG NOT AC AR MRO AF GT POS MV SRI GE AV NOT MV SRO LT NOT AV NOTCE Permissible constants 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32767 2 3 5 9 17 33 65 129 257 513 1025 2049 4097 8193 16385 32768 EXAMPLE Conditional ADD with carry IF EQ AR AXO AYO C Unconditional ADD AR AR 512 4 32 ADSP 218x Instruction Set Reference Instruction Set ADD a negative constant AR AXO 129 32 Bit Addition DIS AR_SAT AR AXO AYO AR AX1 AY1 C AX1 AR DESCRIPTION AR AXO 129 AX1 AX0 AX1 AX0 AYI AVO If not already disabled Add
195. ution to con tinue at the address specified by the instruction The addressing mode for the CALL on FI must be direct If JUMP or CALL is the last instruction inside a DO UNTIL loop you must ensure that the loop stacks are properly handled For direct addressing using an immediate address value or a label the program address is stored directly in the instruction word as a full 14 bit field ADSP 218x Instruction Set Reference 4 141 Program Flow Instructions STATUS GENERATED No status bits affected INSTRUCTION FORMAT Conditional JUMP or CALL on Flag In Direct Instruction Type 27 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 0 0 0 0 0 0 1 1 Address Addr AC 12 LSBs 2 MSB s SE Specifies JUMP 0 or CALL 1 FIC Latched state of FI pin SEE ALSO Jump and Call Codes on page A 20 FI Condition Codes on page A 16 4 142 ADSP 218x Instruction Set Reference Modify Flag Out Pin SYNTAX IF cond SET FLAG_OUT Esa ds RESET FLO TOGGLE FL1 FL2 EXAMPLE IF MV SET FLAG OUT RESET FL1 DESCRIPTION Evaluate the optional condition and if true set to one reset to zero or toggle the state of the specified flag output pin s Otherwise perform a no operation and continue with the next instruction Omitting the condi tion performs the operation unconditionally Multiple flags may be modified by including multiple clauses separated by commas in
196. utput For example if you wished to divide a 16 16 number by a 1 15 number the output format would be 16 1 1 16 15 1 or 16 0 which is legal Now assume you happened to have 16384 0x4000 as the dividend and 25 0x2000 as the divisor the quotient would be 65536 which does not fit in 16 0 format This opera tion would overflow producing an erroneous result Input operands can be checked before division to ensure that an overflow will not result If the magnitude of the upper 16 bits of the dividend is larger than the magnitude of the divisor an overflow will result Integer Division One special case of division that deserves special mention is integer divi sion There may be some cases where you wish to divide two integers and produce an integer result It can be seen that an integer integer division will produce an invalid output format of 32 16 1 0 0 1 or 17 1 To generate an integer quotient you must shift the dividend to the left one bit placing it in 31 1 format The output format for this division will ADSP 218x Instruction Set Reference 4 69 ALU Instructions be 31 16 1 1 0 1 or 16 0 You must ensure that no significant bits are lost during the left shift or an invalid result will be generated Division Exceptions Although the divide primitives for the ADSP 218x family work correctly in most instances there are two cases where an invalid or inaccurate result can be generated The first case involve
197. vides flexible system definition through Linker Description Files LDF In a single LDF you can define different types of executables for a single or multiprocessor system The Linker resolves symbols over multiple executables maximizes memory use and easily shares common code among multiple processors The Loader sup ports creation of a 16 bit host port and 8 bit PROM boot images Along with the Linker the Loader allows a variety of system configurations with smaller code and faster boot time Simulator The Simulator is a cycle accurate instruction level simulator that allows you to simulate your application in real time Emulator The EZ ICE serial emulator system provides state of the art emulation for the ADSP 218x family of DSPs using a controlled environ ment for observing debugging and testing activities in a target system The key features of the ADSP 218x EZ ICE include a shielded enclosure with the reset switch a high speed RS 232 serial port interface and sup port for 2 5 3 3 and 5 0V DSPs The EZ ICE connects directly to the target processor via the emulation interface port It s ease of use full ADSP 218x DSP Instruction Set Reference 1 5 For More Information About Analog Products speed emulation and shield board will ensure that your design process runs smoothly 3rd Party Extensible The VisualDSP environment enables third party companies to add value using Analog Devices published set of Applica t
198. werful Here is an example of one instruction IF EQ JUMP my_label JUMP of course is a familiar construct from many other languages My_label is any identifier you wish to use as a label for the destination jumped to Instead of the label an index register in DAG2 may be explic itly used The default scope for any label is the source code module in which it is declared The assembler directive ENTRY makes a label visible as an entry point for routines outside the module Conversely the EXTERNAL directive makes it possible to use a label declared in another module If the counter condition DO UNTIL CE IF NOT CE is to be used an assign ment to CNTR must be executed to initialize the counter value JUMP and CALL permit the additional conditionals FLAG_IN and NOT FLAG_IN to be used for branching on the state of the FI pin but only with direct address ing not with DAG as the address source RTS and RTI provide for conditional return from CALL or interrupt vectors respectively The IDLE instruction provides a way to wait for interrupts IDLE causes the processor to wait in a low power state until an interrupt occurs When an interrupt is serviced control returns to the instruction following the IDLE statement IDLE uses less power than loops created with NOPs ADSP 218x Instruction Set Reference 4 23 Program Flow Control Table 4 8 gives a summary of all program flow control instructions The condition codes are described i
199. when executing the Absolute Value operation ABS Set if the source operand is negative lt MAC gt operation ASTAT 7 6 5 4 3 2 1 0 SS MV AQ AS AC AV AN AZ MV Set if the accumulated product overflows the lower order 32 bits of the MR register Cleared otherwise 4 194 ADSP 218x Instruction Set Reference INSTRUCTION FORMAT ALU MAC with Data and Program Memory Read Instruction Type 1 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 1 JO 1 1 PD IDD AMF Yop Xop PM PM DM DM I M I M PD AMF Yop SEE ALSO Program Destination register DD Data Destination register ALU MAC operation M Modify register Y operand Xop X operand Indirect address register Program Memory Destination Codes on page A 18 Data Memory Destination Codes on page A 14 Index Register Selection Codes on page A 17 Modify Register Selection Codes on page A 18 X Operand Codes on page A 24 Y Operand Codes on page A 24 AMF Function Codes on page A 10 ADSP 218x Instruction Set Reference 4 195 Multifunction Instructions 4 196 ADSP 218x Instruction Set Reference A INSTRUCTION CODING Overview This appendix gives a summary of the complete instruction set of the ADSP 218x family processors This section is divided into two sections e Opcode Definitions on page A 2 This section provides the opcode bits liste
200. with Program Memory Read Write A 2 Type 6 Load Data Register Immediate A 2 Type 7 Load Non Data Register Immediate A 3 Type 8 ALU MAC with Internal Data ADSP 218x DSP Instruction Set Reference I 7 Register Move A 3 Type 9 Conditional ALU MAC A 3 U Unsigned division 4 67 W Wait states 4 28 X X X Operand codes A 24 Y Y Y Operand codes A 24 YY CC BO ALU MAC constant codes A 25 Z Z ALU MAC Result register codes A 25 I 8 ADSP 218x DSP Instruction Set Reference

ADSP-218x DSP Instruction Set Reference

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