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1. 15 6 UART Functional Block 15 8 Timing Diagram for UART Mode 0 Operation ener 15 9 Timing Diagram for UART Mode 1 Operation I nnne 15 10 Timing Diagram for UART Mode 2 Operation I enne 15 12 Connection Example for Multiprocessor Serial Data Communications 15 14 A D Converter Control Register ADCONJ sassa 16 2 A D Converter Data Register ADDATAH ADDATAL a nennen 16 3 A D Converter Circuit Diagram entente nennen intres tnnt 16 3 A D Converter Timing 1 16 4 Recommended A D Converter Circuit for Highest Absolute Accuracy 16 5 Watch Timer Circuit 17 3 LCD Function BICI rc 18 1 LCD Circ lt Diagram ated 18 2 LCD Display Data RAM Organization rennen 18 3 LCD Mode Control Register U U 18 4 LCD Port Gontrol Register L u ie ee ede lee i niet ee 18 5 Internal Voltage Dividing Resistor Connection 18 6 LCD Signal Waveforms 1 8 Duty 1 4 Bias U enne 18 7 LCD Signal Waveforms 1 4 Duty 1 3 Bias U
2. 2 18 Figure 2 15 4 bit Working Register Addressing 2 18 Figure 2 16 8 bit Working Register 00 2 19 Figure 2 17 8 Working Register Addressing 2 20 Fig re 2 18 Stack Operations ertet e pet er ested co edi Ee do enu E o dh aeter ieu sasa 2 21 Figure 3 1 Register Addressing eee 3 2 Figure 3 2 Working Register 00 0 3 2 Figure 3 83 Indirect Register Addressing to Register 3 3 Figure 3 4 Indirect Register Addressing to Program 3 4 Figure 3 5 Indirect Working Register Addressing to Register 3 5 Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 Figure 3 7 Indexed Addressing to Register File 1 U U 3 7 Figure 3 8 Indexed Addressing to Program Data Memory with Short Offset 3 8 Figure 3 9 Indexed Addressing to Program or Data 3 9 Figure 3 10 Direct Addressing for Load 3 10 Figure 3 11 Direct Addressing for Call and Jump Instructions 3 11 Figure 3 12 Indirect Addressing erii
3. eiaa 3 12 Figure 3 13 Relative 0 U U uu u 3 13 SAMSUNG ELECTRONICS Figure 3 14 Figure 4 1 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 6 1 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 Figure 9 11 Figure 9 12 Figure 10 1 Figure 10 2 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 Figure 11 6 Figure 12 1 Figure 12 2 Figure 12 3 Figure 13 1 Figure 13 2 Figure 13 3 Immediate Addressing Nan 3 14 Register Description AA tenerent nnn nenas 4 4 S3C8 Series Interrupt Types 5 3 S3C8418X F8418X C84I9X F84l9XInterrupt Structure 5 5 ROM Vector Address Area 1 5 6 Interrupt Function Diagram 5 9 System Mode Register SYM 5 11 Interrupt Mask Register IMR uuu Ea 5 12 Interrupt Request Priority Groups n
4. 15 1 15 1 1 Programming Procedure n 15 1 15 1 2 UART Control Register UARTCONJ U L 15 2 15 1 3 UART Interrupt Pending Register 15 4 15 1 4 UART Data Register 2 tena 15 6 15 1 5 UART Baud Rate Data Register BRDATAH BRDATAL sss 15 6 15 1 6 Baud Rate Calculations 15 7 15 2 SOCKS uuu u uuu uu usu uter 15 8 15 2 1 UART Mode 0 Function Deseriptignh u LLL 15 9 15 2 2 UART Mode 1 Function Description U 15 10 15 2 3 UART Mode 2 Function DesoripBtioen uuu u u uuu 15 11 15 2 4 Serial Communication for Multiprocessor Configurations sene 15 13 16 A D CONVERTER get E 16 1 16 T OVO M UE 16 1 16 2 FUNCTION Descriptio gresss rere niente nied 16 1 16 2 1 A D Converter Control Register ADCONJ n nanan 16 2 16 2 2 Internal Reference Voltage Levels U U 16 4 16 2 9 Conversion timing u G u aa ra estan eeu xen 16 4 16 2 4 Internal A D Conversion Procedure
5. dedo 8 6 8 2 2 1016 8 7 9 VO PORTS U 9 1 meus 9 1 9 2 Port Data B6glsters 9 2 9 2 T 9 3 9 2 2 PO 9 5 9 2 9 9 9 2 4 9 14 9 25 UT 9 17 jgzlexi 10 1 Tu c kun 10 1 10 1 Timer BP uuu nee Uie 10 1 10 1 2 Basic Timer Control Register BTCON I nennen nnns nennen 10 1 10 2 Basic Timer Function 10 3 10 2 1 Watchdog Timer Fufidlieli Dur texta ere eterne re veter evene vea erect peus 10 3 10 2 2 Oscillation Stabilization Interval Timer Function 10 3 11 8 BIT 11 1 11 1 8 BIL EIN n 11 1 S MESI UI a qaquy 11 1 11 12 Function DescriptiOl eiae erede erret 11 2 11 1 3 Timer Control Register
6. 23 9 23 1 7 In Circuit Emulator for SAM8 Family U l n n 23 9 23 1 8 OTP MTP Progralniiaer U sitet einn aqasha 23 9 23 1 9 Development Tools Suppliers eene enne ennt enn snnt nnns 23 9 23 1 10 8 58 23 9 23 1 11 OTP MTP Programmer Writer nennen nnns nennen 23 10 SAMSUNG ELECTRONICS ex List of Figures Figure Title Page Number Number Figure 1 1 S3C8418 F8418 C8419 F8419 Block Diagram eese mene 1 6 Figure 1 2 S8C8418X F8418X C84I9X F8419X Pin Assignment 44 pin 1 7 Figure 1 3 S8C8419X F8419X Pin Assignment 42 pin SDIP L a 1 8 Figure 1 4 Pin Circuit Type B nRESET l 1 11 Figure 1 5 Circuit Quid 1 11 Figure 1 6 Pin Circuit Type Diss ccc aku eiae note tC anes Fo IE Sora 1 12 Figure 1 7 Pin Circuit Type D 5 P1 0 P1 3 enne 1 12 Figure 1 8 Pin Circuit Type E P2 2 P2 3 enr sens 1 13 Figure 1 9 Pin Circuit Type H 4 __ u u rai doen estu 1 14 Figure 1 10 Pin Circuit Type H 14 P4 4 P4 7
7. 2 7 Setting the Register Pointers entente nennen trn 2 12 Using the RPs to Calculate the Sum of a Series of 2 13 Addressing the Common Working Register Area sse 2 17 Standard Stack Operations Using PUSH and POP sse 2 22 To make PO as Normal I O or Alternative function 9 4 To make P2 as Normal I O or Alternative function sssssssseeeeennrene 9 13 To make as Normal I O or Alternative function 9 16 To make as Normal I O or Alternative function 9 19 To generate 38 kHz 1 signal through 11 9 To generate a pulse signal through 2 0 sese ene 11 10 Usmg ihe c 11 11 Usmo TNS Timer Brrr 11 12 Using the Timer 0 E 12 8 Programming the PWM Module to Sample 13 7 Sem 14 6 Configuring A D 16 6 Using the Watch 17 4 Sector Erase Not to Use an Interrupt sse enne nennen 20 7 Sector Erase To Use an 1 0
8. 4 24 4 1 24 P2PUR Port 2 Pull up Resistor Control Register FAH Set 1 Bank0 4 25 4 1 25 Port Control Register High Byte EEH Set 1 4 26 4 1 26 Port Control Register Low Byte EFH Set 1 4 27 4 1 27 PACONH Port 4 Control Register High Byte Set 1 4 28 4 1 28 PACONL Port 4 Control Register Low Byte F1H Set 1 Banko 4 29 4 1 29 PP Register Page Pointer DFH Set 1 U nnns 4 30 4 1 30 PN MCON PWM Control Register F5H Set 1 1 4 31 4 1 31 RPO Register Pointer 0 D6H 1 4 32 4 1 32 Register Pointer 1 D7H 4 32 4 1 33 SIOCON Serial Module Control Registers F2H Set 1 Bank1 FOFFFFFFF 4 33 4 1 34 SIOPS SIO Prescaler Register Set 1 1 4 34 4 1 35 SPH Stack Pointer High Byte D8H Set 1 4 34 4 1 36 SPL Stack Pointer Low Byte Set 1 L 4 34 4 1 37 STOPCON Stop Control Register E5H Set 1 Bank0 4 35 4 1 38 SYM System Mode Register DEH Set 1 4 36 4 1 39 T
9. I nennen nnne nennen 16 5 17 WATCH TIMER H 17 1 Em 17 1 17 1 1 Watch Timer Control Register WTCON 17 2 17 1 2 Watch Timer Circuit Diagram n 17 3 18 LCD CONTROLLER DRIVER 18 1 QNO ER 18 1 LOD Circuit TIMIDI 18 2 18 1 2 LCD RAM Address Area ener entente 18 3 18 1 3 LCD Mode Control Register LMOD sesenta 18 4 18 1 4 LCD Port Control Register enne nennen 18 5 18 1 5 LCD Voltage Dividing Resistors U Q nnne nennen 18 6 18 1 6 Common COM Signals UU u usa auqa eene nennen 18 6 1831 7 Segment SEG Signals pe a erui eta eee 18 6 19 LOW VOLTAGE RESET T 19 1 19 19 1 SAMSUNG ELECTRONICS ex 20 EMBEDDED FLASH MEMORY INTERFACE 20 1 20 1 OVeIVIeW RE 20 1 20
10. 9 14 Port Low Byte Control Register 9 15 Port 4 High Byte Control Register 9 17 Port 4 Low Byte Control Register P4CONL a s 9 18 Basic Timer Control Register BTCONJ U L n u 10 2 Basic Timer Block Diagrai 10 4 Timer A Control Register TACON sse enne enne nennen sinn intrent 11 3 Timer A Functional Block Diagram U nennen nnne 11 4 Timer B Functional Block 11 5 Timer B Control Register 11 6 Timer Data Registers TBDATAH 11 6 Timer B Output Flip Flop Waveforms in Repeat 11 8 Timer 1 0 1 Control Register T1 CONO 12 5 Timer A Timer 1 0 1 Pending Register TINTPND u 12 6 Timer 1 0 1 Functional Block Diagram uu 12 7 10 Bit PWM Basic Waveform nnns nennen inen nnne nnne 13 3 10 Bit Extended PWM U nennen entren 13 4 PWM Control Register neret nennen 13 5 SAMSUNG ELECTRONICS ex Figure 13 4 Figure 14 1 Figure 14 2 Figure 14 3 Figu
11. Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034H 0C5H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 H OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H NOTE LDEI instruction can be used to read write the data of 64 Kbyte data memory SAMSUNG ELECTRONICS 6 54 e 53 8419 00 6 Instruction Set 6 6 40 LDCPD LDEPD Load Memory with Pre Decrement These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory LDCPD dst src LDEPD dst src Operation rr rr 1 dst lt src Flags No flags are affected Format src dst Examples LDCPD RR6 RO LDEPD RR6 RO Bytes Cycles Opcode Addr Mode Hex dst src 2 14 F2 I
12. a 4 10 4 1 9 IMR Interrupt Mask Register DDH Set 1 4 11 4 1 10 IPH Instruction Pointer High Byte 1 4 12 4 1 11 IPL Instruction Pointer Low Byte DBH Set 1 4 12 4 1 12 IPR Interrupt Priority Register Set 1 0 4 13 4 1 13 IRQ Interrupt Request Register DCH Set 1 nens 4 14 4 1 14 LMOD LCD Mode Control Register F6H Set 1 1 sse 4 15 4 1 15 LCD Port Control Register F7H Set 1 Bank1 4 16 4 1 16 OSCCON Oscillator Control Register F2H Set 1 4 17 4 1 17 POCON Port 0 Control Register High Byte E6H Set 1 4 18 4 1 18 P1CONH Port 1 Control Register High Byte E8H Set 1 4 19 4 1 19 P1CONL Port 1 Control Register Low Byte E9H Set 1 4 20 4 1 20 P1INTPND Port 1 Interrupt Pending Register EAH Set 1 Bank0 i tiet 4 21 4 1 21 P1INT Port 1 Interrupt Enable EBH Set 1 0 4 22 4 1 22 P2CONH Port 2 Control Register High Byte Set 1 4 23 4 1 23 P2CONL Port 2 Control Register Low Byte EDH Set 1
13. gt Max _ __ 3 7 Vpp Vss 033 5 8 gt Conversion time is the time required from the moment a conversion operation starts until it ends 2 lapc is operating current during A D conversion 3 fosc is the main oscillator clock 4 AVref must be tied to Vdd SAMSUNG ELECTRONICS ex 32 ELECTRICAL DATA PAGE 21 14 VDD Vss Test Reset S3C8418X F8418X C8419X F8419X Figure 21 9 The Circuit Diagram to Improve EFT Characteristics NOTE To improve EFT characteristics we recommend using capacitor between Vdd and Vss Test and Vss Reset and Vss closely from S3C8418X F8418X C8419X F8419X And you d better also put External crystal closely from S3C8418X F8418X C8419X F8419X SAMSUNG ELECTRONICS eux 33 cHAPTER 23 overview Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator OPENice i500 and SK 1200 for the 3 7 53 9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options Target Boards Target boards are available for all the
14. nnns tnnt n sitne 11 3 11 14 Block Diagram 11 4 11 2 8 11 5 DEA EOU CUI 11 5 11 22 Block Biagram tei tone tette emeret eh 11 5 11 2 3 Timer B Control Register TBCONJ I n rente snnt entere 11 6 11 2 4 Timer b PULSE WIDTH CALCULATIONS sse enne nnns inneren sinn intrent 11 7 12 16 BIT TIMER 1 0 1 u 12 1 12 1 12 11 F nctiom descriptiOTi 1e croire etico estes PER 12 2 12 1 2 Timer 1 0 1 control register t1conO t1con1 uuu nens 12 4 12 13 Block Diagram m 12 7 13 10 PWM PULSE WIDTH MODULATION 13 1 432 OVelVISW C 13 1 13 2 FUNCTION COSCHIPTIOMN eL 13 1 SABE 13 1 13 2 2 PWM Control Register inneren 13 5 SAMSUNG ELECTRONICS ex 14 SERIAL INTERFACE cdi 14 1 INEO 14 1 14 11 Programming Procedure 14 1 14 1 2 SIO Control Registers 1 enne nnne 14 2 14 1 3 SIO Prescaler Register SIOPS 14 3 UART NUR 15 1 M
15. enne 20 7 u u Qua 20 9 REACING kssqa 20 12 Hard Lock 20 13 List of Conventions Register RW Access Type Conventions Type Definition Description R Read Only The application has permission to read the Register field Writes to read only fields have no effect W Write Only The application has permission to write in the Register field RW Read amp Write The application has permission to read and writes in the Register field The application sets this field by writing 1 b1 and clears it by writing 1 bO Register Value Conventions Expression Description x Undefined bit X Undefined multiple bits Undefined but depends on the device or pin status Device dependent The value depends on the device Pin value The value depends on the pin status Reset Value Conventions Expression Description 0 Clears the register field 1 Sets the register field x Don t care condition Warning Some bits of control registers are driven by hardware or write operation only As a result the indicated reset value and the read value after reset might be different SAMSUNG ELECTRONICS ex 53 8419 UM REV3 00 1 Product Overview Product Overview 1 1 S3C8 Series Microcontrollers Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers off
16. 1 15 Figure 1 11 Pin Circuit Type H 16 PO 0 PO 3 l senten terrens tnis 1 15 Figure 1 12 Pin Circuit Type H 17 P3 0 P3 7 P4 0 P4 1 16 Figure 1 13 Pin Circuit Type H 18 2 4 P2 7 terret sensn nennen ns 1 16 Figure 2 1 Program Memory Address Space U 2 2 Fig re 2 2 Sman Opto EE 2 3 Figure 2 3 Internal Register File Organization of 5328419 8419 sse 2 5 Figure 2 4 Internal Register File Organization of 5 84 8 22 2 6 Figure 2 5 Register Page Pointer u 2 7 Figure 2 6 Set 1 Set 2 Prime Area Register 53 8419 8419 sse 2 9 Figure 2 7 Set 1 Set 2 Prime Area Register 53 8418 4 8 2 10 Figure 2 8 8 byte Working Register Areas Slices sssssssssssss eee 2 11 Figure 2 9 Contiguous 16 byte Working Register Block L 2 12 Figure 2 10 Non Contiguous 16 byte Working Register 2 13 Figure 2 11 16 Bit Register 2 14 Figure 2 12 Register File Addressing I U U 2 15 Figure 2 13 Common Working Register Area n n n nennen nnns trenes 2 16 Figure 2 14 4 bit Working Register Addressing
17. Hex dst src 88116 0 src 3 6 27 r0 Rb opc src b 1 dst 3 6 27 Rb ro NOTE In the second byte of the 3 byte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H 00000111B and register 01H 03H 0000001 1B BXOR R1 01H 1 gt 1 06H register 01H 03H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example the destination working register R1 has the value 07H 00000111B and the source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of the register 01H the source with bit zero of R1 the destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of the source register 01H is unaffected SAMSUNG ELECTRONICS 6 24 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 13 CALL Call Procedure CALL Operation Flags Format Examples dst SP lt SP 1 SP lt PCL SP lt SP 1 QSP lt PCH PC lt dst The contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instructio
18. 18 8 LCD Signal Waveforms 1 3 Duty 1 3 18 9 Low Voltage Reset Circuit Do ades e de 19 2 Flash Memory Control Register 2 20 3 Flash Memory User Programming Enable Register 20 4 Sectors in User Program Mode 20 5 Flash Memory Sector Address Register FMSECH sse 20 6 Flash Memory Sector Address Register FMSECL 20 6 Input Timing for External Interrupts Ports 2 1 u uu 21 5 Input Timing for nRESET rete peace trente 21 5 Clock Timing Measurement at XIN cease nennen rennen inttr 21 7 Stop Mode Release Timing initiated by 21 8 Stop Mode Main Release Timing Initiated by 21 9 Stop Mode Sub Release Timing Initiated by 21 9 Waveform for UART Timing Characteristics L a 21 10 Operating Voltage Range 21 12 Figure 21 9 Figure 22 1 Figure 22 2 Figure 23 1 Figure 23 2 Figure 23 3 Figure 23 4 Figure 23 5 Figure 23 6 The Circuit Diagram to
19. 2 2 5 55 V Max 2 BE VDD k e 2 gt gt 2 1 is operating current during A D conversion 3 fOSC is the main oscillator clock 4 AVref must be tied to Vdd SAMSUNG ELECTRONICS 21 11 a 53 8419 UM REV3 00 21 Electrical Data Table 21 12 LVR Low Voltage Reset Circuit Characteristics TA 25 C Paameer Sumo Test Gonaition win Typ Max uni Main Oscillator Frequency CPU Clock 10 MHz Supply Voltage V Minimum instruction clock 1 4 Oscillator clock Figure 21 8 Operating Voltage Range Vss Test Reset S3C8418X F8418X 8419 8419 Figure 21 9 Circuit Diagram to Improve EFT Characteristics NOTE To improve EFT characteristics we recommend using capacitor between Vdd and Vss Test and Vss Reset and Vss closely from S3C8418X F8418X C8419X F8419X And you d better also put External crystal closely from S3C8418X F8418X C8419X F8419X SAMSUNG ELECTRONICS 21 12 Lm 53 8419 UM REV3 00 21 Electrical Data Table 21 13 AC Electrical Characteristics for Internal Flash ROM TA 25 to 85 C Flash Erase Write Read Voltage VDD Programming Time 1 Ftp Sector Erasing Time 2 Ftp1 Chip Erasing Time 9 C Fe Times ree L rss NOTE 1 The program times is the time during which one byte 8 bit is programmed 2 The Sector erasing time is the t
20. 85 2 5 V to 5 5 V Um OSC gt 400 kHz SF e Oscillation stabilization occurs when VDD is Main Ceramic equal to the minimum oscillator voltage range External Clock Main System XIN input High and Low width tXH tXL Oscillator WAIT when released by a reset 1 EN 216105 Stabilization Wait Time when released by an interrupt 2 Een NOTE 1 fOSCisthe oscillator frequency 2 The duration of the oscillator stabilization wait time tWAIT when it is released by an interrupt is determined by the settings in the basic timer control register BTCON SAMSUNG ELECTRONICS 21 6 x_n 53 8419 UM REV3 00 21 Electrical Data 4 tosc _ gt Vpp 0 5 V 0 4 V Figure 24 3 Clock Timing Measurement at XIN Table 21 7 Sub Oscillator Frequency fOSC2 25 C 85 C VDD 2 5 to 5 5 V Glock Cireut Test Gonaition Min Max Uni XT IN XT OUT Crystal oscillation frequency R C1 100 pF C2 100 pF 3309 32 32 768 34 kH esta 1 XTIN and XTOUT are E pi pi connected with R and C by soldering Table 21 8 Subsystem Oscillator crystal Stabilization Time tST2 25 C NOTE Oscillation stabilization time tST2 is the time required for the oscillator to it s normal oscillation when stop mode is re
21. Call cette 6 25 6 6 14 CCF Complement Carry Flag n nnns 6 26 6 6 15 Cleat ioi cornetto re tecta Vain Fe xat 6 27 6 6 16 COM Complement U L 6 28 5 6 17 COMP ANG uu M 6 29 6 6 18 CPIJE Compare Increment and Jump on 6 30 6 6 19 CPIJNE Compare Increment and Jump on Non Equal sse 6 31 6 6 20 DA Decimal 02044 1 0 1 1 nennen enne nn 6 32 6 6 21 DEC Decree Mtemi iniiai aaa ES 6 34 6 6 22 DECW Decrement Word I ener An enses nennen ns 6 35 6 6 23 DI Disable Interrupts ett teet Certe Cue eet 6 36 6 6 24 DIV Divide 6 37 6 6 25 DJNZ Decrement and Jump if 7 6 38 06 6 26 El Enable Interr pts rte ee ep nes 6 39 6 6 27 ENTER Enteru uu u uka tme 6 40 6 6 28 M M 6 41 6 6 29 IDLE Idle etti esee e neret rb Dude unt ane 6 42 SAMSUNG ELECTRONICS ex
22. Pharm Memor 8 Kbyte Flash ROM for SSF8418X 8 Kbyte Mask ROM for 3 8418 9 32 Kbyte Flash ROM for S3F84I9X 32 Kbyte Mask ROM for 53 8419 2 5 V to 5 5 V LVR off 2 5 V to 5 5 V LVR off Operating Voltages VOD LVR to 5 5 V LVR on LVR to 5 5 V LVR on VDD 5 V VPP 12 5 V S3F84I8X VPP 57 S3F8419X ws Pin Configuration 44QFP 42SDIP EPROM Programmability User Program multi time Programmed at the factory 20 1 2 User Program Mode This mode supports sector erase and one protection modes The 53 8419 has the pumping circuit internally therefore 12 5 V into Vpp Test pin is not needed To program a flash memory in this mode several control registers will be used There are four kind functions programming reading sector erase hard lock protection SAMSUNG ELECTRONICS 20 2 ea 53 8419 UM REV3 00 20 Embedded Flash Memory Interface 20 2 Flash Memory Control Registers 20 2 1 Flash Memory Control Register FMCON register is available only in user program mode to program some data to the flash memory Flash Memory Control Register FMCON FCH Set1 Bank1 R W Flash Memory Mode Selection Bits Flash Operation Start Bit 0101 Programming mode 0 Operation stop 1010 Erase mode 1 Operation start 0110 Hard lock mode This bit will be cleared automatically others Not used for 5328419 just after the corresponding operation completed Sector Erase Fail Flag 0 Sector Erase
23. PACONH 240 Fon o o o o o Port 4 control register low byte _ 241 o 0 0 Oscillator control register OSCCON 2H EAES3ESESES3ESESEN Location FBH is not mapped UART pending register UARTPND UART data register UDATA UART control register UARTCON A D converter control register F7H A D converter data register high byte F8H A D converter data register low byte ADDATAL 249 FH 0 Port 2 pull up enable control register P2PUR 250 O Location FBH is not mapped E BE BE EB E nimi yr S o Location FCH is factory use only Basic timer counter register Brent 253 Location is mapped SAMSUNG ELECTRONICS 8 3 Lm 53 8419 UM REV3 00 8 RESET and Power Down Table 8 3 S3C8418X F8418X 8419X F8419X Set 1 Bank 1 Register values after RESET RegeerMame 888 neat De Hex 7 6 5 4 3 2 1 0 Timer 1 interrupt pending register_ TINTPND 224 E o o o 0 0 0 0 TimerAconrolregster TACON 25 oO 0 0 Jo 0 0 0 Timer A counter register TACNT 227 ESH o o 0 0 0 0 Timer 1 0 control register Ticono 232 Es o o 0 0 0 Timer 101 con
24. SAMSUNG ELECTRONICS 6 47 e 53 8419 UM REV3 00 6 Instruction Set 6 6 35 LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst opc src 2 4 r IM 4 ra r R src opc dst 2 4 r9 R r r OtoF dst src 2 4 C7 r Ir 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR dst src 3 6 E6 R IM D6 IR IM src dst 3 6 F5 IR R opc dst src x 3 6 87 r x r src dst x 3 6 97 x r r SAMSUNG ELECTRONICS 6 48 Lm 53 8419 UM REV3 00 6 Instruction Set Examples Given RO 01H R1 OAH register OOH 01H register 01H 20H register 02H 02H LOOP 30H and register 3AH OFFH LD RO 10H gt RO 10H LD RO 01H gt RO 20H register 01H 20H LD 01 0 gt Register 01H 01H RO O1H LD R1 RO gt R1 20H RO 01H LD RO R1 gt RO 01H R1 OAH register 01H OAH LD 00H 01H gt Register 00H 20H register 01 20H LD 02H Q00H gt Register 02H 20H register 00H 01H LD 0AH gt Register OOH OAH LD Q00H 410H gt Register 00H 01 register 01H 10H LD Q00H 02H gt Register 01 register 01H 02 register 02H 02H LD RO LOOP R1 gt RO O
25. Wate for Interrupt WFI Operation The CPU is effectively halted before an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4n 3F NOTE 1 2 3 Example The following sample program structure shows the sequence of operations that follow statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed SAMSUNG ELECTRONICS 6 85 eux 53 8419 00 6 6 71 XOR Logical Exclusive OR XOR dst src Operation dst dst XOR src 6 Instruction Set The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different Otherwise a 0 bit is stored Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 B2 r r B3 r Ir src dst 3 6 B4 R R
26. dst src RA If dst src 0 PC lt PC Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is O the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Src dst RA 3 12 C2 r Ir Given R1 02H R2 and register 02H CPIJE R1 QR2 SKIP gt R2 04H PC jumps to SKIP location In this example the working register R1 contains the value 02H the working register R2 the value 03H and the register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJE instruction must be within the allowed range of 127 to 128 SAMSUNG ELECTRONICS 6 30 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 19 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Fla
27. 1 nnne ens 2 4 IJI cp 4 1 Set 1 Bank 0 Registers eed ere ____ __ read d 4 2 1 Bank 1 R8glslers l uu elena MELDE 4 3 Interrupt ecc 5 7 Interrupt Control Register 1 20 00 202121 2 110001000006 nnn einen en 5 8 Interrupt Source Control and Data 5 10 Instruction Group Summary irte tree LM HE LER ee 6 2 Flag Notation ConVventi9 ns nao 7 Instruction Set Symbols J L a te EIER era dust 7 Instruction Notation Conventions U 8 OPGODE Quick Heference iiiter Ee CHE eee eed Dean LP side RR 9 Condition CodeS 11 S3C8418X F8418X 8419X F8419X Set 1 Register values after RESET 8 2 S3C8418X F8418X 8419X F8419X Set 1 Bank 0 Register values after 8 3 S3C8418X F8418X 8419X F8419X Set 1 Bank 1 Register values after 8 4 S3C8418X F8418X 8419X F8419X Port Configuration Overview 9 1 Port Data Register Summary 9 2 PWM Control and Da
28. 6 1 6 123 Addressing 0 825 aR AE 6 1 6 2 FLAGS REGISTER LIE ERE RF exea este Reese snp aas 6 5 6 3 Flag DesScriptiOris uae deci ugue dun da putet uv 6 6 6 4 Instruction Set Notalionu u N Q A LR k ga m a een 7 6 5 Condition 8 c 11 6 6 Instruction DescriptiOns tiro o 12 6 6 1 Add With 6 13 6 622 ADD AG uuu ua 6 14 6 6 3 AND Logical AND D Rue RR REL ea adds 6 15 6 6 4 BAND Bit AND tend eee 6 16 6 65 BCP Bit accent bt Lente Eee reuerendi uc aet etu rtt rtt 6 17 6 6 6 BITC Bit Complement U 6 18 6 6 7 BITR RESOU e ett etis paqa aun a edd e ans Costs s bee ctus etus 6 19 6 628 BITS Bit Sel oie P ee ien haad Beet a Pann E see assqa qasay dee 6 20 6 6 9 BOR Bit OR C M 6 21 6 6 10 BTJRF Bit Test Jump Relative on False a 6 22 6 6 11 BTJRT Bit Test Jump Relative on True a 6 23 6 612 BXOR Bit XOR iu Mt 6 24 6 6 19 CALL
29. If you want below For example 1 LD LPOT 00000000B 2 LD LPOT 01001111B N channel open drain output NOTE If you want to use as a LCD port you must set register appropriately Refer to Ex 2 below to use as a Normal I O you must set LPOT register appropriately Refer to Ex 1 P4 0 P4 3 is Normal I O P4 0 P4 3 is LCD port For more detail please refer to page 9 19 SAMSUNG ELECTRONICS 12 CONTROL REGISTERS PAGE 4 31 PP Register Page Pointer DFH Set 1 Bit Identifier RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits hr pee DEM 3 0 Source Register Page Selection Bits lia iM B RU n NOTES 1 In the S3C8418X F8418X microcontroller the internal register file is configured as two pages Page 0 Page 2 The page 0 is used for the general purpose register file and data register 2 In the S8C8419X F84I9X microcontroller the internal register file is configured as three pages Page 0 2 The page 0 and page 1 are used for the general purpose register file and data register 3 The page 2 is used for the LCD display ram and it is a write only memory SAMSUNG ELECTRONICS ex 13 PORT CONTROL REGISTERS PAGE 9 5 PROGRAMMING TIP make as Normal I O or Alternative function ORG 0100H STAR
30. K 0 Push pull output mode If you want register Alternative function mode ADO input NOTE If you want to use PO as a LCD port you must set LPOT register appropriately Refer to Ex 2 below to use PO as a Normal I O or Alternative function ADCO ADC3 you must set appropriately Refer to Ex 1 below For example 1 LD LPOT 00000000B 2 LD LPOT 01001111B P0 0 P0 3 is Normal I O or Alternative function ADCO ADC3 P0 0 P0 3 is LCD port For more detail please refer to page 9 5 SAMSUNG ELECTRONICS 7 CONTROL REGISTERS P2CONH Port 2 Control 7 6 PAGE 4 24 Register High Byte ECH Set 1 P2 7 SEG3 TxD Configration Bits Input mode Alternative function mode Not used K EEJ Push pull output mode 5 4 Alternative function mode TxD output P2 6 SEG2 RxD Configration Bits KEE Input mode RxD input cake Alternative function mode Not used Push pull output mode Alternative function mode RxD output P2 5 SEG1 SCK Configration Bits o Input mode SCK input Alternative function mode Not used Push pull output mode Alternative function mode SCK output 2 4 5 0 5 Configration Bits 81 Input mode o i Alternative function mode Not used 1 0 Push pull output mode If you want LPOT Alternative function mode SO output NOTE If you want to use a P2 as LCD port you must set LPOT
31. Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode Prime Data Registers All Addressing Modes LCD Display Registers NOTE Page2 s 00H 13H is used for LCD Display Registers Write only Figure 2 3 Internal Register File Organization of 53 8419 8419 SAMSUNG ELECTRONICS 2 5 Lm 53 8419 UM REV3 00 2 Address Spaces Bank 0 System and Peripheral Control Registers Register Addressing Mode General Purpose Data Registers Indirect Register Indexed System and Mode and Stack Operations Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode Prime Data Registers All Addressing Modes LCD Display Registers NOTE Page2 s 00H 13H is used for LCD Display Registers Write only Figure 2 4 Internal Register File Organization of S3F8418X C8418X SAMSUNG ELECTRONICS 2 6 ea 53 8419 UM REV3 00 2 Address Spaces 2 3 1 Register Page Pointer PP The S3C8 series architecture supports the logical expansion of the physical 512 byte internal register file using an 8 bit data bus into as many as 2 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the S3C8418X F8418X C8419X F8419X microcontroller a paged register file expansion is implemented for data registers and the register page pointer must be changed to addres
32. Ports Total 34 bit programmable pins 44QFP Total 32 bit programmable pins 42SDIP SAMSUNG ELECTRONICS 1 3 1 Product Overview 53 8419 UM REV3 00 1 Product Overview Timers and Timer Counters e One programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer function e One 8 bit timer counter Timer A with three operating modes Interval mode capture mode and PWM mode e One 8 bit timer Timer B with carrier frequency or PWM generator e Two 16 bit timer counter Timer 10 11 with three operating modes Interval mode Capture mode and PWM mode Watch Timer e Real time and interval time measurement e Four frequency output to BUZ pin e Clock generation for LCD LCD Controller Driver Optional e 8COMX 16 SEG e 3 4 and 8 common selectable A D Converter e 10 bit resolution e Eight analog input channels Asynchronous UART e One Asynchronous UART e Programmable baud rate generator e Supports serial data transmit receive operations with 8 bit 9 bit in UART PWM module e One 10 bit programmable PWM output Serial I O e One synchronous serial I O module e Selectable transmit and receive rates Built in RESET circuit LVR e Low Voltage check to make system reset e 2 8 V by smart option SAMSUNG ELECTRONICS 1 4 e 53 8419 UM REV3 00 Oscillation Frequency e 1 MHz to 10 MHz external crystal oscillator Operating Temperature Range e 25 C to
33. SAMSUNG ELECTRONICS te however that you cannot access locations COH FFH in Register File ADDRESS Point to One Register in Register File Address of Operand used by Instruction Value used in OPERAND ruction Execution Where SHIFT is the label of an 8 bit register address Indirect Register Addressing to Register File 3 3 53 8419 UM REV3 00 3 Addressing Modes Register File REGISTER Example struction References OPCODE Points to Address Points to Program Memory Program Memory 16 Bit Sample Instructions Value used in OPERAND CALL RR2 nstruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory SAMSUNG ELECTRONICS 3 4 e 53 8419 UM REV3 00 3 Addressing Modes Register File d NN RPO or RP1 RPO or RP1 Selected RP points Program Memory to start fo P working register D NENNEN block Working dst src Register Point to the ADDRESS Address Working Register po Go __________ Value used in OPERAND LN spumam Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File SAMSUNG ELECTRONICS 3 5 ea 53 8419 UM REV3 00 4 bit Working Register Address Example Instruction References either Program Memory or Data Memory Program Memory Ec Sample Instructions LCD LDE LDE Figure 3 6 SAMSUNG ELECTRONICS R5 RR6 R3 RR14 RR4 R8 3 Addressing
34. SAMSUNG ELECTRONICS 13 2 Lm S3F8419_UM_REV3 00 13 10 bit PWM Pulse width Modulation Table 13 2 PWM Output stretch Values for Extension Data Register PWMDATAL 1 0 PWMDATAL Bit Biti BitO Stretched Cycle Number 11 PWM Data 4 MHz 00000000B XXXXXX00B 00000001B Register Values PWMDATAH PWMDATAL 10000000B Xxxxxx0OOB 11111111B Xxxxxx0OOB Figure 13 1 10 Bit PWM Basic Waveform SAMSUNG ELECTRONICS 13 3 ea 53 8419 UM REV3 00 13 10 bit PWM Pulse width Modulation PWM Clock 4 MHz 00000010B 01 Basic PWMDATA 00001001B waveform 27 V 01 B ist 2nd 3th 4th 1st 2nd 3th 4th Extended waveform 40H Figure 13 2 10 Bit Extended PWM Waveform SAMSUNG ELECTRONICS 13 4 eux 53 8419 UM REV3 00 13 10 bit PWM Pulse width Modulation 13 2 2 PWM Control Register PWMCON The control register for the PWM module PWMCON is located at register address FSH PWMCON is used the 10 bit PWM modules Bit settings in the PWMCON register control the following functions e PWM counter clock selection e PWM data reload interval selection e PWM counter clear e PWM counter stop start or resume operation e PWM counter overflow 10 bit counter overflow interrupt control A reset clears all PWMCON bits to logic zero disabling the entire PWM module PWM Control Register PWMCON F5H R W Reset 00H PWM input clo
35. 2 0 Not used for the 53 8418 8418 8419 8419 SAMSUNG ELECTRONICS 4 32 Lm 53 8419 00 4 Control Registers 4 1 33 SIOCON Serial Module Control Registers F2H Set 1 Bank1 FOFFFFFFF Bit Identifier RESET Value Read Write SAMSUNG ELECTRONICS R W R W R W R W R W SIO Shift Clock Selection Bit R W R W R W 0 Interval clock P S Clock 1 External clock SCK Data Direction Control Bit 0 MSB first mode 1 LSB first mode SIO Mode Selection Bit 0 Receive only mode 1 Transmit Receive mode Shift Clock Edge Selection Bit 0 Tx at falling edges Rx at rising edges 1 Tx at rising edges Rx at falling edges SIO Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting SIO Shift Operation Enable Bit O Disable shift and clock counter 1 Enable shift and clock counter SIO Interrupt Enable Bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO Interrupt Pending Bit 0 interrupt pending 1 Interrupt pending Clear pending bit when write 4 33 53 8419 UM REV3 00 4 Control Registers 4 1 34 SIOPS SIO Prescaler Register FOH Set 1 Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write RAN RAN RAN RAN RAN RAN R W R W Add
36. 4 3 2 7 9 1 1 1 1 1 1 1 1 RESET Value Read Write R W R W R W R W R W R W R W R W 7 P2 7 Pull up Resistor Enable Disable Pull up resistor disable B Pull up resistor enable 6 P2 6 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 5 P2 5 Pull up Resistor Enable Disable Pull up resistor disable 1 Pull up resistor enable 4 P1 4 Pull up Resistor Enable Disable Pull up resistor disable B Pull up resistor enable 3 P2 3 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 2 P2 2 Pull up Resistor Enable Disable Pull up resistor disable 1 Pull up resistor enable 1 P2 1 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable 0 2 0 Pull up Resistor Enable Disable Pull up resistor disable ES Pull up resistor enable SAMSUNG ELECTRONICS 4 25 53 8419 UM REV3 00 4 Control Registers 4 1 25 P3CONH Port 3 Control Register High Byte EEH Set 1 Bank0 Bit Identifier 7 6 5 4 3 2 o 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 7 SEG11 Configration Bits ofo mame Fo t mumoewhpuup 1 0 Push pull output mode N channel open drain output 5 4 P3 6 SEG10 Configration Bits oforme Fo r mumwewmpdu i 0 Pustput ouput mode ____
37. 6 6 28 EXIT Exit EXIT Operation IP lt SP SP lt SP 2 lt lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 16 2F Example The diagram below shows an example of how to use an EXIT statement Before After Address Data Address Data Address Address Data PC 0110 50 PCL old 60 Main 51 PCH 140 20 21 IPL 50 22 Data Miu 22 Data PSI Stack Stack SAMSUNG ELECTRONICS 6 41 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 29 IDLE Idle Operation IDLE Operation Flags Format Example See description The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F The instruction IDLE stops the CPU clock but it does stop the system clock SAMSUNG ELECTRONICS 6 42 eux 53 8419 UM REV3 00 6 6 30 INC Increment INC Operation Flags Format Examples dst dst dst
38. 6 6 6 BITC Bit Complement BITC Operation Flags Format dst b dst b NOT dst b This instruction complements the specified bit within the destination without affecting any other bit in the destination C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 60 2 4 57 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R1 1 gt R1 05H If the working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101 in the register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register 0D5H is cleared SAMSUNG ELECTRONICS 6 18 eu 53 8419 UM REV3 00 6 Instruction Set 6 6 7 BITR Bit Reset BITR dst b Operation dst b 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst 45116 0 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address 0 is three bi
39. 65535 where 2 14 Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode addr addr range 0 65535 Relative addressina mode addr addr a number from 127 to 128 that is an 9 offset relative to the address of the next instruction Immediate addressing mode data data 0 255 Immediate long addressing mode data data 0 65535 Indirect register pair or indirect working RRp or reg reg 0 254 even only register pair where p 0 2 14 SAMSUNG ELECTRONICS 8 a 53 8419 UM REV3 00 6 Instruction Set Table 6 5 OPCODE Quick Reference NIBBLE mn DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 11 72 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM 0 is SBC SBC SBC SBC SBC BTJR IRR1 11 72 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 b RA DA OR LDB R1 ii A E Hs ip R2 R1 es e B n ro Rb POP POP AND AND AND AND AND BITC R1 IR1 11 72 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM 0 PUSH PUSH TM BIT R2 IR2 B 2 i R2 R1 Pi Ai n r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 X RL POPUD POPUI DIV DIV DIV R1 ie IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 Pe X a INCW INCW CP LDC RR1 IR1 d ie R2
40. 85 C Operating Voltage Range e LVR on LVR to 5 5 V 8 MHz e LVR off 2 5 V to 5 5 V 8 MHz e LVR off on 4 5 V to 5 5 V 10 MHz Package Type 42 pin SDIP Only for 53 8419 8419 44 pin QFP 53 8418 8418 8419 8419 SAMSUNG ELECTRONICS 1 Product Overview 53 8419 UM REV3 00 1 Product Overview 1 4 Block Diagram P1 0 P1 5 0 0 0 3 INTO INTS TBOUT PWM BUZ COM0 COM3 TAOUT TACAP TACK AD5 AD6 ADO AD3 T1OUT1 T1CK1 T1CAP1 Port 0 Port 1 Xin p Xout lt OSC XTin nRESET XTout lt nRESET 8 Bit Basic Timer P2 0 P2 7 T1OUTO0 T1CKO0 T1CAPO AD4 AD7 SEGO SEG3 PWM SI SO SCK RxD TxD TBPWM I O Port and Interrupt Control P1 0 TAOUT 8 Bit Timer Counter P2 0 TBPWM A B P3 0 P3 7 SEG4 SEG11 SAM8RC CPU P2 2 T1OUT0 lt WAT E em gt P13 TOUTI lt 4 Timer Counter P4 0 P4 7 SEG12 SEG19 COM4 COM7 P1 4 T1CK1 gt 10 11 P1 5 TICAP1 ADCO ADC7 P0 0 P0 3 P1 4 P1 5 P2 2 P2 3 AVREF AVss P2 7 TxD 8 32K Byte 272 528 Byte P 6 RxD gt UART ROM RAM 8 LCD Driver SEGO SEG19 SEG16 lt Controller AAS ENT YN YY SIO EM Y P2 3 P2 5 P2 4 P2 1 PWM SCK SO Figure 1 1 53 8418 8418 8419 8419 Block Diagram SAMSUNG ELECTRONICS 1 6 Lm 53 8419 UM REV3 00 1 5 Pin Assignment INTO TAOUT P1 0
41. Example 17 1 Using the Watch Timer ORG 0000h VECTOR OD6h WT INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt LD IMR 00010000b Enable IRQ3 interrupt LD SPH 00000000b LD SPL 0FFh LD BTCON 10100011b Disable Watch dog LD WTCON 11001110b 0 5 kHz buzzer 1 955ms duration interrupt _ Interrupt enable fxt 32 768Hz EI MAIN ROUTINE T MIAN WTCON 11111110b pending clear SAMSUNG ELECTRONICS 17 4 e 53 8419 UM REV3 00 18 LCD Controller Driver LCD Controller Driver 18 1 Overview S3C8418X F8418X 8419X F8419X microcontroller can directly drive an up to 128 dot 16segments x 8 commons LCD panel Its LCD block has the following components e LCD controller driver e Display RAM for storing display data e 16 segment output pins SEGO SEG 15 e 8 common output pins COM0 COM7 e Internal resistor circuit for LCD bias To use the LCD controller bit 1 in the watch mode register WTCON must be set to 1 because LCDCK is supplied by the watch timer The LCD mode control register LMOD is used to turn the LCD display on or off to select LCD clock frequency to turn the COM signal output on or off to select bias and duty Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control The LCD port control register LPOT is used to determine the LCD signal pins used for display output When a sub clock is selec
42. Figure 16 3 A D Converter Circuit Diagram SAMSUNG ELECTRONICS 16 3 a 53 8419 UM REV3 00 16 A D Converter 16 2 2 Internal Reference Voltage Levels In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVSS to AVREF AVREF VDD Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first bit conversion is always 1 2 AVREF 16 2 3 Conversion timing The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore total of 50 clocks is required to complete a 10 bit conversion With a 10 MHz CPU clock frequency one clock cycle is 400 ns 4 fxx If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits set up time 10 clock 50 clocks 50 clock x 400 ns 20 us at 10 MHz 1 clock time 4 fxx ADCON 0 lt 1 I I I Conversion 50 ADC Clock Start I I I KR KERALA I ADDATAH 8 Bit ADDATAL 2 Bit Valid i Data Set up time 10 clock I Previous Value 40 Clock Figure 16 4 A D Converter Timing Diagram SAMSUNG ELECTRONICS 16 4 e 53 8419 00 16 A D Converter 16 2 4 Internal A D Conversion Procedure 1
43. Pin Configuration 44QFP 42SDIP EPROM Programmability User Program multi time Programmed at the factory SAMSUNG ELECTRONICS ex 29 FLASH MEMORY CONTROL REGISTERS PAGE 20 1 20 2 Flash Memory Control Register FMCON register is available only in user program mode to program some data to the flash memory Flash Memory Control Register FMCON FCH Set1 Bank1 R W Flash Memory Mode Selection Bits Flash Operation Start Bit 0101 Programming mode 0 Operation stop 1010 Erase mode 1 Operation start 0110 Hard lock mode This bit will be cleared automatically others Not used for 5328419 just after the corresponding operation completed Sector Erase Fail Flag 0 Sector Erase success 1 Sector Erase fail INT enable bit during sector erase 0 2 INT disable 1 2 INT enable Figure 20 1 Flash Memory Control Register FMCON You can select whether to use interrupt or not during Flash Sector erase process If you set FMCON 3 to 0 you don t use interrupt during Flash Sector erase process If you set FMCON 3 to 1 you use interrupt during Flash Sector erase process If you intended to use some interrupts during Flash Sector erase you must check Sector Erase Fail Flag after Flash Sector erase is done Please refer to page 20 7 SAMSUNG ELECTRONICS eux 30 PROGRAMMING TIP OF FLASH MEMORY PAGE 20 7 PROGRAMMING TIP Sector Erase Not to use an interrupt SBI LD FMUSR 0A5H User Program mode enab
44. System Registers CFH Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H RP1 to locations C8H CFH that is to the common working register area NOTE In the 53 8419 8419 microcontroller pages 0 2 are implemented and S3C8418X F8418X microcontroller page0 and are inplemented 0 2 contain all of the addressable registers in the internal register file Register Addressing Only 2 Address Spaces General Purpose Register Prime Registers Page 0 1 Page 0 1 Page 2 All Addressing Modes Indirect Register All Indexed Addressing Modes Addressing Modes Can be pointed by Register Pointer Can be pointed by Register Pointer Figure 2 12 Register File Addressing SAMSUNG ELECTRONICS 2 15 53 8419 UM REV3 00 2 Address Spaces 2 4 1 Common Working Register Area COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO COH C7H e C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for
45. e starts the A D conversion Only one analog input channel can be selected at a time You can dynamically select any one of the eight analog input pins ADCO ADC7 by manipulating the 3 bit value for ADCON 6 ADCON 4 A D Converter Control Register ADCON F7H Set 1 Bank 0 R W ADCON 3 bit is read only Not used Start or Enable bit must keep always 0 0 Disable Operation 1 Start Operation A D Input Pin Selection bits A D Input pin Clock Selection bit Conversion Clock fxx 16 fxx 8 fxx 4 Not used End of Conversion bit read only 0 Conversion not complete 1 Conversion complete Figure 16 1 A D Converter Control Register ADCON SAMSUNG ELECTRONICS 16 2 Lm 53 8419 UM REV3 00 16 A D Converter Conversion Data Register High Byte ADDATAH F8H Set 1 Bank 0 Read only Conversion Data Register Low Byte ADDATAL F9H Set 1 Bank 0 Read only Figure 16 2 A D Converter Data Register ADDATAH ADDATAL ADCON 4 6 Select one input pin of the assigned 11 fxx 16 ADCON 2 1 To ADCON 3 y EOC Flag p Clock fxx 4 gt Selector ADCON O ADC Enable Input Pins Analog ADCO ADC7 Comparator 0 0 PO 3 1 4 P1 5 P2 2 P2 3 Successive Approximation Logic ADCON 0O A D Conversion enable 10 bit result is loaded into A D Conversion Data Register o0xo0 o0 c 10 bit D A Conversion Result Converter ADDATAH ADDATAL To Data bus
46. 0 L nennen 5 9 SAMSUNG ELECTRONICS ex 5 8 Peripheral Interrupt Control Registers 5 10 5 9 System Mode Register SYM 5 11 5 10 Interrupt Mask Register 5 12 5 11 Interrupt Priority Register denne eee de Panno 5 13 5 12 Interrupt Request Register IRQ 5 15 5 13 Interrupt Pending Function Typ8s u U 5 16 ETE 5 16 5 13 2 Pending Bits Cleared Automatically by 2 5 16 5 13 3 Pending Bits Cleared by the Service Routine a 5 16 5 14 Interrupt Source Polling Sequence sse enne 5 17 5 14 1 Interrupt Service Routines U U entente sinn 5 17 5 15 Generating interrupt Vector Addresses U n 5 18 5 15 1 Nesting of Vectored 5 18 6 INSTRUCTION SET J J J J J 6 1 BT OV ORV IW UD o 6 1 6 1 Dala TYPOS 6 1 6 1 2 nn San Ere au
47. 00101010B in the destination register 00H The sign flag and the overflow flag are both cleared to SAMSUNG ELECTRONICS 6 73 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 59 580 Select Bank 0 SBO Operation BANK lt 0 The 580 instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting the bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 Example The statement SBO clears FLAGS 0 to 0 selecting the bank 0 register addressing SAMSUNG ELECTRONICS 6 74 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 60 SB1 Select Bank 1 SB1 Operation BANK 1 The 581 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting the bank 1 register addressing in the set 1 area of the register file NOTE Bank 1 is not implemented in some KS88 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement 581 sets FLAGS 0 to 1 selectin the bank 1 register addressing if bank 1 is implemented in the microcontrooler s internla register file SAMSUNG ELECTRONICS 6 75 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 61 SBC Subtract with Carry SBC Operation Flags Format Examples dst src dst lt dst src c The source operand along wit
48. 2 Analog input must remain between the voltage range of AVSS and AVREF Configure 0 0 0 3 P1 4 P1 5 2 2 2 3 for analog input before A D conversions To do this you load the appropriate value to the POCONL for ADCO ADCS P1CONH for ADC5 ADC6 and P1CONH for ADCA ADC7 registers Before the conversion operation starts you must first select one of the eight input pins ADCO ADC7 by writing the appropriate value to the ADCON register When conversion has been completed 50 clocks have elapsed the EOC ADCON 3 flag is set to 1 so that a check can be made to verify that the conversion was successful The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state The digital conversion result can now be read from the ADDATAH and ADDATAL register Analog ADCO Input Pin ADC7 S3C8419X F8419X S3C8418X F8418X AVss Vss NOTE 1 The symbol R signifies an offset resistor with a value of from 50 to 1000 2 Avref must be tied to Vdd Figure 16 5 Recommended A D Converter Circuit for Highest Absolute Accuracy SAMSUNG ELECTRONICS 16 5 Lm 53 8419 UM REV3 00 ADO CHK AD3 CHK SAMSUNG ELECTRONICS 16 A D Converter Example 16 1 Configuring A D Converter POCON 11111111B ADCON 00000001B ADCON 00001000B Z ADO_CHK ADOBUFH ADDATAH ADOBUFL ADDATAL ADCON 00110001B ADCON 00001000B Z AD3_CHK ADS
49. 3 2 P3 5 SEG9 Configration Bits Fo r mumwewmpdu Pustput ouput mode 1 0 P3 4 SEG8 Configration Bits o mima SSCS o i Push pull output mode N channel open drain output NOTE If you want to use P3 as a LCD port you must set LPOT register appropriately Refer to Ex 2 below If you want to use P3 as a Normal I O you must set LPOT register appropriately Refer to Ex 1 below For example 1 LD LPOT 00000000B P3 4 P3 7 is Normal I O 2 LD LPOT 01001111B P3 4 P3 7 is LCD port For more detail please refer to page 9 16 SAMSUNG ELECTRONICS 4 26 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 26 P3CONL Port 3 Control Register Low Byte EFH Set 1 Bank0 Bit Identifier 7 6 5 4 3 2 o 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 SEG7 Configration Bits Push pull output mode N channel open drain output 5 4 P3 2 SEG6 Configration Bits 3 3 P3 1 SEG5 Configration Bits o o mumm Fo r mumwewmpdu Pustput ouput mode 1 0 P3 0 SEG4 Configration Bits Push pull output mode N channel open drain output NOTE If you want to use P3 as LCD port you must set LPOT register appropriately
50. AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in the register R1 SAMSUNG ELECTRONICS 6 15 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 4 BAND Bit AND BAND dst src b BAND dst b src Operation dst 0 lt dst 0 AND src b or dst b lt dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or the source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Flags C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 67 ro Rb src b 1 dst 3 6 67 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 gt 1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example the source register 01H contains the value 05H 00000101 and the destination working register R1 contains 07H 000001 11B The statement BAND R1 01H 1 ANDS the bit 1 value of the source register 0
51. B5 R IR dst src 3 6 B6 R IM Examples Given RO 0C7H R1 and register 02H 23H XOR RO R1 XOR RO R1 XOR 00H 01H XOR 00H 01H XOR OOH 54H 02H R2 18H register OOH 2BH register 01H 02H gt RO OC5H R1 02H gt RO OE4H R1 02H register 02H 23H gt Register 29H register 01H 02H gt Register 08H register 01H 02H register 02H 23H gt Register 00H 7FH In the first example if the working register RO contains the value 0C7H and if the register R1 contains the value 02H RO value and stores the SAMSUNG ELECTRONICS the statement RO R1 logically exclusive ORs the R1 value with the result OC5H in the destination register RO 6 86 mm 53 8419 00 7 Clock Circuit Clock Circuit 7 1 Overview The clock frequency generated for the Main clock of S3C8418X F8418X C84I9X F8419X by an external crystal can range from 1 MHz to 10 MHz The maximum CPU clock frequency is 10 MHz The XIN and XOUT pins connect the external oscillator or clock source to the on chip clock circuit Also the subsystem clock frequency for the Watch timer by an external crystal can range from 30 kHz to 35 kHz The XTIN and XTOUT pins connect the external oscillator or clock source to the on chip clock circuit 7 1 1 System clock Circuit The system clock circuit has the following components e External crystal or ceramic resonator oscillation source
52. Data Bus fxx 4096 Clear Y fxx 1024 8 Bit Up Counter BTCNT Read Only 128 R NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Start the CPU nete Figure 10 2 Basic Timer Block Diagram SAMSUNG ELECTRONICS 10 4 eux 53 8419 UM REV3 00 11 8 bit Timer A B 8 bit Timer A B 11 1 8 Bit Timer A 11 1 1 Overview The 8 bit timer A is an 8 bit general purpose timer counter Timer A has three operating modes you can select one of them using the appropriate TACON setting e Interval timer mode Toggle output at TAOUT e Capture input mode with a rising or falling edge trigger at the TACAP pin e PWM mode TAPWM Timer A has the following functional components e Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer e External clock input pin TACK e 8 bit counter TACNT 8 bit comparator and 8 bit reference data register TADATA e pins for capture input PWM or match output TAOUT e Timer A overflow interrupt vector C2H and match capture interrupt IRQ1 vector COH generation e Timer A control register TACON set 1 bank1 E1H read write SAMSUNG ELECTRONICS 11 1 ea 53 8419 UM REV3 00 11 8 bit Timer A B 11 1 2 Function Description 11 1 2 1 Timer A Interrupts IRQ1 Vectors COH and C2H The timer A module can generate two
53. Elapsed time for low and high data values 1 0 1 Not Used 3 Ti 3 er B Interrupt Enable Bit Disable Interrupt 1 Enable Interrupt 2 Ti 3 er B Start Stop Bit Stop timer B 1 Start timer B 1 Timer B Mode Selection Bit One shot mode 1 Repeating mode 0 Timer B Output flip flop Control Bit T FF is low 1 T FF is high NOTE fxx is selected clock for system SAMSUNG ELECTRONICS 4 40 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 43 TINTPND Timer A Timer 1 Interrupt Pending Register EOH Set 1 Bank1 Bit Identifier L7 6 8 4 3 2 4 o 0 0 0 0 0 0 0 0 RESET Value Read Write _ _ R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the 53 8418 8418 8419 8419 must keep always 0 5 Timer 1 1 Overflow Interrupt Pending Bit EN No interrupt pending E Clear pending bit when write Interrupt pending 4 Timer 1 1 Match Capture Interrupt Pending Bit ea No interrupt pending EN Clear pending bit when write Interrupt pending 3 Timer 1 0 Overflow Interrupt Pending Bit No interrupt pending EN Clear pending bit when write Interrupt pending 2 Timer 1 0 Match Capture Interrupt Pending Bit EN No interrupt pending EN Clear pending bit when write Interrupt pending 1 Timer A Overflow Interrupt Pending Bit No interrupt pending EN Clear pending bit when write Interrupt pending 0 Timer Match Capture In
54. INT1 BUZ TACK P1 1 SDAT INT2 TACAP P1 2 SCLK INT3 T1OUT1 P1 3 VDD vss Xout Xin Vpp TEST Xtin Xtout Figure 1 2 SAMSUNG ELECTRONICS O Q G N 43 P4 6 SEG18 COM6 42 L3 P4 5 SEG17 COM5 41 E3 4 SEG16 COM4 40 DJ P4 3 SEG 15 39 P4 2 S EG 14 38 L3 P4 1 SEG13 37 P4 0 SEG12 36 E P3 7 SEG11 35 P3 6 SEG10 44 L3 P4 7 SEG19 COM7 34 LJ P3 5 SEG9 53 8419 8419 S3C8418X F8418X Top View 44 QFP nRESET 12 TBPWM T1 2 0 13 PWM T1CAPO P2 1 14 T1OUTO AD4 P2 2 15 T1CK1 AD5 P1 4 16 T1 CAP1 AD6 1 5 17 SI AD7 P2 3 18 SO SEGO P2 4 C 19 SCK SEG1 P2 5 20 Rx SEG2 P2 6 21 1 7 TX SEG3 P2 7 22 1 Product Overview P3 4 SEG8 P3 3 SEG7 P3 2 SEG6 P3 1 SEG5 P3 0 SEG4 PO 3 COM3 AD3 P0 2 COM2 AD2 P0 1 COM 1 AD 1 P0 0 COMO ADO Avss Avref S3C8418X F8418X C8419X F8419X Pin Assignment 44 pin 53 8419 UM REV3 00 SEG 14 P4 2 SEG 15P4 3 SEG 16 4 4 4 SEG 17 COM5 P4 5 COM6 SEG 18 P4 6 COM7 SEG 19 P4 7 INTO TAOUT P1 0 INT 1 BUZ TACK P1 1 SDAT INT2 TACAP P1 2 SCLK INT3 T1 OUT 1 P1 3 VDD VSS Xout Xin Vpp TEST XTin XTout nRESET TBPWM T1CKO P2 0 PWM T1 2 1 T1OUT0 AD4 P2 2 Figure 1 3 SAMSUNG ELECTRONICS 53 8419 8419 View 42 SDIP 1 Product Overview P4 1 SEG 13 P4 0 SEG 12 P3 7 SEG11 P3 6 SEG10 P3 5 SEG9 P3 4 SEG8 P3 3 SEG7 P3 2 SEG6 P3 1 SEG5 P3
55. In operations that test register bits and in shift and rotate operations the Z flag is set to 1 if the result is logic zero S Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number V Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is cleared to 0 after a logic operation has been performed D Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and it cannot be addressed as a test condition H Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is normally not accessed directly by a program FIS Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed wh
56. Table 23 1 Table 23 2 Table 23 3 Table 23 4 Subsystem Oscillator crystal Stabilization Time IST2 21 7 Data Retention Supply Voltage in Stop Mode sse 21 8 UART Timing Characteristics in Mode 0 10 2 21 10 A D Converter Electrical Characteristics sssssssssssseseseeeenennene enne 21 11 LVR Low Voltage Reset Circuit 21 12 AC Electrical Characteristics for Internal Flash ROM a 21 13 Components of TB8419 18 u rete aaa Bees ees 23 4 Power Selection Settings for 8419 L n nennen 23 4 Clock Source Selection Setting esses esee entrent nennen snnt nnne 23 6 PWM Enable Disable Setting U U 23 7 SAMSUNG ELECTRONICS IL Example Number Example 2 1 Example 2 2 Example 2 3 Example 2 4 Example 2 5 Example 9 1 Example 9 2 Example 9 3 Example 9 4 Example 11 1 Example 11 2 Example 11 3 Example 11 4 Example 12 1 Example 13 1 Example 14 1 Example 16 1 Example 17 1 Example 20 1 Example 20 2 Example 20 3 Example 20 4 Example 20 5 SAMSUNG ELECTRONICS List of Examples Title Page Number Using the Page Pointer for RAM clear Page 0 Page 1
57. gt 101AH SP 00 The RET instruction pops the contents of the stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in the location OOFEH 1AH into the PC s low byte and the instruction at the location 101AH is executed The stack pointer now points to the memory location OOFEH SAMSUNG ELECTRONICS 6 69 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 55 RL Rotate Left RL Operation Flags Format Examples dst C lt dst 7 dst 0 lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag as shown in the figure below ee Set if the bit rotated from the most significant bit position bit 7 was 1 2 Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 90 R 4 91 IR Given Register 00H OAAH register 01H 02H and register 02H 17H RL 00H gt Register 00H 55H 1 RL 801 Register 01H 02H register 02H 2EH C 0 In the first example if the general register 00H contains the value OAAH 10101010B the statement RL 00H rotates the OAAH
58. or an external clock source e Oscillator stop and wake up functions e Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 e System clock control register CLKCON e Oscillator control register OSCCON and STOP control register STPCON SAMSUNG ELECTRONICS 7 1 ea 53 8419 UM REV3 00 7 Clock Circuit XIN S3C8418X S3F8418X S3C8419X S3F8419X Xour Figure 7 1 Main Oscillator Circuit Crystal or Ceramic Oscillator XTIN 53 8418 0 53 8418 53 8419 53 8419 XT OUT 32 768 kHz Figure 7 2 Sub System Oscillator Circuit Crystal Oscillator SAMSUNG ELECTRONICS 7 2 Lm 53 8419 UM REV3 00 7 1 2 Clock Status During Power Down Modes 7 Clock Circuit The two power down modes Stop mode and Idle mode affect the system clock as follows e n Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock e idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release N N Main Ststem Oscillator Circuit OSCCON 3 5 0 S
59. with the bit O value of the register R1 destination leaving the value 06H 00000110B in the register R1 SAMSUNG ELECTRONICS 6 16 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 5 BCP Bit Compare BCP Operation Flags Format dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison C Unaffected Z Setif the two bits are the same cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 src 3 6 17 r0 Rb NOTE In the second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Example Given R1 07H and register 01H 01H BCP R1 01H 1 gt Rl 07H register 01H 01H If the destination working register R1 contains the value 07H 000001 11B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H SAMSUNG ELECTRONICS 6 17 e 53 8419 UM REV3 00 6 Instruction Set
60. 00 15 UART 15 1 6 Baud Rate Calculations The baud rate is determined by the baud rate data register 16 bit BRDATA e Mode 0 baud rate fxx 16 x 16Bit BRDATA 1 e Mode 1 baud rate fxx 16 x 16Bit BRDATA 1 e Mode 2 baud rate fxx 16 x 16Bit BRDATA 1 Table 15 1 Commonly Used Baud Rates Generated by 16bit BRDATA BRDATAH BRDATAL ma om o w 7 m sm sw o o 6 ow s r am sw 39 sm 12 3 2m dez30Hz 12 OCH SAMSUNG ELECTRONICS 15 7 ea 53 8419 UM REV3 00 15 UART 15 2 Block Diagram SAM88 Internal Data Bus RxD P2 6 Baud Rate Generator Zero Detector 4 Tx Control Tx Clock TIP UDRTA gt Start Interrupt gt Rx Clock RIP Receive Rx Control Shift 1 to 0 Transition Detector Shift Value RxD P2 6 SAMBS Internal Data Bus Figure 15 5 UART Functional Block Diagram SAMSUNG ELECTRONICS 15 8 Lu S3F8419_UM_REV3 00 15 UART 15 2 1 UART Mode 0 Function Description In mode 0 UART is input and output through the RxD P2 6 pin and TxD P2 7 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received
61. 1 The contents of the destination operand are incremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Hex dst opc 1 4 rE r OtoF dst 2 4 20 21 Given RO 1BH register OOH OCH and register 1BH OFH INC RO gt RO 1CH INC 00H gt Register OOH INC GRO gt 1 register 01H 10H 6 Instruction Set Addr Mode dst r In the first example if the destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The second example shows the effect an INC instruction has on the register at the location 00H assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of the register 1BH from OFH to 10H SAMSUNG ELECTRONICS 6 43 53 8419 UM REV3 00 6 Instruction Set 6 6 31 INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result is negat
62. 1 1 Tool Program nete rtt entice tet 20 1 20 1 2 User Programi eei idee nate Red nacre tds 20 2 20 2 Flash Memory Control Registers n n nunus 20 3 20 2 1 Flash Memory Control Register l nennen nnns nennen ns 20 3 20 2 2 Flash Memory User Programming Enable Register eee 20 4 20 3 Sector EFAS 20 5 20 4 Program MING et 20 8 20 5 ROACING eee 20 12 20 6 Hard Lock Protection 20 13 2 cu 21 1 21 21 1 22 MECHANICAL 22 1 221 OVelVieW EE 22 1 23 DEVELOPMENT TOOLS 23 1 23 1 En 23 1 2311 Target m 23 1 23 1 2 Programming Socket 23 1 23 1 3 TB8419 18 Target Board rccco odere Bitch Ede ed Ite tede de b Ee Pee need 23 3 Pepa Re o Da E 23 5 2315 STOP LED uu u uu u pas 23 5 23 1 6 Third Parties for Development Tools
63. 15 UART UART Control Register UARTCON F6H Set1 Bank 0 R W Reset Value 00H vso ws ver woe ses s see o mM Operating mode and baud rate selection bits see table below Transmit interrupt enable bit 0 Disable 1 Enable Received interrupt enable bit 0 Disable 1 Enable Multiprocessor communication 1 enable bit mode 2 only 0 Disable 1 Enable If parity disable mode PEN 0 location of the 9th data bit that was received in UART mode 2 0 or 1 Serial data receive enable bit 0 Disable 1 Enable If parity enable mode PEN 1 Even odd parity selection bit for receive data in UART mode 2 0 Even parity check for the received data 1 Odd parity check for the received data If parity disable mode PEN 0 location of the 9th data bit to be transmitted in UART mode 2 0 or 1 If parity enable mode PEN 1 Even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data 2 Mode Description Baud Rate Shift register 16 x 16bit BRDATA 1 8 bit UART _ fxx 16 x 16bit BRDATA 1 9 bit UART fxx 16 x 16bit BRDATA 1 MS1 MSO NOTES 1 In mode 2 if the UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if UARTCON 5 1 then the receive interrut will not be activate
64. 23 1 4 IDLE LED This LED is ON when the evaluation chip S3E8410 is in idle mode 23 1 5 STOP LED This LED is ON when the evaluation chip 5328410 is in stop mode SAMSUNG ELECTRONICS 23 5 23 Development Tools 53 8419 UM REV3 00 23 Development Tools 0000 3EH 0 3EH 1 2 3FH 7 OFF NOTE Smart option is determined by DIP switch Figure 23 3 DIP Switch for Smart Option Ms uon EN ME Table 23 3 Clock Source Selection Setting LVR enable JP10 When to use the external clock from socket Y2 JP10 When to use the internal clock from an emulator SAMSUNG ELECTRONICS 23 6 a 53 8419 UM REV3 00 23 Development Tools Table 23 4 PWM Enable Disable Setting PWM is disabled during no run PWM is always enabled whether run or not INTO TAOUT P1 0 INT1 BUZ TACK P1 1 INT2 TACAP P1 2 P4 7 SEG19 COM7 P4 6 SEG18 COM6 P4 5 SEG17 COM5 P4 4 SEG16 COM4 P4 3 SEG15 P4 2 SEG14 P4 1 SEG13 P4 0 SEG12 P3 7 SEG11 P3 6 SEG10 P3 5 SEG9 P3 4 SEG8 P3 3 SEG7 INTS T1OUT1 P1 3 VDD VSS XOUT WD nRESET TBPWM T1CKO P2 0 T1CAPO PWM P2 1 P3 2 SEG6 T1OUTO AD4 P2 2 P3 1 SEG5 AD5 T1CK1 P1 4 P3 0 SEG4 T1CAP1 AD6 P1 5 P0 3 COM3 AD3 SI AD7 P2 3 P0 2 COM2 AD2 SO SEGO P2 4 P0 1 COM1 AD1 SCK SEG1 P2 5 P0 0 COMO ADO Rx SEG2 P2 6 Avss TX SEG3 P2 7 Avref 1352068 Nid t t Figure 23 4 44 Pin Connector Pin Assignment for TB84I9 SAMSUNG ELECTRONICS 23 7 53
65. 6 6 30 INC 6 43 6 6 31 INCW Increment Word 6 44 6 6 32 IRE T Interrupt Retu aea 6 45 6 6 33 JP JUMP e Te Ert eed eu ELS E RUE 6 46 6 6 34 JR Jump Relative rerit eater i ride kb apnd 6 47 6 6 35 LD EE 6 48 6 6 96 Load iie ridi edd aser aod se ud deat sedans 6 50 6 6 37 LDC LDE Load need caet dere rote Roca ER Ces Le EE 6 51 6 6 38 LDCD LDED Load Memory and 6 53 6 6 39 LDCI LDEI Load Memory and Increment a a 6 54 6 6 40 LDCPD LDEPD Load Memory with 6 55 6 6 41 LDCPI LDEPI Load Memory with 6 56 6 6 42 LDW Load 6 57 6 6 43 MULT Multiply Unsigned uu uuu 6 58 6 6 44 NEXT ue 6 59 6 6 45 NOP No Operations u i ee eee eee 6 60 6 6 46 OR Logical OR 2 6 61 6 6 47 POP Pop from Stack eter ede HIRED Co Ce ELE nor eaae 6 62 6 6 48 POPUD Pop User Stack
66. 7 is LCD port For more detail please refer to page 9 19 SAMSUNG ELECTRONICS 4 28 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 28 PACONL Port 4 Control Register Low Byte F1H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 3 BUZ SEG15 Configration Bits 1 Push pull output mode 5 4 P4 2 SEG14 Configration Bits KEE Input mode 0 1 Input mode with pull up Pt o Push putloutputmede 3 2 P4 1 SEG13 Configration Bits o o mumm Fo input modewihpukup Pustput ouput mode 1 0 P4 0 SEG12 Configration Bits o i ilo Push pull output mode N channel open drain output NOTE If you want to use P4 as LCD port you must set LPOT register appropriately Refer to Ex 2 below If you want to use P4 as Normal I O you must set LPOT register appropriately Refer to Ex 1 below For example 1 LD LPOT 00000000B P4 0 P4 3 is Normal I O 2 LD LPOT 01001111B P4 0 P4 3 is LCD port For more detail please refer to page 9 19 SAMSUNG ELECTRONICS 4 29 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 29 PP Register Page Pointer DFH Set 1 Bit Identifier _5 4 3 2 4 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page
67. 8419 UM REV3 00 23 Development Tools SEG14 P4 2 SEG15P4 3 SEG16 COM4 P4 4 SEG17 COM5 P4 5 COMG6 SEG18 P4 6 COM7 SEG19 P4 7 INTO TAOUT P1 0 INT1 BUZ TACK P1 1 INT2 TACAP P1 2 P4 1 SEG13 P4 0 SEG12 P3 7 SEG11 P3 6 SEG10 P3 5 SEG9 P3 4 SEG8 P3 3 SEG7 P3 2 SEG6 P3 1 SEG5 P3 0 SEG4 AD3 COM3 P0 3 AD2 COM2 P0 2 AD1 COM1 P0 1 TEST AVss XTin AVref XTout P2 7 SEG3 TxD nRESET P2 6 SEG2 RxD TBPWWM T1CKO P2 0 P2 5 SEG1 SCK PWM T1CAPO P2 1 2 4 5 0 5 T1OUTO ADA P2 2 P2 8 AD7 SI WD INTS T1OUT1 P1 3 VDD vss Xout Xin 1351908 Nid cr Figure 23 5 42 Pin Connector Pin Assignment for 8419 Target Board Target System J101 A S 2 5 5 Q Q o o 5 2 2 2 o 5 S Figure 23 6 TB8419 Adapter Cable for 44pin Connector Package SAMSUNG ELECTRONICS 23 8 Lm 53 8419 UM REV3 00 23 Development Tools 23 1 6 Third Parties for Development Tools SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system with an OTP MTP programmer 23 1 7 In Circuit Emulator for SAM8 Family e OPENIice i500 e SmartKit SK 1200 23 1 8 OTP MTP Programmer e SPW uni e AS pro e US
68. Bank 0 R W Reset Value 00H we 7 Ts Pen ree Not used Not used UART transmit interrupt pending flag must keep always 0 must keep 0 Not pending always 0 0 Clear pending bit when write UART parity enable disable 1 Interrupt pending 0 Disable t Enable UART receive parity error UART receive interrupt pending flag 0 No error 0 Not pending 1 Parity error 0 Clear pending bit when write 1 Interrupt pending NOTES In order to clear a data transmit or receive interrupt pendingflag you must write a 0 to the appropriate pending bit A 0 has no effect TO avoid errors we recommend using load instruction except for LDB when manipulating UARTPND values Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted Figure 15 2 UART Interrupt Pending Register UARTPND SAMSUNG ELECTRONICS 15 4 e S3F8419_UM_REV3 00 15 UART In mode 2 9 bit UART data by setting the parity enable bit PEN of UARTPND register to 1 the 9th data bit of transmit data will be an automatically generated parity bit Also the 9th data bit of the received data will be treated as a parity bit for checking the received data In parity enable mode PEN 1 UARTCON 3 TB8 and UARTCON 2 RB8 will be a parity selection bit for transmit and receive data respectivel
69. Circuit Emulator o LR EN SK 1200 0PENIce 1 500 vit Fe ve 0 zu 50 8008 0 D J101 J102 20 10 1 9 428DIP 44QFP R4 160 1 44 150 40 5 40 35 10 35 Swi 15 4oJOaUU0D Uld 001 100 Pin Connector 90 100110120 30 JP1 AR2 25 21 23 SMDS2 SMDS2 Figure 23 2 SSF8419X S3F8418X Target Board Configuration SAMSUNG ELECTRONICS 23 3 Lm 53 8419 UM REV3 00 23 Development Tools Table 23 1 Components of 8419 18 CN1 100 pin connector Connection between emulator and TB8419 8 target board 9101 0102 50 pin connector 2 between target board and user application RESET Push button Generation low active reset signal to S3F8419X 8X EVA chip VCC GND POWER connector External power connector for 8419 8 Indicate the status of STOP or IDLE of S3F8419X 8X IDEE STOP LED Display EVA chip TB8I9 8 target board Table 23 2 Power Selection Settings for 8419 To User Vcc Settings Operating Mode SMDS2 or SK 1000 supplies VDD to the target board evaluation chip and the target system To User SMDS2 or SK 1000 supplies To User VDD only to the target board evaluation chip The target system must have a power supply of its own SMDS2 or SK 1000 SAMSUNG ELECTRONICS 23 4 ex S3F8419_UM_REV3 00
70. Clock Control Register CLKCON SAMSUNG ELECTRONICS 7 4 eux 53 8419 UM REV3 00 7 Clock Circuit Oscillator Control Register OSCCON F2H Set 1 Bank 0 R W Not used must keep always 0 E 1 Subsystem oscillator select Not used must keep always 0 Subsystem oscillator control bit 0 Subsystem oscillator RUN 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP NOTE When the CPU is operated with fxt sub oscillation clock it is possible to use the stop instruction but in this case before using stop instruction you must select fxx 128 for basic timer counter input clock Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms 100 ms Here the warm up time is from the time that the stop release signal activates to the time that basic timer starts counting Figure 7 5 Oscillator Control Register OSCCON STOP Control Register STOPCON E5H Set 1 Bank 0 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction Figure 7 6 STOP Control Register STOPCON SAMSUNG ELECTRONICS 7 5 Lm 53 8419 UM REV3 00 8 RESET and Power Down RESET and Power Down 8 1 System Reset 8 1 1 Overview During a power on reset the voltage at VDD goes to High level and the RESET pin is forced to Low level The RESET signal is input through a Schmitt trigger circuit where it is then synchron
71. EG18 COM6 42 1 P4 5 SEG17 COM5 41 L3 4 SEG16 COM4 40 L1 3 SEG 15 39 P4 2 SEG 14 38 1 1 SEG13 37 1 P4 0 SEG12 36 P3 7 SEG11 35 L3 P3 6 SEG10 34 P3 5 SEG9 O 53 8419 8419 S3C8418X F8418X Top View 44 QFP nRESET C 12 TBPWM T1CKO0 P2 0 13 PWM T1CAPO P2 1 Ci 14 T1OUTO AD4 P2 2 C 15 T1CK1 AD5 P1 4 16 T1CAP1 AD6 P1 5 17 SI AD7 P2 3 18 SO SEGO P2 4 19 SCK SEG1 P2 5 c 20 Rx SEG2 P2 6 21 TX SEG3 P2 7 22 I P3 4 SEG8 P3 3 SEG7 P3 2 SEG6 P3 1 SEG5 P3 0 SEG4 C P0 3 COMS3 ADS3 L P 0 2 C OM 2 AD2 C P0 1 COM 1 AD1 P0 0 COMO ADO LJ Avss Avref Figure 1 2 S3C8418X F8418X C8419X F8419X Pin Assignment 44 SAMSUNG ELECTRONICS eL 2 PIN ASSIGNMENT PAGE 1 5 SEG14 P4 2 SEG15P4 3 SEG16 COM4 P4 4 SEG17 COM5 P4 5 COM6 SEG18 P4 6 COM7 SEG19 P4 7 INTO TAOUT P1 0 INT1 BUZ TACK P1 1 SDAT INT2 TACAP P1 2 SCLK INT3 T10UT1 P1 3 VDD VSS Xout Xin Vpp TEST XTin XTout nRESET 2 0 PWM T1CAPO P2 1 T1OUTO AD4 P2 2 53 8419 8419 Top View 42 SDIP P4 1 SEG13 P4 0 SEG12 P3 7 SEG11 P3 6 SEG10 P3 5 SEG9 P3 4 SEG8 P3 3 SEG7 P3 2 SEG6 P3 1 SEG5 P3 0 SEG4 AD3 COM3 P0 3 AD2 COM2 P0 2 AD1 COM1 P0 1 ADO COMO PO 0 AVss AVref P2 7 SEG3 TxD P2 6 SEG2 RxD P2 5 SEG1 SCK P2 4 SEG0 SO P2 3 AD7 SI Figure 1 3 S3C8419X F8419X Pin Assignment 4
72. ELECTRONICS 6 45 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 33 JP Jump JP JP Operation Flags Format NOTE cc dst Conditional dst Unconditional If cc is true PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC No flags are affected 2 Bytes Cycles Opcode Addr Mode Hex dst cc opc dst 3 8 ccD DA cc 0 to F opc dst 2 8 30 IRR 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the 3 byte instruction format conditional jump the condition code and the OPCODE are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W gt LABEL W 1000H PC 1000H JP 00 gt 0120H The first example shows a conditional JP Assuming that the carry is set to 1 the statement JP C LABEL W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP i
73. R1 m E n r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL RRC RRC CPIJE LDC LDW LDW LDW R1 IR1 Ir r2 RA r lrr2 RR2 RR1 IR2 RR1 RR1 IML is SRA SRA CPIJNE LDC CALL R1 IR1 Irr r2 RA r2 lrr1 ie p Ir1 r2 RR LDCD LDCI LD LDC R1 bh r1 Irr2 r1 Irr2 R2 R1 i Bl M r1 Irr2 xs X F SWAP SWAP LDCPD LDCPI CALL CALL LDC R1 IR1 r2 lrr1 r2 Irr1 IRR1 S DA1 r2 1171 xs E NIBBLE A EXIT SAMSUNG ELECTRONICS 9 53 8419 UM REV3 00 6 Instruction Set ___ j j J NN SAMSUNG ELECTRONICS 10 x_n 53 8419 UM REV3 00 6 Instruction Set 6 5 Condition Codes The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes 0 2 1 2 0 i Z Mom TERI UGE om uE Unsigned less than or equal 00820 NOTE 1 It indicate condition codes which are related to two different mnemon
74. Refer to Ex 2 below If you want to use P3 as Normal I O you must set LPOT register appropriately Refer to Ex 1 below For example 1 LD LPOT 00000000B P3 0 P3 3 is Normal I O 2 LD LPOT 01001111B P3 0 P3 3 is LCD port For more detail please refer to page 9 16 SAMSUNG ELECTRONICS 4 27 Lm 53 8419 UM REV3 00 4 Control Registers 4 1 27 PACONH Port 4 Control Register High Byte FOH Set 1 Bank0 Bit Identifier 7 6 5 4 3 2 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 7 COM7 SEG19 Configration Bits Fo r mumoewnpuup Push pull output mode N channel open drain output 5 4 P4 6 COM6 SEG18 Configration Bits Fo 1 Pustput ouput mode 3 3 P4 5 COM5 SEG17 Configration Bits Fo r mumwewmpdu 1 0 P4 4 COM4 SEG16 Configration Bits ofo mame _ Push pull output mode N channel open drain output NOTE If you want to use P4 as LCD port you must set LPOT register appropriately Refer to Ex 2 below If you want to use P4 as Normal I O you must set LPOT register appropriately Refer to Ex 1 below For example 1 LD LPOT 00000000B P4 4 P4 7 is Normal I O 2 LD LPOT 01001111B P4 4 P4
75. Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON SAMSUNG ELECTRONICS 8 1 a 53 8419 UM REV3 00 8 RESET and Power Down 8 1 2 Hardware Reset Values Table 8 1 8 2 and 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values e 1 0 shows the reset bit value as logic one or logic zero respectively e An x means that the bit value is undefined after a reset e Adash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 53 841 8 8418 8419 8419 Set 1 TID values after RESET ICI SESERESERERERERER FwmerBemworegse moon 208 o o o o o o Basic mer convoi register ercon 24 o o o o CexCoworgse 22 o o o ras 218 D x x x mgsepomeo PResistr pointers Re zs we o 9 Hmemeremesrgse ma 20 o o o o o Ssemmoergse ze o o x mgserpsepome PP 223 SAMSUNG ELECTRO
76. System TEL 82 31 223 661 1 FAX 82 331 223 6613 E mail openice aijisystem com URL http www aijisystem com H SK 1200 Seminix TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com SAMSUNG ELECTRONICS eux OTP MTP Programmer Writer _ SPW uni Single OTP MTP FLASH Programmer Download Upload and data edit function PC based operation with USB port Full function regarding OTP MTP FLASH MCU programmer Read Program Verify Blank Protection Fast programming speed 4Kbyte sec Support allof SAMSUNG OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC New devices will be supported just by adding device files or upgrading the software SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com AS pro On board programmer for Samsung Flash MCU Portable amp Stand alone Samsung OTP MTP FLASH Programmer for After Service Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices HEX file download via USB port from PC Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second Internal large buffer memory 118M Bytes Driver software run under various O S Windows 95 98 2000 XP Full function regarding OTP MTP programme
77. The 53 8418 5 embedded 8K byte memory respectively has one operating feature as below e Tool Program Mode S3F8418X S3F8419X e User Program Mode 53 8419 Only 20 1 1 Tool Program Mode The 6 pins are connected to a programming tool and programmed by Serial OTP MTP Tools SPW2plus single programmer or GW PRO2 gang programmer In case of S3F8418X the 12 5V programming power is supplied into the Vpp Test pin In case of SSF8419X the The same voltage of Vdd is supplied into the Vpp Test pin The other modules except flash memory module are at a reset state This mode doesn t support sector erase but chips erase and two protection modes Hard lock protection Read protection Table 20 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming Serial data pin output when reading Input when writing Input and push pull output port can be assigned 4 44 pin 10 42 pin Serial clock pin input only pin 9 44 pin Power supply pin for flash ROM cell writing 15 42 pin indicates that MTP enters into the writing mode When 12 5 V S3F84I8X Vdd SSF8419X is applied MTP is in writing mode 12 44 pin aud 18 42 up 5 6 44 pin VDD VSS VDD VSS Et 42 pin EZ Logic power supply pin SAMSUNG ELECTRONICS 20 1 a 53 8419 UM REV3 00 20 Embedded Flash Memory Interface Table 20 2 Comparison of S3F8418X F84I9X and S3C8418X C8419X Features 53 8418 8419 53 8418 8419
78. When the sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the interrupt pending bit If interrupts match capture or overflow are enabled the pending bit is cleared automatically by hardware SAMSUNG ELECTRONICS 12 4 eux 53 8419 UM REV3 00 12 16 bit Timer 1 0 1 Timer 1 Control Register T1CONO E8H Set 1 Bank 1 R W T1CON1 E9H Set 1 Bank 1 R W ve 2 Timer 1 clock source selection bit Timer 1 overflow interrupt enable bit 000 fxx 1024 001 fxx 256 0 Disable overflow interrupt 010 fxx 64 1 Enable overflow interrrupt 011 fxx 8 100 fxx Timer 1 match capture interrupt enable bit 101 External clock falling edge 0 Disable interrupt 110 External clock rising edge 1 Enable interrrupt 111 Counter sto P Timer 1 counter clear bit 0 No effect 1 Clear counter Auto clear bit Timer 1 operating mode selection bit 00 Interval mode 01 Capture mode capture on rising edge OVF can occur 10 Capture mode capture on falling edge OVF can occur 11 PWM mode NOTE Interrupt pending bits are located in TINTPND register Figure 12 1 Timer 1 0 1 Control Register T1CONO 1 SAMSUNG ELECTRONICS 12 5 ea 53 8419 UM REV3 00 12 16 bit Timer 1 0 1 Timer A Timer 1 Pending Register TINTPND Set 1 Bank 1 R W must keep always 0 Timer 1 1 overflow interrupt pending bi
79. a valid stop bit is received SAMSUNG ELECTRONICS 15 13 x_n S3F8419_UM_REV3 00 15 UART 15 2 4 2 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications 1 Set all S8C8418X F8418X 8419X F8419X devices masters and slaves to UART mode 2 with parity disable 2 Write the MCE bit of all the slave devices to 1 3 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 2 1 Next bytes data 9th bit 0 4 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex 53 841 8 8418 8419 8419 Interconnect RxD RxD TxD RxD TxD RxD Master Slave 1 Slave 2 Slave 53 8419 8419 53 8419 8419 3C8419X F8419X 3C8419X F8419X S3C8418X F8418X S3C8418X F84l8X S3C8418X F8418X S3C8418X F8418X Figure 15 9 Connection Example for Multiprocessor Serial Data Communications SAMSUNG ELECTRONICS 15 14 eux 53 8419 UM REV3 00 16 A D Converter A D Converter 16 1 Overview The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10
80. affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00 gt Register 41H register 02H 6FH register 42H 6FH If the general register 00H contains the value 42H and the register 42H the value 6FH the statement POPUD 02H 200H loads the contents of the register 42H into the destination register The user stack pointer is then decremented by one leaving the value 41H SAMSUNG ELECTRONICS 6 63 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 49 POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst lt src IR lt IR 1 The POPUI instruction is used for user defined stacks the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 00H gt Register 02H register 01 70H register 02H 70H If the general register OOH contains the value 01H and the register 01H the value 70H the statement POPUI 02H 900H loads the value 70H into the destination general register 02H user stack poin
81. as COMO COMS ADO ADS Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Alternatively P1 0 P1 5 can be used as INTO INT3 TAOUT TACK TACAP 100 1 T1CK1 T1CAP1 AD5 AD6 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P2 0 P2 7 can be used ADC4 ADC7 SI TTCAPO TTOUTO T1CK0 SEGO SEG3 SO SCK RxD TxD TBPWM PWM Bit programmable port input or output mode selected by software input or push pull N channel open drain output Software assignable pull up Alternately P3 0 P3 7 can be used as SEG4 SEG11 Bit programmable port input or output mode selected by software input or push pull output N channel open drain output Software assignable pull up Alternatively P4 0 P4 5 can be used as SEG12 SEG19 COM4 COM7 SAMSUNG ELECTRONICS 9 1 Lm 53 8419 00 9 I O Ports 9 2 Port Data Registers Table 9 2 gives you an overview of the register locations of all seven S3C8418X F8418X 8419X F8419X I O port data registers Data registers for ports 0 1 2 3 and 4 have the general format shown in Table 9 2 Table 9 2 Port Data Register Summary Port 0 data register Set 1 Bank 0 Port 1 data register Set 1 Bank 0 Port 3 data register 2H Set 1 Bank 0 Port 4 data register EAH m a SAMSUNG ELECTRONICS 9 2 ea 53 8419 UM REV3 0
82. bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 88116 0 src 3 6 07 r0 Rb opc src b 1 dst 3 6 07 Rb ro NOTE In the second byte of the 3 byte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit Examples Given R1 07H and register 01H BOR R1 01 1 gt 1 07H register 01H 03H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example the destination working register R1 contains the value 07H 000001 11B and the source register 01H the value 03H 0000001 1B The statement BOR R1 01H 1 logically ORs bit one of the register 01H source with bit zero of R1 destination This leaves the same value 07H in the working register R1 In the second example the destination register 01H contains the value 0000001 1B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of the register 01H destination with bit zero of R1 source This leaves the value 07H in the register 01H SAMSUNG ELECTRONICS 6 21 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 10 BTJRF Bit Test Jump Relative on
83. data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH 1100 0000 LCD Data Register Area NOTE There is no page lin 53 8418 8418 Figure 2 13 Common Working Register Area SAMSUNG ELECTRONICS 2 16 a 53 8419 UM REV3 00 2 Address Spaces Example 2 4 Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 OC2H 40H Invalid addressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H lt the value in location 40H Example 2 45H i Invalid addressing mode Use working register addressing instead SRP 0COH ADD 45H R3 C3H R3 45H 2 4 2 4 bit Working Register Addressing Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address e high order bit of the 4 bit address selects one of the regi
84. drain output Figure 9 10 Port 3 Low Byte Control Register PSCONL 9 15 9 I O Ports 53 8419 UM REV3 00 9 I O Ports Example 9 3 make as Normal 1 0 or Alternative function ORG 0100H Reset address DI LD LPOT 00H P3is normal I O or alternative function LD P3CONH 00H is input mode LD P3CONL 00H is input mode LD P3CONH 55H is input mode with pull up LD P3CONL 55H is input mode with pull up LD P3CONH 0AAH P3is Push pull output mode LD P3CONL 0AAH is Push pull output mode LD P3CONH 0FFH is N channel open drain output LD P3CONL 0FFH is N channel open drain output LPOT 4FH P3is LCD port P3CONH 0AAH use as LCD port P3CONH register value doesn t care P3CONL 0AAH use as LCD port P3CONL register value doesn t care SAMSUNG ELECTRONICS 9 16 eux 53 8419 UM REV3 00 9 I O Ports 9 2 5 Port 4 Port 4 is a 8 bit I O port that you can use two ways e General purpose digital I O e Alternative function SEG12 SEG19 COM4 COM7 Port 4 is accessed directly by writing or reading the port 4 data register P4 at location E4H in set 1 bank 0 9 2 5 1 Port 4 Control Register P4CONL Port 4 has two 8 bit control registers PACONH for 4 4 4 7 and P4CONL for P4 0 P4 3 A reset clears the PACONH and P4CONL registers to OOH configuring all pins to input mode You use control registers settings
85. dst dst 2 4 DO R 4 01 IR Given Register 00H register 02H register OBCH and 1 SRA OOH gt Register 00H OCD 0 SRA 02H gt Register 02H 03H register 03H ODEH 0 In the first example if the general register 00H contains the value 9AH 10011010B the statement SRA 00H shifts the bit values in the register OOH right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in the destination register OOH SAMSUNG ELECTRONICS 6 78 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 64 SRP SRPO SRP1 Set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples src src src If src 1 1 and src 0 0 then RPO 3 7 src 3 7 If src 1 0 and src 0 1 then RP1 3 7 src 3 7 If src 1 0 and src 0 0 then RPO 4 7 src 4 7 3 lt 0 RP1 4 7 lt src 4 7 RP1 3 lt 1 The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src opc src 2 4 31 IM The statement SRP 40H sets the
86. dst src IR IR 1 dst lt src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Opc dst src 3 8 82 IR R Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H gt Register 02H register 01 05H register 02H 05H If the user stack pointer the register 00H for example contains the value 03H the statement PUSHUD 200H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer SAMSUNG ELECTRONICS 6 66 eux 53 8419 00 6 Instruction Set 6 6 52 PUSHUI Push User Stack Incrementing PUSHUI Operation Flags Format Example dst src IR lt IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Opc dst src 3 8 83 IR R Given Register 00H 03H register 01H 05H and register 04H 2AH
87. e Start bit 0 e 8 data bits LSB first e Programmable 9th data bit or parity bit e Stop bit 1 lt In parity disable mode PEN 0 gt The 9th data bit to be transmitted can be assigned a value of 0 or 1 by writing the TB8 bit UARTCON 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 x 16bit BRDATA 1 clock frequency lt In parity enable mode PEN 1 gt The 9th data bit to be transmitted can be an automatically generated parity of 0 or 1 depending on a parity generation by means of TB8 bit UARTCON 3 When receiving the received 9th data bit is treated as a parity for checking receive data by means of the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 x 16bit BRDATA 1 clock frequency 15 2 3 1 Mode 2 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 2 9 bit UART by setting UARTCON bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 0 if you don t use a parity mode If you want to use the parity enable mode select the parity bit to be transmitted by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 1 3 Write transmission data to the shift register UDATA F5H to start the transmit operation 15 2 3 2 Mode 2 Recei
88. lower 2 bits of the PWMDATAL counter can be used to modulate the stretch cycle To control the stretching of the PWM output duty cycle at specific intervals the lower 2 bits of PWMDATAL counter value is compared with the PWMDATAL 1 0 SAMSUNG ELECTRONICS 13 1 a 53 8419 00 13 10 bit PWM Pulse width Modulation 13 2 1 2 PWM Data and Extension Registers PWM duty data registers located in Set 1 Bank1 at address F3H F4H determine the output value generated by each 10 bit PWM circuit To program the required PWM output you load the appropriate initialization values into the 8 bit reference data register PWMDATAH 7 0 and the 2 bit extension data register PWMDATAL 1 0 To start the PWM counter or to resume counting you set PWMCON 2 to 1 A reset operation disables all PWM output The current counter value is retained when the counter stops When the counter starts counting resumes at the retained value 13 2 1 3 PWM Clock Rate The timing characteristics of PWM output is based on the fOSC clock frequency The PWM counter clock value is determined by the setting of PWMCON 6 7 Table 13 1 PWM Control and Data Registers PWMDATAH 7 0 F3H Set 1 Bank 1 8 bit PWM basic cycle frame value PWM data registers PWMDATAL 1 0 Set 1 Bank 1 2 bit extension stretch value PWM control registers PWMCON F5H Set 1 Bank 1 EM pouner stop and PWM counter clock settings 13
89. mode 2 with the parity disable mode In mode 2 9 data bits are received The 9th bit value is written to RB8 UARTCON 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the bit in the UARTCON registers When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data 15 2 4 1 Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9th bit is 1 and in a data byte it is O The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless
90. must be met Interrupt processing must be globally enabled El 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence 1 2 3 4 Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request SAMSUNG ELECTRONICS 5 17 eu S3F8419_UM_REV3 00 5 Interrupt Structure 5 15 Generating interrupt Vector Addresses The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence 1 2 6 Push the program counter s low byte va
91. r e s eee 1 s 0 IRQO gt IRQ1 Undefined 1 IRQ1 gt IRQO gt gt Group B gt gt 0 IRQ2 gt IRQ3 IRQ4 B gt A gt C 1 IRQ3 IRQ4 gt IRQ2 C gt A gt B __ Subgroup B gt gt 0 IRQ3 gt IRQ4 A gt C gt B 1 IRQ4 gt IRQ3 Undefined Group C 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 Figure 5 8 Interrupt Priority Register IPR 5 14 S3F8419_UM_REV3 00 5 Interrupt Structure 5 12 Interrupt Request Register IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs
92. register 03H OAH SBC 01H 8AH gt Register 01H 95H C S and V 1 In the first example if the working register R1 contains the value 10H and the register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in the register R1 SAMSUNG ELECTRONICS 6 76 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 62 SCF Set Carry Flag SCF Operation C lt 1 The carry flag C is set to logic one regardless of its previous value Flags C Setto 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to 1 SAMSUNG ELECTRONICS 6 77 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 63 SRA Shift Right Arithmetic SRA Operation Flags Format Examples dst dst 7 lt dst 7 C lt dst 0 dst n lt dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into the bit position 6 C Setifthe bit shifted from the LSB position bit zero was 1 Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex
93. reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed SAMSUNG ELECTRONICS 8 7 eux 53 8419 UM REV3 00 9 I O Ports I O Ports 9 1 Overview The S8C8418X F8418X 8419X F8419X microcontroller has five bit programmable ports PO P4 This gives a total of 34 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required Table 9 1 gives you a general overview of the S3C8418X F8418X 84l9X F8419X I O port functions Table 9 1 S3C84I8X F8418X 8419X F8419X Port Configuration Overview Configuration Options Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Alternately P0 0 P0 3 can be used
94. src Examples 03H OAH ADC R1 R2 gt ADC R1 R2 gt ADC 01H 02H gt ADC 01H 02H gt ADC 11H gt SAMSUNG ELECTRONICS 6 13 179 53 8419 UM REV3 00 6 Instruction Set 6 6 2 ADD Add ADD dst src Operation dst lt dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 Set if a from the low order nibble occurred Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 02 r r 03 r Ir src dst 3 6 04 R R 05 R IR dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH ADD R1 R2 gt Rl 15H R2 03H ADD R1 R2 gt R1 1 R2 03H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01 2BH register 02H 03H ADD 01H 25H Register 01 46H In the first example the destination working register R1 co
95. successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH ADDATAL registers where it can be read The ADC module enters an idle state Remember to read the contents of ADDATAH and ADDATAL before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the ADC does not use sample and hold circuitry it is important that any fluctuations in the analog level at the ADCO ADCT input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to circuit noise will invalidate the result SAMSUNG ELECTRONICS 16 1 Lm 53 8419 UM REV3 00 16 A D Converter 16 2 1 A D Converter Control Register ADCON The A D converter control register ADCON is located in set1 bank 0 at address F7H ADCON is read write addressable using 8 bit instructions only But the EOC bit ADCON 3 is read only ADCON has four functions Bits 6 4 select an analog input pin ADCO ADC7 e Bit3 indicates the end of conversion status of the A D conversion e Bits 2 1 select a conversion speed
96. the stack as shown in Figure 2 18 High Address Top of gt stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 18 Stack Operations 2 5 2 User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations 2 5 3 Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register After a reset the SP value is undetermined Because only internal memory space is implemented in the S3C8418X F8418X C8419X F8419X the SPL must be initialized to an 8 bit value the range 0 SAMSUNG ELECTRONICS 2 21 Lm 53 8419 UM REV3 00 2 Address Spaces Example 2 5 Standard Stack Operations Using PUSH and The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions SPL SPL lt Normally the SPL is set to OFFH by the initialization routine address address address address R3 lt Stack address OFBH lt Stack address OFCH RPO lt Stack address OFDH lt Stack address OFEH SAMSUN
97. to select input or output mode push pull Open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 4 control registers must also be enabled in the associated peripheral module Port 4 Control Register High Byte PACONH Set1 R W Reset value 00 7 6 P4 7 COM7 SEG19 Configuration Bits 0 0 2 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P4 6 COM6 SEG18 Configuration Bits 0 0 2 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P4 5 COM5 SEG17 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P4 4 COM4 SEG16 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output Figure 9 11 Port 4 High Byte Control Register PACONH SAMSUNG ELECTRONICS 9 17 Lm 53 8419 UM REV3 00 9 I O Ports Port 4 Control Register Low Byte PACONL Set1 R W Reset value 00 7 6 P4 3 BUZ SEG15 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P4 2 SEG14 Configuration Bits 0 0 Input mode 0 1 Input mode
98. value left one bit position leaving the new value 55H 01010101B and setting the carry C and the overflow V flags SAMSUNG ELECTRONICS 6 70 e 53 8419 UM REV3 00 6 Instruction Set 6 6 56 RLC Rotate Left through Carry RLC Operation Flags Format Examples dst dst 0 C C lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C and the initial value of the carry flag replaces bit Zero 7 0 j Set if the bit rotated from the most significant bit position bit 7 was 1 Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Set if arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 4 11 IR Given Register 00H OAAH register 01H 02H and register 02H 17H C 0 RLC OOH gt Register 00H 54H 1 RLC 801 gt Register 01H 02H register 02H 2EH C 0 In the first example if the general register OOH has the value OAAH 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of the regis
99. while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 R ve e 4 RQ0 IRQ2 IRQ3 IRQ IRQ5 IRQ7 RQ6 Interrupt level request pending bit 0 IRQ interrupt is not pending 1 IRQ interrupt is pending Figure 5 9 Interrupt Request Register IRQ SAMSUNG ELECTRONICS 5 15 a S3F8419_UM_REV3 00 5 Interrupt Structure 5 13 Interrupt Pending Function Types 5 13 1 Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine 5 13 2 Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C8418X F8418X C8419X F841I9X interr
100. with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P4 1 SEG13 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P4 0 SEG12 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output Figure 9 12 Port 4 Low Byte Control Register P4CONL SAMSUNG ELECTRONICS 9 18 ea 53 8419 UM REV3 00 9 I O Ports Example 9 4 To make P4 as Normal I O or Alternative function ORG 0100H DI LD LPOT 00H LD P4CONH 00H LD P4CONL 00H LD P4CONH 55H LD P4CONL 55H LD P4CONH 0AAH LD P4CONL 0AAH LD P4CONH 0FFH LD P4CONL 0FFH P4CONH 0AAH P4CONL 0AAH SAMSUNG ELECTRONICS Reset address is normal I O or alternative function P4 is input mode P4 is input mode P4 is input mode with pull up P4 is input mode with pull up P4 is Push pull output mode P4 is Push pull output mode P4 is N channel open drain output P4 is N channel open drain output P4 is LCD port If you use as LCD port P3CONH register value doesn t care If you use as LCD port register value doesn t care 9 19 ITT 53 8419 UM REV3 00 10 Basic Timer Basic Timer 10 1 Overview 10 1 1 Basic Timer BT You can use the basic timer BT in two different ways e Asa watchdog timer to provide an automatic rese
101. 0 9 I O Ports 9 2 1 Port 0 Port 0 is 4 bit I O port that you can use two ways e General purpose digital I O e Alternative function ADO AD3 Port 0 is accessed directly by writing or reading the port 0 data register PO at location EOH in set 1 bank 0 9 2 1 1 Port 0 Control Register POCON Port 0 has one 8 bit control registers POCON for 0 A reset clears the POCON registers to configuring all pins to input modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 0 control registers must also be enabled in the associated peripheral module Port 0 Control Register Low Byte POCON E6H Set1 R W Reset value 00H 7 6 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode AD3 input 5 4 P0 2 AD2 COM2 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADC2 input 3 2 PO 1 ADC1 COM1Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADC1 input 1 0 P0 0 ADCO COMO Configuration Bits 0 0 Input mode 0 1 2 Input mode w
102. 0 SEG4 AD3 COM3 P0 3 AD 2 COM2 P0 2 AD 1 COM 1 PO 1 AD0 COM0 P0 0 AVss AVref P2 7 SEG3 TxD P2 6 SEG2 RxD P2 5 SEG1 SCK P2 4 SEG0 SO P2 3 AD7 SI 53 8419 8419 Pin Assignment 42 pin SDIP 1 8 53 8419 UM REV3 00 1 Product Overview 1 6 Pin Descriptions Table 1 1 S3C84lI8X F8418X C8419X F8419X Pin Descriptions Type Bit programmable port input or output mode selected COMO ADCO by software input or push pull output Software P0 0 P0 3 assignable pull up resistor Alternately can be used as ADO AD3 Bit programmable port input or output mode selected by software input or push pull output Software 1 0 1 5 assignable pull up resistor Alternatively can be used as INTO INT3 TAOUT TACK TACAP T1CAP1 T1CK1 T10UT1 AD5 AD6 P2 0 P2 3 Bit programmable port input or output mode selected ADC4 ADC7 by software input or push pull output Software TBWPM PWM assignable pull up d CKO Alternately can be used as ADC4 ADC7 SI TBPWM PWM T1CAPO T1CKO SEGO SEG3 2 4 2 7 SEGO SEGS SO SCK RxD TxD SO SCK RxD TxD COM1 ADC1 COM2 ADC2 COM3 ADC3 INTO INT3 TAOUT TACK TACAP T1CK1 T1CAP1 AD5 T1OUT1 AD6 Bit programmable port input or output mode selected P3 0 P3 7 by software input or push pull N channel open drain SEGA 11 output Software assignable pull up Alternately can be used as SEGA SEG11 Bit programmable port input or output mode sel
103. 00000000b LD BTCON 10100011b Disable Watch dog LD P2CONL 03H Enable TBPWM output LD TBDATAH 80h LD TBDATAL 80h LD TBCON 11101110b Enable interrupt fxx 256 Repeat Duration 6 605ms 10 MHz El MAIN ROUTINE T MAIN TBUN_INT Interrupt service routine SAMSUNG ELECTRONICS 11 12 Lm 53 8419 UM REV3 00 12 16 bit Timer 1 0 1 16 bit Timer 1 0 1 12 1 Overview 53 8418 8418 8419 8419 has two 16 bit timer counters The 16 bit timer 1 0 1 is an 16 bit general purpose timer counter Timer 1 0 1 has three operating modes one of which you select using the appropriate T1CONO T1CON setting is e Interval timer mode Toggle output at T1OUTO T1OUT1 pin e Capture input mode with a rising or falling edge trigger at the T1CAPO T1CAP1 pin e PWM mode T1PWMO T1PWM1 PWM output shares their output port with T1OUTO T1OUT1 pin Timer 1 0 1 has the following functional components e Clock frequency divider fxx divided by 1024 256 64 8 1 with multiplexer e External clock input pin T1CKO T1CK1 e A 16 bit counter T1CNTHO LO T1CNTH1 L1 a 16 bit comparator and two 16 bit reference data register T1DATAHO LO T1DATAH 1 L1 pins for capture input T1 CAPO T1CAP1 or match output TTOUTO T1TOUT1 e Timer 1 0 overflow interrupt IRQ2 vector C6H and match capture interrupt IRQ2 vector generation 1 overflow interrupt IRQ2 vector CAH and match c
104. 00H BFH of the S3C8419X F8419X s two 256 byte register pages S3C8418X F8418X s one 256 byte is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 or 1 you must set the register page pointer PP to the appropriate source and destination values Set 1 Bank 0 Bank 1 CPU and system control m General purpose LCD DATA Register Peripheral and I O us Figure 2 6 Set 1 Set 2 Prime Area Register 53 8419 8419 SAMSUNG ELECTRONICS 2 9 e 53 8419 UM REV3 00 2 Address Spaces CPU and system control General purpose 1 Peripheral and I O LCD data Register Area Figure 2 7 Set 1 Set 2 Prime Area Register S3C8418X F8418X Page 2 SAMSUNG ELECTRONICS 2 10 ea 53 8419 UM REV3 00 2 Address Spaces 2 3 5 Working Registers Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register blo
105. 0100H Reset address DI LD LPOT 00H P2is normal I O or alternative function LD P2CONH 00H P2 is input mode LD P2CONH 0AAH 2 is Push pull output mode LD P2CONH 0FFH P2is TXOUT RXOUT SCK OUT SO OUT LPOT 4FH P2is LCD port P2CONH 0AAH use P2 as LCD port P2CONH register value doesn t care P2PUR 00H P2PUR is disabled when P2 is used as a LCD port SAMSUNG ELECTRONICS 9 13 ea 53 8419 UM REV3 00 9 I O Ports 9 2 4 Port 3 Port is an 8 bit I O port that can be used for general purpose digital The pins are accessed directly by writing or reading the port 3 data register at location E3H in set 1 bank 0 0 7 can serve as inputs outputs push pull or you can configure the following alternative functions e General purpose digital I O e Alternative function SEG4 SEG11 9 2 4 1 Port 3 Control Register P3CONL Port 3 has two 8 bit control registers PSCONH for P3 4 P3 7 and PSCONL for P3 0 P3 3 A reset clears the P3CONH and P3CONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull Open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port 3 Control Register High Byte EEH Set
106. 1 Bit Identifier 7 6 5 4 3 2 0 0 0 0 0 0 0 RESET Value 0 Read Write _ _ _ R W R W R W _ R W Addressing Mode Register addressing mode only 7 4 Not used for the 53 84 8 841 8 8419 8419 must keep always 0 3 Main System Oscillator Control Bit Main System Oscillator RUN 1 System Oscillator STOP 2 Sub System Oscillator Control Bit Sub system oscillator RUN 1 Sub system oscillator STOP Not used for the S3C84l8X F8418X C8419X F8419X must keep always 0 0 System Clock Selection Bit lt Main oscillator select 1 Subsystem oscillator select SAMSUNG ELECTRONICS 4 17 ea 53 8419 UM REV3 00 4 Control Registers 4 1 17 POCON Port 0 Control Register High Byte E6H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 3 AD3 COMG Configration Bits E Input mode Input mode with pull up ES Push pull output mode Alternative function mode AD3 input 5 4 P0 2 AD2 COM 2 Configration Bits Input mode Input mode with pull up Push pull output mode Alternative function mode AD1 input NOTE If you want to use PO as a LCD port you must set LPOT register appropriately Refer to Ex 2 below If you want to use PO as a Normal I O or Alternative function ADCO ADC3 you must set LPOT register appropriately Refer to Ex 1 below For example 1 LD L
107. 1 Bank0 R W Reset value 00 7 6 P3 7 SEG11 Configuration Bits 0 0 Input mode 0 1 2 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P3 6 SEG10 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P3 5 SEG9 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P3 4 SEG8 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output Figure 9 9 Port 3 High Byte Control Register P3CONH SAMSUNG ELECTRONICS 9 14 e 53 8419 UM REV3 00 SAMSUNG ELECTRONICS Port Control Register Low Byte Set1 R W Reset value 00 7 6 P3 3 SEG7 Configuration Bits 0 0 2 Input mode 0 1 Input modewith pull up 1 0 Push pull output mode 11 N channel open drain output 5 4 P3 2 SEG6 Configuration Bits 0 0 2 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P3 1 SEG5 Configuration Bits 0 0 2 Input mode 0 1 Input modewith pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P3 0 SEG4 Configuration Bits 0 0 2 Input mode 0 1 Input modewith pull up 1 0 Push pull output mode 1 1 N channel open
108. 1 SEG13 P4 0 SEG12 P3 7 SEG11 P3 6 SEG10 P3 5 SEG9 P3 4 SEG8 P3 3 SEG7 P3 2 SEG6 P3 1 SEG5 P3 0 SEG4 AD3 COM3 PO 3 AD2 COM2 P0 2 AD1 COM1 PO 1 Xin ADO COMO PO 0 TEST AVss XTin AVref XTout P2 7 SEGS TxD nRESET P2 6 SEG2 RxD TBPWM T1CKO P2 0 P2 5 SEG1 SCK PWM T1CAPO P2 1 P2 4 SEG0 SO T1OUTO ADA P2 2 P2 3 AD7 SI O OI N INT3 T1OUT1 P1 3 VDD vss Xout 1351008 Nid Figure 23 5 42 Pin Connector Pin Assignment for 8419 Target Board Target System J101 2 5 Q Q o o 2 5 5 5 2 S 5 Figure 23 6 TB8419 Adapter Cable for 44pin Connector Package SAMSUNG ELECTRONICS ex Third parties for development tools SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system with an OTP MTP programmer In Circuit Emulator for SAM8 family e OPENice i500 e SmartKit SK 1200 OTP MTP Programmer e SPW uni e AS pro e US pro e GW PRO2 8 gang programmer Development Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools 8 bit In Circuit Emulator OPENice i500
109. 1 ms TBDATAH 40 ms 1 ms 40 TBDATAL 1 e Set P2 0 to TBPWM mode ORG 0100H Reset address DI LD TBDATAH 40 1 Set40ms LD TBDATAL 1 Setany value except OOH LD TBCON 00010001B Clock Source lt fxx 4 Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop T FF high P2CONL 03H Set P2 0 to TBPWM mode PULSE OUT TBCON 00000101B Start Timer B operation to make the pulse at this point After the instruction is executed 0 75 ms is required before the falling edge of the pulse starts SAMSUNG ELECTRONICS 11 10 x_n 53 8419 UM REV3 00 11 8 bit Timer A B Example 11 3 Using the Timer A ORG 0000h VECTOR OCOh TAMC INT VECTOR OC2h TAOV INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt SYM LD IMR 00000010b Enable IRQ1 interrupt LD SPL 00000000b LD BTCON 10100011b Disable watch dog LD P1CONL 0ABH Enable TAOUT output LD TADATA 80h LD TACON 01001010b M Match interrupt enable 6 55 ms duration 10 MHz x tal El MAIN ROUTINE TAMC_INT Interrupt service routine TAOV_INT Interrupt service routine IRET END SAMSUNG ELECTRONICS 11 11 Lm 53 8419 UM REV3 00 11 8 bit Timer A B Example 11 4 Using the Timer B ORG 0000h VECTOR OBEh TBUN INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt LD IMR 00000001b Enable IRQO interrupt LD SPL
110. 1CONO Timer 1 0 Control Register E8H Set 1 Bank 4 37 4 1 40 T1CON1 Timer 1 1 Control Register E9H Set 1 Bank 4 38 4 1 41 TACON Timer A Control Register E1H Set 1 1 4 39 4 1 42 TBCON Timer B Control Register DOH 1 4 40 4 1 43 TINTPND Timer A Timer 1 Interrupt Pending Register EOH Set 1 1 4 41 4 1 44 UARTCON UART Control Register F6H Set 1 0 4 42 4 1 45 UARTPND UART Pending and Parity Control Set 1 Bank0 4 44 4 1 46 WTCON Watch Timer Control Register F8H Set 1 Bank1 4 45 5 INTERRUPT STRUCTURE 5 1 NETS UEM 5 1 1 Levels 5 1 Se onde nomade 5 1 NECESITE 5 1 5 2 Interrupt TYPOS sten u ri u dea u d 5 2 5 3 S3C8418X F8418X C8419X F8419X Interrupt Structure sss 5 4 5 4 Interrupt Vector Addresses 5 6 5 5 Enable Disable Interrupt Instructions El D enm 5 8 5 6 System Level Interrupt Control Registers U ener ennt enne 5 8 5 7 Interrupt Processing Control Points
111. 2 1 4 PWM Function Description The PWM output signal toggles to Low level whenever the 8 bit counter matches the reference data register PWMDATAH If the value in the PWMDATAH register is not zero an overflow of the 8 bits of counter causes the PWM output to toggle to High level In this way the reference value written to the reference data register determines the module s base duty cycle The value in the lower 2 bits of PWMDATAL counter is compared with the extension settings in the 2 bit extension data register PWMDATAL 1 0 This lower 2 bits of counter value together with extension logic and the PWM module s extension data register is then used to stretch the duty cycle of the PWM output The stretch value is one extra clock period at specific intervals or cycles see Table 12 2 If for example the value in the extension PN MDATAH register is 00B and PWMDATAL register is 01B the 2nd cycle will be one pulse longer than the other 3 cycles If the base duty cycle is 50 96 the duty of the 2nd cycle will therefore be stretched to approximately 5196 duty For example if you write 10B to the extension data register all odd numbered pulses will be one cycle longer If you write 11H to the extension data register all pulses will be stretched by one cycle except the 4th pulse PWM output goes to an output buffer and then to the corresponding PWM output pin In this way you can obtain high output resolution at high frequencies
112. 2 pin SDIP SAMSUNG ELECTRONICS 3 PIN ASSIGNMENT PAGE 1 14 Open Drain EN Pull up Enable Data LCD Out EN Output Disable Normal Input Figure 1 12 Pin Circuit Type 17 0 7 P4 0 P4 lt Pull up Enable LCD Out EN SEG Output Disable Normal Input Figure 1 13 Pin Circuit Type H 18 2 4 2 7 SAMSUNG ELECTRONICS e 4 REGISTER ARCHITECTURE PAGE 2 5 Bank 0 System and Peripheral Control Registers Register Addressing Mode System and Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode LCD Display Registers Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations Prime Data Registers All Addressing Modes NOTE Page2 s 00H 13H is used for LCD Display Registers Write only Figure 2 3 Internal Register File Organization of 53 8419 8419 SAMSUNG ELECTRONICS Bank 0 System and Peripheral Control Registers Register Addressing Mode General Purpose Data Registers Indirect Register Indexed System and Mode and Stack Operations Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode Prime Data Registers All Addressing Modes LCD Display Registers NOTE 2 5 00H 18H is used for LCD Display Registers Write only Figure 2 4 Internal Regist
113. 3 8419 UM REV3 00 15 UART UART 15 1 Overview The UART block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes e Shift Register I O with baud rate of fxx 16 x 16 bit BRDATA 1 e 8 bit UART mode variable baud rate fxx 16 x 16 bit BRDATA 1 e 9 bit UART mode variable baud rate fxx 16 x 16 bit BRDATA 1 UART receive and transmit buffers are both accessed via the data register UDATA is at address F5H Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received the first data byte will be lost Overrun error In all operating modes transmission is started when any instruction usually a write operation uses the UDATA register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit UARTPND 1 is 0 and the receive enable bit UARTCON 4 is 1 In mode 1 and 2 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCON 4 is set to 1 15 1 1 Programming Procedure To program the U
114. 53 58419 8 bit CMOS Microcontrollers Revision 3 00 December 2013 User s Manual SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS INFORMATION AND SPECIFICATIONS WITHOUT NOTICE Products and specifications discussed herein are for reference purposes only All informa tion discussed herein is provided on an AS IS basis without warranties of any kind This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics No license of any patent copyright mask work trademark or any other intellectual property right is granted by one party to the other party under this document by implication estoppel or otherwise Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply For updates or additional information about Samsung products contact your nearest Samsung office All brand names trademarks and registered trademarks belong to their respective owners 2013 Samsung Electronics Co Ltd All rights reserved SAMSUNG ELECTRONICS Lm Important Notice Samsung Electronics Co Ltd Samsung reserves the right to make changes to the information in this publication at any time without prior notice
115. 6 6 65 STOP Stop Operation rien eile ERE e snes 6 80 6 6 66 SUB 6 81 6 6 67 SWAP Swap 2 6 82 6 6 68 TCM Test Complement under 6 83 5 6 69 TM Test under Mask eerte tenete ee ee Der pe Eta eed 6 84 6 6 70 Wate for Interrupt 6 85 6 6 71 XOR Logical Exclusive 4 U a 6 86 7 1 7 1 7 1 7211 System 7 1 7 1 2 Clock Status During Power Down Modes sse eee neret nnne nennen 7 3 7 1 3 System Clock Control Register 7 4 SAMSUNG ELECTRONICS ex 8 RESET AND POWER DOWIN 8 1 8 1 System eu dread e kusqa qa epu dua ieu aad da 8 1 8 1 1 EDU 8 1 8 1 2 Hardware Reset Values d RUE A gud Ped Eden a 8 2 8 2 Power Down Modes reiecit e wc Ee LESE Ya EROR ice eae a 8 6 8 2 1 Stop Mod iei pa ted ett Fable
116. 6 OR Logical OR OR Operation Flags Format Examples SAMSUNG ELECTRONICS 6 61 dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is 1 otherwise 0 is stored Unaffected Set if the result is 0 cleared otherwise Always cleared to 0 2 S Setif the result bit 7 is set cleared otherwise V D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 42 r r 6 43 r Ir src dst 3 6 44 R R 45 R IR dst src 3 6 46 R IM Given RO 15H R1 R2 01H register 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 3FH 1 2 OR RO R2 gt RO 37H R2 01H register 01H 37H OR 01H gt Register 3FH register 01 37H OR 01 800 gt Register 00H 08H register 01 OR OOH 02H gt Register In the first example if the working register RO contains the value 15H and the register R1 the value the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result 3FH in the destination register RO Other examples show the use of the logical OR instruct
117. A dst Operation dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand is not the result of a valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 06 0 SBC 1 7 F 0 0 9 60 1 1 6 F 1 6 F 66 1 Flags C Set if there was a carry from the most significant bit cleared otherwise see table Z Setif result is 0 cleared otherwise S Setif result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 40 R 4 41 IR SAMSUNG ELECTRONICS 6 32 53 8419 UM REV3 00 6 Instruction Set Example Given The working register RO contains the value 15 BCD the working register R1 contains 27 BCD and the address 27H contains 46 BCD ADD 1 0 C lt 0 lt 0 Bits 4 7 3 bits 0 3 C DA R1 Rl 4 3CH 06 If an addition is performed us
118. ART modules follow these basic steps 1 Configure P2 6 and P2 7 to alternative function RXD P2 6 TXD P2 7 for UART module by setting the P2CONH register to appropriatly value 2 Load an 8 bit value to the UARTCON control register to properly configure the UART module 3 For parity generation and check in UART mode 2 set parity enable bit UARTPND 5 to 1 4 For interrupt generation set the UART interrupt enable bit UARTCON 1 or UARTCON O to 1 5 When you transmit data to the UART buffer write transmit data to UDATA the shift operation starts 6 When the shift operation transmit receive is completed UART pending bit UARTPND 1 or 0 is set to 1 and an UART interrupt request is generated SAMSUNG ELECTRONICS 15 1 Lm 53 8419 UM REV3 00 15 UART 15 1 2 UART Control Register UARTCON The control register for the UART is called UARTCON at address F6H It has the following control functions e Operating mode and baud rate selection e Multiprocessor communication and interrupt control e Serial receive enable disable control e 9th data bit location for transmit and receive operations mode 2 e Parity generation and check for transmit and receive operations mode 2 e UART transmit and receive interrupt control A reset clears the UARTCON value to 00H So if you want to use UART module you must write appropriate value to UARTCON SAMSUNG ELECTRONICS 15 2 eux 53 8419 UM REV3 00
119. All information provided is for reference purpose only Samsung assumes no responsibility for possible errors or omissions or for any consequences resulting from the use of the information contained herein This publication on its own does not convey any license either express or implied relating to any Samsung and or third party products under the intellectual property rights of Samsung and or any third parties Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages Customers are responsible for their own products and applications Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use in applications intended to support or sustain life or for any other application in which the failure of the Samsung product could reasonably be expected to create a situation where personal injury or death may occur Customers acknowledge and agree that they are solely responsible to meet all other legal and regulatory requirements regarding their applications u
120. BUFH ADDATAH ADSBUFL ADDATAL 16 6 0 A D Input MODE Channel ADCO fxx 16 Conversion start A D conversion end EOC check No 8 bit Conversion data 2 bit Conversion data Channel ADC3 fxx 16 Conversion start A D conversion end EOC check No 8 bit Conversion data 2 bit Conversion data 53 8419 UM REV3 00 17 Watch Timer Watch Timer 17 1 Overview Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit1 and bit 6 of the watch timer mode register WTCON 1and 6 to 1 After the watch timer starts and elapses a time the watch timer interrupt is automatically set to 1 and interrupt requests commence in 1 955 ms or 0 125 0 25 and 0 5 second intervals The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to the BUZZER output BUZ pin By setting WTCON 3 WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 1 955 ms High speed mode is useful for timing events for program debugging sequences e Real time and Watch time measurement e Using a main system or subsystem clock source e Buzzer output frequency generator e Timing tests in high speed mode SAMSUNG ELECTRONICS 17 1 ea 53 8419 00 17 Watch Timer 17 1 1 Watch Timer Control Register WTCON R W est w w v v Table 17 1 Watch Timer Contr
121. Before execute the STOP instruction You must set this STPCON register as 101001016 Otherwise the STOP instruction will not be executed SAMSUNG ELECTRONICS 4 35 ea 53 8419 UM REV3 00 4 Control Registers 4 1 38 SYM System Mode Register DEH Set 1 Bit Identifier _ 7 6 5 4 3 2 af 0 0 0 x x x 0 0 RESET Value Read Write _ _ _ R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Not used But you must keep always 0 4 2 Fast Interrupt Level Selection Bits 1 Fast Interrupt Enable Bit Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit note Disable global interrupt processing Enable global interrupt processing NOTE Following a reset you enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O SAMSUNG ELECTRONICS 4 36 Lm 53 8419 UM REV3 00 4 Control Registers 4 1 39 T1CONO Timer 1 0 Control Register E8H Set 1 Bank1 Bit Identifier 7 6 8 4 3 gt 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 1 0 Input Clock Selection Bits Popo ws Pops ojo j 1 0 1 extemal clockfalingedse __ 1 extemalclockrisingedse ___ 4 3 Timer 1 0 Operating Mode Selection Bits fo Interval mode Capture mode Capture on rising edge
122. DC 1 Disable Erasable by LDC ROM Address 003FH LVR on off control bit Not used 0 Disable 1 Enable NOTE The value of unused bits of O3CH 03DH 03EH and must be logic 1 Figure 2 2 Smart Option SAMSUNG ELECTRONICS 2 3 Lm 53 8419 UM REV3 00 2 Address Spaces 2 3 Register Architecture In the S3C8418X F8418X C8419X F8419X implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area set 2 is logically expanded 2 separately addressable register pages page 0 page 1 In case of S3C84I9X F8419X the total number of addressable 8 bit registers is 594 Of these 594 registers 16 bytes are for CPU and system control registers 50 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers 20 bytes are LCD data registers and 492 registers are for general purpose use In case of S3C8418X F8418X the total number of addressable 8 bit registers is 358 Of these 358 registers 16 bytes are for CPU and system control registers 50 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers 20 bytes are LCD data registers and 256 registers are for general purpose use You can always address set 1 register location regardless of whi
123. DD VLC1 VLC2 VLcs VLC4 Vss VDD VLC1 VLC2 Vic3 VLc4 Vss VLCD TET 1 3 VLCD COMO SEGO oV 1 3 VLCD Figure 18 8 LCD Signal Waveforms 1 4 Duty 1 3 Bias SAMSUNG ELECTRONICS 18 8 Lm 53 8419 UM REV3 00 18 LCD Controller Driver SEG2 SEG1 VDD VLC1 VLC2 VLC3 VLC4 Vss VDD Vici 2 Vic3 VLC4 Vss VDD VLC3 VLC4 Vss VDD Vici 2 Vic3 VLC4 Vss VDD Vici 2 Vic3 VLC4 Vss VLCD 1 3 VLCE COMO SEGO OV 1 3 VLCD VLCD Figure 18 9 LCD Signal Waveforms 1 3 Duty 1 3 Bias SAMSUNG ELECTRONICS 18 9 Lm 53 8419 UM REV3 00 19 LOW Voltage RESET LOW Voltage RESET 19 1 Overview 53 8418 8418 8419 8419 can be reset in four ways e by external power on reset e bythe external reset input pin pulled low e bythe digital watchdog timing out e by the Low Voltage reset circuit LVR During an external power on reset the voltage VDD is High level and the nRESET pin is forced Low level The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This brings the S3C8418X F8418X 8419X F8419X into a known operating status To ensure correct start up the user should take that reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency The nRESET pin must be held to Low level for a minimum time interval after the power sup
124. DE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing SAMSUNG ELECTRONICS 3 12 Lm 53 8419 UM REV3 00 3 Addressing Modes 3 7 Relative Address Mode RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE IX Program Memor Address Used PC Value Displacement Current Instruction OPCODE Signed Y U Displacement Value Sample Instructions JR ULT OF FSET Where OFFSET is a value in the range 127 to 12 Figure 3 13 Relative Addressing SAMSUNG ELECTRONICS 3 13 Lm 53 8419 UM REV3 00 3 Addressing Modes 3 8 Immediate Mode IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one wor
125. Decrementing a 6 63 6 6 49 POPUI Pop User Stack Incrementing 6 64 06 6 50 PUSH Push to Stack eret dede a Led deu 6 65 6 6 51 PUSHUD Push User Stack Decrementing ssssssssseeeeneennens 6 66 6 6 52 PUSHUI Push User Stack Incrementing sss 6 67 6 6 53 ROCF Reset Carry Flag nis ned E cde to dire tele Ee EE Le ERE CE 6 68 6 6 54 RE T Return a e patte cider riam pane 6 69 6 6 55 RL Rotate Left cach eae donated tees E aint e perte ke atl eee hee oe eee eee 6 70 6 6 56 Rotate Left through Carry esses ener nennen nnne nnns 6 71 6 657 HR Rotate iiri rede EE eee 6 72 6 6 58 RRC Rotate Right through nnne nnt 6 73 6 6 59 SB0 Select Bank ende rade RR dec e dene ise 6 74 6 6 60 SB1 Select Bank de detained dodi Pr na red dat Du dada adde 6 75 6 6 61 SBC Subtract with 6 76 6 6 62 SCF Set Carty Flag iain tatis ed Deseo ed Neo a Xa esed ELA E 6 77 6 6 63 SRA Shift Right Arithmetic U 6 78 6 6 64 SRP SRPO SRP1 Set Register ana 6 79
126. ELECTRONICS 11 6 Lm 53 8419 UM REV3 00 11 8 bit Timer A B 11 2 4 Timer b PULSE WIDTH CALCULATIONS To generate the above repeated waveform consisted of low period time tLOW and high period time tHIGH When T FF 0 tLOW TBDATAL 1 x 1 fx OH TBDATAL 100H where fx The selected clock tHIGH TBDATAH 1 x 1 fx OH TBDATAH 100H where fx The selected clock When T FF 1 tLOW TBDATAH 1 x 1 fx OH TBDATAH 100H where fx The selected clock tHIGH TBDATAL 1 x 1 fx OH TBDATAL 100H where fx The selected clock To make tLOW 24 us and tHIGH 15 us fOSC 4 MHz fx 4 MHz 4 1 MHz When T FF 0 tLOW 24 us TBDATAL 1 fx TBDATAL 1 x 1 us TBDATAL 23 tHIGH 15 TBDATAH 1 fx TBDATAH 1 x 1 us TBDATAH 14 When T FF 1 tHIGH 15 us TBDATAL 1 fx TBDATAL 1 x 1 us TBDATAL 14 tLOW 24 us TBDATAH 1 fx TBDATAH 1 x 1 us TBDATAH 23 SAMSUNG ELECTRONICS 11 7 ea 53 8419 UM REV3 00 11 8 bit Timer A B Timer B Clock T FF 0 TBDATAL 01 FFH TBDATAH 00H T FF 0 TBDATAL 00H TBDATAH 01 FFH T FF 0 TBDATAL 00H TBDATAH 00H T FF 1 TBDATAL 00H TBDATAH 00H Timer B Clock T FF 1 TBDATAL DFH TBDATAH 1FH T FF 0 TBDATAL DFH TBDATAH 1FH T FF 1 TBDATAL 7FH TBDATAH 7FH T FF 0 TBDATAL 7FH TBDATAH 7FH Figure 11 6 Timer B Output Fl
127. EV3 00 20 Embedded Flash Memory Interface 20 6 Hard Lock Protection User can set Hard Lock Protection by write 0110 in FMCON7 4 If this function is enabled the user cannot write or erase the data in a flash memory area This protection can be released by the chip erase execution in the tool program mode or user program mode In terms of user program mode the procedure of setting Hard Lock Protection is following that Whereas in tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The program procedure in User program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 SetFlash Memory Control Register FMCON to 01100001B 3 Set Flash Memory User Programming Enable Register FMUSR 00000000B Example 20 5 Hard Lock Protection FMUSR 0A5H User Program mode enable FMCON 01100001B Hard Lock mode set amp start FMUSR 0 User Program mode disable SAMSUNG ELECTRONICS 20 13 x_n 53 8419 UM REV3 00 21 Electrical Data Electrical Data 21 1 Overview In this chapter S3C8418X F8418X 8419X F8419X electrical characteristics are presented in tables and graphs The information is arranged in the following order e Absolute maximum ratings e Input output capacitance e D C electrical characteristics electrical characteristics e Oscillation character
128. FFH R1 OAH LD LOOP RO R1 gt Register OAH RO 01H R1 OAH SAMSUNG ELECTRONICS 6 49 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 36 LDB Load Bit LDB dst src b LDB dst b src Operation dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst 60 src 3 6 47 ro Rb src b 1 dst 3 6 47 Rb ro NOTE In the second byte of the instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given RO 06H and general register OOH 05H LDB R0 00H 2 gt RO 07H register 00H 05H LDB 00H 0 RO0 gt 06H register 00H 04H In the first example the destination working register RO contains the value 06H and the source general register OOH the value 05H The statement LD R0 00H 2 loads the bit two value of the 00H register into bit zero of the RO register leaving the value 07H in the register RO In the second example OOH is the destination register The statement LD 00H 0 RO0 loads bit zero of the register RO to the specified bit bit zero of the destination
129. False BTJRF dst src b Operation If src b is a 0 then PC lt PC dst The specified bit within the source operand is tested If it is a the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter Otherwise the instruction following the BTJRF instruction is executed Flags No flags are affected Format NOTE Bytes Cycles Opcode Addr Mode Hex dst src src b 0 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If the working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 SAMSUNG ELECTRONICS 6 22 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 11 BTJRT Bit Test Jump Relative on True BTJRT dst src b Operation If src b is a 1 then PC lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC Otherwise the
130. G ELECTRONICS 2 22 eux 53 8419 UM REV3 00 3 Addressing Modes Addressing Modes 3 1 Overview Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RCinstructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are e Register R e Indirect Register IR e Indexed X e Direct Address DA e Indirect Address IA e Relative Address RA e Immediate IM SAMSUNG ELECTRONICS 3 1 ea 53 8419 UM REV3 00 3 Addressing Modes 3 2 Register Addressing Mode R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File 8 bit Register TES OPERAND i U U U vA OPCODE Register in Register Z i One Operand 47 File Instructio
131. H H LCD common signal output pins System reset pin Pull down resistor connected internally Power input pins ES Main oscillator pins ES NOTE 1 Pin numbers shown in parentheses are for the 44 pin QFP package 2 42 SDIP is only available for S3C84l9X F8419X nRESET TEST VDD VSS Xin Xout SAMSUNG ELECTRONICS 1 10 21 15 16 17 10 4 7 8 1 Product Overview P2 4 P2 7 0 7 4 0 P4 7 P0 0 P0 3 P4 4 P4 7 53 8419 UM REV3 00 1 Product Overview 1 7 Pin Circuits Pull Up Resistor Schmitt Trigger Figure 1 4 Pin Circuit Type B nRESET P Channel Data Out Output N Channel Disable Figure 1 5 Pin Circuit Type C SAMSUNG ELECTRONICS 1 11 ea 53 8419 UM REV3 00 1 Product Overview Pull up Enable Data DECR Pin Circuit Output Type C Disable Figure 1 6 Pin Circuit Type D lt Pull up Pin enable Circuit Type C Port Data Alternative output Output Disable Noise Normal Input Figure 1 7 Pin Circuit Type D 5 P1 0 P1 3 SAMSUNG ELECTRONICS 1 12 Lm 53 8419 UM REV3 00 Pull up Enable Port Data Alternative Output Output Disable SAMSUNG ELECTRONICS Figure 1 8 Pull up Resistor Typical Value 50kQ Pin Circuit Type E 2 2 2 3 1 13 1 Product Overview 53 8419 UM REV3 00 1 Product Overview SEG COM Output Disable Figure 1 9 Pin Circuit Type H 4 SAMSUNG ELECTRO
132. Improve EFT Characteristics 21 12 42 SDIP 600 Package Dimensions 22 1 44 QFP 1010 Package Dimensions eene nennen nnne en 22 2 Development System Configuration ener 23 2 S3F8419X S3F8418X Target Board Configuration 23 3 DIP Switch for Smart Option LULU U tnn nnns 23 6 44 Pin Connector Pin Assignment for TB8419 a 23 7 42 Pin Connector Pin Assignment for 8419 23 8 8419 Adapter Cable for 44pin Connector 23 8 SAMSUNG ELECTRONICS eux Table Number Table 1 1 Table 2 1 Table 2 2 Table 4 1 Table 4 2 Table 4 3 Table 5 1 Table 5 2 Table 5 3 Table 6 1 Table 6 2 Table 6 3 Table 6 4 Table 6 5 Table 6 6 Table 8 1 Table 8 2 Table 8 3 Table 9 1 Table 9 2 Table 13 1 Table 13 2 Table 15 1 Table 17 1 Table 18 1 Table 20 1 Table 20 2 Table 21 1 Table 21 2 Table 21 3 Table 21 4 Table 21 5 Table 21 6 Table 21 7 List of Tables Title Page Number S3C8418X F8418X C84I9X F8419X Pin 1 9 S3C8419X F8419X Register Type Summary sse enne nnne nnne nnns 2 4 S3C8418X F8418X Register Type Summary
133. Interrupt Pending Register P1INTPND EAH Seti R W Reset value 00H 7 4 Not used for S3C84I9X F84I9X 3 P1 3 INT3 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P1 2 INT2 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 P1 1 INT1 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 P1 0 INTO Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Figure 9 4 Port 1 Interrupt Pending Register P1INTPND SAMSUNG ELECTRONICS 9 7 ea 53 8419 UM REV3 00 9 I O Ports Port 1 Interrupt Enable Register P1INT EBH Set1 R W Reset value 00H 4 7 6 P1 3 s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge 5 4 P1 2s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge 3 2 P1 1 s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge 1 0 P1 0 s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Inter
134. Interval Mode match The timer 1 0 module can generate an interrupt the timer 1 0 match interrupt T1INTO belongs to interrupt level IRQ2 and is assigned the separate vector address C4H In interval timer mode a match signal is generated and T1OUTO is toggled when the counter value is identical to the value written to the Timer 1 reference data registers TIDATAHO and T1DATALO The match signal generates a timer 1 0 match interrupt T1INTO vector C4H and clears the counter value The timer 1 1 module can generate an interrupt the timer 1 1 match interrupt T1INT1 T1INT1 belongs to interrupt level IRQ2 and is assigned the separate vector address C8H In interval timer mode a match signal is generated and T1OUTI1 is toggled when the counter value is identical to the value written to the Timer 1 reference data register TIDATAH1 T1DATAL1 The match signal generates a timer 1 1 match interrupt T1INT1 vector C8H and clears the counter value SAMSUNG ELECTRONICS 12 2 eux 53 8419 UM REV3 00 12 16 bit Timer 1 0 1 12 1 1 3 Capture Mode In capture mode for timer 1 0 a signal edge that is detected at the T1CAPO pin opens a gate and loads the current counter value into the timer 1 data registers T1DATAHO T1DATALO for rising edge or falling edge You can select rising or falling edge to trigger this operation The timer 1 0 also gives you capture input source the signal edge at the T1CAPO pin You select
135. LCD port you must set LPOT register appropriately Refer to Ex 2 below If you want to use a P2 as Normal I O or Alternative function SO SCK RxD TxD you must set LPOT register appropriately Refer to Ex 1 below For example 1 LD LPOT 00000000B P2 4 P2 7 is Normal I O or Alternative function SO SCK RxD TxD 2 LD LPOT 01001111B P2 4 P2 7 is LCD port For more detail please refer to page 9 13 SAMSUNG ELECTRONICS 4 23 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 23 P2CONL Port 2 Control Register Low Byte EDH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 AD7 SI Configration Bits Input mode 5 input Alternative function mode Not used Lo ES 1 Push pulloutputmode __ 5 4 P2 2 ADA4 T1OUTO Configration Bits r Memawetndonmode 3 2 P2 1 PWM T1CAPO Configration Bits o mumuertcwoma o uncton moe Notus Pushputlouputmode 1 0 P2 0 TBPWM T1CKO Configration Bits Raga Input mode T1CKO input 1 Alternative function mode T1CKO input Lae EEN Push pull output mode Alternative function mode TBPWM mode SAMSUNG ELECTRONICS 4 24 Lm 53 8419 UM REV3 00 4 Control Registers 4 1 24 P2PUR Port 2 Pull up Resistor Control Register FAH Set 1 Bank0 Bit Identifier 7 6 5
136. Modes Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points to start of working register block Next 2 bit Point to Working Register Pair Register Pair address Program Memory points to or program Data Memory memory or data memory LSB Selects Value used in Instruction OPERAND Program memory access External data memory access External data memory access Indirect Working Register Addressing to Program or Data Memory 53 8419 UM REV3 00 3 Addressing Modes 3 4 Indexed Addressing Mode X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Fig
137. NEXT Next NEXT Operation Flags Format Example Address 1P PC 0120 PC IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 10 OF The following diagram shows an example of how to use the NEXT instruction Before After Address Data 1P PC 0130 Data Address Data 43 Address 44 Address L 45 Address Address Data 43 Address H 01 44 Address L 30 45 Address H 120 130 Routine Memory Memory SAMSUNG ELECTRONICS 6 59 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 45 NOP No Operation NOP Operation No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to affect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 FF Example When the instruction NOP is executed in a program no operation occurs Instead there happens a delay in instruction execution time which is of approximately one machine cycle per each NOP instruction encountered SAMSUNG ELECTRONICS 6 60 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 4
138. NICS 1 14 e 53 8419 UM REV3 00 1 Product Overview Open Drain EN Pull up Enable O Vo LCD Out EN SEG COM Output Disable Input Figure 1 10 Pin Circuit Type H 14 P4 4 P4 7 Open Drain EN Pull up Enable Data LCD Out EN COM Output Disable ADC In EN Normal In ADC In Figure 1 11 Pin Circuit Type H 16 0 0 0 3 SAMSUNG ELECTRONICS 4 15 x_n 53 8419 UM REV3 00 1 Product Overview Open Drain EN Pull up Enable Data LCD Out EN Output Disable Normal Input Figure 1 12 Pin Circuit Type H 17 0 7 P4 0 P4 Pull up Enable LCD Out EN SEG Output Disable Normal Input Figure 1 13 Pin Circuit Type H 18 2 4 P2 7 SAMSUNG ELECTRONICS 1 16 x_n 53 8419 UM REV3 00 2 Address Spaces Address Spaces 2 1 Overview The S3C8418X F8418X C8419X F8419X microcontroller has two types of address space e Internal program memory ROM e Internal register file RAM A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The 53 8419 8419 has an internal 32 Kbyte mask programmable ROM 32 Kbyte Flash ROM and 528 byte RAM The S3C8418X F8418X has an internal 8 Kbyte mask programmable ROM 8 Kbyte Flash ROM and 272 byte RAM SAMSUNG ELECTRONICS 2 1 ea 53 8419 UM REV3 00 2 2 Program Memory ROM 2 Address Spaces Program memory ROM store
139. NICS 8 x_n 53 8419 UM REV3 00 8 RESET and Power Down Table 8 2 S3C8418X F8418X 8419X F8419X Set 1 Bank 0 Register values after RESET oe vex a 3 2 o P se 1 data register P 25 EM 0 o o 2 data register P2 226 o o Jo data register Pa 227 o Jo Port 4 data register 228 O Jo STOP control register 229 EH o o o o o Port 0 control register high byte POCON 230 Jo Location FBH is not mapped Port 1 control register high byte 1 232 o o Port 1 control register low byte PICONL 233 E9H o Port 1 interrupt pending register PIINTPND 234 EAH o o o 0 o 0 Port 1 interrupt control register 235 0 JO O Port 2 control register high byte P2CONH 234 EAH O 0 Port 2 control register low byte 2 235 o Port control register high byte PSCONH 238 o 0 0 o o Port 3 control register low byte PSCONL 239 EH o o o o o o 0 Port 4 control register high byte
140. ON 10100011B Watchdog disable LD P2CONL 00001 100B Configure P2 1 PWM output LD PWMCON 00000110B fOSC 64 counter interrupt enable LD PWMDATAH 80H LD PWMDATAL 0 El Enable interrupt lt lt Main loop gt gt JR t MAIN lt lt Interrupt Service Routines gt gt INT PWM interrupt service routine AND PWMCON 11111110B pending bit clear IRET SAMSUNG ELECTRONICS 13 7 Lm 53 8419 UM REV3 00 14 Serial I O interface Serial I O interface 14 1 Overview Serial I O module SIO can interface with various types of external devices that require serial data transfer The components of each SIO function block are e 8 bit control register SIOCON e Clock selection logic 8 bit data buffer SIODATA e 8 bit presale SIOPS e 3 bit serial clock counter e Serial data I O pins SI SO e External clock input pin SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source 14 1 1 Programming Procedure To program the SIO module follow these basic steps 1 Configure the I O pins at port 2 SO SCK SI by loading the appropriate value to the P2CONL H Register 2 Load an 8 bit value to the SIOCON control register to properly configure the serial I O module In this operation SIOCON 2 must be set to 1 to enable the dat
141. OPENice i500 and SK 1200 for the S8C7 S3C9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options 23 1 1 Target Boards Target boards are available for all the S3C8 S3F8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB8419 8 is a specific target board for the development of application systems using 53 8419 8 23 1 2 Programming Socket Adapter When you program S3F8419X I8X s flash memory by using an emulator or OTP MTP writer you need a specific programming socket adapter for S3F8419X I8 SAMSUNG ELECTRONICS 23 1 ea 53 8419 UM REV3 00 23 Development Tools Development System Configuration IBM PC AT or Compatible Emulator SK 1200 RS 232 USB or R929320 1 USB I 500 RS 232 Target Application System Probe Adapter TB80K9 Target Board EVA Chip Figure 23 1 Development System Configuration SAMSUNG ELECTRONICS 23 2 Lm 53 8419 UM REV3 00 23 Development Tools 23 1 3 8419 18 Target Board The TB80KB target board can be used for development of SSF80K9X and SSF80KBX together But you should be careful to set the memory size to program internal flash memory The TB80KB target board is operated as target CPU with Emulator SK 1200 OPENIce 1 500 TB8419 8 84H5 xx OFFL__ ON 9 04 1 2588 In
142. OVF can occur K EEN Capture mode Capture on falling edge OVF can occur PWM mode 2 Ti 3 er 1 0 Counter Enable Bit No effect 1 Clear the timer 1 0 counter Auto clear bit 1 Timer 1 0 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer 1 0 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt SAMSUNG ELECTRONICS m x_n 53 8419 UM REV3 00 4 Control Registers 4 1 40 1 Timer 1 1 Control Register E9H Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 a O 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 1 1 Input Clock Selection Bits opi oja 1 o 1 EMemalcockfaligedoe __ 1 extemalclockrisingedse ___ 4 3 Timer 1 1 Operating Mode Selection Bits fo Interval mode Capture mode Capture on rising edge OVF can occur K EEN Capture mode Capture on falling edge OVF can occur PWM mode 2 Ti 3 er 1 1 Counter Enable Bit No effect 1 Clear the timer 1 1 counter Auto clear bit 1 Timer 1 1 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer 1 1 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt SAMSUNG ELECTRONICS 4 38 Lm 53 8419 UM REV3 00 4 Contro
143. Offset 3 8 53 8419 UM REV3 00 3 Addressing Modes Register File Tou ru RPO or RP1 RPO or RP1 Selected block RP points Program Memory to st of working OFFSET register OFFSET NEXT 2 Bits 4 bit Working dst src src Register Register Address Point to Working Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory m eee 16 Bits 16 Bits OPERAND Value used in 16 Bits Instruction Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000 are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory SAMSUNG ELECTRONICS 3 9 Lm 53 8419 UM REV3 00 3 Addressing Modes 3 5 Direct Address Mode DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Used Program Memory Upper Address Byte Lower Address Byte dst src or 1 dst src LSB Se
144. P1 AR2 4 SMDS2 5 052 Figure 23 2 S3F8419X S3F8418X Target Board Configuration SAMSUNG ELECTRONICS e Table 23 1 Components of 8419 18 Symbols Usage Description 100 pin connector Connection between emulator and TB8419 8 target board J101 J102 50 pin connector Connection between target board and user application System RESET Push button Generation low active reset signal to 53 8419 8 EVA chip VCC GND POWER connector External power connector for 8419 8 IDLE STOP LED STOP IDLE Display Indicate the status of STOP or IDLE of S3F8419X 8X EVA chip on 819 8 target board Table 23 2 Power Selection Settings for TB84I9 To User Vcc Settings Operating Mode To User SMDS2 or SK 1000 supplies Vpp to the target board evaluation chip and the target system To User SMDS2 or SK 1000 supplies Vpp only to the target board evaluation chip The target system must have a power supply of its own SMDS2 or SK 1000 SAMSUNG ELECTRONICS ex IDLE LED This LED is ON when the evaluation chip S3E8410 is in idle mode STOP LED This LED is ON when the evaluation chip S3E8410 is in stop mode SAMSUNG ELECTRONICS 001 3EH 0 1 SEH 2 3FH 7 CON Ton NOTE Smart option is determined by DIP switch Figure 23 3 DIP Switch for Smart Option Address Switch Function 3EH 1 3EH 0 ON ON I
145. POT 00000000B P0 0 P0 3 is Normal I O or Alternative function ADCO ADC3 2 LD LPOT 01001111B P0 0 P0 3 is LCD port For more detail please refer to page 9 5 SAMSUNG ELECTRONICS 4 18 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 18 P1CONH Port 1 Control Register High Byte E8H Set 1 Bank0 Bit Identifier 7 6 8 4 3 2 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the 53 84 8 841 8 8419 8419 must keep always 0 3 2 P1 5 T1CAP1 AD6 Configration Bits o 0 Input mode 1 1 input 1 Input mode with pull up T1CAP1 input EHE Push pull output mode Alternative function mode AD6 1 0 P1 4 T1CK1 AD5 Configration Bits KEE Input mode T1CK1 input o i Input mode with pull up T1CK1 input EEEU Push pull output mode Alternative function mode AD5 SAMSUNG ELECTRONICS 4 19 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 19 P1CONL Port 1 Control Register Low Byte E9H Set 1 Bit Identifier 7 8 4 2 7 29 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 T1OUT1 INT3 Configration Bits fo Input mode Interrupt input INT3 o i Input mode with pull up Interrupt input INT3 K 0 Push pull output mode Alternative function mode T1OUT1 mo
146. PUSHUI 00H 01H gt Register 04H register 01 05H register 04H 05H If the user stack pointer the register OOH for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer SAMSUNG ELECTRONICS 6 67 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 53 RCF Reset Carry Flag RCF Operation Flags Format Example RCF C 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex 1 4 Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero SAMSUNG ELECTRONICS 6 68 ea 53 8419 UM REV3 00 6 Instruction Set 6 6 54 RET Return RET Operation Flags Format Example PC SP SP lt SP 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement to be executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 10 AF Given SP 00FCH SP 101AH and PC 1234 RET
147. Prescaler ps Prescaler Value 1 SIOPS 1 First Mode Select gt X Figure 14 3 SIO Functional Block Diagram SAMSUNG ELECTRONICS 14 3 Lm 53 8419 UM REV3 00 14 Serial I O interface so Cer X pos pos Y pos oor oos Transmit N Complete Set SIOCON 3 Figure 14 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 Transmit IRQS Complete Set SIOCON 3 Figure 14 5 Serial Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 SAMSUNG ELECTRONICS 14 4 IL 53 8419 UM REV3 00 14 Serial I O interface Shift Clock Data Input Data Output IRQ5 Start 11 Figure 14 6 Serial Timing Receive Only Mode SAMSUNG ELECTRONICS 14 5 x_n 53 8419 UM REV3 00 ORG VECTOR ORG INITIAL LD LD LD LD e LD LD LD LD El SUB_SIO INT_SIO SAMSUNG ELECTRONICS Example 14 1 0000H 00H INT_SIO 0100H SYM 00H BTCON 10100010B CLKCON 00011000B SPL 00H P2CONH 10101111B P2CONL 00101010B SIOCON 00100110B SIOPS 20 SUB_SIO MAIN SIODATA TRANSBUF SIOCON 00001000B SIOCON 11111110 14 6 14 Serial I O interface SIO Global Fast interrupt disable gt SYM Watch dog disable non divided CPU clock SIO setting Enable SIO Interrupt setting baud rate Data transmit routine 1 byte transmission Shift start 8 bit transmit Pending bit clear 5
148. RONICS 5 10 x_n S3F8419_UM_REV3 00 5 Interrupt Structure 5 9 System Mode Register SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing see Figure 5 5 A reset clears SYM 0 to 0 The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W Global interrupt enable bit 0 Disable all interrupts processing 1 Enable all interrupts processing Not used for the S3C8419X F8419X Fast interrupt enable bit 0 Disable fast interrupts processing 1 Enable fast interrupts processing Fast interrupt level selection bits 0 0 1 1 0 0 1 1 Figure 5 5 System Mode Register SYM SAMSUNG ELECTRONICS 5 11 Lm S3F8419_UM_REV3 00 5 Interrupt Structure 5 10 Interrupt Mask Register IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required setting
149. RP point to the working register common area RPO points to addresses COH C7H and RP1 points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Example 2 2 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 9 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 9 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements Example 2 2 Setting the Register Pointers 70H 70H lt 78H 48H no change RP1 48H 0A0H RP1 lt no change RPO OOH lt no change RP1 40F8H no change lt OF8H Register File Contains 32 8 Byt
150. Register P3CONL SAMSUNG ELECTRONICS 20 PORT CONTROL REGISTERS PAGE 9 16 PROGRAMMING TIP To make as Normal I O or Alternative function ORG 0100H Reset address START DI SB1 LD LPOT 00H PSis normal I O or alternative function SBO LD P3CONH 00H P3isinput mode LD P3CONL 00H is input mode LD P3CONH 55H is input mode with pull up LD P3CONL 55H is input mode with pull up LD P3CONH 0AAH is Push pull output mode LD P3CONL 0AAH is Push pull output mode LD P3CONH 0FFH is N channel open drain output LD P3CONL 0FFH is N channel open drain output SB1 LD LPOT 04FH PSisLCD port SBO LD P3CONH 0AAH lf you use as LCD port P3CONH register value doesn t care LD P3CONL 0AAH If you use as LCD port P3CONL register value doesn t care SAMSUNG ELECTRONICS 21 PORT CONTROL REGISTERS PAGE 9 19 PROGRAMMING TIP make P4 as Normal I O or Alternative function ORG 0100H Reset address START DI SB1 LD LPOT 00H SBO LD P4CONH 00H LD P4CONL 00H LD P4CONH 55H LD P4CONL 55H LD P4CONH 0AAH LD P4CONL 0AAH LD P4CONH 0FFH LD P4CONL 0FFH SB1 LD LPOT 4FH SB0 LD P4CONH 0AAH LD P4CONL 0AAH SAMSUNG ELECTRONICS is normal I O or alternative function P4 is input mode P4 is input mode P4 is input mode with pull up P4 is input mode with pull up P4is Push pull output mode P4is Push pull output mode P4is N chann
151. S 24 PNM CONTROL REGISTER PAGE 13 5 PWM Control Register PWMCON F5H R W Reset 00H PWM input clock PWM OVF interrupt pending bit selection bits 0 No interrupt pending 00 fosc 64 0 Clear pending condition when write 01 fosc 8 1 Interrupt pending 10 fosc 2 11 fosc 1 PWM OVF interrupt enable bit 0 Disable interrupt 1 Enable interrupt Not used for S3C8418X F8418X C8419X F8419X PWM counter enable bit 0 Stop counter 1 Start resume countering PWMDATA reload interval selection bit 0 reload from 10bit up counter overflow 1 reload from 8bit PWM counter clear bit up counter overflow 0 No effect 1 Clear the PWM counter Figure 13 3 PWM Control Register PWMCON SAMSUNG ELECTRONICS eux 25 uart baud rate data register PAGE 15 7 Table 15 1 Commonly Used Baud Rates Generated by 16bit BRDATA 225 BRDATAH BRDATAL Baud Rate Oscillation Clock o o 7 m _ oi home o n 4 9 9 m SAMSUNG ELECTRONICS IL 26 Internal A D Conversion Procedure PAGE 16 5 Analog ADCO Input Pin ADC7 S3C8419X F8419X S3C8418X F8418X AVss Vss NOTES 1 The symbol R signifies an offset resistor with a value of from 50 to 100 Q 2 Avref must be tied to Vdd Figure 16 5 Recommended A D Converter Circuit for Highest Absolute Accuracy SAMSUNG ELECTRONICS eux 27 LCD RAM ADDRESS AREA PAGE 18 3 RAM ad
152. S3C8 S3F8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB8419 8 is a specific target board for the development of application systems using SSF8419X 8X programming socket adapter When you program S3F8419X I8X s flash memory by using an emulator or OTP MTP writer you need a specific programming socket adapter for S3F8419X I8X SAMSUNG ELECTRONICS eux Development System Configuration IBM PC AT or Compatible Emulator SK 1200 RS 232 USB or Dessen D I 500 RS 232 Target Application System TB80K9 Target Board EVA Chip Figure 23 1 Development System Configuration SAMSUNG ELECTRONICS eux 8419 8 Target Board The TB80KB target board can be used for development of S3F80K9X and S3F80KBX together But you should be careful to set the memory size to program internal flash memory The TB80KB target board is operated as target CPU with Emulator SK 1200 OPENIce 1 500 v 8419 8 84 5 SK 1200 0PENIce 1 500 ve 8003 0 w J101 J102 RESET 0 T 42SDIP 44QFP In Circuit Emulator EAS 4 8 E N UT R5 30s 20 101 160 1 5 AR1 5 001 00 134 C16 10 90 100110 120 swi 15 J
153. SEG15 LCD display control bit 0 Display off 1 Normal display on Figure 18 4 LCD Mode Control Register SAMSUNG ELECTRONICS 18 4 e 53 8419 UM REV3 00 18 LCD Controller Driver 18 1 4 LCD Port Control Register The LCD port control register is used to control LCD signal pins or normal pins Following a RESET LPOT values are cleared to 0 LCD Port Control Register LPOT F7H SET1 B ANK1 R W SEGO P2 4 selection bit 0 Normal I O port 1 SEG port Not used SEG4 SEG19 and selection bits 000 PO P3 P4 Normal I O SEG1 P2 5 selection bit 010 P3 0 P4 7 Normal I O Others LCD signal pins 0 Normal I O port 100 4 LCD signal pins 1 SEG port 101 P3 0 P3 3 Normal I O Others LCD signal pins 110 P3 0 P3 7 Normal I O Others LCD signal pins 111 P3 0 P4 3 Normal I O Others LCD signal pins SEG2 P2 6 selection bit 0 Normal port 1 SEG port SEG3 P2 7 selection bit 0 Normal I O port 1 SEG port Figure 18 5 LCD Port Control Register SAMSUNG ELECTRONICS 18 5 ea 53 8419 UM REV3 00 18 LCD Controller Driver 18 1 5 LCD Voltage Dividing Resistors 1 5 Bias 1 4 Bias 1 3 Bias 3 8419 8419 3 8419 8419 53 8419 8419 S3C8418X F8418X 3 8418 8418 3 8418 8418 VDD VDD VDD Figure 18 6 Internal Voltage Dividing Resistor Connection 18 1 6 Common COM Signals The common signal o
154. SP Protection size 256bytes 3EH 1 3EH 0 ON OFF ISP Protection size 512bytes 3EH 1 3EH 0 OFF ON ISP Protection size 1024bytes 3EH 1 3EH 0 OFF OFF ISP Protection size 2048bytes ON ISP protection enable 3EH 2 OFF ISP protection disable ON LVR disable 3FH 7 OFF LVR enable Table 23 3 Clock Source Selection Setting JP10 When to use the external clock from socket Y2 When to use the internal clock from an emulator SAMSUNG ELECTRONICS a Table 23 4 PWM Enable Disable Setting mno PWM is disabled during no run 1 om PWM is always enabled whether run or not INTO TAOUT P1 0 INT1 BUZ TACK P1 1 INT2 TACAP P1 2 P4 7 SEG19 COM7 P4 6 SEG18 COM6 P4 5 SEG17 COM5 P4 4 SEG16 COM4 P4 3 SEG15 P4 2 SEG14 P4 1 SEG13 P4 0 SEG12 P3 7 SEG11 P3 6 SEG10 P3 5 SEG9 P3 4 SEG8 P3 3 SEG7 INTS T1OUT1 P1 3 VDD VSS XOUT XIN TEST Xtin Xtout nRESET TBPWM T1CKO P2 0 T1CAPO PWM P2 1 P3 2 SEG6 T1OUTO AD4 P2 2 P3 1 SEG5 AD5 T1CK1 P1 4 P3 0 SEG4 T1CAP1 AD6 P1 5 P0 3 COM3 AD3 SI AD7 P2 3 P0 2 COM2 AD2 SO SEGO0 P2 4 P0 1 COM1 AD1 SCK SEG1 P2 5 P0 0 COMO ADO Rx SEG2 P2 6 Avss TX SEG3 P2 7 Avref ON O WD A gt M z z 70 o m Figure 23 4 44 Pin Connector Pin Assignment for 8419 SAMSUNG ELECTRONICS SEG14 P4 2 SEG15P4 3 SEG16 COM4 P4 4 SEG17 COMB P4 5 COM6 SEG18 P4 6 COM7 SEG19 P4 7 INTO TAOUT P1 0 INT1 BUZ TACK P1 1 INT2 TACAP P1 2 P4
155. Selection Bits ES Destination page 0 Destination page 1 Destination page 2 Other values Don t care Source page 0 Source page 1 Source page 2 Other values Don t care NOTE 1 In the S8C8418X F8418X microcontroller the internal register file is configured as two pages Page 0 Page 2 The page 0 is used for the general purpose register file and data register 2 Inthe S3C8419X F8419X microcontroller the internal register file is configured as three pages Page 0 2 The page 0 and page 1 are used for the general purpose register file and data register 3 The page 2 is used for the LCD display ram and it is a write only memory SAMSUNG ELECTRONICS 4 30 ea 53 8419 UM REV3 00 4 Control Registers 4 1 30 PWMCON PWM Control Register F5H Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 4 o 0 0 _ 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W 7 6 PWM Input Clock Selection Bits o 1 fOSC 1 Not used for 53 8418 8418 8419 8419 4 PWMDATA Reload Interval Selection Bit Reload from 10 bit up counter overflow 1 Reload from 8 bit up counter overflow 3 PWM Counter Clear Bit No effect 1 Clear the PWM counter when write 2 PWM Counter Enable Bit Stop counter 1 Start Resume countering PWM Overflow Interrupt Enable Bit 8 Bit Overflow Disable interrupt 1 Enable interrupt 0 PWM Overflow Interrupt Pend
156. T DI SB1 LD LPOT 00H SBO LD POCON 00H LD POCON 055H LD POCON 0AAH LD POCON 0FFH SB1 LD LPOT 4FH SB0 LD POCON 0AAH SAMSUNG ELECTRONICS Reset address 5 5 5 5 5 5 PO is normal or alternative function PO is input mode PO is input pull up mode PO is Push pull output mode PO is ADC input PO is LCD port If you use PO as LCD port POCON register value doesn t care 14 PORT CONTROL REGISTERS PAGE 9 7 Port 1 Control Register High Byte PI CONH E8H Set1 R W Reset value 00 7 4 Not used must keep always 0 3 2 P1 5 T1CAP1 AD6 Configuration Bits 0 0 Input mode T1CAP1 input 0 1 Input mode with pull up T1CAP1 input 1 0 Push pull output mode 1 1 Alternative function mode AD6 1 0 P1 4 T1CK1 AD5 Configuration Bits 00 Input mode T1CK1 input 0 1 Input mode with pull up T1CK1 input 1 0 Push pull output mode 1 1 Alternative function mode AD5 Figure 9 2 Port 1 High Byte Control Register P1CONH Port 1 Control Register Low Byte P1CONL E9H R W Reset value 00H MSB 7 6 5 4 2 1 0 7 6 P1 3 T1OUT1 INT3 Configuration Bits 0 0 Input mode Interrupt input INT3 01 mode with pull up Interrupt input INT3 1 0 Push pull output mode 1 1 Alternative function mode T1OUT1 output 5 4 P1 2 TACAP INT2 Configuration Bits 0 0 Input mode Int
157. TOP OSC inst STPCON fxr Selector 1 Y V Sub system Watch Timer Oscillator Circuit v 1 8 1 4096 OSCCON 2 Basic Timer Timer Counter Frequency Watch Timer fxx 256 Dividing Circuit UART p A D Converter 1 2 1 8 1 16 v v CLKCON 4 3 SAMSUNG ELECTRONICS Selector 2 Figure 7 3 System Clock CPU Clock gt IDLE Instruction System Clock Circuit Diagram 7 3 53 8419 00 7 Clock Circuit 7 1 3 System Clock Control Register CLKCON The system clock control register CLKCON is located in set 1 address D4H It is read write addressable and has the following functions e Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON Set 1 R W 5 Not used must keep always 0 Not used must keep always 0 Divide by selection bits for CPU clock frequency 00 fxx 16 01 fxx 8 10 fxx 2 11 fxx 1 non divided NOTE The fxx can be generated by both main system and sub system oscillator therefore while main system stops peripherals can be operated by sub system Figure 7 4 System
158. There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V1 one source S1 Type 2 One level IRQn one vector V1 multiple sources S1 Sn Type 3 One level IRQn multiple vectors V1 Vn multiple sources S1 Sn Sn 1 Sn m In the S3C8418X F8418X C8419X F8419X microcontroller two interrupt types are implemented SAMSUNG ELECTRONICS 5 2 eux S3F8419_UM_REV3 00 5 Interrupt Structure Levels Vectors Sources V1 NOTES 1 The number of Sn and Vn value is expandable 2 Inthe S3C8418X F8418X 8419X F8419X implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types SAMSUNG ELECTRONICS 5 3 Lm S3F8419_UM_REV3 00 5 Interrupt Structure 5 3 S3C8418X F8418X C8419X F8419X Interrupt Structure S3C8418X F8418X C8419X F8419X microcontroller supports sixteen interrupt sources All of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interr
159. V3 00 6 Instruction Set Table6 1 Instruction Group Summary Wemoic Operands LD D LD UJ O D dst dst dst dst dst O 5 TU gt gt g gt _________ DEC m 7 oV memm INOW mvmewwd SAMSUNG ELECTRONICS 6 2 Lu 53 8419 UM REV3 00 6 Instruction Set ENTER EXIT NEXT Wr waitress SSS cicic 20 70 7 4 00 55 RL RLC SR Shift right arithmetic SWAP Swap nibbles CPU Conirol Instructions SAMSUNG ELECTRONICS 6 3 a 53 8419 UM REV3 00 6 Instruction Set Mnemonic Omm m emeememps emmenps ug eweWemde stp d er Stop mode NOTE LDE LDED LDEI LDEPP and LDEPI instructions can be used to read write the data from the 64 Kbyte data memory SAMSUNG ELECTRONICS T x_n 53 8419 UM REV3 00 6 Instruction Set 6 2 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits which describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 be tested and used with conditional jump instructions Two other flag bits FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to in
160. Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH SAMSUNG ELECTRONICS 4 12 ea 53 8419 UM REV3 00 4 Control Registers 4 1 12 IPR Interrupt Priority Register Set 1 Bit Identifier 7 5 4 3 2 x x x x x x x RESET Value x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 1 Priority Control Bits for Interrupt Groups A B and C Group priority undefined B gt C gt A A gt B gt C B gt A gt C gt A gt C gt B gt A A gt C gt B Group priority undefined Lo Lo Lo EN ofo ofo ofi ofi ERES CHEA 1 6 Interrupt Subgroup C Priority Control Bit o 1806 gt IRQ7 IRQ7 gt IRQ6 5 Interrupt Group C Priority Control Bit IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQS 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQ4 IRQ4 gt IRQ3 e 2 Interrupt Group B Priority Control Bit IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group Priority Control Bit IRQO gt IRQ1 gt IRQO Eo SAMSUNG ELECTRONICS 4 13 53 8419 UM REV3 00 4 Control Registers 4 1 13 IRQ Interrup
161. a shifter 3 For interrupt generation set the serial I O interrupt enable bit SIOCON 1 to 1 4 When you the transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 the shift operation starts 5 When the shift operation transmit receive is completed the SIO pending bit SIOCON 0 is set to 1 and an SIO interrupt request is generated SAMSUNG ELECTRONICS 14 1 Lm 53 8419 UM REV3 00 14 Serial I O interface 14 1 2 SIO Control Registers SIOCON The control registers for serial I O interface SIOCON is located Seti Bank 1 at F2H It has the control settings for SIO module e Clock source selection internal or external for shift clock e Interrupt enable e Edge selection for shift operation e Clear 3 bit counter and start shift operation e Shift operation transmit enable e Mode selection transmit receive or receive only e Data direction selection MSB first or LSB first A reset clears the SIOCON value to 00H This configures the corresponding module with an internal clock source at the SCK selects receive only operating mode and clears the 3 bit counter The data shift operation and the interrupt are disabled The selected data direction is MSB first SIO Control Registers SIOCON F2H Set 1 Bank 1 R W Reset 00H d d SIO shift clock select bit SIO interrupt pending bit 0 Internal clock P S clock 0 No interrupt pending 1 External clock SCK 0 Clear pending c
162. able Watch dog LD T1CONO0 01000110b Enable interrupt fxx 64 Interval Interval 1 536 ms 10 MHz x tal T1DATAHO 400F0h T1DATAHO 00h T1DATALO FOh El MAIN ROUTINE TIM1_INT Interrupt service routine SAMSUNG ELECTRONICS 12 8 Lm 53 8419 UM REV3 00 13 10 bit PWM Pulse width Modulation 10 bit PWM Pulse width Modulation 13 1 Overview This microcontroller has the 10 bit PWM circuit The operation of all PWM circuit is controlled by a single control register PWMCON The PWM counter is a 10 bit incrementing counter It is used by the 10 bit PWM circuits To start the counter and enable the PWM circuits you set PWMCON 2 to 1 If the counter is stopped it retains its current count value when re started it resumes counting from the retained count value When there is a need to clear the counter you set PWMCON 3 to 1 You can select a clock for the PWM counter by set PWMCON 6 7 Clocks which you can select are fXX 64 fXX 8 fXX 2 1 13 2 Function description 13 2 1 PWM The 10 bit PWM circuits have the following components e 8 bit comparator and extension cycle circuit 8 bit reference data register PWMDATAH 7 0 e 2 bit extension data register PWMDATAL 1 0 e PWM output pins P2 1 PWM 13 2 1 1 PWM Counter To determine the PWM module s base operating frequency the upper 8 bits of counter is compared to the PWM data PWMDATAH 7 0 In order to achieve higher resolutions the
163. alling edge depending on the corresponding control register setting Figure 5 2 S3C8418X F8418X C8419X F84I9XInterrupt Structure SAMSUNG ELECTRONICS 5 5 eux S3F8419_UM_REV3 00 5 Interrupt Structure 5 4 Interrupt Vector Addresses All interrupt vector addresses for the S3C8418X F8418X C8419X F8419X interrupt structure are stored in the vector address area of the internal 8 Kbyte ROM 0H 1FFFH S3C8418X F8418X 32 Kbyte ROM OH 7FFFH S8C8418X F8419X see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H 32 Kbyte RESET RESET lt Address 0100H lt FFH Address 255 Interrupt Interrupt Area Vector Vector Area 53 8419 8419 S3C8418X F8418X Figure 5 3 ROM Vector Address Area SAMSUNG ELECTRONICS 5 6 Lm S3F8419_UM_REV3 00 5 Interrupt Structure Table 5 1 Interrupt Vectors Vector Address Reset Clear Decimal Hex Interrupt Source Value Value 256 100H Basic timer WDT overflow UART transmit UART receive NOTE 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one wit
164. and all measures both in equity and law available to it and claim full damages against any party that misappropriates Samsung s trade secrets and or confidential information BE DOCH MAAR ES ta e Ot A T IURIS PR OT BUDE 2 B FARIA AE PB RE Fd fed FEER RE AS HI A SD AB CB AR TU AR 1 UU SCA XE SB ARO LB T 5 UE AE WAT SRS RS HADOR IE LT AGERE CLF AS BRP BE LE EP TBO o n 4 AL Trademarks All brand names trademarks and registered trademarks belong to their respective owners Exynos Exynos 5410 FlexOneNAND and OneNAND are trademarks of Samsung Electronics e ARM Jazelle TrustZone and Thumb are registered trademarks of ARM Limited Cortex ETM ETB Coresight ISA and Neon are trademarks of ARM Limited e Java is a trademark of Sun Microsystems Inc e SD iis a registered trademark of Toshiba Corporation e MMC and eMNC are trademarks of MultiMediaCard Association e JTAG is a registered trademark of JTAG Technologies Inc e Synopsys is a registered trademark of Synopsys Inc e 125 is a trademark o
165. apture interrupt IRQ2 vector C8H generation 0 control register T1 CONO set 1 E8H Bank 1 read write 1 control register T1CON1 set 1 E9H Bank 1 read write e Timer 1 e Timer 1 e Timer 1 SAMSUNG ELECTRONICS 12 1 Lm 53 8419 00 12 16 bit Timer 1 0 1 12 1 1 Function description 12 1 1 1 Timer 1 0 1 Interrupts IRQ2 Vectors C6H and CAH The timer 1 0 module can generate two interrupts the timer 1 0 overflow interrupt T1OVFO and the Timer 1 0 match capture interrupt 1 T1OVFO is interrupt level IRQ2 vector C6H T1INTO also belongs to interrupt level IRQ2 but is assigned the separate vector address C4H A timer 1 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 0 match capture interrupt T1INTO pending condition is also cleared by hardware when it has been serviced The timer 1 1 module can generate two interrupts the timer 1 1 overflow interrupt T1OVF1 and the timer 1 1 match capture interrupt T1INT1 T1OVF1 is interrupt level IRQ2 vector CAH T1INT1 also belongs to interrupt level IRQ2 but is assigned the separate vector address C8H A timer 1 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 1 match capture interrupt T1INT1 pending condition is also cleared by hardware when it has been serviced 12 1 1 2
166. bit digital values The analog input level must lie between the AVREF and AVSS values The A D converter has the following components e Analog comparator with successive approximation logic D A converter logic resistor string type e ADC control register ADCON set 1 bank 0 F7H read write but ADCON 3 is read only e Eight multiplexed analog data input pins ADCO ADC7 e 10 bit A D conversion data output register ADDATAH ADDATAL 16 2 Function Description To initiate an analog to digital conversion procedure at first you must configure P0 0 P0 3 P1 4 P1 5 P2 2 P2 3 to analog input before A D conversions because the P0 0 P0 3 P1 4 P1 5 P2 2 P2 3 pins can be used alternatively as normal data or analog input pins To do this you load the appropriate value to the POCONL P1CONH P2CONL for ADCO ADC7 register And you write the channel selection data in the A D converter control register ADCON to select one of the eight analog input pins ADCn n 0 7 and set the conversion start or enable bit ADCON O A 10 bit conversion operation can be performed for only one analog input channel at a time The read write ADCON register is located in set 1 bank 0 at address F7H During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The
167. c RESET The MCU can start only when the supply voltage rises over the reference voltage When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode SAMSUNG ELECTRONICS 19 1 Lm 53 8419 UM REV3 00 19 LOW Voltage RESET Watchdog RESET nRESET B Internal System nRESET When the level is lower than 2 8V NOTES 1 The target of voltage detection level is 2 8 V at VDD 5 V 2 BGR is Band Gap voltage Reference Figure 19 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON SAMSUNG ELECTRONICS 19 2 Lm 53 8419 UM REV3 00 20 Embedded Flash Memory Interface Embedded Flash Memory Interface 20 1 Overview The SSF8418X 8419X has an on chip flash memory internally instead of masked ROM The flash memory is accessed by LDC instruction and the type of sector erase and a byte programmable flash a user can program the data in a flash memory area any time you want The 53 8419 5 embedded 32K byte memory has two operating features and
168. cal working register address addressing Register pointer Three low order bits prov ides five high order bits FLU 11111 8 bit phy sical address Figure 2 16 98 bit Working Register Addressing SAMSUNG ELECTRONICS 2 19 Lm 53 8419 UM REV3 00 2 Address Spaces 011001000 Selects RP1 R11 8 bit address Register 100 1 O 1 1 form instruction 10101 address LD R11 R2 OABH Specifies working register addressing Figure 2 17 8 Bit Working Register Addressing Example SAMSUNG ELECTRONICS 2 20 x_n 53 8419 UM REV3 00 2 Address Spaces 2 5 System and User Stack The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The 53 8418 8418 8419 8419 architecture supports stack operations in the internal register file 2 5 1 Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of
169. ch of the 2 register pages is currently selected The set 1 locations however can only be addressed using direct addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 and Table 2 2 Table 2 1 S3C84I9X F84I9X Register Type Summary Register Type Number of Bytes General purpose registers including 16 byte common working register area two 192 byte prime register area and two 64 byte set 2 area LCD data registers Page2 s 00H 13H CPU and system control registers Mapped clock peripheral control and data registers Table 2 2 S3C84I8X F84I8X Register Type Summary General purpose registers including 16 byte common working register area expanded 2 separately addressable register pages LCD data registers Page2 s 00H 13H CPU and system control registers Mapped clock peripheral control and data registers Total Addressable Bytes SAMSUNG ELECTRONICS 2 4 ex 53 8419 UM REV3 00 2 Address Spaces Bank 1 Page 0 Bank 0 System and Set 2 Peripheral Control Registers Register Addressing Mode General Purpose Data Registers Indirect Register Indexed System and Mode and Stack Operations
170. ck Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces e One working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 e One working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2 The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO always point to the 16 byte common area in set 1 Slice 32 11111XXX Slice 31 RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Figure 2 8 8 byte Working Register Areas Slices SAMSUNG ELECTRONICS 2 11 e 53 8419 UM REV3 00 2 Address Spaces 2 3 6 Using the Register Pointers Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset
171. ck PWM OVF interrupt pending bit selection bits 0 No interrupt pending 00 fxx 64 0 Clear pending condition when write 01 fxx 8 1 Interrupt pending 10 fxx 2 11 fxx 1 PWM OVF interrupt enable bit 0 Disable interrupt Not used for 1 Enable interrupt S3C8418X F8419X C8419X F8419X PWM counter enable bit 0 Stop counter 1 Start resume countering PWMDATA reload interval selection bit 0 reload from 1 Obit up counter overflow 1 reload from 8bit PWM counter clear bit up counter overflow 0 No effect 1 Clear the PWM counter Figure 13 3 PWM Control Register PWMCON SAMSUNG ELECTRONICS 13 5 Lm 53 8419 UM REV3 00 13 10 bit PWM Pulse width Modulation PWMCON 6 7 2 bit Extend bit 8 bit up counter PWMDATAL PWMDATAH 2 bit 8 bit Counter Counter PWMCON 2 1 When lt Comparator P2 1 PWM H 8 bit Data Buffer Extension Data Buffer 8 bit Data F3H Set1 Bank1 Register F3H PWMDATAH Set Bank1 PWMDATAL 1 0 PWMCON 3 clear 8 bit up counter overflow DATA BUS 7 0 Figure 13 4 PWM Functional Block Diagram SAMSUNG ELECTRONICS 13 6 ax 53 8419 UM REV3 00 13 10 bit PWM Pulse width Modulation Example 13 1 Programming the PWM Module to Sample Specifications lt lt Interrupt Vector Address gt gt ORG 0000H VECTOR ODAH INT PWM lt lt Initialize System and Peripherals gt gt ORG 0100H DI disable interrupt LD BTC
172. cuting a DI instruction it will be serviced when the El instruction is executed No flags are affected Bytes Cycles Opcode Hex opc 1 4 OF Given SYM 00H EI If the SYM register contains the value OOH that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts 5 is the enable bit for global interrupt processing SAMSUNG ELECTRONICS 6 39 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 27 ENTER Enter ENTER Operation SP lt SP 2 SP lt IP IP lt lt IP IP lt IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 1F Example The diagram below shows an example of how to use an ENTER statement Before After Address Data Address 0050 0043 Address Address 0040 Enter PC 0110 Enter Address H Address H Address L Address L 0022 Address H 0020 Address H 20 IPH 00 21 IPL 50 M 22 Data 22 Data pd Stack Stack SAMSUNG ELECTRONICS 6 40 e 53 8419 UM REV3 00 6 Instruction Set
173. d Addressing Mode X 3 7 3 5 Direct Address Mode DA etaed e eta obe erc nad abe M a ERU FRE E a YER o daba depo dn 3 10 3 6 Indirect Address Mode lA 2 ccena elk aa DR 3 12 3 7 Relative Address Mode 4 40044 00 110 3 13 3 8 immediate Mode IM 3 14 4 CONTROL REQGISTERS 4 1 Ad OVGIVIOW ER E R R 4 1 4 1 1 ADCON A D Converter Control Register _ F7H Set 1 4 5 4 1 2 BTCON Basic Timer Control Register Set 1 4 6 4 1 3 System Clock Control Register D4H Set 1 4 7 4 1 4 FMCON Flash Memory Control Register Set 1 1 4 8 4 1 5 FMSECH Flash Memory Sector Register High byte F9H Set 1 Bank1 4 9 SAMSUNG ELECTRONICS ex 4 1 6 FMSECL Flash Memory Sector Register Low byte FAH Set 1 Bank1 4 9 4 1 7 FMUSR Flash Memory User Programming Enable Register FBH Set 1 Bank1 4 9 4 1 8 FLAGS System Flags Register D5H Set 1
174. d if a valid stop bit was not received The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit Parity enable bits PEN is located in the UARTPND register at address F4H Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Figure 151 UART Control Register UARTCON SAMSUNG ELECTRONICS 15 3 S3F8419_UM_REV3 00 15 UART 15 1 3 UART Interrupt Pending Register UARTPND The interrupt pending register UARTPND is located at address F4H It contains the UART data transmit interrupt pending bit UARTPND 0 and the receive interrupt pending bit UARTPND 1 In mode 0 of the UART module the receive interrupt pending flag UARTPND 1 is set to 1 when the 8th receive data bit has been shifted In mode 1 or 2 the UARTPND 1 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UARTPND 1 flag must be cleared by software in the interrupt service routine In mode 0 of the UART module the transmit interrupt pending flag UARTPND O is set to 1 when the 8th transmit data bit has been shifted In mode 1 or 2 the UARTPND O bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the UARTPND O flag must be cleared by software in the interrupt service routine UART Pending Register UARTPND F4H Set1
175. d in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD Figure 3 14 Immediate Addressing SAMSUNG ELECTRONICS 3 14 eux 53 8419 UM REV3 00 4 Control Registers Control Registers 4 1 Overview Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual The locations and read write characteristics of all mapped registers in the S3C8418X F8418X C8419X F84I9X register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers RegserName mnemonics Hex reguest register _________ ma 2 D Resistor page pointer PP 23 nw 2 B SAMSUNG ELECTRONICS 4 1 Lu 53 8419 UM REV3 00 4 Control Registers Table 4 2 Set 1 Bank 0 Registers 7 7 RegserName mnemonic He _ P E RW ister z Port 3 control register Low Byte RW converter data register Hoh ADDATAH 248 R co
176. d in target address to write data LD FMSECL 00H SECTOR128 sector base address 4000H LD R9 0A3H Load data to write LD R10 40H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register WR_BYTE1 LDC RR10 R9 Write data A3H at flash memory location INC R11 DJNZ R1 WR_BYTE1 SAMSUNG ELECTRONICS 20 10 x_n 53 8419 UM REV3 00 20 Embedded Flash Memory Interface FMCON 01010000B Programming stop FMUSR 00H User Program mode disable RR10 R9 Write data written by R9 at flash memory location R11 RO WR BYTE SAMSUNG ELECTRONICS 20 11 ea 53 8419 UM REV3 00 20 Embedded Flash Memory Interface 20 5 Reading The read operation starts by LDC instruction The program procedure in User program Mode 1 Load a flash memory upper address into upper register of pair working register 2 Load a flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode Example 20 4 Reading R2 03H load flash memory upper address to upper of pair working register R3 00H load flash memory lower address to lower pair working register RO RR2 read data from flash memory location Between 300H and 3FFH R3 R3 0FFH NZ LOOP SAMSUNG ELECTRONICS 20 12 ea 53 8419 UM R
177. de 5 4 P1 2 TACAP INT2 Configration Bits 0 0 Input mode Interrupt input INT2 0 Input mode with pull up Interrupt input INT2 TACAP 3 2 P1 1 TACK BUZ INT1 Configration Bits Input mode Interrupt input INT1 TACK Input mode with pull up Interrupt input INT1 K 0 Push pull output mode Alternative function mode BUZ out mode 1 0 P1 0 TAOUT INTO Configration Bits Input mode Interrupt input INTO 1 Input mode with pull up Interrupt input INTO K Push pull output mode Alternative function mode TAOUT mode SAMSUNG ELECTRONICS 4 20 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 20 P1INTPND Port 1 Interrupt Pending Register EAH Set 1 Bank0 Bit Identifier 7 5 4 3 2 0 0 0 0 RESET Value Read Write _ _ _ _ R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for S3C8418X F8418X C8419X F8419X 3 P1 3 INT3 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P1 2 INT2 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 P1 1 INT1 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 1 0 P1 0 INTO Interrupt Pending Bit Interr
178. de Hex dst src 2 10 E2 r Irr Given R6 10H R7 33H R8 12H program memory location 1033H OCDH and external data memory location 1033H ODDH LDCD R8 RR6 LDED R8 RR6 OCDH into R8 ODDH into R8 contents of program memory location 1033H is loaded R8 and RR6 is decremented by one R6 10H R7 32H RR6 lt RR6 1 contents of data memory location 1033H is loaded R8 and RR6 is decremented by one RR6 RR6 1 ODDH R6 10H R7 32H NOTE LDED instruction can be used to read write the data of 64 Kbyte data memory SAMSUNG ELECTRONICS 6 53 Lum 53 8419 UM REV3 00 6 Instruction Set 6 6 39 LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples dst src dst src dst lt src rr rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Ir an even number for program memory an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 10 E3 r Irr
179. dicate whether register bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then two write will simultaneously occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W wo 7 5 3 2 2 B Bank address status flag BA Carry flag NH Fast interrupt Zero flag Z status flag FS Sign flag S Half carry flag Ov erf low flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS SAMSUNG ELECTRONICS 6 5 Lm 53 8419 UM REV3 00 6 Instruction Set 6 3 Flag Descriptions C Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations have been performed it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Z Zero FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero
180. dresses of page 2 are used as LCD data memory It is Write only memory When the bit value of a display segment is 1 the LCD display is turned on when the bit value is 0 the display is turned off Display RAM data are sent out through segment pins SEGO SEG19 using a direct memory access DMA method that is synchronized with the f cp signal SAMSUNG ELECTRONICS eux 28 TOOL PROGRAM MODE PAGE 20 1 20 2 Table 20 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming P1 2 SDAT 3 44 pi data pin output when reading Input when writing Input and push pull output port can be assigned SCLK 4 44 pin Serial clock pin input only pin 10 42 pin TEST 9 44 pin Power supply pin for flash ROM cell writing 15 42 pin indicates that MTP enters into the writing mode When 12 5 V SSF8418 Vdd S3F8419 is applied MTP is in writing mode nRESET nRESET 2 44 pin 8 42 pin Vpp Vss Vpp Vss 5 6 44 pin Logic power supply pin ie 42 pin Table 21 2 Comparison of S3F8418X F8419X and S3C8418X C8419X Features S3F8418X 8419X S3C8418X 8419X Program Memory 8 Kbyte Flash ROM for S3F8418X 8 Kbyte Mask ROM for 53 8418 32 Kbyte Flash ROM for 53 8419 32 Kbyte Mask ROM for 53 8419 Operating Voltage Vpp 25V to 5 5V LVR off 2 5V to 5 5 V LVR off LVR to 55V CUR on LVR to 5 5V LVR on MTP Programming Mode Vpp 5 V 12 5 V SSF8418X 5V 53 8419
181. duty 1 3 bias COMO COM3 SEGO SEG19 4 0 1 8 duty 1 4 bias 7 5 0 5 015 1 8 duty 1 5 bias COM0 COM7 SEGO SEG15 1 0 LCD Clock Selection Bits o tw 2 256 Hz when fw is 32 768 kHz o 1 tw 2 512 Hz when fw is 32 768 kHz 1 fw 25 1 024 Hz when fw is 32 768 kHz fw 24 2 048 Hz when fw is 32 768 kHz SAMSUNG ELECTRONICS 4 15 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 15 LPOT LCD Port Control Register F7H Set 1 Bank1 Bit Identifier 4 E 4 RESET Value 0 0 0 0 0 0 0 Read Write _ R W R W R W R W R W R W R W 7 Not used for 53 8418 8418 8419 8419 6 4 SEG4 SEG19 and Selection Bit SEG4 7 SEG8 11 SEG12 15 SEG16 19 COM0 3 COM7 COM4 Fo Po Pon Pw Pon 0 ron Po Fe Pon cow sea se ses secicow cow Pn se ses secicow cow Po Pn Po ses SEGCOM cow 3 SEG3 P2 7 Selection Bit 0 Normal I O port 1 SEG port 2 SEG2 P2 6 Selection Bit Normal port SEG port SEG1 P2 5 Selection Bit Normal I O port SEG port fel 0 SEGO0 P2 4 Selection Bit Normal port SEG port NOTE SEG16 SEG19 are shared with COM4 COM7 SAMSUNG ELECTRONICS 4 16 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 16 OSCCON Oscillator Control Register F2H Set
182. e Enable watchdog function 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bit 00 fxx 4096 01 fxx 1024 10 fxx 128 11 fxx 1 Not used Figure 10 1 Basic Timer Control Register BTCON SAMSUNG ELECTRONICS 10 2 ea 53 8419 UM REV3 00 10 Basic Timer 10 2 Basic Timer Function Description 10 2 1 Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock The CPU is reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a clear instr
183. e Not used 10 Push pull output mode 11 Alternative function mode TxD output 5 4 P2 6 SEG2 RxD Configuration Bits 0 0 2 Input mode RxD iput 0 1 Alternative function mode Not used 1 0 Push pull output mode 11 Alternative function mode RxD output 3 2 P2 5 SEG1 SCK Configuration Bits 0 0 Input mode input 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode output 1 0 P2 4 SEG0 SO Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode SO output Figure 9 6 Port 2 High Byte Control Register P2CONH 17 PORT CONTROL REGISTERS PAGE 9 11 Port 2 Control Register Low Byte P2CONL EDH Set1 R W Reset value 00 7 6 P2 3 AD7 SI Configuration Bits 0 0 Input mode SI 0 1 Alternative function mode Not used 1 0 Push pull output mode 11 2 Alternative function mode AD7 7 6 P2 2 ADA T1OUTO Configuration Bits 0 0 2 Input mode 0 1 Alternative function mode T1OUTO 1 0 Push pull output mode 11 Alternative function mode AD4 7 6 P2 1 PWM T1CAPO Configuration Bits 0 0 Input mode T1CAPO 0 1 Alternative function mode Not used 1 0 Push pull output mode 11 Alternative function mode PWM 7 6 P2 0 TBPWM T1CKO Configuration Bits 0 0 Input mode T1CKO 0 1 Alternative function mode T1CKO 1 0 Push pull
184. e Sub Release Timing Initiated by Interrupts SAMSUNG ELECTRONICS 21 9 x_n 53 8419 UM REV3 00 21 Electrical Data Table 21 10 UART Timing Characteristics in Mode 0 10 MHz TA 25 C to 85 2 5 V to 5 5 V Load capacitance 80 pF Serial port clock cycle time tSCK 500 tCPU x 6 700 Output data setup to clock rising edge tS1 300 tCPU x 5 1 Alltimings are in nanoseconds ns and assume 10 MHz CPU clock frequency 2 Theunit tCPU means one CPU clock period Figure 21 7 Waveform for UART Timing Characteristics SAMSUNG ELECTRONICS 21 10 x_n 53 8419 UM REV3 00 21 Electrical Data Table 21 11 A D Converter Electrical Characteristics TA 25 to 85 AVREF VDD VSS 0 V Parameter Symbol Test Conditions Total accuracy VDD 5 12 V Integral linearity ILE CPU clock 10 MHz error AVREF 5 12 V Differential DLE AVSS 0 V linearity error Offset error of top T lt H Offset error of bottom m 10 bit conversion 50 x 4 fOSC note 3 fOSC 10 MHz reference voltage AVREF VDD 5 V conversion time 20 us AVREF VDD 5 conversion time 20 us Analog block AVREF VDD 23V current note 2 conversion time 20 us AVREF VDD 5 V when power down mode NOTE 1 Conversion time is the time required from the moment a conversion operation starts until it ends Conversion time note 1 1000
185. e Bit Disable receive interrupt Enable receive interrupt 0 Transmit Interrupt Enable Bit SAMSUNG ELECTRONICS 4 42 a 53 8419 UM REV3 00 4 Control Registers Disable transmit interrupt Enable transmit Interrupt NOTE 1 In mode 2 if the MCE UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if MCE 1 then the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE UARTCON 5 bit should be 0 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit 3 Parity enable bits PEN are located in the UARTPND register at address F4H bank 0 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only SAMSUNG ELECTRONICS 4 43 ea 53 8419 00 4 Control Registers 4 1 45 UARTPND UART Pending and Parity Control F4H Set 1 Bit Identifier RESET Value Read Write 7 6 NOTE o7 6 5 4 3 2 4 9 0 0 0 0 0 0 0 0 _ _ R W R W _ R W R W Not used for the S3F8415X F84I9X must keep always 0 UART Parity Enable Disable PEN Disable Enable 1 UART Receive Parity Error RPE No error 1 Parity error Not used for the S3F8415X F84I9X must keep always 0 UART Receive Interrupt Pending Flag Nip EN Clear pending bit when write Int
186. e C flag to 1 and the sign flag and the overflow flag are also set to 1 SAMSUNG ELECTRONICS 6 72 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 58 RRC Rotate Right through Carry RRC Operation Flags Format Examples dst dst 7 lt C C lt dst 0 dst lt dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag and the initial value of the carry flag replaces bit 7 MSB Set if the bit rotated from the least significant bit position bit zero was 1 Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Set if arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 CO R C1 IR Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC 00H gt Register 00H 2AH C 1 RRC 801 gt Register 01H 02H register 02H OBH C 1 In the first example if the general register 00H contains the value 55H 01010101B the statement RRC rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH
187. e Slices 8 Byte Slice 16 Byte Contiguous RP1 5 RPO Figure 2 9 Contiguous 16 byte Working Register Block SAMSUNG ELECTRONICS 2 12 Lm 53 8419 UM REV3 00 2 Address Spaces 8 Byte Slice Register File Contains 32 16 byte Non contiguous 11110XXX 8 Byte Slices working RPO register block 00000XXX Figure 2 10 Non Contiguous 16 byte Working Register Block Example 2 3 Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 H respectively SRPO 80H RPO lt 80H ADD RO R1 RO RO R1 ADC RO R2 RO RO R2 ADC RO R3 RO RO R3 ADC RO R4 RO RO R4 ADC RO R5 RO RO R5 The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H E lt 80H 81H ADC 80H 82H 80H 82H ADC 80H 83H 80H 83H ADC 80H 84H 80H 84H ADC 80H 85H 80H 85H Now the sum of the six registers is also located in register However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rath
188. e e edd E ca er Eder Sc 2 7 2 3 2 LIS EET HEP 2 8 2 3 3 Register Set 2 nee nde d d eel cie ne acu de ada e ada 2 8 2 3 4 Prime Register 5 te re ie ad ped E V Ra de aud aaa ed doge a ined EDU uda a dade 2 9 2 3 5 Working Registers ierit Eee pec se do heat 2 11 2 3 6 Using the Register trennen ennt 2 12 2 4 Register teria M 2 14 2 4 1 Common Working Register Area enn 2 16 2 4 2 4 bit Working Register Addressing essen nennen nennen nennen 2 17 2 4 3 8 bit Working Register 2 19 2 5 Systemiand User Stack eee ee ee Gee 2 21 2 5 1 Stack Operations ER teannain onaniaa anaia aa aaaea aaa aaa 2 21 2 5 2 User Defined Stacks ettet n eI d e ERE aa a 2 21 2 5 8 Stack Pointers SPLE LL dere pedet e dod bi xe eri nce dit uerba Mad edades ned 2 21 ADDRESSING MODES 3 1 BV OVORVIOW 222 3 1 3 2 Register Addressing Mode 3 2 3 3 Indirect Register Addressing Mode enn 3 3 3 4 Indexe
189. e note the following conditions for Stop mode release e f you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged e f you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode e When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used e The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed 8 2 1 3 How to Enter into Stop Mode There are two steps to enter into Stop mode 1 Handling STOPCON register to appropriate value 10100101 2 Writing Stop instruction keep the order SAMSUNG ELECTRONICS 8 6 ex 53 8419 UM REV3 00 8 RESET and Power Down 8 2 2 Idle Mode Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a
190. ected 1 2 41 42 SEG12 SEG15 P4 0 P4 3 by software input or push pull 37 40 N channel open drain output Software assignable pull up Alternatively can be used as SEG16 SEG19 SEG12 SEG15 P4 4 P4 7 COM7 SEG16 SEG19 COM4 7 input pins for external interrupt 7 1 1 0 1 3 INTO INTS Alternatively used as general purpose digital input output port 1 Analog input pins for A D converter module a P0 0 P0 3 P2 2 Alternatively used as general purpose digital H us 25 28 P2 3 input output port 0 and port 2 15 1 8 P1 4 P1 5 27 28 A D converter reference voltage and ground 23 24 Serial data RxD pin for receive input and transmit 25 output mode 0 21 Serial data TxD pin for transmit output and shift clock P2 7 output mode 0 s SAMSUNG ELECTRONICS 1 9 ax 53 8419 UM REV3 00 T1OUTO T1CK1 1 T1OUT1 toggle output pins za E E NN el SEGO SEG3 SEG4 SEG15 LCD segment display signal output pins NN Ds External clock input pins for timer 1 0 Capture input pins for timer 1 0 Timer 1 0 16 bit PWM mode output or counter match toggle output pins External clock input pins for timer 1 1 Timer 1 1 16 bit PWM mode output or counter match Do EIE EN epee ppm D 5 D 5 D 5 D 5 D 5 D 5 D 5 E E E 18 17 14 16 H H
191. ed control operation mode or Stand alone SEMINIX Full Function regarding OTP MTP program TEL 82 2 539 7891 Read Program Verify Protection Blank FAX 82 2 539 7819 Data back up even at power break E mail After setup in Design Lab it can be moved to the sales seminix com factory site URL Key Lock protecting operator s mistake http www seminix com Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Operation status displayed in LCD panel SAMSUNG ELECTRONICS 23 11 eux
192. ed sector SSF8419X has 256 sectors to be erased written in flash memory Sectors have all 128 byte sizes as program memory areas Sector Erase is not supported in Tool Program Modes MDS mode Sector 255 128 byte Sector 254 128 byte Sector 127 128 byte Sector 19 128 byte Sector 18 128 byte Sector 0 17 128 byte x 18 Figure 20 3 Sectors in User Program Mode SAMSUNG ELECTRONICS 20 5 ea 53 8419 UM REV3 00 20 Embedded Flash Memory Interface Flash Memory Sector Address Register FMSECH F9H SET1 BANK1 R W Flash Memory Sector Address Register Enable bit You have to input High address of sector that s accessed Figure 20 4 Flash Memory Sector Address Register FMSECH Flash Memory Sector Address Register FMSECL FAH SET1 BANK1 R W Flash Memory Sector Address Register Enable bit You have to input Low address of sector that s accessed Figure 20 5 Flash Memory Sector Address Register FMSECL The Sector Erase Procedure in User program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Sector Address Register FMSECH FMSECL 3 Set Flash Memory Control Register FMCON to 10100001B 4 Set Flash Memory User Programming Enable Register FMUSR to 00000000B SAMSUNG ELECTRONICS 20 6 Lm 53 8419 UM REV3 00 20 Embedded Flash Memory Interface Example 20 1 Sector Erase Not to Use an Interrupt FMUSR 0A5H User Prog
193. el open drain output P4is N channel open drain output P4 is LCD port If you use as LCD port register value doesn t care If you use as LCD port P3CONL register value doesn t care 22 FUNCTION DESCRIPTION PAGE 11 2 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the Timer A data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the Timer A capture input selection bit in the port 1 control register P1CONL set 1 bank 0 E9H When P1CONL 5 4 is 00 or 01 the TACAP input or normal input is selected When P1CONL 5 4 is set to 1X normal push pull output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the Timer A data register SAMSUNG ELECTRONICS eux 23 FUNCTION DESCRIPTION PAGE 13 1 PWM The 10 bit PWM circuits have the following components e 8 bit comparator and extension cycle circuit e 8 bit reference data register PWMDATAH 7 0 e 2 bit extension data register PWMDATAL 1 0 e PWM output pins P2 1 PWM SAMSUNG ELECTRONIC
194. en the IRET instruction is executed BA Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when the SBO instruction is executed and is set to 1 select bank 1 when the SB1 instruction is executed SAMSUNG ELECTRONICS 6 6 Lm 53 8419 UM REV3 00 6 Instruction Set 6 4 Instruction Set Notation Table 6 2 Flag Notation Conventions Bewmim owe SSCS smo Table6 3 Instruction Set Symbols Flags register D5H Repone _ 5 8 rymmbrsfik SAMSUNG ELECTRONICS 7 a 53 8419 UM REV3 00 6 Instruction Set Table 6 4 Instruction Notation Conventions i E o an n 0 16 Bit 0 LSB of working register Rn n 0 15 Bit b of register or working register reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where p 0 2 14 Indirect addressing mode addr addr 0 254 even number only Indirect working register only n 0 15 Indirect register or indirect working Indirect working register pair only RRp p 0 2 14 Register pair or working register pair Indexed addressing mode streg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where p 0 2 14 addr RRp addr range 0
195. er FMUSR 251 RW 4 5 6 7 8 9 0 1 2 3 4 5 36 7 38 9 0 1 2 3 4 5 6 7 8 9 50 51 Flash memory control register 252 Location FDH FFH are not mapped SAMSUNG ELECTRONICS a x_n 53 8419 UM REV3 00 Bit number s that is are appended to the register name for bit addressing 4 Control Registers Name of indiv idual bit or related bits Register ID FLAGS System Flags Register Bit Identifier RESET Value Read Write Bit Addressing Mode 7 R Read only W Write only R W Read write Not used Ty pe of addressing that must be used to address the bit 1 bit 4 bit or 8 bit SAMSUNG ELECTRONICS Register location Register address in the internal Register name hexadecimal register file D5H parse sg x x x x x x 0 0 R W R Set 1 RW RW R W R W Register addressing mode only R W Carry Flag C Operation does not generate a carry or borrow condition EN Operation generates carry out or borrow into high order bit 7 Zero Flag Z EN Operation result is a non zero value Operation result is zero Sign Flag S Operation generates positive number MSB 0 Operation generates negative number MSB 1 Description of the effect of specific bit settings RESET value notation Not used x Undetermined value 0 Logic zero 1 Logic one Bit n
196. er File Organization of 53 8418 8418 SAMSUNG ELECTRONICS e 5 REGISTER PAGE POINTER PAGE 2 7 Register Page Pointer PP DFH Set 1 R W Destination register page selection bits Source register page selection bits Source Page 0 Destination Page 0 Source Page 1 Destination Page 1 Destination Page 2 Source Page 2 In the 53 8419 8419 microcontroller page 0 1 2 are implemented In the S3C8418X F8418X microcontroller page 0 2 are implemented A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer 00H These values should be modified to other pages Figure 2 5 Register Page Pointer PP SAMSUNG ELECTRONICS 6 CONTROL REGISTERS POCON Port 0 Control R 7 6 PAGE 4 19 egister High Byte E6H Set 1 PO S AD3 COMSG Configration Bits 0 inpumode Fo t mumoewhpuup E Eats Push pull output mode Alternative function mode AD3 input P0 2 AD2 COM2 Configration Bits O 0 mpumode j 0 mpumodewthpulup __ 1 Push pulloutputmode __ Alternative function mode AD2 input P0 1 AD1 COM1 Configration Bits o 0 1 mpumodewthpulup __ 1 Push pulloutputmode 000 00 Alternative function mode AD1 input P0 0 ADO COMO Configration Bits mame Fo r mumoewnpuup
197. er mode a match signal is generated when the counter value is identical to the value written to the Timer A data register TADATA In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from OOH Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAOUT pin is held to Low level as long as the reference data value is less than or equal to x the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to tCLK 256 11 1 2 4 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the Timer A data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the Timer A capture input selection bit in the port 1 control register P1 CONL set 1 bank 0 E9H When P1CONL 5 4 is 00 or 01 the TACAP input or normal input is selected When P1CONL 5 4 is set to 1X normal push pull output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflo
198. er than 36 cycles SAMSUNG ELECTRONICS 2 13 Lm 53 8419 UM REV3 00 2 Address Spaces 2 4 Register Addressing The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space LSB n Even address Figure 2 11 16 Bit Register Pair SAMSUNG ELECTRONICS 2 14 eux 53 8419 UM REV3 00 Special Purpose Registers Control Registers
199. er to page 9 16 SAMSUNG ELECTRONICS 9 CONTROL REGISTERS PAGE 4 28 P3CONL Port 3 Control Register Low Byte EFH Set 1 7 6 P3 3 SEG7 Configration Bits mame Fo t mumoewhpuup KEE Push pull output mode N channel open drain output P3 2 SEG6 Configration Bits O 0 Inputmode j 0 1 mpumodewthpulup __ 1 Pushpuloutputmods __ N channel open drain output P3 1 SEG5 Configration Bits O Ojnma 0 1 mpumodewthpulup __ 1 Push pulloutputmode N channel open drain output P3 0 SEG4 Configration Bits Fo t mumoewhpuup 1 0 Push pull output mode If you want below For example 1 LD LPOT 00000000B 2 LD LPOT 01001111B N channel open drain output NOTE If you want to use P3 as aLCD port you must set LPOT register appropriately Refer to Ex 2 below to use P3 as a Normal I O you must set LPOT register appropriately Refer to Ex 1 P3 0 P3 3 is Normal P3 0 P3 3 is LCD port For more detail please refer to page 9 16 SAMSUNG ELECTRONICS 10 CONTROL REGISTERS PAGE 4 29 P4CONH Port 4 Control Register High Byte FOH Set 1 ofo fma Fo input mode win pukup EAE Push pull output mode N channel open drain output 4 6 COM6 SEG18 Configration Bi
200. errupt input INT2 TACAP 01 mode with pull up Interrupt input INT2 TACAP 1 0 Push pull output mode 1 1 Alternative function mode Not used 3 2 P1 1 TACK BUZ INT1 Configuration Bits 0 0 Input mode Interrupt input INT1 TACK 0 1 Input mode with pull up Interrupt input INT1 TACK 1 0 Push pull output mode 1 1 Alternative function mode BUZ output 1 0 P1 0 TAOUT INTO Configuration Bits 0 0 Input mode Interrupt input INTO 0 1 Input mode with pull up Interrupt input INTO 1 0 Push pull output mode 1 1 Alternative function mode TAOUT output Figure 9 3 Port 1 Low Byte Control Register P1 CONL SAMSUNG ELECTRONICS 15 PORT CONTROL REGISTERS PAGE 9 9 Port 2 Port 2 is an 8 bit port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank 0 2 0 2 7 can serve as digital inputs outputs push pull or you can configure the following alternative functions e General purpose digital I O e Alternative function SEGO SEG3 ADC4 ADC7 SI TICAP0 T1OUTO T1CK0 TBPWM PWM SAMSUNG ELECTRONICS eux 16 PORT CONTROL REGISTERS PAGE 9 10 SAMSUNG ELECTRONICS Port 2 Control Register High Byte P2CONH ECH Set1 R W Reset value 00 7 6 P2 7 SEG3 TxD Configuration Bits 0 0 2 Input mode 0 1 Alternative function mod
201. errupt pending UART Transmit Interrupt Pending Flag Not pending EN Clear pending bit when write Interrupt pending 1 In order to clear data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit 2 To avoid programming errors we recommend using load instruction except for LDB when manipulating UARTPND values 3 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted SAMSUNG ELECTRONICS 4 44 eim 53 8419 UM REV3 00 4 Control Registers 4 1 46 WTCON Watch Timer Control Register F8H Set 1 Bank1 Bit Identifier 7 6 8 4 3 2 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Watch Timer Clock Selection Bit EN Main system clock divided by 256 fxx 256 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit Disable watch timer interrupt Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 0 5 kHz buzzer BZOUT signal output ERE 1 kHz buzzer BZOUT signal output 2 kHz buzzer BZOUT signal output 4 kHz buzzer BZOUT signal output 3 2 Watch Timer Speed Selection Bits ossmena Fo rjnssmma _ 41 Watch Timer Enable Bit Disable watch timer Clear frequency dividing circuits Enable
202. ers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes The major CPU features are e Efficient register oriented architecture e Selectable CPU clock sources e and Stop power down mode released by interrupt or reset e Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels SAMSUNG ELECTRONICS 1 1 ea 53 8419 UM REV3 00 1 Product Overview 1 2 S3C8418X F8418X C8419X F8419X Microcontroller S3C8418X F8418X C8419X F8419X single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process technology based on Samsung s latest CPU architecture The S3C84l9X is a microcontroller with a 32K byte mask programmable ROM embedded The S3F8419X is a microcontroller with a 32K byte Full Flash ROM embedded The S3C8418X is a microcontroller with a 8K byte mask programmable ROM embedded The SSF8418X is a microcontroller with a 8K byte Half Flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C8418X F8418X C84I9X F8419X by integrating the following peripheral modules with the powerful SAMB e Five programmable ports 42SDIP 32pins 44QFP 34pins including po
203. erwise V Setifthe quotient is gt 2 or if the divisor 0 cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 R2 40H register 40H 80H DIV RRO R2 gt RO 03H R1 40H DIV RRO R2 gt RO 03H R1 20H DIV RRO 20H gt RO 03H R1 80H In the first example the destination working register pair RRO contains the values 10H RO and 03H R1 and the register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 SAMSUNG ELECTRONICS 6 37 e 53 8419 UM REV3 00 6 Instruction Set 6 6 25 DJNZ Decrement and Jump if Non Zero DJNZ Operation NOTE Flags Format Example r dst r r 1 If r z 0 PC PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relat
204. esult The destination and the source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 62 r r 6 63 r Ir src dst 3 6 64 R R 65 R IR dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register OOH 2BH register 01H 02H and register 02H 23H TCM RO R1 E RO OC7H R1 02H Z 1 TCM RO R1 gt RO OC7H R1 02H register 02H 23H Z 0 TCM 01H gt Register 2BH register 01H 02H 2 1 TCM 00H Q01H gt Register 00H 2BH register 01H 02H register 02H 23H Z 1 TCM 34 gt Register 00H 2BH Z 0 In the first example if the working register RO contains the value 0C7H 11000111B and the register R1 the value 02H 00000010B the statement TCM RO R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation 179 53 8419 00 6 Instruction Set 6 6 69 TM Test under Mask TM Operation Flags Format Examples SAMSUNG ELECTRONICS 6 84 dst src dst AND src This instruction tests selected bits in the destination operand for a logic zero
205. f Phillips Electronics 2 a trademark of Phillips Semiconductor Corp e MIPI and Slimbus are registered trademarks of the Mobile Industry Processor Interface MIPI Alliance All other trademarks used in this publication are the property of their respective owners SAMSUNG ELECTRONICS x Chip Handling Guide Precaution against Electrostatic Discharge When using semiconductor devices ensure that the environment is protected against static electricity 1 Wear antistatic clothes and use earth band 2 All objects that are in direct contact with devices must be made up of materials that do not produce static electricity 3 Ensure that the equipment and work table are earthed 4 Useionizer to remove electron charge Contamination Do not use semiconductor products in an environment exposed to dust or dirt adhesion Temperature Humidity Semiconductor devices are sensitive to e Environment e Temperature e Humidity High temperature or humidity deteriorates the characteristics of semiconductor devices Therefore do not store or use semiconductor devices in such conditions Mechanical Shock Do not to apply excessive mechanical shock or force on semiconductor devices Chemical Do not expose semiconductor devices to chemicals because exposure to chemicals leads to reactions that deteriorate the characteristics of the devices Light Protection In non Epoxy Molding Compound EMC package do not expose semiconduc
206. first 15 2 1 1 Mode 0 Transmit Procedure 1 Select mode 0 by setting UARTCON 6 and 7 to 00B 2 Write transmission data to the shift register UDATA F5H to start the transmission operation 15 2 1 2 Mode 0 Receive Procedure 1 Select mode 0 by setting UATCON 6 and 7 to 008 2 Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 3 Setthe UART receive enable bit UARTCON 4 to 1 4 The shift clock will now be output to the TxD P2 7 pin and will read the data at the RxD P2 6 pin A UART receive interrupt vector E4H occurs when UARTCON 1 is set to 1 Write to Shift Register UDATA E dun 7 po X o X X os X me Transmit TIP Write to UARTPND Clear RIP and set RE RE st JL JL JUL 1 Jl JL D1 D D3 OM D5 H D6 RxD Data In TxD Shift Clock _ Ll Figure 15 6 Timing Diagram for UART Mode 0 Operation SAMSUNG ELECTRONICS 15 9 Lm S3F8419_UM_REV3 00 15 UART 15 2 2 UART Mode 1 Function Description In mode 1 10 bits are transmitted through the TxD P2 7 pin or received through the RxD P2 6 pin Each data frame has three components e Start bit 0 e 8 data bits LSB first e Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCON register The baud rate f
207. ge VIL2 VDD o XIN o XTIN VDD 5 0 V Output High Voltage 2 VDD 1 0 All Ports VDD 5 0 V IOL 16 mA YQLI Ports 0 and 4 Output Low Voltage VOL2 VDD 5 0 V IOL 4 Ports 1 2 and 3 ILIH1 VIN VDD Input High Leakage All input pins except ILIH2 Current VIN VDD ILIH2 XIN XOUT and XTIN XTOUT ina Y OY Input Low Leakage All input pins except and ILIL2 Operating Voltage o Current TE VIN 0V XIN XOUT and XTIN XTOUT Output High ILOH VOUT VDD Leakage Current All output pins Output Low ILOL VOUT 0 V Leakage Current All output pins LCD Voltage Dividing Resistor Lon di IVLCD SEGx Voltage Drop x 0 19 Middle Output VLC2 VDD 2 5 V to 5 5 V 0 8 VDD 0 8 VDD VDD 2 5 V to 5 5 V 15 uA per common pin 2 VDD 2 5 V to 5 5 V age Drop i 15 pA per common pin I 0 8 VDD SAMSUNG ELECTRONICS 21 3 53 8419 UM REV3 00 21 Electrical Data Voltage VDD 5V VIN 0V 25 All pins except VDD 5 V VIN 0V 25 nRESET only VDD 4 5 Vto 5 5 V RUN mode 10 MHz CPU clock VDD 2 5 V to 3 3 V RUN mode 4 MHz CPU clock VDD 4 5 V to 5 5 V Idle mode 10 MHz CPU clock VDD 2 5 V to 3 3 V Idle mode 4 MHz CPU clock Sub operating main osc stop VDD 2 5 V to 3 3 V 32768 Hz crystal oscillator Pull up Resistor Supply Current 1 Sub idle mode mai
208. gister Overview Control Register i RW Function Description Bit settings in the IMR register enable or disable interrupt registar processing for each of the eight interrupt levels IRQ0 IRQ 7 Controls the relative processing priorities of the interrupt levels The seven levels of S3F8415X F8419X are organized Interrupt priority register R W into three groups B and C Group A is IRQO and IRQ1 group is IRQ2 IRQ3 and IRQ4 and group C IRQ5 IRQ6 and IRQ7 Interrupt request This register contains a request pending bit for each interrupt register level System mode register SYM R W This register enables disables fast interrupt processing dynamic global interrupt processing NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended SAMSUNG ELECTRONICS 5 8 a S3F8419_UM_REV3 00 5 Interrupt Structure 5 7 Interrupt Processing Control Points Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are e Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM 0 e Interrupt level enable disable settings IMR register e Interrupt level priority settings IPR register e Interrupt source enable disable settings the corresponding peripheral control registers NOTE When writing an applicati
209. gram counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Normal Hex opc 1 12 BF IRET Bytes Cycles Opcode Fast Hex opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupt are enabled When an interrupt occurs the program counter and the instruction pointer are swapped This causes the PC to jump to the address 100H and the IP to keep the return address The last instruction in the service routine is normally a jump to IRET at the address FFH This loads the instruction pointer with 100H again and causes the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H 100 Interrupt Service Routine JP to FFH FFFFH NOTE In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last tow instruction The IRET cannot be immediately proceeded by an instruction which clears the interrupt status as with a reset of the IPR register SAMSUNG
210. gs Format Example dst src RA If dst src z 0 lt RA Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Src dst RA 3 12 D2 r Ir Given R1 02H R2 03H and register 03H 04H CPIJNE R1 R2 SKIP gt R2 04H PC jumps to SKIP location The working register R1 contains the value 02H the working register R2 the source pointer the value 03H and the general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJNE instruction must be within the allowed range of 127 to 128 SAMSUNG ELECTRONICS 6 31 e 53 8419 00 6 6 20 DA Decimal Adjust 6 Instruction Set D
211. h a higher vector address The priorities within a given level are fixed in hardware SAMSUNG ELECTRONICS x_n S3F8419_UM_REV3 00 5 Interrupt Structure 5 5 Enable Disable Interrupt Instructions El Dl Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register 5 6 System Level Interrupt Control Registers In addition to the control registers for specific interrupt sources four system level registers control interrupt processing e The interrupt mask register IMR enables un masks or disables masks interrupt levels e The interrupt priority register IPR controls the relative priorities of interrupt levels e The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source e The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Re
212. h the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands C Setif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 32 r r 6 33 r Ir opc src dst 3 6 34 R R 35 R IR dst src 3 6 36 R IM Given R1 10H R2 C 1 register 01H 20H register 02H and register 03H OAH SBC R1 R2 gt R1 OCH R2 03H SBC R1 QR2 gt R1 05H R2 03H register 03H SBC 01H 02H gt Register 01 1 register 02H 03H SBC 01H 02H gt Register 01 15H register 02H 03H
213. he captured data value in T1DATAH1 T1DATAL1 and assuming a specific value for the timer 1 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the pin 12 1 1 4 PWM Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the T1OUTO T1OUT1 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 1 0 1 data registers In PWM mode however the match signal does not clear the counter but can generate a match interrupt Instead it runs continuously overflowing at FFFFH and then continuous increasing from OOOOH Whenever an overflow occur an overflow T1OVFO 1 interrupt can be generated Although you can use the match or overflow interrupts in the PWM mode these interrupts are not typically used in PWM type applications Instead the pulse at the T1OUTO T1OUT1 pin is held to low level as long as the reference data value is less than or equal to the counter value and then the pulse is held to high level for as long as the data value is greater than gt the counter value One pulse width is equal to Tclk SAMSUNG ELECTRONICS 12 3 Lm 53 8419 00 12 16 bit Timer 1 0 1 12 1 2 Timer 1 0 1 control register t1conO t con1 You use the timer 1 0 1 control register TTCONO T1CON1 to e Select the timer 1 0 1 operating mode Inte
214. he second set of values used in the formats 9 and 10 are used to address data memory 5 LDE instruction can be used to read write the data of 64 Kbyte data memory SAMSUNG ELECTRONICS 6 51 eux 53 8419 UM REV3 00 Examples 6 Instruction Set Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC RO RR2 LDE RO RR2 LDC RR2 RO LDE RR2 RO LDC RO 01 282 LDE RO 01H RR2 LDC 01H RR2 RO LDE O01H RR2 RO LDC RO 1000H RR2 LDE RO 1000H RR2 LDC RO 1104H LDE RO 1104H LDC 1105H RO LDE 1105H RO RO lt contents of program memory location 0104H RO 1AH R2 01 R3 04H lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of location 0104H R 11H contents of location 0104H R is loaded into program memory RO R2 R3 no change is loaded into external data memory RO R2 RO R2 RO R2 R3 no change lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0105H 01H 0104H 11H contents of RO is loaded into external data memory loca
215. ics but which test the same For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used Following a CP instruction you would probably want to use the instruction EQ 2 For operations using unsigned numbers the special condition codes UGE ULT UGT and ULE must be used SAMSUNG ELECTRONICS 11 Lm 53 8419 UM REV3 00 6 Instruction Set 6 6 Instruction Descriptions This Chapter contains detailed information and programming examples for each instruction in the S3C8 series instruction set Information is arranged in a consistent format for improved readability and for quick reference The following information is included in each instruction description e Instruction name mnemonic e Full instruction name e Source destination format of the instruction operand e Shorthand notation of the instruction s operation e Textual description of the instruction s effect e Flag settings that may be affected by the instruction e Detailed description of the instruction s format execution time and addressing mode s e Programming example s explaining how to use the instruction SAMSUNG ELECTRONICS 12 eux 53 8419 00 6 6 1 ADC Add with Carry 6 Instruction Set The source operand along with the carry flag setting is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s comple
216. ime during which all 128bytes of one sector block is erased 3 In the case of 5328419 the chip eraseing is available in TOOL Program Mode Only SAMSUNG ELECTRONICS 21 13 x_n 53 8419 UM REV3 00 22 Mechanical Data Mechanical Data 22 1 Overview The S3F8419X F8419Xmicrocontrollers are available in 42 SDIP 600 44 QFP 1010 package 42 SDIP 600 14 00 0 20 39 50 MAX 39 10 0 20 WI 3 50 0 20 5 08 MAX 0 50 0 10 1 77 L 1 00 0 10 NOTE Dimensions are in millimeters 0 51 Figure 22 1 42 5 600 Package Dimensions SAMSUNG ELECTRONICS 22 1 Lm 53 8419 UM REV3 00 9 8 o o H e o N e w SAMSUNG ELECTRONICS 22 Mechanical Data 13 20 0 30 10 00 0 20 0 10 4 4 0 15 0 05 44 QFP 1010 e 0 10 MAX 0 80 0 20 0 05 MIN 2 05 0 10 2 30 MAX NOTE Dimensions are in millimeters Figure 22 2 44 QFP 1010 Package Dimensions 22 2 en 53 8419 UM REV3 00 23 Development Tools Development Tools 23 1 Overview Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator
217. ing Bit No interrupt pending when read Clear pending bit when write Interrupt is pending when read NOTE PWMCON 3 is not auto cleared You must pay attention when clear pending bit refer to page 11 8 SAMSUNG ELECTRONICS m x_n 53 8419 UM REV3 00 4 Control Registers 4 1 31 RPO Register Pointer 0 D6H Set 1 RESET Value 1 1 0 0 0 _ _ _ Read Write R W R W R W R W R W _ _ _ Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RP0 and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP0 points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C8418X F8418X C8419X F8419X 4 1 32 RP1 Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 _ _ _ Read Write RAN R W R W R W R W _ _ _ Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice
218. ing the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using the standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 23CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C lt 0 lt 0 Bits 4 7 3 bits 0 3 1 DA R1 Rl ae 31 0 leave the value 31 BCD in the address 27H 1 SAMSUNG ELECTRONICS 6 33 eux 53 8419 UM REV3 00 6 6 21 DEC Decrement DEC Operation Flags Format Examples dst dst dst 1 The contents of the destination operand are decremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setif result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Hex dst 2 4 00 01 Given R1 and register 10H DEC R1 gt R1 02H DEC R1 gt Register 03H OFH 6 Instruction Set Addr Mode dst R IR In the first example if the working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC QR1 decrements the value 10H contained in the destinati
219. instruction following the BTJRT instruction is executed Flags No flags are affected Format NOTE Bytes Cycles Opcode Addr Mode Hex dst src src b 1 dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRT SKIP R1 1 If the working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location addressed by the BTJRT instruction must be within the allowed range of 127 to 128 SAMSUNG ELECTRONICS 6 23 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 12 BXOR Bit XOR BXOR dst src b BXOR dst b src Operation dst 0 dst 0 XOR src b or dst b dst b XOR src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or the source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Flags C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode
220. interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT TAOVF is interrupt level IRQ1 vector C2H TAINT also belongs to interrupt level IRQ1 but is assigned the separate vector address COH Timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced Timer A match capture interrupt TAINT pending condition is also cleared by hardware when it has been serviced 11 1 2 2 Interval Timer Function The timer A module can generate an interrupt the timer A match interrupt TAINT TAINT belongs to interrupt level IRQ1 and is assigned the separate vector address COH When the timer A match interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware In interval timer mode a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the timer A reference data register TADATA The match signal generates a timer A match interrupt TAINT vector COH and clears the counter If for example you write the value 10H to TADATA and OAH to TACON the counter will increment until it reaches 10H At this point the Timer A interrupt request is generated the counter value is reset and counting resumes 11 1 2 3 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAOUT pin As in interval tim
221. ion mode AD6 1 0 P1 4 T1CK1 AD5 Configuration Bits 0 0 Input mode T1CK1 input 0 1 Input mode with pull up T1CK1 input 1 0 Push pull output mode 1 1 Alternative function mode AD5 Figure 9 2 Port 1 High Byte Control Register P1 CONH SAMSUNG ELECTRONICS 9 5 Lu 53 8419 UM REV3 00 9 I O Ports Port 1 Control Register Low Byte P1CONL E9H Seti R W Reset value 00H MSB 7 6 4 SAMSUNG ELECTRONICS 7 6 P1 3 T1OUT1 INT3 Configuration Bits 0 0 Input mode Interrupt input 01 mode with pull up Interrupt input 1 0 Push pull output mode 1 1 Alternative function mode T1OUT1 output 5 4 P1 2 TACAP INT2 Configuration Bits 0 0 Input mode Interrupt input INT2 TACAP 01 mode with pull up Interrupt input INT2 TACAP 1 0 Push pull output mode 1 1 Alternative function mode Not used 3 2 P1 1 TACK BUZ INT1 Configuration Bits 0 0 Input mode Interrupt input INT1 TACK 0 1 Input mode with pull up Interrupt input INT1 TACK 1 0 Push pull output mode 1 1 Alternative function mode BUZ output 1 0 P1 0 TAOUT INTO Configuration Bits 0 0 2 Input mode Interrupt input INTO 0 1 2 Input mode with pull up Interrupt input INTO 1 0 Push pull output mode 1 1 Alternative function mode TAOUT output Figure 9 3 Port 1 Low Byte Control Register P1 CONL 53 8419 UM REV3 00 9 I O Ports Port 1
222. ion with various addressing modes and formats 53 8419 UM REV3 00 6 Instruction Set 6 6 47 POP Pop from Stack POP Operation Flags Format Examples dst dst lt SP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 50 R 51 IR Given Register 00H 01H register 01H 1BH SPH OD8H 00H SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register 55H SP OOFCH POP 800 gt Register OOH 01H register 01H 55H SP OOFCH In the first example the general register 00H contains the value 01H The statement POP 00H loads the contents of the location OOFBH 55H into the destination register OOH and then increments the stack pointer by one The register 00H then contains the value 55H and the SP points to the location OOFCH SAMSUNG ELECTRONICS 6 62 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 48 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are
223. ip Flop Waveforms in Repeat Mode SAMSUNG ELECTRONICS 11 8 x_n 53 8419 00 11 8 bit Timer A B Example 11 1 To generate 38 kHz 1 3duty signal through P2 0 This example sets Timer B to the repeat mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 us pr 17 59 us 37 9 kHz 1 3 Duty e Timer B is used in repeat mode e Oscillation frequency is 16 MHz 0 0625 ms fx fxx 4 4 MHz 0 25 ms TBDATAH 8 795 ms 0 25 ms 35 18 TBDATAL 17 59 ms 0 25 ms 70 36 e Set P2 0 to TBPWM mode Reset address TBDATAL 35 1 Set8 75 ms TBDATAH 70 1 Set17 5ms TBCON 00100111B Clock Source lt _ fxx 4 Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer B Output flip flop T FF high P2CONL 03H P2 0 to TBPWM mode This command generates 38 kHz 1 3 duty pulse signal through P2 0 SAMSUNG ELECTRONICS 11 9 Lm 53 8419 00 11 8 bit Timer A B Example 11 2 To generate a one pulse signal through P2 0 This example sets Timer B to the one shot mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 40ms width pulse The program parameters are 4 e Timer is used in one shot mode e Oscillation frequency is 4 MHz fx 1 4 clock
224. is performed by adding the two s complement of the source operand to the destination operand Flags C Set if a borrow occurred cleared otherwise Z Set if the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 22 r r 23 r Ir opc src dst 3 24 R R 25 R IR dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH SUB R1 R2 gt R1 OFH R2 03H SUB R1 QR2 gt R1 08H R2 03H SUB 01H 02H gt Register 01 register 02H 03H SUB 01H 02H gt Register 01H 17H register 02H 03H SUB 01H 90H gt Register 01H 91H C S and V SUB 01H 65H gt Register 01 1 0 In the first example if he working register R1 contains the value 12H and if the register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in the destination register R1 SAMSUNG ELECTRONICS 6 81 x_n 53 8419 UM REV3 00 6 Instructio
225. ister IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels 5 1 2 Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware 53 8418 8418 8419 8419 uses sixteen vectors 5 1 3 Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S8C8419X F84I9X interrupt structure there are sixteen possible interrupt sources When a service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit SAMSUNG ELECTRONICS 5 1 a S3F8419_UM_REV3 00 5 Interrupt Structure 5 2 Interrupt Types The three components of the 53 8 interrupt structure described before levels vectors and sources combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic
226. ister is loaded into the 8 bit counter when the operation of the timer B starts And then if a underflow occurs in the counter the value of the TBDATAH register is loaded into the value of the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded into the value of the 8 bit counter To output TBPWM as carrier wave you have to set P4CONL 7 6 as 11 Figure 11 3 Timer B Functional Block Diagram SAMSUNG ELECTRONICS 11 5 Lm 53 8419 UM REV3 00 11 8 bit Timer A B 11 2 3 Timer B Control Register TBCON Timer B Control Register TBCON DOH Set 1 Bank 0 R W Timer B input clock selection bit Timer B output flip flop 00 fxx 4 control bit 01 fxx 8 0 T FF is low 10 fxx 64 1 T FF is high 11 fxx 256 Timer B mode selection bit Timer B interrupt time selection bit 0 One shot mode 00 Elapsed time for low data value 1 Repeating mode 01 Elapsed time for high data value 10 Elapsed time for low and high data value Timer B start stop bit 11 Invaild setting 0 Stop timer B 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 4 Timer B Control Register TBCON Timer B Data High Byte Register TBDATAH D1H Set 1 Bank 0 R W Reset Value FFh Timer B Data Low Byte Register TBDATAL D2H Set 1 Bank 0 R W Reset Value FFh Figure 11 5 Timer B Data Registers TBDATAH TBDATAL SAMSUNG
227. istics e Oscillation stabilization time e Data retention supply voltage in stop mode e UART timing characteristics in mode 0 e converter electrical characteristics e LVR Loew Voltage Reset Circuit Characteristics e AC Electrical Characteristics for Internal Flash ROM SAMSUNG ELECTRONICS 21 1 ea 53 8419 UM REV3 00 21 Electrical Data Table 21 1 Absolute Maximum Ratings TA 25 C Parameter __ Um supply Votage wo 5 Output Current High pins active 0780 mA Output Current Low IOL Operating TA 25 to 85 Temperature C Storage Temperature TSTG ee 65 to 150 Table 21 2 Input Output Capacitance TA 25 to 85 VDD 0 V Parameter Symbol wm Max Ut Input Capacitance ON f 1 MHz unmeasured pins Output Capacitance COUT are tied to VES I O Capacitance SAMSUNG ELECTRONICS 21 2 ea 53 8419 UM REV3 00 21 Electrical Data Table 21 3 D C Electrical Characteristics TA 25 C to 85 2 5 V to 5 5 Symbol fx 20 8 MHz fxt 32 8 kHz LVR off fx 0 8 MHz fxt 32 8 kHz LVR on fx 0 10MHz 0 f x O0 1OMZ MHz 4 5 VDD 2 5 Vto 5 5 V All Port and nRESET pG vB Input High Voltage VDD 25 Vto55V 2 o 5 VIH2 XIN and Soo VILA VDD c All Ports and c Input Low Volta
228. ite TACON 1 to 1 To generate the exact time interval you should write TACON 3 and 0 to 1 which cleared counter and interrupt pending bit When interrupt service routine is served the pending condition must be cleared by software by writing a 0 to the interrupt pending bit TINTPND O or TINTPND 1 Timer A Control Register TACON E1H Set 1 Bank 1 R W Reset 00H ve 5 2 Timer A input clock selection bit Timer A start stop bit 00 fxx 1024 0 Stop timer A 01 fxx 256 1 Start timer A 10 fxx 64 11 External clock TACK Timer A match capture interrupt Timer A operating mode selection bit enable bit 00 Interval mode TAOUT mode 0 Disable interrupt 01 Capture mode capture on rising edge 1 Enable interrupt counter running OVF can occur 10 Capture mode capture on falling edge Timer A overflow interrupt enable bit counter running OVF can occur 0 Disable overflow interrupt 11 PWM mode OVF interrupt and match 1 Enable overflow interrrupt interrupt can occur Timer A counter clear bit 0 No effect 1 Clear the timer A counter when write NOTE When th counter clear bit 3 is set the 8 bit counter is cleared and it also is cleared automatically Figure 11 1 Timer A Control Register TACON SAMSUNG ELECTRONICS 11 3 Lm 53 8419 UM REV3 00 11 1 4 Block Diagram TACON 2 TACON 7 6 Overflow Data Bus TACON O f xx 1024 fxx 256 ad EE fx
229. ith pull up 1 0 Push pull output mode 1 1 Alternative function mode ADCO input Figure 9 1 Port 0 Low Byte Control Register POCON SAMSUNG ELECTRONICS 9 3 eu 53 8419 UM REV3 00 9 I O Ports Example 91 To make PO as Normal I O or Alternative function ORG 0100H Reset address DI LD LPOT 00H PO is normal I O or alternative function LD POCON 00H PO is input mode LD POCON 055H PO is input pull up mode LD POCON 0AAH PO is Push pull output mode LD POCON 0FFH PO is ADC input LPOT 4FH PO is LCD port POCON 0AAH use as LCD port POCON register value doesn t care SAMSUNG ELECTRONICS 9 4 eux 53 8419 UM REV3 00 9 I O Ports 9 2 2 Port 1 Port 1 is a 6 bit I O port with individually configurable pins that you can use two ways e General purpose digital I O e Alternative function INTO INT3 TACK TACAP T1OUT1 T1CK1 T1CAP1 AD5 ADG Port 1 is accessed directly by writing or reading the port 1 data register P1 at location E1H in set 1 bank 0 9 2 2 1 Port 1 Control Register P1CONH P1CONL Port 1 has two 6 bit control registers PI CONH for 1 4 1 5 and P1CONL for P1 0 P1 3 A reset clears the P1CONH and P1CONL registers to OOH configuring all pins to input modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O fu
230. ive address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement In case of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst r dst 2 8 jump taken rA RA 8 no jump r OtoF Given R1 02H and LOOP is the label of a relative address SRP 0COH DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example the working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements the register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label SAMSUNG ELECTRONICS 6 38 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 26 El Enable Interrupts EI Operation Flags Format Example SYM 0 lt 1 The El instruction sets bit zero of the system mode register SYM O to 1 This allows interrupts to be serviced as they occur assuming they have the highest priority If an interrupt s pending bit was set while interrupt processing was disabled by exe
231. ive cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 AO RR A1 IR Given RO 1AH R1 02H register 02H OFH and register 03H OFFH INCW RRO gt RO R1 03H INCW R1 gt Register 02H 10H register 03H 00H In the first example the working register pair RRO contains the value 1AH in the register RO and 02H in the register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in the register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of the general register from OFFH to 00H and the register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem it is recommended to use the INCW instruction as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP SAMSUNG ELECTRONICS 6 44 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 32 IRET Interrupt Return IRET Operation Flags Format Example IRET Normal IRET Fast FLAGS lt SP PC lt gt IP SP lt SP 1 FLAGS lt FLAGS PC lt SP FIS lt 0 SP lt SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the pro
232. ized with the CPU clock This procedure brings S8C8418X F8418X 8419X F8419X into a known operating status To allow time for internal CPU clock oscillation to stabilize the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required oscillation stabilization time for a reset operation is 1 millisecond Whenever a reset occurs during normal operation that is when both VDD and RESET are High level the RESET pin is forced Low and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation e Interrupt is disabled e The watchdog function basic timer is enabled e Ports 0 4 are set to input mode e Peripheral control and data registers are disabled and reset to their default hardware values e The program counter PC is loaded with the program reset address in the ROM 0100H e When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed Normal Mode Reset Operation In normal masked ROM mode the TEST pin is tied to VSS A reset enables access to the 32 Kbyte on chip ROM NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering
233. l Registers 4 1 41 TACON Timer A Control Register E1H Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer Input Clock Selection Bits oojaa 11246 o S 5 4 Timer A Operating Mode Selection Bits 0 o Interval mode TAOUT mode Capture mode capture on rising edge counter running OVF can occur 0 Capture mode capture on falling edge counter running OVF can occur PWM mode OVF interrupt can occur 3 Timer A Counter Clear Bit No effect 1 Clear the timer A counter Auto clear bit 2 Timer A Overflow Interrupt Enable Bit Disable overflow interrupt 1 Enable overflow interrupt Ti 3 er A Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer A Start Stop Bit Stop Timer A 1 Start Timer A SAMSUNG ELECTRONICS 4 39 Lm 53 8419 UM REV3 00 4 Control Registers 4 1 42 TBCON Timer B Control Register DOH Set 1 Bit Identifier L7 6 8 42 3 2 A o 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer Input Clock Selection Bits 7 9 omm SSCS 5 4 Timer B Interrupt Time Selection Bits Elapsed time for low data value 0 1 Elapsed time for high data value
234. le LD FMSECH 2 Set Sector 4 200H 27FH LD FMSECL 00H You can set FMSECL from 00H to 7FH LD FMCON 10100001B Start sector erase a FMUSR 0 User Program mode disable BO PROGRAMMING TIP Sector Erase To use an interrupt SBI LD FMUSR 0A5H User Program mode enable LD FMSECH 2 Set Sector 4 200H 27FH LD FMSECL 00H You can set FMSECL from 00H to 7FH REPEAT LD FMCON 10101001B Start sector erase and enable INT during erasing NOP NOP TM FMCON 4 Sector erase fail flag check JP NZ REPEAT if failed repeat Sector erase FMUSR 0 User Program mode disable BO SAMSUNG ELECTRONICS eux 31 ELECTRICAL DATA PAGE 21 12 Table 21 11 A D Converter Electrical Characteristics TA 25 C to 85 C Vpp Vss Symbol Test 2 Total accuracy 5 12 V Integral linearity CPU clock 10 MHz error AVrer 5 12 V Differential AVss OV linearity error aa error of bottom mesin time 10 bit conversion 20 note 1 50 x 4 Hea 3 fosc 10 MHz Analog input Vian AVss voltage Analog input impedance Analog AVngr reference voltage Analog ground Analog input lADIN AVner 5V current conversion time 20 us Analog block lape AVner Vpp 5V current 799 2 conversion time 20 us AVrer conversion time 20 us AVrer 5V when power down mode E Mn NE NONE NN FE BEL NL Es ____ ____
235. leased by interrupts SAMSUNG ELECTRONICS 21 7 Lm 53 8419 UM REV3 00 21 Electrical Data Table 21 9 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 2 5V to 5 5 V Data Retention VDDDR Stop mode 25 5 5 V Supply Voltage Data Retention IDDDR Stop mode VDDDR 2 5 V Supply Current NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads Oscillation n Stabilzation Stop Mode Time Data Retention Mode gt gt Normal Operating Execution of Mode STOP Instrction NOTE is the same as 4096 x 16 1 Figure 21 4 Stop Mode Release Timing initiated by RESET SAMSUNG ELECTRONICS 21 8 x_n 53 8419 UM REV3 00 21 Electrical Data Oscillation Stabilization Time 31 Stop gt Idle Mode lt Data Retention Mode Normal Execution of Operating Mode STOP Instruction Interrupt is the same as 4096 x 16 x BT clock Figure 21 5 Stop Mode Main Release Timing Initiated by Interrupts Oscillation Stabilization Time 31i Stop st Idle Mode Data Retention A Execution of STOP Instruction Normal Operating Mode Interrupt NOTE When the case of select the fxx 128 for basic timer input clock bef ore enter the stop mode tWAIT 128 x 16 x 1 32768 62 5 ms Figure 21 6 Stop Mod
236. lects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions SAMSUNG ELECTRONICS 3 10 Lm 53 8419 UM REV3 00 3 Addressing Modes Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions SAMSUNG ELECTRONICS 3 11 eux 53 8419 UM REV3 00 3 Addressing Modes 3 6 Indirect Address Mode 1A In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero Current Instruction OPCO
237. lue to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location Branch to the service routine specified by the concatenated 16 bit vector address NOTE 16 bit vector address always begins at an even numbered ROM address within the range of OOH FFH 5 15 1 Nesting of Vectored Interrupts It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 2 5 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it Occurs When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent SAMSUNG ELECTRONICS 5 18 e 53 8419 UM REV3 00 6 Instruction Set Instruction Set 6 1 Overview The instruction set is specifically designed to support large register files that are typical of most S3C8 series microcontroller
238. ment addition is performed In multiple precision arithmetic this instruction lets the carry value from the addition of low order operands be carried into the addition of high order operands Set if there is a carry from the most significant bit of the result cleared otherwise Set if arithmetic overflow occurs that is if both operands are of the same sign and the Set if there is a carry from the most significant bit of the low order four bits of the result Bytes Cycles 2 6 3 6 3 6 Opcode Hex 12 13 14 15 16 Addr Mode dst src r r r Ir R R R IR R IM Given R1 10H R2 C flag 1 register 01H 20H register 02H and register R1 14H R2 R1 1BH R2 Register 01H Register 01H Register 01H 03H 03H 24H register 02H 2BH register 02H 32H 03H 03H In the first example the destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in the register R1 ADC dst src Operation dst lt dst src c Flags C Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V result is of the opposite sign cleared otherwise Always cleared to 0 H cleared otherwise Format dst src src dst dst
239. mple SAMSUNG ELECTRONICS 2 18 x_n 53 8419 UM REV3 00 2 Address Spaces 2 4 3 8 bit Working Register Addressing You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 16 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address The three low order bits of the complete address are provided by the original instruction Figure 2 17 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 3 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects RPO or RP1 Address These address 1 bits indicate 8 bit 8 bit logi
240. n 5 13 Interrupt Priority Register e Re EE Eee e eee 5 14 Interrupt Request Register IRQ 5 15 System Flags Register FLAGS n s 6 5 Main Oscillator Circuit Crystal or Ceramic Oscillator 7 2 Sub System Oscillator Circuit Crystal Oscillator 4 7 2 System Clock Circuit Diagram nennen 7 3 System Clock Control Register eene tentent nnne en 7 4 Oscillator Control Register OSCCON L n tnit rentes entere en 7 5 STOP Control Register 7 5 Port 0 Low Byte Control Register POCON n aaa 9 3 Port 1 High Byte Control Register 9 5 Port 1 Low Byte Control Register P1CONL 9 6 Port 1 Interrupt Pending Register 9 7 Port 1 Interrupt Enable Register 9 8 Port 2 High Byte Control Register 2 9 10 Port 2 Low Byte Control Register P2CONL a 9 11 Port 2 Pull up Control Register P2PUR n nana 9 12 Port High Byte Control Register
241. n Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File s RPO ot RP1 RPO or RP1 Selected RP points to start of working register Program Memory 4 bit Working Register nU dst block OPCODE Point to the OPERAND gt Working Register Two Operand 1 of 8 Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing SAMSUNG ELECTRONICS 3 2 Lm 53 8419 00 3 3 Indirect Register Addressing Mode In Indirect Register IR addressing mode the content operand Depending on the instruction used the actua 3 Addressing Modes of the specified register or register pair is the address of the address may point to a register in the register file to program memory ROM or to an external memory space see Figure 3 3 Figure 3 4 Figure 3 5 and Figure 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please no set 1 using the Indirect Register addressing mode Program Memory 8 bit Register File Address OPCODE One Operand Instruction Example Inst Sample Instruction RL SHIFT Figure 3 3
242. n RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 3 14 F6 DA opc dst 2 12 F4 IRR dst 2 14 D4 IA Given RO 35H R1 21H PC 1A47H and SP 0002H CALL 3521H 9 SP 0000H Memory locations 0000H 1AH 0001H 4AH where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 0001H 49H CALL 40H gt SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to the memory location 0000H The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and the stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and the stack pointer are the same as in the first example if the program address 0040H contain
243. n the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to OOH Immediately following the write operation the 0 value is automatically cleared to 0 3 Thefxxis selected clock for system main OSC or sub OSC SAMSUNG ELECTRONICS 4 6 Lm 53 8419 UM REV3 00 4 Control Registers 4 1 3 CLKCON System Clock Control Register D4H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write _ _ RW RAN _ _ _ Addressing Mode Register addressing mode only 7 5 Not used for the 53 84 8 841 8 8419 8419 keep always 0 4 3 CPU Clock System Clock Selection Bits note _ _ 2 0 Not used for the S3C8418X F8418X C8419X F8419X must keep always 0 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 SAMSUNG ELECTRONICS 4 7 ea 53 8419 UM REV3 00 4 Control Registers 4 1 4 FMCON Flash Memory Control Register FCH Set 1 Bank1 Bit Identifier 27 6 5 4 3 2 4 o 0 0 0 0 0 0 0 RESET Value Read Write RAN RAN RAN RAN RAN RAN RAN 7 4 Flash Memory Mode Selection Bits o 1 Programmingmede 10 1 O Po ward uock mode Others Not used 3 INT Enable Bit During Sec
244. n Set 6 6 67 SWAP Swap Nibbles SWAP Operation Flags Format Examples dst dst 0 3 lt gt dst 4 7 The contents of the lower four bits and the upper four bits of the destination operand are swapped 7 43 0 C Undefined 2 Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 FO R 4 F1 IR Given Register 00H 3EH register 02H 03H and register 03H OA4H SWAP 00H gt Register 00H SWAP 02H gt Register 02H 03H register 03H 4AH In the first example if the general register OOH contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and the upper four bits nibbles in the OOH register leaving the value 1110001 1B SAMSUNG ELECTRONICS 6 82 e 53 8419 UM REV3 00 6 Instruction Set 6 6 68 TCM Test Complement under Mask TCM Operation Flags Format Examples SAMSUNG ELECTRONICS is dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the r
245. n osc stop VDD 2 5 V to 3 3 V 32768 Hz crystal oscillator NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads IDD1 and IDD2 include a power consumption of subsystem oscillator IDD3 and IDD4 are the current when the main system clock oscillation stop and the subsystem clock is used IDD5 is the current when the main and subsystem clock oscillation stop All currents IDD1 IDD4 include the current consumption of LVR circuit IDD5 is the same regardless of LVR on or LVR off e gud m c SAMSUNG ELECTRONICS 21 4 eux 53 8419 UM REV3 00 21 Electrical Data Table 21 4 A C Electrical Characteristics TA 25 C to 85 2 5 V to 5 5 V Parameter Symbol Gonaitions Mex Uni Interrupt Input High Low tINTH Width Ports 1 inte Dev 180 in NOTE User must keep more large value then min value Figure 21 1 Input Timing for External Interrupts Ports 2 Figure 21 2 Input Timing for nRESET SAMSUNG ELECTRONICS 21 5 x_n 53 8419 UM REV3 00 21 Electrical Data Table 21 5 Main Oscillator Frequency fOSC1 25 85 2 5 V to 5 5 V oscilator Clock Gweu Test Conaition Wim Max Umi Main Crystal or Ceramic External Clock Main System VDD 2 5V 5 5V Table 21 6 Main Oscillator Clock Stabilization Time tST1 25
246. nction you configure using the port 1 control registers must also be enabled in the associated peripheral module 9 2 2 2 Port 1 Interrupt Enable Pending and Edge Selection Registers P1INT P1INTPND To process external interrupts at the port 1 pins three additional control registers are provided the port 1 interrupt enable register SET1 BANK 0 the port 1 interrupt pending bits P11NTPND EBH SET1 BANK 0 The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P1INTPND1 3 0 register at regular intervals When the interrupt enable bit of any port 1 pin is 1 a rising or falling edge at that pin will generate an interrupt request The corresponding P1INTPND1 bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing 0 to the corresponding P1INTPND1 bit Port 1 Control Register High Byte P1 CONH E8H Set1 R W Reset value 00 7 4 Not used must keep always 0 3 2 P1 5 T1CAP1 AD6 Configuration Bits 0 0 Input mode T1CAP1 input 0 1 Input mode with pull up T1CAP1 input 1 0 Push pull output mode 1 1 Alternative funct
247. nds are unaffected by the comparison C Setif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 A2 r r 6 A3 r Ir src dst 3 6 A4 R R A5 R IR opc dst src 3 6 A6 R IM 1 Given R1 02H and R2 03H CP R1 R2 gt Set the C and S flags The destination working register R1 contains the value 02H and the source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because borrow occurs and the difference is negative the and the S flag values are 1 2 Given R1 and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example the destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in the working register R3 SAMSUNG ELECTRONICS 6 29 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 18 CPIJE Compare Increment and Jump on Equal CPIJE Operation Flags Format Example
248. ng operator s mistake Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Operation status displayed in LCD panel SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com SAMSUNG ELECTRONICS Revision Descriptions for Revision 3 00 Chapter Name Major Changes comparing with Last Version The number of Flash Endurance is modified 20 MTP The delay time for erase is deleted 21 electrical data 21 13 Table 21 13 is added SAMSUNG ELECTRONICS eux Table of Contents TPHODUCT OVERVIEW 1 1 1 1 S3C8 Series Microcontrollers esses entente ennt s snnt senten en 1 1 1 2 S8C8418X F8418X C8419X F8419X Microcontroller seen 1 2 Po FEUER 1 3 VA Block Diagram AE eee 1 6 Lo ASSINO enn E 1 7 1 9 Uma uei u u u 1 11 2 ADDRESS SPACES 2 1 2 EE 2 1 2 2 Program Memory ROM u uu uu unamasa ened dead De a Rea ca dn 2 2 22 1 SMart tees ee eel ie eG ee 2 3 2 9 Register Architecture iecit 2 4 2 31 Register Page Pointer PP iter rere ered
249. nstruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair OOH and 01H leaving the value 0120H SAMSUNG ELECTRONICS 6 46 e 53 8419 UM REV3 00 6 Instruction Set 6 6 34 JR Jump Relative JR cc dst Operation If cc is true PC lt PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See the list of condition codes at the beginning of this chapter The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement Flags No flags are affected Format NOTE Bytes Cycles Opcode Addr Mode Hex dst cc opc dst 2 6 ccB RA cc 0to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits in length Example Given The carry flag 1 and LABEL_X 1FF7H JR C LABEL X gt 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is currently in the program counter Otherwise the program instruction following the JR will be executed
250. ntains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in the register R1 SAMSUNG ELECTRONICS 6 14 eu 53 8419 UM REV3 00 6 Instruction Set 6 6 3 AND Logical AND AND dst src Operation dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation causes a 1 bit to be stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 52 r r 6 53 r Ir src dst 3 6 54 R R 55 R IR dst src 3 6 56 R IM Examples Given R1 12H R2 register 01H 21H register 02H register OAH AND R1 R2 gt Rl 02H R2 03H AND R1 GR2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01 register 02H 03H AND 01H 02H gt Register 01 00H register 02H 03H AND 01H 25H gt Register 01H 21H In the first example the destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement
251. nverter data register Low Byte ADDATAL R Port 2 pull up enable control register Location FCH is factory use only Basic mer counter regse R Imemppinymdse me rm nw z 2 2 22 Div z z R W R W R W R W SAMSUNG ELECTRONICS 4 2 a 53 8419 UM REV3 00 4 Control Registers Table 4 3 Set 1 Bank 1 Registers Register Name Mnemonic Timer A Timer 1 interrupt pending register Timer A control register Timer A data register Timer A counter register Timer 1 0 data register High Byte 0 data register Low Byte High Byte Timer 1 1 data register Low Byte Timer 1 0 control register Timer 1 1 control register Timer 1 0 counter register High Byte Low Byte Timer 1 Timer 1 1 data register Timer 1 0 counter register Timer 1 1 counter register High Byte TICNTH1 22 22 22 22 22 22 23 23 23 23 23 23 2 Timer 1 1 counter register Low Byte 23 2 23 24 24 24 24 24 24 24 24 24 24 2 2 UART baud rate data register High Byte BRDATAH UART baud rate data register Low Byte BRDATAL SIO pre scalar register SIO data register Serial control register PWM data register High PWM data register LOW PWM control register LCD mod register LCD port control register Watch timer control register Flash memory sector register Hige byte Flash memory sector register Low byte Flash memory user enable regist
252. ol Register WTCON Set 1 Bank 1 F8H R W WTCON 1 Select fx 256 as the watch timer clock fx Main clock Select subsystem clock as watch timer clock Disable watch timer interrupt Enable watch timer interrupt 0 5 kHz buzzer BUZ signal output 1 kHz buzzer BUZ signal output 2 kHz buzzer BUZ signal output 4 kHz buzzer BUZ signal output Set watch timer interrupt to 0 5 s Set watch timer interrupt to 0 25 s Set watch timer interrupt to 0 125 s Set watch timer interrupt to 1 955 ms Disable watch timer clear frequency dividing circuits Enable watch timer Interrupt E not Bene clear pending bit when write Interrupt is pending WTCON 6 NOTE Main system clock frequency fx is assumed to be 9 8304 MHz WTCON 5 WTCON 3 2 Values 9 NEN 9 NECI ofo afo ESEN ofo afo 9 SAMSUNG ELECTRONICS 17 2 Lm 53 8419 UM REV3 00 17 Watch Timer 17 1 2 Watch Timer Circuit Diagram BUZZER Output BUZ SON WTCON 6 WTCON 4 WTINT fw 64 0 5 kHz WTCON 3 fw 32 fw 16 2 kHz WTCON 2 fw 8 4 kHz Enable Disable WTCON 1 Selector Circuit WTCON O Frequency Clock Mns WTCON 7 Selector Dividing 32768 Hz Circuit 5256 fx Main System Clock 9 8304MHz fxr Subsystem Clock 32768 Hz fw Watch timer Figure 17 1 Watch Timer Circuit Diagram SAMSUNG ELECTRONICS 17 3 Lm 53 8419 UM REV3 00 17 Watch Timer
253. on program that handles interrupt processing be sure to include the necessary register file address register pointer information EI S Q Interrupt Request Register Polling RESET R Read only Cycle IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM 0 manipulation Figure 5 4 Interrupt Function Diagram SAMSUNG ELECTRONICS 5 9 Lm S3F8419_UM_REV3 00 5 Interrupt Structure 5 8 Peripheral Interrupt Control Registers For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s set1 Timer B underflow TBCON TBDATAH TBDATAL D1H D2H Timer A overflow Timer 1 0 match capture Timer 1 0 overflow Timer 1 1 match capture P1 1 external 1 1 external interrupt P1INT EBH bank 0 P4 2 external interrupt 2 external EDT P1INTPND EAH bank 0 P1 3 external 1 3 extemal interrupt r UART receive transmit IRQ7 UDATA UARTPND F5H F4H bank 0 BRDATAH BRDATAL EEH EFH bank 1 NOTE If a interrupt is un mask Enable interrupt level in the IMR register the pending bit and enable bit of the interrupt should be written after a DI instruction is executed SAMSUNG ELECT
254. on register by one leaving the value OFH SAMSUNG ELECTRONICS 6 34 53 8419 UM REV3 00 6 Instruction Set 6 6 22 DECW Decrement Word DECW dst Operation dst lt dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 80 RR 81 IR Examples Given RO 12H R1 34H R2 30H register 30H and register 31H 21H DECW RRO gt 12H R1 33H DECW R2 gt Register 30H OFH register 31H 20H In the first example the destination register RO contains the value 12H and the register R1 the value 34H The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H NOTE A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem it is recommended to use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO JR NZ LOOP SAMSUNG ELECTRONICS 6 35 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 23 DI Disable Inter
255. ondition when write 1 Interrupt is pending Data direction control bit 0 MSB first mode 1 LSB first mode SIO interrupt enable bit 0 Disable SIO interrupt SIO mode selection bit 1 Enable SIO interrupt 0 Rececive only mode 1 Transmit Receive mode SIO shift operation enable bit 0 Disable shifter and clock counter Shift clock edge selection bit 1 Enable shfter and clcok counter 0 Tx falling edges Rx at rising edges 1 Tx rising edges Rx at falling edges SIO counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 14 1 Serial I O Interface Control Register SIOCON SAMSUNG ELECTRONICS 14 2 e 53 8419 UM REV3 00 14 Serial I O interface 14 1 3 SIO Prescaler Register SIOPS The control register for serial I O interface module SIOPS is located in Set 1 Bank 1 at FOH The value stored in the SIO prescaler registers SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock Fxx 4 SIOP 1 or external SCK input clock SIO Pre Scaler Registers SIOPS FOH SET1 Bank 1 R W Baud Rate Fxx 4 SIOPS 1 Figure 14 2 SIO Pre Scaler Register SIOPS 3 Bit Counter Clear SIOCON O Pending SIOCON 1 SIOCON 7 Interrupt Enable Shift Clock Source Select SIOCON 4 SIOCON 2 Edge Select Shift Enable SIOCON 5 Mode Select SIOPS F4H m CLK g Bit SIO Shift Buffer it SIODATA 5 RETE ee
256. or mode 1 is variable 15 2 2 1 Mode 1 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 1 8 bit UART by setting UARTCON bits 7 and 6 to 01B 3 Write transmission data to the shift register UDATA F5H The start and stop bits are generated automatically by hardware 15 2 2 2 Mode 1 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P1 4 pin will cause the UART module to start the serial data receive operation Tx ock Write to Shift Registe Transmit start Bi DO X D1 X D2 X D3 X D4 X D5 X D6 x D7 y Stop Bit 14 som 9 Cr XB X 5 X 9s X oe X Y Susi TTL TTL TTL TTL oe RIP Figure 15 7 Timing Diagram for UART Mode 1 Operation SAMSUNG ELECTRONICS 15 10 x_n S3F8419_UM_REV3 00 15 UART 15 2 3 UART Mode 2 Function Description In mode 2 11 bits are transmitted through the TxD pin or received through the RxD pin Each data frame has four components
257. output mode 11 Alternative function mode TBPWM Figure 9 7 Port 2 Low Byte Control Register P2CONL SAMSUNG ELECTRONICS eux 18 PORT CONTROL REGISTERS PAGE 9 13 PROGRAMMING TIP To make P2 as Normal I O or Alternative function ORG 0100H Reset address START DI SB1 LD LPOT 00H P2is normal I O or alternative function SBO LD P2CONH 00H P2isinput mode LD P2CONH 0AAH P2 is Push pull output mode LD P2CONH 0FFH P2is TXOUT RXOUT SCK OUT SO OUT SB1 LD LPOT 04FH P2isLCD port SBO LD P2CONH 0AAH If you use P2 as LCD port P2CONH register value doesn t care LD P2PUR 00H P2PUR is disabled when P2 is used as a LCD port SAMSUNG ELECTRONICS 19 PORT CONTROL REGISTERS PAGE 9 15 Port 3 Control Register Low Byte PSCONL Set1 R W Reset value 00 7 6 P3 3 SEG7 Configuration Bits 0 0 2 Input mode 0 1 Input modewith pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P3 2 SEG6 Configuration Bits 0 0 2 Input mode 0 1 2 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P3 1 SEG5 Configuration Bits 0 0 2 Input mode 0 1 2 Input modewith pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P3 0 SEG4 Configuration Bits 0 0 Input mode 0 1 Input modewith pull up 1 0 Push pull output mode 1 1 N channel open drain output Figure 9 10 Port 3 Low Byte Control
258. per register of pair working register Load flash memory lower address into lower register of pair working register Write data 33H at flash memory location Reset address in the same sector by INC instruction Check whether the end address for programming reach 407FH or not Programming stop User Program mode disable 20 9 IT 53 8419 UM REV3 00 20 Embedded Flash Memory Interface Case3 Programming to the Flash Memory Space Located in Other Sectors WR INSECTOR2 LD R0 40H LD R1 40H SB1 LD FMUSR 0A5H User Program mode enable LD FMCON 01010001B Programming mode enable LD FMSECH 01H Set sector address located in target address to write data LD FMSECL 00H SECTOR2 sector base address 100 LD R9 0CCH Load data CCH to write LD R10 201H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register WR_BYTE LD 0 40 WR 50 LD FMSECH 19H Set sector address located in target address to write data LD FMSECL 00H 50 sector base address 1900H LD R9 55H Load data 55H to write LD R10 19H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE WR_INSECTOR128 LD FMSECH 40H Set sector address locate
259. ply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 6 55 ms 216 fosc fosc 10 MHz When a reset occurs during normal operation with both VDD and nRESET at High level the signal at the nRESET pin is forced Low and the reset operation starts All system and peripheral control registers are then set to their default hardware reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The S3C8418X F8418X 8419X F8419X has a built in low voltage reset circuit that allows detection of power voltage drop of external VDD input level to prevent a MCU from malfunctioning in an unstable MCU power level This voltage detector works for the reset operation of MCU This Low Voltage reset includes an analog comparator and Vref circuit The value of a detection voltage is 2 8V and the value can be on and off by Smart option The on chip Low Voltage Reset features static reset when supply voltage is below a reference voltage value Typical 2 8 V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and stati
260. pro e GW PRO2 8 gang programmer 23 1 9 Development Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools 23 1 10 8 bit In Circuit Emulator OPENice i500 System TEL 82 31 223 661 1 FAX 82 331 223 6613 E mail openice aijisystem com URL http www aijisystem com SK 1200 TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com SAMSUNG ELECTRONICS 23 9 a 53 8419 00 23 1 11 OTP MTP Programmer Writer SAMSUNG ELECTRONICS SPW uni Single OTP MTP FLASH Programmer Download Upload and data edit function PC based operation with USB port Full function regarding OTP MTP FLASH MCU programmer Read Program Verify Blank Protection Fast programming speed 4 Kbyte sec Support all of SAMSUNG OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC New devices will be supported just by adding device files or upgrading the software AS pro On board programmer for Samsung Flash MCU Portable amp Stand alone Samsung OTP MTP FLASH Programmer for After Service Small size and Light for the portable use Support all of SAMSUNG OTP MTP FLASH devices HEX file download via USB port from PC Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second Internal large buffer memory 118M B
261. r Read Program Verify Blank Protection Two kind of Power Supplies User system power or USB power adapter Support Firmware upgrade SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com SAMSUNG ELECTRONICS US pro Portable Samsung OTP MTP FLASH Programmer e Portable Samsung OTP MTP FLASH Programmer e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices e Convenient USB connection to any IBM compatible PC or Laptop computers e Operated by USB power of PC e PC based menu drive software for simple operation e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Support Samsung standard Hex or Intel Hex format e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Support Firmware upgrade SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com GW PRO2 Gang Programmer for OTP MTP FLASH MCU 8 devices programming at one time Fast programming speed 1 2Kbyte sec PC based control operation mode or Stand alone Full Function regarding OTP MTP program Read Program Verify Protection Blank e Data back up even at power break After setup in Design Lab it can be moved to the factory site Key Lock protecti
262. r LMOD A LMOD is located in SET 1 BANK 1 at address F6H and is read write addressable using register addressing mode It has the following control functions e LCD duty and bias selection e LCD clock selection e LCD display control e COM signal output control The LMOD register is used to turn the LCD display on off to select duty and bias to select LCD clock to control and to turn the COM signal output on off Following a RESET all LMOD values are cleared to 0 This turns off the LCD display select 1 3 duty and 1 3 bias and select 256Hz for LCD clock The LCD clock signal determines the frequency of COM signal scanning of each segment output This is also referred as the LCD frame frequency Since the LCD clock is generated by watch timer clock fw The watch timer should be enabled when the LCD display is turned on LCD Mode Control Register LMOD F6H SET1 BANK1 R W Not used LCD clock selection bits 00 fw 2 256 Hz when fw is 32 768 kHz nw fw 2 512 Hz when fw is 32 768 kHz EE COM pins high impedance fw 25 1024 Hz when fw is 32 768 kHz control bit i fw 2 2048 Hz when fw is 32 768 kHz 0 Normal COMs signal output 1 High impendane COM pins LCD duty and bias selection bits 00 1 3 duty 1 3 bias COMO COMe SEGO SEG19 Not used 01 1 4 duty 1 3 bias COMO COMS SEGO SEG19 10 1 8 duty 1 4 bias 7 SEGO SEG15 11 1 8 duty 1 5 bias 7 SEGO
263. ram mode enable FMSECH 2 Set Sector 4 200H 27FH FMSECL 00H You can set FMSECL from 00H to 7FH FMCON 10100001B Start sector erase FMUSR 0 User Program mode disable Example 20 2 Sector Erase To Use an Interrupt FMUSR 0A5H User Program mode enable FMSECH 2 Set Sector 4 200H 27FH FMSECL 00H You can set FMSECL from 00H to 7FH REPEAT FMCON 10101001B Start sector erase and enable INT during erasing FMCON 4 Sector erase fail flag check NZ REPEAT if failed repeat Sector erase FMUSR 0 User Program mode disable SAMSUNG ELECTRONICS 20 7 Lm 53 8419 UM REV3 00 20 Embedded Flash Memory Interface 20 4 Programming A flash memory is programmed in one byte unit after sector erase And for programming safety s sake must set FMSECH FMSECL to flash memory sector value The write operation of programming starts by LDC instruction The program procedure in User program Mode 1 2 Must erase sector before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Control Register FMCON to 01010001B Set Flash Memory Sector Address Register FMSECH FMSECL to sector value of the address to write data Load a transmission data into a working register Load a flash memory upper address into upper register of pair working register Load a flash memory lower address into lower register of pair working register Load transmission data to fla
264. re 14 4 Figure 14 5 Figure 14 6 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 15 5 Figure 15 6 Figure 15 7 Figure 15 8 Figure 15 9 Figure 16 1 Figure 16 2 Figure 16 3 Figure 16 4 Figure 16 5 Figure 17 1 Figure 18 1 Figure 18 2 Figure 18 3 Figure 18 4 Figure 18 5 Figure 18 6 Figure 18 7 Figure 18 8 Figure 18 9 Figure 19 1 Figure 20 1 Figure 20 2 Figure 20 3 Figure 20 4 Figure 20 5 Figure 21 1 Figure 21 2 Figure 21 3 Figure 21 4 Figure 21 5 Figure 21 6 Figure 21 7 Figure 21 8 SAMSUNG ELECTRONICS PWM Functional Block DI8gf8m 13 6 Serial I O Interface Control Register SIOCON sess 14 2 SIO Pre Scaler Register SIOPS 14 3 SIO Functional Block 14 3 Serial I O Timing Transmit Receive Mode Tx at falling SIOCON 4 0 14 4 Serial I O Timing Transmit Receive Mode Tx at rising SIOCON 4 1 14 4 Serial I O Timing Receive Only Mode l L nnne nnne 14 5 UART Control Register 15 3 UART Interrupt Pending Register UARTPND 15 4 UART Data Register dedi eite eee Eee de ED n Eia 15 6 UART Baud Rate Data Register BRDATAH BRDATAL
265. register leaving 04H in the general register 00H SAMSUNG ELECTRONICS 6 50 eu 53 8419 UM REV3 00 6 Instruction Set 6 6 37 LDC LDE Load Memory LDC LDE Operation Flags Format 10 NOTE dst src dst src dst lt src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes Irr or rr values an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 10 C3 r Irr opc src dst 2 10 D3 Irr r opc dst src XS 3 12 E7 r XS rr opc src dst XS 3 12 F7 XS rr r opc dst src XLL XLH 4 14 A7 r XL rr opc src dst XLL XLH 4 14 B7 XL rr r opc dst 0000 DAL DAH 4 14 A7 r DA src 0000 DAL DAH 4 14 B7 DA r opc dst 0001 DAL DAH 4 14 A7 r DA opc src 0001 DAL DAH 4 14 B7 DA r 1 The source src or the working register pair rr for formats 5 and 6 cannot use the register pair 0 1 2 Forthe formats 3 and 4 the destination XS rr and the source address XS rr are both one byte 3 Forthe formats 5 and 6 the destination XL rr and the source address XL rr are both two bytes 4 The DA and the r source values for the formats 7 and 8 are used to address program memory T
266. register appropriately Refer to Ex 2 below to use a P2 as Normal or Alternative function SO SCK RxD TxD you must set register appropriately Refer to Ex 1 below For example 1 LD LPOT 00000000B 2 LD LPOT 01001111B P2 4 P2 7 is Normal I O or Alternative function SO SCK RxD TxD P2 4 P2 7 is LCD port For more detail please refer to page 9 13 SAMSUNG ELECTRONICS 8 CONTROL REGISTERS P3CONH Port 3 Control 7 6 PAGE 4 27 Register High Byte EEH Set 1 P3 7 SEG11 Configration Bits mame Fo t mumoewhpuup KEE Push pull output mode N channel open drain output P3 6 SEG10 Configration Bits O 0 mpumode j 0 1 mpumodewthpulup __ 1 Push pulloutputmode ____ N channel open drain output P3 5 SEG9 Configration Bits o __ 0 1 mpumodewthpulup __ 1 Push pulloutputmode __ N channel open drain output P3 4 SEG8 Configration Bits Push pull output mode If you want below For example 1 LD LPOT 00000000B 2 LD LPOT 01001111B N channel open drain output NOTE If you want to use P3 as a LCD port you must set LPOT register appropriately Refer to Ex 2 below to use P3 as a Normal I O you must set LPOT register appropriately Refer to Ex 1 P3 4 P3 7 is Normal I O P3 4 P3 7 is LCD port For more detail please ref
267. register pointer 0 RPO at the location OD6H to 40H and the register pointer 1 RP1 at the location OD7H to 48 H The statement SRPO 50H would set RPO to 50H and the statement SRP1 68H would set RP1 to 68H NOTE Before execute the STOP instruction You must set the STPCON register as 101001010 Otherwise the STOP instruction will not execute SAMSUNG ELECTRONICS 6 79 e 53 8419 UM REV3 00 6 Instruction Set 6 6 65 STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 4 Example The statement STOP halts all microcontroller operations SAMSUNG ELECTRONICS 6 80 eux S3F8419_UM_REV3 00 6 6 66 SUB Subtract 6 Instruction Set SUB dst src Operation dst lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction
268. ressing The upper two 32 byte areas bank 0 and bank 1 of set 1 EOH FFH contains 64 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes 2 3 3 Register Set 2 The same 64 byte physical space that is used for set 1 locations is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For S3C8418X F8418X C8419X F8419X the set 2 address range COH FFH is accessible on pages 0 1 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations SAMSUNG ELECTRONICS 2 8 ea 53 8419 UM REV3 00 2 Address Spaces 2 3 4 Prime Register Space The lower 192 bytes
269. ressing Mode Register addressing mode only 7 0 Baud rate z Input clock fxx SIOPS 1 x4 SCK input clock 4 1 35 SPH Stack Pointer High Byte D8H Set 1 Bit Identifier 7 6 5 4 3 gt x x x x x x x x RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset 4 1 36 SPL Stack Pointer Low Byte D9H Set 1 RESET Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SP0 The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset SAMSUNG ELECTRONICS 4 34 ex 53 8419 UM REV3 00 4 Control Registers 4 1 37 STOPCON Stop Control Register E5H Set 1 Bank0 Bit Identifier 7 6 5 4 3 2 7 29 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE
270. rr r Given RO 77H R6 30H and R7 OOH RR6 lt RR6 1 77H the contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH RR6 lt RR6 1 77H the contents of RO is loaded into external data memory location 2FFFH 3000H 1H NOTE LDEPD instruction can be used to read write the data of 64 Kbyte data memory SAMSUNG ELECTRONICS 6 55 53 8419 00 6 6 41 LDCPI LDEPI Load Memory with Pre Increment 6 Instruction Set LDCPI dst src LDEPI dst src Operation rr rr 1 dst lt src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src src dst 2 14 F3 Irr r Examples Given RO 7FH R6 21H and R7 LDCPI RR6 RO RR6 lt bRR6 1 7FH the contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 lt bRR6 1 7FH the content
271. rts shared with segment common drive outputs e Four bit programmable pins for external interrupts e One 8 bit basic timer for oscillation stabilization and watchdog function system reset e Two 8 bit timer counter and Two 16 bit timer counter with selectable operating modes e One asynchronous UART and One synchronous SIO e One 10 bit PWM output e 10 bit 8 channel A D converter e Watch timer for real time S3C8418X F8418X C8419X F8419X is versatile microcontroller for home appliances and ADC applications etc They are currently available in 44 pin QFP and 42 SDIP Only for S3C8419X F8419X package SAMSUNG ELECTRONICS 1 2 eux 53 8419 UM REV3 00 1 3 Features CPU e SAMB8RC CPU core Memory e 528 bytes internal register file S3C84l9X F8419X e 272 bytes internal register 3 8418 8418 e 8 Kbytes program memory S3C8418X F8418X Half Flash e 32 Kbytes program memory 53 8419 8419 Full Flash User programmable by LDC instruction Endurance 10 000 Erase Program cycles Sector 128 byte Erase available Oscillation Sources e Main clock oscillator Crystal Ceramic e clock divider 1 1 1 2 1 8 1 16 Instruction Set e 78 instructions e IDLE and STOP instructions added for power down modes Instruction Execution Time e 400 ns at 10 MHz fOSC minimum Interrupts e 16 interrupt sources with 16 vectors e 8 level 16 vector interrupt structure
272. rupt Falling Edge 11 Enable Interrupt Rising Edge Figure 9 5 Port 1 Interrupt Enable Register P1INT SAMSUNG ELECTRONICS 9 8 ea 53 8419 UM REV3 00 9 I O Ports 9 2 3 Port 2 Port 2 is an 8 bit port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank 0 2 0 2 7 can serve as digital inputs outputs push pull or you can configure the following alternative functions e General purpose digital I O e Alternative function SEGO SEG3 ADC4 ADC7 SI TT CAPO TTOUTO TBPWM PWM 9 2 3 1 Port 2 Control Register P2CONH P2CONL Port 2 has two 8 bit control registers 2 for 2 4 2 7 and P2CONL for P2 0 P2 3 A reset clears the P2CONH and P2CONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 2 control registers must also be enabled in the associated peripheral module 9 2 3 2 Port 2 Pull up control Registers P2PUR Using the port 2 pull up control register P2PUR FA SET1 BANKO you can configure pull up resistors to individual port 0 pins SAMSUNG ELECTRONICS 9 9 eux 53 8419 UM REV3 00 9 I O Ports Port 2 Control Register High Byte P2CONH ECH Se
273. rupts DI Operation Flags Format Example SYM 0 0 Bit zero of the system mode control register 0 is cleared to globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM 01H Di If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing SAMSUNG ELECTRONICS 6 36 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 24 DIV Divide Unsigned DIV Operation Flags Format dst src dst src dst UPPER lt REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 2 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers C Set if the V flag is set and the quotient is between 2 and 2 1 cleared otherwise Z Set if the divisor or the quotient 0 cleared otherwise S Set if MSB of the quotient 1 cleared oth
274. rval timer Capture mode PWM mode e Select the timer 1 0 1 input clock frequency e Clear the timer 1 0 1 counter TTCNTHO LO T1CNTH1 L1 e Enable the timer 1 0 1 overflow interrupt e Enable the timer 1 0 1 match capture interrupt T1CONO is located in set 1 and Bank 1 at address E8H and is read write addressable using Register addressing mode T1CON1 is located in set 1 and Bank 1 at address E9H and is read write addressable using Register addressing mode A reset clears T1CONO T1CON 1 to 00H This sets timer 1 0 1 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer 1 0 1 interrupts To disable the counter operation please set T1CON 0 1 7 5 to 111B You can clear the timer 1 0 1 counter at any time during normal operation by writing a 1 to T1CON 0 1 3 The timer 1 0 overflow interrupt T1OVFO is interrupt level IRQ2 and has the vector address C6H And the timer 1 1 overflow interrupt T1OVF1 is interrupt level IRQ2 and has the vector address CAH To generate the exact time interval you should write 1 to T1CON 0 1 2 and clear appropriate pending bits of the TINTPND register To detect a match capture or overflow interrupt pending condition when T1INTO T1INT1 or T1OVFO T1OVF1 is disabled the application program should poll the pending bit TINTPND register bank 1 address EOH When a 1 is detected a timer 1 0 1 match capture or overflow interrupt is pending
275. s 4 1 8 FLAGS System Flags Register D5H Set 1 Bit Identifier _ 7 6 5 3 2 j a x x x x x x 0 0 RESET Value Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C EN Operation does not generate a carry or underflow condition Operation generates a carry out or underflow into high order bit 7 6 Zero Flag Z ES Operation result is a non zero value Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 Operation generates a negative number MSB 1 4 Overflow Flag V ER Operation resultis lt 127 or gt 128 Operation resultis gt 127 or lt 128 3 Decimal Adjust Flag D E Add operation completed Subtraction operation completed 2 Half Carry Flag H No carry out of bit 3 or no underflow into bit 3 by addition or subtraction Addition generated carry out of bit 3 or subtraction generated underflow into bit 3 Fast Interrupt Status Flag FIS EN Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag Bank 0 is selected Bank 1 is selected SAMSUNG ELECTRONICS 4 10 x_n 53 8419 UM REV3 00 4 Control Registers 4 1 9 IMR Interrupt Mask Register DDH Set 1 Bit Identifier 7 8 4 3 2 4 29 x x x x x x x RESET Value x Read Write R W R W R W R W R W R W R W R W Addressing Mode Regis
276. s There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide e No special I O instructions I O control data registers are mapped directly into the register file e Decimal adjustment included in binary coded decimal BCD operations e 16 bit word data can be incremented and decremented e Flexible instructions for bit addressing rotate and shift operations 6 1 1 Data Types The CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit 6 1 2 Register Addressing To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces 6 1 3 Addressing Modes There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes SAMSUNG ELECTRONICS 6 1 Lm 53 8419 UM RE
277. s 35H and the program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example SAMSUNG ELECTRONICS 6 25 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 14 CCF Complement Carry Flag CCF Operation Flags Format Example C NOTC The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero If C 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one SAMSUNG ELECTRONICS 6 26 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 15 CLR Clear CLR Operation Flags Format Examples dst dst lt 0 The destination location is cleared to 0 No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 BO R 4 B1 IR Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR 00H gt Register 00H 00H CLR 801 gt Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register OOH value to 00H In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H regi
278. s by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W Interrupt level enable 0 Disable mask interrupt level 1 Enable un mask interrupt level Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR SAMSUNG ELECTRONICS 5 12 Lu S3F8419_UM_REV3 00 5 Interrupt Structure 5 11 Interrupt Priority Register IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority i
279. s fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ4 GroupC IRQ5 IRQ6 IRQ7 IPR IPR IPR Group A Group B Group C A1 A2 B1 B2 C1 C2 B21 B22 C21 C22 IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B C A The setting 101B would select the relationship C B A The functions of the other IPR bit settings are as follows e PR 5controls the relative priorities of group C interrupts e Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C e PR O controls the relative priority setting of IRQO and IRQ1 interrupts SAMSUNG ELECTRONICS 5 13 a 53 8419 UM REV3 00 Group priority 07 D4 01 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 SAMSUNG ELECTRONICS 5 Interrupt Structure Interrupt Priority Register IPR FFH Set 1 Bank 0 R W ve
280. s of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H NOTE LDEPI instruction can be used to read write the data of 64 Kbyte data memory SAMSUNG ELECTRONICS T 53 8419 UM REV3 00 6 Instruction Set 6 6 42 LDW Load Word LDW Operation Flags Format Examples dst src dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 C4 RR RR 8 C5 RR IR dst src 4 8 C6 RR IML Given R4 06H R5 R6 05H R7 02H register register 01H 02H register 02H 03H and register 03H OFH LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register 00H 03H register 01 OFH register 02H 03H register 03H OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04H 01H gt Register 04H 03H register 05H OFH LDW RR6 1234H gt R6 12H R7 34H LDW 02H fOFEDH gt Register 02H register OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H and 03H into the destination word 00H and 01H This leaves the value 03H in the general register OOH and the value OFH in the register 01H Other examples show how to
281. s other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W Destination register page selection bits Source register page selection bits Destination Page 0 Source Page 0 Destination Page 1 Source Page 1 Destination Page 2 Source Page 2 In the 53 8419 8419 microcontroller page 0 1 2 are implemented In the S8C8418X F8418X microcontroller page 0 2 are implemented A hardware reset operation writes the 4 bit destination and source values shown above to the register page 00 These values should be modified to other pages Figure 2 5 Register Page Pointer PP Example 2 1 Using the Page Pointer for RAM clear Page 0 Page 1 Destination 4 0 Source 0 Page 0 RAM clear starts RO 00H Destination 4 1 Source lt 0 Page 1 RAM clear starts SAMSUNG ELECTRONICS 2 7 ex 53 8419 UM REV3 00 2 Address Spaces 2 3 2 Register Set 1 The term set 1 refers to the upper 64 bytes of the register file locations COH FFH The upper 32 byte area of this 64 byte space EOH FFH is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 add
282. s program codes or table data The 53 8419 8419 has 32Kbytes of internal mask programmable program memory and the S3C8418X F8418X has 8Kbytes of internal mask programmable program memory The program memory address range is therefore OH 7FFFH and OH 1FFFH see Figure 2 1 The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal 32 767 Internal Program Memory Flash S3F8419X SAMSUNG ELECTRONICS Decimal 8 192 S3F8419X 32Kbyte Internal Program Memon Flash S3F84I8X 8Kbyte ISP Sector Interrupt Vector Area Smart Option Rom Cell S3F8418X Figure 2 1 Program Memory Address Space 53 8419 UM REV3 00 2 Address Spaces 2 2 1 Smart Option Smart option is the ROM option for starting condition of the chip The ROM addresses used by smart option are from 003CH to 003FH The default value of ROM is FFH ROM Address 003CH Not used ROM Address 008DH Not used ROM Address 003EH Not used ISP Protection size selection 00 256 bytes 01 512 bytes 10 1024 bytes 11 2048 bytes ISP Protection enable disable bit 0 Enable Not erasable by L
283. s reduced to less than 3 pA except for the current consumption of LVR Low voltage Reset circuit All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts NOTE Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage 8 2 1 1 Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock 1 16 because CLKCON 3 and CLKCON 4 are cleared to 00B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H 8 2 1 2 Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C8418X F8418X 8419X F8419X interrupt structure that can be used to release Stop mode are e External interrupts P1 0 P1 3 INTO INT3 Pleas
284. sh memory location area on LDC instruction by indirectly addressing mode Set Flash Memory User Programming Enable Register FMUSR to 000000008 SAMSUNG ELECTRONICS 20 8 ea 53 8419 UM REV3 00 Case1 1BYTE Programming FMUSR 0A5H FMCON 01010001B FMSECH 40H FMSECL 00H R9 0AAH R10 40H R11 10H RR10 R9 FMCON 01010000B FMUSR 00H Case2 Programming in the Same Sector WR_INSECTOR LD RO 40H SB1 LD FMUSR 0A5H LD FMCON 01010001B LD FMSECH 40H LD FMSECL 00H LD R9 33H LD R10 40H LD R11 40H RR10 R9 R11 RO WR BYTE FMCON 01010000B FMUSR 00H SAMSUNG ELECTRONICS 20 Embedded Flash Memory Interface Example 20 3 Programming Write data to flash memory address 4010H User Program mode enable Programming mode enable Set flash sector address Set sector address of pointer to write data Load data AA to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Write data AAH at flash memory location 4010H Programming stop User Program mode disable RR10 gt Address copy R10 high address R11 low address User Program mode enable Programming mode enable Set sector address located in target address to write data SECTOR128 sector base address 4000H Load data 33H to write Load flash memory upper address into up
285. sing Samsung products notwithstanding Copyright 2013 Samsung Electronics Co Ltd Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea 446 711 Contact Us prodakim samsung com Home Page http www samsungsemi com SAMSUNG ELECTRONICS any information provided in this publication Customer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim including but not limited to personal injury or death that may be associated with such unintended unauthorized and or illegal use WARNING No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung This publication is intended for use by designated recipients only This publication contains confidential information including trade secrets of Samsung protected by Competition Law Trade Secrets Protection Act and other related laws and therefore may not be in part or in whole directly or indirectly publicized distributed photocopied or used including in a posting on the Internet where unspecified access is possible by any unauthorized third party Samsung reserves its right to take any
286. ster pointers 0 selects RPO 1 selects RP1 e five high order bits in the register pointer select an 8 byte slice of the register space e The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 14 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 15 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B SAMSUNG ELECTRONICS 2 17 e 53 8419 UM REV3 00 2 Address Spaces Selects RPO or RP1 Address OPCODE sma 4 bit address Register pointer prov ides three prov ides five low order bits high order bits LN Together they create an 8 bit register address Figure 2 14 4 bit Working Register Addressing RPO 01110 000 Selects RPO R6 OPCODE Register 01110 11 0 address 76H Figure 2 15 4 bit Working Register Addressing Exa
287. ster value to 00H SAMSUNG ELECTRONICS 6 27 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 16 COM COM Operation Flags Format Examples Complement dst dst NOT dst The contents of the destination location are complemented one s complement All 1s are changed to Os and vice versa Unaffected Set if the result is 0 cleared otherwise Always reset to 0 2 S Set if the result bit 7 is set cleared otherwise V D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 60 R 4 61 IR Given R1 07H and register 07H OF 1H COM R1 gt 1 OF8H COM R1 gt R1 07H register 07H OEH In the first example the destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and logic zeros to logic ones leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of the destination register 07H 11110001B leaving the new value OEH 00001110B SAMSUNG ELECTRONICS 6 28 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 17 CP Compare CP Operation Flags Format Examples dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both opera
288. success 1 Sector Erase fail INT enable bit during sector erase 0 INT disable 1 INT enable Figure 20 1 Flash Memory Control Register FMCON You can select whether to use interrupt or not during Flash Sector erase process If you set FMCON 3 to 0 you don t use interrupt during Flash Sector erase process If you set FMCON 3 to 1 you use interrupt during Flash Sector erase process If you intended to use some interrupts during Flash Sector erase you must check Sector Erase Fail Flag after Flash Sector erase is done Please refer to page 20 7 SAMSUNG ELECTRONICS 20 3 Lm 53 8419 UM REV3 00 20 Embedded Flash Memory Interface 20 2 2 Flash Memory User Programming Enable Register After reset the user programming mode is disabled because the value of FMUSR is 000000008 If necessary you can use the user programming mode by setting the value of FMUSR is 10100101B Flash Memory User Programming Enable Register FMUSR FBH Set1 Bank 1 R W Flash Memory User Programming Enable bits 10100101 Enable user programming mode Other values Disable user programming mode Figure 20 2 Flash Memory User Programming Enable Register FMUSR SAMSUNG ELECTRONICS 20 4 eux 53 8419 UM REV3 00 20 Embedded Flash Memory Interface 20 3 Sector Erase User can erase a flash memory partially by using sector erase function only in User Program Mode The only unit of flash memory to be erased and written in User Program Mode is call
289. t 0 No interrupt pending 1 Interrrupt pending Timer 1 1 match capture interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer A match capture pending bit interrupt 0 No interrupt pending 1 Interrrupt pending Timer A overflow pending 0 No interrupt pending 1 Interrrupt pending Timer 1 0 match capture interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 0 overflow interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Figure 12 2 SAMSUNG ELECTRONICS Timer A Timer 1 0 1 Pending Register TINTPND 53 8419 UM REV3 00 12 16 bit Timer 1 0 1 12 1 3 Block Diagram T1CON 7 5 T1CON 0 fxx 1024 gt Overflow 256 fxx 64 8 1 16 bit Up Counter _ gt Read Only V s 16 bit Comparator Data Bus TICK gt ty M U X 16 bit Timer Data Register TI DATAH L 4 3 Data Bus T1CON 4 3 NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 12 3 Timer 1 0 1 Functional Block Diagram SAMSUNG ELECTRONICS 12 7 Lm 53 8419 UM REV3 00 12 16 bit Timer 1 0 1 Example 12 1 Using the Timer 1 0 ORG 0000h VECTOR OC4h TIM1 INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt LD IMR 00001000b Enable IRQ2 interrupt LD SPL 00000000b LD BTCON 10100011b Dis
290. t Request Register DCH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R Addressing Mode Register addressing mode only 7 Inte rupt Level 7 IRQ7 Request Pending Bit Not pending le Pending 6 Interrupt Level 6 IRQ6 Request Pending Bit Not pending le Pending 5 Interrupt Level 5 IRQ5 Request Pending Bit Not pending Pending e 4 Interrupt Level 4 IRQ4 Request Pending Bit Not pending le Pending 3 Interrupt Level 3 IRQ3 Request Pending Bit Not pending le Pending 2 Interrupt Level 2 IRQ2 Request Pending Bit Not pending ee Pending 1 Interrupt Level 1 IRQ1 Request Pending Bit Not pending Pending le 0 Interrupt Level 0 IRQO Request Pending Bit Not pending Pending SAMSUNG ELECTRONICS 4 14 53 8419 UM REV3 00 4 Control Registers 4 1 14 LMOD LCD Mode Control Register F6H Set 1 Bank1 Bit Identifier 4 5 4 RESET Value 0 0 0 Read Write _ R W RAN RAN RAN R W R W 7 Not used for S3C8418X F8418X C8419X F8419X 6 COM Pins High Impedance Control Bit LO Normal COMs signal output 1 COM pins are at high impedance Not used for S3C8418X F8418X C8419X F8419X 4 LCD Display Control Bit Display off cut off the LCD voltage dividing resistors Normal display on 3 2 LCD Duty and Bias Selection Bits 1 8 duty 1 3 bias 0 2 5 0 5 019 0 1 1 4
291. t mechanism in the event of a system malfunction e signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are e Clock frequency divider fxx divided by 4096 1024 or 128 with multiplexer e 8 bit basic timer counter BTCNT set 1 bank 0 FDH read only e Basic timer control register BTCON set 1 D3H read write 10 1 2 Basic Timer Control Register BTCON The basic timer control register BT CON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using register addressing mode A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of fXX 4096 To disable the watchdog function write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON 4 The 8 bit basic timer counter BTCNT set 1 bank 0 FDH can be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers write a 1 to 0 SAMSUNG ELECTRONICS 10 1 Lm 53 8419 UM REV3 00 10 Basic Timer Basic Timer Control Register BTCON D3H Set 1 R W ve e Watchdog timer enable bit Divider clear bit 1010B Disable watchdog function 0 No effect Other valu
292. t used 1 0 Push pull output mode 11 Alternative function mode PWM 7 6 P2 0 TBPWM T1CKO Configuration Bits 0 0 Input mode T1CKO 0 1 Alternative function mode T1CKO 1 0 Push pull output mode 11 Alternative function mode TBPWM Figure 9 7 Port 2 Low Byte Control Register P2CONL SAMSUNG ELECTRONICS 9 11 Lm 53 8419 UM REV3 00 9 I O Ports Port 2 Pull up Control Register P2PUR FAH Set1 R W Reset value 00 7 P2 7 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 6 P2 6 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 5 P2 5 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 4 P2 4 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 3 P2 3 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 2 P2 2 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 1 P2 1 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 0 P2 0 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable Figure 9 8 Port 2 Pull up Control Register P2PUR SAMSUNG ELECTRONICS 9 12 Lm 53 8419 UM REV3 00 9 I O Ports Example 9 2 To make P2 as Normal I O or Alternative function ORG
293. t1 Bank0 R W Reset value 00 MSB 7 6 4 2 1 0 168 SAMSUNG ELECTRONICS 7 6 P2 7 SEG3 TxD Configuration Bits 0 0 2 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode TxD output 5 4 P2 6 SEG2 RxD Configuration Bits 0 0 Input mode RxD iput 0 1 Alternative function mode Not used 1 0 Push pull output mode 11 Alternative function mode RxD output 3 2 P2 5 SEG1 SCK Configuration Bits 0 0 Input mode SCK 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode output 1 0 P2 4 SEGO0 SO Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode SO output Figure 9 6 Port 2 High Byte Control Register P2CONH 9 10 en 53 8419 UM REV3 00 9 I O Ports Port 2 Control Register Low Byte P2CONL EDH Set1 R W Reset value 00 7 6 P2 3 AD7 SI Configuration Bits 0 0 Input mode SI 0 1 Alternative function mode Not used 1 0 Push pull output mode 11 Alternative function mode AD7 7 6 P2 2 ADA T1OUTO Configuration Bits 0 0 Input mode 0 1 Alternative function mode T1OUTO 1 0 Push pull output mode 11 Alternative function mode AD4 7 6 P2 1 PWM T1CAPO Configuration Bits 0 0 Input mode T1CAPO 0 1 Alternative function mode No
294. ta n nennen nennen nns nnns innen en 13 2 PWM Output stretch Values for Extension Data Register PWMDATAL 1 0 13 3 Commonly Used Baud Rates Generated by 16bit 15 7 Watch Timer Control Register WTCON Set 1 Bank 1 F8H 17 2 Common and Segment Pins per Duty 9 18 3 Descriptions of Pins Used to Read Write the Flash 20 1 Comparison of SSF8418X F8419X and S3C8418X C8419X Features 20 2 Absolute Maximum Ratings eicit ee pitt e no es ERR eda Pas 21 2 Input Output nnns innen en 21 2 D C Electrical Characteristics UU L 00 enne 21 3 A C Electrical Characteristics U L 21 5 Main Oscillator Frequency fOSC1 21 6 Main Oscillator Clock Stabilization Time 1671 2040 4 0000 21 6 Sub Oscillator Frequency 05 2 21 7 SAMSUNG ELECTRONICS ex Table 21 8 Table 21 9 Table 21 10 Table 21 11 Table 21 12 Table 21 13
295. ted as the LCD clock source the LCD display is enabled even during main clock stop and idle modes LCD Controller Driver COM4 SEG19 COM7 SEG16 UJ D 9 c o SEGO P2 4 SEG15 P4 3 Figure 18 1 LCD Function Diagram SAMSUNG ELECTRONICS 18 1 Lm 53 8419 UM REV3 00 18 LCD Controller Driver 18 1 1 LCD Circuit Diagram O SEG15 P4 3 SEG Display Control RAM Page2 Selector O SEGO P2 4 e 2 m v COM OCOMT7 SEG16 P4 4 Control Controller OF selector OCOM4 SEG19 P4 7 COM COMSF0 0 LCD Voltage Control Figure 18 2 LCD Circuit Diagram SAMSUNG ELECTRONICS 18 2 Lm 53 8419 UM REV3 00 18 LCD Controller Driver 18 1 2 LCD RAM Address Area RAM addresses of page 2 are used as LCD data memory It is Write only memory When the bit value of a display segment is 1 the LCD display is turned on when the bit value is 0 the display is turned off Display RAM data are sent out through segment pins SEGO SEG19 using a direct memory access DMA method that is synchronized with the signal SEGO SEG1 SEG2 SEG3 SEG17 SEG18 SEG19 b 201H 202H 208H 211H 212H 213H b Figure 18 5 LCD Display Data RAM Organization Table 18 1 Common and Segment Pins per Duty Cycle SAMSUNG ELECTRONICS 18 3 Lm 53 8419 UM REV3 00 18 LCD Controller Driver 18 1 3 LCD Mode Control Registe
296. ter the register OOH is then incremented by one changing its value from 01H to 02H SAMSUNG ELECTRONICS 6 64 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 50 PUSH Push to Stack PUSH Operation Flags Format Examples src SP lt SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register OAAH SPH and SPL PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value 0000H and the general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of the register 40H into the location OFFFFH and adds this new value to the top of the stack SAMSUNG ELECTRONICS 6 65 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 51 PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example
297. ter OOH leaving the value 55H 01010101B The MSB of the register 00H resets the carry flag to 1 and sets the overflow flag SAMSUNG ELECTRONICS 6 71 e 53 8419 UM REV3 00 6 Instruction Set 6 6 57 RR Rotate Right RR Operation Flags Format Examples dst C lt dst 0 dst 7 lt dst 0 dst n dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C C Setifthe bit rotated from the least significant bit position bit zero was 1 Z Setif the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 EO R 4 E1 IR Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H gt Register 00H 98H 1 801 Register 01H 02H register 02H 8BH C 1 In the first example if the general register 00H contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets th
298. ter addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit Disable mask 1 Enable un mask 6 Interrupt Level 6 IRQ6 Enable Bit Disable mask le Enable un mask 5 Interrupt Level 5 IRQ5 Enable Bit Disable mask Enable un mask le 4 Interrupt Level 4 IRQ4 Enable Bit Disable mask le Enable un mask 3 Interrupt Level 3 IRQ3 Enable Bit Disable mask le Enable un mask 2 Interrupt Level 2 IRQ2 Enable Bit Disable mask le Enable un mask 1 Interrupt Level 1 IRQ1 Enable Bit Disable mask Enable un mask le 0 Interrupt Level 0 IRQO Enable Bit Disable mask 1 Enable un mask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU SAMSUNG ELECTRONICS 4 11 53 8419 UM REV3 00 4 Control Registers 4 1 10 IPH Instruction Pointer High Byte DAH Set 1 Bit Identifier 7 5 4 3 2 7 29 x x x x x x x x RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH 4 1 11 IPL Instruction Pointer Low Byte DBH Set 1 Bit Identifier _5 4 3 2 a x x x x x x x RESET Value x Read
299. terrupt Pending No interrupt pending ES Clear pending bit when write Interrupt pending SAMSUNG ELECTRONICS 4 41 a 53 8419 UM REV3 00 4 Control Registers 4 1 44 UARTCON UART Control Register F6H Set 1 Bank0 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 6 Operating mode and baud rate selection bits Mode 0 Shift Register fxx 16 x 16bit BRDATA 1 oo o 1 Mode UART et BROATA D 1 Mode 2 9 bit UART fxx 16 x 16bit BRDATA 1 5 Multiprocessor communication 1 enable bit for mode 2 only Disable Enable 4 Serial data receive enable bit Disable Enable 3 If Parity disable mode 0 location of the 9th data bit to be transmitted in UART mode 2 0 or 1 If Parity enable mode PEN 1 even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data 2 If Parity disable 0 location of the 9th data bit that was received in UART mode 2 0 or 1 If Parity enable mode PEN 1 even odd parity selection bit for receive data in UART mode 2 0 Even parity check for the received data 1 Odd parity check for the received data A result of parity error will be saved in RPE bit of the UARTPND register after parity checking of the received data Receive Interrupt Enabl
300. the capture input by setting the value of the timer 1 0 capture input selection bit in the port 0 control register high POCONH set 1 bank0 E6H Both kinds of timer 1 0 interrupts T1OVFO can be used in capture mode the timer 1 0 overflow interrupt is generated whenever a counter overflow occurs the timer 1 0 capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading the captured data value in T1DATAHO T1DATALO and assuming a specific value for the timer 1 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAPO pin In capture mode for Timer 1 1 a signal edge that is detected at the T1CAP1 pin opens a gate and loads the current counter value into the timer 1 data register T1DATAH1 T1DATAL1 for rising edge falling edge You can select rising or falling edges to trigger this operation The timer 1 1 also gives you capture input source the signal edge at the T1CAP1 pin You select the capture input by setting the value of the timer 1 1 capture input selection bit in the port 0 control register low POCONL set 1 bank0 E7H Both kinds of timer 1 1 interrupts T1OVF1 T1INT1 can be used in capture mode the timer 1 1 overflow interrupt is generated whenever a counter overflow occurs the timer 1 1 capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading t
301. tion 0105H 01H 0104H RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 0 R3 04H RO lt contents of program memory location 1104H RO 88H RO lt contents of external data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H 11H contents of RO is loaded into external data memory location 1105H 1105H 11H NOTE The LDC and the LDE instructions are not supported by masked ROM type devices SAMSUNG ELECTRONICS 6 52 en 53 8419 UM REV3 00 6 Instruction Set 6 6 38 LDCD LDED Load Memory and Decrement LDCD dst src LDED dst src Operation dst lt src rr rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD refers to program memory and LDED refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format dst src Examples Bytes Cycles Opcode Addr Mo
302. tor Erase INT disable INT enable 2 Sector Erase Fail Flag Sector Erase success 1 Sector Erase fail Not used for the 53 8418 8418 8419 8419 0 Flash Mode Start Bit With Out Programming Mode amp Reading Mode Stop bit 1 Start bit auto cleared SAMSUNG ELECTRONICS x_n 53 8419 UM REV3 00 4 Control Registers 4 1 5 FMSECH Flash Memory Sector Register High byte F9H Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 4 o 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W 7 0 Flash Memory Sector address Bits You have to input High address of sector that s accessed 4 1 6 FMSECL Flash Memory Sector Register Low byte FAH Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W 7 0 Flash Memory Sector address Bits You have to input Low address of sector that s accessed NOTE f you want to erase Sector 8 200H 27FH you have to set 02H to FMSECH and 00H 7FH to FMSECL 4 1 7 FMUSR Flash Memory User Programming Enable Register FBH Set 1 Bank1 Bit Identifier 7 6 5 4 3 2 4 o 0 0 0 0 0 0 0 RESET Value 0 Read Write R W R W R W R W R W R W R W R W 7 0 Flash Memory User Programming Mode Selection Bits Disable user programming mode 10100101 Enable user programming mode SAMSUNG ELECTRONICS 4 9 Lm 53 8419 UM REV3 00 4 Control Register
303. tor IC to bright light Exposure to bright light causes malfunctioning of the devices However a few special products that utilize light or with security functions are exempted from this guide Radioactive Cosmic and X ray Radioactive substances cosmic ray or X ray may influence semiconductor devices These substances or rays may cause a soft error during a device operation Therefore ensure to shield the semiconductor devices under environment that may be exposed to radioactive substances cosmic ray or X ray EMS Electromagnetic Susceptibility Strong electromagnetic wave or magnetic field may affect the characteristic of semiconductor devices during the operation under insufficient PCB circuit design for Electromagnetic Susceptibility EMS SAMSUNG ELECTRONICS ax Revision History Revision No Date Description Author s 1 00 Nov 2006 e First edition T H Kim 2 00 Jun 2007 e Second edition T H Kim 3 00 Dec 2013 e Third edition J I Kim SAMSUNG ELECTRONICS Revision Descriptions for Revision 2 00 Samsung 8 bit CMOS S3C8418X F8418X C8419X F8419X Microprocessor User s Manual Document Number 02 2 00 S3 C8418X F8418X C8419X F8419X 062007 Publication June 2007 1 PIN ASSIGNMENT PAGE 1 4 INTO TAOUT P1 0 INT1 BUZ TACK P1 1 SDAT INT2 TACAP P1 2 SCLK INTS T1OUT1 P1 3 VDD VSS Xout Xin Vpp TEST Xtin Xtout OI 44 L3 P4 7 SEG19 COM7 43 C P 4 6 5
304. trol register 283 0 O ojo Timer 1 0 counter register high T1CNTHO 234 EA byte H Timer 1 0 counter register low byte T1CNTLO 235 H Timer 1 1 counter register high T1CNTH1 236 EC byte H Timer 1 1 counter register low byte TICNTL1 237 H UART baud rate data register high BRDATAH UART baud rate data register low BRDATAL SiO pre scalar register 1 9028 240 Foo 0 SiO data register SIODATA 24 Fi 0 0 0 o Jo 0 0 0 Serial VO control register SIOCON 242 rad o 0 ojo 0 0 0 PWM data register high PWMDATAH 243 FSH 0 O 0 0 0 PWM data register ow PWMDATAL 244 0 0 0 0 o PWM contotregster Pwmoon 26 Fn oo o Flash memory sector register FMSECH 249 high byte Flash memory sector register FMSECL 250 low byte Flash memory user enable register FMUSR B SAMSUNG ELECTRONICS 8 4 Lu 53 8419 UM REV3 00 8 RESET and Power Down Register Name EI nn 7 6 543210 Location F9H are not mapped SAMSUNG ELECTRONICS 8 5 ea 53 8419 UM REV3 00 8 RESET and Power Down 8 2 Power Down Modes 8 2 1 Stop Mode Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current i
305. ts fmm Fo r mumwewmpdu 0 Push pullouputmede P4 5 COM5 SEG17 Configration Bits Fo input mode wih pukup a o 4 4 COM4 SEG16 Configration Bits ofo mame Fo t mumoewhpuup ESEA Push pull output mode N channel open drain output NOTE If you want to use asa LCD port you must set register appropriately Refer to Ex 2 below If you want below For example 1 LD LPOT 00000000B 2 LD LPOT 01001111B to use Normal you must set LPOT register appropriately Refer to Ex 1 P4 4 P4 7 is Normal I O P4 4 P4 7 is LCD port For more detail please refer to page 9 19 SAMSUNG ELECTRONICS 11 CONTROL REGISTERS PAGE 4 30 PACONL Port 4 Control Register Low Byte F1H Set 1 P4 3 BUZ SEG15 Configration Bits mame o i Push pull output mode N channel open drain output P4 2 SEG14 Configration Bits o 0 1 mpumodewthpulup _ 1 Push pulloutputmode N channel open drain output P4 1 SEG13 Configration Bits OO Inputmode j 0 1 mpumodewthpulup __ 1 Push pulloutputmode __ N channel open drain output P4 0 SEG12 Configration Bits O o mume o irou mode winpop Push pull output mode
306. ts and the LSB address value is one bit in length Example Given R1 07H BITR R1 1 gt 1 05 If the value the working register R1 is 07H 000001 11B the statement R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101 SAMSUNG ELECTRONICS 6 19 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 8 BITS Bit Set BITS dst b Operation dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst dst b 1 2 4 77 rb NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R1 3 gt 1 OFH If the working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B SAMSUNG ELECTRONICS 6 20 eux 53 8419 UM REV3 00 6 Instruction Set 6 6 9 BOR Bit OR BOR BOR Operation Flags Format dst src b dst b src dst 0 lt dst 0 OR src b or dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified
307. uction If a malfunction does occur a reset is triggered automatically 10 2 2 Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an external interrupt When BTONT 4 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts 2 power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an external interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source 3 Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows 4 When a 4 overflow occurs normal CPU operation resumes SAMSUNG ELECTRONICS 10 3 Lm 53 8419 UM REV3 00 10 Basic Timer RESET or STOP Bits 3 2 Basic Timer Control Register y Write 1010xxxxB to disable
308. umber MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format 4 4 53 8419 UM REV3 00 4 Control Registers 4 1 1 ADCON A D Converter Control Register F7H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write _ RAN RAN RAN R RAN RAN RAN Addressing Mode Register addressing mode only 7 Not used for the S3C8418X F8418X C8419X F84I9X must keep always 0 6 4 A D Input Pin Selection Bits 3 End of Conversion Bit Read only A D conversion opration is in progress A D conversion opration is complete 2 1 Clock Source Selection Bits 0 Start or Enable Bit EN Disable operation Start operation SAMSUNG ELECTRONICS as x_n 53 8419 UM REV3 00 4 Control Registers 4 1 2 BTCON Basic Timer Control Register D3H Set 1 Bit Identifier 7 6 5 4 3 2 4 O 0 0 0 0 0 0 0 0 RESET Value Read Write R W RAN RAN RAN RAN RAN RAN RAN Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset Disable watchdog timer function Other Vaules Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer 2 No effect Clear both clock frequency dividers NOTE 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operatio
309. upt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed SAMSUNG ELECTRONICS 5 4 eux 53 8419 UM REV3 00 5 Interrupt Structure Levels Vectors Sources Reset Clear BEH IRQO Timer B underflow COH Timer A match capture H W S W IRQ1 C2H Timer A overflow H W S W C4H Timer 1 0 match capture H W S W C6H Timer 1 0 overflow H W S W C8H Timer 1 1 match capture H W S W CAH Timer 1 1 overflow H W S W CEH P1 0 external interrupt S W DOH P1 1 external interrupt S W D2H P1 2 external interrupt S W D4H P1 3 external interrupt S W Watch timer S W SIO receive transmit PWM overflow interrupt UART data receive UART data transmit NOTES 1 Within a given interrupt level the lower vector address has high priority For example DCH has higher priority than DEH within the level IRQ5 the priorities within each level are set at the factory External interrupts are triggered by a rising or f
310. upt request is not pending pending bit clear when write 0 1 Interrupt request is pending SAMSUNG ELECTRONICS 4 21 Lm 53 8419 UM REV3 00 4 Control Registers 4 1 21 P1INT Port 1 Interrupt Enable EBH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 s Interrupt Enable Disble Selection Bit 5 4 Interrupt Enable Falling edge Interrupt Enable Rising edge 3 3 1 0 SAMSUNG ELECTRONICS 4 22 Lm 53 8419 UM REV3 00 4 Control Registers 4 1 22 P2CONH Port 2 Control Register High Byte ECH Set 1 Bit Identifier 7 6 8 4 3 2 4 0 0 0 0 0 0 0 0 RESET Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 SEG3 TxD Configration Bits 00 Input mode n Alternative function mode Not used 1 0 Push pull output mode Alternative function mode TxD output 5 4 P2 6 SEG2 RxD Configration Bits Co o mumuemoma Fo uncton 1 Pushputlouputmode ____ 3 2 P2 5 SEG1 SCK Configration Bits o mumoe skmu Fo AmawefutonmodeNotued Pr 0 Push pul ouputmode _ 2 1 0 2 4 5 0 5 Configration Bits fo Input mode oji Alternative function mode Not used Push pull output mode Alternative function mode SO output NOTE If you want to use a P2 as
311. upt structure the timer B underflow interrupt IRQO belongs to this category of interrupts in which pending condition is cleared automatically by hardware 5 13 3 Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the S3C8418X F8418X C8419X F841I9X interrupt structure pending conditions for IRQ3 IRQ4 IRQ5 IRQ6 and IRQ7 must be cleared in the interrupt service routine SAMSUNG ELECTRONICS 5 16 eux S3F8419_UM_REV3 00 5 Interrupt Structure 5 14 Interrupt Source Polling Sequence The interrupt request polling and servicing sequence is as follows 1 2 A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the interrupt level of source The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests 5 14 1 Interrupt Service Routines Before an interrupt request is serviced the following conditions
312. ure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 points to OPERAND working register block Value used in Instruction Program Memory Wod Base Address 3 LSBs dst src x L Instruction Point to One of the Example Woking Register 1 Sample Instruction LD RO 4BASE R1 Where BASE is 8 bit immediate value Figure 3 7 Indexed Addressing to Register File SAMSUNG ELECTRONICS 3 7 Lm 53 8419 UM REV3 00 Program Memory OFFSET OPCODE 4 bit Working Register Address Sample Instructions LDC R4 04H RR2 LDE R4 04H RR2 Figure 3 8 SAMSUNG ELECTRONICS 3 Addressing Modes Register File MSB Points to RPO or RP1 gt RPO 1 Register Pair Selected RP points to start of working register block NEXT 2 Bits Point to Working Register Pair 1 of 4 16 Bit address added to p Program Memory offset or Data Memory LSB Selects 8 Bits 16 Bits Value used in Instruction OPERAND 16 Bits The values in the program address RR2 04H are loaded into register R4 Identical operation to LDC example except that external program memory is accessed Indexed Addressing to Program or Data Memory with Short
313. use the LDW instruction with various addressing modes and formats SAMSUNG ELECTRONICS 6 57 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 43 MULT Multiply Unsigned MULT Operation Flags Format Examples dst src dst dst x src The 8 bit destination operand the even numbered register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers C Setifthe result is 255 cleared otherwise Z Setif the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Given Register 00H 20H register 01H 03H register 02H 09H register O3H 06H MULT 00H 02H gt Register 00H 01H register 01H 20H register 02H 09H MULT OOH 01H gt Register OOH OOH register 01 OCOH MULT OOH 30H gt Register 06H register 01H 00H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H SAMSUNG ELECTRONICS 6 58 ex 53 8419 UM REV3 00 6 Instruction Set 6 6 44
314. utput pin selection COM pin selection varies according to the selected duty cycle e In 1 3 duty mode 0 2 pins are selected e In 1 4 duty mode pins are selected e In 1 8 duty mode 7 pins are selected 18 1 7 Segment SEG Signals The 19 LCD segment signal pins are connected to corresponding display RAM locations at page 2 Bits of the display RAM are synchronized with the common signal output pins When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 no select signal to the corresponding segment pin SAMSUNG ELECTRONICS 18 6 Lu 53 8419 UM REV3 00 18 LCD Controller Driver ma 10111213 14151617101 2 3 141516 7 come Br JL JL NN cows DOMO 1 Frame coms JL IE TL coms OOO VDD VLc2 VLC4 Vpp VLC1 VLc2 VLC4 Vss Vpp VLC1 VLc2 VLC4 Vpp VLC1 VLc2 VLC4 Vss 1 AVLCD 5 0 OV 1 4VLcD Figure 18 7 LCD Signal Waveforms 1 8 Duty 1 4 Bias SAMSUNG ELECTRONICS 18 7 Lu 53 8419 UM REV3 00 18 LCD Controller Driver 0111213 01112 3 4 1 Frame VDD VLC1 VLC2 VLcs VLC4 Vss VDD VLC1 VLC2 Vic3 VLc4 Vss VDD VLC1 VLC2 VLcs VLC4 Vss VDD VLC1 VLC2 VLcs VLC4 Vss V
315. value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 72 r r 6 73 r Ir src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO 0C7H R1 02H R2 18H register 2BH register 01H 02H and register 02H 23H RO R1 E RO OC7H R1 02H Z 0 RO R1 gt RO OC7H R1 02H register 02H 23H Z 0 TM 00H O1H gt Register OOH 2BH register 01H 02H Z 0 TM 00H Q01H gt Register 00H 2BH register 01 02H register 02H 23H Z 0 TM 00H 54H gt Register 00H 2BH Z 1 In the first example if the working register RO contains the value 0C7H 11000111B and the register R1 the value 02H 0000001 0B the statement TM RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation 179 53 8419 UM REV3 00 6 Instruction Set 6 6 70 WFI
316. ve Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 2 and set the receive enable bit RE in the UARTCON register to 1 3 If you don t use a parity mode set PEN bit of UARTPND register to to disable parity mode If you want to use the parity enable mode select the parity type to be check by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 1 Only 8 bits BitO to Bit7 of received data are available for data value 4 The receive operation starts when the signal at the RxD pin goes to low level SAMSUNG ELECTRONICS 15 11 ex 53 8419 UM REV3 00 15 UART Je n L L fL J Write to Shift Register UARTDATA G C __ L s TxD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit TIP TB8 or Parity bit n n n n sampe re TTL JTTLTTTLITTLITTLITTLITTLITTL Shift RIP Transmit Figure 15 8 Timing Diagram for UART Mode 2 Operation SAMSUNG ELECTRONICS 15 12 ea 53 8419 UM REV3 00 15 UART 15 2 4 Serial Communication for Multiprocessor Configurations The S3C9 series multiprocessor communication features let a master S3C8418X F8418X 8419X F8419X send multiple frame serial message to a slave device in a multi S3C8418X F8418X 84I9X F8419X configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART
317. w occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the Timer A data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin SAMSUNG ELECTRONICS 11 2 a 53 8419 UM REV3 00 11 8 bit Timer A B 11 1 3 Timer A Control Register TACON You use the timer A control register TACON to e Select the timer A operating mode interval timer capture mode and PWM mode e Select the timer A input clock frequency e Clear the timer A counter TACNT e Enable the timer A overflow interrupt or timer A match capture interrupt e Clear timer A match capture interrupt pending conditions TACON is located in set 1 Bank 1 at address E1H and is read write addressable using Register addressing mode A reset clears TACON to 00H This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at any time during normal operation by writing a 1 to TACON 3 The timer A overflow interrupt is interrupt level IRQ1 and has the vector address C2H When a timer A overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer A match capture interrupt IRQ1 vector COH you must wr
318. watch timer 0 Watch Timer Interrupt Pending Bit Interrupt is not pending Interrupt is pending Lo SAMSUNG ELECTRONICS 4 45 x_n S3F8419_UM_REV3 00 5 Interrupt Structure Interrupt Structure 5 1 Overview The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources 5 1 1 Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQO IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C8418X F8418X C84I9X F8419X interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority reg
319. x 64 U x 8 bit Up Counter Read Only 8 bit Comparator a TACK Es V Timer A Buffer Reg N Timer A Data Register Read Write TACON 5 4 Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 11 2 Timer A Functional Block Diagram SAMSUNG ELECTRONICS 11 4 TACON 5 4 11 8 bit Timer A B TAOUT TAPWM 53 8419 00 11 8 bit Timer A B 11 2 8 Bit Timer B 11 2 1 Overview The S8C8418X F8418X 8419X F8419X micro controller has an 8 bit timer called timer B Timer B which can be used to generate the carrier frequency of a remote controller signal Also it can be used as the programmable buzz signal generator that makes a sound with a various frequency from 200 Hz to 20 kHz These various frequencies can be used to generate a melody sound Timer B has two functions e Asanormal interval timer generating a timer B interrupt at programmed time intervals e To generate a programmable carrier pulse for a remote control signal at P2 0 11 2 2 Block Diagram TBCON 6 7 TBCON 2 PG trigger signal 0 fxx 4 Y gt U D CLK 8 Bit TBPWM P2 0 60 64 x Down Counter TB Underflow fxx 256 gt TBUF TBCON 1 Repeat Control TBCON 4 5 Timer B Data Timer B Data Low Byte Register High Byte Register Data Bus Data Bus NOTE In case of setting TBCON 5 4 at 10 the value of the TBDATAL reg
320. y The UARTCON 3 8 is for settings of the even parity generation TB8 0 or the odd parity generation TB8 0 in the transmit mode The UARTCON 2 888 is also for settings of the even parity checking RB8 0 or the odd parity checking RB8 1 in the receive mode The parity enable generation checking functions are not available in UART mode 0 and 1 If you don t want to use a parity mode UARTCON 2 RB8 UARTCON 3 TB8 are normal control bit as the 9th data bit in this case PEN must be disable 0 in mode 2 Also it is needed to select the 9th data bit to be transmitted by writing TB8 to or 1 The receive parity error flag RPE will be set to 0 or 1 depending on parity error whenever the 8th data bit of the receive data has been shifted SAMSUNG ELECTRONICS 15 5 ea S3F8419_UM_REV3 00 15 UART 15 1 4 UART Data Register UDATA UART Data Register UDATA F5H Set1 Bank 0 R W Reset Value FFH Transmit or Receive data Figure 15 3 UART Data Register UDATA 15 1 5 UART Baud Rate Data Register BRDATAH BRDATAL The value stored in the UART baud rate register BRDATAH BRDATAL lets you determine the UART clock rate baud rate UART Baud Rate Data Register BRDATAH EEH Set1 Bank 1 R W Reset Value FFH BRDATAL EFH Set1 Bank 1 R W Reset Value FFH Brud rate data Figure 15 4 UART Baud Rate Data Register BRDATAH BRDATAL SAMSUNG ELECTRONICS 15 6 Lm S3F8419_UM_REV3
321. ytes Driver software run under various O S Windows 95 98 2000 XP Full function regarding OTP MTP programmer Read Program Verify Blank Protection Two kind of Power Supplies User system power or USB power adapter Support Firmware upgrade US pro Portable Samsung OTP MTP FLASH Programmer Portable Samsung OTP MTP FLASH Programmer Small size and Light for the portable use Support all of SAMSUNG OTP MTP FLASH devices Convenient USB connection to any IBM compatible PC or Laptop computers Operated by USB power of PC PC based menu drive software for simple 23 10 23 Development Tools SEMINIX TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com SEMINIX TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com SEMINIX TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com 53 8419 UM REV3 00 23 Development Tools operation Very fast program and verify time OTP 2Kbytes per second MTP 10 Kbytes per second Support Samsung standard Hex or Intel Hex format Driver software run under various O S Windows 95 98 2000 XP Full function regarding OTP MTP programmer Read Program Verify Blank Protection Support Firmware upgrade GW PRO2 Gang Programmer for OTP MTP FLASH MCU e 8 devices programming at one time Fast programming speed 1 2 Kbyte sec PC bas

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