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STM8S003K3 STM8S003F3

1. 0000 STM8S003K3 STM8S003F3 Value line 16 MHz STM8S 8 bit MCU 8 Kbytes Flash 128 bytes data EEPROM 10 bit ADC 3 timers UART LQFP32 7x7 TSSOP20 UFQFPN20 3x3 Features Core 16 MHz advanced STM8 core with Harvard architecture and 3 stage pipeline Extended instruction set Memories Program memory 8 Kbytes Flash data retention 20 years at 55 C after 100 cycles RAM 1 Kbytes Data memory 128 bytes of true data EEPROM endurance up to 100 000 write erase cycles Clock reset and supply management 2 95 to 5 5 V operating voltage Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitor Power management Low power modes wait active halt halt Switch off peripheral clocks individually Permanently active low consumption power on and power down reset January 2012 Interrupt management Nested interrupt controller with 32 interrupts Up to 27 external interrupts on 6 vectors Timers Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization 16 bit general purpose timer with 3 CAPCOM channels IC OC or PWM 8 bit basic timer with 8 bit prescaler Auto wak
2. Vpop 3 3 V high sink ports 74 Typical Vi and Vin vs Vpp 4 temperatures 76 Typical pull up resistance vs Vpp 4 temperatures 76 Typical NRST pull up current vs Vpp 4 temperatures 77 Recommended reset pin protection 77 SPI timing diagram slave mode 0 79 SPI timing diagram slave mode 1 79 SPI timing diagram master 80 Typical application with bus and timing diagram J a Ak aan 84 ADC accuracy characteristics 84 Figure 43 Typical application with ADC 85 Figure 44 32 pin low profile quad flat package 7 X 7 sse emm 89 Figure 45 20 pin 4 40 mm body 0 65 mm pitch 90 Figure 46 20 lead ultra thin fine pitch quad flat no lead package outline 3x3 92 Figure 47 6 99 5 85003 value line ordering information scheme 95 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Introduction 1 Introduction This datasheet contains the description of the device features pinout electrical characteristics mechanical data and ordering information For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference man
3. Q CPOL 1 x bg eo 50 in SO pte tr SCK tdis SO T Li MISO wsaour OUTPUT 01 MSBOUT OUT 150 91 gt MSB IN X en Y IN INPUT h S ai14134 Figure 39 SPI timing diagram slave mode and CPHA 1 NSS input SU NSS 4 gt i lt 8 58 4 1 i i I a 0 Lh Ny Ng x CPHA 1 t t H 9 CPOL 1 SGK ISO ae th SO 1 OUTPUT BITE OUT imo 2 Sl gt gt RIPE MSB IN IN LSB IN 14135 1 Measurement points are made at CMOS levels 0 3 VDD 0 7 VDD 0 0018576 Rev 2 79 99 Electrical characteristics STM8S003K3 STM8S003F3 Figure 40 SPI timing diagram master mode High NSS input lt te SCK CPHA 0 7 CPOL 0 A i amp CPHA 0 CPOL 1 YIN Fr CPHA 1 1 CPOL 0 N JJ N CPHA 1 CPOL 1 12 1 tw SCKH Isu MI 4 90 twSCKL S Mie gi MISO MSBIN LSB IN thw 1 Na X sor OUTUT SB OUT 100 SB OU ty MO th MO PIG SCK Input ai14136 1 Measurement points are made at CMOS levels 0 3 VDD and 0 7 VDD 9 3 9 interface character
4. ETR I C SCL T PB4 12 SPI NSS TIM2_CH3 HS CHAN TLI TIM1_CH3 HS PC3 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 5 2 3 STM8S003F3 TSSOP20 UFQFPN20 pin description Table 6 STM8S003F3 pin description Alternate function after remap option bit Default alternate function PD4 BEEP X Timer 2 TIM2 CH1 channel UART1 1 BEEP output 22 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Pinout and pin description Alternate function after remap option Default alternate UFQFPN20 a n PD5 AIN5 UART1 input 5 UART1 data transmit PD6 AIN6 UART1 _RX NRST 2 1 OSCIN I O PA2 OSCOUT VCAP TIM2_ CH3 SPI_ NSS input 6 UART1 data receive X jeu Resonator crystal in X X Port Resonator A2 crystal out 1 8 V regulator capacitor i X X Port Timer 2 SPI master A3 channel slave select AFR1 h Pot 12 data 1 5 break input AFR4 19 Port 2c clock ADC external B4 trigger AFR4 X X Port Timer 1 Top level C3 channel interrupt AFR3 Timer 1 inverted channel 1 AFR7 X Port Configurable Timer
5. Monitored conditions frequency band 16 MHz 16 MHz 8MHz 16 MHz Conforming to MHZ MHz ME 130 to 1 GHz SAE EMI level SAE EMI level 1 Data based on characterisation results not tested in production Absolute maximum ratings electrical sensitivity Based on three different tests ESD DLU and LU using specific measurement methods the product is stressed to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins the device 3 parts n 1 supply pin One model be simulated Human body model This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 49 ESD absolute maximum ratings Symbol Conditions Electrostatic discharge TA 25 C conforming to voltage JESD22 A114 Human body model VESD CDM Electrostatic discharge TALQFP32 package voltage 25 C conforming to Charge device model SD22 C101 0 0018576 Rev 2 87 99 Electrical characteristics STM8S003K3 STM8S003F3 Data based on characterization results not tested in production 9 3 11 6 Static latch up 88 99 Two complemen
6. ky DoclD018576 2 73 99 Electrical characteristics STM8S003K3 STM8S003F3 Figure 32 Vpp Vpp 5 V high sink ports Von Figure 33 Typ Vpp Vpp 3 3 V high sink ports Von WH V 9 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 41 NRST pin characteristics 74 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Electrical characteristics VIH NRST NRST input high lg 2 mA 0 7 x Vpp level voltage VOL NRST NRST output low level voltage t Rpu NRST NRST pull up resistor FP NRST NRST input not filtered pulse top NRST NRST output pulse 9 1 Data based on characterization results not tested in production li FP NRST NRST input filtered pulse 2 The Rpy pull up equivalent resistor is based on a resistive transistor Data guaranteed by design not tested in production ky DoclD018576 2 75 99 Electrical characteristics STM8S003K3 STM8S003F3 Figure 34 Typical NRST Vj and Vj vs Vpp 4 temperatures 4 05 85 V Figure 35 Typical NRST pull up resistance vs Vpp 4 temperatures 76 99 NRESET pultup resistor 0 0018576 Rev 2 STM8S003K3 ST
7. 1022 6 1021 IDEAL 1024 2 2 RE D 1 2 3 4 5 amp 7 A DD 1021 10221023 1024 V 1 Example of an actual transfer curve 2 The ideal transfer curve 84 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Electrical characteristics 9 3 11 9 3 11 1 9 3 11 2 3 End point correlation line Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 43 Typical application with ADC STM8 V 06V O Apl AINx 10 bit A D NNN NNN conversion 4 IL L CAIN 06V 1pA p CADC EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs FESD Functional electrostatic discharge positive and negat
8. PB3 AIN3 TIM1_ETR gt N PB2 AIN2 TIM1_CH3N 4 lt O O 5 1 2o SDA I O PB4 2 SCL Table 5 LQFP32 pin description Default alternate after remap option bit x Port A1 Resonator crystal in Port A2 Resonator crystal out Digital ground 1 8 V regulator capacitor Digital power supply SPI master slave select AFR1 X O oO oO O A 9 5 2 data 4 2 Analog input 3 Timer 1 external trigger A 9 X UH mi Analog input 2 Timer 1 inverted channel 3 N aa 0 0018576 Rev 2 19 99 Pinout and pin description STM8S003K3 STM8S003F3 gt a PB1 AIN1 TIM1_CH2N PBO AINO TIM1_CH1N 17 5 SPI NSS 1 TIM1 CH1 UART1 CK 20 1 2 PC4 1 22 PC5 SPI SCK I O 23 PC6 PI MOSI 24 25 PDO TIM1_BKIN CLK_CCO 26 PD1 SWIM 4 27 PD2 TIM2_CH3 20 99 0 0018576 Rev 2 option bit Analog input 1 Timer 1 inverted channel 2 Analog input 0 Timer 1 inverted channel 1 master slave select Timer 1 channel 1 UART1 clock channel 2 channel 3 channel 4 configurable clock output SPI master out slave in SPI master in slave out Timer 1 break
9. any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for and in the port pin characteristics section does not affect the ADC accuracy Table 46 ADC accuracy with Ran lt 10 3 3 V SS Jeonan Juni Total unadjusted error 2 MHz 4 MHz ky DoclD018576 2 83 99 Electrical characteristics STM8S003K3 STM8S003F3 pem s mM Differential linearity error fapc 2 MHz Integral linearity error fapc 2 MHz EET Data based on characterization results not tested in production 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for and in port pin characteristics does not affect the ADC accuracy Figure 42 ADC accuracy characteristics i023
10. ca d 14 4 9 14 4 10 TIM1 16 bit advanced control timer 14 4 11 TIM2 16 bit general purpose timer 15 4 12 TIM4 8 bit basic timer 15 4 13 Analog to digital converter ADC1 2 15 4 14 Communication interfaces 16 AM4 UART Mm 16 4 14 2 A naan 17 4 14 3 FO E AG 17 5 Pinout and pin description U u 18 5 1 STM8S003K3 LQFP32 pinout and pin description 2 18 5 2 STM8S003F3 TSSOP20 UFQFPN20 pinout and pin description 21 5 2 1 STM8S003F3 TSSOP20 pinout and pin description 21 5 2 2 STM8S003F3 UFQFPN20 pinout 22 5 2 3 STM8S003F3 TSSOP20 UFQFPN20 pin description 22 5 3 Alternate function remapping 24 6 Memory and register map M 25 6 1 Memory Map Q t a Us 25 6 2 Register u AALALA aaa 26 6 2 1 I O port hardware register map 26 6 2 2 General hardware register 2 2 27 6 2 3 CPU S
11. DoclD018576 2 89 99 Package information STM8S003K3 STM8S003F3 10 2 90 99 inches 8 800 9 000 9 200 0 3465 0 3543 0 3622 6 800 7 000 7 200 0 2677 0 2756 0 2835 et 0 600 0 750 0 0177 0 0236 10 0295 Values in inches are converted from mm and rounded to 4 decimal digits 20 pin TSSOP package mechanical data Figure 45 20 pin 4 40 mm body 0 65 mm pitch YA ME DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Package information Table 52 20 pin 4 40 mm body 0 65 mm pitch mechanical data qp pe 208 e pol T gt gt fo a em _ E pe f em T u T CNN CNN Values in inches are converted from mm and rounded to 4 decimal digits ky DoclD018576 2 91 99 Package information STM8S003K3 STM8S003F3 10 3 20 lead UFQFPN package mechanical data Figure 46 20 lead ultra thin fine pitch quad flat no lead package outline 3x3 103 A0A5 1 Drawing is not to scale Table 53 20 lead ultra thin fine pitch quad flat no lead package 3x3 mechanical data qe ee m p e 1 Values in inches are converted from mm and rounded to 4 decimal digits 92 99 DocID018576 Rev 2 ky STM8S003K3 STM8S003F3 Thermal characteristics 11 11
12. 0x00 50A0 CR1 External interrupt control register 1 50A1 CR2 External interrupt control register 2 0x00 50A2 to Reserved area 17 bytes 0x00 50B2 0x00 50B3 ram RST SR Reset status register 0x00 50B4 to Reserved area 12 bytes 0x00 50BF 0x00 50 0 CLK_ICKR Internal clock control register ra 50C1 CLK ECKR External clock control register Joxoosoce 50C2 Reserved area 1 Reserved area t Byte 0x00 50C3 CLK_CMSR Clock master status register 38 50 4 CLK_SWR Clock master switch register 28 99 00 0018576 Rev 2 ky 50 6 50 7 PRI 50C8 50C9 50CA STM8S003K3 STM8S003F3 Memory and register map Address Register label Register name Reset status 0x00 50CC E CLK HSITRIMR HSI clock calibration trimming register 0x00 50CD CLK SWIMCCR SWIM clock control register 0x00 50 to ReservLK ed area 3 bytes 0x00 50DO 0x00 50D1 WWDG WWDG CR WWDG control register 0x00 50D2 WWDG_WR WWDR window register 0x00 50D3 to 00 Reserved area 13 bytes 0x00 50EO IWDG IWDG KR IWDG key register 0x00 50 1 IWDG_PR IWDG prescaler register 0x00 50E2 IWDG_RLR IWDG reload register 0x00 50E3 to Reserved area 13 bytes 0x00 50EF O00509 50F0 AWU CSR1 AWU control status register 1 0x00 50F1 AWU APR AWU asynchronous prescaler buffer register raa 50F2 wur TBR AWU timebase selection register 0x00 50F3 BEEP BEEP CSR BEEP control s
13. 9 3 6 I O port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the for example or an external pull up or pull down resistor Table EIC static characteristics Input low level voltage d LE Input high level voltage Pull up resistor 5V Vin Ves Fast I Os Load 50 pF Rise and fall time 10 90 Standard and high sink Load 50 pF lt Digital input leakage current Vss 3 Vin SVpp lt lt Analog input leakage current Vss 3 VS Leakage current in adjacent Injection current 4 mA 1 Hysteresis voltage between Schmitt trigger switching levels Based characterization results not tested in production 2 Data based on characterisation results not tested in production 66 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 Electrical characteristics Figure 21 Typical Vi and Vj vs Vpp 4 temperatures ma 40 C 6 25 C 0 85 C _ 4 gt gt 3 d i n gt n 2 ga n 1 0 T T T T T T 1 25 3 3 5 4 45 5 55 6 Figure 22 Typical pull up resistance vs 4 temperatures 40 C 60 29C 85 C 55 nf ys s 45 2 gt 40 3
14. 21 14 TIM4 10 Pc 24 Reserved PCKEN20 4 6 Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources Wait mode In this mode the CPU is stopped but peripherals kept running The wakeup is performed by an internal or external interrupt or reset Active halt mode with regulator In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset 4 7 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watchdog tim
15. HSE crystal osc 16 MHz usc t clock 16 MHz 2 HSI osc 16 MHz in run mode 128 125 2 HSI RC ose 16 MHz code executed Ipp RUN from RAM fopu HSIR 16 12515625 kiz I MASTERS 128 kHz pasak 2 HSE crystal osc 16 MHz fcpu MASTER HSE user ext clock 16 MHz 16 MHz HSI RC osc 16 MHz fopu fuasrER 2 HSI osc 16 2 8 1 05 2 2 Supply current fopu faster 128 15 625 kHz HSI RC osc 16 MHz 8 fopu fuasrER LSI RC osc 128 128 kHz 0 57 in run mode f code executed MASTER HSI RC osc 16 MHz from Flash 128 125 kHz 2 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 52 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 Electrical characteristics 9 3 2 2 Total current consumption in wait mode Table 22 Total current consumption in wait mode at Vpp 5 V E ENS ES HSE crystal osc 16 MHz ae cpu HSE t clock 16 MHz 4 2 HSI osc 16 MHz pe Supply HSI RC osc 16 MHz 0 7 current in 125 kHz wait mode fopu fuaster 128 fopu fuaster 128 15 625 kHz 0 4 128 2 mo 2 Data based on characterization results not tested in production HSI RC osc 16 MHz 8 0 45
16. Output high level with 4 pins sourced lg 20 mA Vpp25V Data based characterization results not tested in production 0 0018576 Rev 2 69 99 Electrical characteristics STM8S003K3 STM8S003F3 70 99 Figure 24 Typ Vo 5 V standard ports Va V la ma Figure 25 Typ Vo 3 3 V standard ports 0 0018576 Rev 2 STM8S003K3 STM8S003F3 Electrical characteristics Figure 26 Typ Vo 5 V true open drain ports 2 40 2516 ma Figure 27 3 3 V true open drain ports 2 409 20 1 85 ky DoclD018576 2 71 99 Electrical characteristics STM8S003K3 STM8S003F3 Figure 28 Typ Vo Vpp 5 V high sink ports 0 5 10 15 20 25 la m Figure 29 Typ Vo 3 3 V high sink ports 72 99 00 0018576 2 ky STM8S003K3 STM8S003F3 Electrical characteristics Figure 30 Vpop 5 V standard ports Voo Wu V 0 2 4 6 8 10 12 Figure 31 Vpp Vpp 3 3 V standard ports WH V
17. 94 r r r r r 25 3 35 4 45 5 55 6 Voo V DoclD018576 2 67 99 Electrical characteristics STM8S003K3 STM8S003F3 Figure 23 Typical pull up current vs 4 temperatures 140 4 1204 1004 lt 5 80 5 40 C 2 604 NG 2 P d 25 T 404 85 Ve 20 2 Ld o 0 1 2 3 4 5 6 Table 38 Output driving current standard ports Output low level with 8 pins sunk 10 mA Vpp 5 V VoL Output low level with 4 pins sunk Output high level with 8 pins sourced Output high level with 4 pins sourced Data based on characterization results not tested in production Table 39 Output driving current true open drain ports Symb Output low level with 2 pins sunk Output low level with 2 pins sunk OL 68 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Electrical characteristics Output low level with 2 pins sunk OL 1 Data based on characterization results not tested in production Table 40 Output driving current high sink ports Symb Output low level with 8 pins sunk les 1G Vpp25V VoL Output low level with 4 pins sunk lig 0 mA 3 3 V 20 mA Output low level with 4 pins sunk oo SEN 5V Vou Output high level with 8 pins sourced lig 10 mA Vpp 5V Output high level with 4 pins sourced lo TAMA 3 3V
18. AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive Default alternate functions 1 Port alternate function TIM1_CH1N port C4 alternate function TIM1_CH2N AFR6 Alternate function remapping option 6 Reserved 5 Alternate function remapping option 5 Reserved AFR4 Alternate function remapping option 4 0 AFR4 remapping option inactive Default alternate functions 1 Port B4 alternate function ADC_ETR port B5 alternate function TIM1_BKIN AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive Default alternate function 1 Port C3 alternate function TLI AFR2 Alternate function remapping option 2 44199 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Option bytes Reserved AFR1 Alternate function remapping option 12 0 1 remapping option inactive Default alternate functions 1 Port alternate function NSS port D2 alternate function TIM2 CH3 AFRO Alternate function remapping option o 0 AFRO remapping option inactive Default alternate functions 1 Port C5 alternate function TIM2 CH1 port C6 alternate function TIM1 CH 1 port C7 alternate function TIM1 1 Refer to pinout description 2 Do not use more than remapping option in the same port It is forbidden to enable both AFR1 and AFRO ky DoclD018576 2 45 99 Electrical characteristics STM8S003K3 STM8S00
19. 1 C4 clock inverted output Timer channel 2 1 channel AFR7 4 Analog input 2 X Port SPI clock Timer 2 C5 channel 1 AFRO 0 0018576 Rev 2 23 99 PB5 c _ SDA TIM1_ BKIN PB4 wom SCL PC3 TIM1_CH3 TLI TIM1_ CH1N ia 5 PC4 CLK CCO TIM1_ CHYAIN2TIM1 CH2N PC5 SPI_SCK TIM2_ CH1 5 4 d Pinout pin description STM8S003K3 STM8S003F3 Alternate function after remap option bit Default alternate SPI master Timer 1 SPI MOSI out slave in channel 1 TIM1 CH1 AFRO SPI master Timer 1 SPI MISO in slave channel 2 TIM1 CH2 AFRO out SWIM data interface Analog Timer 2 input 3 channel 3 AFR1 PD3 AIN4 x 2 2 input 4 ETR Timer 2 2 trigger 1 I O pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings 2 When the MCU is in halt active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use 1 only in input mode if halt active halt is used in the application 3 In the open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to Vpp
20. 2 33 99 Memory register map STM8S003K3 STM8S003F3 EERE status 0x00 5317 to Reserved area 43 bytes 0x00 533F 0x00 5340 TIM4 TIM4 CR1 TIM4 control register 1 0 00 5341 Reserved 34 99 00 0018576 2 ky STM8S003K3 STM8S003F3 Memory and register map pF em E status 0x00 5349 to Reserved area 153 bytes 0x00 53DF 0x00 53E0 to ADC _DBxR ADC data buffer registers 0x00 53F3 0x00 53F4 to Reserved area 12 bytes 0x00 53FF ky 00 0018576 Rev 2 35 99 Memory register map STM8S003K3 STM8S003F3 status 0x00 540C ADC_AWSRH ADC analog watchdog status register high 0x00 540D ADC_AWSRL ADC analog watchdog status register low 0x00 540E ADC AWCRH ADC analog watchdog control register high 0x00 540F ADC_AWCRL ADC analog watchdog control register low 0x00 5410 to Reserved area 1008 bytes 0x00 57FF Depends on the previous reset source Write only register 6 2 3 CPU SWIM debug module interrupt controller registers Table 9 Habana aa controller registers CA 0 00 7F03 Program counter low Ox00 7F04 Ca X index register high 0 00 7 05 X index register low 36 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 Memory and register map TT Register name name Register name Resetstatus status 0x00 7FOB to 0x00 7F5F 0x00 7F60 CPU CFG_GCR Global configuration register 0x00 7F70 IT
21. ADC_ETR UART1 TX AIN5 HS H 2 19 1 PD2 HS AIN3 TIM2 CH3 UART1 RX AING HS PD6 CI 18 1 PD1 HS SWIM NRST DJ 4 17 FI HS SPI_MISO TIM1_CH2 OSCIN PA1 B 5 16 FT PC6 HS SPI MOSI TIM1_CH1 OSCOUT PA2 15 FI PC5 HS SPI_SCK TIM2_CH1 vss H7 14 3 HS TIM1_CH4 CLK_CCO AIN2 TIM1_CH2N vcAP 13 2 HS TIM1 CH3 TLI TIM1_CH1N vop H 9 12 ppa SCL ADC_ETR SPI NSS TIM2_CH3 HS 10 11 F PB5 TTC SDA TIM1 BKIN 1 HS high sink capability 4 0 0018576 Rev 2 21 99 Pinout and pin description STM8S003K3 STM8S003F3 2 True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 5 2 2 STM8S003F3 20 pinout Figure 5 STM8S003F3 UFQFPN20 pin pinout AIN4 TIM2_CH2 ADC_ETR 1 BEEP 2 CH1 UART1 AINS UART1 TX AING UART1 TIM2 CH3 AINS PD5 HS PD4 HS PDE HS HS a PD2 HS n o NRST 2 18 77 PDT HS SWIM OSCIN PA1 141 PC7 HS SPI_MISO TIM1_CH2 OSCOUT PA2 vss gt VCAP gt 1 2 3 13 PCe HS SPI MOSI TIM1_CH1 4 HS SPI SCK TIM2 CH1 5 5 CH4 CLK CCO AIN2 TIM1 CH2N a e o 3 TIM1 BKIN 2C SDA T PB5
22. Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 11 Option bytes Option Option Option bits Factory name byte no default 0 4800 Read out OPTO 7 0 0 00 protection ROP 0 4801 User boot OPT1 UBC 7 0 code UBC 0x4802 NOPT1 NUBC 7 0 0x4803 Alternate 2 AFR7 AFR6 AFR5 AFR4 AFR3 2 AFR AFRO function 0x4804 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO OxFF AFR 0x4805h Miscell LSI EN IWDG WWDG WWDG 0 00 option TRIM _HW _HW _HALT 0x4806 NOPT3 Reserved NHSI NLSI_ NIWDG NWWDG NWW OxFF TRIM EN HW _HW G_HALT 0x4807 Clock OPT4 Reserved EXT CLK CKAWU PRS C1 PRSCO option SEL 0x4808 NOPT4 Reserved NEXT NCKA NPRSC1 NPR OxFF CLK WUSEL SCO 0x4809 HSE clock OPT5 7 0 startup 0x480A NOPT5 NHSECNT 7 0 Table 12 Option byte description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol ky DoclD018576 2 41 99 Option bytes STM8S003K3 STM8S003F3 Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Page 0 defined as UBC memory writ
23. Parameter Conditions Supply current halt Flash in operating mode HSI clock 75 A DD H after wakeup H ky DoclD018576 2 55 99 Electrical characteristics STM8S003K3 STM8S003F3 Max at 85 Symbol Parameter Conditions Flash in power down mode HSI clock after wakeup Data based on characterization results not tested in production 9 3 2 5 Low power mode wakeup times Table 28 Wakeup times Wakeup time from 0 to 16 MHz See 2 twuwEn wait mode to run mode fepu fmaster 16 MHz Wakeup time active MVR voltage Flash in operating halt mode to run regulator 5 mode mode on Wakeup time active MVR voltage Flash in halt mode to run regulator power down mode on mode twu AH Wakeup time active MVR voltage Flash in operating halt mode to run regulator 5 mode mode ofr Wakeup time active MVR voltage Flash in halt mode to run regulator power down mode mode Wakeup time from Flash in operating mode 52 halt mode to run H 5 3 Flash in power down mode mode 1 Data guaranteed by design not tested in production 2 twuwen 2 X 1 fmaster X 1 fcpu 56 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Electrical characteristics 3 Measured from interrupt event to interrupt vector fetch Configured by the REGAH bit in the register 5 Configured by the AHALT bit in the FLA
24. Raisonance C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www raisonance com STM8 assembler linker Free assembly toolchain included the STVD toolset which allows you to assemble and link your application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family 0 0018576 Rev 2 97 99 Revision history STM8S003K3 STM8S003F3 14 Revision history Table 55 Document revision history YU 09 Jan 2012 Added Naw and for data EEPROM in Table 36 Flash program memory and data EEPROM Updated Rp in Table 41 NRST pin characteristics and Table 37 static characteristics Updated notes related to VcAp in Table 18 General operating conditions 98 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 4 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its
25. STM8S003K3 STM8S003F3 jP e Total current out of Vss ground lines sink y mE Output current sunk by any I O and control pin 2 Output current source by any I Os and control pin 3 4 INJ PIN Injected current on NRST pin Injected current on OSCIN pin Injected current other pin g 21 id 5 Total injected current sum of all I O and control pins 20 Data based on characterization results not tested in production All power and ground Vss pins must always be connected to the external supply must never be exceeded This is implicitly insured if Vy maximum is respected If Vy maximum cannot be respected the injection current must be limited externally to the ly pi Value A positive injection is induced by V y gt Vpp while a negative injection is induced by ViN lt Vss For true open drain pads there is no positive injection current and the corresponding Vi maximum must always be respected 9 accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for lins PIN and in the I O port pin characteristi
26. for T given in the previous table and the value for given in Thermal characteristics This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator ky DoclD018576 2 49 99 Electrical characteristics STM8S003K3 STM8S003F3 Figure 9 f pymax Versus MHz Functionality not guaranteed in this area F netioralitj ee er 40 to 85 C 2 95 4 0 5 0 5 5 Supply voltage Table 19 Operating conditions at power up power down sma ee R tvpp 7 1 minimum ooperating voltage Vpp min when the delay has elapsed Reset is always generated after delay The application must ensure that Vpp is still above the 9 3 1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cgy4 to the Vcap pin is specified in the Operating conditions section Care should be taken to limit the series inductance to less than 15 nH Figure 10 External capacitor ESR ESL uia doi Rleak 1 ESR is the equivalent series resistance and ESL is the equivalent inductance 50 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Electrical characteristics 9 3 2 Supply current characteristics The current consumption is measured as described in Pin input voltage 9 3 2 1 Total current consumption in run mode Th
27. is approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value Refer to crystal manufacturer for more details 9 Data based on characterization results not tested in production 2 tsu HsE IS the start up time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 18 HSE oscillator circuit diagram fHSE to cor o i gt m mel OSCIN 9 e Resonator Consumption control Resonator I hd CL OSCOUT STM8 HSE oscillator critical g equation 2 x fuse Rm 2Co Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification C Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 47 Grounded external capacitance Om gt gt 9 3 4 Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and High speed internal RC oscillator HSI Table 33 HSI oscillator characteristics Symbol Parameter Conditions Min e 1410
28. selectable ADC scan mode or with analog watchdog Values converted from AIN12 are stored only into the ADC_DRH ADC_DRL registers Communication interfaces The following communication interfaces are implemented UART 1 Full feature UART synchronous mode SPI master mode Smartcard mode IrDA mode single wire mode LIN2 1 master capability SPI Full and half duplex 8 Mbit s Up to 400 Kbit s UART1 Main features One Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers DoclD018576 2 ky STM8S003K3 STM8S003F3 Product overview 4 14 2 4 14 3 SPI master operation 8 bit data communication Maximum speed 1 Mbit s at 16 MHz fepy 16 LIN master mode Emission Generates 13 bit synch break frame Reception Detects 11 bit break fra
29. static characteristiCs a dei dene de n 66 Table 38 Output driving current standard ports 68 Table 39 Output driving current true open drain ports 68 Table 40 Output driving current high sink ports 69 Table 41 NRST pin characteristics 74 Table 42 SPI characteristics 78 Table 43 characteristics 1 cerco Add 80 Table 44 ADC characteristics 3 9 82 Table 45 ADC accuracy with Ran lt 10 KO 5 eee emen enne 82 Table 46 ADC accuracy with Ran lt 10 Rain Vpp 3 8 V 83 Table 4 7 EMS data pP 86 4 99 DoclD018576 Rev 2 STM8S003K3 STM8S003F3 List of tables Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 ducam 86 ESD absolute maximum ratings 2 nnd 87 Electrical sensitivities tte ed aeo aaa eda ee eed 88 32 pin low profile quad flat package mechanical data 89 20 pin 4 40 mm body 0 65 mm pitch mechanical data 91 20 lead ultra thin fine pitch quad flat no lead package 3x3 mechanical data 92 Thermal characteristics canes ceeds Fui e R
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31. 0 57 UN 1 2 Default clock configuration measured with all peripherals off Table 23 Total current consumption in wait mode at Vpp 3 3 V HSE crystal osc 1 1 16 MHz fcPu faster HSE user ext clock 16 MHz 16 MHz HSI RC osc 16 MH Supply current me i in wait mode fopy fuaster 128 HSI RC osc 125 kHz 16 MHz fopy faster 128 HSI RC osc 15 625 kHz 16 2 icon S LSI RC osc 128 kHz 128 kHz ky DoclD018576 2 53 99 Electrical characteristics STM8S003K3 STM8S003F3 1 2 9 3 2 3 Default clock configuration measured with all peripherals off Data based on characterization results not tested in production Total current consumption in active halt mode Table 24 Total current consumption in active halt mode at Vpp 5V Symbol Parameter Supply current in pD active halt mode Supply current in DD active halt mode Supply current in DD active halt mode Supply current in DD active halt mode Supply current in DD AH active halt mode 1 Supply current in DD AH active halt mode AH AH H Conditions Flash mode Operating mode Operating mode Power down mode Power down mode Operating mode Power down mode Configured by the REGAH bit in the CLK ICKR register 3 Configured by AHALT bit in the FLASH register Clock source HSE crystal osc 16
32. 1 11 2 Thermal characteristics The maximum chip junction temperature max must never exceed the values given in Operating conditions The maximum chip junction temperature T may in degrees Celsius may be calculated using the following equation ymax TAmax Oja Where 9 Timax is the maximum ambient temperature in C O is package junction to ambient thermal resistance in C W Ppmax is the sum of PiNTmax and Pintmax Pintmax 5 the product of Ipp andVpp expressed in Watts This is the maximum chip internal power Promax represents the maximum power dissipation on output pins Where 2 2 taking into account the actual Vo and of the I Os at low and high level in the application Table 54 Thermal characteristics Thermal resistance junction ambient 84 C W TSSOP20 4 4 mm Thermal resistance junction ambient UFQFPN20 3 x3 mm Thermal resistance junction ambient LQFP32 7 x 7 mm Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Oja Oja Oja Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org Selecting the product temperature range When ordering the microcontroller the temperature range is spe
33. 2 pinout and pin description Figure 3 STM8S003K3 LQFP32 pinout CLK CCO TIM2 CH2 ADC ETR TLI TIM1 CH4 UART1 RX UART1 TX BEEP TIM2 CH1 TIM2_CH3 TIM1 BKIN PD7 PD6 PD5 PD4 PD3 PD2 PD1 PDO 32 31 30 29 28 27 26 25 NRST 01 24 1 MISO 1 02 23 1 pce HSy SPI MOSI OscouT PA2 22 pcs HS SPI_SCK vss 04 21 0 HS TIM1 CH4 CLK 05 20 HS TIM1 CH3 vpp 6 19 pce Hs TIM1 cH2 SPI NSS TIM2 5 C17 18 PC1 HS TIM1 CH1 UART1 CK 18 17 PES s SPI NSS 9 10 11 12 13 14 15 16 amm ammauosc CSP IE 54539232 o lt lt lt gt 532 a r Z 259 9 5 18 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 Pinout and pin description 1 HS high sink capability 2 True open drain P buffer and protection diode to not implemented 3 alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Type function after reset function i m FINE d PA2 OSCOUT 2 CH3 SPI_NSS
34. 3F3 9 9 1 9 1 5 46 99 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 25 C and TA Tama given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 2 Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 2 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in the following figure Figure 7 Pin load
35. 4 4 1 4 2 10 99 Product overview The following section intends to give an overview of the basic features of the device functional modules and peripherals For more detailed information please refer to the corresponding family reference manual 0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing 20 addressing modes indexed indirect addressing mode for look up tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 1
36. 4 62 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 Electrical characteristics Symb Accuracy of HSI User trimmed with oscillator CLK_HSITRIMR register for given and conditions Accuracy of HSI Vpp 5 V oscillator factory 25 C lt T lt 85 C calibrated HSI oscillator wakeup time including calibration HSI oscillator power consumption 1 Refer to application note Data based on characterization results not tested in production 9 Guaranteed by design not tested in production Figure 19 Typical HSI frequency variation vs Vpp 4 temperatures 95 C 85 C 1 00 45 C 0 00 accuracy ky 00 0018576 Rev 2 63 99 Electrical characteristics STM8S003K3 STM8S003F3 Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Table 34 LSI oscillator characteristics Symbol Parameter typ u jung Figure 20 Typical LSI frequency variation vs Vpp 4 temperatures 25 85 5 00 _ 45 400 3 00 2 00 1 00 0 00 accuracy 1 00 2 00 3 00 4 00 5 00 Vo V 9 3 5 Memory characteristics RAM and hardware registers Table 35 RAM and hardware registers Symbol Parameter Demons ln retention mode Halt mode or reset Minimum supply voltage without los
37. 6 Rev 2 77 99 Electrical characteristics STM8S003K3 STM8S003F3 78 99 tai s S g 4 3 5 O Table 42 SPI characteristics SPI clock Master mode frequency fsck1 SPI clock frequency SPI clock rise and Capacitive load 30 pF fall time NSS setup time Slave mode tMASTER SCK high and low Master mode tecid tecid time 2 15 2 15 7577 Data output Slave mode 3x access time EC Data output Slave mode disable time Data output valid Slave mode time after enable edge Data output valid Master mode time after enable edge Data output hold Slave mode time after enable edge Data output hold Master mode time after enable edge DoclD018576 Rev 2 YI STM8S003K3 STM8S003F3 Electrical characteristics 4 1 Parameters given by selecting 10 MHz I O output frequency 2 Data characterization in progress 9 values based on design simulation and or characterization results and not tested in production Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 5 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z Figure 38 SPI timing diagram slave mode and CPHA 0 NSS input tsU NSS lt gt lt tc SCK gt 99 CPHA 0 WEM 2 CPOL 0 x 0
38. 6 bit division Bit manipulation Data transfer between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming DoclD018576 2 ky STM8S003K3 STM8S003F3 Product overview 4 3 4 4 SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers R W to RAM and peripheral registers in real time R W access to all resources by stalling the CPU Breakpoints on all program memory instructions software breakpoints Two advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 27 external interrupts on 6 vectors including TLI Up to 37 external interrupts on 6 vectors including TLI Trap and reset interrupts Flash program memory and data EEPROM 8 Kbytes of F
39. C_SPR1 Interrupt software priority register 1 050075710 7F71 ITC_SPR2 Interrupt software priority register 2 Reserved area 85 bytes Reserved area bytes poor 7F73 E TF74 pom 7 75 7 76 KEE 7F77 eeu 7F78 to 7 79 0 00 7 80 NENNEN _ SWIM_CSR SWIM control status register Ba 7F81 to Ba 7F8F Ox00 7F90 ae BK1RE DM breakpoint 1 register extended OXFF byte E BK1RL DM e 1 register low DM breakpoint 1 register low byte Reserved area 15 05007601 7F91 DM BKIRH BK1RH DM breakpoint 1 register DM breakpoint 1 register high byte byte OFF E 7F92 byte DM BIQRH BK2RH DM DM breakpoint 2 register high byte 2 register DM breakpoint 2 register high byte byte OFF ky 00 0018576 Rev 2 37 99 7 94 ES 7 95 EE 7 96 Bing 7 97 Memory register STM8S003K3 STM8S003F3 Address Address Register label Register name 000 name lRegistername status 0x00 7F98 DM CSR1 DM debug module control status register 1 pum 7 99 DM_CSR2 DM debug module control status 0x00 register 2 mE DM DM ENFCTR DM enable DM enable function register DM enable function register OFF aa 7F9B to area 5 bytes 7F9F Accessible by debug module only 38 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 Interrupt vector mapping 7 Interrupt vector mapping Table 10 Int
40. Configurable input clock output AFR5 SWIM data interface Timer 2 channel 3 AFR1 STM8S003K3 STM8S003F3 Pinout and pin description Main Default function alternate after reset function after remap option bit TIM2_CH2 channel 2 ADC ADC_ETR external trigger PD4 BEEP TIM2_CH1 channel 1 BEEP output PD5 UART1 UART1 TX transmit PD6 UART1 data UART1_RX receive PD7 TLI Top level Timer 1 TIM1 CH4 interrupt channel 4 AFR6 1 I O pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings see Electrical characteristics 2 When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application in the open drain output column defines a true open drain I O P buffer weak pull up and protection diode to Vpp are not implemented the PD1 pin is in input pull up during the reset phase and after internal reset release 5 2 STM8S003F3 TSSOP20 UFQFPN20 pinout and pin description 5 2 1 STM8S003F3 TSSOP20 pinout and pin description Figure 4 STM8S003F3 TSSOP20 pinout UART1_CK TIM2_CH1 BEEP HS PD4 20 L PDs HS AIN4 TIM2_CH2
41. ENE E NG ERR 93 Document revision history eene nennen nennen nennen 98 DoclD018576 2 5 99 List of figures STM8S003K3 STM8S003F3 List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Block diagram 9 Flash memory organization 12 STM8S003K3 LOFP32 PINOUL uuu su R aa 18 STM8S003F3 TSSOP20 pinout 21 5 85003 UFQFPN20 pin pinout 2 22 Memory map Pc 25 Pin loading conditione uuu een e ERR LUI paasa ina 46 Pin input volage AT febumay VISUS VB iine detener eterna ti eri ner d niu e LR E AA 50 External capacitor Cpp 50 Ipp guw YS HSE user external clock fopy 16 MHZ 58 YS fopy HSE user external clock Vpp 5 V 58 Ipp RuN YS HSI RC ose 16 MHZ 0 0 4 02000 nnne ttes 59 1 VS HSE user external clock fepy 16
42. KENR1 2 registers 13 Table 3 TIM timer features u u u een GING GG Re HERR e ERE DURER Pre E eee 15 Table 4 Legend abbreviations for pinout tables seems 18 Table 5 EQFP32 pin description naaa BG hanku 19 Table 6 STM8S003F3 pin description 22 Table 7 I O port hardware register map 26 Table 8 General hardware register map 27 Table 9 CPU SWIM debug module interrupt controller registers 2222 36 Table 10 Interrupt mapping 7 m 9 39 Table T1 Option DVS MESTRE 98 Table 12 Option byte description em ener enne 41 Table 13 STM8S003K3 alternate function remapping bits for 32 pin devices 43 Table 14 STM8S003F3 alternate function remapping bits for 20 pin devices 44 Table 15 Voltage characteristics 1 inest AT Table 16 Current characteristics ee emeret AT Table 17 Thermal characteristics nne ERE e A ree 48 Table 18 General operating conditions 2 0 10 na a 49 Table 19 Operating conditions at power
43. M8S003F3 Electrical characteristics 9 3 8 Figure 36 Typical NRST pull up current vs 4 temperatures 5 100 5 5 80 5 5 60 2 40 one gt 25 40 Pp z 85 4 20 P od os T T 1 0 1 2 3 4 5 6 Voo V The reset network shown in the following figure protects the device against parasitic resets The user must ensure that the level on the can go below V NRST max see unique_55 CD662 otherwise the reset is not taken into account internally For power consumption sensitive applications the external reset capacitor value can be reduced to limit the charge discharge current If NRST signal is used to reset external circuitry attention must be taken to the charge discharge time of the external capacitor to fulfill the external devices reset timing conditions Minimum recommended capacity is 10 nF Figure 37 Recommended reset pin protection External reset circuit optional SPI serial peripheral interface Unless otherwise specified the parameters given in the following table are derived from tests performed under ambient temperature fmaster frequency Vpp supply voltage conditions 1 MASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO 0 001857
44. MHz 59 lppwen VS fceu HSE user external clock Vpn 5 60 HS RC fopy 16 MHz 60 HSE external clock SOUFGG ea edie addin ed idea veel 61 HSE oscillator circuit diagram 62 Typical HSI frequency variation vs 60 4 temperatures 63 Typical LSI frequency variation vs Vpp 4 temperatures 64 Typical Vi and Vi vs Vpp 4 temperatures 67 Typical pull up resistance vs 4 temperatures 67 Typical pull up current vs Vpp 4 temperatures 68 VoL Vpp 5 V standard ports 70 Figure 25 Typ Vo 3 3 V standard ports 70 Figure 26 Vo Vpp 5 V true open drain ports 71 Figure 27 Typ Vo Vpp 3 3 V true open drain ports 71 Figure 28 Typ Vo Vpp 5 V high sink ports 72 Figure 29 Typ Vo 60 Vpp 3 3 V high sink ports 72 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Vpp Vpp 5 V standard ports 73 3 3 V standard ports 73 Vpop 5 V high sink ports 74
45. MHz LSI RC osc 128 kHz HSE crystal osc 16 MHz LSI RC osc 128 kHz LSI RC osc 128 kHz LSI RC osc 128 kHz Data based on characterization results not tested in production Table 25 Total current consumption in active halt mode at Vpp 3 3 V Conditions Main voltage Typ regulator Flash mode Clock source MVR Symbol Parameter Supply current in IDD AH active halt mode HSE crystal osc 54 99 DoclD018576 Rev 2 STM8S003K3 STM8S003F3 Electrical characteristics Conditions Symbol Parameter Main voltage 3 regulator Flash mode Clock source MVR LSI RC osc Operating mode i Supply current in 128 kHz active halt mode HSE tal crystal osc Power down mode LSI RC osc DRA 128 kHz Supply current in H H H active halt mode EL LSI RC osc Off Power down 128 kHz DD AH mode Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 9 Configured by AHALT bit in the FLASH_CR1 register 9 3 2 4 Total current consumption in halt mode Table 26 Total current consumption in halt mode at Vpp 5 V Symbol Parameter Conditions Supply current in halt mode Flash in power down mode HSI clock after wakeup 1 Data based on characterization results not tested in production Table 27 Total current consumption in halt mode at 3 3 V Max at 85
46. SH CR1 register 6 Plus 1 LSI clock depending on synchronization 9 3 2 6 Total current consumption and timing in forced reset state Table 29 Total current kan dud and timing in forced reset state mt LEE ax tRESETBL Reset pin release to s vector fetch H 1 Data guaranteed by design not tested in production 2 Characterized with all I Os tied to Vs 9 3 2 7 Current consumption of on chip peripherals Subject to general operating conditions for Vpp and HSI internal RC fopy fmaster 16 MHz 5 V Table 30 Peripheral current ET Symbol 0 Symbol Parameter TIM1 supply current TIM2 supply current p TIM4 timer supply current ky 00 0018576 Rev 2 57 99 Electrical characteristics STM8S003K3 STM8S003F3 1 at 16 MHz No IC OC programmed no I O pads toggling Not tested in production 2 Data based on a differential Ibp measurement between reset configuration and timer counter running Data based on a differential 1 measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production 3 conversions Not tested in production 9 3 2 8 58 99 Current consumption curves Data based on a differential 1 measurement between reset configuration and continuous A D The following figures show typical current consumption m
47. THORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately voidany warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2011 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 0 0018576 Rev 2 99 99
48. WIM debug module interrupt controller registers U 36 7 Interrupt vector mapping nennen nnne nnne nnne nnne nnn nenne 39 S nu cge Q 41 8 1 Alternate function remapping bits nennen A3 2 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Contents 9 Electrical characteristics mam 46 9 1 Parameter conditions 46 9 1 1 Minimum and maximum values 2 46 9 1 2 Typical values 46 9 1 3 Typical CURVES taa eere Jahan 46 9 1 4 Loading Capacitor XA NAAN 46 9 1 5 Pini input voltage 2 uu u reete E 46 9 2 Absolute maximum ratings sse d AT 9 3 Operating conditions A9 9 3 1 VCAP external capacitor 50 9 3 2 Supply current characteristics 51 9 3 3 External clock sources and timing characteristics 60 9 3 4 Internal clock sources and timing characteristics 62 9 3 5 Memory characteristics 64 9 3 6 port pin characteristics 66 9 3 7 Reset pin characteristics 74 9 3 8 SPI serial peripheral interface 4 77 9 3 9 interface char
49. acteristics 80 9 3 10 10 bit ADC characteristics 81 9 3 11 EMC characteristics 85 10 Package information Me M 89 10 1 32 pin LQFP package mechanical data 2 89 10 2 20 pin TSSOP package mechanical data 90 10 3 20 lead UFQFPN package mechanical data 92 11 Thermal characteristics AA AA 93 11 1 Reference document ier et eee NANANA 93 11 2 Selecting the product temperature range 2 93 12 Ordering information me AA 95 13 STM8 development tools 96 13 1 Emulation and in circuit debugging tools 96 13 2 Software tools naaa tet ndm etra adde eel duda nde dea mage Er RE Edad 96 13 2 1 STM8 toolset 97 13 2 2 and assembly toolchains see 97 18 3 Programming tools uuu ua ire NAAN Eo pe 97 14 Revision history M 98 ky 00 0018576 Rev 2 3 99 List of tables STM8S003K3 STM8S003F3 List of tables Table 1 STM8S003xx value line features 8 Table 2 Peripheral clock gating bit assignments in PC
50. ating conditions for Vpp and Table 31 HSE user external clock characteristics Symb fusE ext User external clock source frequency OSCIN input pin high level voltage _ 0 3 V OSCIN input pin low level voltage OSCIN input leakage current 60 99 DocID018576 Rev 2 STM8S003K3 STM8S003F3 Electrical characteristics Data based on characterization results not tested in production Figure 17 HSE external clock source HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 32 HSE oscillator characteristics External high speed oscillator frequency Feedback resistor Recommended load capacitance HSE oscillator power C 20 pF 6 startup consumption fosc 16 MHz 1 6 stabilized C 10 pF 6 startup fosc 16 MHz 12 stabilized Oscillator transconductance tsu HsE Startup time Vpp is stabilized 4 0 0018576 Rev 2 61 99 Electrical characteristics STM8S003K3 STM8S003F3 C
51. cified in the order code 0 0018576 Rev 2 93 99 Thermal characteristics STM8S003K3 STM8S003F3 94 99 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions Maximum ambient temperature 75 C measured according to JESD51 2 9 l bDmax 8 MA Vpp 5 V Maximum 20 I Os used at the same time in output at low level with lo 8 MA Vo 0 4 V Pintmax 8 MA x 5 V 400 mW Amax 9 Pomax 400 mw 64 mW Thus Ppmax 464 mW TJmax for LQFP32 can be calculated as follows using the thermal resistance O 75 C 60 C W x 464 mW 75 C 27 8 C 102 8 C This is within the range of the suffix 6 version parts 40 lt lt 105 C In this case parts must be ordered at least with the temperature range suffix 6 00 0018576 Rev 2 ky STM8S003K3 STM8S003F3 Ordering information 12 Ordering information Figure 47 STM8S003x value line ordering information scheme Example STM8 S 003 K T 6 TR Product class STM8 microcontroller Family type S Standard Sub family type 00x Value line 003 sub family Pin count K 32 pins F 20 pins Program memory size 3 8 Kbytes Package type 1 T LQFP P TSSOP U UFQFPN Temperature range 6 40 C to 85 Package pitch Blank 0 5 or 0 65 mm 1 C 0 8 mm 2 Packin
52. cs section does not affect the ADC accuracy 5 When several inputs are submitted to a current injection the maximum 21 is the absolute sum INJ PIN of the positive and negative injected currents instantaneous values These results are based on characterization with maximum current injection on four I O port pins of the device Table 17 Thermal characteristics Symbol Ratings Vale Unit Storage temperature range 65 to 150 Hi Maximum junction temperature 48 99 DocID018576 Rev 2 ky STM8S003K3 STM8S003F3 Electrical characteristics 9 3 Operating conditions Table 18 General operating conditions Internal CPU clock frequency Standard operating voltage capacitance of 470 3300 external capacitor ESR of external at 1 MHz capacitor ESL of external nF capacitor Power dissipation at TA 85 C UFQFPN20 for suffix 6 LQFP32 Ambient temperature for 6 suffix Maximum power dissipation 3 lt version 4 N N N Junction temperature range for i 40 suffix 6 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors The parameter maximum value must be respected for the full application range 2 To calculate Pomax T a use the formula Pomax Tymax see Thermal characteristics with the value
53. cts the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organization Option bytes Data EEPROM 128 bytes Programmable UBC area area from 64 i i i bytes 1 page Remains write protected during IAP up to B Kbytes in 1 page steps Low density Flash program memory 8 Kbytes Program memory area Write access possible for IAP Read out protection ROP The read out protection blocks reading and writing from to the Flash program memory and the data EEPROM in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller Clock controller The clock controller distributes the system clock fyaster coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler Safe clock switching Clock sources can be changed safely on the fly in run mode through a c
54. e MCU is placed under the following conditions All I O pins in input mode with a static value at Vpp or Vss no load All peripherals are disabled clock stopped by peripheral clock gating registers except if explicitly mentioned Subject to general operating conditions for Vpp and Table 20 Total current consumption with code execution in run mode at Vpp 5V HSE crystal osc 16 MHz fopu 16 MHz HSE user ext clock 16 MHz HSI RC osc 16 MHz IDDRUN ii run moda 125 kHz HSI RC osc 16 MHz code executed from RAM fopu fmaster 128 15 625 kHz HSI RC osc 16 2 8 fopu faster 128 kHz Supply current HSE crystal osc 16 MHz fopu MASTER in run mode HSE user ext clock 16 MHz code executed 16 MHz from Flash HSI RC osc 16 MHz fopu fuasrER 2 MHz LSI RC osc 128 kHz HSI RC osc 16 2 8 fopu fuasrER 128 Supply current 125 kHz in run mode code executed from Flash HSI RC osc 16 MHz fopu fuasren 128 HSI RC osc 16 MH 15 625 kHz fopu fuasrER LSI R 128 kH 128 kHz SI RC osc 128 kHz 4 DoclD018576 Rev 2 51 99 Electrical characteristics STM8S003K3 STM8S003F3 1 2 Data based on characterization results not tested in production Default clock configuration measured with all peripherals off Table 21 Total current consumption with code execution in run mode at Vpp 3 3 V
55. e protected 0x02 Pages 0 to 1 defined as UBC memory write protected Page 0 and 1 contain the interrupt vectors Ox7F Pages 0 to 126 defined as UBC memory write protected Other values Pages 0 to 127 defined as UBC memory write protected Note Refer to the family reference manual RM0016 section on Flash write protection for more details AFR 7 0 Refer to following section for alternate function remapping decriptions of bits 7 2 and 1 0 respectively HSITRIM High speed internal clock trimming register size 0 3 bit trimming supported in CLK HSITRIMR register 1 4 bit trimming supported in CLK HSITRIMR register LSI EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG_HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG Window watchdog reset on halt 42 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Option bytes 8 1 Option byte no 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wake up unit clock 0 LSI clock source selected f
56. e up timer Window watchdog and independent watchdog timers Communications interfaces UART with clock output for synchronous operation Smartcard IrDA LIN master mode SPI interface up to 8 Mbit s interface up to 400 Kbit s Analog to digital converter ADC 10 bit 1 LSB ADC with up to 5 multiplexed channels scan mode and analog watchdog Os Up to 28 I Os on a 32 pin package including 21 high sink outputs Highly robust I O design immune against current injection Development support Embedded single wire interface module SWIM for fast on chip programming and non intrusive debugging DoclD018576 Rev 2 1 99 www st com Contents STM8S003K3 STM8S003F3 Contents juices ERN 7 2 Description EM E TcT PO 8 3 Block diagrami c 9 4 Product eee 10 4 1 Central processing unit STM8 10 4 2 Single wire interface module SWIM and debug module DM 10 4 3 Interrupt controller 11 4 4 Flash program memory data EEPROM 11 4 5 Clock controllet a aa 12 4 6 Power management 13 4 7 Watchdog timers dd e a a dee d de 13 4 8 Auto wakeup COUNTER uu u eet ttes eerta tace nn aaO NERA Ld
57. easured with code executing in RAM Figure 11 Typ VS Vpp HSE user external clock fcpu 16 MHz IDD run HSE mA 25 85 45 C Figure 12 Typ VS fcpu HSE user external clock Vpp 5 V ISE mA IDD_run_H mee 25 C 85 C 25 4590 MHz 0 0018576 2 STM8S003K3 STM8S003F3 Electrical characteristics Figure 13 Typ Ipp RuN VS HSI osc 16 MHz 05 C 85 mi 45 C IDD run HSI mA ng Figure 14 Ippwrn VS HSE user external clock fcpu 16 MHz s 25 18 85 C 45 0 1 6 14 lt 12 ma a a a i doni I 08 z 08 04 02 0 2 2 5 3 38 4 45 5 55 6 Msg V ky DoclD018576 2 59 99 Electrical characteristics STM8S003K3 STM8S003F3 Figure 15 Typ lpp wr VS fcpy HSE user external clock Vpp 5 V SE mA IDD WFLH 2 4 8 8 10 12 4 18 18 MHz Figure 16 VS HSI osc 16 MHz para To 18 85 45 C IDD_WFI_HSI mA o 2 6 3 35 4 45 5 55 6 MHz 9 3 3 External clock sources and timing characteristics HSE user external clock Subject to general oper
58. errupt mapping halt mode active halt mode 1 update overflow underflow 0x00 8034 trigger break IM1 TIM1 capture compare Eo 0x00 8038 IM2 TIM2 update overflow F 0x00 803C N m NI NI I I I a a a a a ss Qm l OIl N co o Nf O BR O 22 end of conversion analog 0x00 8060 DC1 watchdog interrupt DoclD018576 Rev 2 39 99 C C 0 Source block TIM1 4 Interrupt vector mapping STM8S003K3 STM8S003F3 Source Description Wakeup from Wakeup from Vector address block halt mode active halt mode TIM4 TIM4 update overflow 0 00 8064 Reserved 0x00 806C to 0x00 807C 1 Except PA1 40 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in the table below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S
59. ers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset ky DoclD018576 2 13 99 Product overview STM8S003K3 STM8S003F3 4 8 4 9 4 10 14 99 Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 KHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter Used for auto wakeup from active halt mode Clock source Internal 128 kHz internal low frequency RC oscillator or external clock LSI clock can be inter
60. g No character Tray or tube TR Tape and reel 1 TSSOP and UFQFPN package 2 LQFP package For a list of available options e g package packing and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you 0 0018576 Rev 2 95 99 STM8 development tools STM8S003K3 STM8S003F3 13 13 1 13 2 96 99 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STMB is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In add
61. ing conditions STM8 pin bun Pin input voltage The input voltage measurement on a pin of the device is described in the following figure DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Electrical characteristics Figure 8 Pin input voltage STM8 pin 9 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 15 Voltage characteristics Symbol Input voltage on true open drain pins 6 5 0 6 5 50 IVssx Vssl Variations between all the different ground mE pins Vesp Electrostatic discharge voltage us electrical sensitivity All power Vpp and ground Vss pins must always be connected to the external power supply must never be exceeded This is implicitly insured if Vy maximum is respected If Vy maximum cannot be respected the injection current must be limited externally to the liy pi Value A positive injection is induced by Vy Vpp while a negative injection is induced by Viys Vas For true open drain pads there is no positive injection current and the corresponding Vi maximum must always be respected Table 16 Current characteristics ky DoclD018576 2 47 99 Electrical characteristics
62. ing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to the Operating conditions section for the value of Vir max 64 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 Electrical characteristics Flash program memory and data EEPROM prog including erase for byte word block 1 byte 4 bytes 64 bytes Fast programming time for EN Table 36 Flash program memory and data EEPROM 1 block 64 bytes Symbol Parameter Conditions M terase Erase time for 1 block 64 bytes in 1 Vpp Operating voltage all modes execution fopy lt 16 MHz 2 95 write erase t New Erase write cycles 100 program memory Erase write cycles 100 k data memory 20 20 1 Standard programming time Data retention program memory after 100 erase write cycles at T4 85 C Tret 55 C Data retention data memory after 10 k erase write cycles at T4 85 C Data retention data memory after 100 k 85 erase write cycles at T4 85 Supply current Flash programming or erasing for 1 to 128 bytes ky 00 0018576 Rev 2 65 99 Electrical characteristics STM8S003K3 STM8S003F3 Data based on characterization results not tested in production The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte
63. istics Table 43 characteristics yb ol Standard mode Fast mode Pc tw tw 5 4 0 WA t SDA a SDA and SCL rise time triscL tispa SDA SCL fall time 0 tasta START condition hold time Repeated START condition setup time 80 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Electrical characteristics symbol Standard mode Fast mode Pc STO tystosta STOP to START condition time 1 3 S bus free H b 1 2 3 low time 4 the undefined region of the falling edge of SCL faster Must be at least 8 MHz to achieve max fast speed 400kHz Data based on standard protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge Figure 41 Typical application with bus and timing diagram Vpp Vpp 4 7kQ 4 7kQ i 1000 SDA 5 85 NW bus 1000 SCL NAN 4 START START 7 tsusta tw STO STA lt START 4 X nm 1 1 x lt gt e 1 1 0 TSDA i kaso raj Es aD a pr Z N m Z N lt gt lt gt pi pe PIG 1 6 twscLH w SCLL tyscL tsu STO ai17490 1 Measure
64. ition STice offers in circuit debugging and programming of STM8 microcontrollers via the 5 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features Occurrence and time profiling and code coverage new features Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read write on the fly of memory during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 Software tools STM8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Rai
65. ive is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard FTB A burst of fast transient voltage positive and negative is applied to and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 EMC design guide for STMicrocontrollers Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application 0 0018576 Rev 2 85 99 Electrical characteristics STM8S003K3 STM8S003F3 Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior i
66. lash program single voltage Flash memory 128 bytes of true data EEPROM User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory the data EEPROM and the option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to modify the content of the main program memory and data EEPROM or to reprogram the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to the figure below The size of the UBC is programmable through the UBC option byte in increments of 1 page 64 byte block by programming the UBC option byte in ICP mode This divides the program memory into two areas Main program memory 8 Kbytes minus UBC User specific boot code UBC Configurable up to 8 Kbytes 0 0018576 Rev 2 11 99 Product overview STM8S003K3 STM8S003F3 4 5 12 99 The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It prote
67. map 6 2 1 port hardware register map Table 7 I O port hardware register map Ca 26 99 DoclD018576 2 STM8S003K3 STM8S003F3 Memory and register map Address Register label Register name Reset status 0x00 5018 5018 PotE E PE 0 Port E control register2 control Port E control register2 2 a 5019 NUT E ODR Port F data output latch register Port F 0 00 501 501 Depends the external circuitry E 501B aa 501C 5010 1 6 2 2 General hardware register Table 8 General hardware register map Address Register label Register name Reset status 0x00 501E to Reserved area 60 bytes 0x00 5059 0x00 505A Flash FLASH CR1 Flash control register 1 0 00 505B FLASH CR2 Flash control register 2 Ox00 505C FLASH NCR2 Flash complementary control register 2 0 00 505D FLASH FPR Flash protection register 0 00 505E FLASH NFPR Flash complementary protection register 0 00 505F FLASH IAPSR Flash in application programming status 0x00 register Ox00 5060 to Reserved area 2 bytes 0 00 5061 0 00 5062 FLASH PUKR Flash program memory unprotection register 0 0018576 Rev 2 27 99 4 Memory register map STM8S003K3 STM8S003F3 Address Register label Register name Reset status 5063 Reserved area 1 byte 0x00 5064 FLASH_DUKR Data EEPROM unprotection register T 5065 to Reserved area 59 bytes T 509F
68. me SPI Maximum speed 8 Mbit s 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin PC master features Clock generation Start and stop generation slave features Programmable 2 address detection Stop bit detection Generation and detection of 7 bit 10 bit addressing and general call Supports different communication speeds Standard speed up to 100 kHz Fast speed up to 400 kHz 0 0018576 Rev 2 17 99 Pinout and pin description STM8S003K3 STM8S003F3 5 Pinout and pin description Table 4 Legend abbreviations for pinout tables l Input Output S Power supply Output HS High sink SHIpHtspesd O1 Slow up to 2 MHz O2 Fast up to 10 MHz Fast slow programmability with slow as default state after reset OA Fast slow programmability with fast as default state after reset Port and control Input float floating wpu weak pull up configuration Output T True open drain OD Open drain PP Push pull Reset sale Bold X pin state after internal reset release Unless otherwise specified the pin state is the same during the reset phase and after the internal reset release 5 1 STM8S003K3 LQFP3
69. ment points are made at CMOS levels 0 3 x VDD and 0 7 x VDD 9 3 10 10 bit ADC characteristics Subject to general operating conditions for Vpp faster and Ta unless otherwise specified ky DoclD018576 2 81 99 Electrical characteristics STM8S003K3 STM8S003F3 82 99 Table 44 ADC characteristics Vain Conversion voltage range Capc Internal sample and hold capacitor Minimum total conversion time including sampling time 10 bit resolution 1 During the sample time the input capacitance C a pF max be charged discharged 8 the external source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock tg depend on programming Table 45 ADC accuracy with Ran lt 10 Vpp 5 V P _ p Total unadjusted error Offset error 2 MHz 0 0018576 Rev 2 STM8S003K3 STM8S003F3 Electrical characteristics symbol Parameter 000 Conditions wp ax Ecl Gain error CNN e Differential linearity error 2 MHz Integral linearity error Jesus foo fis Data based on characterization results not tested in production 2 ADC accuracy vs negative injection current Injecting negative current
70. nally connected to TIM1 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz The beeper output port is only available through the alternate function remap option bit AFR7 TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver 16 bit up down and up down autoreload counter with 16 bit prescaler Four independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output Synchronization module to control the timer with external signals Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time DoclD018576 2 ky STM8S003K3 STM8S003F3 Product overview Encoder mode interrupt sources 3 x input capture output compare 1 x overflow update 1 x break 4 11 TIM2 16 bit general purpose timer 16 bit autoreload AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 3 individually configurable capture compare channels PWM mode Interrupt sources 3 x input capture output compare 1 x ove
71. not implemented the PD1 pin is in input pull up during the reset phase and after internal reset release 5 3 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the ports see the GPIO section of the family reference manual RM0016 24199 0 0018576 Rev 2 STM8S003K3 STM8S003F3 Memory and register map 6 Memory and register map 6 1 Memory map Figure 6 Memory map 0x00 0000 0x00 03FF 0x00 0800 0x00 4000 0x00 407F 0x00 47FF 0x00 4800 0x00 480A 0x00 480B 0x00 4FFF 0x00 5000 0x00 57 0x00 5800 0x00 7EFF 0x00 7 00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 0x00 9FFF 0x00 A000 0x02 7FFF RAM 1 Kbyte 513 bytes stack Reserved Data EEPROM Reserved Option bytes Reserved GPIO and periph reg Reserved CPU SWIM debug ITC registers Flash program memory 8 Kbytes Reserved 0 0018576 Rev 2 25 99 Memory register STM8S003K3 STM8S003F3 6 2 Register
72. onfiguration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory Master clock sources Four different clock sources can be used to drive the master clock 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI DoclD018576 2 ky STM8S003K3 STM8S003F3 Product overview Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts Clock security system CSS This feature be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and interrupt can optionally be generated Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments CLK PCKENR17 2 registers Peripheral Peripheral Peripheral Peripheral clock clock clock clock PCKEN17 TIM1 PCKEN13 UART1 27 Reserved PCKEN23 PCKEN15 TIM2 PCKEN11 SPI 25 Reserved
73. or AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler HSECNT 7 0 HSE crystal oscillator stabilization time 0x00 2048 HSE cycles 0 4 128 HSE cycles OxD2 8 HSE cycles 0 1 0 5 HSE cycles Alternate function remapping bits Table 13 STM8S003K3 alternate function remapping bits for 32 pin devices OPT2 AFR7 Alternate function remapping option 7 Reserved AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive Default alternate function 1 Port D7 alternate function 1 5 Alternate function remapping option 5 0 AFR5 remapping option inactive Default alternate function 0 0018576 Rev 2 43 99 Option bytes STM8S003K3 STM8S003F3 1 Port DO alternate function CLK_CCO AFR 4 2 Alternate function remapping options 4 2 Reserved AFR1 Alternate function remapping option 1 0 AFR1 remapping option inactive Default alternate functions 1 Port alternate function 55 port D2 alternate function TIM2 CH3 AFRO Alternate function remapping option 0 Reserved Do not use more than one remapping option in the same port It is forbidden to enable both AFR1 and AFRO 2 Refer to pinout description Table 14 STM8S003F3 alternate function remapping bits for 20 pin devices OPT2
74. ose timer TIM1 SPI rc UART Peripheral set window WDG independent WDG ADC PWM timer TIM2 8 bit timer TIM4 1 Without read while write capability 8 99 DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Block diagram 3 Block diagram Figure 1 Block diagram Reset block XTAL 1 16 MHz lt Clock controller Reset Reset lt RCint 16 MHz Detector POR BOR 128 2 TZE Clock to peripherals and core Wi WD core G Independent WDG Single wire D WIM lt 8 Kbyt debug interf nG program Flash 2 128 byte 400 Kbit s m gt s 5 M 1 Kbyte Up to 8 Mbit s SPI 9 p 5 4 3 channels 3 complementary LIN master 1 lt 16 bit advanced outputs SPI emul UART1 control timer TIM1 16 bit general purpose Upto i TIM2 timer HMA 3 CAPCOM channels 8 bit basic timer Up to 5 TIM4 channels A ADEI i 1 2 4 kHz gt AWU timer beep ky DoclD018576 Rev 2 9 99 Product overview STM8S003K3 STM8S003F3
75. rflow update 4 12 TIM4 8 bit basic timer 8 bit autoreload adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source CPU clock interrupt source 1 x overflow update Table 3 TIM timer features Counter Counting Prescaler size bits mode channels outputs Any integer from 1 to Up down Timer synchronization chaining Any power of 2 from 1 to Any power of 2 from 1 to 4 13 Analog to digital converter ADC1 The STM8S003xx products contain a 10 bit successive approximation A D converter ADC1 with up to 5 external multiplexed inputs channels and the following features The STM8S105xx products contain a 10 bit successive approximation A D converter with up to 10 multiplexed input channels and the following main features Input voltage range 0 to Vpp Input voltage range O to Vppa Conversion time 14 clock cycles Single and continuous and buffered continuous conversion modes Buffer size 10 bits where number of input channels ky DoclD018576 2 15 99 Product overview STM8S003K3 STM8S003F3 4 14 4 14 1 16 99 Scan mode for single and continuous conversion of a sequence of channels Analog watchdog capability with programmable upper and lower thresholds Analog watchdog interrupt External trigger input Trigger from TIM1 TRGO End of conversion EOC interrupt ac Note Additional AIN12 analog input is not
76. s detected the software can be hardened to prevent unrecoverable errors occurring See application note AN1015 Software techniques for improving microcontroller EMC performance Table 47 EMS data Symbol Parameter Conditions Level class Voltage limits to be applied on any W O pin to 3 3 V TA 25 C faster 16 MHZ p 7 induce a functional HSI clock conforming to IEC 61000 4 2 disturbance Fast transient voltage burst limits to be applied through 100 pF on Vpp 3 3 V TA 25 C fuasreg 18 MHz f and Vss pins to induce a HSI clock conforming to IEC 61000 4 4 functional disturbance Data obtained with HSI clock configuration after applying HW recommendations described in AN2860 EMC guidelines for STM8S microcontrollers 9 3 11 3 Electromagnetic interference EMI Based on a simple application running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm SAE IEC 61967 2 which specifies the board and the loading of each pin Table 48 EMI data Max fuce fopy 7 General Monitored conditions frequency band 16 MHz 16 MHz 8 MHz 16 MHz Peak level 5 0 1 MHz to 95 5 5 Siji 30 2 2 86 99 DoclD018576 2 ky STM8S003K3 STM8S003F3 Electrical characteristics 9 3 11 4 9 3 11 5 Max tysefeeu pon
77. sonance C compilers for STM8 which are available in a free version that outputs up to 16 Kbytes of code DoclD018576 2 ky STM8S003K3 STM8S003F3 STM8 development tools 13 2 1 13 2 2 13 3 STMB8 toolset 8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST Visual Develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontroller s Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include Cosmic compiler for STM8 Available free version that outputs up to 16 Kbytes of code For more information see www cosmic software com
78. tary static tests are required on 10 parts to assess the latch up performance A supply overvoltage applied to each power supply pin Acurrent injection applied to each input output and configurable pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 50 Electrical sensitivities Static latch up class 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard DoclD018576 Rev 2 ky STM8S003K3 STM8S003F3 Package information 10 10 1 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 32 pin LQFP package mechanical data Figure 44 32 pin low profile quad flat package 7 x 7 RE 5V ME Table 51 32 pin low profile quad flat package mechanical data Joao foore foor m pem es 5 asa
79. tatus register 0x00 50F4 to Reserved area 12 bytes 0x00 50FF 0x00 5200 CR1 SPI control register 1 5201 SPI SPI control register 2 ky 00 0018576 Rev 2 29 99 Memory register map STM8S003K3 STM8S003F3 Address Register label Register name Reset status 0x00 5202 SPI SPI interrupt control register 0x00 5203 0x00 5208 to Reserved area 8 bytes 0x00 520F 30 99 00 0018576 Rev 2 ky 0x00 5204 5205 oos 5206 5207 STM8S003K3 STM8S003F3 Memory and register map Address Register label Register name Reset status 0x00 521C 2 register high 0x00 521D 2 TRISER TRISE register I2C_PECR re packet error checking register 0x00 521F to Reserved area 17 bytes 0x00 522F 0x00 523 to Reserved area 21 bytes 0x00 523F 0x00 5250 TIM1 TIM1 CR1 TIM1 control register 1 0 00 5251 TIM1_CR2 TIM1 control register 2 rM 521E ky 00 0018576 Rev 2 31 99 Memory register map STM8S003K3 STM8S003F3 EERE E status 32 99 00 0018576 Rev 2 ky STM8S003K3 STM8S003F3 Memory and register map Fm E status 0x00 526E TIM1_DTR TIM1 dead time register 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 5270 to Reserved area 147 bytes 0x00 52FF 0x00 5300 TIM2 2 CR1 2 control register 1 0 00 5301 Reserved 0x00 5302 Reserved ky 00 0018576 Rev
80. ual RM0016 For information on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual 0051 For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual 0 0470 For information on the STM8 core please refer to the STM8 CPU programming manual 0044 ky DoclD018576 2 7 99 Description STM8S003K3 STM8S003F3 2 Description The 5 85003 value line 8 bit microcontrollers feature 8 Kbytes Flash program memory plus integrated true data EEPROM The STM8S microcontroller family reference manual 0016 refers to devices in this family as low density They provide the following benefits performance robustness and reduced system cost Device performance and robustness are ensured by integrated true data EEPROM supporting up to 100000 write erase cycles advanced core and peripherals made in a state of the art technology a 16 MHz clock frequency robust I Os independent watchdogs with separate clock source and a clock security system The system cost is reduced thanks to high system integration level with internal clock oscillators watchdog and brown out reset Full documentation is offered as well as a wide choice of development tools Table 1 STM8S003xx value line features Ext interrupt pins True data EEPROM bytes 128 7 128 7 Multipurp
81. up power down 50 Table 20 Total current consumption with code execution in run mode at Vpp 5 51 Table 21 Total current consumption with code execution in run mode at Vpp 3 3 V 52 Table 22 Total current consumption in wait mode at Vpp 5 V 53 Table 23 Total current consumption in wait mode at Vpp 3 3 V 53 Table 24 Total current consumption in active halt mode at Vpp 5 54 Table 25 Total current consumption in active halt mode at Vpp 3 3 V 54 Table 26 Total current consumption in halt mode at Vpp 5 55 Table 27 Total current consumption in halt mode at Vpp 3 3 V 55 Table 28 Wakeup times 2 9 56 Table 29 Total current consumption and timing in forced reset state 57 Table 30 Peripheral current consumption nnne nnne 57 Table 31 HSE user external clock characteristics 60 Table 32 HSE oscillator characteristics sss eene 61 Table 33 HSI oscillator characteristics 62 Table 34 LSI oscillator characteristics 64 Table 35 RAM and hardware registers 64 Table 36 Flash program memory and data EEPROM 65 Table 37 VO

STM8S003K3 STM8S003F3

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