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USER`S MANUAL

1. 5 9 6 1 Instruction Group nene nene n ener 6 2 6 2 Flag Notation meme 6 8 6 3 Instruction Set Symbols 6 8 6 4 Instruction Notation Conventions 6 9 6 5 Opcode Quick Reference a ra eo YER Qe 6 10 6 6 Condition M 6 12 8 1 S3C8235B F8235B Set 1 Register Values after 8 2 8 2 S3C8235B F8235B Set 1 Bank 0 Register Values after RESET 8 3 8 3 S3C8235B F8235B Set 1 Bank 1 Register Values after RESET 8 4 9 1 3C8235B F8235B Port Configuration 9 1 9 2 Port Data Register Summary nene mener 9 2 13 1 Watch Timer Control Register WTCON Set 1 Bank 0 F2H 13 2 14 1 LCD Control Register LCON Organization eese 14 4 14 2 Frame Frequency according to LCD Clock Signal LCDCK 14 5 14 3 LCD Drive Voltage Values External Resistor 14 7 17 1 VLDCON Value and Detection 17 3 xvi 3C8235B F8235B MICROCONTR
2. M 10 1 Basic Timer BT i ette d ot Eee EUER oL MR d erar Duis 10 1 Basic Timer Control Register 10 1 Basic Timer Function DeSCription u L aaa kasku em eene n enn nn ener heres 10 3 S3C8235B F8235B MICROCONTROLLER vii Table of Contents Continued Chapter 11 8 bit Timer A B B BIE IRPA LS SS cce kie ge ae ix Mx Eco aaa bese See 11 1 eu E 11 1 Function 2 11 2 Time A Control Register ooo Wa edu emen pene de pe e pee Ade arn et eue aq Mora 11 3 BlOCK CUT 11 4 8 B 11 5 eU p PLE 11 5 Chapter 12 16 bit Capture Timer 1 era rcr 12 1 Function BI i To groom 12 2 Timer 1 Control Register 12 3 Block BIT To 1o Mm 12 4 Chapter 13 Watch Timer OVOIVIOW 0 13 1 Watch Timer Control Register WTCON 13 2 Watch Timer Circuit mene menn 13 3 Chapter 14 LCD Controller Driver OVelViGW 5 OO 14 1 LCD Gireuit Diara
3. 5 10 Interrupt Mask Register 00000000000 nnne nnn nennen nnns nennen nnns 5 11 Interrupt Priority Register nnn enne nnne nnn hne nen 5 12 Interrupt Request Register 5 14 Interrupt Pending Function 5 15 Interrupt Source Polling E 5 16 Interrupt Service n nennen nnn nennen h nnns nennen nnn 5 16 Generating Interrupt Vector 0 5 17 Nesting of Vectored 5 17 Chapter 6 Instruction Set eu A 6 1 BEWOHNER ILE 6 1 Register Addressing i u roa roce tego e ete egi eet eu a 6 1 Addressing Modes iss or ee E ERU Rude E REO e a BR qe EXE de RR REED PUR REG 6 1 Flags Register FLAGS nidi knie DLP Este be Se e edebat Peta 6 6 Fag DescriptiOris t ite ie trece ut ve ite ut Ure sue 6 7 Instruction Set oe e cete reb ne eau ved ee iure om 6 8 Goriditiori GOdes E 6 12 Merican Descriptors irrena cel co eo
4. 4 16 OSCCON Oscillator Control eene nnne 4 17 POCONH Port 0 Control Register High 4 18 POCONL Port 0 Control Register Low 4 19 POINT Port 0 Interrupt Control 4 20 POPND Port 0 Interrupt Pending Register 4 21 P1CONH Port 1 Control Register High 4 22 P1CONL Port 1 Control Register Low 4 23 P1PUR Port 1 Pull up Control 0 4 24 P2CONH Port 2 Control Register High 4 25 P2CONL Port 2 Control Register Low 4 26 P3CON Port S Control Registet cce Et ea RR Rite HR 4 27 PSINT Port Interrupt Control 4 28 PSPND Port Interrupt Pending ee 4 29 Port 4 Control 4 30 PGCON Pattern Generation Control Register 4 31 S3C8235B F8235B MICROCONTROLLER xix List of Register Descriptions continued Register Full Register Name Page Identifier Number PP Register Page nennen nnn 4 32 RPO Register 4 33 Register Polnter T s uy e On te Elend exe lu AS us YR 4 33 SPH Stack Pointer High
5. 12 4 13 1 Watch Timer Circuit 13 3 14 1 LCD Function Diagram eene irte EE ERE 14 1 14 2 LOD Circuit Diagram 2 2 iine ed dore ee Edda o et Y dee Eg s 14 2 14 3 LCD Display Data RAM Organization 4 14 3 14 4 LCD Mode Contol Register 2 14 6 14 5 Select No Select Bias Signals in Static Display 14 7 14 6 LCD Signal and Wave Forms Example in 1 8 Duty 1 4 Bias Display Mode 14 8 14 7 LCD Signals and Wave Forms Example 1 4 Duty 1 3 Bias Display Mode 14 9 14 8 Voltage Dividing Resistor Circuit 14 10 14 9 Key Strobe Contol nnne nnns 14 11 14 10 Key Input Check Sequence During Key Strobe Out Duration 14 12 14 11 Example of Key Strobe Mode with 1 4 Duty SEG 14 13 15 1 A D Converter Control Register 15 2 15 2 A D Conversion Interrupt Register 15 3 15 3 A D Converter Data Register 15 3 15 4 A D Converter Functional Block Diagram 15 4 15 5 Recommended A D Converter Circuit for Highest Absolute 15 4 16 1 Voltage Booste
6. 14 2 EGD RAM AQOQIeSS Area eto retos tee teen deles eec obe ta rebote nda tud xx 14 3 LCD Control Register LCON 0 440440 14 4 LOD Mode Register LMOD R ERE Ue dubia SERRE TER Te MS 14 5 LOD Drive VONAGE RM 14 7 ESL 14 7 EGD Voltage Driving Method 14 10 LCD Key Strobe Output Mode u ce pM eds nage 14 11 Chapter 15 10 bit Analog to Digital Converter e 15 1 FUNCTION Bi iTo loo D ES 15 1 eren nI 15 2 A D Converter Control Register 15 2 Internal Reference Voltage Levels 15 3 Block Diagram viii 3C8235B F8235B MICROCONTROLLER Table of Contents Concluded Chapter 16 Voltage Booster OVelViGW tertie Eee e ER eei erbe ea I am FUNCTION DESCHIPTION eH a y u Su ede tite tts betreten i utet itt a Chapter 17 Voltage Level Detector CN D PI CE M Voltage Level Detector Control Register Chapter 18 Pattern Generation Module NIMMT Pattern Gneration
7. 4 4 34 SPL Stack Pointer Low 4 34 STPCON stop ides Le Bot e EE p BER wae ERREUR 0 We CAMERAS 4 35 SYM System Mode Register 4 36 T1CON Timer 1 Control 4 37 TACON Timer Control 4 38 Timer B Control Rogister eaii aea eee t eode Rete Pet 4 39 TINTPND Timer A 1 Interrupt Pending 4 40 VLDCON Voltage Level Detector Control Register 4 41 WTCON Watch Timer Control e enn 4 42 S3C8235B F8235B MICROCONTROLLER Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITS BOR BTJRF BTJRT BXOR CALL CCF CLR COM CP CPIJE CPIJNE DA DEC DECW DI DIV DJNZ EI ENTER EXIT IDLE INC INCW IRET JP JR LD LDB List of Instruction Descriptions Full Register Name N Logical AND Y L eene eee Honda IUE BELAND i eee eau ES Bit Compleient Ave cep eae e UE EU CERE M BIL OSC c cort o Et ttt ur eut demde tree de x tide d uL Bit Test Jump Relative on Bit Test Jump Relative on BIEXOB CR aane eum Ge I a Raa Gall ProcedUre soot eei us
8. 6 56 LDCPI LDEPI Load Memory with 6 57 LDW Load Word ite p ae ROUEN cur dab ees 6 58 MULT Multiply tisigned e d etc ttu AE S Ec ttu eum 6 59 NEXT Mm n 6 60 NOP 6 61 OR Cogita OR 6 62 Pop from Stack ue Et eed oce fite REN EH 6 63 POPUD Pop User Stack emen 6 64 POPUI Pop User Stack 6 65 PUSH Push to Stacke Lt aset en uet bi reti reta d of tle Meses 6 66 PUSHUD Push User Stack mener 6 67 PUSHUI Push User Stack Incrementing 6 68 RCF Reset Carry Flag OR Mie con de EVE oe CUR dec 6 69 RET tee le toS Lem E teen Me 6 70 RL Rotate ater tetendit ceto ie asd Ute 6 71 RLC Rotate Left through Carry 6 72 RR Rotate Hightech at et RE ER Re 6 73 RRC Rotate Right through Carry 0 eene 6 74 SBO Select Bank cione n e eene ated ca a ee c oes 6 75 SB1 Select Bank 1 kesh nob rete RD i p DEED sp PERS 6 76 SBC subtract with Cary s c irpoc S e Eod
9. Stop Mode PM ES Idle Mode Data Retention Mode 3 Execution of STOP Instruction Normal Operating Mode Interrupt NOTE 128 x 16 x 1 32768 62 5 ms Figure 19 5 Stop Mode sub Release Timing Initiated by Interrupts ELECTRONICS 19 7 ELECTRICAL DATA S3C8235B F8235B Table 19 6 A D Converter Electrical Characteristics TA 25 C to 85 2 5 V to 5 5 V Vas 0 V Resolution Total accuracy Integral Linearity Error Differential Linearity Error DLE CPU clock 8 MHz Offset Error of Top EOT Offset Error of Bottom Conversion time 1 10 bit resolution 50 x fxx 4 fxx 8 MHz Analog input voltage __ Analog reference voltage AV REF boom Vm V von f Analog block current 2 AV pr Vpp 3V AVper Vpp 5V When Power Down mode NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 lApcis an operating current during A D conversion 19 8 ELECTRONICS 53 8235 8235 ELECTRICAL DATA Table 19 7 Main Oscillator Frequency fosc1 TA 25 C to 85 C Crystal Main oscillation 2 7V 5 5V frequency 2 0V 5 5V Ceramic Main oscillation 2 7V 5 5V frequency 2 0V 5 5V E External clock Xy input frequency 2 7V 5 5V 2 0V 5 5V EUM u i Table 19 8 Main Oscillator Clock Stabiliza
10. 01234 56 ofi fifi fofi fofo Data Register page 2 Data Register page 2 Address 00H LD 00H 5Dh Address 01H LD 01H 2Eh Figure 14 6 LCD Signal and Wave Forms Example in 1 8 Duty 1 4 Bias Display Mode 14 8 ELECTRONICS 53 8235 8235 LCD CONTROLLER DRIVER 011 2 3 0 1 23 lt PI sra SEG3 1 e 7012345 6 7 1 Lofa fof d 0 12345 6 7 Data Register page 2 Data Register page 2 Address 03H Address 00H Data Register page 2 Data Register page 2 Address 02H LD 00H 0Eh Address 01H LD 01H 03h LD 02H 03h LD 03H 06h Figure 14 7 LCD Signals and Wave Forms Example in 1 4 Duty 1 3 Bias Display Mode ELECTRONICS 14 9 LCD CONTROLLER DRIVER 53 8235 8235 LCD VOLTAGE DRIVING METHOD By Voltage Booster For run the voltage booster enable the watch timer for fyooster Set LCON 1 0 to 01 for make enable voltage booster Recommendable capacitance value is 0 1 uF CA B C1 C2 C4 By Voltage Dividing Resistors Externally For make external voltage dividing resistors Set LCON 1 0 to 10 for make disable voltage booster floating the CA and CB pin Recommendable R 100 Kohm 1 3 Bias VLcb 3 at V pp 5 V 1 3 Bias VLcb 5 V at V pp 5 V 1 4 Bias VLcD 4 V at V pp 5 V Static V LcD 5 V at V pp 5 V NOTE About pin connection of CAP bias refer to chap
11. Vpp 0 1 V 0 1 V Figure 19 7 Clock Timing Measurement at ELECTRONICS 19 11 ELECTRICAL DATA S3C8235B F8235B Table 19 11 Analog Circuit Characteristics and Consumed Current Ta 25 85 C Vpp 2 0 V to 5 5 V a NE NEL V Liquid Crystal Connect a 1MQ LCON 7 5 0 drive Voltage Load resistance LCON 7 5 1 x 0 9 95 x 1 1 Between LCON 7 5 2 1 I TI I v c note LCON 7 5 3 No pannel load LCON 7 5 4 1 LCON 7 5 5 1 ae LCON 7 5 6 1 HS LCON 7 5 7 1 125 Connect 1Mohm load resistance 2x Vict 2x Vict between Vss and V cz ote x 0 9 x 1 1 No panel load Connect a 1Mohm load resistance 3 x Vig 3 x Vie between Vss and V c note x 0 9 x 14 No panel load Connect a 1Mohm load resistance 4 x Vic 4 x Vic between Vss and Vi cg note x 0 9 x 1 1 No panel load NOTES 1 The Vi cp should be less than or equal to Vpp when CAP bias mode is used to 1 8 duty 2 Itis characteristics when a 1 load resistor is connected to only a selected symbol V node The value of cN N 2 3 and 4 is determined by Vj that are measured Table 19 12 Characteristics of Voltage Level Detect Circuit TA 25 85 C Vpp 2 0 V to 5 5 V Hysteresis Voltage 1 0 00b 10 100 mV Slew Rate of VLD a 0 11b VLD Circuit aH Fw 32 768 kHz 1 0 ms Response Time 19 12 ELECTRONICS 53 8235
12. 1 3 PICASSO OHIO wes R 1 4 PIN IDESCrIPUONS Dm 1 6 Pri ssepe ce eee dte eed ee A Df iced ee 1 9 Chapter 2 Address Spaces e c ME 2 1 Program Memory ROM ice eoe docto rod aee doge ane v eee Roger SA eve rang 2 2 2 3 Register 2 4 Register Page Pointer PP u bea sted nay su Sau A 2 6 Register Set lu y u 2 7 Hegister au um Qa u ay dete t kapa Qha a aY UE o tei 2 7 Prime Register dv Idee voee eli Rude 2 8 Wotking Registets akakaw ku ush Spa 2 9 Using the Register Points iere av eee Ua 2 10 Register Addressing en 2 12 Common Working Register Area 2 14 4 Bit Working Register Addressing mene nme nne nnne 2 15 8 Bit Working Register 2 17 System and User Stack oie re RM 2 19 Chapter 3 Addressing Modes OVOIVIGW s art De d dot ed coe ge o ru edet aute etus 3 1 Register Addressing Mode R etr e RH PUR IRE ERU
13. 21 5 21 4 D C Electrical 21 5 22 1 Power Selection Settings for 8235 22 4 22 2 Power Selection Settings for EVA Chip Operation For using SMDS2 only 224 22 3 The SMDS2 Selection 8 22 5 S3C8235B F8235B MICROCONTROLLER xvii List of Programming Tips Description Page Number Chapter 2 Address Spaces Using the Page Pointer for RAM clear Page 0 1 2 6 Setting the Register 2 10 Using the RPs to Calculate the Sum of a Series of Registers 2 11 Addressing the Common Working Register 2 15 Standard Stack Operations Using PUSH and mene n ene n nne 2 20 Chapter 11 8 bit Timer A B Using the Timer Avis ie icd Ri edo ei ie ties des Mees oae e dea eva iu Po Le eed ats 11 8 Using the TMer D ia IT 11 9 Chapter 12 16 bit Capture Timer 1 Using the Timer Torsa eee ae n AE Mu ERE AA E A 12 5 Chapter 13 Watch Timer Using the Watch Timer t eeii 13 4 Chapter 14 LCD Controller Driver Using the ECD Display uy u S 14 14 Using the LCD Key Strobe and 14 16 Chapter 15 10 Bit Ana
14. di duda 1 12 1 14 Pin Circuit Type H 15 4 0000 1 13 2 1 Program Memory Address 2 2 2 2 SMart Option E dies 2 3 2 3 Internal Register File 2 5 2 4 Register Page Pointer nne nnne 2 6 2 5 Set 1 Set 2 Prime Area Register and LCD Data Register Map 2 8 2 6 8 Byte Working Register Areas 08 2 9 2 7 Contiguous 16 Byte Working Register 2 10 2 8 Non Contiguous 16 Byte Working Register 2 11 2 9 16 Bit Register Palpa a u oom abate eoe pie Beebe 2 12 2 10 Register File Addressing u a 2 13 2 11 Common Working Register 2 14 2 12 4 Bit Working Register 0 ee 2 16 2 13 4 Bit Working Register Addressing 2 16 2 14 8 Bit Working Register 0 2 17 2 15 8 Bit Working Register Addressing 2 18 2 16 stack Operations eR eren te e e e ene Ua dec V nuu 2 19 3 1 Register Addressirig 2 2 1 ev i 3 2 3 2 Working Register 0
15. 3 Level 3 IRQ3 Request Pending Bit 0 0 0 3 External Interrupts ot pending ending 2 Level 2 IRQ2 Request Pending Bit Timer 1 Match Capture or Overflow ot pending ending 4 Level 1 IRQ1 Request Pending Bit Timer Underflow Not pending je Pending 0 Level 0 IRQO Request Pending Bit Timer Match Capture or Overflow Not pending je Pending ELECTRONICS 4 1 CONTROL REGISTERS 53 8235 8235 KSCON Key Strobe Control Register EBH Set 1 Bank 1 Reset Value 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Key Strobe Enable Disable Selection Bit Key Strobe output disable 1 Key Strobe output enable 6 5 Not used for the S3C8235B F8235B 4 Strobe Duration Selection Bit 45 usec 1 5 clock 61 usec 2 0 clock 3 2 Strobe Interval Selection Bits 1 32 clock 2 msec 64 clock o 3 msec 96 clock 4 msec 128 clock 1 0 Key Strobe Output Port Selection Bits O Oj Pp 0 00 00 1 P24P27andPAOPA3 NOTE x means don t care 4 14 ELECTRONICS 53 8235 8235 CONTROL REGISTER Lcp Control Register DOH Set 1 Reset Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Booster Reference Voltage Selection Bits 4 Not used for the S3C8235B F8235B 3 2 LCD Dot On O
16. 0 7 nRESET input low width NOTE User must keep more large value then min value t INTL tINTH O ArIh m Figure 19 1 Input Timing for External Interrupts PO nRESET Figure 19 2 Input Timing for RESET ELECTRONICS 19 5 ELECTRICAL DATA 53 8235 8235 Table 19 4 Input Output Capacitance TA 25 C to 85 C OV Input CN f 1 MHz unmeasured pins capacitance are returned to Vac Output Cour capacitance capacitance Table 19 5 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 Data retention VpppR supply voltage Data retention IpppR 2V supply current RESET Occurs Oscillation Y Stabilization 31 Stop Mode Time lt Data Retention Mode lt Operating Mode D Execution of STOP Instrction nRESET NOTE is the same as 4096 x 16 x 1 fosc Figure 19 3 Stop Mode Release Timing Initiated by RESET 19 6 ELECTRONICS 53 8235 8235 ELECTRICAL DATA Oscillation Stabilization Time Y 4 31i Stop Mode l Idle Mode Data Retention Mode Normal Execution of Operating Mode STOP Instruction Interrupt twAiT is the same as 4096 x 16 x BT clock Figure 19 4 Stop Mode main Release Timing Initiated by Interrupts Oscillation Stabilization Time 44 0
17. Display is turned off LCDCK frequency is the watch timer clock fw 2 256 Hz The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source The LCD output voltage level is supplied by the voltage booster Table 14 2 Frame Frequency according to LCD Clock Signal LCDCK LMOD 3 2 LCDCK Static COMO 1 4 Duty COMO COM3 1 8 Duty COMO COM7 LT 256 ELECTRONICS 14 5 LCD CONTROLLER DRIVER 53 8235 8235 LCD Mode Control Register LMOD D1H Set 1 R W T TsTsT T5 T2 T2 T9 eo LCD SEG20 23 or I O port 4 Duty and Bias selection for LCD display selection bit 0 I O port 4 is selected 1 8 duty 1 4 bias 1 LCD SEG20 23 is selected 22 1 8 bias tatic LCD 5 16 19 or I O port 2 4 2 7 selection bit 3 LCD clock LCDCK selection bit 0 I O port 2 4 2 7 is selected 7 1 LCD SEG16 SEG19 is selected Ie fw 26 LCD 5 12 15 or I O port 2 0 2 3 tw 25 selection bit 0 I O port 2 0 2 3 is selected 2 1 LCD SEG12 SEG15 is selected LCD COM7 COM4 or I O port 1 4 1 7 selection bit 0 I O port 1 4 1 7 is selected 1 LCD COM7 COMA is selected NOTE The pull up resistor of Port 1 is disable when LMOD 4 1 Figure 14 4 LCD Mode Contol Register 14 6 ELECTRONICS 53 8235 8235 LCD CONTROLLER DRIVER LCD DRIVE VOLTAGE The LCD display is turned on only when the voltage difference between the c
18. O pins for capture input TACAP or PWM or match output TAPWM TAOUT Timer A overflow interrupt IRQO vector and match capture interrupt IRQO vector DEH generation Timer A control register TACON set 1 bank0 EAH read write ELECTRONICS 11 1 8 BIT TIMER A B S3C8235B F8235B FUNCTION DESCRIPTION Timer A Interrupts IRQO Vectors DEH and EOH The timer A module can generate two interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT TAOVF is interrupt level IRQO vector EOH TAINT also belongs to interrupt level IRQO but is assigned the separate vector address DEH A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer A match capture interrupt TAINT pending condition is also cleared by hardware when it has been serviced Interval Timer Function The timer A module can generate an interrupt the timer A match interrupt TAINT TAINT belongs to interrupt level IRQO and is assigned the separate vector address DEH When timer A measure interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware In interval timer mode a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the TA reference data register TADATA The match signal generates a timer A match interrupt TAINT vector DEH and clears the cou
19. INOOD 2915 9 81995 9d QV Z Ld VINOO 8H 19 Z ed 6L93S c9d 9QV 9 Ld SINOO 6H SM vrOd 0 vrd 0cO3S LOd SQV S Ld 9INOO OLH ISM SOd Fvd L293S 0Sd r V r Ld ZINOO 11915 99 995 QV Ld cLH1SM 49d vd e293S cQv e Ld Ld 0dV 0 Ld jJ3HAV LOTA COTA YOTA SSAV Vo ZINI dVO LL Z Od 53 8235 64 LQFP 1010 89 ONIW LNOVLINMdVL 0 Ed 9 LNI MO L L 9 0d S LNI LPYO LL S Od NTO Cy 4 C4 5 PO 2 INT2 6 SDAT PO 3 INT3 C 7 NT4 Cj 8 Vss Vss 10 VPP TEST C 13 P3 3 BUZ KIN3 PO 0 P3 1 TACK KIN1 C4 1 P3 2 TACAP KIN2 C 2 nRESET nRESET 16 SCLK PO 4 21 3 Figure 21 2 S3F8235B Pin Assignments 64 LQFP 1010 ELECTRONICS S3F8235B FLASH MCU 53 8235 8235 Table 21 1 Descriptions of Pins Used to Read Write the EPROM Main Chip During Programming P0 3 SDAT 7 Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port SCLK Serial clock pin Input only pin TEST Power supply pin for FlashROM cell writing indicates that FLASH MCU enters into the writing mode When 12 5 V is applied FLASH MCU is in writing mode and when 5 V is applied FLASH MCU is in reading mode Option nRESET nRESET 6 Chip Initialization Vpp Vss Vpop ss 9 10 Logic power supply pin Vpp should be tied to 5 V during programming Table 21 2 Comparison of S3F8235B and S3C8235
20. 8235 INSTRUCTION SET SRA shift Right Arithmetic SRA Operation Flags Format Examples dst dst 7 lt dst 7 C lt dst 0 dst n dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into the bit position 6 C Set if the bit shifted from the LSB position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 DO R D1 IR Given Register 9AH register 02H register OBCH and C 1 SRA 00H gt Register OOH OCD C 0 SRA 02H gt Register 02H register 0 In the first example if the general register contains the value 10011010B the statement SRA shifts the bit values in the register OOH right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in the destination register ELECTRONICS 6 79 INSTRUCTION SET 53 8235 8235 SRP SRPO SRP 1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples
21. BOR Bit or BOR BOR Operation Flags Format Examples 6 22 dst src b dst b src dst 0 lt dst 0 OR src b or dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 Undefined D Unaffected H Unaffected m Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 07 Rb ro NOTE In the second byte of the 3 byte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H BOR R1 01H 1 gt R1 07H register 01H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example the destination working register R1 contains the value 07H 00000111B and the source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of the register 01H source with bit zero of R1 destination This leaves the same value 07H in the working register R1 In the second example the destination register 01H contains the value 03H 00000011B and the source working register R1 the value 07H 00000111B The st
22. IRET END ELECTRONICS 8 TIMER Disable Global interrupt Enable IRQ1 interrupt Set stack area Disable Watch dog Enable TBPWM output Enable interrupt Duration 256 us 8 MHz x tal S3C8235B F8235B 16 BIT CAPTURE TIMER 1 16 BIT CAPTURE TIMER 1 OVERVIEW The 16 bit timer 1 is an 16 bit general purpose timer counter Timer 1 has three operating modes one of which you select using the appropriate T1CON setting Interval timer mode Toggle output at T1OUT pin Capture input mode with a rising or falling edge trigger at the T1CAP pin Timer 1 has the following functional components Clock frequency divider fxx divided by 64 8 or 1 with multiplexer External clock input T1CK TBUF A 16 bit counter T1 CNTH L a 16 bit comparator and two 16 bit reference data register 1 1 T1DATA2 pins for capture input T1CAP or match output T1OUT Timer 1 overflow interrupt IRQ2 vector E6H and match capture interrupt IRQ2 vector E4H generation Timer 1 control register T1 CON set 1 F1H Bank 1 read write ELECTRONICS 12 1 16 BIT CAPTURE TIMER 1 3C8235B F8235B FUNCTION DESCRIPTION Timer 1 Interrupts IRQ2 Vectors E4H and E6H The timer 1 module can generate two interrupts the timer 1 overflow interrupt T1OVF and the timer 1 match capture interrupt T1INT T1OVF is interrupt level IRQ2 vector E6H T1INT also belongs to interrupt level 2 but is assigned the separate
23. NOTE 6 80 src src src If src 1 1 src 0 Othen 3 7 lt src 3 7 If src 1 0 and src 0 1 RP1 3 7 lt src 3 7 If src 1 and src 0 Othen RPO 4 7 lt src 4 7 RPO 3 lt 0 4 7 lt src 4 7 3 lt 1 The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src src 2 4 31 IM The statement SRP 40H sets the register pointer 0 RPO at the location OD6H to 40H and the register pointer 1 RP1 at the location OD7H to 48 H The statement SRPO 50H would set RPO to 50H and the statement SRP1 68H would set RP1 to 68H Before execute the STOP instruction You must set the STPCON register as 101001010 Otherwise the STOP instruction will not execute ELECTRONICS 53 8235 8235 INSTRUCTION SET STOP Stop Operation STOP Operation Flags Format Example The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be release
24. 53 8235 8235 INSTRUCTION SET ENTER Enter ENTER Operation Flags Format Example Address IP PC Enter PC 22 Data Address H SP SP 2 SP lt IP IP lt PC PC lt IP lt IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex 1 14 1 The diagram below shows an example of how to use ENTER statement Before After Address Data IP 0043 Data Address Address 40 Enter 41 Address 42 Address L 43 Address H Address H Address L 110 i 20 IPH 00 Routine 21 IPL 50 22 Data Memory Stack Stack ELECTRONICS 6 41 INSTRUCTION SET 53 8235 8235 EXIT Exit EXIT Operation IP SP SP SP 2 PC IP P lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opc
25. NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware 5 6 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as
26. 8235 CONTROL REGISTER CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the S3C8235B F8235B register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Register Name Mnemonic LCD control register LCD mode register Basic timer control register Clock Control register System flags register Register pointer 0 Register pointer 1 Stack pointer high byte Stack pointer low byte Instruction pointer high byte Instruction pointer low byte ELECTRONICS 4 1 CONTROL REGISTERS 53 8235 8235 Table 4 2 Set 1 Bank 0 Registers Port 0 Data Register 224 R W Port 1 Data Register 225 R W Port 2 Data Register 226 R W Port 3 Data Register 227 Port 4 Data Register 228 Port 0 interrupt control register Port 0 interrupt pending register Port 3 interrupt control register Port 3 interrupt pending register Timer A Timer 1 interrupt pending register 233 Timer A control register 234 Timer A counter register 235 Timer A data register 236 ECH R W Timer B control register 237 EDH R W Timer B data r
27. BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS 53 8235 8235 Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SBO SB1 SCF SRP src SRP0 src SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode INSTRUCTION SET 53 8235 8235 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits which describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions Two other flag bits FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether register bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as
28. Input mode Input mode pull up Push pull output SEG20 Key strobe KSTR9 output enable Alternative function PG4 output Figure 9 13 Port 4 Control Register P4CON 9 16 ELECTRONICS 53 8235 8235 BASIC TIMER BASIC TIMER OVERVIEW BASIC TIMER BT You can use the basic timer BT in two different ways As watchdog timer to provide an automatic reset mechanism in the event of a system malfunction signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter BTCNT set 1 bank 0 FDH read only Basic timer control register BTCON set 1 D3H read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using register addressing mode A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of 13 4096 To disable the watchdog function write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON A The 8 bit basic timer counter BTCNT set 1 bank 0 FDH can be c
29. WATCH WATCH CIRCUIT DIAGRAM BUZZER Output WTCON 5 WTCON 6 WTCON 4 WTCON 3 fw 64 0 5 kHz fw 32 1 kHz fw 16 2 kHz WTCON 1 eae fw 8 4 kHz d won Circuit Ill fw 27 WTCON 7 Clock posee Selector 39 768kHz Circuit fLcp 2 KHZ fvLD 4096 HZ fBOOSTER 4096 HZ fx 128 fx Main Clock where fx 4 19 MHz fxt Subsystem Clock 32 768 Hz fw Watch timer frequency Figure 13 1 Watch Timer Circuit Diagram ELECTRONICS 13 3 WATCH TIMER 59 PROGRAMMING TIP Using the Watch Timer INITIAL MAIN WT INT ORG 0000h VECTOR OE8h WT INT ORG 0100h LD SYM 00h i LD IMR 00100000b SPH 00000000b i LD SPL 00000000b LD BTCON 10100011b LD WTCON 11001110b MAIN ROUTINE JR T MAIN AND WTCON 11111110b IRET END S3C8235B F8235B Disable Global interrupt Enable IRQB5 interrupt Set stack area Disable Watch dog 0 5 KHz buzzer 3 91ms duration interrupt 8 MHz x tal pending clear ELECTRONICS 53 8235 8235 LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S3C8235B micro controller can directly drive an up to 192 dot 24 segment x 8 common LCD panel The LCD module has the following components LCD controller driver Display RAM 00H 17H for storing display data in page 2 24 segment output pins SEGO SEG23 8 common output pins COMO 4 LCD operati
30. 0 Key strobe output disable 00 P4 0 P4 3 1 Key strobe output enable P2 4 P2 7 and P4 0 P4 3 P2 0 P2 7 and P4 0 P4 3 Not used for the S3C8238B C8235B Interval between strobe start edge synchronous to frame frequency 00 1 msec 32 clock 0 1 2 msec 64 clock 10 3 msec 96 clock 1 1 14 msec 128 clock Strobe duration 0 45 usec 1 5 clock 1 61 usec 2 clock NOTE x means don t care Figure 14 9 Key Strobe Contol Register NOTES 1 When you want to configure SEG12 SEG23 pins as key strobe output you must configure P2 and P4 output mode previously 2 enable key input you must configure PSCON as input mode external interrupt or alternative mode 3 If SEG12 SEG23 pins used as only key strobe output should be configured input mode external Interrupt but SEG12 SEG23 pins are used as both SEG signal output and key strobe output should be configured alternative mode ELECTRONICS 14 11 LCD CONTROLLER DRIVER 53 8235 8235 Sub clock 32768 Hz Key strobe 1 Pull up srt Key input check Pull up enable Key input check Key input enable Key input enable Figure 14 10 Key Input Check Sequence During Key Strobe Out Duration 14 12 ELECTRONICS 53 8235 8235 LCD CONTROLLER DRIVER lt 1 Frame 1st strobe 1st strobe KS KSDATA 0001 1 Tinterval 1 VLC3 2 VLC1 VLCO When other SEG pin output strobe this SEG pin m
31. Clear pending bit when write Interrupt pending 0 Timer A Match Capture Interrupt Pending No interrupt pending EJ Clear pending bit when write Interrupt pending 4 40 ELECTRONICS 53 8235 8235 CONTROL REGISTER VLDCON Voltage Level Detector Control Register F1H Set 1 Bank 0 Reset Value 0 0 0 0 Read Write R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the S3C8235B F8235B 3 VLD Level Set Bit 2 VLD Operation Enable Bit Operation off 1 0 Reference Voltage Selection Bits 1 0 Vapsdsy ELECTRONICS 4 41 CONTROL REGISTERS 53 8235 8235 WTCON watch Timer Control Register F2H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Watch Timer Clock Selection Bit EJ Main system clock divided by 2 fxx 128 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit Disable watch timer interrupt nable watch timer interrupt 5 4 Buzzer Signal Selection Bits 0 5 kHz buzzer BUZ signal output 1 kHz buzzer BUZ signal output 2 kHz buzzer BUZ signal output 4 kHz buzzer BUZ signal output 3 2 Watch Timer Speed Selection Bits o o osmema _ fo 1 0 5 s Interval 0 25 s Interval 3 91 ms Interval 1 Watch Timer Enable Bit Disable watch timer Clear frequency dividing circuits 1 En
32. Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then two write will simultaneously occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 RW wo B Bank address status flag BA Fast interrupt status flag FS Carry flag C Zero flag 2 Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS 53 8235 8235 INSTRUCTION SET FLAG DESCRIPTIONS C carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations have been performed it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Z Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero In operations that test register bits and in shift and rotate operations the Z flag is set to 1 if the result is logic zero S Sign Flag FLAGS 5 Following arithmetic logic rotate
33. Min Tp Max Unit UE 4 MHz crystal oscillator Ippe Idle mode Vpp 5 V 10 3 10 8 MHz crystal oscillator 4 MHz crystal oscillator Idle mode Vpp 3 V 10 1 2 3 8 MHz crystal oscillator 4 MHz crystal oscillator i EKARA Sub idle mode main osc stop 32768 Hz crystal oscillator Vpp 5 V 10 Vpp 3 V 10 Main stop mode sub osc stop Vpp 5 V 10 TA 25 Sub operating main osc stop 32768 Hz crystal oscillator Vpp 5 V 10 3 V 10 Vpp 3 V 10 TA 25 C NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 lpp4 and include a power consumption of subsystem oscillator 3 and Ipp are the current when the main system clock oscillation stop and the subsystem clock is used And they does not include the LCD and Voltage booster and voltage level detector current Ipps is the current when the main and subsystem clock oscillation stop Voltage booster s operating voltage rage is 2 0V to 5 5V If you use LVR module supply current increase refer to Table 19 13 If the selected Vj yp voltage is typically 2 6V or 3 6V by smart option All the current items at Vpp are useless 19 4 ELECTRONICS 53 8235 8235 ELECTRICAL DATA Table 19 3 A C Electrical Characteristics TA 25 C to 85 C Vpp 2 0 V to 5 5 V Interrupt input high low width
34. Push pull output Alternative mode KIN2 Key input Only falling edge interrupt When key strobe output is enable KSCON 7 1 port status is high impedence during interval and pulled up during strobe out 3 2 bit P3 1 TACK KIN1 Input mode External interrupt TACK input Push pull output Alternative mode KIN1 Key input Only falling edge interrupt When key strobe output is enable KSCON 7 1 port status is high impedence during interval and pulled up during strobe out 0 bit P3 0 TAPWM TAOUT KINO Input mode External interrupt TAPWM or TAOUT output Push pull output Alternative mode KINO Key input Only falling edge interrupt When key strobe output is enable KSCON 7 1 port status is high impedence during interval and pulled up during strobe out Figure 9 10 Port 3 Control Register P3CON 9 14 ELECTRONICS 53 8235 8235 Port 3 Interrupt Control Register P3INT E7H Set 1 Bank 0 R W ve 2 2 Interrupt Enable Disable Selection Ox Interrupt disable 10 Interrupt enable falling edge 11 Interrupt enable rising edge NOTE When you want to use any pin in P3 as alternative mode to get a key input KINO KIN3 then you have to choose only falling edge interrupt Figure 9 11 Port 3 Interrupt Control Register P3INT Port Interrupt Pending Register PBPND E8H Set 1 Bank 0 R W
35. SEGO SEG 11 LCD Segment signal output 345 H H H SEG12 SEG19 LCD Segment signal output 14 46 53 P2 0 P2 7 KSTR1 KSTR8 SEG20 SEG23 LCD Segment signal output 15 54 57 P4 0 P4 3 KSTR9 KSTR12 D 4 verve _ 59 Remote controller signal output Carrier EE output or PWM output 4 Po amp Po uz vo Buxzersigraioup pe s vo Tmora caprei pe 2 ae vo WmeAQeksucemu PM ELECTRONICS 1 7 PRODUCT OVERVIEW S3C8235B F8235B Table 1 1 S3C8235B F8235B Pin Descriptions Continued m EDO Type Description Type Functions Test signal input pin for factory use only 13 must be connected to Main oscillator pins Sub oscillator pins NEED E e TEST Pow Mo 1 vss ower supply input pin Ground pin 10 1 8 ELECTRONICS 53 8235 8235 PIN CIRCUITS Pull Up Resistor Schmitt Trigger Figure 1 4 Pin Circuit Type B nRESET P Channel Out Output N Channel Disable Figure 1 5 Pin Circuit Type C ELECTRONI S PRODUCT OVERVIEW Figure 1 6 Pin Circuit Type D 2 P3 Pull up Data ERE Enable Pin Circuit o lo Output Disable Ext INT Data Figure 1 7 Pin Circuit Type D 4 0 0 0 7 except P0 4 1 9 PRODUCT OVERVIEW Pull up Enable P0 4 Data TB Underflow DOE Carrier on off P0 4 Pin Circuit Typ
36. previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent ELECTRONICS 5 17 53 8235 8235 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and blocks can issue interrupt requests In other words peripheral and operations are interrupt driven There are eight possible interrupt levels IRQ0 IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C8235B F8235B interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt prior
37. register 01H 01H If the destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS 53 8235 8235 INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b dst b NOT dst b This instruction complements the specified bit within the destination without affecting any other bit in the destination C Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst b 0 2 4 57 rb opo NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC R1 1 gt R1 05H If the working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in the register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET 53 8235 8235 BI
38. register 40H 80H DIV RRO R2 m RO R1 40H DIV RRO GR2 gt RO 03H R1 20H DIV RRO 20H gt RO 03H R1 80H In the first example the destination working register pair RRO contains the values 10H RO and 03H R1 and the register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 ELECTRONICS 53 8235 8235 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ Operation NOTE Flags Format Example r dst 1 If r z 0 PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement In case of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO SRP 1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8
39. register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B ELECTRONICS 2 15 ADDRESS SPACES 53 8235 8235 Selects RPO or Address O
40. system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information El S Q Interrupt Request Register nRESET R Read only IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM O manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer A overflow TINTPND E9H bank 0 Timer A match capture TACON EAH bank 0 TACNT EBH bank 0 TADATA ECH bank 0 Timer B underflow IRQ1 TBCON EDH bank 0 TBDATAH TBDATAL EEH EFH bank 0 Timer 1 overflow TINTPND E9H bank 0 Timer 1 match
41. toggle with match flow INT overflow IRQ2 INT T1CON 1 M 4 bit y x match capture T 1PS High 4 bit T1CON 4 3 PG output trigger signal T1DATA2 16 bit Figure 12 2 Timer 1 Functional Block Diagram NOTES 1 When capture mode is running the 16 bit counter must be cleared if capture signal is inputted An actual time of capture operation is determined by POCONH 7 6 register on the contrary T1CON 4 3 determines the period of interrupt 2 In interval mode only T1DATA1 register is used for comparison with the 16 bit counter T1DATA2 register is not used 3 In 4 bit prescaler using low 4 bit of T1PS register the clock frequency inputted to the 16 bit counter is divided by m1 where the value of low 4 bit is m Similarly with 4 bit prescaler using high 4 bit the frequency of T1OUT signal is divided by n1 where the value of high 4 bit is n 4 If you set POCONH 7 6 at 00 TIDATA1 used as period is loaded with T1CNT at rising edge when T1CNT is cleared T1DATA 2 used as upper duration is loaded with T1CNT at falling edge when T1CNT continues to increase If you set POCONH 7 6 at 11 TIDATA1 used as lower duration is loaded with T1CNT at rising edge when T1CNT continues to increase T1DATA2 used as period is loaded with T1CNT at falling edge when T1CNT is cleared T1CON4 3 informs only when capture occurs Only T1DATA 1 is used to compare to T1CNT in match mode When setting T1 CON 2 T1ONT is clea
42. 00H Z0AH LD 00H 10H gt LD 00H 02H LD RO LOOP R1 LD LOOP RO R1 6 50 a se Se ale Se ek 4 i4 RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 register 01H Register 20H register 01H 20H Register 02H 20H register OOH 01H Register 00H 0AH egister 01H register 01H 10H Register 01H register 01H register 02H 02H RO OFFH R1 OAH Register OAH RO 01H R1 OAH 02 ELECTRONICS 53 8235 8235 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 47 Rb m NOTE n the second byte of the instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register OOH 05H LDB R0 00H 2 gt RO 07H register OOH 05H LDB 00H 0 RO gt RO 06H register OOH 04H In the first example the destination working register RO contains the
43. 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS 53 8235 8235 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Address Used Memory Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES 53 8238 8235 8235 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory lt Next Instruction LSB Must be Zero dst Current Instruction OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS 53 8235 8235 RELATIV
44. 11100011B ELECTRONICS 6 83 INSTRUCTION SET 53 8235 8235 TCM rest Complement under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir opc src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register 2BH register 01H 02H and register 02H 23H TCM RO R1 gt RO OC7H R1 02H Z 1 TCM RO R1 gt RO OC7H R1 02H register 02H 23H 2 TCM 00H 01H gt Register 00H 2BH register 01H 02H Z 1 TCM 00H 01H gt Register OOH 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register OOH 2BH Z 0 In the first example if the working register RO contains the value 0C7H 11000111B and the register R1 the value 02H 00000010B the statement
45. 22h 1Ch 0 0 0 0 0 0 LCD CONTROLLER DRIVER 14 15 LCD CONTROLLER DRIVER 53 8235 8235 S Programming Tip Using the LCD Key Strobe and Display ORG 0000h VECTOR OFEh KEY INT ORG 0100h INITIAL LD SYM 00h Disable Global interrupt LD IMR 10000000b Enable IRQ7 interrupt LD SPH 00000000b Set stack area LD SPL 00000000b LD BTCON 1010001 1b Disable Watchdog SB1 LD P1CONH 10101010b Enable COM signal output LD P2CONH 10101010b Enable SEG signal output LD P2CONL 10101010b Enable SEG signal output LD P4CON 10101010b Enable SEG signal output LD P3CON 11111111b Enable Key strobe input SBO LD 8101010100 Key input falling edge int LD WTCON 10001110b Clock generation for LCD display LD LCON 01001101b CAP bias Enable LCD display LD LMOD 11111000b 1 8duty amp 1 4bias SB1 LD KSCON 10011111b All ports are used as key strobe SBO LCD RAM clear routine area page2 00h 17h LD R0 17h LCD CLR LD PP 20h LD RO 0 DJNZ RO LCD_CLR LD RO 0 LD PP 00h CLR RO CLR R1 CLR R6 EI 14 16 ELECTRONICS 53 8235 8235 LCD CONTROLLER DRIVER Programming Tip Using the LCD Key Strobe and Display Continued MAIN DSP_LOOP DSP_DAT NOP NOP NOP CLR CLR LD ADD LDC LD LD INC INC JP ELEGTRONIGS R6 R1 R4 0 R5 RO R5 R1 R3 DSP_DAT RR4 PP 20H R6 R3 PP 00 R1 R6 R1 24 ULT DSP_LOOP T MAIN 080h 1 2 3 4 5 6 7 8
46. 3 2 3 3 Indirect Register Addressing to Register 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 Indirect Working Register Addressing to Register 3 5 3 6 Indirect Working Register Addressing to Program or Data 3 6 3 7 Indexed Addressing to Register 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data 3 9 3 10 Direct Addressing for Load 3 10 3 11 Direct Addressing for Call and Jump Instructions 3 11 3 12 Indirect Addressing eer Ce eel E 3 12 3 13 Relative Addressing eie due dude 3 13 3 14 Immediate Addressing 4 0 enne enne nnn 3 14 S3C8235B F8235B MICROCONTROLLER xi List of Figures Continued Figure Title Page Number Number 4 1 Register Description 4 4 5 1 S3C8 Series Interrupt 5 2 5 2 S3C8235B F8235B Interrupt 5 4 5 3 ROM Vecto
47. 3 byte instruction formats the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bitin length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example the source register 01H contains the value 05H 00000101B and the destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit 0 value of the register R1 destination leaving the value 06H 000001 10B in the register R1 ELECTRONICS 6 17 INSTRUCTION SET 53 8235 8235 BCP sit Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison C Unaffected Z Setif the two bits are the same cleared otherwise S Oleared to O V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src NOTE Inthe second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H BCP R1 01H 1 gt R1 07H
48. 4 MHz crystal oscillator Idle mode Vpp V 10 1 2 3 8 MHz crystal oscillator 4 MHz crystal oscillator EE M Sub idle mode main osc stop 32768 Hz crystal oscillator Vpp 5 V 10 96 Vpp 3 V 10 96 Sub operating main osc stop 32768 Hz crystal oscillator Vpp 5 V 10 3 V 10 Main stop mode sub osc stop 5 V 10 Ty 25 C 3V 10 TA 25 3 and lpp4 are the current when the main system clock oscillation stop and the subsystem clock is used And they does not include the LCD and Voltage booster and voltage level detector current Ipps is the current when the main and subsystem clock oscillation stop Voltage booster s operating voltage rage is 2 0V to 5 5V If you use LVR module supply current increase refer to Table 19 13 If the selected Vj yp voltage is typically 2 6V or 3 6V by smart option All the current items at Vpp are useless ELECTRONICS 21 7 S3F8235B FLASH MCU 53 8235 8235 Supply Voltage V Minimum instruction clock 1 4 x oscillator frequency Figure 21 3 Operating Voltage Range 21 8 ELECTRONICS 53 8235 8235 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer tha
49. 8235 ELECTRICAL DATA Table 19 13 LVR Low Voltage Reset Circuit Characteristics TA 25 LVR Voltage Vi vR 2 3 E 5 voltage rising 10 LVR circuit consumption IppPR Vpp 5V 10 bep NOTES 1 216 8 19 ms at fx 8 MHz 2 Current consumed when Low Voltage reset circuit is provided internally Figure 19 8 LVR Low Voltage Reset Timing ELECTRONICS 19 13 ELECTRICAL DATA 53 8235 8235 Supply Voltage V Minimum instruction clock 1 4 x oscillator frequency Figure 19 9 Operating Voltage Range 19 14 ELECTRONICS 53 8235 8235 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C8235B microcontroller is currently available in 64 QFP 64 LQFP package 23 90 0 30 17 90 0 30 14 00 0 20 e I 5 0 05 MIN 2 65 0 10 0 80 0 20 NOTE Dimensions are in millimeters Figure 20 2 64 QFP 1420F Package Dimensions ELECTRONICS 20 1 MECHANICAL DATA 53 8235 8235 12 00 BSC 64 1 1010 12 00 BSC 10 00 BSC 1 0 07 0 20 0 03 1 60 MAX 1 40 0 05 0 45 0 75 Figure 20 3 64 LQFP 1010 Package Dimensions 20 2 ELECTRONICS 53 8235 8235 S3F8235B FLASH MCU 2 1 53 8235 FLASH MCU OVERVIEW The SSF8235B single chip CMOS microcontroller is the Flash MCU version of the S3C8235B microcontroller It has an on chip
50. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 14 17 LCD CONTROLLER DRIVER 53 8235 8235 S Programming Tip Using the LCD Key Strobe and Display Continued KEY INT PUSH LD LD AND TM JP TM JP TM JP JP KEY INT KINO ADD JP KEY INT ADD JP KEY INT KIN2 ADD JP KEY INT KIN3 ADD JP WHAT KEY LD POP IRET END 14 18 PP PP 00H RO KSDATA R0 00001111b P3PND 00000001b NZ KEY INT KINO P3PND 00000010b NZ KEY INT P3PND 00000100b NZ KEY_INT_KIN2 KEY_INT_KIN3 R0 0 WHAT KEY R0 12 WHAT_KEY R0 24 WHAT KEY R0 36 WHAT_KEY P3PND 00b PP Mask high 4 bit of ksdata Check KIN0 Check KIN1 Check KIN2 pending clear ELECTRONICS 53 8235 8235 A D CONVERTER 10 BIT ANALOG TO DIGITAL CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values The analog input level must lie between the AVper and AV ss values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type control register ADCON AD i
51. A SECO Ot ga E M Dea a Lied a 6 13 vi 3C8235B F8235B MICROCONTROLLER Table of Contents Continued Part Hardware Descriptions Chapter 7 Clock Circuit s EG Ee et cA si s E deccm cid 7 1 System Glock GIFCUIE oco coe e e Eee eee eg evt o eee 7 1 Main Oscillator er cese 7 2 SUB Oscillatot CIrGUits UL anu et E er ED e ae Rod 7 2 Clock Status During Power Down ee emen n 7 3 System Clock Control Register 7 4 Oscillator Control Register 05 7 5 Switching The GPU CIOCK it ott oo eet t o b Er E Ee 7 6 Chapter 8 RESET and Power Down System RESET cei ote e eeu dea etd Dt ad wc edu 8 1 Qu C UI 8 1 Normal Mode Reset 8 1 Hardware Reset Valugs ere adco m A 8 2 Power Down Modes mE 8 5 exuere 8 5 Idle foo 8 6 Chapter 9 I O Ports Sa S 9 1 uua e EE 9 7 POM 9 11 gc c S 9 13 aD p M 9 16 Chapter 10 Basic Timer S c
52. C to 85 C Vpp 2 0 V to 5 5 V Output high voltage Vpp 2 4 Vi lgu 4 mA Vpp 0 7 Vpp 0 3 Port 0 4 only Vou Vpp 5 V 4 mA Port 3 Vous 5V 1 mA All output pins except P0 4 P3 Output low voltage Vou Vpp 2 4 V Io 12 mA P0 4 only Vpp 5V Io 15 P3 5 lg 4 All output pins except P0 4 P3 Input high leakage current lii VN Vpp All input pins except iio li2 Vpp XTN Input low leakage current VN 0V All input pins except gt VN7 OV Xy XTN lou All I O pins and Output pins lo 0 All I O pins and Output pins Rosci Vpp 5 0 25 Xn Xour 0 V Port 0 1 2 4 TA 25 C Output high leakage current Output low leakage current Oscillator feed back resistors Pull up resistor L2 Vin 0 V Vpp 5 V 1096 TA 25 C nRESET only COM output Vpp Vica 24V voltage deviation Vi IO 15 p uA i 0 3 Vpp 4 V Vi cs SEGi IO 15 p uA i 0 23 lt g O SEG output voltage deviation lt IE ELECTRONICS 19 3 ELECTRICAL DATA S3C8235B F8235B Table 19 2 D C Electrical Characteristics Concluded TA 25 C to 85 Vpp 2 0 V to 5 5 V Supply current 1 2 Vpp 5 V 10 8 MHz crystal oscillator 3 V 10 8 MHz crystal oscillator
53. EE 3 2 Indirect Register Addressing Mode 3 3 Indexed Addressing Mode n nennen nnn nennen EAA TRAN 3 7 Direct Address Mode IDA si aroi ieran Meet tede ide ipu do Meet Ete eren Medo n 3 10 Indirect Address rideo re E aei piven MR eue Res EYE NES RARE ERE AREE di 3 12 Relative Address Mode PA eoe tend ea Dec A Dade tod E Me Doce pet dud 3 13 hu usestcRueeSlmee 3 14 S3C8235B F8235B MICROCONTROLLER Table of Contents Continued Chapter 4 Control Registers 4 1 Chapter 5 Interrupt Structure SIMI ELI DELI 5 1 Interrupt orc 5 2 S3C8235B F8235B Interrupt w 5 3 Interrupt 0 565 252 niin iiie eNA ite caves dag Doe o Dea ete DOE a e c dde gas 5 5 Enable Disable Interrupt Instructions El 5 7 System Level Interrupt Control Registers 5 7 Interrupt Processing Control 5 8 Peripheral Interrupt Control Registers 5 9 System Mode Register
54. Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 0 P3 0 KINO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending NOTE When you want to use any pin in P3 as alternative mode to get a key input KINO 3 then you have to choose only falling edge interrupt ELECTRONICS 4 2 CONTROL REGISTERS 53 8235 8235 PACON Port 4 Control Register EAH Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 3 SEG23 PG7 KSTR12 o o mumm 1 0 Push pull output SEG23 Key strobe KSTR12 output enable Alternative function PG7 output 5 4 P4 2 SEG22 PG6 KSTR11 o o mame o Push pul ouput SEG22 Cey RSTRNT 3 2 P4 1 SEG21 PG5 KSTR10 o o mumd o mume 71 0 Push pull output SEG2U Key sobe KSTRIO output enai Alternative function PG5 output 1 0 P4 0 SEG20 PG4 KSTR9 ofofo 1 0 Push pull output SEG20 Key strobe KSTR9 output enable Alternative function PG4 output 4 30 ELECTRONICS 53 8235 8235 CONTROL REGISTER PGCON Pattern Generation Control Register F5H Set 1 Bank 0 Reset Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register add
55. Key strobe KSTR8 output enable Open drain output SEG19 Key strobe KSTR8 output enable 5 4 P2 6 SEG18 KSTR7 o o mume o Push pul output 8618 sobe KSTAT output erabe UU 3 2 P2 5 SEG17 KSTR6 o o mame Co _ Push pul output SEGIKeysrobe KSTRGGupurenabe 1 0 P2 4 SEG16 KSTR5 o o mame ON 1 0 Push pull output SEG16 Key strobe KSTRS output enable Open drain output SEG16 Key strobe KSTR5 output enable ELECTRONICS 4 25 CONTROL REGISTERS 53 8235 8235 P2CONL Port 2 Control Register Low Byte E7H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 SEG15 KSTRA o o mamm 1 0 Push pull output SEG15 Key strobe KSTR4 output enable Open drain output SEG15 Key strobe KSTR4 output enable 5 4 P2 2 SEG14 KSTR3 o o mame Push pul ouput SEG AiKey KSTRGouporenabe 3 2 P2 1 SEG13 KSTR2 o o mame o i imeut mose paro Push pul ouput SEGT3 Cey sobe KSTRZ output erabe 1 0 P2 0 SEG12 KSTR1 o o mame 1 0 Push pull output SEG12 Key strobe KSTR1 output enable Open drain output SEG12 Key strobe KSTR1 output enable 4 26 ELECTRONICS 3C8235B F8235B CONTR
56. Level 3 IRQ3 Enable Bit External Interrupts 0 0 0 3 Disable mask 1 Enable un mask 2 Interrupt Level 2 IRQ2 Enable Bit Timer 1 Match Capture or Overflow Disable mask 1 Enable un mask 1 Interrupt Level 1 IRQ1 Enable Bit Timer B Underflow Disable mask 1 Enable un mask 0 Interrupt Level 0 IRQO Enable Bit Timer A Match Capture or Overflow Disable mask 1 Enable un mask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU 4 10 ELECTRONICS 53 8235 8235 CONTROL REGISTER IPH instruction Pointer High Byte DAH Set 1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address 15 8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH ELECTRONICS 4 11 CONTROL REGISTERS 53 82
57. NCW R1 uses Indirect Register IR addressing mode to increment the contents of the general register 03H from OFFH to 00H and the register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem it is recommended to use the INCW instruction as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET 53 8235 8235 IRET Interrupt Return IRET Operation Flags Format Example NOTE 6 46 IRET Normal RET Fast FLAGS SP PC o IP SP SP 1 FLAGS FLAGS PC SP FIS 0 SP SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Normal Hex opc 1 12 BF IRET Bytes Cycles Opcode Fast Hex opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupt are enabled When an interrupt
58. System clock selection Main oscillator control Sub oscillator control OSCCON 0 register settings select Main clock or Sub clock as system clock After a reset Main clock is selected for system clock because the reset value of OSCCON 0 is The main oscillator can be stopped or run by setting OSCCON 3 The sub oscillator can be stopped or run by setting OSCCON 2 Oscillator Control Register OSCCON F3H Set 1 Bank 0 R W 7 T4 T2 e Not used System clock selection bit 0 Mainsystem oscillator select 1 Subsystem oscillator select Not used Subsystem oscillator control bit 0 Subsystem oscillator RUN 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP When the CPU is operated with fxt sub oscillation clock it is possible to use the stop instruction but in this case before using stop instruction you must select fxx 128 for basic timer counter clock input Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms Here the warm up time is from the stop release signal activates until the basic timer counter counting start So the totaly needed oscillation stabilization time will be less than 162 5 ms Figure 7 8 Oscillator Control Register OSCCON ELECTRONICS 7 5 CLOCK CIRCUIT 53 8235 8235 SWITCHING THE CPU CLOCK Data loading in the oscillator control register OSCCON determi
59. TCM 0 1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS 53 8235 8235 INSTRUCTION SET TM Test under Mask TM Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir opc src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO 0C7H R1 02H R2 18H register 2BH register 01H 02H and register 02H 23H TM RO R1 gt RO OC7H R1 02H 2 0 RO R1 gt RO OC7H R1 02H register 02H 23H 2 0 TM 00H 01H gt Register OOH 2BH register 01H 02H Z 0 TM 00H 01H gt Register OOH 2BH register 01H 02H register 02H 23H Z 0 TM 00H 54H gt Register 00H 2BH Z 1 In the first example if th
60. W R W R W Addressing Mode 7 5 4 3 ELECTRONI S Register addressing mode only Timer 1 Input Clock Selection Bits iC Timer 1 Operating Mode Selection Bits o o mewimd fo 1 Capture mode Capture on falling edge OVF can occur oo Capture mode Capture on rising edge OVF can occur Capture mode Capture on both edge OVF can occur Timer 1 Counter Enable Bit zi No effect 1 Clear the timer 1 counter Auto clear bit Timer 1 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt Timer 1 Overflow Interrupt Enable Bit Disable overflow interrupt 1 Enable overflow interrupt 4 3 N CONTROL REGISTERS 53 8235 8235 TACON rimer A Control Register EAH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer Input Clock Selection Bits ofopwa SSS opes SSCS 00000 02 5 4 Timer Operating Mode Selection Bits o Interval mode TAOUT mode fo Capture mode capture rising edge counter running OVF can occur Lil Capture mode capture on falling edge counter running OVF can occur PWM mode OVF interrupt can occur 13 Timer Counter Clear Bit 3 No effect 1 Clear the timer A counter After clearing return to zero 2 3 er A Overflow Interrupt Enable Bit Disable o
61. capture T1CON F1H bank 1 T1CNTH F2H bank 1 TICNTL F3H bank 1 T1DATA1H bank 1 T1DATA1L F5H bank 1 T1DATA2H F6H bank 1 T1DATA2L F7H bank 1 T1PS F8H bank 1 0 3 external interrupt POCONL E1H bank 1 0 2 external interrupt POINT E5H bank 0 P0 1 external interrupt POPND E6H bank 0 0 0 external interrupt P0 7 external interrupt POCONH EOH bank 1 0 6 external interrupt POINT E5H bank 0 0 5 external interrupt POPND E6H bank 0 P0 4 external interrupt Watch timer overflow IRQ5 WTCON F2H bank 0 AD Interrupt ADCON F7H bank 0 ADDATAH F8H bank 0 ADDATAL F9H bank 0 ADINT FAH bank 0 P1CONH E4H bank 1 P1CONL E5H bank 1 Key strobe interrupt IRQ7 KSCON EBH bank 1 em ommo ELECTRONICS 5 9 INTERRUPT STRUCTURE 53 8235 8235 SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing see Figure 5 5 A reset clears SYM 0 to 0 The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the and DI instructions for this purpose System Mode R
62. dst src b If src b is a 1 then PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC Otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst Src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If the working register R1 contains the value 07H 000001 11B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location addressed by the BTJRT instruction must be within the allowed range of 127 to 128 ELECTRONICS 53 8235 8235 INSTRUCTION SET BXOR Bit xon BXOR BXOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or the source The result bit is stored in the specified bit of the destination No other bits of the de
63. ee Ree YR ERE 6 77 SCF Set Carry Flag toii ed o todo ence tede ied a to PE euo Ped dia ls 6 78 SRA Shift Right Arithimetie 5 ep PING ER ERE 6 79 SRP SRPO SRP1 Set Register Poirier uid cvi cena de do cag o V ene vds 6 80 STOP Slop Operation cysteine Cen te A i Cei a C e a 6 81 SUB Gail 2 ERE 6 82 SWAP Swap NIDDICS Lu US 6 83 TCM Test Complement under 6 84 TM Test nder Mask EE 6 85 WFI OMUR rectc ere ene iere k aa uQ ere can eene rete unns 6 86 XOR Logical Excl siVe up ien etin am xr 6 87 S3C8235B F8235B MICROCONTROLLER xxiii 53 8235 8235 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes The major CPU features are Efficient register oriented architecture Selectable CPU clock sources Idle and Stop power down mode released by interrupt or reset Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors 53 8235 8235 MICROCONTROLLER The S3C8235B F8235B single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process based on Samsung s latest C
64. function PG2 output 9 2 bit P1 5 PG1 AD5 COM6 Input mode AD5 converter input Normal input off Push pull output COM6 output enable Alternative function PG1 output 1 0 bit P1 4 PGO AD4 COM7 Input mode AD4 converter input Normal input off Push pull output COM7output enable Alternative function PGO output When users use port 1 users must be care of the pull up resistance status Figure 9 5 Port 1 High Byte Control Register P1 CONH ELECTRONICS 53 8235 8235 Port 1 Control Register Low Byte P1CONL E5H Set 1 Bank 1 R W None ne n mu 0 ADO 21 1 AD1 P1 2 AD2 P1 3 AD3 7 6 bit P1 3 AD3 Input mode AD3 input Normal input off Push pull output Open drain output 5 4 bit P1 2 AD2 Input mode input Normal input off Push pull output Open drain output 3 2 bit P1 1 AD1 Input mode AD1 input Normal input off Push pull output Open drain output 1 0 bit P1 0 ADO Input mode ADO input Normal input off Push pull output Open drain output NOTE When users use port 1 users must be care of the pull up resistance status Figure 9 6 Port 1 Low Byte Control Register P1 CONL ELECTRONICS PORTS 9 9 PORTS Port 1 Pull up Control Register P1PUR E3H Set 1 Bank 1 R W ws 5 5 P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 0 P1PUR Bit Configuration Settings 0 Pull up disable 1 Pull up enable NOTES 1 Yo
65. input level must remain within the range to AVper usually AVper Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first conversion bit is always 1 2 AV pEr ELECTRONICS 15 3 A D CONVERTER 53 8235 8235 BLOCK DIAGRAM ADCON 6 4 Select one input pin of the assigned E L To ADINT 0 n Flag xm d Clock E Selector Analog Comparator Successive Approximation Logic ADCON O AD C Enable Input Pins ADO AD7 P1 0 P1 7 ADCON O A D Conversion enable 10 bit result is loaded into A D Conversion Data Register M u t i p x e r Conversion Result ADDATAH ADDATAL F8 F9H Set1 Bank 0 10 bit D A Converter Figure 15 4 A D Converter Functional Block Diagram Reference Voltage Input AVREF lt VDD Analog AD0 AD7 S3C8235B Input Pin Figure 15 5 Recommended A D Converter Circuit for Highest Absolute Accuracy 15 4 ELECTRONICS 53 8235 8235 Programming Tip Using the ADC Interrupt INITIAL MAIN ADC_INT ORG 0000h VECTOR OFAh ADC_INT ORG 0100h LD SYM 00h LD IMR 01000000b LD SPH 00000000b LD SPL 00000000b LD BTCON 10100011b SB1 LD P1CONH 01010101b LD P1CONL 01010101b SBO LD ADCON 00001001b LD R4 0 EI MAIN ROUTINE JR T MAIN OR ADCON 00000001b I
66. is arranged in a consistent format for improved readability and for quick reference The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Flag settings that may be affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELEGTRONIGS INSTRUCTION SET ADC Add with Carry ADC dst src Operation dst lt dst src 53 8235 8235 The source operand along with the carry flag setting is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction lets the carry value from the addition of low order operands be carried into the addition of high order operands Flags C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to O H Setif the
67. occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low order nibble occurred Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir src dst 3 6 04 R R 05 R IR opc dst src 3 6 06 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 08H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H ADD 01H 25H gt Register 01H 46H In the first example the destination working register R1 contains 12H and the source working register R2 contains The statement ADD R1 R2 adds to 12H leaving the value 15H in the register R1 ELECTRONICS 6 15 INSTRUCTION SET 53 8235 8235 AND Logical AND AND Operation Flags Format Examples dst src dst dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation causes a 1 bit to be stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffec
68. opposed to each interrupt source system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register ID R W Function Description Interrupt mask register IMR RW _ Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels 0 7 Interrupt priority register IPR R W Controls the relative processing priorities of the interrupt levels The seven levels of S3C8235B F8235B are organized into three groups B C Group A is IRQO and IRQ1 group is IRQ2 IRQ3 and IRQ4 and group is IRQ5 IRQ6 and IRQ7 Interrupt request register IRQ R This register contains a request pending bit for each interrupt level System mode register SYM RW _ This register enables disables fast interrupt processing dynamic global interrupt processing and external interface control An external memory interface is implemented in the S3C8235B F8235B microcontroller NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended ELECTRONICS 5 7 INTERRUPT STRUCTURE 53 8235 8235 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specif
69. pending bits one type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other must be cleared in the interrupt service routine by software Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C8235B F8235B interrupt structure the timer B underflow interrupt IRQ1 belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the S8C8235B F8235B interrupt structure pending conditions for IRQ3 IRQ4 IRQ5 and IRQ7 must be cleared in the interrupt service routine ELECTRONICS 5 15 INTERRUPT STRUCTURE 53 8235 82
70. relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 D2 r Ir Given R1 02H R2 and register 04H CPIJNE R1 R2 SKIP R2 04H PC jumps to SKIP location The working register R1 contains the value 02H the working register R2 the source pointer the value 03H and the general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 0000001 0B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJNE instruction must be within the allowed range of 127 to 128 ELECTRONICS 53 8235 8235 DA Decimal Adjust INSTRUCTION SET DA dst Operation dst DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destinatio
71. select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C8235B F8235B Register Pointer 1 D7H Set 1 Reset Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode 7 3 2 0 ELECTRONI S Register addressing only Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice C8H CFH Not used for the S3C8235B F8235B CONTROL REGISTERS 53 8235 8235 SPH stack Pointer High Byte D8H Set 1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addr
72. selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to OOB If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS 53 8235 8235 PORTS PORTS OVERVIEW The S3C8235B F8235B microcontroller has five bit programmable I O ports 4 The port and port 4 are 4 bit ports and the others are 8 bit ports This gives a total of 32 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required Table 9 1 gives you a general overview of the S3C8235B F8235B I O port functions Table 9 1 S3C8235B F8235B Port Configuration Overview Configuration Options 1 bit programmable I O port Schmitt trigger input or push pull output mode selected by software software assignable pull up P0 0 P0 7 can be used as inputs for external interrupts INTO INT7 with noise filter and interrupt control 1 bit programmable port Normal input AD input and output mode se
73. the basic timer counter value is cleared to Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to Immediately following the write operation the 0 value is automatically cleared to O 3 Thefxxis selected clock for system main OSC or sub OSC ELECTRONICS 4 CONTROL REGISTERS 53 8235 8235 System Clock Control Register D4H Set 1 Reset Value 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 5 Not used for the S3C8235B F8235B always logic zero 4 3 CPU Clock System Clock Selection Bits note O o SSS 16622 oade o O 2 0 Not used for the S3C8235B F8235B always logic zero NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 4 8 ELECTRONICS 53 8235 8235 CONTROL REGISTER FLAGS System Flags Register D5H Set 1 Bit Identifier 6 5s 4 2 o x x x x x x 0 0 Reset Value Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C Operation does not generate a carry or underflow condition Operation generates a carry out or underflow into high order bit 7 6 Zero Flag Z EN Operation re
74. value 06H and the source general register OOH the value 05H The statement LD RO0 00H 2 loads the bit two value of the 00H register into bit zero of the RO register leaving the value 07H in the register RO In the second example is the destination register The statement LD 00H 0 RO loads bit zero of the register RO to the specified bit bit zero of the destination register leaving 04H in the general register 00H ELECTRONICS 6 51 INSTRUCTION SET 53 8235 8235 LDC LDE Load Memory LDC dst src LDE dst src Operation dst lt src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes Irr or rr values an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src 1 2 10 C3 r Irr 2 src dst 2 10 D3 Irr r 3 dst src 3 12 E7 r XS rr 4 F X or 5 dst src 4 14 r XL rr 6 src dst 4 14 B7 XL rr r 7 DA 4 14 7 r DA 8 opc DA 4 14 B7 DA r 9 DA DA 4 14 7 r DA 10 DA 4 14 7 DA r NOTES 1 The source src or the working register pair rr for formats 5 and 6 cannot use the register pair 0 1 2 For the formats and 4 the destination XS rr and the source address XS rr are
75. vector address E4H A timer 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 match capture interrupt T1INT pending condition is also cleared by hardware when it has been serviced Interval Mode match The timer 1 module can generate an interrupt the timer 1 match interrupt T1INT belongs to interrupt level 2 and is assigned the separate vector address E4H In interval timer mode a match signal is generated and T1OUT is toggled when the counter value is identical to the value written to the T1 reference data register T1 DATA1H L The match signal generates a timer 1 match interrupt T1INT vector E4H and clears the counter Capture Mode In capture mode a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter value into the T1 data register TTDATA1H L for rising edge T1 DATA2H L for falling edge You can select rising or falling edges to trigger this operation Timer 1 also gives you capture input source the signal edge at the T1CAP pin You select the capture input by setting the value of the timer 1 capture input selection bit in the port 0 control register high POCONH set 1 bank 1 When POCONH 7 6 is 00 or 11 the T1CAP input is selected Both kinds of timer 1 interrupts T1OVF can be used in capture mode the timer 1 overflow interrupt is generated whenever a counter overflow occurs t
76. 0 S3E8230 EVA Chip 40 Pin Connector 40 Pin Connector SM1317A Figure 22 2 TB8235 Target Board Configuration ELECTRONICS 22 3 DEVELOPMENT TOOLS 53 8235 8235 Table 22 1 Power Selection Settings for TB8235 To User Vcc Settings Operating Mode To User Vcc The SMDS2 SMDS2 supplies or TB8235 Vcc to the target board on Voc evaluation chip and the target Vss gt system Vss gt The target system must have its own power supply To User The SMDS2 SMDS2 supplies e s Bases External Target Vcc only to the target board Off en Vcc System evaluation chip NOTE The following symbol in the To User Vcc Setting column indicates the electrical short off configuration Table 22 2 Power Selection Settings for EVA CHIP Operation For using SMDS2 only To User Vcc ettings Operating Mode The SMDS2 supplies 5V to EVA OHIE TB8235 target board 3V 5V 8235 S3E8230 So the target y System be operated by 5V The SMDS2 supplies to EUR TB8235 target board 5V 8235 x i S3E8230 So the target y System be operated by 3V NOTE For using SMDS2 Fix to side EVA CHIP settings 22 4 ELECTRONICS 53 8235 8235 DEVELOPMENT TOOLS SMDS2 SELECTION 5 8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a swit
77. 0001 10006 Non divided SB1 LD P1CONH 11111111b Enable PG output LD P4CON 11111111b Enable PG output SBO EI MAIN NOP NOP OR PGCON 200001 000b Triggering then pattern data are output NOP NOP JR T MAIN END ELECTRONICS 18 3 53 8235 8235 ELECTRICAL DATA OVERVIEW In this chapter S8C8235B electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode A D converter electrical characteristics ELEGTRONIGS ELECTRICAL DATA ELECTRICAL DATA S3C8235B F8235B Table 19 1 Absolute Maximum Ratings 25 Parameter faing Bmw pRRSRS LIC LOL vo RN 7728 Output current low lot One I O pin active Total pin current for port Table 19 2 D C Electrical Characteristics TA 25 C to 85 C 2 0 V to 5 5 V Operating voltage Vpp fopy 8 MHz Input high voltage All input pins except Vip Input low voltage All input pins except Vi NOTE PO are schmitt trigger ports 19 2 ELECTRONICS 53 8235 8235 ELECTRICAL DATA Table 19 2 D C Electrical Characteristics Continued TA 25
78. 2 S3C8235B F8235B Interrupt Structure 5 4 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8235B F8235B interrupt structure are stored in the vector address area of the first 256 bytes of the program memory ROM You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 16 384 16 Kbyte Internal Program Memory ROM Area Reset Address Interrupt Vector Address Area Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE 53 8235 8235 Table 5 1 Interrupt Vectors Vector Address Interrupt Source Request Reset Clear Decimal Hex Interrupt Priority in H W S W Value Value Level Level 2s Basictineroveriow Fer 7724 Key stobe ma Y xe p oem uem 0 7 external interrupt IRQ4 3 0 6 external interrupt 2 P0 5 external interrupt 1 P0 4 external interrupt 0 0 3 external interrupt IRQ3 3 P0 2 external interrupt 2 P0 1 external interrupt 1 0 0 external interrupt 0 Timer 1 overflow IRQ2 usnu eer EH B Timer B underflow Ju Timer A overflow
79. 2 2 2 2 2 2 2 2 4 ias Chapter 19 Electrical Data eI Ep Chapter 20 Mechanical Data II MEME T Ee LM MEM Chapter 21 S3F8235B FLASH MCU eremi erui einem t eR PI y yaa Operating Mode Chapter 22 Development Tools S3C8235B F8235B MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 53 8235 82 5 Block 1 3 1 2 S3C8235B F8235B Pin Assignment 64 1420 1 4 1 3 S3C8235B F8235B Pin Assignment 64 LQFP 1010 1 5 1 4 Pin Circuit Type 1 9 1 5 Pin Circuit Type C dae il dv dede l ed pde divans 1 9 1 6 Pin Circuit Type Ds2 P3 22 te rae erdt dc eden 1 9 1 7 Pin Circuit Type 0 4 0 0 0 7 except 4 1 9 1 8 Pin Circuit Type D 4 P0 4 certet Re 1 10 1 9 Pin Circuit Type F 19 P1 4 P1 7 1 10 1 10 Pin Circuit Type F 20 1 0 1 11 1 11 Pin Circuit Type H 1 11 1 12 Fin Circuit Lype HA n toS Ce eel ea ee adie 1 12 1 13 Pin Circuit Type H 14 P2 iiie
80. 22 53 8235 8235 032004 USER S MANUAL 53 8235 8235 8 Bit CMOS Microcontroller Revision 2 ELECTRONICS 53 8235 8235 8 5 MICROCONTROLLERS USER S MANUAL Revision 2 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C8235B F8235B 8 Bit CMOS Microcontrollers User s Manual Revision 2 Publication Number 22 S3 C8235B F8235B 032004 2004 Samsung Electronics Typical parameters can and do var
81. 2CONL 9 12 ELECTRONICS 53 8235 8235 PORTS 3 Port is an 4 bit I O port with individually configurable pins Port pins accessed directly by writing or reading the port data register at location E3H set 1 bank 0 0 can serve as inputs as push pull outputs or you can configure the following alternative functions TACK TAOUT TAPWM BUZ and KINO KINS inputs Port 3 Control Registers PSCON A reset clears the PSCON registers to configuring all pins to input mode You use control registers settings to select input or output mode and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module ELECTRONICS 9 13 PORTS 53 8235 8235 Port 3 Control Register PSCON E8H Set 1 Bank 1 R W we x P3 0 TAPWM TAOUT KINO P 3 1 TACK KIN1 P3 2 TACAP KIN2 P3 3 BUZ KIN3 7 6 bit P3 3 BUZ KIN3 Input mode External interrupt Watch timer buzzer output Push pull output Alternative mode KIN3 Key input Only falling edge interrupt When key strobe output is enable KSCON 7 1 port status is high impedence during interval and pulled up during strobe out 5 4 bit P3 2 TACAP KIN2 Input mode External interrupt TACAP input
82. 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the 3 byte instruction format conditional jump the condition code and the OPCODE are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H Secs JP C LABEL W gt LABEL_W 1000H PC 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement 900 replaces the contents of the PC with the contents of the register pair 00H and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET 53 8235 8235 JR Jump Relative JR Operation Flags Format Example 6 48 cc dst If cc is true PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See the list of condition codes at the beginning of this chapter The range of the relative address is 127 128 and the or
83. 35 INTERRUPT SOURCE POLLING SEQUENCE The dme interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The 1 2 3 4 CPU then initiates an interrupt machine cycle that completes the following processing sequence Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt v
84. 35 8235 IPR Interrupt Priority Register FFH Set 1 Bank 0 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Priority Control Bits for Interrupt Groups A B and C Group priority undefined 0 1 gt gt KEREN A gt B gt B gt A gt C gt gt gt gt 0 gt gt Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 E Lo 5 Interrupt Group C Priority Control Bit IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQ4 IRQ4 gt IRQ3 2 Interrupt Group B Priority Control Bit IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group A Priority Control Bit IRQO gt IRQ1 IRQ1 gt IRQO je 53 8235 8235 CONTROL REGISTER IRQ Interrupt Request Register DCH Set 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending Bit Key Strobe Interrupt Not pending EB Pending 6 Level 6 IRQ6 Request Pending Bit AD Interrupt Not pending je Pending 5 Level 5 IRQ5 Request Pending Bit Watch Timer Overflow Not pending EE Pending 4 Level 4 IRQ4 Request Pending Bit 0 4 0 7 External Interrupts Not pending Pending
85. 4 TBPWM 1 Data Bus NOTE In case of setting TBCON 5 4 at 10 the value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer B starts And then if a underflow occurs in the counter the value of the TBDATAH register is loaded with the value of the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded with the value of the 8 bit counter To output TBPWM as carrier wave you have to set POCONH 1 0 as 11 and also set REMCON O as 1 Figure 11 3 Timer B Functional Block Diagram ELECTRONICS 11 5 8 BIT TIMER A B S3C8235B F8235B Timer B Control Register TBCON EDH Set 1 Bank 0 R W we mE Timer B input clock selection bit Timer B output flip flop 00 fxx 1 01 fxx 2 10 fxx 4 11 fxx 8 Timer B interrupt time selection bit 00 Interrupt on TBDATAL underflow 01 Interrupt on TBDATAH underflow control bit 0 T FF is low TBDATAH gt high width 1 T FF is high TBDATAH gt low width Timer B mode selection bit 0 One shot mode 1 Repeating mode 10 Interrupt on TBDATAH and TBDATAL underflow Timer B start stop bit 11 Invaild setting 0 Stop timer B 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 4 Timer B Control Register TBCON ELECTRONICS 53 8235 8235 8 Timer
86. 5 8235 Port3 Interrupt Control Register E7H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 4 6 P3 3 KING Interrupt Enable Disable Selection Bits x Interrupt Disable Interrupt Enable falling edge Interrupt Enable rising edge 5 4 x Interrupt Disable Interrupt Enable falling edge 1 Interrupt Enable rising edge 3 2 P3 1 KIN1 Interrupt Enable Disable Selection Bits Interrupt Disable 1 o ro ENEE 1 0 P3 0 KINO Interrupt Enable Disable Selection Bits Interrupt Enable rising edge nterrupt Disable Interrupt Enable falling edge 1 Interrupt Enable rising edge NOTE When you want to use any pin in P3 as alternative mode to get a key input KINO 3 then you have to choose only falling edge interrupt 4 28 ELECTRONICS 53 8235 8235 CONTROL REGISTER P3PND pPort3 Interrupt Pending Register E8H Set 1 Bank 0 Reset Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the S308235B F8235B 3 P3 3 KIN3 Interrupt Pending Bit lo Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 2 P3 2 KIN2 Interrupt Pending Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 41 P3 1 KIN1 Interrupt Pending Bit
87. 53 8235 8235 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ4 Group C IRQ5 IRQ6 IRQ7 IPR Group C B21 B22 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B C A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows PR 5 controls the relative priorities of g
88. 6 RO RR6 bRR6 1 the contents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH LDEPI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 57 INSTRUCTION SET 53 8235 8235 LDW Load Word LDW dst src Operation dst src The contents of the source a word are loaded into the destination The contents of the source are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 C4 RR RR C5 RR IR opc dst src 4 8 C6 RR IML Examples Given R4 06H R5 1CH R6 05H R7 02H register 00H register 01H 02H register 02H 03H and register 03H OFH LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register OOH register 01H OFH register 02H register OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04H 01H gt Register 04H 03H register 05H OFH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH gt Register 02H OFH register 03H OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H and 03H into the destination word and 01H This leaves the value 03H in the general register 00H and the value OFH in the register 01H Other examples show how to use the LDW instruction with various addressing modes and formats 6 58
89. A All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts NOTE Do not use stop mode if you are using an external clock source because Xy input must be restricted internally to Vss to reduce current leakage Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock 1 16 because CLKCON 3 CLKCON 4 are cleared to 00B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C8235B F8235B interrupt structure that can be used to release Stop mode are External interrupts 0 0 0 7 INTO NT7 Please note the following conditions for Stop mode release lf you release Stop mode using an external interrupt the current value
90. B Features Program Memory 16K byte Flash ROM 16K byte mask ROM Operating Voltage V pp 2 0V to 5 5 V 2 0V to 5 5 V FLASH MCU Programming Vpp 5 V Vpp TEST 12 5 V D l Mode Programmability User Program multi time Programmed at the factory 21 4 ELECTRONICS 53 8235 8235 S3F8235B FLASH MCU OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the Vpp TEST of the S8F8235B the FlashROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 21 3 below Table 21 3 Operating Mode Selection Criteria Vpp TEST REG nMEM Address 15 0 OOH 1 Flash ROM read 12 5 V 0000H 0 Flash ROM program 125V o 0000H Flash ROM verify 12 5 V IEEE Flash ROM read protection NOTE 0 means Low level 1 means High level Table 21 4 D C Electrical Characteristics TA 25 C to 85 C Vpp 2 0 V to 5 5 V EN NENNEML WENN Input low voltage All input pins except Vi NOTE PO are schmitt trigger ports ELECTRONICS 21 5 S3F8235B FLASH MCU 53 8235 8235 Table 21 4 D C Electrical Characteristics Continued TA 25 C to 85 C Vpp 2 0 V to 5 5 V Output high voltage Output low voltage Input high leakage current Input low leakage current Output high leakage current Output low leakage current Oscillator
91. CONH POCONL Port 0 pins are configured individually by bit pair settings in two control registers located in set 1 bank 1 POCONL low byte E1H and POCONH high byte EOH When you select output mode a push pull circuit is configured In input mode three different selections are available Schmitt trigger input with interrupt generation on falling signal edges Schmitt trigger input with timer 1 capture signal Schmitt trigger input with interrupt generation on falling rising signal edges Port 0 Interrupt Enable and Pending Registers POINT POPND To process external interrupts at the port 0 pins two additional control registers are provided the port 0 interrupt enable register POINT E5H set 1 bank 0 and the port 0 interrupt pending register POPND E6H set 1 bank 0 The port 0 interrupt pending register POPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the POPND register at regular intervals When the interrupt enable bit of any port 0 pin is 1 a rising or falling signal edge at that pin will generate an interrupt request The corresponding POPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pe
92. Control Register High Byte E4H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 7 PG3 AD7 COMA Input mode 1 AD7 converter input Normal input off 1 0 Push pull output output enable Alternative function PG3 output 5 4 P1 6 PG2 AD6 COM5 o o mame 1 ADs Push pul ouput COMS ouput 3 2 P1 5 PG1 AD5 COM6 o o mumd o 1 ADS converter input Push pullouput COMB output erao Alternative function PG1 output 1 0 P1 4 PG0 AD4 COM7 Input mode ola AD4 converter input Normal input off Push pull output output enable Alternative function PGO output NOTE When users use Port 1 users must be care of the pull up resistance status 4 22 ELECTRONICS 53 8235 8235 CONTROL REGISTER P1CONL Port 1 Control Register Low Byte E5H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 AD3 o o mamm o i aoso noman 5 4 P1 2 AD2 o o mame Fo memuNomamud o Pro 3 2 P1 1 AD1 o o mamm Lo o aor moos woman o o eemo 1 0 P1 0 ADO o o mame o womuNomdmud a NOTE When users us
93. DD Vss XOUT XIN TEST XTIN XTOUT nRESET P0 5 T1OUT INT5 P0 6 T1CK INT6 P0 7 T1CAP INT7 64 3 P3 0 TAPWM TAOUT KINO P1 0 ADO 22 57 1 SEG23 P4 3 PG7 KSTR12 56 7 SEG22 P4 2 PG6 KSTR11 55 3 SEG21 P4 1 PG5 KSTR10 54 SEG20 P4 0 PG4 KSTR9 53 3 SEG19 P2 7 KSTR8 52 L3 SEG18 P2 6 KSTR7 S3C8235B S3F8235B 64 QFP 1420F P1 3 AD3 25 P1 2 AD2 24 COM7 P1 4 AD4 PG0 C 26 P1 1 AD1 23 COMO P1 5 AD5 PG1 CJ 27 COMB P1 6 AD6 PG2 28 COM4 P1 7 AD7 PG3 C 29 S3C8235B F8235B SEG17 P2 5 KSTR6 SEG16 P2 4 KSTR5 SEG15 P2 3 KSTR4 SEG14 P2 2 KSTR3 SEG13 P2 1 KSTR2 SEG12 P2 0 KSTR1 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEGA SEGS SEG2 SEG1 SEGO COMO Figure 1 2 S3C8235B F8235B Pin Assignment 64 QFP 1420F 1 4 PRODUCT OVERVIEW PIN ASSIGNMENT 53 8235 8235 48 1 SEG14 P2 2 KSTR3 47 SEG13 P2 1 KSTR2 46 SEG12 P2 0 KSTR1 vTHlSM cd SL OdS SH LSM v ed 9 945 41160 9 15 9 4 41995 EWOO LH1ISM 9 ed 8103S Od ZQV Z Ld FINOO 8H1SM Z ed 6L93S cO9d 9Q0V 9 Ld SIWNOO 6H 1SM vOd 0 Yd 0cO3S LOd SQV S Ld 9INOO OLH 1SM SOd F vd Le93S 0Sd r V r Ld ZINOO LLHISM 9O9d 2 vd ec 93S QV ld cLH1S9 29d vd cO3S cQv e ld LOTA cO lA 0QV 0 Ld COTA A3dHAV YOTA SSAV LLNI dVO LL Z Od 99 9 LNI MO L L 9 0d ONDM LOOV L INMdV L 0 d SLNI LYYOLL S Od m m LO LO o UN LL S 9 4 090 oo NTO Cy 4 NT1 C
94. Data High Byte Register TBDATAH EEH Set 1 Bank 0 R W Reset Value FFh Timer B Data Low Byte Register TBDATAL EFH Set 1 Bank 0 R W Reset Value FFh Figure 11 5 Timer B Data Registers TBDATAH L Carrier On Off Control Register REMCON FBH Set 1 Bank 0 R W Not used Carry on off 0 0 1 TBPWM Figure 11 6 Carrier on off Control Register REMCON ELECTRONICS 11 7 8 BIT TIMER A B PROGRAMMING TIP Using the Timer A INITIAL MAIN TAMC INT ORG 0000h VECTOR ODEh TAMC INT VECTOR OEOh TAOV INT ORG 0100h LD SYM 00h LD IMR 00000001b LD SPH 00000000b LD SPL 00000000b LD BTCON 10100011b LD TADATA 80h LD TACON 01001010b EI MAIN ROUTINE JR T MAIN Interrupt service routine Interrupt service routine IRET END 5 S3C8235B F8235B Disable Global interrupt SYM Enable IRQO interrupt Set stack area Disable watch dog Match interrupt enable 4 10 ms duration 8 MHz x tal ELECTRONICS 53 8235 8235 59 PROGRAMMING Using the Timer B INITIAL MAIN TBUN INT ORG 0000h VECTOR OE2h TBUN INT ORG 0100h LD SYM 00h LD IMR 200000010b LD SPH 00000000b LD SPL 00000000b LD BTCON 10100011b SB1 LD POCONH 0000001 1b SBO LD TBDATAH 80h LD TBDATAL 80h LD TBCON 11001110b EI MAIN ROUTINE JR T MAIN Interrupt service routine
95. E ADDRESS MODE RA ADDRESSING MODES In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE Displacement Current Instruction OPCODE Sample Instructions Program Memory Address Used Current PC Value Signed Displacement Value JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELEGTRONIGS ADDRESSING MODES 53 8238 8235 8235 IMMEDIATE MODE In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS 53 8235
96. ELECTRONICS 53 8235 8235 MULT Multiply Unsigned MULT Operation Flags Format Examples dst src dst dst x src INSTRUCTION SET The 8 bit destination operand the even numbered register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers C Set if the result is gt 255 cleared otherwise Set if the result is 0 cleared otherwise Set if MSB of the result is a 1 cleared otherwise Unaffected Unaffected Given MULT MULT MULT 2 5 V Cleared D H src 00H 02H 00H 01H 00H 30H dst gt Bytes Cycles Opcode Addr Mode Hex dst src 3 22 84 RR R 22 85 RR IR 22 86 RR Register OOH 20H register 01H register 02H register 06H Register 01H register 01H 20H register 02H 09H Register register 01H 0 Register 06H register 01H OOH In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register 00H of the register pair 00H 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET 53 8235 8235 NEXT next NEXT Operation Flags Format Exa
97. F8H R W R W 4 3 CONTROL REGISTERS Bit number s that is are appended to the register name for bit addressing 53 8235 8235 Name of individual bit or related bits Register location Register ID FLAGS System Flags Register Bit Identifier RESET Value Read Write Bit Addressing Mode 7 R Read only W Write only R W Read write Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit Register address in the internal Register name hexadecimal register file D5H Set 1 ee Be ee x x x x x x 0 0 R W R W R W R W R W R W R R W Register addressing modejonly Carry Flag C EN Operation does not generate a carry or borrow conditio Iz Operation generates carry out or borrow into high orderbit7 Zero Flag Z Operation result is a non zero value Operation result is zero Sign Flag S Operation generates positive number MSB 0 EN Operation generates negative number MSB 1 Description of the effect of specific bit settings nRESET value notation Not used x Undetermined value 0 2 Logic zero 1 Logic one Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format ELECTRONI S 53 8235 8235 CONTROL REGISTER ADCON A D Converter Control Register F7H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W A
98. Flash MCU ROM instead of a masked ROM The Flash ROM is accessed by serial data format The S3F8235B is fully compatible with the S3C8235B both in function and in pin configuration Because of its simple programming requirements the S3F8235B is ideal as an evaluation chip for the S8C8235B ELECTRONICS 21 1 S3F8235B FLASH MCU 53 8235 8235 64 1 P3 0 TAPWM TAOUT KINO 57 1 SEG23 P4 3 PG7 KSTR12 56 1 SEG22 P4 2 PG6 KSTR11 55 1 SEG21 P4 1 PG5 KSTR10 54 3 SEG20 P4 0 PG4 KSTR9 53 1 SEG19 P2 7 KSTR8 52 1 SEG18 P2 6 KSTR7 SEG17 P2 5 KSTR6 SEG16 P2 4 KSTR5 SEG15 P2 3 KSTR4 SEG14 P2 2 KSTR3 SEG13 P2 1 KSTR2 SEG12 P2 0 KSTR1 SEG11 P3 1 TACK KIN1 P3 2 TACAP KIN2 P3 3 BUZ KIN3 P0 0 INTO PO 1 INT1 P0 2 INT2 SDAT PO 3 INT3 SCLK PO 4 INT4 SEG10 VDD VDD S3F8235B SEG9 Vss Vss SEG8 XOUT SEG7 XIN 64 QFP 1420F SEGG VPP TEST SEG5 XTIN SEG4 XTOUT SEG3 nRESET nRESET SEG2 P0 5 T1OUT INT5 5 P0 6 T1CK INT6 SEGO P0 7 TACAP INT7 COMO 1 2 3 4 5 6 7 8 9 P1 3 AD3 25 P1 2 AD2 24 1 4 CH 26 P1 0 ADO 22 P1 1 AD1 23 COMO P1 5 AD5 PG1 CJ 27 COMB P1 6 AD6 PG2 28 COM4 P1 7 AD7 PG3 C 29 Figure 21 1 S3F8235B Pin Assignments 64 QFP 1420F 21 2 ELECTRONICS S3F8235B FLASH MCU 53 8235 8235 48 1 SEG14 P2 2 KSTR3 47 1 SEG13 P2 1 KSTR2 46 1 SEG12 P2 0 KSTR1 44 Fo SEG10 VYULSM Eed SLDAS LNOO 15 7 64 9 9045 41160 9H 1S S ed ZLO3S
99. H 02H If the general register OOH contains the value 42H and the register 42H the value 6FH the statement POPUD 02H 900H loads the contents of the register 42H into the destination register The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS 53 8235 8235 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst src IR lt IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 00H gt Register OOH 02H register 01H register 02H 70H If the general register 00H contains the value 01H and the register 01H the value 70H the statement POPUI 02H OOH loads the value 70H into the destination general register 02H The user stack pointer the register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET 53 8235 8235 PUSH Push to Stack PUSH Operation Flags Format Examples 6 66 src SP lt SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads th
100. Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 l ftwoor more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware 4 4 4 4 4 x 5 6 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing interrupt mask register IMR enables un masks or disables masks interrupt levels interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each in
101. N 2 to 11b the watch timer will function in high speed mode generating an interrupt every 3 91 ms High speed mode is useful for timing events for program debugging sequences The watch timer supplies the clock frequency for the LCD controller f Therefore if the watch timer is disabled the LCD controller does not operate Real Time and Watch Time Measurement Using a Main System or Subsystem Clock Source Clock Source Generation for LCD Controller Buzzer Output Frequency Generator Timing Tests in High Speed Mode ELECTRONICS 13 1 WATCH TIMER S3C8235B F8235B WATCH TIMER CONTROL REGISTER WTCON R W rm wrcon wrcows wrcows wrcova wrcona wrcow WICONA WICONO Reset vw v v j v j v v v Table 13 1 Watch Timer Control Register WTCON Set 1 Bank 0 F2H R W ves ms F2H WTCON 7 Co Select fxx 128 as the watch timer clock Select subsystem clock as watch timer clock WTCON 6 o Disable watch timer interrupt Enable watch timer interrupt WTCON 5 4 0 5 kHz buzzer BUZ signal output 1 kHz buzzer BUZ signal output 2 kHz buzzer BUZ signal output 4 kHz buzzer BUZ signal output Set watch timer interrupt to 1 05 WIGONG dul NOTE fxxis assumed to be 4 19 MHz o i ERE WTCON 3 2 o 0 0 1 Setwateh timer interrupt to O58 11090 Ooo 0 13 2 ELECTRONICS 53 8235 8235
102. NSTRUCTION SET 53 8235 8235 SB1 Select Bank 1 SB1 Operation Flags Format Example 6 76 BANK lt 1 The SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting the bank 1 register addressing in the set 1 area of the register file NOTE Bank 1 is not implemented in some KS88 series microcontrollers No flags are affected Bytes Cycles Opcode Hex opc 1 4 5F The statement SB1 sets FLAGS 0 to 1 selectin the bank 1 register addressing if bank 1 is implemented in the microcontrooler s internla register file ELECTRONICS 53 8235 8235 INSTRUCTION SET SBC subtract with Carry SBC Operation Flags Format Examples dst src dst dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands C Setif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occu
103. No effect 1 Clear the timer A counter when write When timer A counter clear bit 3 is set the 8 bit counter is cleared and it also is cleared automatically Figure 11 1 Timer A Control Register TACON ELECTRONICS 11 3 8 BIT TIMER A B S3C8235B F8235B BLOCK DIAGRAM TACON 2 TACON 7 6 Overflow Data Bus Pending TINTPND 1 fxx 1024 fxx 256 M 8 bit U p Counter TACON 3 fxx 64 x Read Only TACON S TACON 1 Match 8 bit ME TINTPND O Timer A Buffer Reg TACON 5 4 TACON 5 4 Timer A Data PG output signal Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Interrupt pending bits are located TINTPND register Figure 11 2 Timer A Functional Block Diagram 11 4 ELECTRONICS 53 8235 8235 8 8 OVERVIEW The S3C8235B F8235B micro controller has an 8 bit counter called timer B Timer B which can be used to generate the carrier frequency of a remote controller signal Timer B has two functions Asa normal interval timer generating a timer B interrupt at programmed time intervals supply a clock source to the 16 bit timer counter module timer 1 for generating the timer 1 overflow interrupt 7 PG output signal REMCON 0 TBCON 7 6 TBCON 2 TB Underflow TBUF To other block Timer 1 source clock P0
104. OH CFH After a reset register pointers RPO and automatically select two 8 byte register slices set 1 locations CFH as the active 16 byte working register block RPO COH C7H RP1 C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area d locations COH CFH LCD Data RPO Register Area RPI Figure 2 11 Common Working Register Area 2 14 ELECTRONICS 53 8235 8235 ADDRESS SPACES PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0C0H LD R2 40H R2 C2H the value in location 40H 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0C0H ADD R3 45H R3 C3H R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a
105. OL REGISTER P3CON Port 3 Control Register E8H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 1 0 ELECTRONI S Register addressing mode only P3 3 BUZ KIN3 Inputmode External Interrupt Watch timer Buzzer output KEREN Push pull output impedence during interval and pull up during strobe out 1 1 Alternative mode KIN3 input Only falling edge interrupt When key strobe output is enable KSCON 7 1 port status is high P3 2 TACAP KIN2 x Inputmode External Interrupt TACAP input Push pull output 1 1 Alternative mode KIN2 input Only falling edge interrupt When key strobe output is enable KSCON 7 1 port status is high impedence during interval and pull up during strobe out P3 1 TACK KIN1 x Inputmode External Interrupt TACK input ERER Push pull output Alternative mode KIN1 input Only falling edge interrupt When key strobe output is enable KSCON 7 1 port status is high impedence during interval and pull up during strobe out P3 0 TAPWM TAOUT KINO Inputmode External Interrupt 0 1 TAPWM or TAOUT output Push pull output 1 1 Alternative mode KINO input Only falling edge interrupt When key strobe output is enable KSCON 7 1 port status is high impedence during interval and pull up during strobe out 4 27 CONTROL REGISTERS 53 823
106. OLLER List of Tables continued Table Title Page Number Number 19 1 Absolute Maximum Ratings meme 19 2 19 2 D C Electrical 19 2 19 3 Electrical 19 5 19 4 Input Output nnn nnne 19 6 19 5 Data Retention Supply Voltage in Stop 19 6 19 6 A D Converter Electrical Characteristics 19 8 19 7 Main Oscillator 19 9 19 8 Main Oscillator Clock Stabilization Time ter mI 19 9 19 9 Sub Oscillator Frequency es n 19 10 19 10 Sub Oscillator Crystal Start Up Time 19 11 19 11 Analog Circuit Characteristics and Consumed Current 19 12 19 12 Characteristics of Voltage Level Detect Circuit 19 12 19 13 LVR Low Voltage Reset Circuit Characteristics 11 1 19 13 21 1 Descriptions of Pins Used to Read Write the 21 4 21 2 Comparison of S3F8235B and S3C8235B Features 21 4 21 3 Operating Mode Selection
107. OP Not used for the S3C8235B F8235B 0 System Clock Selection Bit Main oscillator select 1 Subsystem oscillator select ELECTRONICS 4 1 N CONTROL REGISTERS 53 8235 8235 POCONH Port control Register High Byte EOH Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 7 T1ICAP INT7 Input mode T1CAP input rising start interrupt on both edge 1 Input mode pull up interrupt on falling edge oo Push pull output Input mode T1CAP input falling start 5 4 P0 6 T1CK INT6 Input mode T1CK input interrupt on both edge EVES Input mode pull up T1CK input interrupt on falling edge 13 2 0 5 1 5 9 o 1 mme puupimemetontamgege o peeo 1 0 PO 4 TBPWM INTA Input mode interrupt on both edge fo 1 Input mode pull up interrupt on falling edge Push pull output Alternative function TBPWM 4 18 ELECTRONICS 53 8235 8235 CONTROL REGISTER POCONL Port 0 Control Register Low Byte E1H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 3 INT3 Input mode interrupt on rising edge Input mode pull up interrupt on falling edge oo Input mode interrupt
108. OR LDB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 5 POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 7 PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 ri x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x rl A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 lrr2 RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irrr2 RA r2 lrr1 IA1 IR1 IM Ir1 r2 E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 lrr2 12 R2 R1 R2 IR1 R1 IM r1 Irr2 xs F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 Irr1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs 6 10 ELECTRONICS 53 8235 8235 INSTRUCTION SET Table 6 5 OPCODE Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET 53 8235 8235 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare ope
109. PCODE fF 2 LT TTT ttt 4 bit address Register pointer provides three provides five low order bits high order bits IN MK Together they create an 8 bit register address Figure 2 12 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Register Instruction 01110 address 0110 1110 IEEE 76H Figure 2 13 4 Bit Working Register Addressing Example 2 16 ELECTRONICS 53 8235 8235 ADDRESS SPACES 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address
110. PU architecture The S3C8235B is a microcontroller with a 16K byte mask programmable ROM embedded The S3F8235B is a microcontroller with a 16K byte Flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C8235B F8235B by integrating the following peripheral modules with the powerful SAM8 core Five programmable ports including three 8 bit ports and two 4 bit ports for a total of 32 pins Eight bit programmable pins for external interrupts One 8 bit basic timer for oscillation stabilization and watchdog function system reset Two 8 bit timer counter and one 16 bit timer counter with selectable operating modes Watch timer for real time 8 channel A D converter The S3C8235B F8235B is versatile microcontroller for camera LCD and ADC application etc They are currently available in 64 pin LQFP and 64 pin QFP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM88RC CPU Memory 552 byte internal register file including LCD display RAM e 16K byte program memory Oscillation Sources e Crystal Ceramic or RC for main clock e Crystal for sub clock 32 768 kHz e CPU clock divider 1 1 1 2 1 8 1 16 Instruction Set e 78 instructions e Idle and Stop instructions Instruction Execution Time 500 5 at fx 8 MHz minimum main clock e 122 5 at fxt 32 768 kHz sub clock Interrupts e 8 interrupt lev
111. R1 OFH R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H register 02H SUB 01H 02H gt Register 01H 17H register 02H 03H SUB 01H 90H gt Register 01H 91H C S and V 1 SUB 01H 65H gt Register 01H OBCH C 5 1 In the first example if he working register R1 contains the value 12H and if the register R2 contains the value the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in the destination register R1 6 82 ELECTRONICS 53 8235 8235 INSTRUCTION SET SWAP swap Nibbles SWAP Operation Flags Format Examples dst dst 0 3 e dst 4 7 The contents of the lower four bits and the upper four bits of the destination operand are swapped 7 43 0 C Undefined Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R F1 IR Given Register register 02H and register 03H OA4H SWAP 00H gt Register OOH OE3H SWAP 02H gt Register 02H register 03H 4AH In the first example if the general register OOH contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and the upper four bits nibbles in the OOH register leaving the value OE3H
112. RET END ELECTRONICS A D CONVERTER Disable Global interrupt Enable IRQ6 interrupt Set stack area Disable Watch dog ADC input ADC input Enable ADC interrupt Hardware pending clear Resume conversion A D CONVERTER 53 8235 8235 S Programming Tip Using the ADC Main Routine ORG ORG INITIAL MAIN NOP OR NOP NOP NOP AD LOOP JP LD LD NOP NOP NOP JR END 0000h 0100h SYM 00h IMR 01000000b SPH 00000000b SPL 00000000b BTCON 10100011b P1CONH 01010101b P1CONL 01010101b ADCON 00000000b R4 0 ADCON 00000001b ADINT 00000001b Z AD_LOOP ADINT 0 RO ADDATAH T MAIN Disable Global interrupt Enable IRQ6 interrupt Set stack area Disable Watch dog ADC input ADC input Disable ADC interrupt Conversion start Check EOC Pending clear by software ELECTRONI S 53 8235 8235 VOLTAGE BOOSTER VOLTAGE BOOSTER OVERVIEW This voltage booster works for the power control of LCD generates 4 x Vp Vi 3 x Vi Vicgi 2x ci 1 x Vn Vic4 This voltage booster allows low voltage operation of LCD display with high quality This voltage booster circuit provides constant LCD contrast level even though battery power supply was lowered This voltage booster include voltage regulator and voltage charge pump circuit FUNCTION DESCRIPTION The voltage booster has built for driving the LCD The voltage booster provides the capability of
113. RONICS 2 1 ADDRESS SPACES 53 8235 8235 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C8235B F8235B has 16 Kbytes of internal mask programmable program memory The program memory address range is therefore OH 3FFFH see Figure 2 1 The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal 16 384 16 KByte Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS 53 8235 8235 ADDRESS SPACES SMART OPTION Smart Option 1 ROM Address 003FH Not used Smart Option 1 ROM Address 003EH we LVR level selection bit 00 3 7V 01 2 8V 1x22 3V LVR enable bit 0 Enable LVR 1 Disable LVR Figure 2 2 Smart Option Smart option is the ROM option for start condition of the chip The ROM address used by smart option is from to 003FH The S3C8235B F8235B only use 003EH The default value of ROM is FFH LVR disable ELECTRONICS 2 3 ADDRESS SPACES 53 8235 8235 REGISTER ARCHITECTURE In the S3C8235B F8235B implementation the upper 64 byte area of register files
114. S register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 16 High Address Top of stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 16 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SP0 is stored in the SPL register D9H After a reset the SP value is undetermined Because only internal memory space is implemented in the S3C8235B F8235B the SPL must be initialized to an 8 bit value in the range 00H FFH The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose da
115. TR Bit Reset BITR Operation Flags Format Example 6 20 dst b dst b 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Given R1 07H BITR R1 1 R1 05H If the value of the working register R1 is 07H 000001 11B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS 53 8235 8235 INSTRUCTION SET BITS Bit set BITS Operation Flags Format Example dst b dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R1 3 gt R1 OFH If the working register R1 contains the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001 111B ELECTRONICS 6 21 INSTRUCTION SET 53 8235 8235
116. The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H 80H 81H ADC 80H 82H 80H lt 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H 80H 84H C ADC 80H 85H 80H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles ELECTRONICS 2 11 ADDRESS SPACES 53 8235 8235 REGISTER ADDRESSING The S3C series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and th
117. The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011 Selects or Address These address bits indicate 8 bit oo 8 bit logical working register address addressing Register pointer Three low order bits provides five high order bits NENNEN 8 bit physical address Figure 2 14 8 Bit Working Register Addressing ELECTRONICS 2 17 ADDRESS SPACES 53 8235 8235 Selects RP1 R11 8 bit address Register 1100 10 11 form instruction 10101 address LD R11 R2 OABH Specifies working register addressing Figure 2 15 8 Bit Working Register Addressing Example 2 18 ELECTRONICS 53 8235 8235 ADDRESS SPACES SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S3C8235B architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAG
118. able watch timer 0 Watch Timer Interrupt Pending Bit Interrupt is not pending Clear pending bit when write Interrupt is pending 4 42 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQO IRQ also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C8235B F8235B interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Int
119. al assembly It runs on the MS DOS operating system It produces the relocatable object code only so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code file by HEX2ROM the value FF is filled into the unused ROM area up to the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all S8C8 series microcontrollers All required target system cables and adapters are included with the device specific target board ELECTRONICS 22 1 DEVELOPMENT TOOLS 53 8235 8235 or Compatible RS 232C SMDS2 gt PROM OTP Writer Unit Target Application System gt RAM Break Display Unit lt lt Trace Timer Unit TB8235 lt gt SAMB8 Base Unit Target Board Eva gt Power Supply Unit Chip Figure 22 1 SMDS Product Configuration SMDS2 22 2 ELECTRONICS 53 8235 8235 DEVELOPMENT TOOLS TB8235 TARGET BOARD The TB8235 target board is used for the S3C8325B F8235B microcontroller It is supported with the SMDS2 Smart Kit and TB8235 To User Vcc Off On 1 5V 3V 74HC11 Stop Idle qt RESET 4050 4050 o o o e 16
120. al value of the carry flag replaces bit zero C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 11 IR Given Register OAAH register 01H 02H and register 02H 17H C 0 RLC 00H gt Register OOH 54H C 1 RLC 01H gt Register 01H 02H register 02H 2EH C In the first example if the general register has the value 10101010B the statement RLC OOH rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of the register 00H leaving the value 55H 01010101B The MSB of the register resets the carry flag to 1 and sets the overflow flag ELECTRONICS 53 8235 8235 INSTRUCTION SET RR Rotate Right RR Operation Flags Format Examples dst C lt dst 0 dst 7 lt dst 0 dst n dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Set if the bit rotate
121. ange 19 14 20 1 64 QFP 1420F Package 20 2 20 2 64 LQFP 1010 Package Dimensions 20 3 21 1 SSF8235B Pin Assignments 64 QFP 1420F 21 2 21 2 SSF8235B Pin Assignments 64 LQFP 1010 21 3 21 3 Operating Voltage 21 9 22 1 SMDS Product Configuration 5 052 22 2 22 2 TB8235 Target Board Configuration 22 3 22 3 40 Pin Connectors J101 J102 for TB8235 a 22 6 224 S3C8235B F8235B Probe Adapter Cables for 64 QFP 22 6 S3C8235B F8235B MICROCONTROLLER xv List of Tables Table Title Page Number Number 1 1 S3C8235B F8235B Pin Descriptions 1 6 2 1 S3C8235B F8235B Register Type 2 3 4 1 Registers wasa 4 1 4 2 Set 1 Bank 0 Registers 4 2 4 3 Set 1 Bank T Registers ic Les A ee 4 3 5 1 Interrupt eor cm 5 6 5 2 Interrupt Control Register Overview 5 7 5 3 Interrupt Source Control and Data
122. ans that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3C8235B F8235B Set 1 Register Values after RESET Stack pointer high byte Stack pointer low byte Instruction pointer high byte Instruction pointer low byte 8 2 ELECTRONICS 53 8235 8235 RESET POWER DOWN Table 8 2 S3C8235B F8235B Set 1 Bank 0 Register Values after RESET ITI 224 s N m _ 2 227 m rm O 5 m E 231 232 ITI e IN S S w Q S m rmi rm Oo Z m rm gt Timer A data register TADATA 23 Timer B control register TBCON 237 m m rm TI rm BB Basic ner oaa regse eront ros o o o o o o o s rw Tx xx x 41 42 4 IS IS Go G B K 4 CH 1 TI Q N T 2 2 2 4 O m B I mimim m lolo o IJIJ I I 7 Timer B data register low byte TBDATAL 24 24 Timer B data register high byte TBDATAH i ister gt do TII ELECTRONICS 8 3 RESET and POWER DOWN 53 8235 8235 Table 8 3 S3C8235B F8235B Set 1 Bank 1 Register Values after RESET m Register Name Add Port 0 control High register 224 Port 0 co
123. any time during normal operation by writing a 1 to TACON 3 The timer A overflow interrupt TAOVF is interrupt level IRQO and has the vector address EOH When a timer overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware or must be cleared by software To enable the timer A match capture interrupt IRQO vector DEH you must write TACON 1 to 1 To detect a match capture interrupt pending condition the application program polls TINTPND 0 When a 1 is detected a timer A match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing to the timer 0 match capture interrupt pending bit TINTPND O Timer A Control Register EAH Set 1 Bank 0 R W Reset 00H Timer A input clock selection bit M used 00 fxx 1024 01 fxx 256 Timer A match capture interrupt 10 2 fxx 64 enable bit 11 External clock TACK 0 Disable interrupt Enable interrrupt Timer A operating mode selection bit 00 Interval mode TAOUT mode Timer A overflow interrupt enable bit 01 Capture mode capture on rising edge 0 Disable overflow interrupt counter running OVF can occur 1 Enable overflow interrrupt 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mode OVF interrupt and match interrupt can occur Timer A counter clear bit 0
124. atement BOR 01H 2 R1 logically ORs bit two of the register 01H destination with bit zero of R1 source This leaves the value 07H in the register 01H ELECTRONICS 53 8235 8235 INSTRUCTION SET BTJRF Bit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is a 0 then PC PC dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter Otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If the working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is O the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET 53 8235 8235 BTJ RT Bit Test Jump Relative on True BTJRT Operation Flags Format Example 6 24
125. ation 0105H 01H 0104H LDE 3 01 H RR2 RO 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC R0 4 1000H RR2 RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H LDE R0 1000H RR2 RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H LDC R0 1104H RO lt contents of program memory location 1104H RO 88H LDE R0 1104H RO e contents of external data memory location 1104H RO 98H LDC 1105 0 11H contents of RO is loaded into program memory location 1105H 1105H 11H LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H 11H NOTE The LDC and the LDE instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET 53 8235 8235 LDCD LDED Load Memory and Decrement LDCD LDED Operation Flags Format Examples NOTE 6 54 dst src dst src dst src m lt 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD refers to program memory and LDED refers to ex
126. ation routine which follows a reset operation Although you can manipulate 5 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W 7 5 2 Not used Global interrupt enable bit 0 Disable global interrupt processing 1 Enable global interrupt processing Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W ve RQ0 IRQ2 IRQ3 IRQ4 IRQ6 IRQ5 IRQ7 Interrupt level e
127. both one byte 3 Forthe formats 5 and 6 the destination XL rr and the source address XL rr are both two bytes 4 The DA andthe r source values for the formats 7 and 8 are used to address program memory The second set of values used in the formats 9 and 10 are used to address data memory 5 LDEinstruction can be used to read write the data of 64 Kbyte data memory 6 52 ELECTRONICS 53 8235 8235 LDC LDE Load Memory LDC LDE Continued INSTRUCTION SET Examples Given RO 11H R1 R2 01H R3 04H Program memory locations 0103H 0104H 1A 0105H 6DH and 1104H 88H 0103 5FH 0104H External data memory locations 2AH 0105H 7DH and 1104H 98H LDC RO RR2 RO lt contents of program memory location 0104H RO 1AH R2 01H R3 04H LDE RO RR2 RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H LDC RR2 RO 11H contents of RO is loaded into program memory location 0104H RR2 RO R2 no change LDE RR2 RO 11H contents of RO is loaded into external data memory location 0104H RR2 RO R2 no change LDC RO 01H RR2 RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H LDE RO 01H RR2 RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H LDC 01H RR2 RO 11H contents of RO is loaded into program memory loc
128. c timer is enabled Ports 0 4 are set to input mode Peripheral control and data registers are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE RESET OPERATION In normal masked ROM mode the Test pin is tied to Vac A reset enables access to the 16 Kbyte on chip ROM The external interface is not automatically configured NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET and POWER DOWN 53 8235 8235 HARDWARE RESET VALUES Table 8 1 8 2 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values A 1 or a 0 shows the reset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset Adash me
129. cation addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 50 R 51 IR Given Register 01H register 01H 1BH SPH 0D8H SPL 0D9H OFBH and stack register OFBH 55H POP 00H gt Register OOH 55H SP OOFCH POP 00H gt Register OOH 01H register 01H 55H SP OOFCH In the first example the general register OOH contains the value 01H The statement POP OOH loads the contents of the location OOFBH 55H into the destination register and then increments the stack pointer by one The register 00H then contains the value 55H and the SP points to the location OOFCH ELECTRONICS 6 63 INSTRUCTION SET 53 8235 8235 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example 6 64 dst src dst src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register OOH 41H register 02H 6FH register 42H 6F
130. ce First of all you have to change the PGDATA into what you want to output And then you have to set the PGCON to enable the pattern generation module and select the triggering signal From now bits of PGDATA are on the P1 4 P1 7 and P4 0 P4 3 whenever the selected triggering signal happens Data write to PGDATA Triggering signal selection PGCON 3 0 Triggering signal generation Data output through P1 4 P1 7 P4 0 P4 3 Figure 18 1 Pattern Generation Flow ELECTRONICS 18 1 PATTERN GENERATION MODULE 18 2 Pattern Generation Module Control Register F5H Set 1 Bank 0 R W PG operation mode selection bit Timer A match signal triggering Timer B underflow signal triggering Timer 1 match signal triggering S W triggering mode Bit2 0 PG operation disable 1 PG operation enable Bit3 0 No effect 1 S W trigger start auto clear Figure 18 2 PG Control Register PGCON PGDATA Set 1 Bank 0 F6H PG Buffer Timer A match signal Timer B underflow signal Timer 1 match signal Figure 18 3 Pattern Generation Circuit Diagram 53 8235 8235 ELECTRONICS S3C8235B F8235B PATTERN GENERATION MODULE Programming Tip Using the Pattern Generation ORG 0000h ORG 0100h INITIAL SB0 LD SYM 00h Disable Global interrupt gt SYM LD SPH 00h High byte of stack pointer SPH LD SPL 00h Low byte of stack pointer SPL LD BTCON 10100011b Disable Watch dog LD CLKCON
131. ch as follows Otherwise the program memory writing function is not available Table 22 3 The SMDS2 Tool Selection Setting SMDS2 Og SMDS2 RW RW Target System SMDS2 IDLE LED The Yellow LED is ON when the evaluation chip S3E8230 is in idle mode STOP LED The Red LED is ON when the evaluation chip S3E8230 is in stop mode ELECTRONICS 22 5 DEVELOPMENT TOOLS 53 8235 8235 P3 1 TACK KS1 P3 2 TACAP KS2 COMO SEGO P3 3 BUZ KS3 PO O INTO SEG1 SEG2 PO 1 INT1 PO 2 INT2 SEG3 SEG4 SDAT P0 3 INT3 SCLK P0 4 TBPWM INT4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 P2 0 SEG13 P2 1 SEG14 P2 2 P0 6 T1CK INT6 SEG15 P2 3 SEG16 P2 4 AVss SEG17 P2 5 SEG18 P2 6 P1 0 ADO SEG19 P2 7 SEG20 P4 0 PG4 P1 2 AD2 SEG21 P4 1 PG5 SEG22 P4 2 PG6 COM7 P1 4 AD4 PGO SEG23 P4 3 PG7 VLC1 COM6 P1 5 AD5 PG1 COM5 P1 6 AD6 PG2 VLC2 VLC3 COM4 P1 7 AD7 PG3 COM3 VLC4 CA COM2 COM1 CB P3 0 TAPWM N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C N C P0 5 TTOUT INT5 P0 7 T1CAP INT7 AVREF P1 1 AD1 P1 3 AD3 40 D9UUOD 0 40 D9UUOD Figure 22 3 40 Connectors J101 J102 for TB8235 Target Board Target System J101 J102 J102 J101 2 Part Name AP64SD C Order Cods SM6532 40199UUO U d Or A I 5 g 79 O o 3 5 a 9 Figure 22 4 53C8235B F8235B Probe Adapter Cables for 64 QFP Package 22 6 ELECTRONICS
132. d by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F 2 The statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET 53 8235 8235 SU B subtract SUB dst src Operation dst lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Flags C Setif a borrow occurred cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 6 23 r Ir src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 register 01H 21H register 02H register OAH SUB R1 R2 gt
133. d from the least significant bit position bit zero was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R E1 IR Given Register register 01H 02H and register 02H 17H RR 00H gt Register 00H 98H C 1 RR 01H gt Register 01H 02H register 02 8BH C 1 In the first example if the general register 00H contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and the overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET 53 8235 8235 RRC Rotate Right through Carry RRC Operation Flags Format Examples 6 74 dst dst 7 C C lt dst 0 dst n dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag and the initial value of the carry flag replaces bit 7 MSB C Set if the bit rotated from the least significant bi
134. d with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Examples Given RO 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H OR RO R1 gt RO SFH R1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register register 01H 37H OR 01H 00H gt Register OOH 08H register 01H OBFH OR 00H 02H gt Register OOH OAH In the first example if the working register RO contains the value 15H and the register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result in the destination register RO Other examples show the use of the logical OR instruction with various addressing modes and formats 6 62 ELECTRONICS 53 8235 8235 INSTRUCTION SET POP Pop from Stack POP Operation Flags Format Examples dst dst SP SP SP 1 The contents of the lo
135. ddress is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE 53 8235 8235 Sources Reset Clear Basic timer overflow H W Timer A match capture H W S W Timer A overflow H W S W Timer B underflow H W Timer 1 match capture H W S W Timer 1 overflow H W S W P0 0 external interrupt S W P0 1 external interrupt S W P0 2 external interrupt S W P0 3 external interrupt S W P0 4 external interrupt S W P0 5 external interrupt S W P0 6 external interrupt S W P0 7 external interrupt S W IRQ5 Watch timer overflow S W IRQ6 nn AD interrupt H W S W IRQ7 Key strobe interrupt S W NOTES 1 Within a given interrupt level the lower vector address has high priority For example DEH has higher priority than EOH within the level IRQO the priorities within each level are set at the factory 2 External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5
136. ddressing Mode Register addressing mode only 7 Not used for the S3C8235B F8235B Always logic zero 6 4 A D Input Pin Selection Bits 3 ADC Interrupt Enable Bit interrupt disable ADC interrupt enable 2 1 Clock Source Selection Bits oop 77 oppe LL 0 Start Disable Bit Disable operation Start operation ELECTRONICS 4 5 CONTROL REGISTERS 53 8235 8235 ADINT A D Conversion Interrupt Register FAH Set 1 Bank 0 Reset Value 0 Read Write R W Addressing Mode Register addressing mode only 7 1 Not used for the S3C8235B F8235B 0 Interrupt Pending Bits Interrupt is not pending When reading Clear pending bit When writing Interrupt is pending When reading 4 6 ELECTRONI S 53 8235 8235 CONTROL REGISTER BTCON Basic Timer Control Register D3H Set 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset E 0 1 0 Disable watchdog timer function Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits fo fina 4 Basic Timer Counter Clear Bit 1 No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for all Timers 2 EN No effect Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1
137. directly connecting an LCD panel to the MCU without having to separately generate and supply the higher voltages required by the LCD panel The voltage booster operates on an internally generated and regulated LCD system voltage and generates a doubled a tripled and a four fold voltage levels to supply the LCD drive circuit External capacitor are required to complete the power supply circuits The Vdd power line is regulated to get the Vi c4 Vp level which become a base level for voltage boosting Then doubled a tripled and a four fold voltage will be made by capacitor charge and pump circuit NOTE The V should be less than or equal to Vpp when CAP bias mode is used to 1 8 duty ELECTRONICS 16 1 VOLTAGE BOOSTER S3C8235B F8235B BLOCK DIAGRAM Voltage Regulator Figure 16 1 Voltage Booster Block Diagram COMO COM7 SEGO SEG 23 Booster Voltage Regulator 0 90 1 25V In case of 1 4 bias and static mode pins must be connected as above but in case of 1 3 bias mode VLC4 pin must be opened Figure 16 2 Pin Connection Example 16 2 ELECTRONICS 53 8235 8235 VOLTAGE LEVEL DETECTOR VOLTAGE LEVEL DETECTOR OVERVIEW The S3C8235B F8235B micro controller has a built in VLD Voltage Level Detector circuit which allows detection of power voltage drop through software Turning the VLD operation on and off can be controlled by software Because the IC consumes a large amount of current during VLD operati
138. dividual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET 53 8235 8235 Table 6 1 Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst src Load LDB dst src Load bit LDE dst src Load external data memory LDC dst src Load program memory LDED dst src Load external data memory and decrement LDCD dst src Load program memory and decrement LDEI dst src Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POPUI dst src Pop user stack incrementing PUSH SIC Push to stack PUSHUD dst src P
139. dst src opc 2 14 F2 Given RO 77H R6 30H and R7 00H LDCPD RR6 R0 RR6 lt RR6 1 77H the contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH LDEPD RR6 RO RR6 RR6 1 77H the contents of RO is loaded into external data memory location 2FFFH 3000H LDEPD instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 53 8235 8235 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples NOTE dst src dst src rm rr 1 dst src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Ir an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 RO RR6 bRR6 1 the contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H LDEPI RR
140. e Main System Sub system Oscillator Oscillator Circuit Circuit Watch Timer LCD Controller Selector 1 OSCCON 2 STOP OSC 1 1 1 4096 Basic Timer inst Timer Counters Watch Timer Frequency LCD Controller Dividing Voltage Booster A D Converter VLD 14 12 1 8 1 16 System Clock CPU Clock P IDLE Instruction Figure 7 3 System Clock Circuit Diagram ELECTRONICS 7 8 CLOCK CIRCUIT 53 8235 8235 SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in the bank 0 of set 1 address It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to 8 bo72 or 1 System Clock Control Register CLKCON D4H Set 1 R W 5 s Not used must keep always 0 Not used must keep always 0 Divide by selection bits for CPU clock frequency 00 fxx 16 01 fxx 8 10 fxx 2 11 fxx 1 non divided Figure 7 7 System Clock Control Register CLKCON 7 4 ELECTRONI S 53 8235 8235 CLOCK CIRCUIT OSCILLATOR CONTROL REGISTER OSCCON The oscillator control register OSCCON is located in set 1 bank 0 at address F3H It is read write addressable and has the following functions
141. e C Output Disable Ext INT Data Figure 1 8 Pin Circuit Type D 4 0 4 Pull up Enable Data Circuit Output Disable yo LCD Out Enable COM Output Disable ADC In EN Data ADC In Figure 1 9 Pin Circuit Type F 19 P1 4 P1 7 S3C8235B F8235B ELECTRONI S 53 8235 8235 PRODUCT OVERVIEW Open Drain Enable Pull up Enable Data yo ADC In Enable Data ADC In Beg Figure 1 10 Pin Circuit Type F 20 P1 0 P1 3 SEG COM Figure 1 11 Pin Circuit Type H SEG COM ELECTRONICS 1 11 PRODUCT OVERVIEW COM SEG Output Disable Figure 1 12 Pin Circuit Type H 4 Open Drain EN Pull up Enable Data o lO LCD Out EN SEG Disable Figure 1 13 Pin Circuit Type H 14 P2 S3C8235B F8235B ELECTRONICS 53 8235 8235 PRODUCT OVERVIEW Pull up Enable Data Circuit o VO Output Disable Type C LCD Out Enable Yn SEG a Marec Disable Data Figure 1 14 Pin Circuit Type H 15 P4 ELECTRONICS 1 13 53 8235 8235 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C8235B F8235B microcontroller has two types of address space Internal program memory ROM Internal data memory RAM A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3C8235B F8235B has an internal 16K byte mask programmable ROM and 552 byte RAM ELECT
142. e Ee SRI uya eee etc eee 2 redde reae retta E deett oria Suri on Compare Increment and Jump on Compare Increment and Jump on Non Equal see Decimal ave hii rep der Rete Ue ee ER dene Up E eet VEN RH eee 2 e tte a tbe tes der oL aL RE kak u Tee REL cta Lu Rx us uy BRE Decrement ee EG eee ERE ee i ERE EP Ne Ret PG MR dis Disable Interr pts cu cte repro et eub o eal ate Divide Brsigned ior err o erre DRE OBERE B RR ERE Decrement and Jump if 2 0 nnne INCREMENT Iricremernt MOrd c ua notet toe cete S3C8235B F8235B MICROCONTROLLER Page umber xxi List of Instruction Descriptions Continued Instruction Full Register Name Page Mnemonic Number LDC LDE Load Memory uapa t ace E e eee iue Inv e hi od a dee 6 52 LDCD LDED Load Memory and 6 54 LDCI LDEI Load Memory and Increment hene 6 55 LDCPD LDEPD Load Memory with Pre Decrement
143. e Idle mode only CPU clock stops Stop mode system clock and CPU stop Operating Temperature Range e 25 C to 85 C Operating Voltage Range e 2 0 V to 5 5 V at 4 MHz main clock e 2 7 V to 5 5 V at 8 MHz main clock e 2 0 V to 5 5 V at 32 768 kHz sub clock Package Type e 64 QFP 1420F 64 LQFP 1010 Smart Option e Low Voltage Reset LVR level and enable disable are at your hardwired option ROM address ELECTRONICS 53 8235 8235 PRODUCT OVERVIEW BLOCK DIAGRAM P0 0 P0 7 P1 0 P1 7 INTO INT7 AVREF gt ADO AD7 XIN XTIN Xour XTouT OSC nRESET nRESET gt I O Port and Interrupt Control 8 Bit Basic Timer E P3 0 TAPWM 8 Bit P3 1 TACK Timer P3 2 TACAP Counter A P3 0 P3 3 SAM88RC CPU P4 0 P4 3 gt gt gt gt lt gt gt i lt gt gt P0 7 T1CAP gt 16 Bit 4 VLC1 VLCA PO 6 T1CK Timer Counter LCD 0 P0 5 T1OUT i a Driver SEGO SEG 11 SEG12 SEG23 8 Bit 4 16k byte 552 byte P0 4 TBPWM Timer Key strobe 2 LVR Pattern Smart Option Generation Voltage CB P1 4 P1 7 P4 0 P4 3 P3 3 BUZ Watch Timer Booster d VLC1 VLC4 Figure 1 1 S3C8235B F8235B Block Diagram ELECTRONICS 1 3 PRODUCT OVERVIEW PIN ASSIGNMENT P3 1 TACK KIN1 P3 2 TACAP KIN2 P3 3 BUZ KIN3 P0 0 INTO PO 1 INT1 PO 2 INT2 P0 3 INT3 P0 4 TBPWM INT4 V
144. e Port 1 users must be care of the pull up resistance status ELECTRONICS 4 23 CONTROL REGISTERS 53 8235 8235 P1PUR Por Pull up Control Register Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P1 7 Pull up Resistor Enable Pull up disable je Pull up enable 6 P1 6 Pull up Resistor Enable Bit Pull up disable Pull up enable je 5 P1 5 Pull up Resistor Enable Bit Pull up disable je Pull up enable 4 P1 4 Pull up Resistor Enable Bit Pull up disable Pull up enable Je 3 P1 3 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 2 P1 2 Pull up Resistor Enable Bit Pull up disable Pull up enable P1 1 Pull up Resistor Enable Pull up disable k Pull up enable 0 P1 0 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable NOTES 1 Youcan enable Port 1 pull up resistor when Port 1 is configured only as input mode or open drain output mode 2 The pull up resistor of Port 1 is disable when LMOD 4 1 4 24 ELECTRONICS 53 8235 8235 CONTROL REGISTER P2CONH Port 2 Control Register High Byte E6H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 SEG19 KSTR8 o o mamm 1 0 Push pull output SEG19
145. e address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space LSB n Even address Rn 1 Figure 2 9 16 Bit Register Pair 2 12 ELECTRONICS 53 8235 8235 ADDRESS SPACES Purpose Registers General Purpose Register I Benk Bani 0 Bank 1 Control Registers IE E Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area NOTE In the S3C8235B F8235B microcontroller pages 0 2 are implemented Pages 0 2 contain all of the addressable registers in the internal register file Page 0 Page 0 Register Addressing Only All Indirect Register All Addressing Indexed Addressing Modes Addressing Modes Modes Can be Pointed by Register Pointer Can be Pointed to By register Pointer Figure 2 10 Register File Addressing ELECTRONICS 2 13 ADDRESS SPACES 53 8235 8235 COMMON WORKING REGISTER AREA C
146. e and push pull output Pull up resistors are assignable by software Alternately configurable to output pins for LCD COM and I PG output I and Key strobe P3 2 mode The port 3 pins have high current drive P3 3 capability configurable to output pins for LCD SEG P3 0 I O port with bit programmable pins 64 KINO TAPWM Configurable to schmitt trigger input mode P3 1 key strobe input mode or push pull output 1 2 2 3 KIN3 BUZ 1 6 ELECTRONICS 53 8235 8235 PRODUCT OVERVIEW Table 1 1 S3C8235B F8235B Pin Descriptions Continued Pin Pin Circuit Shared Type Description Type Functions P4 0 4 3 I O port with bit programmable pins H 15 54 57 SEG20 SEG23 Configurable to normal input mode and push KSTR9 KSTR12 pull output mode pull up resistors are PG4 PG7 assignable by software Alternately configurable to output pins for LCD SEG key strobe and PG output INTO INT3 External interrupts input with noise filter D 4 4 7 P0 0 PO 3 INT5 INT7 17 19 0 5 0 7 INT4 External interrupts input with noise filter pa 8 Pos ADO AD3 A D converter analog input channels F 20 22 25 P1 0 P1 3 F 19 26 29 P1 4 P1 7 A D converter reference voltage rer A D converter Ground sedi Capacitor terminal for voltage booster E a a j COMO COM3 LCD Common signal output H Oo o o COM4 COM7 LCD Common signal output 29 26 P1 7 P1 4
147. e contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst Opc SIC 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH SPH and PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value 0000H and the general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of the register 40H into the location OFFFFH and adds this new value to the top of the stack ELECTRONICS 53 8235 8235 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 82 IR R Given Register 00H 03H
148. e of the timer A capture input selection bit in the port control register PSCON set 1 bank 1 E8H When 5 4 is 00 the TACAP input or normal input is selected When P3CON 5 4 is set to 10 normal output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the TA data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin 11 2 ELECTRONICS 53 8235 8235 8 TIMER CONTROL REGISTER You use the timer A control register TACON to Select the timer A operating mode interval timer capture mode and PWM mode Select the timer A input clock frequency Clear the timer A counter TACNT Enable the timer A overflow interrupt or timer A match capture interrupt Clear timer match capture interrupt pending conditions TACON is located in set 1 Bank 0 at address EAH and is read write addressable using Register addressing mode A reset clears TACON to 00H This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at
149. e working register RO contains the value 0C7H 11000111B and the register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET 53 8235 8235 WEI wate tor Interrupt WFI Operation Flags Format Example 6 86 The CPU is effectively halted before an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 4n 3F 1 2 3 The following sample program structure shows the sequence of operations that follow WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS 53 8235 8235 INSTRUCTION SET Logical Exclusive OR XOR dst src Operation dst dst src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are diffe
150. ector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence o gi d t mm Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location Branch to the service routine specified by the concatenated 16 bit vector address NOTE 16 bit vector address always begins at an even numbered ROM address within the range of OOH FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables on
151. egister 9 6 9 5 Port 1 High Byte Control Register 9 8 9 6 Port 1 Low Byte Control Register 9 9 9 7 Port 1 Pull up Control Register 9 10 9 8 Port 2 High Byte Control Register 2 9 11 9 9 Port 2 Low Byte Control Register 2 9 12 9 10 Port Control Register 9 14 9 11 Port Interrupt Control Register 3 9 15 9 12 Port Interrupt Pending Register 9 15 9 13 Port 4 Control Register 9 16 S3C8235B F8235B MICROCONTROLLER xiii List of Figures Continued Page Title Page Number Number 10 1 Basic Timer Control Register 10 2 10 2 Basic Timer Block 10 4 11 1 Timer A Control Register 11 3 11 2 Timer A Functional Block 11 4 11 3 Timer B Functional Block 11 5 11 4 Timer B Control Register 11 6 11 5 Timer Data Registers TBDATAH L essen eene 11 7 11 6 Carrier on off Control Register 11 7 12 1 Timer 1 Control Register 1 12 3 12 2 Timer 1 Functional Block
152. egister SYM DEH Set 1 RW Not used Global interrupt enable bit 0 Disable global interrupt processing 1 Enable global interrupt processing Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W 7 e 00 IRQ2 IRQ3 IRQ4 5 IRQ7 Interrupt level enable bits 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupt must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE
153. egister high byte Timer B data register low byte Key strobe data register Voltage level detector control register Watch timer control register Oscillator control register 243 F3H R W STOP Control register 244 F4H R W Pattern generation control register 245 F5H R W Pattern generation data register 246 F6H R W A D converter control register A D converter data register high byte A D converter data register low byte Carrier on off control register 251 FBH Location FCH is not mapped 4 2 ELECTRONI S 53 8235 8235 Register Name Port 0 control High register Port 0 control Low register Port 1 pull up control register Port 1 control High register Port 1 control Low register Port 2 control High register Port 2 control Low register Port 3 control register Port 4 control register Key strobe control register Timer 1 control register Timer 1 counter register high byte Timer 1 counter register low byte Timer 1 data register 1 high byte Timer 1 data register 1 low byte Timer 1 data register 2 high byte Timer 1 data register 2 low byte Timer 1 prescaler register ELECTRONI S Table 4 3 Set 1 Bank 1 Registers Mnemonic Location E2H is not mapped 227 228 CONTROL REGISTER Location E9H is not mapped KSCON 232 234 235 Locations are not mapped T1CON R W R W T1DATA2L TIPS 247 248 Locations F9H FFH are not mapped F7H
154. egister page pointer PP to the appropriate source and destination values Set 1 Bank 0 Bank 1 1 CPU and system control 1 General purpose Peripheral and I O LCD data register LCD Data Register Area Figure 2 5 Set 1 Set 2 Prime Area Register and LCD Data Register Map 2 8 ELECTRONICS 53 8235 8235 ADDRESS SPACES WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 328 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possib
155. els and 16 internal source 32 I O Ports 16 normal I O pins e 16 pins sharing with LCD signals Timers and Timer Counters One programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer function One 8 bit timer counter Timer A with three operating modes Interval mode capture mode and PWM mode One 8 bit timer counter Timer B Carrier frequency or PWM generator e One 16 bit capture timer counter Timer 1 with two operating modes Interval mode Capture mode for pulse period or duty Watch Timer e Interval Time 3 19ms 0 25s 0 55 1 0s at 32 768 kHz e 0 5 1 2 4 kHz buzzer output selectable 1 2 S3C8235B F8235B LCD Controller Driver 24 segments and 8 common terminals e 4 8 common selectable e nternal resistor circuit for LCD bias Analog to Digital Converter e 8 channel analog input e 10 bit conversion resolution e 2b5ys conversion Voltage Booster drive voltage supply S W control Enable Disable Low Voltage Reset LVR Low Voltage Check to make system reset VivR 2 3V 2 8V 3 7V Pattern Generation Module e Pattern generation module triggered by timer match signal and S W Voltage Detector for Indication e Voltage Detector to indicate specific voltage e S W control 2 35V 3 3V 4 5V Key Strobe Mode e Support automatic key strobe output with LCD driver Maximum 4 x 12 key matrices Two Power Down Modes
156. ember to read the contents of ADDATAH L before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the A D converter has no sample and hold circuitry it is very important that fluctuation in the analog level at the ADO AD7 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to noise will invalidate the result If the chip enters to STOP or IDLE mode in conversion process there will be a leakage current path in A D block You must use STOP or IDLE mode after ADC operation is finished ELECTRONICS 15 1 A D CONVERTER 53 8235 8235 CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to set up A D conversion Therefore total of 50 clocks are required to complete an 10 bit conversion When fxx 8 is selected for conversion clock with an 8 MHz fxx clock frequency one clock cycle is 1 us Each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits set up time 50 clocks 50 clock x 1us 50 us at 1 MHz 8 2 8 A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located at address F7H in set 1 bank 0 It has three functions Analog input pin selection bits 4 5 and 6 ADC interrupt enable bit 3 A D operation start or disable bit 0 A D c
157. emory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H and 1034H external data memory locations 1033 ODDH and 1034H 0D5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt 6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H LDEI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 55 INSTRUCTION SET 53 8235 8235 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples NOTE 6 56 dst src dst src rr rm 1 dst src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes an even number for program memory and an odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex
158. ending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C8235B F8235B interrupt structure the timer B underflow interrupt IRQ1 belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the S3C8235B F8235B interrupt structure pending conditions for IRQ3 IRQ4 IRQ5 and IRQ7 must be cleared in the interrupt service routine ELECTRONICS 5 15 INTERRUPT STRUCTURE 53 8235 8235 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows L yone O N A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending c
159. er bank 0 E9H When a 1 is detected a timer 1 match capture or overflow interrupt is pending When the sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the interrupt pending bit If interrupt match capture or overflow are enabled the pending bit is cleared automatically by hardware Timer 1 Control Register T1CON F1H Set 1 Bank 1 R W ve e E e e s Timer 1 clock source selection bit Timer 1 overflow interrupt 000 fxx 1 enable bit 001 fxx 8 0 Disable overflow interrupt 010 fxx 64 1 Enable overflow interrrupt 011 2 T1CK 10 Timer 1 match capture interrupt enable bit 11x Counter stop 0 Disable interrupt 1 Enable interrrupt Timer A counter clear bit 0 No effect 1 Clear counter Auto clear bit Timer 1 operating mode selection bit 00 Interval mode 01 Capture mode capture interrupt on falling edge OVF can occur 10 Capture mode capture interrupt on rising edge OVF can occur 11 Capture mode capture interrupt on both edge OVF can occur NOTE Interrupt pending bits are located in TINTPND register Figure 12 1 Timer 1 Control Register T1CON ELECTRONICS 12 3 16 BIT CAPTURE TIMER 1 3C8235B F8235B BLOCK DIAGRAM T1CON TIONS hot gt 8 gt T1CON 2 M 4 bit 16 bit TCK X Prescaler Counter lt gt TIPS Low 4 bi 4 3 T1OUT Vss gt S Low 4 bit
160. errupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for SS3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3C8235B F8235B uses sixteen vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S3C8235B F8235B interrupt structure there are sixteen possible interrupt sources When service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE 53 8235 8235 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure c
161. es dst C lt dst 7 dst 0 lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag as shown in the figure below ati Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 90 R 91 IR Given Register register 01H 02H and register 02H 17H RL 00H gt Register OOH 55H C 1 RL 01H gt Register 01H 02H register 02H 2bEH C 0 In the first example if the general register contains the value 10101010B the statement RL OOH rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry C and the overflow V flags ELECTRONICS 6 71 INSTRUCTION SET 53 8235 8235 RLC Rotate Left through Carry RLC Operation Flags Format Examples 6 72 dst dst 0 C C lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C and the initi
162. essing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SPO The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset 4 34 ELECTRONICS 53 8235 8235 CONTROL REGISTER STPCON Stop Control Register F4H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before executing the STOP instruction You must set this STPCON register as 101001010 Otherwise the STOP instruction will not be executed ELECTRONICS 4 35 CONTROL REGISTERS 53 8235 8235 SYM System Mode Register DEH Set 1 Reset Value 0 x x x 0 0 Read Write R W _ R W Addressing Mode Register addressing mode only 7 Not used always logic zero 6 1 Not used for the S3C8235B F8235B 0 Global Interrupt Enable Bit note Disable global interrupt processing 1 Enable global interrupt processing NOTE Following reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to 5 0 4 36 ELECTRONICS S3C8235B F8235B CONTROL REGISTER T1CON rimer 1 Control Register F1H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R
163. essing mode to clear the 02H register value to OOH ELECTRONICS 53 8235 8235 INSTRUCTION SET COM Complement COM dst Operation dst NOT dst The contents of the destination location are complemented one s complement All 1s are changed to Os and vice versa Flags Unaffected Set if the result is 0 cleared otherwise Always reset to O Unaffected 2 S Setif the result bit 7 is set cleared otherwise V D H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 60 R 61 IR Examples Given R1 07H and register 07H OF1H COM R1 gt R1 OF8H COM R1 gt R1 07H register 07H OEH In the first example the destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and logic zeros to logic ones leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of the destination register 07H 11110001B leaving the new value OEH 00001 110B ELECTRONICS 6 29 INSTRUCTION SET 53 8235 8235 CP Compare CP Operation Flags Format Examples 6 30 dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Se
164. et addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate long addressing mode ELECTRONICS See list of condition codes in Table 6 6 n 2 0 15 Rn b n 0 15 b 0 7 n 2 0 15 RRp 0 2 4 14 reg or Rn reg 0 255 n 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where p 0 2 14 addr addr 0 254 even number only Rn n 0 15 Rn or reg 0 255 n 0 15 RRp p 0 2 14 RRp or reg reg 0 254 even only where p 0 2 14 reg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where p 0 2 14 addr RRp addr range 0 65535 where p22 14 addr addr range 0 65535 addr addr a number from 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data 0 65535 INSTRUCTION SET 53 8235 8235 Table 6 5 OPCODE Quick Reference OPCODE MAP LOWER NIBBLE E RN DEC DEC ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 b RA 4 DA DA OR OR OR OR
165. f the result is 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 3 C rc Y Given R1 02H R2 and register 02H CPIJE R1 R2 SKIP R2 04H PC jumps to SKIP location In this example the working register R1 contains the value 02H the working register R2 the value 03H and the register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJE instruction must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET 53 8235 8235 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example 6 32 dst src RA If dst src _ 0 PC PC RA Ir lt Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the
166. feed back resistors Pull up resistor COM output voltage deviation SEG output voltage deviation Mn Typ Vpp 0 7 Vpp 0 3 Vout 2 4 V 4 Port 0 4 only Port 3 Vous 5 V 1 mA All output pins except P0 4 P3 Vou Vpp 2 4 V 12 P0 4 only VoL3 Vpp 5 V loL 4 mA All output pins except P0 4 P3 All input pins except ILIH2 Vn Vpp XTN 0 All input pins except l j 2 Vin 0 V XT lou Vour All I O pins and Output pins lo 0 All I O pins and Output pins Rosct Vpp25 0V TA 25 C Xn 0 Vin 0 V Vpp 5 V 10 96 Port 0 1 2 4 25 C Rio ViN 0 V Vpp 5 V 10 25 C nRESET only M DS Vi gg COMI IO 15 i 0 3 V Vpp Vica 4 V ca SEGi IO 15 pA i 0 23 53 8235 8235 S3F8235B FLASH MCU Unit NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 lpp and Ippo include a power consumption of subsystem oscillator Table 21 4 D C Electrical Characteristics Concluded TA 25 C to 85 C Vpp 2 0 V to 5 5 V Supply current 1 2 Vpp 5 V 10 8 MHz crystal oscillator 3 V 10 8 MHz crystal oscillator Min Tp Max Pe 4 MHz crystal oscillator Ippe Idle mode Vpp 5 V 10 3 10 8 MHz crystal oscillator
167. ff Control Bits Off signal Normal display 1 0 External resistor bias booster off display on Valid signal output though COM SEG NOTE The Vicp should be less than or equal to VDD when CAP bias mode is used to 1 8 duty ELECTRONICS 4 15 CONTROL REGISTERS 53 8235 8235 LMOD Lcp Mode Control Register D1H Set 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 LCD SEG20 SEG23 or I O Port 4 Selection Bit I O port is selected LCD SEG is selected 1 6 LCD SEG16 SEG19 or I O Port 2 4 2 7 Selection Bit I O port is selected 1 LCD SEG is selected 5 LCD SEG12 SEG15 or I O Port 2 0 2 3 Selection Bit I O port is selected LCD SEG is selected 1 4 LCD or I O Port 1 7 1 4 Selection Bit I O port is selected LCD COM is selected je 3 2 LCD Clock Selection Bits 1 0 Duty and Bias Selection Bits 1 8 duty 1 4 bias fo 1 1 4 duty 1 3 bias Static 4 16 ELECTRONICS 53 8235 8235 CONTROL REGISTER OSCCON Oscillator Control Register F3H Set 1 Bank 0 Reset Value 0 0 0 Read Write R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the S308235B F8235B 3 Main Sytem Oscillator Control Bit lo Main System Oscillator RUN Main System Oscillator STOP 2 Sub System Oscillator Control Bit Sub system oscillator RUN 1 Sub system oscillator ST
168. he timer 1 capture interrupt is generated whenever the counter value is loaded into the T1 data register By reading the captured data value in T1DATAH L and assuming a specific value for the timer 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAP pin 12 2 ELECTRONICS S3C8235B F8235B 16 BIT CAPTURE TIMER 1 TIMER 1 CONTROL REGISTER T1CON You use the timer 1 control register T1 CON to Select the timer 1 operating mode interval timer capture mode Select the timer 1 input clock frequency Clear the timer 1 counter T1CNTH L Enable the timer 1 overflow interrupt or timer 1 match capture interrupt Clear timer 1 match capture interrupt pending conditions T1CON is located in set 1 and Bank 1 at address F1H and is read write addressable using Register addressing mode A reset clears T1CON to OOH This sets timer 1 to normal interval timer mode selects an input clock frequency of fxx 1 and disables all timer 1 interrupts To disable the counter operation please set T1CON 7 5 to 111B You can clear the timer 1 counter at any time during normal operation by writing a 1 to TICON 2 The timer 1 overflow interrupt T1OVF is interrupt level IRQ2 and has the vector address E6H To detect match capture or overflow interrupt pending condition when or T1OVF is disabled the application program should poll the pending bit TINTPND regist
169. ic interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information EI S Q 5 Interrupt Request Register nRESET R IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM O manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer A overflow TINTPND E9H bank 0 Timer A match capture TACON EAH bank 0 TACNT EBH bank 0 TADATA ECH bank 0 Timer B underflow IRQ1 TBCON EDH bank 0 TBDATAH TBDATAL EFH bank 0 Timer 1 o
170. if the destination working register R0 contains the value 1BH the statement INC RO leaves the value 1CH in that same register The second example shows the effect an INC instruction has on the register at the location assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of the register 1BH from OFH to 10H ELECTRONICS 53 8235 8235 INSTRUCTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Unaffected 2 5 V Setif arithmetic overflow occurred cleared otherwise D H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 0 RR A1 IR Given RO R1 02H register 02H OFH and register INCW RRO gt RO 1AH R1 03H INCW R1 gt Register 02H 10H register O3H OOH In the first example the working register pair RRO contains the value 1AH in the register RO and 02H in the register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in the register R1 In the second example the statement
171. iginal value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst dst 2 6 ccB RA cc O to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits in length Given The carry flag 1 and LABEL X 1FF7H JR C LABEL X gt PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL_X will pass control to the statement whose address is currently in the program counter Otherwise the program instruction following the JR will be executed ELECTRONICS 53 8235 8235 INSTRUCTION SET LD Loap LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src sic 2 4 r8 r R r 0toF D7 Ir r SIC dst 3 6 E4 R R E5 R IR dst src 3 6 E6 R IM D6 IR IM r m m r ELECTRONICS 6 49 INSTRUCTION SET L D Load LD Continued 53 8235 8235 Examples Given RO 01H R1 OAH register 01H register 01H 20H register 02H 02H LOOP and register OFFH LD 0 10 LD R0 01H LD 01H RO LD R1 RO LD QRO R1 LD 00H 01H LD 02H 00H LD
172. ing register block Program Memory Two O Base Address Wo peran dst src x L Instruction Point to One of the Example Woking Register 1 of 8 Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES 53 8238 8235 8235 INDEXED ADDRESSING MODE Continued Register File MSB Points to RPO or RPO or RP1 Selected block RP points to start of workin Program Memory NI E DPGODE p 1 of 4 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits Instruction Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS 53 8235 8235 ADDRESSING MODES INDEXED ADDRESSING MODE Concluded Register File joco M 7 7 7 C CC RPO or RPO or RP1 Selected o RP points to start of working register Program Memory OFFSET OFFSET NEXT 2 Bits block 4 bit Working dst src src Register Address Register Pair 16 Bit addre
173. interrupt Enable interrupt 4 20 ELECTRONICS 53 8235 8235 CONTROL REGISTER POPND Port o Interrupt Pending Register E6H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0 7 PND7 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 6 P0 6 PND6 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 5 P0 5 PND5 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 4 P0 4 PND4 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 je Interrupt request is pending 3 P0 3 PND3 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 je Interrupt request is pending 2 P0 2 PND2 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 41 P0 1 PND1 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending E 0 P0 0 PNDO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending ELECTRONICS 4 2 CONTROL REGISTERS 53 8235 8235 P1CONH Port 1
174. interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources S S Type 3 One level IRQn multiple vectors V4 V multiple sources S S5 S4 4 Spam In the S3C8235B F8235B microcontroller two interrupt types are implemented Levels Vectors Sources Type 1 IRQn V1 51 1 Type2 IRQn S2 S3 Sn 1 3 NOTES 1 The number of Sn and Vn value is expandable 2 In the S3C8235B F8235B implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE 3C8235B F8235B INTERRUPT STRUCTURE The S3C8235B F8235B microcontroller supports sixteen interrupt sources All sixteen of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector a
175. ion References OPCODE Points to Progam ee ie Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND l ti CALL RR2 nstruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS 53 8235 8235 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File 2 RPO or or Selected RP points Program Memory to start fo ips working register 02 EC block i x Working dst src Register Point to the ADDRESS Address un Working Register B Value used OPERAND M 20 iac E UN NN Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES 53 8238 8235 8235 INDIRECT REGISTER ADDRESSING Concluded Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points to start of working register 4 bit Working i block Register Address ee dst src ej Register Next 2 bit Point Pair IE References either Register Pair Program Memory or 1 of 4 Data Memory Program Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in OPERAND Instruction Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 Externa
176. ion in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3C8235B F8235B microcontroller Also included in Part Il are electrical mechanical Flash MCU and development tools data It has 16 chapters Chapter 7 Clock Circuit Chapter 15 10 bit Analog to Digital Converter Chapter 8 RESET and Power Down Chapter 16 Voltage Booster Chapter 9 Ports Chapter 17 Voltage Level Detector Chapter 10 Basic Timer Chapter 18 Pattern Generation Module Chapter 11 8 bit Timer A B Chapter 19 Electrical Data Chapter 12 16 bit Timer 1 Chapter 20 Mechanical Data Chapter 13 Watch Timer Chapter 21 SSF8235B Flash MCU Chapter 14 LCD Controller Driver Chapter 22 Development Tools Two order forms are included at the back of this manual to facilitate customer order for S3C8235B F8235B microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative S3C8235B F8235B MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview S3C8 Series Microcontrollers 211111 nennen nenne nennen nnne sn nnn nnn nnne nnne nnne nnne nnns 1 1 9968235B F8235B Microcontrollet k ort e ree hee o eee apa he Re eve nego eee 1 1 1 2 Block Diagram iiie
177. is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In addition set 2 is logically expanded 2 separately addressable register pages page 0 1 In case of S3C8235B F8235B the total number of addressable 8 bit registers is 632 Of these 632 registers 16 bytes are for CPU and system control registers 24 bytes are for LCD data registers 64 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 512 registers are for general purpose use You can always address set 1 register locations regardless of which of the 2 register pages is currently selected Set 1 locations however can only be addressed using direct addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C8235B F8235B Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte common 528 working register area two 192 byte prime register area and two 64 byte set 2 area LCD data registers CPU and system control
178. is used to release stop mode the value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows When a BTCNT 3 overflow occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER 53 8235 8235 RESET or STOP Bits 3 2 Basic Timer Control Register Write 1010 to disable Data Bus fxx 4096 Clear fxx 1024 8 Bit Up Counter Read Only fxx 128 R NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Start the CPU note Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS 53 8235 8235 8 8 8 OVERVIEW The 8 bit timer A is an 8 bit general purpose timer counter Timer A has three operating modes you can select one of them using the appropriate TACON setting Interval timer mode Toggle output at TAOUT pin Capture input mode with a rising or falling edge trigger at the TACAP pin PWM mode TAPWM Timer A has the following functional components Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer External clock input pin TACK 8 bit counter TACNT 8 bit comparator and 8 bit reference data register
179. isters DOH DFH and a 16 byte common working register area COH CFH Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the S8C8235B F8235B the set 2 address range COH FFH is accessible on pages 0 1 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations ELECTRONICS 2 7 ADDRESS SPACES 53 8235 8235 PRIME REGISTER SPACE The lower 192 bytes 00H BFH of the S3C8235B F8235B s two 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 or 1 you must set the r
180. ity register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3C8235B F8235B uses sixteen vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S3C8235B F8235B interrupt structure there are sixteen possible interrupt sources When service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE 53 8235 8235 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of
181. jump taken 8 r OtoF Given R1 02H and LOOP is the label of a relative address SRP 0C0H DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example the working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements the register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET 53 8235 8235 E Enabie Interrupts El Operation Flags Format Example 6 40 SYM 0 1 The El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have the highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when the EI instruction is executed No flags are affected Bytes Cycles Opcode Hex 1 4 9F Given SYM 00H EI If the SYM register contains the value that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts is the enable bit for global interrupt processing ELECTRONICS
182. l data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS 53 8235 8235 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 Value used in Instruction points to A OPERAND SEN d work
183. lation CALL DLY16 Delay 16 ms AND OSCCON 06H Switch to the main clock RET DLY16 SRP 0COH LD RO 20H DEL NOP DJNZ RO DEL RET 7 6 ELECTRONICS 53 8235 8235 CLOCK CIRCUIT STOP Control Register STPCON Set 1 Bank 0 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction Figure 7 9 STOP Control Register STPCON ELECTRONICS 7 7 53 8235 8235 RESET POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at goes to High level and the nRESET is forced to Low level The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings S3C8235B F8235B into a known operating status To allow time for internal CPU clock oscillation to stabilize the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required oscillation stabilization time for a reset operation is 1 millisecond Whenever a reset occurs during normal operation that is when both Vpp and nRESET are High level the nRESET pin is forced Low and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation Interrupt is disabled The watchdog function basi
184. le for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 11111XXX Slice 31 RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register EN space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Figure 2 6 8 Byte Working Register Areas Slices ELECTRONICS 2 9 ADDRESS SPACES 53 8235 8235 USING THE REGISTER POINTS After a reset RP point to the working register common area RPO points to addresses COH C7H and points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and point to the uppe
185. leared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers for all timers input clock you write a 1 to BTCON O ELECTRONICS 10 1 BASIC TIMER 53 8235 8235 Basic Timer Control Register BTCON D3H Set 1 R W we Watchdog timer enable bit Divider clear bit 1010B Disable watchdog function 0 No effect Other value Enable watchdog function 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTONT Basic timer input clock selection bit 00 fxx 4096 01 fxx 1024 10 2 fxx 128 11 Not used Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS 53 8235 8235 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock A reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occuring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular inte
186. lected by software for P1 0 P1 3 push pull or open drain output mode can be selected by software software assignable pull up Alternatively P1 4 P1 7 can be used as PGO PG3 or COM7 COM4 1 bit programmable I O port Normal input open drain and push pull output with software assignable pull up Alternatively P2 0 P2 7 can be used as SEG12 SEG19 or KSTR1 KSTR8 1 bit programmable I O port Push pull output and schmitt trigger input with mode selected by software P3 0 P3 3 can alternately be used as KINO KIN3 or TAPWM TAOUT TACK TACAP and BUZ 1 bit programmable I O port Push pull output and normal input mode with software assignable pull up Alternatively P4 can be used asPG4 PG7 SEG20 SEG23 or KSTR9 KSTR12 ELECTRONICS 9 1 PORTS 53 8235 8235 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all five S3C8235B F8235B I O port data registers Data registers for ports 0 1 2 3 and 4 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary Register ame Mnemonic Decimal Hex Location WW 9 2 ELECTRONICS 53 8235 8235 PORTS 0 Port 0 is an 8 bit I O Port that you can use two ways General purpose I O External interrupt inputs for INTO INT7 Alternative function Port 0 is accessed directly by writing or reading the port 0 data register PO at location EOH in set 1 bank 0 Port 0 Control Register PO
187. loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Given RO 35H R1 21H PC 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations 0000H 0001H where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to the memory location 0000H The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and the stack pointer are the same as in the first example the statement CALL QRRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program co
188. log To Digital Converter Using the ADG IURE s oo ee 15 5 Using the ADC Main Ro Utlng ert ertet eder kt te E tees hax ua saa esa a Ra ax sa squa aaa 15 6 Chapter 17 Voltage Level Detector Using the Voltage Level Detector ai E a a kau nnne nennen enne kaqa 17 4 Chapter 18 Pattern Generation Module Using the Pattern 111000 18 3 xviii 3C8235B F8235B MICROCONTROLLER List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A D Converter Control 4 5 ADINT A D Conversion Interrupt 4 6 BTCON Basic Timer Control 4 7 CLKCON System Clock Control 4 8 FLAGS System Flags Register 2 0 eret Da Rete E HER ata 4 9 IMR Interrupt Mask Registet tine ie denne 4 10 IPH Instruction Pointer High Byte 4 11 IPL Instruction Pointer Low 4 11 IPR Interrupt Priority 4 12 IRQ Interrupt Request Register 4 13 KSCON Key Strobe Control Register 0 2 04 4 14 LCON EGD Gontrol Fleglster 4 15 LMOD LCD Mode Control
189. ly the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent ELECTRONICS 5 17 53 8235 8235 INSTRUCTION SET INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3C8 series microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an in
190. mple Address 6 60 0043 0120 gt 43 44 lt IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 10 OF The following diagram shows an example of how to use the NEXT instruction Before After Address Data 1P PC 0130 Data Address Data 43 Address 44 Address L 45 Address Address Data Address H 01 Address L 30 45 Address 120 130 Routine ELECTRONICS 53 8235 8235 INSTRUCTION SET NOP No Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to affect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex ope 1 4 FF When the instruction NOP is executed in a program no operation occurs Instead there happens a delay in instruction execution time which is of approximately one machine cycle per each NOP instruction encountered ELECTRONICS 6 61 INSTRUCTION SET 53 8235 8235 OR Logical OR OR dst src Operation dst lt dst OR src The source operand is logically ORe
191. n be changed in 3 kinds voltages by selecting Voltage Level Detector Control register VLDCON When you write 2 bit data value to VLDCON an established resistor string is selected and the VVLD is fixed in accordance with this resistor Table 17 1 shows specific of levels Resistor string Voltage Level Detect Control F1H Set 1 Bank 0 R W Reset 00H we Not used VIN Comparator VREF Bias BANDGAP VLD Enable Disable Figure 17 3 Voltage Level Detect Circuit and Control Register Table 17 1 VLDCON Value and Detection Level 99 235 sof ELECTRONICS 17 3 VOLTAGE LEVEL DETECTOR 53 8235 8235 Programming Tip Using the Voltage Level Detector ORG 0000h ORG 0100h INITIAL SB0 LD SYM 00h Disable Global interrupt gt SYM LD SPH 00h High byte of stack pointer SPH LD SPL 00h Low byte of stack pointer SPL LD BTCON 1010001 1b Disable Watch dog LD CLKCON 00011000b Non divided LD VLDCON 00000100b Set 2 35 V El MAIN NOP NOP TM VLDCON 00001000b If Vpp is lower than the reference voltage VLDCON 3 bit is set JP NZLOW VDD NOP NOP JR T MAIN LOW VDD JR T MAIN END 17 4 ELECTRONICS S3C8235B F8235B PATTERN GENERATION MODULE PATTERN GENERATION MODULE OVERVIEW PATTERN GNERATION FLOW You can output up to 8 bit through P1 4 P1 7 and P4 0 P4 3 by tracing the following sequen
192. n operand is not the result of a valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 06 0 SBC 1 7 0 0 9 A0 60 1 1 6 F 1 6 F 9A 66 1 Flags C Setif there was a carry from the most significant bit cleared otherwise see table Z Setif result is 0 cleared otherwise S Setif result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 40 R 41 IR ELECTRONICS 6 33 INSTRUCTION SET 53 8235 8235 DA Decimal Adjust DA Continued Example Given The working register RO contains the value 15 BCD the working register R1 contains 27 BCD and the address 27H contains 46 BCD ADD R1 RO i C H lt 0 Bits 4 7 3 bits 0 3 C R1 lt DA R1 R1 lt 06 If an addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using the standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 3CH The DA instruction adjusts this result so
193. nable Open drain output SEG18 Key strobe KSTR7 output enable 3 2 bit P2 5 SEG17 KSTR6 Input mode Input mode pull up Push pull output SEG17 Key strobe KSTR6 output enable Open drain output SEG17 Key strobe KSTR6 output enable 1 0 bit P2 4 SEG16 KSTR5 Input mode Input mode pull up Push pull output SEG16 Key strobe KSTR5 output enable Open drain output SEG16 Key strobe KSTR5 output enable Figure 9 8 Port 2 High Byte Control Register P2CONH ELECTRONICS 9 11 PORTS 53 8235 8235 Port 2 Control Register Low Byte P2CONL E7H Set 1 Bank 1 R W wT 3142 ERENER P2 0 SEG12 KSTR1 P2 1 SEG13 KSTR2 P2 2 SEG14 KSTR3 P2 3 SEG15 KSTR4 7 6 bit P2 3 SEG15 KSTR4 Input mode Input mode pull up Push pull output SEG15 Key strobe KSTR4 output enable Open drain output SEG15 Key strobe KSTR4 output enable 5 4 bit P2 2 SEG14 KSTR3 Input mode Input mode pull up Push pull output SEG14 Key strobe KSTR3 output enable Open drain output SEG14 Key strobe KSTR3 output enable 3 2 bit P2 1 SEG13 KSTR2 Input mode Input mode pull up Push pull output SEG13 Key strobe KSTR2 output enable Open drain output SEG13 Key strobe KSTR2 output enable 1 0 bit P2 0 SEG12 KSTR1 Input mode Input mode pull up Push pull output SEG12 Key strobe KSTR1 output enable Open drain output SEG12 Key strobe KSTR1 output enable Figure 9 9 Port 2 Low Byte Control Register P
194. nable bits 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupt must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE 53 8235 8235 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA _IRQO IRQ1 GroupB IRQ2 IRQ3 IRQ4 GroupC IRQ5 IRQ6 IRQ7 B21 B22 C21 IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt group
195. nd following that location are treated as a single 16 bit value that is decremented by one C Unaffected Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Unaffected 2 5 V Setif arithmetic overflow occurred cleared otherwise D H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 80 RR 81 IR Given RO 12H R1 R2 30H register 30H OFH and register 21H DECW RRO gt DECW R2 gt RO 12H R1 33H Register 30H OFH register 20H In the first example the destination register RO contains the value 12H and the register R1 the value 34H The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem it is recommended to use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 53 8235 8235 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 0 Bit zero of the system mode control register SYM O is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is di
196. nding condition by writing a 0 to the corresponding POPND bit ELECTRONICS 9 3 PORTS 53 8235 8235 Port 0 Control Register High Byte POCONH EOH Set 1 Bank 1 R W ws P0 7 0 6 P0 5 P0 4 6 1 INT5 T1OUT INT4 TBPWM 7 6 bit PO 7 T1CAP INT7 Input mode T1CAP input rising start interrupt on both edge Input mode pull up interrupt on falling edge Push pull output Input mode T1CAP input falling start 5 4 bit P0 6 T1 CK INT6 Input mode T1CK input interrupt on both edge Input mode pull up T1CK input interrupt on falling edge Push pull output Push pull output 3 2 bit P0 5 T1OUT INT5 Input mode interrupt on both edge Input mode pull up interrupt on falling edge Push pull output Alternative function T1OUT 0 bit P0 4 TBPWM INT4 Input mode interrupt on both edge Input mode pull up interrupt on falling edge Push pull output Alternative function TBPWM Figure 9 1 Port 0 High Byte Control Register POCONH 9 4 ELECTRONICS 53 8235 8235 ELECTRONICS PORTS Port 0 Control Register Low Byte POCONL E1H Set 1 Bank 1 R W 5 P0 3 P0 2 P0 1 P0 0 INT2 INT1 INTO Input mode interrupt on rising edge Input mode pull up interrupt on falling edge Input mode interrupt on both edge Push pull output 5 4 bit PO 2 INT2 Input mode interrupt on rising edge Inp
197. nductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 424 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea C P O Box 37 Suwon 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page http www samsungsemi com Printed in the Republic of Korea Preface The S3C8235B F8235B Microcontroller User s Manual is designed for application designers and programmers who are using the S3C8235B F8235B microcontroller for application development It is organized in two main parts Part Programming Model Part Il Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3C8235B F8235B with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addre
198. ne whether a main or a sub clock is selected as the CPU clock and also how this frequency is to be divided by setting CLKCON This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies OSCCON O select the main clock fx or the sub clock fxt for the CPU clock OSCCON 3 start or stop main clock oscillation and OSCCON 2 start or stop sub clock oscillation CLKCON 4 3 control the frequency divider circuit and divide the selected fxx clock by 1 2 8 16 For example you are using the default CPU clock normal operating mode and a main clock of fx 16 and you want to switch from the fx clock to a sub clock and to stop the main clock To do this you need to set CLKCON 4 3 to 11 OSCCON 0 to 1 and OSCCON 3 to 1 simultaneously This switches the clock from fx to fxt and stops main clock oscillation The following steps must be taken to switch from a sub clock to the main clock first set OSCCON 3 to 0 to enable main clock oscillation Then after a certain number of machine cycles has elapsed select the main clock by setting OSCCON O0 to 0 59 PROGRAMMING TIP Switching the CPU clock 1 This example shows how to change from the main clock to the sub clock MA2SUB LD OSCCON 01H Switches to the sub clock Stop the main clock oscillation RET 2 This example shows how to change from sub clock to main clock SUB2MA AND OSCCON 07H Start the main clock oscil
199. ng power supply pins c4 Vi c4 Bit settings in the LCD mode register LMOD determine the LCD frame frequency duty and bias and the segment pins used for display output When a subsystem clock is selected as the LCD clock source the LCD display is enabled even during stop and idle modes The LCD control register LCON turns the LCD display on and off and switches current to the charge pump circuits for the display LCD data stored in the display RAM locations are transferred to the segment signal pins automatically without program control LCD O VLC1 VLC4 Controller Driver COMO COM7 W UJ c o O SEGO SEG23 Figure 14 1 LCD Function Diagram ELECTRONICS 14 1 LCD CONTROLLER DRIVER 53 8235 8235 LCD CIRCUIT DIAGRAM Segment Driver 00H 6 00H 5 Timing COM Controller Control LCD Voltage Control NOTE fico fw 2 fw 2 fw 2 fw 2 Figure 14 2 LCD Circuit Diagram 14 2 ELECTRONICS 53 8235 8235 LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses 00H 17H of page 2 are used as LCD data memory When the bit value of a display segment is 1 the LCD display is turned on when the bit value is O the display is turned off Display RAM data are sent out through segment pins SEGO SEG23 using a direct memory access DMA method that is synchronized with the f cp signal RAM addresses in this location that not used for LCD display can be alloca
200. nter If for example you write the value 10H to TADATA and to TACON the counter will increment until it reaches 10H At this point the TA interrupt request is generated the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer A data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from OOH Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAPWM pin is held to Low level as long as the reference data value is less than or equal lt the counter value and then the pulse is held to High level for as long as the data value is greater than the counter value One pulse width is equal to 256 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the TA data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the valu
201. nterrupt register ADINT Eight multiplexed analog data input pins ADO 07 alternately digital data I O port 10 bit A D conversion data output register ADDATAH L and AVss pins AVss is internally connected to Vgg FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at the first you must set port control register P1 CONH L for AD analog input And you write the channel selection data in the A D converter control register ADCON 4 6 to select one of the eight analog input pins ADO 7 and set the conversion start or enable bit ADCON 0 The read write ADCON register is located in set 1 bank 0 at address The unused pin can be used for normal 1 During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed ADINT 0 the end of conversion EOC bit or pending bit is automatically set to 1 and the result is dumped into the ADDATAH L register where it can be read The A D converter then enters an idle state Rem
202. ntrol Low register 22 Location E2H is not mappe Port 1 pull up control register 227 Port 1 control High register P1CONH Port 1 control Low register P1CONL Port 2 control High register P2CONH Port 2 control Low register P2CONL 231 Port 3 control register P3CON 232 Location E9H is not mapped Port 4 control register 234 Key strobe control register KSCON 235 Locations FOH mom 2 41 Timer 1 counter register high byte T1CNTH 242 Timer 1 counter register low byte TICNTL Timer 1 data register 1 high byte TIDATA1H 244 Timer 1 data register 1 low byte T1DATA1L Timer 1 data register 2 high byte T1DATA2H Timer 1 data register 2 low byte T1DATA2L 247 Timer 1 prescaler TIPS 248 Locations F9H FFH are not mapped m 9 iu T m rm O Bn S S S rm rm m x m B m x 221p r 3 r I Q 3 x e o T mi m Oo O ake AE 8 4 ELECTRONI S 53 8235 8235 RESET POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 3 p
203. nts External crystal ceramic resonator RC oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator control register OSCCON and STOP control register STPCON CPU Clock Notation In this document the following notation is used for descriptions of the CPU clock fx main clock fxt sub clock fxx selected system clock ELECTRONICS 7 1 CLOCK CIRCUIT MAIN OSCILLATOR CIRCUITS XIN XOUT Figure 7 1 Crystal Ceramic Oscillator fx XIN XOUT Figure 7 2 External Oscillator fx XIN XOUT Figure 7 3 RC Oscillator fx 53 8235 8235 SUB OSCILLATOR CIRCUITS 32 768 kHz Figure 7 4 Crystal Ceramic Oscillator fxt XTIN XTourT Figure 7 5 External Oscillator fxt ELECTRONI S 53 8235 8235 CLOCK CIRCUIT CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted Stop mode is released and the oscillator started by a reset operation or an external interrupt with RC delay noise filter In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Releas
204. occurs the program counter and the instruction pointer are swapped This causes the PC to jump to the address 100H and the IP to keep the return address The last instruction in the service routine is normally a jump to IRET at the address FFH This loads the instruction pointer with 100H again and causes the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H 0H FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last tow instruction The IRET cannot be immediately proceeded by an instruction which clears the interrupt status as with a reset of the IPR register ELECTRONICS 53 8235 8235 INSTRUCTION SET JP sump JP cc dst Conditional JP dst Unconditional Operation If cc istrue PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC Flags No flags are affected Format 1 Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 ccD DA cc 0 to F opc dst 2 8 30 IRR NOTES 1 The
205. ocess the next interrupt request ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM OOH FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence 1 Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location oD Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of 0 NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs Boom When the lower priority interrupt service routine ends restore the IMR to its original value by returning the
206. ode Hex opc 1 16 2F Example The diagram below shows an example of how to use an EXIT statement Before After Address Data Address Data IP 0050 IP Address Address Data 6 42 p 60 Main 140 IPL 50 22 Data memey Stack Stack ELECTRONICS 53 8235 8235 INSTRUCTION SET IDLE Operation IDLE Operation Flags Format Example See description The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F The instruction IDLE stops the CPU clock but it does not stop the system clock ELECTRONICS 6 43 INSTRUCTION SET 53 8235 8235 Increment INC Operation Flags Format Examples 6 44 dst dst lt dst 1 The contents of the destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst r OtoF opc dst 2 4 20 R 21 IR Given RO 1BH register OCH and register 1BH OFH INC R0 RO 1CH INC 00H Register 00H 0DH INC RO RO 1BH register 01H 10H In the first example
207. ommon and segment signals is greater than Vi cp The LCD display is turned off when the difference between the common and segment signal voltages is less than cp The turn on voltage Vi cp or Vi is generated only when both signals are the selected signals of the bias Table 14 3 shows LCD drive voltages for static mode 1 3 bias and 1 4 bias Table 14 3 LCD Drive Voltage Values External Resistor Bias LCD Power Supply Static Mode 1 3 Bias 1 4 Bias Ooo e __ w Ooo oo w NOTE TheLCD panel display may be deteriorated if a DC voltage is applied that lies between the common and segment signal voltage Therefore always drive the LCD panel with AC voltage LCD SEG COM SIGNALS The 24 LCD segment signal pins are connected to corresponding display RAM locations at 00H 17H Bits 0 7 of the display RAM are synchronized with the common signal output pins COMO COM7 When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal is sent to the corresponding segment pin Each bias has select and no select signals i4 amp Select 4 Non Select gt Figure 14 5 Select No Select Bias Signals in Static Display Mode ELECTRONICS 14 7 LCD CONTROLLER DRIVER 53 8235 8235 10111213 41516171011 121314151617 I 1 Frame tO x e N Yu e
208. omponents called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources S Sj Type 3 One level IRQn multiple vectors V4 V multiple sources S4 Sh 3 Shim In the S3C8235B F8235B microcontroller two interrupt types are implemented Levels Vectors Sources 1 IRQn V1 Si 51 2 IRQn S2 S3 Sn 51 Type3 NOTES 1 The number of Sn and Vn value is expandable 2 Inthe S3C8235B F8235B implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE S3C8235B F8235B INTERRUPT STRUCTURE The S3C8235B F8235B microcontroller supports sixteen interrupt sources All sixteen of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed fir
209. on It is recommended that the VLD operation should be kept OFF unless it is necessary Also the VLD criteria voltage can be set by the software The criteria voltage can be set by matching to one of the 3 kinds of voltage 2 35V 3 3V 4 5V VDD reference voltage The VLD block works only when VLDCON 2 is set If Vpp level is lower than the reference voltage selected with VLDCON 1 0 VLDCON 3 will be set If VDD level is higher VLDCON 3 will be cleared Please do not operate the VLD block for minimize power current consumption Voltage Level Detector Control Register VLDCON F1H Set 1 Bank 0 R W 5 5 Ts Not used Reference voltage selection bit 00 2 35 V 01 Not used 10 3 3V 11 4 5V VLD operation enable bit 0 Operation off 1 Operation on Voltage level set bit 0 VDD is higher than reference voltage 1 is lower than reference voltage Figure 17 1 VLD Control Register VLDCON ELECTRONICS 17 1 VOLTAGE LEVEL DETECTOR 53 8235 8235 Vpp Pin Voltage Level VLDCON 3 Detector VLD out Voltage VLD run Level Setting VLDCON 1 VLDCON 0 Set the level Figure 17 2 Block Diagram for Voltage Level Detect 17 2 ELECTRONICS 53 8235 8235 VOLTAGE LEVEL DETECTOR VOLTAGE LEVEL DETECTOR CONTROL REGISTER VLDCON The bit 2 of VLDCON controls to run or disable the operation of Voltage level detector Basically this Vvip is set as 2 35 V by system reset and it ca
210. on both edge Push pull output 5 4 PO 2 INT2 o o inputmode inieruptonsingedge CS Fo input mode pulps interrupt on tating eae Input mode interrupt on both edge 13 2 PO 1 INT1 KEE Input mode interrupt on rising edge Input mode pull up interrupt on falling edge 1 Input mode interrupt on both edge 1 0 PO 0 INTO Input mode interrupt rising edge Input mode pull up interrupt on falling edge Input mode interrupt on both edge ELECTRONICS 4 19 CONTROL REGISTERS 53 8235 8235 POINT Porto Interrupt Control Register E5H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0 7 External Interrupt INT7 Enable Bit Disable interrupt je Enable interrupt 6 0 6 External Interrupt INT6 Enable Bit Disable interrupt je Enable interrupt 5 0 5 External Interrupt INT5 Enable Bit Disable interrupt je Enable interrupt 4 0 4 External Interrupt 4 Enable Bit Disable interrupt je Enable interrupt 3 0 3 External Interrupt INT3 Enable Bit Disable interrupt Enable interrupt 2 P0 2 External Interrupt INT2 Enable Bit Disable interrupt Enable interrupt RB 1 P0 1 External Interrupt INT1 Enable Bit Disable interrupt Enable interrupt le 0 0 0 External Interrupt INTO Enable Bit Disable
211. ondition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence 1 Boom Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to pr
212. onversion speed selection bit 1 2 After a reset the start bit is turned off You can select only one analog input channel at a time Other analog input pins ADO AD7 can be selected dynamically by manipulating the ADCON 4 6 bits And the pins not used for analog input can be used for normal I O function A D Converter Control Register ADCON F7H Set 1 Bank 0 R W ws rTsDsDI DIsT2 e e Always logic zero Start or Disable bit 0 Disable operation A D input pin selection bits 1 Start operation Auto clear A D input pin conversion CLK 6 0 0 0 0 1 1 1 1 00 C ADC interrupt enable bit 0 Disable interrrupt 1 Enable interrupt Figure 15 1 A D Converter Control Register ADCON 15 2 ELECTRONICS 53 8235 8235 A D CONVERTER A D Conversion Interrupt Register ADINT FAH Set 1 Bank 0 RW Not used Interrupt pending bit or EOC 0 Not interrupt is pending When read 0 Clear pending bit When write 1 Interrupt is pending When read Figure 15 2 A D Conversion Interrupt Register ADINT Conversion Data Register High Byte ADDATAH F8H Set 1 Bank 0 Ready only Conversion Data Register Low Byte ADDATAL F9H Set 1 Bank 0 Ready only ZEEENERENEXENESEJ _ Figure 15 3 A D Converter Data Register ADDATAH L INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog
213. or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number V Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is cleared to 0 after a logic operation has been performed D Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and it cannot be addressed as a test condition H Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is normally not accessed directly by a program FIS Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed BA Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 o
214. or you can configure the following alternative functions Low byte pins 1 0 1 3 ADO AD3 High byte pins 1 4 1 7 AD4 AD7 COM7 COM4 0 Port 1 Control Register P1CONH P1CONL Port 1 has two 8 bit control registers P1CONH for P1 4 P1 7 P1CONL for 1 0 1 3 A reset clears the P1CONH and P1CONL registers to configuring all pins to input mode You use control registers settings to select input or output mode push pull or open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Pull up Resistor Enable Register P1PUR Using the port 1 pull up resistor enable register P1PUR set 1 bank 1 you can configure pull up resistors to individual port 1 pins ELECTRONICS 9 7 PORTS 9 8 NOTE 53 8235 8235 Port 1 Control Register High Byte P1 CONH Set 1 Bank 1 R W 7 5 5 P1 4 AD4 COM7 PGO P1 5 AD5 COM6 PG1 P1 6 AD6 COM5 PG2 P1 7 AD7 COM4 PG3 7 6 bit P1 7 PG3 AD7 COM4 Input mode AD7 converter input Normal input off Push pull output COM4 output enable Alternative function PG3 output 5 4 bit P1 6 PG2 AD6 COM5 Input mode AD6 converter input Normal input off Push pull output 5 output enable Alternative
215. page selection bits 0000 Destination Page 0 0000 Source Page 0 NOTE the S3C8235B F8235B microcontroller pages 0 1 and 2 are implemented A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should be modified to address other pages Figure 2 4 Register Page Pointer PP 59 PROGRAMMING Using the Page Pointer for RAM clear Page 0 Page 1 LD PP 00H Destination 0 Source 0 SRP 0COH LD RO 0FFH Page 0 RAM clear starts RAMCLO CLR RO DJNZ RO RAMCLO CLR RO RO 00H LD PP 10H Destination 1 Source 0 LD RO 0FFH Page 1 RAM clear starts RAMCL1 CLR RO DJNZ RO RAMCL1 CLR RO RO 00H NOTE You should refer to page 6 39 and use DJNZ instruction properly when DJNZ instruction is used in your program 2 6 ELECTRONICS 53 8235 8235 ADDRESS SPACES REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations The upper 32 byte area of this 64 byte space EOH FFH is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 contains 48 mapped system and peripheral control registers The lower 32 byte area contains 16 system reg
216. r slice see Figure 2 6 Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange lt 48H SRPO 0A0H RPO lt RP1 lt nochange CLR RPO RPO lt OOH lt nochange LD RP1 0F8H RPO lt nochange lt OF8H Register File Contains 32 8 Byte Slices 8 Byte Slice 16 Byte Contiguous RP1 5 Figure 2 7 Contiguous 16 Byte Working Register Block 2 10 ELECTRONICS 53 8235 8235 ADDRESS SPACES 8 Byte Slice 16 Byte 8 Byte Slices 00000XXX 8 Byte Slice RPO Register File Contiquous 00001 7X XX Contains 32 2 Working RP1 Register block Figure 2 8 Non Contiguous 16 Byte Working Register Block PROGRAMMING TIP Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 H respectively SRPO 80H RPO lt 80H ADD RO R1 RO lt RO Ri ADC R0 R2 RO lt RO R2 C ADC RO R3 RO lt RO ADC R0 R4 RO lt RO R4 G ADC R0 R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H
217. r Address 00 00 enne enne a 5 5 5 4 Interrupt Function 5 8 5 5 System Mode Register 5 5 10 5 6 Interrupt Mask Register 5 11 5 7 Interrupt Request Priority 5 12 5 8 Interrupt Priority Register 5 13 5 9 Interrupt Request Register 5 14 6 1 System Flags Register 6 6 7 1 Crystal Ceramic Oscillator fx eese 7 2 7 2 External Oscillator fx 7 2 7 3 Oscillator fx divi demie 7 2 7 4 Crystal Ceramic Oscillator 7 2 7 5 External Oscillator 7 2 7 3 System Clock Circuit 7 3 7 7 System Clock Control Register 7 4 7 8 Oscillator Control Register 05 menn 7 5 7 9 STOP Control Register 7 7 9 1 Port 0 High Byte Control Register 9 4 9 2 Port 0 Low Byte Control Register 9 5 9 3 Port 0 Interrupt Control Register 9 6 9 4 Port 0 Interrupt Pending R
218. r Block 16 2 16 2 Pin Connection Example ennas raie a A nes 16 2 xiv 3C8235B F8235B MICROCONTROLLER List of Figures Concluded Page Title Page Number Number 17 1 VLD Control Register emen 17 1 17 2 Block Diagram for Voltage Level 17 2 17 3 Voltage Level Detect Circuit and Control 17 3 18 1 Pattern Generation 1 eene nnn enne nnne 18 1 18 2 PG Control Register 18 2 18 3 Pattern Generation Circuit 18 2 19 1 Input Timing for External Interrupts 19 5 19 2 Input Timing for RESET ecc cuia it puce uay SG TEATAS EAPN aou az yz 19 5 19 3 Stop Mode Release Timing Initiated by 19 6 19 4 Stop Mode main Release Timing Initiated by Interrupts 19 7 19 5 Stop Mode sub Release Timing Initiated by Interrupts 19 7 19 6 Clock Timing Measurement al ierant sanae reden 19 10 19 7 Clock Timing Measurement at XT qw 19 11 19 8 LVR Low Voltage Reset 19 13 19 9 Operating Voltage R
219. r bank 1 The flag is cleared to 0 select bank 0 when the SBO instruction is executed and is set to 1 select bank 1 when the SB1 instruction is executed ELECTRONICS 6 7 INSTRUCTION SET 53 8235 8235 INSTRUCTION SET NOTATION Table 6 2 Flag Notation Conventions Flag Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero C Z S V D H 0 1 Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode 6 8 ELECTRONICS 53 8235 8235 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Condition code Working register only Bit b of working register Bit LSB of working register Working register pair Register or working register Bit b of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed short offs
220. ration only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes mmy as sot Always false Always true II Carry II No carry II Zero Not zero Plus Minus Overflow No overflow 0 0 1 1 0 1 Equal II Not equal Greater than or equal OR V 0 OR V 1 gt Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than R S V 0 V 1 OO Nao NN lt lt II C 0 AND Z 0 1 Unsigned less than or equal C OR 2 1 NOTES 1 Itindicate condition codes which are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used Following a CP instruction you would probably want to use the instruction EQ 2 Foroperations using unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS 53 8235 8235 INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each instruction in the S3C8 series INSTRUCTION SET instruction set Information
221. re is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Examples Given R1 src dst 10H R2 03H C flag 1 register 01H 20H register 02H 03H and register 03H OAH ADC ADC ADC ADC ADC R1 R2 R1 R2 01H 02H 01H 02H 01H 11H dst src EN EN Bytes Cycles Opcode Addr Mode Hex dst 4 12 r 6 13 r 6 14 R 15 R 6 16 R R1 14H R2 03H R1 1BH R2 Register 01H Register 01H Register 01H 03H 24H register 02H 2BH register 02H 32H src r Ir In the first example the destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value The statement ADC R1 R2 adds and the carry flag value 1 to the destination value 10H leaving 14H in the register R1 ELECTRONICS 53 8235 8235 INSTRUCTION SET ADD Add ADD Operation Flags Format Examples dst src dst dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setif the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow
222. red and buffer to compare to T1CNT is loaded with T1DATA1 eL gnum TIDATA2 x 48 T1DATA1 48 T1DATA2 r T1CON 4 3 01 10 or 11 but 00 T1CON 4 3 01 10 or 11 but 00 POCONH 7 6 00 Rising Start POCONH 7 6 11 Falling Start 12 4 ELECTRONICS 53 8235 8235 PROGRAMMING TIP Using the Timer 1 INITIAL MAIN T1MC INT ORG 0000h VECTOR OEA4h T1MC INT ORG 0100h LD SYM 00h LD IMR 00000100b LD SPH 00000000b LD SPL 00000000b LD BTCON 10100011b SB1 LD T1CON 01000110b LDW T1DATA1H 0F0h LD T1PS 00h EI MAIN ROUTINE JR T MAIN Interrupt service routine IRET END ELECTRONI S 16 BIT CAPTURE TIMER 1 Disable Global interrupt Enable IRQ2 interrupt Set stack area Disable Watch dog Enable interrupt Duration 1 92 ms 8 MHz x tal 53 8235 8235 WATCH WATCH OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit 1 and bit 6 of the watch timer mode register WTCON 1 and 6 to 1 After the watch timer starts and elapses a time the watch timer interrupt is automatically set to 1 and interrupt requests commence in 3 91ms 0 25s 0 5s or 1 0s intervals The watch timer can generate a steady 0 5kHz 1kHz 2 kHz or 4 kHz signal to the BUZZER output By setting WTCON 3 and WTCO
223. register 01H 05H and register 02H 1AH PUSHUD 90 01 gt Register OOH 02H register 01H register 02H 05H If the user stack pointer the register 00H for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET 53 8235 8235 PUSHUI Push User Stack Incrementing PUSHUI Operation Flags Format Example 6 68 dst src IR lt IR 1 dst src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 83 IR R Given Register 00H 03H register 01H 05H and register 04H 2AH PUSHUI 00 01 gt Register OOH 04H register 01H register 04H 05H If the user stack pointer the register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS 53 8235 8235 RCF Reset Carr
224. registers Mapped clock peripheral control and data registers Total Addressable Bytes 2 4 ELECTRONICS 53 8235 8235 0 System and Peripheral Control Registers Register Addressing Mode System and Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode 2i LCD Display Reigster ADDRESS SPACES Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations Prime Data Registers All Addressing Modes Figure 2 3 Internal Register File Organization ELEGTRONIGS 2 5 ADDRESS SPACES 53 8235 8235 REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the S3C8235B F8235B microcontroller a paged register file expansion is implemented for LCD data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W TPT Destination register page selection bits Source register
225. rent Otherwise a 0 bit is stored Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 B2 r r 6 B3 r Ir src dst 3 6 B4 R R B5 R IR opc dst src 3 6 B6 R IM Examples Given RO 0C7H R1 02H R2 18H register 2BH register 01H 02H and register 02H 23H XOR RO R1 gt RO 5 R1 02H XOR RO QGR1 gt RO OE4H R1 02H register 02H 23H XOR 00H 01H gt Register 00H 29H register 01H 02H XOR 00H 01H gt Register OOH 08H register 01H 02H register 02H 23H XOR 00H 54H gt Register OOH 7FH In the first example if the working register RO contains the value 0C7H and if the register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result OC5H in the destination register RO ELECTRONICS 6 87 53 8235 8235 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The S3C8235B F8235B microcontroller has two oscillator circuits a main clock and a sub clock circuit The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits The maximum CPU clock frequency of S3C8235B F8235B is determined by CLKCON register settings SYSTEM CLOCK CIRCUIT The system clock circuit has the following compone
226. ressing mode only 7 4 Not used for the S308235B F8235B 3 S W Trigger Start Bit LO No etet 000000000002 S W trigger start Auto clear 2 PG Operation Disable Enable Selection Bit PG operation disable PG operation enable 1 0 PG Operation Mode Selection Bits Timer A match siganal triggering 1 Timer B underflow siganal triggering Timer 1 match siganal triggering S W triggering ES ELECTRONICS 4 31 CONTROL REGISTERS 53 8235 8235 PP _ Register Page Pointer DFH Set1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits Destination page 0 1 Destination page 1 Destination page 2 Source page 0 1 Source page 1 Source page 2 NOTE Inthe S3C8235B F8235B microcontroller the internal register file is configured as three pages Pages 0 2 The pages 0 1 are used for general purpose register file and page 2 is used for LCD data register or general purpose registers 4 32 ELECTRONICS S3C8235B F8235B CONTROL REGISTER RPO Register Pointer 0 D6H Set 1 Reset Value 1 1 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can
227. roup C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C 0 controls the relative priority setting of IRQO and IRQ1 interrupts 5 12 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE Interrupt Priority Register IPR FFH Set 1 Bank 0 R W ve e Group priority HEN EIE ERN d D7 D4 01 0 IRQ0 gt IRQ1 Undefined 1 IRQ1 gt IRQ0 B gt CsA Group B A gt B gt C 0 IRQ2 gt IRQ3 IRQ4 B gt A gt C 1 IRQ3 IRQ4 gt IRQ2 C gt A gt B Subgroup B C gt BsA 0 IRQ3 gt IRQ4 A gt C gt B 1 IRQ4 gt IRQ3 Undefined Group C 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 0O O O Figure 5 8 Interrupt Priority Register IPR ELECTRONICS 5 13 INTERRUPT STRUCTURE 53 8235 8235 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt reques
228. rred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir src dst 3 6 34 R R 35 R IR opc dst src 3 6 36 R IM Given R1 10H R2 08H C 1 register 01H 20H register 02H 03H and register O3H SBC R1 R2 gt R1 OCH R2 03H SBC R1 R2 gt R1 05H R2 register OAH SBC 01H 02H gt Register 01H 1CH register 02H SBC 01H 02H gt Register 01H 15H register 02H register OAH SBC 01H 8AH gt Register 01H 95H C S and V 1 In the first example if the working register R1 contains the value 10H and the register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in the register R1 ELECTRONICS 6 77 INSTRUCTION SET 53 8235 8235 SCF set Carry Flag SCF Operation C lt 1 The carry flag C is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex 1 4 DF Example The statement SCF sets the carry flag to 1 6 78 ELECTRONICS 53 8235
229. rupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH 1 Read only RQ0 IRQ2 IRQ3 IRQ4 IRQ6 IRQ5 IRQ7 Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt
230. rvals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an internal and an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an internal and an external interrupt When overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an internal and external interrupt
231. s A B and C For example the setting 001B for these bits would select the group relationship B C A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C 0 controls the relative priority setting of IRQO and IRQ1 interrupts 5 12 ELECTRONICS 53 8235 8235 Group priority D7 D4 D1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 ELECTRONICS Undefined B gt CsA gt gt gt gt gt gt gt gt gt gt Undefined INTERRUPT STRUCTURE Interrupt Priority Register IPR FFH Set 1 Bank 0 R W 0 IRQO gt IRQ1 1 IRQ1 gt IRQ0 Group B 0 IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 __ Subgroup B 0 IRQ3 gt IRQ4 1 IRQ4 gt IRQ3 __ Group C 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 Figure 5 8 Interrupt Priority Register IPR 5 13 INTERRUPT STRUCTURE 53 8235 8235 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor inter
232. s in system and peripheral control registers are unchanged except STPCON register lf you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed How to Enter into Stop Mode Handling STPCON register then writing Stop instruction keep the order LD STPCON 10100101 STOP NOP NOP NOP ELECTRONICS 8 5 RESET and POWER DOWN 53 8235 8235 IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically
233. s specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR _ Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES 53 8238 8235 8235 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File 8 bit Register OPERAND Point to One 27 DESDE Register in Register PSI OneOpeand e Instruction Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot or RP1 Selected RP points to start 7 register block Program Memory Working Register dst OPCODE Kua ihe OPERAND Working Regi
234. sabled No flags are affected Bytes Cycles Opcode Hex 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing ELECTRONICS 6 37 INSTRUCTION SET 53 8235 8235 DIV Divide Unsigned DIV Operation Flags Format Examples 6 38 dst src dst src dst UPPER REMAINDER dst LOWER QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers C Set if the V flag is set and the quotient is between 28 and 29 41 cleared otherwise Set if the divisor or the quotient 0 cleared otherwise Set if MSB of the quotient 1 cleared otherwise Unaffected 2 5 V Setif the quotient is gt 28 or if the divisor 0 cleared otherwise D H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Given RO 10H R1 03H R2 40H
235. ss added to Program Memory offset LSB Selects or Data Memory gt Register Point to Working Pair 8 Bits 16 Bits OPERAND Value used in 16 Bits Instruction Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES 53 8238 8235 8235 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte or 1 4 LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed Figure 3
236. ssing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3C8235B F8235B interrupt structure in detail and further prepares you for additional information presented the individual hardware module descriptions in Part II Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part II If you are not yet familiar with the S3C series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the informat
237. st The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE Levels RESET IRQO IRQ1 IRQ2 IRQ5 IRQ6 IRQ7 NOTES Vectors 100H DEH EOH E2H E4H E6H E8H EAH ECH EEH FOH F2H F6H F8H FAH FEH Sources Basic timer overflow Timer A match capture Timer A overflow Timer B underflow Timer 1 match capture Timer 1 overflow P0 0 external interrupt P0 1 external interrupt P0 2 external interrupt P0 3 external interrupt P0 4 external interrupt P0 5 external interrupt P0 6 external interrupt P0 7 external interrupt Watch timer overflow AD interrupt Key strobe interrupt 53 8235 8235 Reset Clear H W H W S W H W S W H W H W S W H W S W S W S W S W S W S W S W S W S W S W 1 Within a given interrupt level the lower vector address has high priority For example DEH has higher priority than EOH within the level IRQO the priorities within each level are set at the factory 2 External interrup
238. ster Two Operand ty Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS 53 8235 8235 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations in set 1 using the Indirect Register addressing mode Program Memory Register File PE dee e j 20 ADDRESS OPCODE Point to One gt Register in Register OneOperand I File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES 53 8238 8235 8235 INDIRECT REGISTER ADDRESSING MODE Continued Register File REGISTER Example Instruct
239. stination are affected The source is unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 27 Rb r NOTE Inthe second byte of the 3 byte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 gt R1 06H register 01H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example the destination working register R1 has the value 07H 00000111B and the source register 01H has the value 00000011 The statement BXOR R1 01H 1 exclusive ORs bit one of the register 01H the source with bit zero of R1 the destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of the source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET 53 8235 8235 CALL Call Procedure CALL Operation Flags Format Examples 6 26 dst SP lt SP 1 SP lt PCL SP lt SP 1 SP lt PCH PC lt ast The contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then
240. sult is a non zero value eration result is zero 1 5 Sign Flag S Operation generates a positive number MSB 0 Operation generates a negative number MSB 1 4 Overflow Flag V Operation result is lt 127 or gt 128 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag D Add operation completed Subtraction operation completed 2 Half Carry Flag H No carry out of bit 3 or no underflow into bit 3 by addition or subtraction Addition generated carry out of bit 3 or subtraction generated underflow into bit 3 1 Fast Interrupt Status Flag FIS EN Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag BA Bank 0 is selected Bank 1 is selected ELECTRONICS 4 CONTROL REGISTERS 53 8235 8235 IMR Interrupt Mask Register DDH Set 1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit Key Strobe Interrupt Disable mask RB Enable un mask 6 Interrupt Level 6 IRQ6 Enable Bit AD Interrupt Disable mask 1 Enable un mask 5 Interrupt Level 5 IRQ5 Enable Bit Watch Timer Overflow Disable mask 1 Enable un mask 4 Interrupt Level 4 IRQ4 Enable Bit External Interrupts 0 4 0 7 Disable mask 1 Enable un mask 3 Interrupt
241. t has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 Read only ve RQ0 2 IRQ4 IRQ5 IRQ7 IRQ6 Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other must be cleared in the interrupt service routine by software Pending Bits Cleared Automatically by Hardware For interrupt p
242. t operates with MS DOS as its operating system can be used One type of debugging tool including hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 for S3C7 S3C9 S3C8 families of microcontrollers The SMDS2 is a new and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information 5 5 88 The 5 5 88 is a relocatable assembler for Samsung s S3C8 series microcontrollers The SASM88 takes a source file containing assembly language statements and translates into a corresponding source code object code and comments The SASM88 supports macros and condition
243. t position bit zero was 1 Z Set if the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 CO R C1 IR Given Register 55H register 01H 02H register 02H 17H and C 0 RRC 00H gt Register OOH 2AH C 1 RRC 01H gt Register 01H 02H register 02H OBH 1 In the first example if the general register 00H contains the value 55H 01010101B the statement RRC OOH rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in the destination register 00H The sign flag and the overflow flag are both cleared to 0 ELECTRONICS 53 8235 8235 INSTRUCTION SET SBO Select Bank 0 SBO Operation Flags Format Example BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting the bank 0 register addressing in the set 1 area of the register file No flags are affected Bytes Cycles Opcode Hex opc 1 4 4F The statement SBO clears FLAGS 0 to 0 selecting the bank 0 register addressing ELECTRONICS 6 75 I
244. ta register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of 00H ELECTRONICS 2 19 ADDRESS SPACES 53 8235 8235 PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP 2 20 SPL 0FFH PP RPO RP1 R3 R3 RP1 RPO SPL FFH Normally the SPL is set to OFFH by the initialization routine Stack address OFEH PP Stack address OFDH lt RPO Stack address OFCH lt RP1 Stack address OFBH lt R3 R3 lt Stack address OFBH RP1 lt Stack address OFCH RPO lt Stack address OFDH PP lt Stack address OFEH ELECTRONICS 53 8235 8235 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operand
245. ted H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir opc src dst 3 6 54 R R 55 R IR opc dst src 3 6 56 R IM Given R1 12H R2 register 01H 21H register 02H register OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 AND 01H 02H gt Register 01H 01H register 02H 03H AND 01H 02H gt Register 01H OOH register 02H 03H AND 01H 25H gt Register 01H 21H In the first example the destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in the register R1 ELECTRONICS 53 8235 8235 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 dst 0 AND src b or dst b dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or the source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst 3 6 67 Rb ro NOTE Inthe second byte of the
246. ted to general purpose use se COM7 COM6 COM1 COMO Figure 14 3 LCD Display Data RAM Organization ELECTRONICS 14 3 LCD CONTROLLER DRIVER 53 8235 8235 LCD CONTROL REGISTER LCON DOH Table 14 1 LCD Control Register LCON Organization Seung ooa os LCON 1 0 Internal CAP bias display off Low signal output through COM SEG Booster Off 1 Internal CAP bias display on Valid signal output through COM SEG External resistor bias Booster Off display on Valid signal output through COM SEG Not used NOTES 1 Toconfigure SEG12 23 and COM4 7 as COM SEG output port control register must be configured output mode previously 2 The Vj cp should be less than or equal to Vpp when cap bias mode is used to 1 8 duty 14 4 ELECTRONICS 53 8235 8235 LCD CONTROLLER DRIVER LCD MODE REGISTER LMOD The LCD mode control register LMOD is mapped to RAM addresses D1H LMOD controls these LCD functions Duty and bias selection LMOD 1 LMOD 0 LCDCK clock frequency selection LMOD 3 LMOD 2 The LCD clock signal LCDCK determines the frequency of COM signal scanning of each segment output This is also referred to as the frame frequency Since LCDCK is generated by dividing the watch timer clock fw the watch timer must be enabled when the LCD display is turned on RESET clears the LMOD and LCON register values to logic zero This produces the following LCD control settings
247. ter 16 voltage booster Figure 14 8 Voltage Dividing Resistor Circuit Diagram 14 10 ELECTRONICS 53 8235 8235 LCD CONTROLLER DRIVER LCD KEY STROBE OUTPUT MODE The LCD segment output pins SEG12 SEG23 can also output key strobe signal for key scan KINO KIN3 pins check key press When SEG12 SEG23 are set as key strobe output selected key strobe is output pin by pin continuously with selected interval and duration When pins are set as an alternative mode KIN pins status is high impedance normally but when key strobe is output through SEG pins KIN pins status become pull up enable input mode To decide which SEG pin output key strobe you should check P2 and P4 data register If all SEG12 SEG23 are used as key strobe output KSDATA data register constains one number between 1 and 12 If SEG16 SEG23 are used as key strobe output KSDATA data register constains one number between 5 and 12 If SEG20 SEG23 are used as key strobe output KSDATA data register constains one number between 9 and 12 KSDATA data register value is not changed until next strobe occurs To decide which pin receive key strobe you should check P3PND register in interrupt routine So check KSDATA data register and PSPND register and you will get the key press information Key Strobe Control Register KSCON EBH Set 1 Bank 1 R W Key strobe enable bit Key strobe output port selection
248. ternal data memory The assembler makes an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H ODDH LDCD R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H LDED instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 53 8235 8235 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples NOTE dst src dst src dst src m rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Ir an even number for program memory an odd number for data m
249. terrupt level as opposed to each interrupt source system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register RW Function Description Interrupt mask register R W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQ0 IRQ7 Interrupt priority register R W Controls the relative processing priorities of the interrupt levels The seven levels of S8C8235B F8235B are organized into three groups A B and C Group A is IRQO and group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register EMEN This register contains a request pending bit for each interrupt level System mode register SYM R W This register enables disables fast interrupt processing dynamic global interrupt processing and external interface control An external memory interface is implemented in the S3C8235B F8235B microcontroller NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended ELECTRONICS 5 7 INTERRUPT STRUCTURE 53 8235 8235 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The
250. that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C lt H lt 0 Bits 4 7 3 bits 0 3 1 DA QR1 R1 lt 31 0 leave the value 31 BCD in the address 27H R1 6 34 ELECTRONICS 53 8235 8235 INSTRUCTION SET DEC DEC Operation Flags Format Examples Decrement dst dst dst 1 The contents of the destination operand are decremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setif result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 00 R 01 IR Given R1 and register 10H DEC R1 gt R1 02H DEC R1 gt Register 03H OFH In the first example if the working register R1 contains the value the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET 53 8235 8235 DECW Decrement Word DECW Operation Flags Format Examples NOTE 6 36 dst dst lt dst 1 The contents of the destination location which must be an even address and the opera
251. tif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 A3 r Ir opc src dst 3 6 A4 R R A5 R IR opc dst src 3 6 A6 R IM 1 Given R1 02H and R2 08H CP R1 R2 gt Set the C and S flags The destination working register R1 contains the value 02H and the source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative the C and the S flag values are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD RS R1 In this example the destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in the working register R3 ELECTRONICS 53 8235 8235 INSTRUCTION SET CPIJE Compare Increment and Jump on Equal CPIJE Operation Flags Format Example dst src RA If dst src 0 PC RA Ir 1 The source operand is compared to subtracted from the destination operand I
252. tion Time Typ TA 25 C to 85 C Vpp 2 0 V to 5 5 V Oscillator Test Condition Min Typ Max Unit V eves Stabilization occurs when Vpp is equal to the minimum 4 oscillator voltage range External clock Xy input high and low level width ty txt so NOTE Oscillation stabilization time ter4 is the time required for the CPU clock to return to its normal oscillation frequency after a power on occurs or when Stop mode is ended by anRESET signal ELECTRONICS 19 9 ELECTRICAL DATA 53 8235 8235 lt 05 1 5 lt st e txH Figure 19 6 Clock Timing Measurement at Xi Table 19 9 Sub Oscillator Frequency fosc2 TA 25 C to 85 C Vpp 2 0 V to 5 5 V Clock Creu Gondtion Mm Max Unit Crystal XTN C1 33 pF C2 33 pF 32 32 768 35 kHz 19 10 ELECTRONICS 53 8235 8235 ELECTRICAL DATA Table 19 10 Sub Oscillator Crystal Start Up Time tsr gt To Vpp 2 0 V to 5 5 V Test Condition Tp Max unt Ewa memes 700000 p 9 pe External clock XT input high and low level width 5 18 us NOTE Oscillation stabilization time teo is the time required for the CPU return to its normal operation when Stop mode is released by interrupts 14052
253. ts are triggered by a rising or falling edge depending on the corresponding control register setting 5 4 Figure 5 2 S3C8235B F8235B Interrupt Structure ELECTRONICS 53 8235 8235 INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8235B F8235B interrupt structure are stored in the vector address area of the first 256 bytes of the program memory ROM You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 16 384 16 Kbyte Internal Program Memory ROM Area Reset Address Interrupt Vector Address Area Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE 53 8235 8235 Table 5 1 Interrupt Vectors Value Value Level Level me RESET 34 eH Kwseemewt mx 29 mo v v 2 22 0 7 external interrupt IRQ4 3 0 6 external interrupt 2 0 5 external interrupt 1 P0 4 external interrupt 0 0 3 external interrupt IRQ3 3 0 2 external interrupt 2 P0 1 external interrupt 1 P0 0 external interrupt 0 Timer 1 overflow IRQ2 CL 00000 underflow v Timer A overflow 212 e NOTES 1
254. u can enable Port 1 pull up resistor when Port 1 is configured only as input mode or open drain output mode 2 The pull up resistor of Port 1 is disable when LMOD 4 1 Figure 9 7 Port 1 Pull up Control Register P1PUR 53 8235 8235 ELECTRONICS 53 8235 8235 PORTS PORT 2 Port 2 is an 8 bit I O port that can be used for general purpose I O and SEG12 SEG19 The pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank O To individually configure the port 2 pins P2 0 P2 7 you make bit pair settings in two control registers located in set 1 bank 1 P2CONL low byte E7H and P2CONH high byte E6H Port 2 Control Registers P2CONH P2CONL Two 8 bit control registers are used to configure port 2 pins 2 E7H set 1 Bank 1 for pins P2 0 P2 3 and P2CONH E6H set 1 Bank 1 for pins P2 4 P2 7 Each byte contains four bit pairs and each bit pair configures one pin of port 2 Port 2 Control Register High Byte P2CONH E6H Set 1 Bank 1 R W P2 4 SEG16 KSTR5 P2 5 SEG17 KSTR6 P2 6 SEG18 KSTR7 P2 7 SEG19 KSTR8 7 6 bit P2 7 SEG19 KSTR8 Input mode Input mode pull up Push pull output SEG19 Key strobe KSTR8 output enable Open drain output SEG19 Key strobe KSTR8 output enable 5 4 bit P2 6 SEG18 KSTR7 Input mode Input mode pull up Push pull output SEG18 Key strobe KSTR7 output e
255. unter and the stack pointer are the same as in the first example if the program address 0040H contains 35H and the program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS 53 8235 8235 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero If C 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET 53 8235 8235 CLR clear CLR dst Operation dst 0 Flags Format Examples 6 28 The destination location is cleared to O No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 BO R B1 IR Given Register 4FH register 01H 02H and register 02H CLR 00H gt Register OOH OOH CLR 01H gt Register 01H 02H register 02H OOH In Register R addressing mode the statement CLR OOH clears the destination register OOH value to 00H In the second example the statement 901 uses Indirect Register IR addr
256. ush user stack decrementing PUSHUI dst src Push user stack incrementing 6 2 ELECTRONICS 53 8235 8235 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELEGTRONECS 6 3 INSTRUCTION SET 53 8235 8235 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR
257. ust maintain high status although LCD SEG output is not high Figure 14 11 Example of Key Strobe Mode with 1 4 Duty SEG Output NOTE If KSCON 7 1 and P3 is configured as alternative mode P3 0 P3 3 remain floating in interval duration and get pull up in strobe low duration 1 5 or 2 clock when KSDATA contains strobe sequence number 1 12 ELECTRONICS 14 13 LCD CONTROLLER DRIVER 53 8235 8235 59 PROGRAMMING Using the LCD Display ORG 100h INITIAL LD SYM 00h Disable Global interrupt LD BTCON 10100001b Disable Watchdog LD CLKCON 00011000b Select non divided oscillator frequency LD SPL 0 Set SPL LD SPH 0 SB1 LD P1CONH 10101010b Enable COM signal output LD P2CONH 10101010b Enable SEG16 SEG19 LD P2CONL 10101010b Enable SEG12 SEG15 LD P4CON 10101010b Enable SEG20 SEG23 SBO LD WTCON 11000010b LD LCON 11101001b LD LMOD 11111100b LCD RAM clear routine area page 00h 17h LD R0 17h LCD CLR LD PP 20h LD R0 0 DJNZ CLR LD R0 0 LD PP 00h El 14 14 ELECTRONICS 53 8235 8235 PROGRAMMING Using the LCD Display Continued lt lt MAIN ROUTINE gt gt MAIN LDW LD LDC DSP LOOP INC INCW IDC JP JP DSP DAT ELEGTRONIGS RR4 0 R2 40 R3 DSP_DAT RR4 R6 R2 PP 20h R6 R3 PP 00 R2 RR4 R3 DSP_DAT RR4 R2 17h ULE DSP_LOOP MAIN 0 26h 49h 49h 32h 7Fh 8h 34h 43h 0 41h 7Fh 41h 0h 0h 7Fh 41h 41h
258. ut mode pull up interrupt on falling edge Input mode interrupt on both edge Push pull output 3 2 bit PO 1 INT1 Input mode interrupt on rising edge Input mode pull up interrupt on falling edge Input mode interrupt on both edge Push pull output 0 bit PO 0 INTO Input mode interrupt on rising edge Input mode pull up interrupt on falling edge Input mode interrupt on both edge Push pull output Figure 9 2 Port 0 Low Byte Control Register POCONL 9 5 PORTS 53 8235 8235 Port 0 Interrupt Control Register POINT E5H Set 1 Bank 0 R W d aon dede d d INT7 6 INT5 INT4 INTS INT2 INTI INTO POINT Bit Configuration Settings 0 Interrupt disable 1 Interrupt enable Figure 9 3 Port 0 Interrupt Control Register POINT Port 0 Interrupt Pending Register POPND E6H Set 1 Bank 0 R W BERNER PND7 PND6 PND5 PND4 PND3 PND2 PND1 PNDO POPND Bit Configuration Settings 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Figure 9 4 Port 0 Interrupt Pending Register POPND 9 6 ELECTRONICS 53 8235 8235 PORTS 1 Port 1 is 8 bit I O port with individually configurable pins Port 1 pins are accessed directly by writing or reading the port 1 data register P1 at location E1H in set 1 bank 0 1 0 1 7 can serve as inputs outputs push pull or open drain
259. verflow TINTPND E9H bank 0 Timer 1 match capture T1CON F1H bank 1 T1CNTH F2H bank 1 T1CNTL F3H bank 1 T1DATA1H bank 1 T1DATA1L F5H bank 1 T1DATA2H F6H bank 1 T1DATA2L F7H bank 1 5 F8H bank 1 P0 3 external interrupt POCONL E1H bank 1 P0 2 external interrupt POINT E5H bank 0 P0 1 external interrupt POPND E6H bank 0 P0 0 external interrupt 0 7 external interrupt POCONH EOH bank 1 0 6 external interrupt POINT E5H bank 0 P0 5 external interrupt POPND E6H bank 0 P0 4 external interrupt Watch timer overflow IRQ5 WTCON F2H bank 0 AD Interrupt ADCON F7H bank 0 ADDATAH F8H bank 0 ADDATAL F9H bank 0 ADINT FAH bank 0 P1CONH bank 1 P1CONL E5H bank 1 Key strobe interrupt IRQ7 KSCON EBH bank 1 KSDATA bank 0 NOTE If a interrupt is un mask Enable interrupt level in the IMR register the pending bit and enable bit of the interrupt should be written after a DI instruction is executed ELECTRONICS 5 9 INTERRUPT STRUCTURE 53 8235 8235 SYSTEM REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing see Figure 5 5 A reset clears SYM O to 0 The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initializ
260. verflow interrupt 1 Enable overflow interrupt 1 Ti 3 er A Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt Not used for the S3C8235B F8235B i 4 38 53 8235 8235 CONTROL REGISTER TBCON Timer B Control Register EDH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer Input Clock Selection Bits Elapsed time for low data value Elapsed time for high data value 1 EX Elapsed time for low and high data values Invalid setting 2 Ti 3 er B Start Stop Bit Stop timer B Start timer B 1 41 Timer Mode Selection Bit 3 One shot mode 1 Repeating mode 0 Timer B Output flip flop Control Bit 0 T FF is low 1 T FF is high NOTE is selected clock for system ELECTRONICS 4 3 CONTROL REGISTERS 53 8235 8235 TINTPND Timer A 1 Interrupt Pending Register E9H Set 1 Bank 0 Reset Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the S308235B F8235B 3 Timer 1 Overflow Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 2 Timer 1 Match Capture Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 1 Timer A Overflow Interrupt Pending Bit No interrupt pending
261. wes 5 5 Not used 2 KINO Pending Bit Configuration Settings 0 No interrupt pending When write pending clear 1 Interrupt is pending Figure 9 12 Port 3 Interrupt Pending Register P3PND ELECTRONICS PORTS PORTS 53 8235 8235 PORT 4 Port 4 is an 4 bit I O port with individually configurable pins Port 4 pins are accessed directly by writing or reading the port 4 data register P4 at location E4H in set 1 bank 0 P4 0 P4 3 can serve as inputs with or without pull up and push pull output And they can serve as segment pins for LCD and alternative function PG4 PG7 outputs Port 4 Control Registers PACON A reset clears the PACON registers to configuring all pins to input mode Port 4 Control Register PACON EAH Set 1 Bank 1 R W ama ma wa wil P4 ms P4 1 SEG21 PG5 KSTR10 P4 2 SEG22 PG6 KSTR11 P4 3 SEG23 PG7 KSTR12 7 6 bit P4 3 SEG23 PG7 KSTR12 Input mode Input mode pull up Push pull output SEG23 Key strobe KSTR12 output enable Alternative function PG7 output 5 4 bit P4 2 SEG22 PG6 KSTR11 Input mode Input mode pull up Push pull output SEG22 Key strobe KSTR11 output enable Alternative function PG6 output 3 2 bit P4 1 SEG21 PG5 KSTR10 Input mode Input mode pull up Push pull output SEG21 Key strobe KSTR10 output enable Alternative function PG5 output 1 0 bit P4 0 SEG20 PG4 KSTR9
262. y 5 nRESET C4 16 P3 3 BUZ KIN3 4 0 1 2 P0 3 P0 4 TBPWW P3 1 TACK KIN1 1 P3 2 TACAP KIN2 4 2 1 5 Figure 1 3 S3C8235B F8235B Pin Assignment 64 LQFP 1010 ELECTRONI S PRODUCT OVERVIEW S3C8235B F8235B PIN DESCRIPTIONS Table 1 1 S3C8235B F8235B Pin Descriptions Pi Pin Description Circuit Shared Functions Type Type 4 7 P0 0 P0 3 port with bit programmable pins INTO INT3 P0 4 Configurable to schmitt trigger input mode or 8 INT4 TBPWM P0 5 push pull output mode by software 17 INT5 T1OUT P0 6 Pull up resistors are assignable by software 18 INT6 T1CK P0 7 Pins can be assigned individually as external 19 INT7 T1CAP interrupt inputs with noise filters interrupt enable disable and interrupt pending control P1 0 P1 3 22 25 AD0 AD3 P1 4 P1 7 26 29 AD4 AD7 COM7 COM4 PG0 PG3 P2 0 P2 7 I O port with bit programmable pins H 14 46 53 SEG12 SEG19 Configurable to normal input mode or output KSTR1 KSTR8 mode Pin circuits are either push pull or n channel open drain type Pull up resistors are assignable by software Alternately P0 4 pin have high current drive capability I O port with bit programmable pins Configurable to normal input and AD input mode or output mode Pin circuits are either push pull or n channel open drain type Pull up resistors are assignable by software n O O O O O I O port with bit programmable pins Configurable to normal input and AD input mod
263. y Flag RCF Operation Flags Format Example RCF lt 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles 1 4 Given 1 or 0 The instruction RCF clears the carry flag C to logic zero ELEGTRONIGS INSTRUCTION SET Opcode Hex CF 6 69 INSTRUCTION SET 53 8235 8235 RET Return RET Operation Flags Format Example 6 70 PC SP SP SP 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement to be executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 10 AF Given SP 00FCH SP 101AH and PC 1234 RET PC 101AH SP 00FEH The RET instruction pops the contents of the stack pointer location 00FCH 10H into the high byte of the program counter The stack pointer then pops the value in the location 00FEH 1AH into the PC s low byte and the instruction at the location 101AH is executed The stack pointer now points to the memory location 00FEH ELECTRONICS 53 8235 8235 INSTRUCTION SET RL Rotate Left RL Operation Flags Format Exampl
264. y in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semico

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