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AN-6130PCIe Rev. B - updated 3/5/2015

1. 3 12 PCIES SVCC 8311 3 8V 8311 PLL1 5VCC UIA eere 505 2066 P1 2232289522999 NNQQNAHQHETa 9 du dud 8888888888 s B1 A1 SIP SSSI SSS gt gt gt gt Ci R4 Ba 12V PRSNT1 Pag PCIE3 3VCC VDD3 3 GPIOO Bi GPIOT 10K Ba 12V 12V Last VDD3 3 GPIO1 53 Gpioz R5 d 2033 T AT GPIO3 2 0 AT25640 10K 5 JK WAKEIN 4 1 Be SMCLK JTAG2 Fag WAKEIN EECS B7 SMDAT JTAG3 ROOT_COMPLEX EECS 5 1 88 GND JTAG4 PWR OK EECLK 13 EEWRDATA 3 Bg 3 3V JTAGS Fag PLXTI EEWRDATA yg Bro JTAG1 3 3 FAT PLXT2 EERDDATA K 4 EERDDATA Bit 3 3Vaux 3 3V BERST TEST Q WAKER PERST p BUNRI PEX83111 E1 BAROENB BTON BAROENB 2 2 R12 10K T4 A13 1 al PERR TCK i B12 A12 C3 Aii i Bi4 GND REFCLK A14 Hay REFCLK TDI gra f i REFCLK A15 i JT REFCLK TRST i Big PETnO GND aie 1 2 KZ ITDO T 17 GND PERpO PERO GT PETno ITDO 8789 2 PERNO aig C2 PERno F23 GND GND 34 1 2 PERnO 1 e
2. 3 3VCC 3 3VCC 9 9 RN2 RN3 3 3VCC R32 and R33 should not LBEO 1 8 LA2 1 8 be installed by default LBE1 2 id 2 LA31 2 5 ODE MODEO MODE 2 3 5 3 5 0 0 4 5 5 4 5 R35 R36 10K NP NFA 742 08 3 103 XX 742 08 3 103 1 RN5 amp LD 15 0 4 5 ADSn 1 8 LAB 1 8 MODEO R37 BLASTN 2 7 LA7 2 7 PEXREADYn 3 6 LA6 3 6 8 5 85885855585 MOBE R38 2 H EAD 5 5988999898998 988 742 08 3 103 XX 742 08 3 103 1 rg ig ees we SERVNLSSSSSSEEELIREA AR T 4 FING TEE EN g S5882885882rz99 909t ORAuSEX SRSRSS B TERM 3 H Un 88848888 CCSn 3 LAI 3 6 en e e 3 8VCC LINTon 4 E 13 4 5 L16 E18 LRESETn o Li5 Hn 220 KLRESETh 5 742 08 3 103 J XX 742 08 3 103 1 We DPI 3 3VCC 742 08 3 103 1 Ms 082 220 LHOLD R39 Serial EEPROM 9 RNB 019 LHOLDA Local Bus Confi 1 LINTin 1 8 LAM 1 8 LA2 122177 LHOLDA 9 LSERAN 2 7 TAIS 2 7 3 DEA BraS ADSn 5 bs BIGERD 4 5 5 LAS BLAST BLAST 5 LAS READY PEXREADYn 5 vec LAG WIT Dae iP WAIT 9 742 08 3 103 XX 742 08 3 103 1 017 7 LW R pinum ona RNH
3. BIT 15 14 13 12 11 10 9 8 FIELD 4 SW2 5 SW2 4 SW2 3 SW2 2 SW2 1 D5 AUTOEN BIT 7 6 5 4 3 2 1 0 FIELD N A IRQ RT2MC8 RT1MC8 WAIT READY MTPKTRDY ACTIVE DO ACTIVE HI 6130 outputs a high when the BC or RT is processing a 1553 message D1 MTPKTRDY HI 6130 output Monitor Packet active high when message complete D2 READY HI 6130 output Set high when the host can configure the device D3 WAIT HI 6130 output Not used by this design D4 RT1MC8 HI 6130 output Outputs a pulse when a Mode Code 8 is received D5 RT2MC8 HI 6130 output Outputs a pulse when a Mode Code 8 is received D6 IRQ 6130 HI 6130 interrupt output D7 N A Not defined D8 AUTOEN Set by the SW2 DIP switch 6 Input to HI 6130 for auto initialization from EEPROM D9 D5 Not used by connected to a pad on the PCB from D5 to the CPLD D10 SW2 1 DIP SWITCH user defined D11 SW2 2 DIP SWITCH user defined D12 SW2 3 DIP SWITCH user defined D13 SW2 4 DIP SWITCH user defined D14 SW2 5 DIP SWITCH user defined D15 4 Not used but is connected to a pad from A4 to the CPLD Secondary Output Latches R W 0 2 00 0000 BIT 15 D5 4 3 2 1 0 FIELD N A RT2LOCK RT2SSF MTSTOFF RT1LOCK RT1SSF RESET N A 0 0 0 0 0 DO RT1SSF RT1 Subsystem Fail input 01 RT1LOCK R
4. NC PBSE PBI2C LNT gt PT2D PT3D PT5B PT5D PT8D PT11B PB3D PB4D PB4D NC PB8F PB12D 3V3 5 6 swi B4 R6 R11 Sw 5 PT7C PTBE PT12A Te PBAA PBSA PBSA PB7E PB9A PB13A 1 5 PT3B PT3F PTSD PT7D PT8F PT12B PBAB PBSB PBSB PB7F PB9B PB13B ae sw3 E7 T8 P11 T aS 6 PT7A PT9A PT12C T7 PBAC PBSC PBGA PB8A PB9C PB13C 15 485 255 NO PTAD PT6F PT7B PT9B PT12D PBAD PBSD PB6B PB8B PB9D PB13D a SWS PT3E PT5A PT6C PT8A PT9C PT13C 7 PBBC PB9E PB14A 1 113 10K 6 PT8B PT9D PT13D NC PB6B PB7D PB8D PB9F PB14B R57 C6 JTAG R7 R13 7 PT3C PTSC PT6A PT7E PT9E PT14A _ 4 6 PB9A PB10A PB14C HRTF HEADER 10 6 PT7F PT9F PT14B J2 22 PB4F PB6D PB8D PB9B PB10B PB14D B6 011 1 T14 B7 PT4A PTSE PT7A PT9C PT10A PT14C HD17 115 avs PB9C PB10C PB15A Hre e 0 PT4B PT5F PT7B PT9D PT10B PT14D 21 5 PB9D PB10D PB15B 9 3 AS PTAG PTOAPT7C 1 15 10 4 ES Wr TCK NC PB11A PB16A Rie 8 PT4D PT6B PT7D NC PT10D PT15B 5 s TDI NC PB11B PB16B 5 B8 B13 6 7 p4 TDO 1 5 _ 6 PT9E PT10E PT15C 7 4 Tus SLEEPN pi TA 3 PTAF PTGD PT8D PT9F PT10F PT15D 8 PB9F PB10F PB15D 3 14 2 15 T 2 NC PT11A PT16A NC PB11C PB16C 14 lt 7 ao P16 1 NC PTHB PT16B iade tss Me S pins Bin n
5. PR6A PR8C PR10C NC PR15A PR18A LV_T N12 4 4 4 zidi 2 PR6B PR8D PR10D NC PR15B PR18B LV_C NC PRIGA PR20A rr NC PR16B PR20B Pin name sequence 640 1200 2280 Holt Integrated Circuits 23351 Madero Mission Viejo CA 92691 www holtic com Title CPLD power Size Document Number B pate Wednesday August 14 2013 Bheet 8 of 7 E PEX83111 Holt Integrated Circuits 23351 Madero Mission Viejo CA 92691 itle PEX 8311 NC BALLS Size Document Number A lt Doc gt Date Tuesday August 13 2013 Sheet www holtic com Twin Shielded Coax Female Holt Integrated Circuits 23351 Madero Mission Viejo CA 92691 www holtic com itle 6130 PCle MIL STD 1553 Cable Date September 2013 Sheet NNI Bill of Materials PCle 6130 Interface Board Rev 19 Sep 13 Item Qty Description Reference DigiKey Mfr P N 1 1 PCB Bare Evaluation Board NA J J JJ e Advanced Circuits 3568129 MQ 2 2 Ferrite Bead 330 Ohm 100MHz 0805 4 5 490 5988 1 ND BLM21PG331SN1D 3 3 Ferrite Bead 390 Ohm 100MHz 500mA DC 0603 FB1 FB2 FB3 490 5980 1 ND BLM18EG391TN1D 4 8 Capacitor Ceramic 0 001uF 50V 10 X7R 0603 C18 C20 C22 C24 C30 C32 C34 C3
6. RT1 RT2 DIP Misc DIP gt gt SW s SW s SW s 112555 008003 Expansion ports EEPROM EEPROM Pcie Reset 50MHz x Power Power 3 3V wa 12 222 o 3 3V Reg 3V3 HI 6130 CPLD 1 5V HI 6130 PCIe Card Block Diagram HOLT INTEGRATED CIRCUITS 6 AN 6130PCle EEE ee The PEX8300 is used in EndPoint mode which operates in slave mode relative to the host PC A full SDK and RDK reference board design including drivers documentation and demo software is available from PLX This PLX RDK was used as the basis for the Holt card An EEPROM U6 contains configuration data which the PEX8311 latches in at power up to configure the LB for the target hardware base address space data bus width and the number of wait states The data bus width is configured for 16 bits to match the width of the HI 6130 A second EEPROM is also connected to the PEX8311 for optional parameters to enable special configurations mainly for the PCle side A second EEPROM U2 is installed for optional PCle bus configuration but it may or may not be used PLX recommends installing this EEPROM just in case of future needs These EEPROMs can be examined and programmed using the PIxMon utility The PLX utility program PlxMon exe is located in the PIx Bin folder after the SDK is installed Information on how to use this utility is located in the PIxSdkUsersManual document in section 4 PLX Debug Utilities Holt
7. T irs MOCIO2 0 5 Wipro GND NC PR3D PR4D PR7D PR10B PR13B LV C ERE ES TCI VCCIO2 1 GND 7 GND 8 E14 PRSC PRAA PREALV_T PRBA PRIOC PRISC 014 VCCIO3 0 GND 9 PR3D PR4B PRBB LV C PR8B PRIOD PR13D 33 1 Oed VCCIO3 1 GND 10 GND 11 BIS PR2A PRAC PRSC PR8C PR11A PR14A LV_T Heg Pioa VOCIO4 0 is pip cama veers OND PR2B PR4D PR5D PR8D PR11B PR14B LV_C VCCIO4 1 5 GND 13 GND 14 18 PR2C PRSA PREA LV PROA PRTIC PRI4C Hle a 26108 0 T GND 15 PR2D PRSB PR6B LV C PR9B PR11D PR14D 2 VCCIOS 1 GND 16 D16 L15 Eig 5 6 PROC PRI2A PRISA LV_T His 0108 0 5 adii cosmo PR3B PR5D PR6D PR9D PR12B PR15B LV C VCCIO6 1 SES E15 M16 FTE PRANPRGA PRZA LV PR10C PR12C PR15C Wig VCCIO7 0 gt PR4B PR6B PR7B LV_C PR10D PRT2D PR15D VCCIO7 1 VCC 2 F16 114 ias vocii G16 PR5A PR6C PR7C PR10A PR13A PR16A LV_T HiT VCC 0 PR5B PR6D PR7D PR10B PR13B PR16B LV C VCCAUX 0 4 5 33553 912 PRaC PRTA PROALLV T PR11A PR13C PR16C HHE oe 613 PRAD PR7B PRSB LV C PRHB PRISD PRIGD gt rH PEACE CLOSE TO LCMATZO01 avs Hig PReC PR7C PR9C PRHC PRIAAIPRTZALV T ENTS h eoo 93 PR6D PR7D PRSD PR11D PR14B PR17B LV_C da NH al m 2 z 2 Git psopnewomomy z ngpanopao TER pe 1 aey MEQUE PRSD PR8B PR10B LV_C NC PR14D PR17D d xi a a a m a a a a a a
8. HOLT AN 6130PCle INTEGRATED CIRCUITS MIL STD 1553 PCle Card March 4 2015 Evaluation Card Users Guide Introduction The Holt HI 6130 PCle MIL STD 1553 is a PC interface card designed to interface the Holt HI 6130 MIL STD 1553 multi terminal to a single lane x1 x4 8 or x16 PCI Express PCle 1 1 slot on a PC running Windows 7 The 6130 is a single supply 3 3V rail BC MT RT1 RT2 Multi Terminal device for MIL STD 1553 dual redundant bus communications The card is bundled with the Holt high level API software library and two demo programs The two demo projects provided on the included CD ROM demonstrate the basic features of the 6130 and the Holt software library The demo card and software be used as starting point for any new custom design ACTIVE BE Swi en Leo 3 O71 INTEGRATED cir PR LEDS OHolt Inc 83 Lr cu a 1 6130 PCIe Interia LEDA mn Rev 8 2094v 0 2v HOLT INTEGRATED CIRCUITS AN 6130PCle Rev B 1 AN 6130PCle 3 Evaluation Kit Contents e This Application Note AN 6130PCle User s Guide e Holt API library software and user manual ANSI CHI 6130PCle test demo project ANSI C HI 6130 PCle demo project e 9Pin D to MIL STD 1553 BNC breakout cable e Full size PCI card optional bracket e CPLD Verilog project files CD ROM con
9. WAKEOUTSD V PCI Express x1 Edge 2 2 amp C3 Are Low ESR Ceramic caps CRITICAL LAYOUT See PLX docs R19 1K 1K PCIES 3VCC R21 n 18 10k PCIE3 3VCC 1 5VCC ca o 0 01uF 4 g 250 E R22 10k lt 4 VIN VOUT 1 PCIE12VCC 71 5 9 1uF 10V Bi ees LL 12 0 5 BAROENB x R23 0 NP 10uF 10V 2 R24 5 GND BYPASS 0 LM1085 3 3 TO 263 LP2992 MU Ps E 9 4 vout 2 cH a PCIE3 3VCC PLACE CLOSE 8311 OuF 16V PLL Filter le 8311 PLL1 5VCC FBI 9 etn 2 4 Tics 7 C14 c16 R26 10K R27 AUF ATVF 10V y Ni 0 tuF 55 10K d 2 5 3 5 C15 tuF 10V sw 2 quer 1 1 PERST 83114 RESET PERST 4 2 PERSTK 44 8311 15V RST_IN GND y PLACE CLOSE TO 8311 PCIE12VCC PCIES 3VCC 2 4 1 4 7 7 Tew jes je Jos 624 R29 100 is Reset Circuit 2 a R30 100 2 GPIO0 le 625 7 006 ces ou 1 J o cotuF Jour 0 0010 J oo0tuE J oootuF 100 35 8 ji LEDI LED R32 100 15 x 16 our lt gt 2 GPIO1 Nen ee LED2 LED2 o Place close to the 1 580 JB PS edge connector 9 4 LED 1 LED3 LED3 PLACE CLOSE TO 8311 BEIGE aveo 3 1
10. NC PL8A PL9A LV_T PLI0C PLI4C PLI7C 2 8 12LOCK O 55 3V3 1 2 1 001 3 PEXREADYn NO PL8B PL9B LV C PL10D PL14D PL17D 1 6 pad 1 5 as 2 BH PLSC PLBC PLIOC NC PLISA PLTBALV T PLLO T IN Wie 44 M PLSD PL8D PL10D NC PLT5B PLT8B LV C PLLO C IN 7 P amp N4 A E PL11C PLIGA PL19A Ns 1 a 1 26 LED11 LED R69 330 PLHIDIPETSE PLISB 3 E LA27 GREEN 1 2 LEDO2 x i erede LA28 Pin name sequence 25 ac Jac LA29 PL 640 1200 2280 MIPKTRDNQQACTIVE 4 BERON MTPKTRDY 4 K LA 31 2 3 C READY 4 4 7uF 10V RTIMC8n TONGS 2 RT MC Bn 4 2 8 ava mH HI 6130 PQFP RIENCE Cor Con Osca WAIT ROn 4 le 4 C87 lis DWAT 55 WAIT 4 2 PCIE12VCC 351 vec 2 4 T T 1 COSME C88 e C89 1090 el c91 el C92 4093 el 094 ol c95 C96 1 j R70 33 100nFT 100nF T 10uF 10V 100nF T 100nFT 10uF 10V 1001F T 100nF T 10uF 10V AUTOEN AUTOEN 4 34 MCLK GD OUT 7 MCLK 3 12V TO 5V DC DC Converter R71 lt RECOM R 785 0 1 0 NC 3v3 m U10 LM1085 3 3 263 i n _ al 2 RT1AP T5 RT2AP VIN x x gt gt 3V3 4 6 RTTAO TO RT2A0 C98 z RT2A1 C97 C100 RT1A2 12 HT2A2 NP provisional ai ii ep C99 eps T8 RT2A3 E 10uF 16V 10uF 10V 0 01uF RT1A4 T4 2 4 0 1uF
11. PCB layout considerations The PLX data book and hardware checklist should be closely followed for the PCle high speed bus signals Review the Holt AN 550 for PCB layout guidelines for the transformers and decoupling capacitors for the 6120 6130 and 6140 HOLT INTEGRATED CIRCUITS 32 AN 6130PCle Summary The Holt HI 6130 PCle low profile card reference design demonstrates how to interface the HI 6130 MIL STD 1553 multi terminal to a 1 lane x1 PCle bus A Holt high level API software library is provided and demonstrated in the demo software All the design files are included on the CD ROM including the Orcad schematics two software demo projects and Verilog source for the CPLD with other related documents to enable rapid custom development Some guidance how to enhance and customize the design with additional MIL STD terminals ARINC 429 protocol IC s Discrete to Digital devices and memory was provided For questions regarding this design contact Holt and for support on the PLX PEX8311 and PLX software and drivers it is recommended to contact PLX directly using the technical support page on their website References http www holtic com category 351 mil std 1553 aspx http www holtic com category 352 arinc 429 aspx www holtic com category 420 discrete to digital components aspx http www pcisig com home http www plxtech com products expre
12. 16136 Demo selection gt n 16136 Demo selection gt TR Polled RT 3 6361 0202 1717 1818 Message MIU 8688 6663 88084 0505 1919 2020 2121 Message MIW 0000 9595 806806 0707 2121 2222 2323 Polled RT 3 9393 84804 1919 2626 TR Polled RT 3 BBBB 2262 1717 1818 Message 8600 3303 8484 8585 1919 28028 2121 Polled RT 3 9393 6464 1919 2020 Message MIW 0505 806806 0787 2121 2222 2323 6608 8000 ganan 6466 2000 0800 6686 ganan Display 6138 memory 6 xFFFF Display all 6138 system registers GP2 flag for Async demo BC Major Minor Frame demo Menu header 6186 4666 4666 4666 6606 12151515 4666 4666 4666 TimeTag 0000 0707 8888 0905 2323 2424 2525 TimeTag 0000 09809 1616 1111 2525 2626 2727 TimeTag 0000 0707 0808 0909 2323 2424 2525 TimeTag 0000 0909 161 1111 2525 2626 272 HOLT INTEGRATED CIRCUITS 24 Output a value to a specified GPIO port Write to a specified memory location Pulse Master Reset line SR 1918 2626 SA 1212 2828 SA 1910 2626 SR 1212 2828 AN 6130PCle SRT showing Mode Codes received transmitted from an external BC Simple TX Polled Message ode Code 02 ontrol Word 9 1 92 Simple RT Polled Message ode Code 16 ontrol Word Data Word Simple Polled Message od
13. Bheet LOMX0640 1200 2280 FT256 FTN256 uec LCMXO640 1200 2280 FT256 FTN256 VCCIO1 VCCIO5 4 N 4 VCCIOO PT5B PT6F PT9B CLKO p3 NC PB2A PB2A PB5A PB7A PB10E 9 PT5A PT6E PT9A NC PB2B PB2B PB5B PB7B PB10F CLK2 5 ACTIVE NC PT2A PT2C Ne NC PB2C PB2C PB7A PB7C PB10C 5 MTPKTRD NC PT2B PT2D PT9B PT7B PT9D NC PB2D PB2D PB7B PB7D PB10D 5 READY 2 PT6A PT7C PT10A 18 PB2A PB3A PB3A PBGA PB7E PB10A MHO 5 nWAIT PT2B PT3B PT3B PT6B PT7D PT10B CLK1 PB2B PB3B PB3B PB6B PB7F PB10B CLK3 3 5 5 03 NC PT2C PT3C PT6C PT7E PT10C PB2C PB3C PB3C 11 9 5 RT2MC8n NC PT2D PT3D PT6D PT7F PT10D PB2D PB3D PB3D PB6D PB8B PB11D 4 P5 T10 5 IRQn gt PT2E PTAA PTAA PT8C PT8A PT10E 5 PB3A PB4A PB4A PB7C PB8C PB12A FIT PT2F PT4B PT4B PT8D PT8B PT10F PB3B PB4B PB4B PB7D PB8D PB12B 5 AUTOEN gt gt AUTOEN DS PTeC PT3C PTSA PT5C PT8C PT11A 15
14. NO Metal brackets are provided for both full height and low profile PCle cards Use the correct bracket for your PC slot With the PC unpowered plug the card into a PCle x1 x4 8 or x16 card slot and fasten the card with the bracket screw so the card is secure After powering up the PC Windows automatically detects the new hardware and uses the driver installed by the PLX SDK installation After the driver is installed launch the PCle6130Test application exe by double clicking on the file located in the Holt HI 6130 Demo folder on the desktop A menu will be displayed showing sets of numbers 1 though x The Holt card typically appears as the first item 1 with 9056 10b5 b xx s xx f xx Enter 1 and press Enter HOLT INTEGRATED CIRCUITS 3 AN 6130PCle The main menu of commands will appear below 2bug PCle6130Tes 6x6608 6x6668 0 0007 HAHA 8000 0000 HAHA HAHA 6606 HAHA x6G6F 6606 HAHA 4186 AOAO HAHA 6066 6618 6x8616 8x8017 HAHO HONO ANOA 6618 ANHA 6806 6x0618 x G1F 1 0 6466 AHAA HAHA HAHA 6606 HAHA 6x6626 0x808027 2000 4606 HAHA AHAHA 6666 0 0028 xAA2F AHHA H800 HAHO ANAA 6666 BOBO 6x6636 0 32 AAAA HAHA HAHA AHHA 6066 HAHA 0 0038 Gx 3F BACH AHHA AHHA HAHO AHAA 6806 4 0 004 7 11715174 HHOO 71515174 HOHA ANHA 6606 HAHA 6x6648 6606 ANAO ANHA HAHA AHHA 6666
15. To RT2A0 1 2 lt 7 27 2 sw3 g9Srvezi REMOTE REMOTE T2 2 2 3 TERMINAL 1 TERMINAL 2 T8 2 3 419 ADDRESS ADDRESS T4 HT2M 519 nECS R72_p ppg 10K 1348 SMD 6 POS DIP Switch SMD 6 POS DIP Switch T5 RT2AP__6 Holt Integrated Circuits 035010 No 4 SW4 dss015 NO i T6 RTALOCK 7 5 1 veo LE 23351 Madero Mission Viejo CA 92691 www holtic com CT2196LPST ND CT2196LPST ND 17 255 815 EMISO 2 a HE Title TESEN 21855 6 ESCK X TECH Pp ee HI PCle_6130 Interface Header 1x8 GND SI Size Document Number ev 3 TEST BUS MULTI FCTN Un B A EPROM 073016 Date Wednesday September 11 2013 hee 5 of 7 E usp LCMXO640 1200 2280 FT256 FTN256 USE LCMXO640 1200 2280 FT256 FTN256 Ufa VCCIO2 VCCIO3 T D13 NC PR2A PR3A LV_T PR7A PROA PRTIALLV T MCCIOD 0 3 Wecrs GNDLO NC PR2B PR3B LV C PR7B PR9B PR11B LV C VCCIOO 1 GND 1 E13 J12 ELE E42 NC PR9C PR11C 2 VCCIO1 0 GND 3 515 NC PR3B PR4B LV_C NC PR9D PR11D VCCIO1 1 GND 4 F13 J15 NDEs Fi2 NC PR3C PR4C 1
16. 23 3p ABUS 45 Coupling gt BW Limit Fine Invert Probe DC 1M Ohm T HOLT INTEGRATED CIRCUITS 21 AN 6130PCle ee This is the waveform with an external RT responding through a MIL STD 1553 bus coupler The RT amplitude is reduced approximately 75 by bus impedance transformation since RT transmit occurs on a different bus stub b Agilent Technologies THU SEP 12 14 39 19 2013 i 2HACT IVE m ua 3 ABUS 42 Coupling gt BW Limit Fine Invert Probe RT1 Demo If an external RT is not immediately available on chip RT1 can be enabled in the HI 6130 by entering command B The waveform below shows the 6130 responding to BC command with matching address The bus output should be terminated with 70 ohms and the RT response data shows same amplitude as BC since RT transmission occurs on the same bus stub as BC transmission 55 Agilent Technologies THU SEP 12 14 36 52 2013 2 Se S EE 39ABUS i my gt HOLT INTEGRATED CIRCUITS 22 AN 6130PCle RT2 Demo To demonstrate RT2 enter console command C and apply a 1553 command from an external BC with RT address 4 The RT2 will respond SMT Demo To demonstrate the simple bus monitor SMT first issue console command R to reset the HI 6130 to disable the BC or RT s Ent
17. 485 em LED Lena Tic29 080 082 cs 035 7 36 JP5 p LEDS LED6 1 0 10 J o cotuF 0 1UF J 0 001UF J oo0tuE 0 1UF oootuF 2 GPlos ZLED 3 75537 AN 088 AN 039 A 2 3 0 274 OuF 10V 10 10 10uF 10V 8311 1 5V Holt Integrated Circuits PLACE CLOSE TO 8311 R33 R34 54 NOU Place one cap to 1 2K 330 23351 Madero Mission Viejo CA 92691 V each edge connector s xl m 35 PE E mi FE C47 www holtic com 3 3V pin C40 C42 C43 C44 C45 Le itle m Qf O tuF o tuF o tuF f 0 o 47uF 10V HI PCle 6130 PCle bus ira Document Number 2 4 ustom ate Thursday September 19 2013 Bheet 2 of E E
18. HAHA MAINLATCH x24 0780 STATUSINPUTS x28 86FE LATCH2 x2C 0000 Command Menu 1 d or D to Display all 6130 system registers to Output a 1 walking pattern to the LED GPIO port to Display the main Latch Status inputs and Latch2 values to Write a walking 1 pattern to 6138 memory location to Demo transmits three messages to BC Demo A B transmits one message on Bus A and Bus B repeatedly to Write a block of data into 6138 memory space to Uses BC trigger to transmit 3 messages repeatedly every 256ms to Transmit messages and demonstrates interupts to Output this Menu header to Output a value to a specified GPIO port to Issue a MR pulse to the 6138 to Display a 6130 block of memory to Perform a 6130 memory test to Write to a 6130 memory location to Quit demo and release memory A I MuUumSoOXoo od cctN HI6138 Tools selection Press 1 to perform a HI 6130 register memory dump This displays all the HI 6130 system registers from 0x0000 to 0x0047 which initialize to default values after a master reset Default values are specified in the HI 6130 data sheet Notice the word at address 0x0001 contains 0x8000 This is the Master Status and Reset Register 0x0001 in the 6130 The MSB bit 15 high indicates the HI 6130 READY is high which means the device is ready for the host to access the memory and registers in the device See the 6130 data sheet for more details on registers and status
19. InputBuffer 16 hZ Read the 16 inputs assign DataBus oe mux 16 hZ Read the 16 inputs Misc Logic Interrupt MR assign nLINTi InputBuffer 4 amp InputBuffer 5 amp InputBuffer 6 Interrupt pins End of Misc The c delay counter is used to slow down the internal oscillator OSC output to a rate of approximately 0 5 Hz always posedge osc clk or negedge rstn begin if rstn c delay lt 32 h0000 else c delay lt c delay 1 end assign clk c delay 18 endmodule HOLT INTEGRATED CIRCUITS 29 AN 6130PCle Customization This section provides guidelines how to enhance the design This would most likely require a new board design but limited prototyping could be achieved a small add on board using the fourteen CPLD I O s on J12 and J3 header connectors PCle12V 3V3 voltages and ground connections are provided on these connectors When adding circuits using these connections power supply adequacy should be carefully reevaluated especially when using MIL STD 1553 ARINC 429 Holt has several ARINC 429 protocol receivers and transmitters that could be interfaced to the PCle local bus LB and CPLD on this design All the same hardware and software techniques would apply The devices that have a parallel interface would be the easiest to interface on the LB Some suggested ARINC 429 16 bit parallel parts are the HI 3582A HI 3583A and the 1 3584 For a 3 3V
20. PEX8111 and a PCI9056 VenlD Port Rev Type System Management Bus SMBus IDE controller Multimedia device ISA bridge PCI to PCI bridge subtractive dec USB 1 1 Open Host controller PCI to PCl bridge PCI to PCI bridge USB 1 1 Open Host controller USB 2 0 Enhanced Host controller Host bridge Root Complex Host bridge Root Complex Host bridge Root Complex Host bridge Root Complex Host bridge Root Complex Host bridge Root Complex Host bridge Root Complex Host bridge Root Complex PLX PCle 22 PCI bridge 9056 B PLX PCI lt gt Local Bus bridge 8168 10EC 00 Ethernet controller Cancel Set Chip Type HOLT INTEGRATED CIRCUITS 17 AN 6130PCle ee After selecting the Holt card select the LCR button top left to see the Main Control Registers Changes to the LB configuration can be dynamically changed by entering new values from this menu Alternately press the EEPROM button to see the 9056 EEPROM values shown below Notice the Vendor ID is 10B5 This is PLX s vendor ID and must be used with the sub ID 3566 that is assigned to Holt A new end product would require a unique Vendor ID from PCI SIG obtained by becoming a PCI SIG member ora sub ID obtained from PLX For detailed information on these parameters and the PLX API s refer to the PLX SDK user s guide and data sheet on the PEX8311 For the Holt card there is no need to alter any of these values _ PCI Configu
21. V C PL8D PL11D PL14D 9 50 5 67 TP13 10 66 JP6 GREEN TXINHB L3 MODE BUSA INGE Bf 5 6 PLIOA PL12A PL15A LV_T 3 RDn MODE 65 sva mABUS DI M3 y3 42 OE or STR VCC D gt H PL3D PLSD PLeD PL10B PL12B PL15B LV_C ava 38 12160 Buse 64 nBUSA LED9 LED R66 330 R65 1 older Jumper F2 M2 15 MCLK Buse 1 3 1 2 PLSA PL6A PL7A LV_T PL9C PLI2C PLISC NSE SEK iok AWAIT 15 GND VCC H61 Buea JP7 EREN PL5B PL6B PL7B GSR LV_C PL9D PL12D PL15D WAIT or WAIT BUSB gg ATENA a 16 0 E1 J4 nr Ae WE or RT2ENA MEA 45085 ga nBBUS MIRUN E1 PLANPLGC PL7C PLBA PLISA PLIGA LV E 18 RTIADRO RT2ADRO 28 5 Solder Jumper PLAB PLGD PL7D PL8B PL13B PL16B LV_C e RTiA2 fo 1 RT2ADRI 57 RT2A2 CLOSE TO G4 Ri MTSTOFF TP14 EE zg RT1ADR2 RT2ADR2 55 RTAS 0 5 _ NC PLTA PLBA LV T PL11A PL13C PLI6C 55 MR 2 v NC PL7B PL8B LV C PL11B PL13D PL16D 21 55 3V3 1 pad 4 22 RTIADRS BWID 54 15 BCENA G3 K5 GND 28 RTIADR4 A15 RTTENA H3 PL4C PL7C PL8C NC PL14A PL17A LV_T PLLO_T_FB 54 0 14 B PL4D PL7D PL8D NC PL14B PLT7B LV C PLLO FB A12 57 LA2 2514 5 lt 25550 A13 GREEN LEDIO LED d 3 LINTin
22. a Return in this window lists Help page of the commands commands are also documented in the PLX API user manual and some examples are provided in the PLX PEX8311 RDK Hardware Reference Manual HOLT INTEGRATED CIRCUITS 18 AN 6130PCle C Holt HI 6130 PCIe API Demo using Holt s high level API library The HI 6130 PCie API demo program demonstrates Holt s high level API software library The demo consists of menu commands prompted on the console for demonstrating the BC RT1 RT2 SMT and IMT Copy the zipped project folder from the CD ROM to the desktop and unzip the folder there Copy the unzipped project folder to the PLX SDK samples folder PIx PIxSdk Samples The _HI 6130 PCle demo will typically have a version number at the end of the folder name to indicated program revision The folders should appear like the following screen shot The Holt demo project folders are added in the PLX Samples folder Many of the PLX API examples used in Dslave and LocalToPcilnt were used in the Holt projects It s a good idea to review these two projects when first becoming familiar with the PLX APs These PLX projects do not run on the Holt PCle card because the LB memory spaces are defined differently Plx PlxSdk Samples folder File Edit View Tools Help Organize v Include in library Share with v 28 Documents Name Music Pictures E Videos _HI 6130 PCIe API Demo _PCle6130 test Ap
23. b0 reset timer end end else if counter 3 LEDRD lt 1 51 turn off led else counter counter 1 end always posedge c_delay 18 or negedge WRn begin if WRn begin if add L 7 6130 only if 6130 begin LEDWR lt 1 bO Turn on led counter2 6 b0 reset timer end end else if counter2 3 LEDWR lt 1 b1 turn off led else counter2 counter2 41 end Latched 16 GPIO S For Latch outputs always 8 posedge WRn or negedge begin if rstn Latch lt 16 b0001000000110000 Defaults LED1 On low TXINHA TXINHB off else if add L LatchAddress latches decode Latch lt DataBus dbus end For Latch2 outputs always 8 posedge WRn or negedge rstn begin if rstn Latch2 lt 16 h002A Defaults all low 00A5 for testing only else if L Latch2Address latches decode Latch2 lt DataBus dbus end Rose se Read Input Buffers or Latches 16 GPIO s always begin if RDn add L InputsAddress 1 1 turn on buffer else if RDn amp add L LatchAddress oe 1 bl turn on buffer else if RDn 6 add L Latch2Address oe 1 bl turn on buffer HOLT INTEGRATED CIRCUITS 28 AN 6130PCle else oe 1 b0 turn off buffer end assign testpoint oe leave as pin for debugging later change to reg assign DataBus oe
24. bit definitions 6130 bus controller is initialized with several predefined messages Press 5 to command the BC to transmit three commands messages to RT address 3 Message 1 is a Receive command with 32 data words to subaddress SA1 on Bus A Message 2 is a Transmit command with 32 data words to SA1 on Bus B and Message 3 is a Receive command with 32 data words to SA1 on Bus A HOLT INTEGRATED CIRCUITS 4 AN 6130PCle If a separate RT terminal other RT capable MIL STD 1553 test equipment is set for RT address 3 and connected to the bus through a suitable bus coupler the message responses can be monitored The program outputs BC data blocks BC instruction lists and HI 6130 system registers to the console after each transmission To view the transmissions on an oscilloscope trigger rising edge on the ACTIVE test point on the top left side of the card put another scope probe on the ABBUS test point Use a small clip lead to bring this signal up to make it accessible to the scope probe If no external RT or test equipment is connected to the bus then use a 70 ohm termination resistor on the cable output or the signal will be distorted when viewed with the oscilloscope Press 8 to command the BC to transmit three messages repeatedly to RT address 3 Messages 1 and 3 are routed to the Bus A connector and message 2 is routed to the Bus B connector During transmissions LEDs 10 and 11 on the top edge
25. only solution use the HI 3584A with a 3 3V single supply rail line driver such as the HI 8596 or the HI 8597 which includes built in Level 3 lightning protection The following block diagram shows an interface for two ARINC 429 receivers and one transmitter powered by a single 3 3V supply meeting DO 160 Level 3 lightning protection The 1MHz CLK input to the HI 3584A can be supplied directly by the CPLD or optionally by an external oscillator module Refer to the HI 3584A HI 8597 data sheets and AN 3582A application note for more information on these ARINC 429 devices Contact Holt sales for other recommendations Existing circuits 15K X4 Data LD15 LDO TAE RECEIVER 1 8311 RECEIVER 2 test Holt E i 31 ES HI 3584A 15 LLL sa ARINC 429 25 cep RSR Dual Receiver SPARE 1 0 bI One Transmitter from U1 nd Hi 8597 01 2 Line Driver with TRANSMITTER 1 3 Lightning Protection 5 CLK 1MHz HOLT INTEGRATED CIRCUITS 30 AN 6130PCle Discrete to Digital I O Sensing Discrete to Digital sensing capability can easily be added to this design using the Holt 8425 8426 8430 or 8431 parts These also include either four high side or low side output drivers The devices feature adjustable voltage thresholds and wetting currents on the inputs and over current fau
26. or power gnd planes under T1 amp T2 T T TPg RED TP10 PM DB2791S blastelr oe U8B LCMXO640 1200 2280 FT256 FTN256 gt on 5 fo 9 TP9 BLK Es VCCIO7 VCCIO6 s TS 565 gb e nABUS 419 E5 NC PL2A PL2A PLL1T_FB PL6A PLOA PL14A LV_T 5 LA26 3 EE SB Ha 8 pad 3 BLASTn 25 7 NC PL2B PLB PLLIC FB PL6B PL9B PL11B LV_C LA27 3 gt o 2 2 4 BBUS 3 H PL7C PLSC PLIIC 25 200 BED 19 3 5 2 2 NC PL3B PL3B LV C PL7D PL9D PL11D 11 o 1 5 865558899994 e iB BOTRIG PLSA PLSC PLSC PLLIT IN PLGC PLIOA PLI2A LV LA28 3 2568599 amp amp 92 1 nBBUS F4 1 LA29 20 OFarsse SG PL3B PLSD PLSD PLL1C PL6D PL10B PL12B LV_C LA29 3 1 5 52149455 DB9F Loc E3 K2 EECOPY 2 x 01 74 150 R63 PL2C PL4A PL4A LV_T PLOA PL10C PL12C 12 TEST 3 GND 1 A PL2D PL4B PL4B LV_C PL9B PL10D PL12D 4 BCTRIG WPOL 72 3v3 C3 L1 5 012 OK AT RAMEDG C2 NO PLAC PLAC PL7A PL11A PLI3A LV_T qq LAST LA30 3 5 013 BENDI TEST NC PL4D PL4D PL7B PL11B PL13B LV_C LA31 3 014 2 015 RT1LOCK E RUD ee 250 5 E BI PLAA PLBA PLBA LV T TSALL PLBC PLMC PLI4C HSI lt lt LRESETn 3 RAMEDC MTSTOFF pi PL2B PLSB PLSB L
27. output reg 15 0 Latch 16 latched outputs output reg 15 0 Latch2 2nd set of latches output nLINTi Interrupt output to PLX Wires Constants define H6130 8 b11111110 6130 address decode address define LatchAddress 8 b11111101 Latches output decode address define InputsAddress 8 b11111011 Inputs address decode address define Latch2Address 8 b11110111 Inputs address decode address Registers reg 26 0 c_delay reg 7 0 16 reg 0 0 blastq reg 3 0 counter reg 3 0 counter2 reg oe output enable for buffer reads reg 15 0 mux internal bus for muxing readback bus HOLT INTEGRATED CIRCUITS 26 AN 6130PCle Get IC clk and reset GSR GSR INST GSR rstn Reset occurs when argument is active low OSCC OSCC_1 05 8 1 Logic assign LED 3 0 add 1 copy decoder outputs to LEDs for test assign LED 4 blast copy of blast output assign LED 5 WRn copy WRn to output assign LED 6 RDn copy WRn to output assign LED 7 copy clock to output End of test assign decoderOutput add L assign TP13 ads 3 8 Address Decoders alwaysQ case add 65001000 add L H6130 ledl CS20 6130 6 b001001 add L LatchAddress led2 CS24 Output latches 6 b001010 add L InputsAddress led3 CS28 Inputs 6 b001011 add 1 Latch2Address led4 CS2C Latch2
28. vss VDD3 3 vss VDD3 3 vss VDD3 3 vss E qaar au VDD33 VSS Clock Circuit a ETN VDD3 3 vss 0014 O tuF 0 01uF VDD3 3 vss VDD3 3 vss JV VDD3 3 1 VDD3 3 1 4 C54 OE vocc a 100 50 0MHz x 0 00 D D D CD 00 00 00 00 00 00 00 2 00 00 00 CD D D 00 2 00 00 00 00 00 00 00 00 00 000 O0 2 GD OUT 3 d 2 gt LCLK 4 gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt C57 C58 R54 33 oir 1 2 MOK PLACE CLOSE TO 8311 8311 3 3V 8311 2 5V PLACE CLOSE TO 8311 U7 2 5 R55 9 9 9 LT1963AEST 2 5 9 7 4 1A max 1 2 8511228 4 41 vin Hoy 0OHM C59 C60 C6 C 2 064 C65 cee ces ceo en o cz 4 ez 08 o 6 C81 z C80 LED7 LR 7 JK A LA LA c79 C82 0 010 O tuF 0 01uF O O1uF O tuF OOtuF O tuF 0 014 O tuF O 0uF 0 010 O tuF 0 010 O OtuF o 1uF 0 01 O tuF gt 7 Holt Integr ircui 1 1 1 il 1 1 10uF 10V S 10uF 10 OotwF LED olt Integrated Circuits 0 1uF 23351 Madero Mission Viejo CA 92691 www holtic com WU X R56 100 HI PCle 6130 Local bus pes Document Number ev ustom A ate Tuesday August 20 2013 3 of ri
29. 3 2 Header 1x8 Male 0 1 Pitch J2 J5 1012E 08 ND Sullins PEC36SAAN 34 2 Header 1x10 Male 0 1 Pitch J3 J12 1012E 10 ND Sullins PEC36SAAN 35 1 Osc 50MHz 25ppm 3 3V SMD 5x7mm 1 535 10087 1 ND Abracon ASV 50 000MHZ E T 36 11 Green 0805 LED1 LED11 160 1179 1 ND Lite On LTST C170GKT 37 1 Diode Schottky 40V 0 3A SOT23 D1 497 12131 1 ND ST BAT54FILMY 38 1 Switch Tactile SPST NO 0 02A 15V swi P12943SCT ND Panasonic EVQ Q2K03W 39 3 DIP Switch 6 Pos Half Pitch SMD SW2 SW3 SW4 CT2186LPST ND CTS 218 6LPST 40 2 Test Point Red 0 062 hole TP8 TP11 5010K ND eystone 5010 41 3 l est Point Black 0 062 hole TP9 TP12 TP32 5011K ND eystone 5011 42 1 Test Point White 0 062 hole TP20 Active 5012K ND eystone 5012 43 4 Point White 0 040 hole TP10 TP13 TP14 TP31 5002K ND eystone 5002 44 2 Test Point 0 040 hole TP2 TP19 N A 45 7 l est Point Pad 1 2 3 4 5 6 7 46 1 Connector DB9F R A Short Body Board Lock J4 A35107 ND TE 1734354 1 47 1 PEX 8311 PCle IC 337BGA 862 8311 66 PLX PEX 8311 AA66BCF Mouser PN 48 1 C PLD 1200LUTs 211 256FTBGA U8 220 1064 ND Lattice 1200 3 2561 49 1 C EEPROM 512 20 MHz 8 SOIC U11 25LC512T I SNCT ND Micro Chip 25LC512T I SN 50 1 C EEPROM 64K 20MHz 8 SOIC u2 AT25640B SSHL T ND Atmel AT25640B SSHL T 51 1 C HI 6130 100 PQFP U9 6130 Holt IC 52 2 Transformer PM DB2791S 2 5T TTA PM DB2791S Holt IC 53 1 Regulator LDO 1 5V 0 25A SOT23 5 LP29
30. 30 OUTPUT LATCHES W READ BACK 16 6130 STATUS INPUTS 16 _ 6130 OUTPUT LATCHES W READ BACK 5 SPARE CHIP SEL S TEST OUTPUTS 9 AN 6130PCle e HI 6130 Functional Block Diagram RT1A4 0 TRO RT1AP MTPKRDY 2 4 0 READY RT2AP ACTIVE BENDI RTMCS RT1LOCK RT2MC8 RT2LOCK MTSTOFF RAMEDC m MCLK 4 INTERNAL 4 WPOL CLOCKS MTTCLK Qj B Qi R WoWE TXINHA 15 i STR or OE Ao LB Address i WAIT or WAIT Data BUSA A15 1 xm D15 0 n BUSA Address lt Data 88 c 5 5 Contrd Li SCK 919 TXINHB e 6 2 5 B BUSB E 86 8 AUTOEN 5 MR lt voce BCENA E BCTRIG LOGIC POWER 44 vocc MTENA RT1ENA 2 ACKIRQ TEST 155 MODE RT2SSF o gt 5 x 0 MOSI OPTIONAL SERIAL EEPROM AUTO CONFIG HOLT INTEGRATED CIRCUITS 12 AN 6130PCle eee Software Two Holt demo programs are provided on the CD ROM PCle6130 test contains a menu of commands to demonstrate reading and writing to the latched O s read and write to HI 6130 memory space and initialize the HI 6130 for BC transmissions The sim
31. 6 399 1082 1 ND Kemet C0603C102K5RACTU 5 20 Ceramic 10nF 10 50V X7R 0603 4 7 13 49 51 57 59 61 63 65 67 399 1091 1 ND Kemet C0603C103K5RACTU 69 71 73 75 077 082 100 110 C111 6 58 Ceramic 100nF 10 50V X7R 0603 C1 C2 C3 C8 C12 C16 C17 C19 C21 C23 399 5089 1 ND Kemet C0603C104K5RACTU C26 C27 C28 C29 C31 C33 C35 C40 C41 C42 C43 C44 C45 C46 C48 C50 C54 C58 C60 C62 C64 C66 C68 C72 C74 C76 C78 C81 C83 C85 C87 C88 C89 C91 C92 C94 C95 C98 C101 C102 C103 C104 C105 C106 7 2 Capacitor Ceramic 1uF 10V 1096 X7R 0603 C5 C15 399 9449 1 ND Kemet T491A105K010AT 8 1 Capacitor Ceramic 4 7uF 10V 1096 X5R 0603 C113 399 5503 1 ND Kemet C0603C475K8PACTU 9 2 Capacitor Tantalum 4 7uF 1096 10V Size A C53 C86 399 3699 1 ND Kemet T491A475M016AT 10 12 Capacitor Tantalum 10uF 10V 10 Size A C6 C10 C14 C37 C38 C39 C79 C80 C90 C93 C96 399 3684 1 ND Kemet T491A106K010AT C99 11 3 Capacitor Tantalum 10uF 16V 1096 Size A C11 025 C97 399 3687 1 ND Kemet 491 106 016 12 2 Capacitor 47uF 1096 6 3V Tantalum Low ESR SMD C C14 C47 495 1543 1 ND Kemet T495C476K016ZTE300 13 1 Capacitor 68uF 10 6 3V Tantalum Low ESR SMD C C84 495 1507 1 ND Kemet T495C107K006ZTE150 14 1 Resistor Array 270 Ohm 4 Res 1206 742C083271JPCT ND CTS 742 083271 15 13 Resistor Array 10K Ohm 4 Res 1206 RN2 RN3 RN4 RN5 RN6 RN7 RN8 RN9 RN10 RN1 742C083103JPCT ND CTS 742C0
32. 6130 system registers Async Demo GP2 flag for Async demo BC Major Minor Frame demo SMT demo IMT demo RT demo RT2 demo put a value to a specified GPIO port Write to a specified memory location Pulse Master Reset line quit demo Out put this Menu header 6x8667 AHAHA 8606 NOHA 6666 HAHA 0180 6666 8666 HONA 1E66 6466 HONA 6066 2008 0600 6666 4866 AHHA 6666 8666 AHNA paca HAHA AONA 6666 8608 004 8666 8606 HAHA HI6130 Demo selection gt Press D to display the HI 6130 system registers with labels followed by the same registers values formatted by beginning and end addressed rows followed by eight register values HOLT INTEGRATED CIRCUITS 20 AN 6130PCle En BC Demo Press A to run the BC Async demo The BC will begin transmitting messages on bus A to RT 3 When the HI 6130 transacts a message the ACTIVE test point on the card will pulse high during the message To view the messages on a scope trigger on the rising edge of this signal with one probe and view the bus signal on another probe at the ABUS test point This waveform shows no RT responding viewed at the ABUS test point The ABUS output should be terminated with 70 ohms or the waveforms will appear distorted The double messages occur because one retry upon message failure is enabled in each BC Message Block Agilent Technologies THU SEP 12 14 38 25 2013 a
33. 83103JP 1 RN12 RN13 RN14 16 1 Resistor 0 0 Ohm 1 10W 0603 R23 DNP Panasonic ERJ SGEYOROOV 17 1 Resistor Provision 596 1 10W 0603 R50 DNP 18 1 Resistor 4 7K ohm 596 1 10W 0603 R41 DNP Panasonic ERJ 3GEYJ472V 19 2 Resistor 10K Ohm 5 1 10W 0603 R35 R36 DNP Panasonic ERJ 3GEYJ103V 20 2 Resistor 0 0 Ohms 1 8W 0805 R25 R71 DNP Panasonic ERJ 6GEYOROOV 21 5 Resistor 0 0 Ohms 1 8W 0805 R2 R24 R28 R55 R67 PO 0ACT ND Panasonic ERJ 6GEYOROOV 22 8 Resistor 0 0 Ohm 1 10W 0603 R1 R9 R10 R11 R37 R38 R47 R52 P0 0GCT ND Panasonic ERJ SGEYOROOV 23 3 Resistor 33 Ohm 596 1 10W 0603 R53 R54 R70 P33GCT ND Panasonic ERJ 3GEYJ330V 24 5 Resistor 100 Ohm 5 1 10W 0603 R29 R30 R31 R32 R56 P100GCT ND Panasonic ERJ 3GEYJ101V 25 5 Resistor 330 ohm 5 1 10W 0603 R34 R64 R66 R68 R69 P330GCT ND Panasonic ERJ 3GEYJ331V 26 10 _ Resistor 1K Ohm 5 1 10W 0603 R3 R6 R8 R15 R16 R17 R18 R19 R20 R42 P1 0KGCT ND Pansonic ERJ 3GEYJ102V 27 1 Resistor 1 2K Ohm 5 1 10W 0603 R33 P1 2KGCT ND Pansonic ERJ 3GEYJ122V 28 21 Resistor 10K Ohm 5 1 10W 0603 R4 R5 R12 R21 R22 R26 R27 R39 R40 R43 R44 R Panasonic ERJ 3GEYJ103V 45 R46 R48 R49 R51 R57 R63 R65 R72 R133 29 4 1x3 Male 0 1 Pitch JP2 JP3 JP4 JP5 1012E 03 ND Sullins PEC36SAAN 30 4 Shunt 1x2 0 1 Pitch JP2 JP3 JP4 JP5 A26227 ND TE 382811 6 31 3 Header 1x2 Male 0 1 Pitch JP1 J14 15 1012E 02 ND Sullins PEC36SAAN 32 1 Header 1x6 Male 0 1 Pitch J1 1012E 06 ND Sullins PEC36SAAN 3
34. 921M5 1 5 NOPBCT ND LP29921M5 1 5 NOPB 54 1 Regulator 3 3V 3A DDPAK TO 263 4 U10 LM10851S 3 3 NOPB ND TI LM10851SX 3 3 NOPB 55 1 Converter DC DC 1A 5V Out SIP Vertical 04 945 1038 ND Recom Power R 785 0 1 0 56 1 C Reg LDO 2 5V 1 5A SOT223 07 LT1963AEST 2 5 PBF ND Linear LT1963AEST 2 5 PBF 57 1 Reset IC 2 93V SOT 23 5L 05 MAX6306UK29DS3 TCT ND MAX6306UK29D3 T 58 1 C 3 wire EEPROM 2KBb 8 SOIC 06 AT93C56B SSHM TCT ND Atmel AT93C56B SSHM T 59 1 Low Profile PCle Bracket w DB 9 Opening N A Low Bracket Star Mfg Star Manufacturing 60 1 Profile PCle Bracket w DB 9 Opening N A High Bracket Star Mfg Star Manufacturing 61 2 Triax Connector w Bend Relief Spring Plug Crimp N A Mouser 530 PL75 29 Trompeter Emerson PL75 29 63 2 TwoGft in Length Cable N A Mouser 530 TWC 78 1 500ft TWC 78 1 500ft Reel 64 1 Conn DB9 Male Solder Cup Nickel w Gold Plated Pins N A 209ME ND Norcomp 171 009 103L001 65 1 Backshell DB9 Die Cast Black Chrmt N A 970 09BCA ND Norcomp 970 009 040R01 1 REVISION HISTORY P N Rev Date Description of Change AN 6130PCle NEW 09 27 2013 Release AN 6130PCle A 06 30 2014 Revise for API demo program changes AN 6130PCle B 03 04 2015 Update board photo on page 1
35. LT INTEGRATED CIRCUITS 31 AN 6130PCle SSS For new custom designs the user should be aware of the PCle limitations on the maximum allowable current and power dissipation which vary depending on card size full height vs low profile and slot type used x1 through x16 Clocks A single 50MHz oscillator module is shared between the PEX8311 LB CPLD and 6130 The LB can be clocked up to 66MHz to achieve faster bus performance which might be desirable in a more complex design The 6130 must always be clocked at 50MHz so an additional oscillator would be needed If running the LB at 66MHz the number of wait states in the PLX LB EPROM registers would need to be increased to compensate for the faster clock The LB and the CPLD must use the same clock to generate the synchronized strobe signals internal to the CPLD and the CSn RDn WRn strobe signals to the HI 6130 For a faster LB use up to 66MHz for the LB clock input of the PEX8311 and CPLD and use a separate 50MHz clock for the 6130 Additional memory Adding additional on board memory is possible with some moderate design effort Connect the address and data bus directly to the LB signals of the PEX8311 and assign the required number of control signals for the memory by using some spare CPLD pins and modify the Verilog accordingly Configure the LB EEPROM Space registers for the desired memory space number of wait state and bus width type
36. R W 0x2000 0000 0x2000 07FFF 32K Words Main Output Control Latches R W 0x2400 0000 BIT 15 14 13 12 11 10 9 8 FIELD TEST EECOPY LED2 LED1 RT2ENA RTIENA BCENA RESET 0 0 0 1 0 0 0 0 BIT 7 6 5 4 3 2 1 0 FIELD MR MTRUN TXINHB RAMDEC TP31 BCTRING RESET 0 0 1 1 0 0 0 0 DO BCTRIG HI 6130 input Rising edge triggers the BC to execute next Opcode instruction Usually used to start BC transmissions D1 ACKIRQ HI 6130 input D2 TP31 CPLD spare pin D3 RAMEDC HI 6130 Error detection correction input Set Low for this program D4 TXINHB HI 6130 Bus B inhibit input D5 TXINHA 6130 Bus A inhibit input D6 MTRUN 6130 MT enable input D7 MR HI 6130 Master Reset input D8 BCENA HI 6130 BC enable input D9 1 6130 enable input D10 RT2ENA 6130 RT2 enable input D11 LED1 General purpose LED LED10 on board On low at power up D12 LED2 General purpose LED LED11 on board Off high at power up D13 K3 Not used but brought out to a pad on the PCB from the CPLD D14 EECOPY 6130 EECOPY input D15 TEST HI 6130 TEST input Must be set Low for normal operation See data sheet for Test Mode details HOLT INTEGRATED CIRCUITS 8 AN 6130PCle Status Inputs R only 0x2800 0000
37. T1 RT address input lock input D2 MTSTOFF HI 6130 memory test disable Set low by internal pull down resistor D3 RT2SSF RT2 Subsystem Fail input D4 RT2LOCK RT2 RT address input lock input D5 D15 N A Not defined HOLT INTEGRATED CIRCUITS 9 AN 6130PCle U The CPLD is a Lattice LCMX01200 256 BGA device and is programmed through a JTAG port on J2 The Verilog source code listing is included in this document and the actual Verilog source and constraint files are included in the Lattice Diamond tool project included on the CD ROM The CPLD block diagram is shown below The CPLD has an internal reset and RC clock generator which is used in Verilog design Up to 16 wait states can be programmed in the LB timing controlled by the PEX8311 for the HI 6130 output latches and input buffers the CPLD The value of 14 is programmed in the LB EEPROM U6 At 50MHz the access time is 1414 or 1 50MHz 15 300ns This meets the worst case 240ns timing requirement of the HI 6130 for non sequential read cycles with 60ns of margin The LB BLASTn signal is used by the CPLD to time when to de assert the CSn RWn or WRn signals to the 6130 and the internal latches and input buffers The ADSn signal from the LB is used by the CPLD to start the bus cycle A faster access time could have been used for the GPIO but was kept the same to simplify the design See the PEX8311 data book for the LB signal description
38. TAS Yie A8 GND PMEINn 1 8 LAB 1 8 10 Wis 149 ccss b217 CCSn USERo LLOCKon 2 7 19 2 7 LATI Vie A10 AT93C56B USER LLOCKin 3 6 LA20 3 6 018 Ea LINTi amp LINTin 5 INESE a tat a S Wi5 13 LSERRS 742 08 3 103 ri LA14 BREQi TATS yia 15 BREGo RN12 RN13 wig LA16 DMPAF EOT DREQon 1 8 LA22 1 8 LATS 17 BIGENDY DREQIN 2 7 23 2 7 TATS wig 18 USERo LLOCKo DACKOn 3 6 LA24 73 6 TA20 Viz 5319 USERILLOCKW DACKin 4 5 TA25 4 5 7459 Wig LA20 DREQO 22 LA2t DREQUE 742 08 3 103 J XX 742 08 3 103 J XX LA23 LAz2 DACKO DACKin LA24 Vii LA23 BD SELn R42 iK RN14 S ee TA25 10 11 28 His MODEO LA26 1 8 LA26 20 MODET R43 10K LA27 2 7 LA27 Y9 MODE BREQo R44 10K 3 6 28 We 27 EESK 3 3VCC 4 5 29 ven HAS 1820 EEDVEEDO LHOLDA R45 10K WB 1 429 aa 0 LHOLD 742 08 3 103 1 yr LAS PEX83111 LHOLD R47 LHOLDA LA31 BD_SEL BD SEL R48 10K LA28 R49 10K LBEO Wi9 READYn R50 NC LA29 R51 LBEO PMEIN ik en TP2 5 LBE1 lt lt LBE1 PMEOUT LBE2 LBE3 vss vss SURG 248 cLkouT vss CLKIN vss vss adanv X5 5 vss 5 VDD2 5 vss VDD2 5 vss VDD2 5 vss VDD2 5 vss VDD2 5 vss gat asy VDD2 5 vss vss 816 vss Jie VDD3 8 vss 16 1 VDD3 3 vss VDD3 3 vss
39. ane sadnanga e NC PB11D PB16D Em A15 PB 640 1200 2280 58 NC PT 1C PT16C HBTs mm Pin name sequence NC PT11D PT16D I Os in Bank 5 OQ I Os in Bank 4 640 1200 2280 for 01200 1818 for 2280 I Os in Bank 1 Provisonal 1 Os in Bank 0 for X02280 for 01200 fee mM 711111 2 FB4 oE Kroc 2 GND ioco lt Jeo S TP30 SW2 e 593 HEADER 10 SW4 _ J12 SW5 aus J14 015 1 1 SW2 DIP SWITCHES 3 2 2 1 EINS SMD 6 POS DIP Switch header_1x2Male pins ie header_1x2Male pins CT2196LPST ND 3v3 Default SW2 position 6 AUTOEN Holt Integrated Circuits www holtic com should be Open UP 23351 Madero Mission Viejo CA 92691 Title HI 6130 Status Inputs JTAG Document Number Date Thursday September 19 2013 Bheet 4 of 7 A B D E c 3 4 LD 15 0 gt PCB No traces
40. e Code 17 ontrol Word x1811 Data Word x2517 Simple Polled Message ode Code 19 ontrol Word x1C13 Data Word x1119 HOLT INTEGRATED CIRCUITS 25 AN 6130PCle CPLD Verilog Source A current copy of this source file is included in the Verilog source file on the CD ROM Holt PCI 6130 interface module count rstn clk LED clk clk and reset pins testpoint test output add decoderOutput address decoder lclk blast blast q ads lwr RDn WRn Read Write stobes LEDRD LEDWR LED flashers Latch 16 latched outputs DataBus Data bus In Out 16 InputBuffer Inputs 16 nLINTi Interrupt output pin Latch2 TP13 Misc Signals input rstn output output 7 0 LED output clk output testpoint Test OE output TP13 Test ADSn Inputs input lclk LCLK 50 MHZ input input blast blast input input 5 0 adg inputs LA31 LA26 6 for decoder input 15 0 InputBuffer 16 status input pins input ads ADS input input lwr LW R input input RT1MC8n RT2MC8n IROn Interrupt inputs InOuts inout 15 0 DataBus 16 In out Data Bus pins Outputs output blast blast output output 4 0 decoderOutput address decoder outputs output reg RDn RD output strobe output reg WRn WR output strobe output reg LEDRD LEDWR LED flashers for 6130 indication
41. er command S to enable the SMT monitor The HI 6130 monitor will monitor the bus and retrieve any valid message and store it in an internal message queue The ACTIVE test point will pulse high upon valid command detection whether or not there is a responding RT or not The source code for these demos is located in the demos c module of the PCle6130 Holt Visual Studio project To learn more about the Holt high level software API s and these demos refer to the Holt software library user s guide Simple RT SRT The Simple RT demo is integrated into the RT1 demo and is enabled by entering console command B The Simple RT detects and displays traffic data on the console for transmit and receive commands for SA1 SA30 and Mode Codes using the Holt API library Optionally use the internal BC to transmit messages to the RT using the BC Major Minor frame demo N The bus connector should be terminated with 75 ohms or connected to a terminated MIL STD 1553 bus coupler When using an external BC don t enable the onboard BC demos or bus conflicts will occur SA30 is used for 1553 data wraparound purposes A SA30 TX command from a BC will cause the RT to transmit a fixed data pattern from a shared TX RX buffer to the BC When a SA30 received command is received from the BC this same shared buffer is used to store the received data words A subsequent TX command transmits the contents of this buffer back to the BC the next time around SA1 transmi
42. hen designing a custom card At the PC add in card sockets the PCle 3 3V supply can vary by 9 and the 12V supply can vary by 8 The HI 6130 is designed to work within 5 voltage tolerance so powering the device directly from the slot 3 3 volt supply will not meet MIL STD 1553 performance characteristics during transmit power supply regulation is inadequate and transient response will most likely not be suitable Actual power rail characteristics will vary widely from computer to computer MIL STD 1553 devices like the 6130 and 6120 draw up to 0 9 during 1553 transmission A two step power conversion is needed The Holt card uses a 12V to 5V DC DC converter to power a 3 3V linear regulator The tightly regulated output of the 3 3V regulator powers the 6130 and CPLD PCle current draw from the 12V rail cannot exceed 0 5A for x1 cards 2 1A for x4 x8 cards or 4 4A for x16 cards For a PCle x1 card like the Holt example the worst case available power from the slot 12V rail is 12V minus 8 x 5A 5 52W The DC DC conversion efficiency is approximately 90 reducing available load capacity from 5 52 to 4 97W Since the final 5V to 3 3V stage uses a linear regulator output current equals regulator input current Thus the maximum output load current is 4 97W 5V 99A The 3 3V regulator can supply 3 27 Watts Use x1 slots for smaller designs and use either x4 x8 or x16 slots for larger designs that require higher power HO
43. his parameter is TRUE the input address is the full address See the PLX API user s manual for descriptions and usage of the API s BAR spaces and other input parameters associated with the PEX8311 and SDK API s Device BAR Space Address Notes 6130 2 0 0 2000 0000 32K word range Output Latches 3 1 0x2400 0000 First location used Inputs 3 1 0x2800 0000 First location used Output Latches 2 3 1 0 2 00 0000 First location used The U6 EEPROM contains configuration data the PEX8311 uses to configure the LB at power up The LB is configured for a 16 bit data bus 14 wait states 5 0 and 5 1 starting addresses ranges and disables the TA Ready input The PCI PLX sub ID 3566 is also programmed into this EEPROM This sub ID is assigned by PLX exclusively for the Holt demo board The PlxMon utility is launched from the Windows start menu or by double clicking on the application found in the Plx Bin folder The PIxMon utility opening screen is shown below HOLT INTEGRATED CIRCUITS 16 AN 6130PCle File Command Registers wm Vy B Establish Serial Connection Xy Iq Pig PA Np Active Pane Lower Current Mode PLX M Select the Holt PCle card from the Command menu or press the green icon button on the left and select the device with Dev ID 9056 and Ven ID 10B5 The PEX8311 consists internally of a
44. iTest 4 DSlave mc ut 7 Snie d DSlave BypassApi amp eMachines C Launch the program by either double clicking the executable application PCleHolt contained in the Visual Studio project Release sub folder or launch Visual Studio and open the project to run the program in debug mode To run the project in debug mode make sure the debug configuration is selected at the top Sometimes it may be necessary to perform a project clean by selecting Clean PCle6130Holt from the BUILD pull down menu After rebuilding the project some warnings may appear in the Output window which can be ignored but there should be no critical errors preventing the debugger from running the project A menu will be displayed showing sets of numbers 1 though x The Holt card typically appears as the first item 1 with 9056 10b5 b xx s xx f xx Enter 1 and press Enter HOLT INTEGRATED CIRCUITS 19 AN 6130PCle The main menu will appear below BC On Press Press Press Press Press Press Press Press Press a 5 HIGISO PCIe 1_0 Debug PCle6130Holt exe Holt Integrated Circuits Hi 6138 PClIe Project Rev 1 8 Compiled Date Time SMT On 1 On RT On to to to to to to to to to to 6x8088 1 9 0918 0 0020 6x8828 6x8638 6x8838 6x6646 6x8048 Dis run set run Out play all
45. lt protection on the outputs These devices use parallel I O for input and outputs signals which can be driven by some of the spare CPLD pins The 8425 and 8430 are the newest members of the Discrete to digital family others are also available Contact Holt sales for other recommendations EBR 1553 BC MT RT Terminals The HI 6140 could replace the HI 6130 to achieve 10 Mbit sec Extended Bit Rate MIL STD 1553B terminal communication The 6140 uses the same 16 bit parallel bus and 50MHz clock input as the 6130 and has a very similar register set and architecture Holt 4853 slew rate controlled RS 485 transceivers are used to drive the EBR bus This change would require a revised board design not an add on board See the HI 6140 product page on Holt s website for data sheets and application notes or contact Holt sales for recommendations MIL STD 1553 Terminal Options In addition to the HI 6130 the HI 6120 is a good candidate if only a single RT is required The HI 6120 shares the same 16 bit parallel bus interface and 50MHz clock input as the HI 6130 with a similar pin out The RT operation of the HI 6120 is nearly the same as the HI 6130 but does have some differences in the registers and pin outs The HI 6120 is simpler to use and cost less than the HI 6130 This change would require a revised board design not an add on board Power supplies PCle computer add in card slots have limitations which should be considered w
46. nsformer routing HOLT INTEGRATED CIRCUITS 15 AN 6130PCle PLX API s PLX API s use a unique input parameter BAR to specify which LB memory space to read and write from BAR stands for Base Address Register BAR 0 and BAR 1 are reserved for the upstream PCle BAR 2 and BAR 3 are used to provide separate memory spaces on the LB side Bar 2 uses Space 0 and BAR 3 uses Space 1 The Space 0 and Space 1 PEX8311 registers are loaded with the desired starting BAR addresses at power up from the contents of the U6 EEPROM Space O is reserved exclusively for the 6130 64KB memory space and is set to starting address 0x2000 0000 Space 1 is shared and modified on the fly in the API function calls to read write to the output latches and reading the input status buffers The latches are used to set the state of various inputs to the HI 6130 and the inputs are used to read 6130 status and DIP switches The Holt demo code includes several functions to read and write to the HI 6130 memory space latches and input status buffers The API functions are located in HI6130 c These functions use a PLX to access the LB with either PlxPci_PciBarSpaceRead or PciBarSpaceWrite One of the input parameters to these API s is bOffsetAsLocalAddr this parameter controls how the API uses the U32 offset address If OffsetAsLocalAddr is FALSE the input address is an offset address from the Space x value If t
47. of the card count in a binary fashion according to the message sent Two other LEDs flash when the HI 6130 is read or written by the program to provide a visual aid during software development LED 8 flashes when a read occurs and LED 9 flashes when a write occurs aan Press q to quit This is the end of the Quick Start Guide section HOLT INTEGRATED CIRCUITS 5 AN 6130PCle Hardware The Holt HI 6130 PCle interface card consists of three main IC components shown below in the Block Diagram The PEX 8311 is a PCI Express to Generic Local Bus bridge and provides the interface between the PCle slot and the local bus LB A CPLD translates the LB signals into CSn RDn and WRn strobe signals for the HI 6130 timings The CPLD also provides other GPIO and glue logic A shared single 50MHz oscillator module provides the clock for the PEX8311 local bus CPLD and the 6130 HI 6130 must be clocked at 50M Hz Address LA15 LA1 LBE1 Data LD15 LDO v 12 6130 WR gt 1 2 5 6130 RD L ep f ges EXER 9 Pin PEX 8311 AWR 6130 2 PCle Interface nts Conn o Ctl XFER LED10 CPLD wd m 5 E 2 gt lt 12 Prog 55 1 __ EEPROM Status no g gt
48. output latches 6 b001100 add L 8 b11101111 led5 Spare CS default t add i 8 bil1111111 defaul all OFF endcase 16 bit 3 to 1 multiplexer alwaysQ begin case add 1 LatchAddress mux Latch First latches routed to mux InputsAddress mux InputBuffer Status inputs 6130 routed to mux Latch2Address mux Latch2 Second set of latches routed to mux default mux 16 hFFFF default endcase end RD RW 6130CS Stobe generation generate delayed blast signal used to clear RD WR always posedge lclk begin if blast blastq lt 1 bl set high during reset else blastq lt 1 b0 set high during reset end assign blast blastq leave as output pin for possible debugging later generate bracketed RDn stobe always posedge lclk or negedge blastq begin if blastq RDn lt 1 bl set rd high else begin if lwr amp amp ads RDn lt 1 b0 set rd low end end generate bracketed WRn stobe always posedge lclk or negedge blastq begin if blastq WRn lt 1 bl set wr high if blast_q 0 else begin HOLT INTEGRATED CIRCUITS 27 AN 6130PCle SSS EE if lwr amp amp ads WRn lt 1 b0 set wr low end end D E 6130 RD amp WR LED flashers always posedge delay 18 or negedge RDn begin if RDn begin if add L H6130 only if 6130 begin LEDRD lt 1 b0 j Turn on led counter 6
49. ple BC demo periodically transmits 3 types of messages This demo was demonstrated in the Quick Start Guide section The 6130 demo is more complex The main purpose of this demo is to demonstrate Holt s library This demo program demonstrates how to use Holt s API library to initialize the 6130 for RT or MT operations Both demo projects are built using Microsoft Visual Studio 2012 For other compilers the user needs to port the software project All the API s and low level drivers supporting the HI 6130 and GPIOs are contained in module HI6130 c with accompanying header file HI6130 h To rebuild these projects the following three items are needed e Holt demo projects contained on the CD ROM e Microsoft Visual Studio 2012 Not Provided e PLX SDK 7 00 On PLX website The 4 layer demo software is shown below Application Layer Demo software HOLT API s PLX API s PLX DEVICE DRIVERS PLX SDK installation To modify the demo programs the PLX SDK must first be installed so that the Holt projects can be added to the SDK samples folder To develop custom software applications for this card the SDK from PLX is required Download the SDK from the link below PLX requires user registration to download their SDK by filling out their online registration and obtaining a login and password Holt is not authorized to provide the PLX SDK package directly to customers At the time this document wa
50. ration Registers Device VendorID 00 90561085 Class Code Rev 04 O6800044 Hot Swap 54 00004206 gt Subsystem ID 44 35661085 Lat Int Pin amp Line 08 00000100 Capabilities 501 74024801 gt PM Ctrl Status 60 00000000 gt Local Configuration Registers Space 0 Range 14 0000 VPD Boundary Endian Desc 20 20308500 gt Space 0 Remap 18 20000001 Direct Master gt PCI Range 30 00000000 Expansion ROM Range 24 00000000 Direct Master Memory Local Base Addr 34 60000000 Expansion ROM Remap 28 00000000 Direct Master 1 0 Local Base Addr 38 50000000 Space 0 ROM Descriptor 2 43430085 gt Direct Master gt PCI Memory Remap 3 00000000 gt Space 1 Range 48 FFFFFFFO gt Direct Master gt PCI 1 0 PCI Configuration 40 00000000 gt Space 1 Remap 24000001 Mailbox 0 0 00000000 Space 1 Descriptor 50 00000185 gt Mailbox 1 10 00000000 Arbitration 1 01200000 gt PCI Arbiter Control 58 00000000 Load File Display Offsets from Serial EEPROM Base 7 Close Refresh i PLX Chip Register Base Saveds On the bottom of the PlxMon screen is a console window where a menu of commands allow reading and writing to LB memory spaces These are useful during initial hardware checkout to confirm LB configurations Pressing followed by
51. s and timings A large portion of the CPLD is unused with sufficient room for custom expansion A Lattice USB programming cable PN PN USBN 2A is required to reprogram the CPLD but is NOT provided by Holt This is only needed if the end user wishes to alter the Verilog code and reprogram the CPLD Using the Lattice Diamond CPLD development software is beyond the scope of this document but many tutorials are built into Lattice Diamond software which is available for download from their website When the board powers up only LED10 is On This is a convenient way to determine if the CPLD has been programmed The next page shows a block diagram of the CPLD HOLT INTEGRATED CIRCUITS 10 AN 6130PCle CPLD Functional Block Diagram PCle Local Bus Interface LA31 LA26 LD15 LDO 1051000 H Internal Reset Q 20MHz RC Osc Local bus Address decoder 6130 0x20xx xxxx Latch1 0x24xx xxxx Inputs 0 28 Latch2 2 16 1015100 LD15 LDO Internal LCMX01200 CPLD 2 HOLT INTEGRATED CIRCUITS 11 CS and sequenced RDn WRn generation Vu 5 3 6130 Access LED Indicators Interrupt Logic Output Latch 1 w read back Status Inputs d Output Latch 2 w read back HI 6130 Interface 6130 gt 61
52. s written Windows 7 is supported and future OS versions including Linux are planned After the SDK is installed the PC may require a few moments or a reboot for the new drivers to take effect which are also installed by the SDK installation http www plxtech com products sdk pde HOLT INTEGRATED CIRCUITS 13 AN 6130PCle The PLX SDK installs a Plx folder on the root drive with several sub folders The PlxSdkUserManual is located in the C PIx PIxSdk Documentation folder This is an important document for information installation drivers utilities and PLX for the PEX8311 PCle interface Follow these steps to install the demo project into the PLX SDK Samples folder Install the PLX SDK Locate the zipped Holt demo project PCle 6130 test zip on the CD ROM and unzip this project folder into the C PIx PlxSdk Samples folder Use this directory structure because some PLX files reference other files in these directories Launch Microsoft Visual Studio and open the project using Open Project from the File menu or from the Open Project short cut that may appear on the Start Page Alternately double click on the PCle6130Test project file in the PCle6130 test project folder 1 The Solution Explorer with the source files is shown on the left side If this is not seen then open the Solution Explorer from the View menu at the top 2 Torun the program
53. sslane pex8311 http www microsoft com visualstudio eng downloads HOLT INTEGRATED CIRCUITS 33 A B Table Of Contents Block Diagram 1 Cover Page 2 PEX8311 Express Bus 3 PLX8311 Local Bus 4 CPLD J TAG 6130 Inputs 5 H 6130 6 CPLD POVER T PEX8311 NC Balls Lattice LCMX1200C3FTN245I 17 x 17 mm Address decoder Chip Selects RD WR Strobes 6130 RD WR Access LED indicators Status and DIP SW inputs 32bit 50 MHz PLX Local Bus 9 PIN DF CONN Holt HI 6130 MIL STD 1553 BC RT MT Terminals 93C56B u Wire EEPROM Local Bus Config PEX 8311 AA66BCF 337 BGA 21 X 21 mm AT25640A PCI Express X1 Card Edge Connector 12V to 5V 6130 PEX8311 DC DC E Date Changes 9 19 2013 Rev Holt Integrated Circuits 23351 Madero Mission Viejo CA 92691 www holtic com Title HI PCle_6130 d Document Number 1 of Thursday September 19 2013 Bheet E 1 5VCC 3 3VCC R1 8311 1 5V
54. t commands increment data word 1 using an API to demonstrate how the host alters data Other SA commands other than SA1 or SA30 will display the command word with a message No data blocks setup for SA xx To add other SA s to the SRT demo data blocks must be mapped to the desired SA using the HoltRT1DataBIkMapToSA API in demos c BC RT SMT demo initialization occurs in demos c The full SRT implementation is contained in module simpleRT c and is called from the main loop in H6130main c in function displayRT1Traffic u HOLT INTEGRATED CIRCUITS 23 AN 6130PCle Console main menu and HI 6130 registers Holt Integrated Circuits Hi 6138 PCle Project Rev 1 3 Holt API Uer 98 9 3 Pre Pre Pre Pre Pre Pre Pre Pre run Async Demo set run run run run run SMT demo IMT demo RT demo 2 OO mM 060000000007 gt 5 E E 5 gt lt 5 5 5 gt uit dem Output this 12421011 6x8688 4x6616 29545153 8 4x6626 6x8828 54210617 4x6838 4x6646 6x6848 6x8867 29451515 4x661 7 4x661F 27 125451 4 0x0037 0x0047 4 181519 4666 148117 4666 BACA 4606 12151017 HI16136 Demo selection SRT enabled showing message traffic received using B command and N command 16136 Demo selection gt b
55. taining supporting documentation and software Topics e Introduction e Quick Start Guide e Hardware e Programming Reference e Software e Customization Summary e Schematics BOM Board Default Setup Set SW2 position 6 set to Off up position This sets the HI 6130 input pin AUTOEN low which is required for the demos to work properly See the picture below JP6 and JP7 will be open Optionally jumper these when necessary to have the negative side of the bus transformers nXBUS grounded for testing purposes JP2 JP5 are not used or installed See the PLX PEX8311 PCI Express documentation for usage HOLT INTEGRATED CIRCUITS 2 AN 6130PCle C Quick Start Guide This board communicates with a PC using a PCle bridge chip made by PLX Technology plxtech com Install the PLX SDK by following the instructions in the Software section PLX SDK installation of this guide on page 13 A prebuilt Windows 7 compatible executable demo program is included on the CD ROM in the folder Holt HI 6130 PCle Demo Copy this folder to the desktop Confirm the factory default DIP switch settings logic O is down logic 1 is up address 3 SW3 1 3 set 4 6 set On RT2 address 4 SWA all set On except position 4 which is set Off SW2 Positions 1 5 are user defined These may be used by the demo program in future releases Default DIP switch settings 5388 1 12
56. uses this utility to program the two EEPROMs The 6130 uses a 16 bit data bus 16 bit address bus and three more lines to select the device during reads and writes The 50 WRn and RDn are decoded by the CPLD and routed to the 6130 Only the upper address lines LA31 LA26 of the LB are decoded by the CPLD for the chip selects The LB address and data lines connect directly from the PEX8311 to the 6130 In addition to these lines are several dedicated inputs and outputs listed below going to the HI 6130 from the CPLD For a complete description of the HI 6130 refer to the Holt data sheet and application notes that are included on the CD ROM The functions provided by the CPLD e HI 6130 interface signals CSn RDn and WRn meeting the 6130 timings 6130 write and read access LED s e Output latches with read back for control signals to the HI 6130 and LEDs e HI 6130 status and DIP switch inputs e Interrupt source pin The CPLD logically OR s the HI 6130 IRQ RT1MC8 and RT2MCS signals into a single signal that is connected to the interrupt pin of the PLX8311 See the software section for information how PLX API s handles interrupts PLX includes a demo project LocalToPcilnt to demonstrate how interrupts are handled The technique used in LocalToPcilnt was used in the Holt demos HOLT INTEGRATED CIRCUITS 7 AN 6130PCle Programming Reference LB decoded addresses 6130 chip select
57. with the Visual Studio debugger verify that the Debug configuration is selected at the top Build the solution from the Build menu using Build Solution or just press F7 There should be no errors produced in the Output window 3 Pressthe green arrow labeled Local Windows Debugger to run the program The console output should be displayed like the one shown in the Quick Start Guide 4 To build an executable version of the demo code select the Release configuration instead of Debug and rebuild the project The executable file is put into the Release sub folder of the project folder Use the Debug configuration for software development so that source level debugging features are operational Note When the SDK is installed a driver is installed for the PEX8311 HOLT INTEGRATED CIRCUITS 14 AN 6130PCle To understand the software and operation of the card for development work or modifications it is important to read the following documents e PLXSDK Users Manual which is installed when the SDK is installed e PLXPEX8311 Hardware Reference Manual and the PLX PEX8311 data book Latest versions are available from the PLX website These are not included in the SDK e Holt HI 6130 data sheet Provided on the CD ROM e Holt high level API software users manual Provided on the CD ROM Other useful documents e AN 6130 x pdf e AN 6130DG x pdf e AN 550 pdf for IC capacitor decoupling and tra

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