Correction for Incorrect Description Notice RL78/G13 Descriptions in
Contents
1. i be Page 829 Incorrect descriptions revised Signal by Power on reset Circuit and Voltage Detector 1 29 5 1 Serial array unit 1 During communication at same potential UART Page 956 Incorrect descriptions revised mode 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Tage ae eange 30 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics RAJE ADAY Content cnange Document Improvement The above corrections will be made for the next revision of the User s Manual Hardware c 2014 Renesas Electronics Corporation All rights reserved Page 1 of 14 stEN ESAS RENESAS TECHNICAL UPDATE TN RL A026A E Date May 21 2014 Corrections in the User s Manual Hardware Corrections and Applicable Items Pages in this document English RO1UH0146EJ0310 for corrections 5 3 9 High speed on chip oscillator trimming 12 5 7 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Pages 579 and 581 Pages 4 and 5 Figure 12 71 and Figure 12 73 12 6 3 SNOOZE mode function Page 606 12 6 3 SNOOZE mode function Paaes 608 609 Timing Chart of SNOOZE Mode Operation 611 i Pages 7 to 9 Figure 12 90 Figure 12 91 and Figure 12 93 20 2 Configuration of Power on reset Circuit Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit nage qi and Voltage Detector 1 29 5 1 Serial array unit T 1 During communication at same potenti2. 24 NE SAS RENESAS TECHNICAL UPDATE TN RL A026A E T 29 5 1 Serial array unit 1 During communication at same potential UART mode Page 956 Incorrect 29 5 1 Serial array unit 1 During communication at same potential UART mode TA 40 to 85 C 1 6 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Symbol Conditions HS LS LV Unit high speed low speed low voltage main Mode main Mode main Mode MIN ax wm MAK Transfer rate 2 4 Vx EVppo x 5 5 V 6 fuck 6 6 bps 1 Note 2 Note 2 Note 2 Theoretical value of 5 3 1 3 Mbps the maximum transfer rate fuck fcu Note Note 2 Theoretical value of 5 3 1 3 Mbps the maximum transfer rate fuck Pe meme m mm Note 2 Note 2 Theoretical value of 5 3 1 3 Mbps the maximum transfer rate fork Pete Note 2 Theoretical value of 1 3 Mbps the maximum transfer rate fuck fork Note omitted c 2014 Renesas Electronics Corporation All rights reserved 24 NE ESAS Date May 21 2014 29 5 1 Serial array unit 1 During communication at same potential UART mode TA 40 to 85 C 1 6 V x EVppo 1 lt lt 5 5 V Vss EVsso EVss1 Parameter Symbol Conditions HS LS LV high speed low speed low voltage main Mode main Mode main Mode nn u Note 2 Page 12 of 14 0 V T
3. 6 3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode However using the SNOOZE mode enables the UART to perform reception Normally the UART stops communication in the STOP mode operations without CPU operation omitted Cautions 1 The SNOOZE mode can only be used when the high speed on chip oscillator clock fix is selected for fci omitted 4 If a parity error framing error or overrun error occurs while the SSECm bit is set to 1 the PEFmn FEFmn or OVFmn flag is not set and an error interrupt INTSREq is not generated Therefore when the setting of SSECm 1 is made clear the PEFmn FEFmn or OVFmn flag before setting the SWCO bit to 1 and read the value in bits 7 to 0 RxDq register of the SDRm1 register c 2014 Renesas Electronics Corporation All rights reserved 424 NE SAS Date May 21 2014 Correct 12 6 3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode However using the SNOOZE mode enables the UART to perform reception Normally the UART stops communication in the STOP mode operations without CPU operation omitted Cautions 1 The SNOOZE mode can only be used when the high speed on chip oscillator clock fiu is selected for fcuk omitted 4 If a parity error framing error or overrun error occurs while the S
4. AP SP ST ___ Receive data2 AjP SP Shift register 01 PO KX Shit operation X A A Shin operation jJ INTSRO MERE L i TSFO1 lt 2 gt lt 5 gt lt 6 gt lt 8 gt omitted c 2014 Renesas Electronics Corporation All rights reserved 24 NESAS Date May 21 2014 Correct Figure 12 91 Timing Chart of SNOOZE Mode Operation EOCm 1 1 SSECm 0 CPU operation status Normal operation STOP mode Normal operation SS01 3 12 STO t FEE SE01 a EOCO1 SSECO L Clock request signal internal signal Receive data 2 SDRO1 Receive data 1 RxDO pin EMEN Receive data 1 X SP ST Receive data 2 P SP register 01 PCT A ASnftopeaton A XT X AShfopraon XX a EE c2 8 omitted Page 8 of 14 RENESAS TECHNICAL UPDATE TN RL A026A E It is correction of CPU operation status Clock request signal internal signal INTSRO and TSF01 in this Figure Incorrect Figure 12 93 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 1 Normal operation CPU operation status Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode 4 SS01 lt 3 gt STO1 lt 1 gt er EM MM MINE EOCO1 intemal signal Receive data Y 1 SDRO1 Receive data 1 RxDO pin Xp sp e Receive
5. Figure 12 73 Timing Chart of SNOOZE Mode Operation continuous startup Type 1 DAPmn 0 CKPmn 0 CPU operation status Normal operation STOP Bi mode STOP T 5500 3 STOO 1 Ln seo 1 385 SWCO 10 a H Clock request signal int signal SDROO pp Receive data SNOOZE mode T T 5100 pin Receive data 1 EL Receive data 2 Shift register 00 j Reception amp shift operation Reception 8 shift operation Y INTCSIOO m Data reception reception TSF00 2 lt 5 gt lt 6 gt lt 7 gt lt 5 gt lt 6 gt omitted c 2014 Renesas Electronics Corporation All rights reserved 24 NESAS Date May 21 2014 Correct Figure 12 73 Timing Chart of SNOOZE Mode Operation continuous startup Type 1 DAPmn 0 CKPmn 0 CPU operation status Normal operation STOP mode Normal operation STOP mode lt 4 gt 5900 lt 3 gt Clock request signal internal signal Receive data 2 1 Receivedatat DRO m NN EE unnnnnnp 1 900 pin Rees o IK Rest _ Shift register 00 See ce INTCSIOO EU M TSFOO 2 lt 5 gt lt 6 gt lt 7 gt lt 2 gt lt 5 gt lt 6 gt Emu Data reception Data reception omitted Page 5 of 14 RENESAS TECHNICAL UPDATE TN RL A026A E 3 12 6 3 SNOOZE mode function Page 606 Incorrect 12
6. For a falling voltage data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated STOP mode a Operation mode STOP instruction execution Standby release signal interrupt request Page 13 of 14 RENESAS TECHNICAL UPDATE TN RL A026A E 9 30 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Page 1049 Old 0 7 Data Memon TOP Mode Low Voltage Data Retention Characteristics Ta 40 to 105 C Vss 0 V Symbol Data retention supply 144 9 5 5 voltage Note The value depends on the POR de ion voltage When the voltage dron data is retained before a POR reset is effected but data no ined when a POR reset is effected 1 STOP mode Operation mode Data retention mode Vpp STOP instruction execution LA Standby release signal interrupt request c 2014 Renesas Electronics Corporation All rights reserved 424 NE SAS Date May 21 2014 New 30 7 RAM Data Retention Characteristics Ta 40 to 105 C Vss 0 V Data retention supply E 5 5 V voltage Note This depends on the POR detection voltage For a falling voltage data in RAM are retained until the voltage reaches the level that triggers a POR reset but not
7. Shift register 01 575 Shift operation D Shift operation X INTSRO INTSREO L TSFO1 lt 2 gt lt 5 gt lt 6 gt lt 8 gt omitted c 2014 Renesas Electronics Corporation All rights reserved 24 NESAS Date May 21 2014 Correct Figure 12 90 Timing Chart of SNOOZE Mode Operation EOCm 1 0 SSECm 0 1 CPU operation status Normal operation STOP mode mod lt 4 gt Normal operation 5501 lt 3 gt STO1 lt 1 gt SWCO 1 L BENE SSECO L Clock request signal internal signal Receive data 2 SDRO1 REN T QR data 1 19 gt Read oe RxDO pin Receivedatai ST Receivedata2 JAP SP Shift register 01 Shift operation _ le Shift X INTSRO TSF01 omitted Page 7 of 14 RENESAS TECHNICAL UPDATE TN RL A026A E It is correction of CPU operation status Clock request signal internal signal INTSRO and TSF01 in this Figure Incorrect Figure 12 91 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 0 Normal operation CPU operation status Normal operation STOP mode SNOOZE mode gt lt 4 5501 lt 3 gt lt 12 gt 5 01 1 pM SWCO EOCO1 SSECO L Clock request signal internal signal Receive data 2 4 SDRO1 Receive data 1 A Read RxDO pin ___ data1
8. data 2 Shift NE Sim operato SH INTSRO TSFO01 c2 5 6 T 5 6 T 11 8 omitted c 2014 Renesas Electronics Corporation All rights reserved 24 NESAS Date May 21 2014 Correct Figure 12 93 Timing Chart of SNOOZE Mode Operation EOCm 1 1 SSECm 1 Normal operation CPU operation status Normal operation STOP mode STOP mode 4 SS01 32 STOT lt 1 gt MENU se 1 B p rr _ _8858 sce pj Clock request signal E E 5 internal signal SDRO1 RxDO ____ data1 Xj P SP i Shift FR Sift OI INTSRO TSF01 2 5 lt 7 gt lt 5 gt lt 7 gt lt 11 gt lt 8 gt omitted Page 9 of 14 RENESAS TECHNICAL UPDATE TN RL A026A E 5 16 4 3 Multiple interrupt servicing Table 16 5 Relationshi Multiple Interrupt Servicing During Interrupt Servicin Page 796 Incorrect Table 16 5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Software Interrupt Multiple Interrupt Maskable Interrupt Request Priority Level 3 Request Request Priority Level 0 Priority Level 1 Priority Level 2 PR 00 PR 01 PR 10 PR 11 Interrupt Being Serviced Maskable interrupt wwemma o 9l1 l91 l91 1 omitted c 2014 Renesas Electronics Corporation All rights rese
9. external reset is released release from the first external reset f POR after the RESET signal is driven high 1 as well as the vol following release from the POR state after the RESET signal is driven high 1 stabilization wait time after VPOR 1 51 V typ is reached as well as the voltage stabilization wait time after VPOR 1 51 V typ is Reset processing time when the external reset is released is shown below reached After the first release of POR Reset processing time when the external reset is released is shown below 0 672 ms typ 0 832 ms max when the LVD is in use Release from the first external reset following release from the POR state 0 399 ms typ 0 519 ms max when the LVD is off 0 672 ms typ 0 832 ms max when the LVD is in use 4 Reset processing time when the external is rel fter th 0 399 ms typ 0 519 ms max when the LVD is off second release of POR is shown below 4 Reset times in cases of release from an external reset other than the above are After the second release of POR listed below 0 531 ms typ 0 675 ms max when the LVD is in use Release from the reset state for external resets other than the above case 0 259 ms typ 0 362 ms max when the LVD is off 0 531 ms typ 0 675 ms max when the LVD is in use mine 0 259 ms typ 0 362 ms max when the LVD is off omitted c 2014 Renesas Electronics Corporation All rights reserved Page 11 of 14
10. in this Figure ure 12 71 and Figure Incorrect Figure 12 71 Timing Chart of SNOOZE Mode Operation once startup Type 1 DAPmn 0 CKPmn 0 CPU operation status Normal operation STOP mode SNOOZEmode mode SNOOZE mode Normal operation 4 SS00 3 lt 11 gt STOO lt 1 gt g So SWCO 10 sr 0 7 Clock request signal internal signal a SDROO B gt zx E p KL ein SIOO pin 1 Receive data 1 Receive data 2 edis E ai Reception fion amp shi shift operation 7 5 Reception amp shit shift ope operation q INTCSIOO p E E AMEN TSF00 2 5 6 lt gt omitted c 2014 Renesas Electronics Corporation All rights reserved 24 NESAS Date May 21 2014 Correct Figure 12 71 Timing Chart of SNOOZE Mode Operation once startup Type 1 DAPmn 0 CKPmn 0 Normal operation Glock request signal internal signal SDROO SCKOO 900 pin Shift register 00 INTCSIO0 TSF00 Page 4 of 14 2 Receive data 2 M Feceive data 1 O FI Reseau Receive data 2 Reception amp shift operation Feception lt 7 gt Data reception 5 6 omitted RENESAS TECHNICAL UPDATE TN RL A026A E It is correction of CPU operation status Clock request signal internal signal and INTCSI00 in this Figure Incorrect
11. Date May 21 2014 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Document TN RL A026A E Rev 1 00 Category No Correction for Incorrect Description Notice infomation Title RL78 G13 Descriptions in the Hardware User s Manual Technical Notification Rev 3 10 Changed Category Lot No Applicable RL78 G13 Reference RL78 G13 User s Manual Hardware Product R5F100xxx R5F101xxx D CIE e roduc All lots ocumer 801UH0146EJ0310 Nov 2013 This document describes misstatements found in the RL78 G13 User s Manual Hardware Rev 3 10 RO1UH0146EJ0310 Corrections Applicable Item Applicable Page oa on chip oscillator trimming register 12 5 7 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Figure Pages 579 and 581 Incorrect descriptions revised 12 71 and Figure 12 73 12 6 3 SNOOZE mode function Page 606 Incorrect descriptions revised 12 6 3 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Figure Pages 608 609 and 611 Incorrect descriptions revised 12 90 Figure 12 91 and Figure 12 93 16 4 3 Multiple interrupt servicing Table 16 5 Relationship Between Interrupt Requests T Enabled for Multiple Interrupt Servicing Page 796 Incorrect descriptions revised During Interrupt Servicing 20 2 Configuration of Power on reset Circuit Figure 20 2 Timing of Generation of Internal Reset
12. SECm bit is set to 1 the PEFmn FEFmn or OVFmn flag is not set and an error interrupt INTSREq is not generated Therefore when the setting of SSECm 1 is made clear the PEFmn FEFmn or OVFmn flag before setting the SWCO bit to 1 and read the value in bits 7 to 0 RxDq register of the SDRm1 register 5 The CPU shifts from the STOP mode to the SNOOZE mode on detecting the valid edge of the RxDq signal Note however that transfer through the UART channel may not start and the CPU may remain in the SNOOZE mode if an input pulse on the RxDq pin is too short to be detected as a start bit In such cases data may not be received correctly and this may lead to a framing error or parity error in the next UART transfer Page 6 of 14 RENESAS TECHNICAL UPDATE TN RL A026A E 4 12 6 3 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Figure 12 90 Figure 12 91 and Figure 12 93 Pages 608 609 and 611 It is correction of CPU operation status Clock request signal internal signal INTSRO and TSF01 in this Figure Incorrect Figure 12 90 Timing Chart of SNOOZE Mode Operation EOCm 1 0 SSECm 0 1 CPU operation status Normal operation STOP mode SNOOZE mode 501 lt 3 gt STO1 lt 1 gt SEO1 SWCO 11 EOCO1 L Normal operation SSECO L Clock request signal internal signal SDRO Receive daia 1 losa Read RxDO pin Receive data 1 T ST Receivedata2 P sP
13. about 0 05 2 For the usage example of the HIOTRM register see the application note for RL78 MCU series High speed On chip Oscillator HOCO Clock Frequency Correction RO1AN0464 Remark c 2014 Renesas Electronics Corporation All rights reserved 24 NE SAS Date May 21 2014 Correct 5 3 9 High speed on chip oscillator trimming register HIOTRM omitted Figure 5 10 Format of High Speed On Chip Oscillator Trimming Register HIOTRM Address FOOAOH After reset undefined R W Symbol HIOTRM FEE HIOTRM5 HIOTRMA HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO HIOTRM5 HIOTRMA HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO High speed on chip oscillator Minimumspeed Minimumspeed a The value after reset is the value adjusted at shipment Note Remarks 1 The HIOTRM register holds a six bit value used to adjust the high speed on chip oscillator with an increment of 1 corresponding to an increase of frequency by about 0 05 2 For the usage example of the HIOTRM register see the application note for RL78 MCU series High speed On chip Oscillator HOCO Clock Frequency Correction RO1AN0464 Page 3 of 14 RENESAS TECHNICAL UPDATE TN RL A026A E 2 12 5 7 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Fi 12 73 Pages 579 and 581 It is correction of CPU operation status Clock request signal internal signal and TSF00
14. al Page 956 Page 13 UART mode 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics PAOR aE 30 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Wee page fo Incorrect Bold with underline Correct Gray hatched 16 4 3 Multiple interrupt servicing me Sl During Interrupt Servicing EX Revision History RL78 G13 User s Manual Hardware Rev 3 10 Correction for Incorrect Description Notice Document Number TN RL A026A E May 21 2014 First edition issued No 1 to 9in corrections This notice c 2014 Renesas Electronics Corporation All rights reserved Page 2 of 14 aQ NE S AS RENESAS TECHNICAL UPDATE TN RL A026A E register HIOTRM Page 1 5 3 9 High speed on chip oscillator trimmin 243 Incorrect 5 3 9 High speed on chip oscillator trimming register HIOTRM omitted Figure 5 10 Format of High Speed On Chip Oscillator Trimming Register HIOTRM Address After reset undefined R W Symbol HIOTRM ET HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO High speed on chip oscillator speed speed poo o j oo o o tf j 0 3 Dp LO qp The value after reset is the value adjusted at shipment Note 1 Ihe HIOTRM register the high speed on chip lock t ithin
15. heoretical value of 5 9 1 3 Mbps the maximum transfer rate fork Pete Note 2 Theoretical value of 5 3 1 3 Mbps the maximum transfer rate fork Pete 1 7 V lt EVppo lt 5 5 V fuck 6 fuck 6 fuck 6 bps Note 2 Note 2 Theoretical value of 5 3 1 3 Mbps the maximum transfer rate fork Note 1 6 V lt EVppo x 5 5 V Lal 2 Theoretical value jo ui the maximum transfer rate fork Pete omitted RENESAS TECHNICAL UPDATE TN RL A026A E 8 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Page 996 Old 29 7 Data Memon TOP Mode Low Voltage Data Retention Characteristics Ta 40 to 85 C Vss 0 V Symbol Data retention supply VDDDR 1 46 5 5 voltage Note The value depends on the POR de ion voltage When the voltage dron data is retained before a POR reset is effected but data no ined when a POR reset is effected 1 STOP mode Operation mode Data retention mode Vpp STOP instruction execution LA Standby release signal interrupt request c 2014 Renesas Electronics Corporation All rights reserved 424 NE SAS Date May 21 2014 New 29 7 RAM Data Retention Characteristics TA 40 to 85 C Vss 0 V Data retention supply 1 46 5 5 V voltage Note This depends on the POR detection voltage
16. once it reaches the level at which a POR reset is generated STOP mode a Operation mode STOP instruction execution Standby release signal interrupt request M Page 14 of 14
17. rved 424 NE SAS Between Interrupt Requests Enabled for Date May 21 2014 Correct Table 16 5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Software Interrupt Multiple Interrupt Maskable Interrupt Request Priority Level 3 Request Request Priority Level O Priority Level 1 Priority Level 2 PR 00 PR 01 PR 10 PR 11 e ero fen eze e Jezel ee Interrupt Being Serviced Maskable interrupt Software mert O O o omitted Page 10 of 14 RENESAS TECHNICAL UPDATE TN RL A026A E Date May 21 2014 6 20 2 Configuration of Power on reset Circuit Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 Page 829 Incorrect Correct Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit Figure 20 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 3 and Voltage Detector 1 3 1 When the externally input reset signal on the RESET pin is used 1 When the externally input reset signal on the RESET pin is used omitted omitted Notes 3 e time until normal operation starts includes the following rese Notes 3 The time until normal operation starts includes the following reset processing processing time whe e external reset is released after the first release time when the
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