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MPC8XXFADS User`s Manual - Freescale Semiconductor

1. 141 141 1 031 ETHRX 2 41 i 3 Em 030 4 UUFEN 5 029 ETHTX 6 I 2 7 028 8 PCS 2 9 IRDRXD 10 11 027 IRDTXD 12 1 43 026 14 2 15 025 11 16 4 17 024 PA10 18 2 19 20 PC7 2 21 023 22
2. I 1 p vi2 ORM_W 3 1 3 4 TEA 1 5 5 BRY 7 i DSDI 7 8 BURST 9 10 3 9 10 11 12 0500 11 EP 14 1 13 14 2 15 16 15 V2 GPL5B 17 18 17 18 NFO 19 20 19 220 GPLAB 21 22 21 22 1805 R Ww 23 em 2124 i 23 24 2 BCSRCS 25 26 i 25 26 2 CPLBA 27 28 27 E 28 Bi 29 50 29 30 AT3 667 31 32 31 32 SPARE4 33 l E34 1 33 34
3. ut 1 28 D 5 1 GND P1 5 zi i s RX TX JRBB CLSN LIL P3 ETHERNE 5 5 5 R 66232 62 m 52 44 n sf gg 2 9 318 2 5 06 LD7 LD8 109 1110 25 i 4 6834 PCMCIA PORT 364 04 43 pe 43 iis 27 051 m i T m 60 52 44 g 35 5 ADDRESS amp STROBES 61 43 D 27 5 2 1 35 10 18 26 2 U13 U14 U15 P 9 27 F1 U11 10 18 26 u16 17 sid E gt un T 68 52 44 z z 43 5 19 020 121 55 5 1016 F2 E 1 35 E um 023 5 E d 9 27 pg 0017 U18 E 5V pe m U22 10 18 26 a GND E amp 39 29 OTOROLR INC GND PC8XXFADS GND 04 U26 40 28 amp CONTROL 1997 P7 1 1 12
4. A B C D E F G H J K R R 3 98 9 99 R37 10K 10K 10K 10K 10K 10K 100 R22 and C8 are optional MC68160 ETHTX 52 PE68026 7 TX ACX E_TENA 4 ETHTCK 1 TENA ax 22 R34 HEF poss 4 TCLK bg a 5 E 2 54 8 1 16 TPTX 2 BROWN EU i 2 Rx Ax 28 pom 9 2 or TPRX 3 YELLOW ETHRCK 23 R33 LPF GREEN E_CLSN gt ARX 16 e RED E ka CLSN ARX 1 LPF 6 BLACK 9 39 38 1 1d E 2 4 19 7 gt 11 B BLUE ETHEN 10K be s C37 14 E 2 vin GNE 682 TPTX LPF PS 5 46 52 0 0 UF 4 05 10 TPRX 1 RM APORT 29 21 TPAPCE TPFLOL 28 40 ETHLOOP 6 TPFULDL TXLED 7 LOOP RXLEDE S 12 CLLED MFILT 43 16 TPLIL 24 R36 1 TPPLR 11 R10 R12 R19 R14 6 x 30 x5 TPJABB 48 ik 3900PF 20 2 R7 R13 330 330 330 330 330 C31 FES x gt S 0248 18 1 18 18 GND 68PF 68PF ES P gt S ds ne ane 2 0590 35 c15 16 um T3 CE lt lt lt 5 5 Fa E E E GND o a 5j 8 PROJECT MPCBXXFADS REV PILOT SHEET 6 OF 14 ENG
5. B D E G H K 10K 1 5V PULL UPS 5 5V PULL UPS S3 DSD 1 BCSRCS K g A MODIN 13 13 855 R51 TNT DRMPD 1 12 BR 12 DRMCS1 5 DSCK lt gt DRMPD2 11 lt gt 8 did 19 Us ee 10 DRMCS2 48 mE 7013 19 20 799 TRST J145 32eko 014128 14131 DRMiV 8 8 E_CLSN 32 21 D 10K Mes N Jt 1 015 21 129 EE DS z 1 we 19K 11064 38 0165 n2 lt e TON 6 IRQ SA 4 1 017 2 lt 125 _ 4 3 rae 3 IRQ1 ABE M54 jos 10018 27 1 019 22 1 C E 3 Or ROY 18 4 J128 2 018 a 124 LOD ER Tis 3 01 1 020 5 2 11119 C FD 72 SPAREL MS J 4 17021 2 1 F PD7 1 1 866 J132 4 2 30 x 1 5 1 022 58 ____ J110 5 2 40K BREVA 0 1 03 023151 m RN2 RNG 561 J136 gt _4 1 04 36 1 R75 7 1 024 5 A J112 SPARE3 4148 gt 41 08 37 BREVI 0 1 8 1 025 H7 10 V3 3 R81 J142 1 06 38 glee R7 147 1 07 7025 4115 E RENA AU 6 414 14 1 027 38 J109 ES 8 amp 7 BREV2 0 J140 4 1 08 40 1 ADSADR2 13 BCD1 13 15 1 028 29 t J120 CS BINPAK J144 3 1
6. ADI Address Selection HRESET cm ADI Handshake Logic gt SRESET amp Port Control gt VFLSO 1 0 1 1 0 1 VFLS1 S 5 0 FRZ CHINS Control Status Register Data Register gt DSDI DSCK gt Parallel lt gt Serial Converter DSDO To allow for an external debug port controller to be incorporated with the FADS and to allow target system debug by the FADS a standard 10 pin debug port connector is provided and the local debug port controller may be disabled by removing the ADI bundle from the its connector When the ADI s 37 lead cable is disconnected from either the ADI connector or from the FADS s 37 pin connector the debug port controller is disabled allowing either the connection of an external debug port controller or independent s w run i e the MPC boots from the flash memory to run user s application without debug port controller intervention This feature becomes especially handy regarding demo s In this state VFLS 0 1 FRZP signals are routed to the debug port connector so that the external debug port controller has run mode status information The ADI I F supports upto 8 boards connected on the same bundle Address selection is done by 052 1 2 3 See 2 3 1 ADI Port Address Selection on page 15 The debug port I F has two registers a control status register
7. 5V Power Supply Removed From Socket 2 4 3 Stand Alone Operation In this mode the FADS is not controlled by the host via the ADI Debug port It may connect to host via one of its other ports e g RS232 port port Ethernet port etc Operating in this mode requires an appli cation program to be programmed into the board s Flash memory while with the host controlled operation no memory is required at all Release 0 1 MPCSXXFADS User s Manual Hardware Preparation and Installation FIGURE 2 6 Stand Alone Configuration 5V Power Suppl E ga B 2 4 4 45V Power Supply Connection MPC8XXFADS requires 5 max power
8. a FLASH ENABLE DEFAULT FLASH ENABLED FLASH ENABLE PON DEFAULT FLASH ENABLE DRAM ENABLE PON DEFAULT DRAM ENABLED ETH ENABLE PON DEFAULT ETH ENABLED CONT ENABLE PON DEFAULT CONT REG ENABLE RS232 1 ENABLE DEFAULT 5232 1 ENABLE RS232 2 ENABLE PON DEFAULT 5232 2 ENABLE PCC ENABLE PON DEFAULT PCC ENABLE VCC 0 DEFAULT VCC CONT 0 PCC VCC 1 PON DEFAULT PCC VCC CONT 0 PCC VPPO PON DEFAULT _ PON DEFAULT VPP1 T S as default INF RED ENABLE DEFAULT INF RED ENABLE HALF WORD PON DEFAULT HALF WORD SDRAM ENABLE PON DEFAULT SDRAM ENABLED PROTECT PON DEFAULT CNT EN PROTECT Data Bits Assignments 8 FLASH ENABLE DATA 00 DRAM ENABLE DATA BIT 01 ETH ENABLE DATA BIT 02 INF RED ENABLE DATA BIT D3 FLASH CFG ENABLE DATA BIT D4 EN PROTECT DATA 05 CONT REG ENABLE DATA BIT D6 RS232 1 ENABLE DATA BIT D7 ENABLE DATA D8 PCC VCC 0 DATA BIT D9 PCC VPPO DATA BIT D10 DATA D11 151 Release 0 1 MPCSXXFADS User s Manual Support Information HALF WORD DATA D12 RS232 2 ENABLE DATA BIT D13 SDRAM
9. Reference Designation Part Description Manufacturer Part C1 C2 C3 C5 C9 C10 C12 C14 Capacitor 0 1uF 16V 10 SMD AVX 0603YC104KAT20 C17 C20 C21 C22 C24 C26 C27 0603 Ceramic C28 C32 C33 C34 C36 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C76 C77 C78 C79 C82 C83 C84 C86 C88 C90 C91 C4 C11 C13 C18 C19 C23 C25 Capacitor 10uF 20V 10 SMD SIEMENS B45196 H4475 K20 C29 C30 C75 C87 Size C Tantalum C7 Capacitor 4 7uF 20V 10 SMD SIEMENS B45196 H4106 K30 B Tantalum C8 C50 Capacitor 1uF 25V 10 SMD SIEMENS B45196 H5105 K10 Size A Tantalum C15 C16 Capacitor 68pF 50V 5 SMD SIEMENS B37871 K5680J 1206 Ceramic C31 Capacitor 3900pF 50V 5 SIEMENS B37949 K5392J COG SMD 1210 Ceramic C35 Capacitor 0 039uF 50V 5 SMD SIEMENS B37872 K5393J 1206 Ceramic C49 Capacitor 68uF 16V 10 SMD AVX TAJD686K016R Size D Tantalum C80 Capacitor 100pF 50V 10 SMD SIEMENS B37871 K5101K 1206 Ceramic C81 Capacitor 10nF 50V 10 NPO VITRAMNON VJ1210A103KXAT SMD 1210 Ceramic C85 C89 Capacitor 100uF 10V 10 SMD SIEMENS B45196 H2107 K10 Size D Tantalum D1 Zener Diode 12V SMD Motorola 1SMC12AT3 D2 D4 Diode Pair common cathode Motorola MBRD620CT D3 Zener Diode 5V SMD Motorola 1SMC5 0AT3 D5 D6 D7 Diode SMD Motorola LL4004G 0 1 052 Dip Switch 4 X SPST SMD GRAYHILL 90
10. Clock gen pins DbgClk 16 Debug Clock input source IN DbgClkOut 33 istype com to be connected to out Clk2 PIN 14 istype buffer divided by 2 Out Out for testing may be node ICIk PIN 15 Connected to Clkout externally In Misc PIN 23 istype com external indication ChinS PIN 12 active L when chips is In socket 116 Release 0 1 MPCSXXFADS User s Manual Support Information HHHHt HHH HHH F Ht HEH HHH HE HEO HH HHH Odo HHH H HHHH Ho Hi H H H HE H3 4 4 H H H HHHH HR HHE HH HHH K kK Kk K k K K k K K K k K k K kk k kk K k KK k k Clock genrator Internals DbgClkDivBy2 NODE istype buffer DbgClkDivBy4 NODE istype reg buffer DbgClkDivBy8 NODE istype buffer counter divider signals Cstr NODE istype buffer NODE istype buffer Clock Safe Transition Register kK K kk K k K K K K K K Reset active Active when at least one of the reset sources is active PrimReset
11. Pin No Signal Name Attribute Description 130 GND 131 A4 I T S MPC s Address line 4 Not used on the FADS 132 GND 133 A2 I T S MPC s Address line 2 Not used on the FADS 134 GND 135 5 I T S Address line 5 Not used on the FADS 136 GND 137 A1 I T S MPC s Address line 1 Not used on the FADS 138 GND 139 0 I T S MPC s Address line 0 Not used on the FADS 140 GND 87 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 9 PD2 Interconnect Signals Pin No Signal Name Attribute Description V12 O 10V output from voltage doubler Used to switch TMOS gates on both mother and daughter boards Should not be used for any other purpose N C oO AJ O N DSDI DSDI TDI Debug Port Serial Data Input JTAG port serial Data Input Used on the FADS as debug port serial data driven by the debug port controller If the ADI bundle is not connected to the FADS may be driven by external debug JTAG port controller GND DSCK DSCK TCK Debug Port Serial Clock input or JTAG port serial clock input Used on the FADS as debug port serial clock driven by the debug port controller If the ADI bundle is not connected to the FADS be driven by an external debug JTAG port controller 11 DSDO DSDO TDO Debug Port Serial Data Output or JTAG
12. state diagram BPS state BOOT PORT 32 if WRITE 0 amp BPS DATA BIT pin BOOT PORT 8 amp PON RESET BPS PON DEFAULT BOOT PORT 32 KA PON RESET amp BPS PON DEFAULT BOOT PORT 8 then BOOT PORT 8 else if MPC WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT 16 amp PON RESET BPS PON DEFAULT BOOT PORT 32 KA PON RESET amp BPS PON DEFAULT BOOT PORT 16 then BOOT PORT 16 else if MPC WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT RESERVED amp PON RESET BPS PON DEFAULT BOOT PORT 32 KA PON RESET amp BPS PON DEFAULT BOOT PORT then BOOT PORT RESERVED else BOOT PORT 32 state BOOT PORT 8 if WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT 32 amp PON RESET BPS PON DEFAULT BOOT PORT 8 KA PON RESET amp BPS PON DEFAULT BOOT PORT 32 then BOOT PORT 32 else if MPC WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT 16 amp PON RESET BPS PON DEFAULT BOOT PORT 8 KA PON RESET amp BPS PON DEFAULT BOOT PORT 16 then BOOT PORT 16 else if MPC WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT RESERVED amp PON RESET BPS PON DEFAULT BOOT PORT 8 PON RESET amp BPS PON DEFAULT BOOT PORT RESERVED then BOOT PORT RESERVED else 156 Release 0 1 MPCSXXFADS User s Manual Support Information BOOT PORT
13. Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C Contents 0 0126 04 0026 04 0 26 04 0 26 00 1FF5FC84 07 oes 1 OFB98C00 1 01B93C00 10AD7C00 FFFFFCO04 X 2 1 74 45 FOAFFCOO 1FF77C45 FOAFFCOO FFFFFC84 X 3 X F1AFFCOO X FOAFFCOO 05 X 4 X EFBBBCOO X E1BBBC04 X 5 1FE77C34 1FF77C45 X 1FF77C45 X 6 EFAABC34 X X X X 7 1FA57C35 X X X X 8 X X X 9 X X X A X X X B X X X C X X D X X E X X F X X a MRS initialization Uses Free space 34 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS TABLE 3 9 UPMB Initializations for MB811171622A 100 32 MHz 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C Contents 0 1 07 04 1 07 04 1F27FC04 1 07 04 1FF5FC84 7TFFFFCO7 1 EEAEFCOA 4 FFFFFCO04 X 2 4 10ADFC04 01B93C04 10AD7C00 FFFFFC04 3 EFBBBCOO FOAFFCOO 1FF77C47 FOAFFCOO FFFFFCO04 X 4 1FF77C47 FOAFFCOO X FOAFFCOO FFFFFC84 5 1FF77C34 F1AFFCOO X E1BBBC04 FFFFFCO7 6 EFEABC34 EFBBBCOO X 1FF77C47 X 7 1FB57C35 1FF77C47 X X X 8 X X X 9 X X X A X X X B X X X C X X D X X E X X F X X
14. Signal Name Description 1 Not connected with this application 2 D C Data Control selection When 711 the debug port controller s data register is accessed when 0 the debug port controller s control register is accessed 3 HST ACK Host Acknowledge input signal from the host 4 ADS SRESET When asserted 1 and the FADS is selected by the host generates Soft Reset to the MPC 5 ADS HRESET When asserted 17 and the FADS is selected by the host generates Hard Reset to the MPC 6 ADS SEL2 ADI I F address line 2 MSB 7 ADS SEL1 ADI I F address line 1 8 ADS SELO ADI I F address line 0 LSB 9 HOST_REQ HOST Request input signal from the host 10 ADS_REQ ADS Request output signal from the MPC8XXFADS to the host 11 ADS_ACK ADS Acknowledge output signal from the MPC8XXFADS to the host 12 Not connected with this application 13 Not connected with this application 14 Not connected with this application 15 Not connected with this application 16 PD1 Bit 1 of the ADI port data bus 17 PD3 Bit 3 of the ADI port data bus 75 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 1 P1 ADI Port Interconnect Signals Pin No Signal Name Description 18 PD5 Bit 5 of the ADI port data bus 19 PD7 Bit 7 of the ADI port data bus 20 25 GND Ground 26 Not connected with this application 27 29 HOST VCC HOST input from the hos
15. kk k kK kk K k KK k KK k Reset MPC8XX Connected to MPC8XX hard and reset inputs Asynchronous 1 s fe gt F gt F F fe oF F oF F FR F equations PdaHardReset H PdaHardReset oe PdaHardResetEn open drain PdaHardResetEn ADS_IS_SELECTED amp AdsHardReset ADS HARD RESET ACTIVE PdaSoftReset PdaSoftReset oe PdaSoftResetEn needs to be open drain PdaSoftResetEn ADS IS SELECTED amp AdsSoftReset 2 ADS SOFT RESET ACTIVE 126 Release 0 1 MPCSXXFADS User s Manual Support Information oe oe oe Clock generator All i f logic works which is driven externally by the output of DbgCIk divider The debug clock divider is a 3 bit free running counter outputs of which control a 4 1 mux output of which drives ICIK externally Since mux control may change on the fly a protection logic by means of 2 bit register is provided so that mux control is allowed to change only when all divider outputs are high which assures a falling edge prior to a rising edge CIK2 is infact the source for DSCK and is available outside for debug purpose k k equations DbgClkDiv clk DbgClk DbgClkDiv DbgClkDiv fb 1 free running counter Clock Safe Transition Register CSTR The goal
16. Motorola Semiconductor Israel Ltd MICROPROCESSOR amp MEMORY TECHNOLOGIES GROUP MPC8XXFADS Revision ENG amp Revision PILOT User s Manual ISSUE 0 1 Release 15 1 98 AUTHOR YAIR LIEBMAN MSIL ISSUE 0 0 Draft 22 7 97 LI N 1 N nm N c e e eee O1 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6 2 4 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 2 4 6 2 4 7 2 4 8 2 4 9 3 2 1 3 22 323 3 2 4 3 2 5 3 2 6 38247 3 2 8 3 2 9 3 2 10 3 2 11 3 2 12 3 2 13 3 2 14 3 2 15 MPCSXXFADS User s Manual TABLE OF CONTENTS General Information Introduction MPC8XX Family Support Abbreviations List Related Documentation Revision ENG to Revision PILOT Changes Changes to This Document from Previous Issue Draft 0 0 SPECIFICATIONS MPC8XXFADS Features MPC8XXFADS Goals Hardware Preparation and Installation INTRODUCTION UNPACKING INSTRUCTIONS HARDWARE PREPARATION ADI Port Address Selection Clock Source Selection Power On Reset Source Selection VDDL Source Selection Keep Alive Power Source Selection Debug Mode Indication Source Selection INSTALLATION INSTRUCTIONS Host Controlled Operation Debug Port Controller For Target System Stand Alone Operation 5V Power Supply Connection P7 12V Power Supply Connection ADI Installation Host computer to MPC8
17. 5 C6 gt HE Dow 5 x RxD rFDS6000 x c25 cae TF 8 50 i GND us i CND INFRA RED PORT 24104 gt co 1 1DUF 09 1 C2 lt 1704 tss 116 41500 R2 6 RSTXD2 13 12 1x02 2 05 Tx3 7 lt 82 2 o RSOTR2 36 002 bue URS E O str A BS es DTR2 a cd 20 6 510 7 5 2 13 GND E 82 M lt 4 10UF St 0 1UF 14 R6 SHOULD NOT BE ASSEMBELED MOTOROLA ING C7 15 SHORTED WITH Bohm RESISTOR 8 GND PROJECT MPCBXXFADS REV PILOT SHEET 7 OF 14 V YAIR LIEBMAN BLOCK 5232 Infra Red amp Clock Generator CHK DESCRIP A B G D E G H J K tmp_mnt net prince yair 8xx fads m brd pilot sc h 8 drw 07 MAY 97 16 57 last updote 07 MAY 97 16 57
18. k ADS 1 The other state is ADS_REQ ACTIVE HOST READ ADI AdsSelect fb BOARD 15 SELECTED amp 05 HstAck fb HOST ACTIVE amp AdsReq ADS REQ ACTIVE amp HstReq HOST ACTIVE HOST READ ADI DATA AdsSelect fb BOARD IS SELECTED amp DS HstAck fb HOST ACK ACTIVE amp HstReq HOST REQ ACTIVE amp AdsReq ADS REQ ACTIVE amp D HOST READ ADI CONTROL AdsSelect fb BOARD IS SELECTED amp 05 HstAck fb HOST ACTIVE amp HstReq HOST REQ ACTIVE amp AdsReq ADS REQ ACTIVE amp D_C CONTROL 124 Release 0 1 MPCSXXFADS User s Manual Support Information ADS SEND STATUS AdsSelect fb BOARD 15 SELECTED amp 05 HstReq fb HOST REQ ACTIVE amp D_C CONTROL amp AdsAck ADS ACTIVE amp IS STATUS REQUEST k k kk K k KK k KK k ADI Data Bus definitions Wk sk sk sk k IC I 9k I kok kok ak DATA BUFFERS ENABLE AdsSelect fb BOARD IS SELECTED 4 HstAck HOST ACTIVE amp HstReq z HOST REQ ACTIVE STATUS WORD ON ADI BUS AdsSelect fb BOARD IS SELECTED amp HstAck HOST ACTIVE amp HstReq HOST REQ ACTIVE amp D_C CONTROL READ DATA WORD ON ADI BUS z AdsSelect fbD BOARD IS SELECTED 4 HstAck HOST ACTIV
19. is reset 1 its hard soft reset signals are asserted jtis not allowed for the host to initiate data trnasfer towards the MPC8XX It can however access the control status register to either change parameters and or check for status The status of reset signals is added to the status register so it can be polled by the host kK kk K k KK k KK k module dbg_prt8 title MPC8XXFADS Debug Port Controller kK kk K k KK k k Device declaration kK K kk K k K K k K K K U02 device mach220a k E k k k k K K k RE ER K kk K Kk kk K k K K k K K K E HHHO HO HHHH HHHHH HHHH HB HHHO 7 H HHN H HN A HHH HR H HHH Hg H H H HHHH THHHHE dH HHHH H H gd H HOS gd UFGHHHHHHE S HHHH H H HBH HH H HHHH HHH K K K K k K KK K k K K K K K K Pins declaration HE SE CICER SE EE ok ok ADI Port pins HstReq PIN 20 Host to ADS write pulse IN 114 Release 0 1 MPCSXXFADS User s Manual Support Information AdsAck PIN 31 ISTYPE buffer ADS to host write ack OUT 3s AdsReq PIN 2 ISTYPE reg buffer ADS to host write signal OUT 3s HstAck PIN 54 Host to ADS write ack IN AdsHardReset PIN 50 Host to ADS Ha
20. a MRS initialization Uses free space 35 Release 0 1 MPC8XXFADS User s Manual Functional Description 4 Functional Description In this chapter the various modules combining the MPC8XXFADS are described to their design details 4 1 Reset amp Reset Configuration There are several reset sources on the FADS Keep Alive Power On Reset Regular Power On Reset Manual Soft Reset 4 Manual Hard Reset 5 MPC Internal Sources See the appropriate Spec or U M 4 1 1 Keep Alive Power On Reset The Keep Alive Power On Reset logic resides on the daughter board this since the Keep Alive power bus is on that board and it also allows the use of the daughter board connected directly to a user s application 4 1 2 Regular Power On Reset The regular power on reset operates in the same manner as the keep alive power on reset using a similar device the Seiko 5 8052 with detection voltage of 2 595V to 2 805V The reference voltage of this device is the MAIN bus of the MPC while the reset line asserted is the HRESET line When HRESET is asserted to the Hard Reset configuration is made available to the MPC BCSRO See 4 1 6 2 Hard Reset Configuration on 37 and TABLE 4 9 BCSRO Description on page 55 4 1 3 Manual Soft Reset To support application development not around the debug port and resident debuggers a soft reset push
21. lt 1 044 S J8 18 RNS 3435 28 1 016 65 SRESET 34 00 8 9 PDO Jib a 1 017 7046 66 207 BPD1 7 10 PD1 425 1 018 7047 67 _ PD5 35 8202 6 11 PD2 4 5 12 PD3 VELSERZ 56 4 4 13 5 02 RUN 18 BPD5 3 14 PD5 mm 37 BPD6 2 15 PD6 2 6 19 BPD7 1 16 07 CESTA lt _ gt J enti ia 819 lt 212 82 7 y ADSADR _ 31 3 836 MODIN 41 5 052 GND CHINS 7 FRZ MODIN gt 8 PROJECT MPC8XXFADS REV PILOT SHEET 8 OF 14 ENG YAIR LIEBMAN BLOCK DEBUG PORT CONTROLLER CHK DESCRIP A B G D E F G H J tmp _mnt net prince yair 8xx fads m brd pilot sch 9 drw 07 MAY 97 16 49 lost update 07 MAY 97 16 46 A B C D E G H J K FUSE VPP s E gt PWR3 F2 5A MIC29500 VPP i 1SMC5 0AT
22. D jns Co IE CE vec 61 A15 0014 30 RAS1 44 sez 61 BD13 BA13 62 BA13 36 55 _ 808 31 0014 16 0015 147 RAS2 45 63 8014 4 7 12 63 BA12 35 447 0015 aP rt 536 BA11 BA11 34 8 8023 8023 965 RASZ DQ16 4 64 A18 DQ16 105 RAS2DD 33 37 DP1 BA10 66 Bata 33 2440 00179 8022 8022 101 J67 NC5 0017 68 BAS 32 2 20 0018 18 8021 8021 100 70 BA8 31 11 BD20 8020 99 TASO 0018 6 21 0019 BBS1A 43 5 8017 7 72 7 30 12 8019 8019 97 CAST 0019 4 NC7 A22 0020 BBS2A 41 55 7 13 018 CASZ 0920 0021 95 BBSOA 42 092119 8019 T cto 0022 14 8017 mE 93 0022 21 __8020 vec NC1 CET 0023 91 BDRM W 47 23 BD21 NC2 TED 143 002555 BD22 4 7 0024 2 5 0024 E 8051 mE 89 BEDOOE 46 2 27 8023 R45 0025 87 5 Weg 0026 18 8029 8029 5 48 0026 35 DP2 WET 0027 19 8028 8028 483 A Ines 50 BDO WEZ 2 20 8027 8027 482 6 0027 52 Wei 26 BD26 8026 6 pp EDO 0028 WES 0029 77 ORMPD1 87 54 BD2 J11 Dozo 22 8025 BD25 76 DEHDD PD1 0029 22 555 F OE 0031 28 8024 8024 74 PD2 0030 22 502 PD3 DQ31 DRMPD4 HE 032160 806 201 62 806 0035 PD2 64 RBD7 Q34 6 PD 0035 38 DPA PD4 PD5 U7 36100 PDS PD7 DRAM MCM29020E Ua FLASH 7 C BD 0 31 ise DP 0 3 8 PROJECT REV PILOT SHEET 4 OF 14 YAIR LIEBMAN BLOCK DRAM amp FLASH MODULES
23. istype com Primary Reset Host initiated D PrimReset istype delayed Reset DD PrimReset NODE istype double delayed primary reset Reset NODE istype Interface reset PdaRst NODE istype reg buffer MPC8XX continued initiated part of the status register kK K Kk K K K K K K K K ADS_ACK ADS_REQ auxiliary internal control signals k k 5 HstReqNODE istype sync host req 05 HstReqNODE istype double sync host req 5 D C NODE istype buffer synchronized data control selection S HstAckNODE istype buffer sync host ack 117 Release 0 1 MPCSXXFADS User s Manual Support Information 05 HstAckNODE istype buffer double sync host ack BundleDelay1 BundleDelayONODE istype buffer delay counter for bundle delay compensation BndTmrExpNODE istype com terminal count for bundle delay timer PDOeNODE istype Mach to ADI data OE PdaHardResetEnNODE istype com enables hard reset buffer PdaSoftResetEnNODE istype com enables soft reset buffer Tx Shift Register TxReg7 TxReg6 TxReg5 TxReg4 TxReg3 TxReg2 TxRegl TxRegONODE istype buffer Transmit latch and shift register Tx Control
24. COMM PORTS EXPRNSION 5 18 15 20 25 32 18 C SP1 7 17 U27 P8 Release 0 1 14 MPCSXXFADS User s Manual Hardware Preparation and Installation 2 3 1 ADI Port Address Selection The MPC8XXFADS can have eight possible slave addresses set for its ADI port enabling up to eight MPC8XXFADS boards to be connected to the same ADI board in the host computer The selection of the slave address is done by setting switches 1 2 amp 3 in the Dip Switch DS2 Switch 1 stands for the most significant bit of the address and switch 3 stands for the least significant bit If the switch is in the ON state it stands for logical 1 In FIGURE 2 2 051 is shown to be configured to address 0 FIGURE 2 2 Configuration Dip Switch 052 ADR2 ADR2 ADR1 ADR1 ADRO ADRO 3 5 MHz Generator via EXTCLK 32 678 KHz Crystal Resonator DS2 Table 2 1 describes the switch settings for each slave address Table 2 1 ADI Address Selection ADDRESS Switch 1 Switch 2 Switch 3 0 OFF OFF OFF 1 OFF OFF ON 2 OFF ON OFF 3 OFF ON ON 4 ON OFF OFF 5 ON OFF ON 6 ON ON OFF 7 ON ON ON 2 3 2 Clock Source Selection Switch 4 on 052 selects the clock source for the MPC When it is in the ON position while the FADS is powered up the on board 32 768 KHz crystal resonator becomes the clock source and the PLL multiplication factor becomes 1 513 When
25. ACA ACA RAC ARC GR Edo 4 o Hh do GRE HH HHRH HHHHH HHH Edo HH HH H AH H HHHH HHHO B dE HHE 8 H m HHHHH HHE HO GHHHBE 1H PH 4 HH HH os H dbdHHHHE H HHHH Edo Hoo 1 HH HH GHHHHHE _ HHH GHHBHHE d HH HHH H HHH dod Hd d ORHHHHHEO H4 dodo 4 HH Hh dodo HH K k K K K K K K H L X Z 1 0 X Z GDU C D U k k Since all state machines operate at interface clock there is no need to have DbgClk driven during simulation it will double the number of vectors required Therefore an alternative clock generator was built with which the 1 2 clock is the 1 st in the chain This alternative clock is compiled in if the SIMULATION variable is defined not the original clock generator design is compiled however simulation will not pass then K K Kk K K K K K K K K SIMULATION 1 K K KK K K K K K K K K 120 Release 0 1 MPCSXXFADS User s Manual Support Information Signal groups kK K kk K K K K K K K K AdsSel AdsSel2 AdsSell AdsSel0 AdsAddr
26. VCC CONT 0 amp PON RESET USB 1 CONT PON DEFAULT USB VCC CONT 0 KA PON RESET amp USB VCC 1 CONT PON DEFAULT USB VCC CONT 0 then USB VCC CONT 0 else IUSB CONT 0 state diagram VideoOn state VIDEO ENABLED if WRITE BCSR 4 amp VIDEO ENABLE DATA BIT pin VIDEO ENABLED amp PON RESET VIDEO ENABLE PON DEFAULT VIDEO ENABLED PON RESET amp VIDEO ENABLE PON DEFAULT VIDEO ENABLED then ENABLED else VIDEO ENABLED state VIDEO ENABLED if MPC WRITE BCSR 44 VIDEO ENABLE DATA BIT pin VIDEO ENABLED 4 PON RESET VIDEO ENABLE PON DEFAULT VIDEO ENABLED KA PON RESET amp VIDEO ENABLE PON DEFAULT VIDEO ENABLED then VIDEO ENABLED else IVIDEO ENABLED state diagram VideoExtClkEn state VIDEO EXT CLK ENABLED if MPC WRITE BCSR 44 VIDEO EXT EN DATA BIT pin VIDEO EXT ENABLED 4 PON RESET VIDEO EXT EN PON DEFAULT VIDEO EXT ENABLED st 175 Release 0 1 MPCSXXFADS User s Manual Support Information PON RESET amp VIDEO EXT CLK EN PON DEFAULT VIDEO EXT ENABLED then IVIDEO EXT CLK ENABLED else VIDEO EXT CLK ENABLED state VIDEO EXT ENABLED if WRITE BCSR 4 amp VIDEO EXT EN DATA BIT pin VIDEO EXT ENABLED amp PON RESET VIDEO EXT
27. 045 F1 Fuse 1A 250V Miniature 5 X 20mm Fast blow Release 0 1 108 MPCSXXFADS User s Manual Support Information TABLE 5 12 MPC8XXFADS Part List 8w Reference Designation Part Description Manufacturer Part F2 Fuse 5A 250V Miniature 5 X 20mm Fast blow H1 H2 H3 Gnd Bridge Gold Plated PRECIDIP 999 11 112 10 J1 Jumper Header 3 Pole with Fabricated Jumper LD1 LD2 LD3 LD4 1010 1014 Led Yellow SMD SIEMENS LY T670 HK LD15 LD16 LD17 LD5 LD6 LD11 LD12 LD13 Led Green SMD SIEMENS LG T670 HK LD7 LD8 LD9 Led Red SMD SIEMENS LS T670 HK P1 Connector 37 pin Male DType KCC DN 37 P RCZ 90 PA2 PB2 Connector 2 X 9 pin Stacked EDA Inc 8LE 009 009 D 3 06H Female DType 90 P3 Connector 8 pin RJ45 KCC 90015 8P8C Receptacle 90 P4 Connector 68 pin Male SMD MOLEX 53380 6810 PCMCIA P5 Connector header 10 pin dual in SAMTEC TSM 105 03 S DV line SMD P6 Male Part Connector 3 pin Power Straight WB 81135 253303353 with false insertion protection P6 Female Part Connector 3 pin Power Plug WB 81138 253200353 7 Connector 2 pin Power Straight WB 81135 253303253 with false insertion protection P7 Female Part Connector 2 pin Power Plug WB 8113B 253200253 P8 Connector 96 pin Female DIN ELCO 268477096002025 41612 90 P8 Counterpart Connector 96 pin Male DIN ELCO 16845709
28. HHHH 2 H gd H HOS H UFGHHHHHHE H H HHHH H H H H H HHHH HHH 182 Release 0 1 MPCSXXFADS User s Manual Support Information k k k k kk k kk k k kk K k KK k k Pins declaration k k kk K k KK k K K k K kK Kk K k K K k K K K clock generator K K k k k k k k kk k kK kk K k KK k k SYSCLKPIN 50 pda clkout K kk K KK KK K K K K K K K K Dram Associated Pins k k k k k k k k Kk k Kk k Kk k A9 55 10 39 19 38 20 2 A30 PIN 36 pda address lines inputs IN W PIN 23 SizeDetectl PIN 26 SizeDetectOPIN 20 dram simm size detect lines IN HalfWord PIN 51 dram port width selection from control register 1 32 bit 0 16 bit DramBank1Cs PIN 45 1 st bank chip select IN DramBank2Cs PIN 46 2 nd bank chip select IN DramEn PIN 54 Dram enable from control reg IN H Active high to support power control DramAdd10PIN 32 istype DramAdd9PIN 33 istype com dram address lines Ras1 PIN 28 istype 183 Release 0 1 MPCSXXFADS User s Manual Support Information Ras1DD PIN 30 istype Ras2 PIN 29 istype Ras2DD PIN 31 istype dram RAS lines
29. EN PON DEFAULT VIDEO EXT ENABLED KA PON RESET amp VIDEO EXT CLK EN PON DEFAULT VIDEO EXT CLK ENABLED then VIDEO EXT CLK ENABLED else IVIDEO EXT ENABLED I kok k kok k state diagram VideoRst state VIDEO RESET ACTIVE if MPC WRITE BCSR 4 amp VIDEO RESET DATA BIT pin VIDEO RESET ACTIVE 4 PON RESET VIDEO RESET PON DEFAULT VIDEO RESET ACTIVB KA PON RESET amp VIDEO RESET PON DEFAULT VIDEO RESET then IVIDEO RESET ACTIVE else VIDEO RESET ACTIVE state VIDEO RESET ACTIVE if MPC WRITE BCSR 44 VIDEO RESET DATA BIT pin VIDEO RESET ACTIVE amp PON RESET VIDEO RESET PON DEFAULT VIDEO RESET ACTIVE PON RESET amp VIDEO RESET PON DEFAULT VIDEO RESET ACTIVB then VIDEO RESET ACTIVE else IVIDEO RESET ACTIVE II OR k kok IC k state diagram SignaLamp state SIGNAL LAMP ON if MPC WRITE BCSR 4 amp SIGNAL LAMP DATA BIT pin SIGNAL LAMP amp PON RESET SIGNAL LAMP PON DEFAULT SIGNAL LAMP ON PON RESET amp SIGNAL LAMP PON DEFAULT SIGNAL LAMP then ISIGNAL LAMP ON else SIGNAL LAMP ON 176 Release 0 1 MPCSXXFADS User s Manual Support Information state SIGNAL LAMP ON if WRITE BCSR 44 SIGNAL LAMP DATA BIT pin SIGNAL LAMP ON amp PON RESET SIGNAL LAMP PON DEFAULT
30. Pin ipti Number Signal Name Description 1 12V 12V input from external power supply 2 GND GND line from external power supply slot 5 1 8 P6 Serial Ports Expansion Connector P8 is the serial ports expansion connector Its is compatible with the QUADS board and with the MPC821 860ADS P8 is a 96 pin Female DIN 41612 connector Since the pinout of P8 is specific to the Daughter Board connected to the FADS it is described in each Daughter Board User s manual 5 1 9 Daughter Boards Connectors Interconnect Signals PD1 to are 140 pin receptacle inter board connectors which interconnect between this board and the daughter board All MPC pins appear in these connectors plus few auxiliary control pins These connectors are arranged in a quadratic assembly around the MPC to provide short PCB routs The interconnect signals of the connectors are described in TABLE 5 8 PD1 Interconnect Signals on page 82 in TABLE 5 9 PD2 Interconnect Signals on page 88 in TABLE 5 10 PD3 Interconnect Signals on page 95 and in TABLE A True for the MPC860 but true upto an extent for other derivatives 81 Release 0 1 MPCSXXFADS User s Manual Support Information 5 11 PDA Interconnect Signals on page 102 TABLE 5 8 PD1 Interconnect Signals Pin No Signal Name Attribute Description 1 L MPC
31. X MPC821 s or MPC823 s PD9 LD2 or MPC860s PD9 RXD4 Not used on the FADS Appears also at P8 On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as video data 5 116 LD3 I O X MPC821 s or MPC823 s PD10 LD3 or MPC860s PD10 TXD3 Not used on the FADS Appears also at P8 On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as video data 4 117 LD4 I O X MPC821 s or MPC823 s PD11 LD4 or MPC860s PD11 RXD3 Not used on the FADS Appears also at P8 On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as video data 3 118 LD5 MPC821 s or MPC823 s PD12 LD5 or 8605 PD12 L1RSYNCB Not used on the FADS Appears also at P8 On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as video data 2 119 LD6 X MPC821 s or MPC823 s PD13 LD6 or 8605 PD13 L1TSYNCB Not used on the FADS Appears also at P8 On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as video data 1 120 LD7 I O X MPC821 s or MPC823 s PD14 LD7 or MPC860s PD14 L1RSYNCA Not used on the FADS Appears also at P8 On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter boa
32. X MPC port A 10 Appears also at P8 but otherwise unused 18 GND 19 20 PC7 X MPC port C 7 Appears also at P8 but otherwise unused 21 PA9 X MPC PI O port A 9 Appears also at P8 but otherwise unused 22 GND 23 PA8 X MPC PI O port A 9 Appears also at P8 but otherwise unused 24 GND 25 26 PC13 X port C 13 Appears also at P8 but otherwise unused 95 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 10 PD3 Interconnect Signals Pin No Signal Name Attribute Description 27 ETHTCK O X Ethernet port Transmit Clock When the ethernet port is disabled via BCSRt1 tri stated Appears also at P8 28 GND 29 ETHRCK O X Ethernet port Receive Clock When the ethernet port is disabled via BCSRt1 tri stated Appears also at P8 30 GND 31 32 USPSPD O X Usb port Speed control Applicable for MPC823 or MPC850 daughter boards only Controls the speed of the USB transceiver while changing pull up resistors between USB D and D lines No use with any other daughter board See also TABLE 4 23 BCSRA Description on page 65 33 1 X port B 31 Appears also at P8 but otherwise unused 34 BINPAK PCMCIA port Input Port Acknowledge In fact PC15 DREQ1 RTS1 L1ST1 When the PCMCIA port is disabled BCSR1 may be used off board for any alterna
33. k k kk K k K K K K K k Flash Associated Pins F PDIPIN 7 F PD2PIN 65 F PD3PIN 41 PDAPIN 25 FlashCs PIN 49 flash bank chip select FlashEn PIN 15 flash enable from control reg FlashCs1 PIN 12 istype com Flash bank1 chip select FlashCs2 PIN 22 istype com Flash bank2 chip select FlashCs3 PIN 57 istype com Flash bank3 chip select FlashCs4 PIN 24 istype com Flash bank4 chip select FlashOe PIN 58 istype com Flash output enable kK K kk K k K K K K K K Control Register pins K kk K Kk Kk K k K K k K K K ContRegCs PIN 59 control register cs from MPC8XX ContRegEn PIN 56 control register enable from control register K K kk K Kk kK K Kk K K K K K K K K Reset amp Interrupt Logic Pins k K kk K Kk k K KK K K K K k K K K 13 connected to of Reset 21 connected to N O of Reset RegPORIn PIN 9 Regular Power On Reset In H HardReset PIN 48 istype Actual hard reset output O D SoftReset PIN 40 istype Actual soft reset output O D 184 Release 0 1 MPCSXXFADS User s Manual Support Information ResetConfig PIN 67 istype com Drives the RSTCONF signal of the MPC8XX DriveConfig PIN 63 istype com Drives configuration data to the MPC8XX AbrO PIN 10 connected to N C of A
34. 0 PON DEFAULT VCC CONT 0 PON RESET amp 0 PON DEFAULT VCC CONT 0 then VCC CONT 0 else PCC VCC CONT 0 state VCC CONT 0 if WRITE BCSR 1 amp 0 DATA BIT pin VCC CONT 0 amp PON RESET 0 PON DEFAULT CONT 0 KA PON RESET amp VCC 0 PON DEFAULT VCC CONT 0 then PCC VCC CONT 0 else IPCC VCC CONT 0 3k sk sk sok sk sk PB PER k kok state diagram PccVpp0 state VPPO if MPC WRITE BCSR 1 amp VPPO DATA _ amp PON RESET VPPO PON DEFAULT PON RESET amp PON DEFAULT PCC then VPPO else _ state VPPO if MPC WRITE BCSR 1 amp VPPO DATA BIT pin amp PON RESET VPPO PON DEFAULT PCC PON RESET amp PON DEFAULT then PCC VPPO else 170 Release 0 1 MPCSXXFADS User s Manual Support Information kK K kK K k K K K K K K state diagram PccVppl state VPPI if WRITE BCSR 1 amp VPP1 DATA PCC_VPP1 amp PON RESET PON DEFAULT VPPI1 PON RE
35. 1 vec Q 1UF Q 1UF 0 1UF Q 1UF 0 10 0 10 Q 1UF Q 1UF 0 1UF Q 1UF 0 1 Q 1UF C48 e 636 C43 652 lt 226 a 688 a 91 4 261 58 4 17 4679 e 38 GND 2 vec 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 1UF 1UF 1UF Q 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 10 1UF C68 C22 C27 C46 C21 C42 4 62 4 C83 4 C87 4 47 4 051 4 28 65 78 44 33 32 C39 1566 4 C34 V3 3 e 1UF 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 1UF 0 1UF 0 1UF 1UF 1UF 0 1UF 0 1UF 0 10 0 1UF 0 1UF 0 1UF 1UF 0 1UF 1554 60 82 C55 c5 62 672 4673 C53 C59 4 274 C45 cat 4 657 c69 C70 C56 677 4 76 C83 C71 9 DRMPWR M 0 1UF 0 1UF 0 1UF C86 C64 C40 6 GND GND BRIDGE GND BRIDGE GND BRIDGE 1 H12 1 H32 1 H2 E MOTOROLA INC 8 GND PROJECT REV PILOT SHEET 10 OF 14 ENG YAIR LIEBMAN BLOCK DECOUPLING CAPS CHK DESCRIP tmp mnt net prince yair 8xx fads m brd pilot sch 11 drw 15 JAN 98 16 41 lost updote 15 JAN 98 16 40
36. HHH H HHH H gd HH Hg Og HHHO UR HHHH HH HHHH H H gH HHO H H H GHHHHHE H H HH H HHHH HHH k k K k K K K K K K Reset amp Interrupt Logic Pins RstDeb1NODE istype com reset push button debouncer AbrDeb1 istype abort push button debouncer HardResetEnNODE istype enables T S hard reset pin SoftResetEnNODE istype enables T S soft reset pin ConfigHold2 ConfigHoldl ConfigHoldOnode istype reg buffer supplies data hold time for hard reset configuration ConfigHoldEndnode istype k data buffers enable K K K K K SyncHardReset NODE istype reg buffer synchronized hard reset DSyncHardReset NODE istype reg buffer double synchronized hard reset SyncTEA NODE istype reg buffer needed since TEA is HoldOffConsidered NODE istype reg buffer data drive hold off state machine D FlashOe NODE istype delayed flash output enable DD FlashOe NODE istype double delayed flash output enable 186 Release 0 1 MPCSXXFADS User s Manual Support Information TD FlashOe NODE istype com triple delayed flash output enable QD HlashOe NODE istype com quad delayed PD_FlashOe NODE istype com penta delayed KeepP
37. SIGNAL LAMP ON PON RESET amp SIGNAL LAMP PON DEFAULT SIGNAL LAMP ON then SIGNAL LAMP ON else ISIGNAL LAMP ON k sk sk sk sk F I 9k 9k oR 9k I ESE ACS A I kok state_diagram EthLoop state ETH_LOOP if MPC_WRITE_BCSR_4 amp ETH LOOP DATA BIT pin ETH_LOOP amp PON RESET LOOP PON DEFAULT ETH LOOP KA PON RESET amp LOOP PON DEFAULT ETH LOOP then LOOP else ETH LOOP state ETH LOOP if MPC WRITE BCSR 4 amp ETH LOOP DATA BIT pin ETH_LOOP 4 PON RESET LOOP PON DEFAULT ETH_LOOP KA PON RESET amp LOOP PON DEFAULT ETH LOOP then else LOOP ICS R Rok k kok k state diagram TPFLDL state if MPC WRITE BCSR 4 amp FULL DUP DATA BIT pin FULL amp PON RESET FULL DUP PON DEFAULT ETH FULL DUP PON RESET amp ETH FULL DUP PON DEFAULT FULL then FULL else FULL state ETH FULL DUP if MPC WRITE BCSR 4 amp ETH FULL DUP DATA BIT pin ETH FULL DUP amp PON RESET ETH FULL DUP PON DEFAULT ETH FULL 177 Release 0 1 MPCSXXFADS User s Manual Support Information PON RESET amp ETH FULL PON DEFAULT
38. USB FETH EN DATA BIT D4 USB SPEED 05 USB VCC 0 DATA BIT D6 USB VCC 1 DATA BIT D7 VIDEO ENABLE DATA BIT 08 VIDEO EXT EN DATA D9 VIDEO RESET D10 MODEM ENABLE DATA BIT 011 MODEM FUNC SEL DATA D12 kK K Kk K K K K k K K K Equations state diagrams CCG HHHHHHHE THHHE H H HHHH H HHH H H HHH gH HHR HH H d Ho HH OH HE HHH H HHHH d H H 4 dg HHIH HHH HHH H k k Configuration Register Gets its default pon reset values which are driven to the data bus when during hard reset configuration Tf other values are required this register may be written with new values to become active for the next hard reset state machines are built in a way that its power on value is changed in one place the declarations area k kK kk K k KK k K K K equations ifdef SLOW_PLL_LOCK 153 Release 0 1 MPCSXXFADS User s Manual Support Information PonDefault ResetConf RGPORIn BcesrOWrite BrdContR
39. state INT SPACE BASE 0x00F00000 if MPC WRITE BCSR 0 amp 15 DATA BIT pin INT SPACE BASE 0x00000000 amp PON RESET ISB PON DEFAULT INT SPACE BASE 0x00F00000 158 Release 0 1 159 MPCSXXFADS User s Manual Support Information KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00000000 then INT SPACE BASE 0x00000000 else if MPC WRITE BCSR 0 amp 15 DATA BIT pin INT SPACE BASE 0 000000 amp PON RESET ISB PON DEFAULT INT SPACE BASE 0x00F00000 PON RESET amp ISB PON DEFAULT INT SPACE BASE 0 000000 then INT SPACE BASE 0 000000 else if MPC WRITE BCSR 0 amp 15 DATA BIT pin INT SPACE BASE 0xFFF00000 amp PON RESET ISB PON DEFAULT INT SPACE BASE 0x00F00000 PON RESET amp ISB PON DEFAULT INT SPACE BASE 0 00000 then INT SPACE BASE OxFFF00000 else INT SPACE BASE 0x00F00000 state INT SPACE BASE OxFF000000 if WRITE 0 amp ISB DATA BIT pin INT SPACE BASE 0x00000000 amp PON RESET ISB PON DEFAULT INT SPACE BASE 0 000000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00000000 then INT SPACE BASE 0x00000000 else if WRITE BCSR 0 amp ISB DATA BIT pin INT SPACE BASE 0x00F00000 amp PON RESET ISB PON DEFAULT INT SPACE BASE 0 000000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00F
40. 127 m 128 127 128 SPARE3 23 129 130 5 129 130 18077 4 151 132 131 132 A2 155 l 134 133 134 A5 135 136 135 136 1 A1 137 138 137 m 128 OROLA AQ 139 140 139 120 E X PROJECT PD1 GND ET EP 142 5 142 CSE ENG YAIR LIEBMAN BLOCK DAUGHTER BOARD CONNECTORS PCMCIA amp RESEI ADDRESS amp STROBES Y CHK DESCRIP B C D E F G H J tmp mnt net prince yair 8xx fads m brd pilot sch 13 drw Q7 MAY 97 17 01 last update 07 MAY 97 17 01
41. 35 36 1 35 36 EPKROUT F_CS 37 38 37 128 VICE 39 40 39 40 41 42 41 m ORMCS2 45 44 43 44 AD DRMCS1 45 46 45 46 ATO SDRMCS 47 48 47 48 POE A CPL3 49 50 49 50 31 GPL2 52 51 52 BADDR3O WEZ 53 54 i 53 54 WE2 55 56 T 55 56 BADDR29 BT oa 58 1 57 58 852 59 60 1 59 60 61 62 i 61 92 RESETA SPARE1 65 l Eo i 63 64 EDOOE g 65 gt 1566 _ 28 BSOA 67 68 1 67 8 p 58 EXP BS3A 69 S 70 i 69 S 70 AIT B A31 71 72 71 5 2 Mock aS 75 qm 73 S om 75121 75 em a 75 76 _ 77 78 i 77 78 A30 79 80 79 80 21 81 82 81 82 PORST 20 83 84 i 83 84 HRESET AT 85 l i 96 i 85 86 RSTCNF A15 87 88 1 87 88 R PORI 89 90 89 A13 91 92 i 91 92 BWAITA 93 94 93 E BWP A12 9 96 95 96 851 A11 97 98 07 mee BROY A19 99 100 99 100 A9 101 102 __101 Es 02 DP3 A18 105 104 103 124 52 105 m 106 i 105 106 Bco1 17 107 108 i 107 MODIN A16 109 110 1 109 BBVD1 111 112 1 112 02 29 113 114 i 113 114 8 02 27 115 l as 1 116 28 117 oe 118 I 117 118 DPQ 26 119 120 118 128 072 25 121 122 121 122 DP1 24 123 124 123 124 22 125 m 126 125 126 IRQ1
42. 51 09 41 12 BVS2 12 R77 1 16 1 028 011 J122 32 1 J139 5841 010 42 EXTOLIO 4 et Ak UM hte Tae 1o30 412 L 124 EXTOL 10 aco2 _ 17031 53 ____1 126 9 C BVS1 9 R74 ABRO 8 8 w BCSR2R4 GND lt epi 7 0K ELITS 7 9 El 4 x 842 BCSR3RO 0 5 gt 7 4 4 Al RO4 ADSADR 5 3 ADSADR1 2 2 TEAM aie BCSRSRT 0 C x t lt gt 1 ROS END ui R43 BCSR3R13 0 DAUGHTER BOARD HRESET x 222 SPACERS MOUNTS R50 J39 53 tk 5 13 BADDR3 15 R57 J102 DBREV1 12 12 ESSE DISQUE xt N DBREV2 11 ALE_A ND 10 SPAREA 10 BREVA o lt gt eus 9 m BREV1 8 lt BADDR29 8 52 lt gt war 7 VS1 6 lt 6 5 5 gt A xt G 3 x3 6 2 2 lt gt BREVS I lt BADOR28 1 RN1 RN8 yee BCSR3R 15 peevee 7 mp BCSR3R 12 11 AME gt z DBID1 10 C gt 9 825 925 lt 8058 8 INPACK 5 ok ss s SPARE PARTS 98105 6 BVD1 ARS 3 PULL DOWNS BCSR3R13 5 R28 BCSR2RA 4 A EET 802 MOTOROLA INC xil 8 x2 R27 PROJECT MPC8XXFADS REV PILOT SHEET 11 OF 14 1 xu ENG YAIR LIEBMAN BLOCK PULL UP DOWN RESISTORS ETE PC CARD
43. FLASH ENABLEB kK kk K k KK k KK k 147 Release 0 1 MPCSXXFADS User s Manual Support Information Register Access definitions IER k kok I kok CONFIG_REG_ADD 0 1 1 STATUS REG2 ADD 2 STATUS REG3 ADD 3 CONTROL REG 4 ADD 4 WRITE BCSR 0 BrdContRegCs amp amp W amp A27 amp A28 6 A29 amp CntRegEn WRITE BCSR 1 BrdContRegCs amp amp W amp 27 amp A28 amp A29 amp CntRegEn WRITE BCSR 3 BrdContRegCs amp amp W amp 27 amp A28 amp A29 amp CntRegEn WRITE BCSR 4 BrdContRegCs amp amp W amp A27 amp A28 amp A29 amp CntRegEn BCSR WRITE ACTIVE 0 WRITE BCSR 0 BcsrOWrite fb 5 WRITE WRITE BCSR 1 1 Write fb WRITE ACTIVE WRITE BCSR 4 Bcsr4Write fb 5 WRITE READ BrdContRegCs amp W amp CntRegEn READ BCSR 0 BrdContRegCs amp W amp 27 amp 28 amp A29 amp CntRegEn READ BCSR 1 BrdContRegCs amp W amp A27 amp A28 amp A29 amp CntRegEn READ BCSR 2 BrdContRegCs amp W amp 27 amp A28 amp A29 amp CntRegEn READ BCSR 3 BrdContRegCs amp W amp 27
44. a Provided that a 12V power supply is applied 4 11 4 BCSR2 Board Control Status Register 2 BCSR2 is a status register which is accessed at offset 8 from the BCSR base address Its a read only register which may be read at any time BCSR2 s various fields are described in TABLE 4 13 BCSR2 A Provided that BCSR is not disabled 59 Release 0 1 Description on page 60 MPCSXXFADS User s Manual Functional Description TABLE 4 13 BCSR2 Description BIT MNEMONIC Function PON DEF ATT FLASH PD 4 1 Flash Presence Detect 4 1 These lines are connected to the Flash SIMM presence detect lines which encode the type of Flash SIMM mounted on the Flash SIMM socket There are additional 3 presence detect lines which encode the SIMM s delay but appear in BCSR3 For the encoding of FLASH PD 4 1 see TABLE 4 14 Flash Presence Detect 4 1 Encoding on page 60 Reserved Un implemented DRAM PD 4 1 Dram Presence Detect These lines are connected to the DRAM SIMM presence detect lines which encode the size and the delay of the DRAM SIMM mounted on the DRAM SIMM socket For the encoding of DRAM PD 4 1 see TABLE 4 15 DRAM Presence Detect 2 1 Encoding on page 61 and TABLE 4 16 DRAM Presence Detect 4 3 Encoding on page 61 9 12 EXTTOLI 0 3 External Tools Identification These lines which are available at the expansion connectors over the daughter board are in
45. za D22 PA8 8124 4 25 021 28 PC13 2 27 020 28 2 29 30 1 51 019 32 USBSPD 33 018 PB31 34 BINPAK 35 5 017 PB30 136 4 2 57 016 PB29 38 RSTXD1 2 59 RSRXD1 40 RSDTR1 41 D15 42 RSTXD2 2 43 014 RSRXD2 44 RSDTR2 gm D13 PC14 47 m 012 48 49 50 PB27 51 D11 PB28 52 53 010 PC12 54 PB26 55 09 56 E E 4 57 08 58 459 60 4 2 6 07 E_CLSN 62 E_RENA 63 06 SPARE2 64 VDOEN 65 D5 z 66 B 2 6 04 SYSCLK 8 68 2 69 70 71 03 D 72 N 2 13 02 m 74 2 2 75 01 PB17 PB18 77m 00 78 79 E DRMH W 81 DRAMEN 82 ETHEN FCFGEN 83 F_EN 84 IRD_EN SDRAMEN 85 BCSREN PA1 86 USBVCCO 87 PCCEN E 38 EXTOLIO 89 SGLAMP 90 4 EXTOLI2 91 USBVCC1 92 TMS DBREVO 93 EXTOLI1 PB16 94 TRST DBREV2 95 EXTOLI3 PB15 96 RS_EN1 BCSR3R1 97 DBREV1 PB14 98 08101 99 BCSR3RO PCB 100 PCS 0803 101 DBIDO 102 RS EN2 08105 103 08102 SHIFT_C 1044 BCSR3R13 106 08104 gg 09 HSYNC CHINS 107 VSYNC 1084 105 110 LOE 11 VDORST 112 VDOEXTCK 4113 100 114 101 115 102 116 103 g 117 mg 104 118 105 119 106 120 107 121 108 1224 123 124 ETHLOOP 125 TPFLDL 126 TPSQEL 127 MOM_AUD gg 29 MODEMEN 129 138 131 132 133 134 135 136 137 138 T MOTOROLA INC PD4I PROJECT REV PILOT SHEET 142 YAIR LIEBMAN BLOCK DAUG
46. 11 47 4 SFFFCCO6 X 4 OOFFECOO X OCAFCCOO FFFFCC85 5 37FFEC47 00 44 O3AFCC4C FFFFCCO5 6 X OOFFCC08 X OCAFCCOO X 7 X 44 X 8 OCAFCCOO X 9 4 OOFFEC44 B OOFFCCOO C 3FFFC847 D X X E X X F X X Release 0 1 29 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS TABLE 3 5 UPMA Initializations for 60nsec EDO DRAMs 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C Contents 0 24 8FFFEC24 8FFFCC24 8FFFCC24 COFFCC84 7 1 OFF3EC04 4 OFEFCC04 OFEFCC04 OOFFCC04 X 2 4 4 OCAFCCOO OCAFCCOO 07 04 X 3 00 4 11 47 4 SFFFCCO6 X 4 X OCAFCCOO FFFFCC85 5 37F7EC47 FFFFCCO5 6 X X OCAFCCOO X 7 X O3AFCC4C X 8 OCFSECOO OCAFCCOO X 9 00 44 4 X A 0 00 X X B 3FF7EC47 C X X D X X E X X F X X TABLE 3 6 Memory Controller Initializations For 20Mhz Register Device Type Init Value hex Description BRO All Flash SIMMs 02800001 Base at 2800000
47. 19 GND 20 21 22 IRQ3 L IRQ3 CR MPC s interrupt request 3 or Cancel Reservation Pulled up but otherwise not used on the FADS 23 GND 24 FRZ LX Freeze IRQ6 MPC debug state indication or Interrupt request line 6 Used by the debug port controler as debug state indication May be configured to alternate function provided that VFLS 0 1 function as VFLS and J1 is moved to position 1 2 25 GND 26 IRQ2 L RSV IRQ2 Reservation or Interrupt Request 2 Pulled up but otherwise unused on the FADS 27 GND 28 29 30 AT3 B7 PTR AT3 PCMCIA slot B Input Port 7 or Program Trace instruction fetch indication or Address Type 3 For MPC823 or MPC850 daughter boards configured as B7 For all other daughter boards configured as but may be configured to alternate function as no use is done with AT3 on the FADS 31 GND 32 4 MPC s spare line 4 Pulled up but otherwise unused on the FADS 33 GND 34 VFLSO BO IWPO VFLSO PCMCIA slot B Input Port 0 or Instruction Watchpoint 0 or Visible history Flushes Status 0 For the MPC823 or MPC850 daughter boards configured as BO For all other daughter boards configured as VFLSO May be configured to any alternate function Indicates in conjunction with VFLS1 the number of instructions flushed from the core s history buffer Indicates also whether the MPC is in debug mode If not using the debug port may be configured for alter
48. DSCK MPC8XX debug port gated serial clock Kk K equations DSCK oe ADS IS SELECTED when ADS IS SELECTED amp PdaSoftReset then DSCK H debug mode enable else when ADS IS SELECTED amp TxEn fb amp PdaSoftReset then DSCK DebugEntry fb debug mode direct entry else when ADS IS SELECTED amp TxEn fb amp STATE TX ON RISING then DSCK CIK2 debug port clock else when ADS IS SELECTED amp TxEn fb amp STATE TX ON FALLING then DSCK CIK2 debug port inverted clock else when ADS 15 SELECTED then DSCK H default value infact X K k K K K ILL DSDI Debug Port Serial Data in from MPC8XX To provide better hold time for DSDI from the last rising edge of DSCK dedicated enable for DSDI is provided DSDI ENABLE equations DsdiEn ar Reset DsdiEn clk state diagram DsdiEn state DSDI DISABLED if HOST WRITE ADI DATA amp BndTmrExp fb amp PdaRst fb then DSDI ENABLED else DSDI DISABLED state 0501 ENABLED iffSTATE TX DISABLED PdaRst fb then 138 Release 0 1 MPCSXXFADS User s Manual Support Information DSDI DISABLED else DSDI ENABLED equations DSDLoe ADS IS SELECTED amp DIAG LOOP BACK avoid junk driven on DSDI input during diagnostic loop back mode when ADS IS SELECTED amp PdaSoftReset then DSDI H else when ADS IS SE
49. FULL DUP then FULL else FULL DUP k sk sk sk state diagram TPSQEL state 5 TEST if WRITE BCSR 4 amp ETH CLSN TEST DATA BIT pin CLSN TEST amp PON RESET CLSN TEST PON DEFAULT TEST KA PON RESET amp CLSN TEST PON DEFAULT ETH CLSN then ETH CLSN TEST else ETH CLSN TEST state ETH CLSN TEST if MPC WRITE BCSR 4 amp ETH CLSN TEST DATA BIT pin ETH CLSN TEST amp PON RESET CLSN TEST PON DEFAULT ETH CLSN TEST PON RESET amp CLSN TEST PON DEFAULT ETH CLSN TEST then CLSN TEST else CLSN TEST k sk sk sok sk sk B PER k oR k k kok state diagram ModemEn state MODEM ENABLED FOR 823 if MPC WRITE BCSR 4 amp MODEM ENABLE DATA BIT pin MODEM ENABLED FOR 823 amp PON RESET MODEM ENABLE PON DEFAULT MODEM ENABLED FOR 823 KA PON RESET amp MODEM ENABLE PON DEFAULT MODEM ENABLED FOR 823 then IMODEM ENABLED FOR 823 else MODEM ENABLED FOR 823 state ENABLED FOR 823 if MPC WRITE BCSR 4 amp MODEM ENABLE DATA BIT pin MODEM ENABLED FOR 823 amp PON RESET MODEM ENABLE PON DEFAULT MODEM ENABLED FOR 823 PON RESET amp MODEM ENABLE PON DEFAULT MODE
50. ModIn support for 1 513 32KHz crystal or Modck1 ModIn 1 5 SMHz clock gen via CLK4IN ifdef SLOW_32K_LOCK Modck2 ModIn support for 1 1 or 1 5 from CLK4IN only Modck1 H no support for 32K oscillator K K kk K k K K K K K K Hard reset configuration equations ResetConfig oe H DriveConfig oe H Configuration hold counter Since the rise time of the HARD RESET signal 1s relatively slow there is a need to provide a hold time for reset configuration ConfigHold clk SYSCLK when SyncHardReset fb amp ConfigHoldEnd fb then ConfigHold ConfigHold fb 1 else when SyncHardReset fb amp ConfigHoldEnd fb then ConfigHold ConfigHold fb else when SyncHardReset fb then ConfigHold 0 ConfigHoldEnd ConfigHold fb HARD CONFIG HOLD VALUB terminal count ResetConfig HardReset drives RSTCONF to MPC8XX DriveConfig ConfigHoldEnd fb drives configuration data on the bus K K NMI generation 192 Release 0 1 MPCSXXFADS User s Manual Support Information equations NMI oe NMIEn NMI 0 O D NMIEn RstDeb1 fb amp AbrDeb1 fb only abort button depressed local data buffers enable kK kk K k KK k KK k equations SyncHardReset clk SYSCLK DSyncHardReset
51. else RSV13 ACTIVE sk eoe F ook F o state diagram RSV14 state RSVI4 ACTIVE if WRITE BCSR 0 amp RSV14 DATA BIT pin RSV14 ACTIVE amp PON RESET RSVI4 PON DEFAULT 5 14 ACTIVB PON RESET amp RSVI4 PON DEFAULT RSV14_ACTIVE then RSV14 ACTIVE else IRSVI4 ACTIVE state RSVI4 ACTIVE if MPC WRITE BCSR 0 amp RSV14 DATA BIT pin 5 14 ACTIVE amp PON RESET RSVI4 PON DEFAULT RSV14_ACTIVE KA PON RESET amp RSVI4 PON DEFAULT RSV14_ACTIVE then IRSVI4 ACTIVE 164 Release 0 1 MPCSXXFADS User s Manual Support Information else RSV14 ACTIVE F k kok I kok IC ak state diagram RSV15 state 5 15 ACTIVE if WRITE BCSR 0 amp RSV15 DATA BIT pin RSVI5 ACTIVE amp PON RESET RSVI5 PON DEFAULT RSV15_ACTIVE PON RESET amp RSVI5 PON DEFAULT RSV15_ACTIVE then RSV15 ACTIVE else IRSV15 ACTIVE state RSVI5 ACTIVE if MPC WRITE BCSR 0 amp 5 15 DATA BIT pin RSVI5 ACTIVE amp PON RESET RSVI5 PON DEFAULT RSV15_ACTIVE PON RESET amp RSVI5 PON DEFAULT RSV15_ACTIVE then IRSV15 ACTIVE else RSVI15 ACTIVE BCSR 1 equations WideContReg clk SYSCLK DrivenCont
52. gt 422 RESETS 25 PC12 823 24 824 G IRQ7 A24 O 25 G _ 825 FRZ A28 SHIFT_C 26 gt Pca 826 gt 26 5 627 827 IRQ3 A21 G veen 6 828 A28 6 c29 PC6 829 IRQ1 29 HSYNC gt PC5 850 NMI A30 C31 Pca 851 RS_ENT 1 VSYNC t ca2 9 832 A32 2216 216 GND Y Y 8 PROJECT MPC8XXFADS REV PILOT SHEET 14 OF 14 YAIR LIEBMAN BLOCK QUADS COMPATIBLE EXPANSION CONN CHK DESCRIP HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED M otorola Literature Distribution Box 5405 Denver Colorado 80217 1 800 521 6274 or 480 768 2130 J APAN M otorola J apan Ltd SPS Technical Information Center 3 20 1 M inami Azabu M inato ku Tokyo 106 8573 J apan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 HOME PAGE http motorola com semiconductors MOTOROLA Information in this document is provided solely to enable system and software implementers to use Motoro There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated integrated circuits based on the information in this document a products circu
53. initial space at OxFF000000 when 11 initial space at OXFFF00000 10 R W 9 10 DBGC 0 1 Debug Pins Configuration Value during Hard Reset determines the function of the PCMCIA channel Il pins When 00 these pins function as PCMCIA channel Il pins when 01 they serve as Watch Points 10 Reserved when 11 they become show cycle attribute pins e g VFLS VF 11 R W 11 12 DBPC 0 1 Debug Port Pins Configuration Value during Hard Reset determines the location of the debug port pins When 00 debug port pins are on the JTAG port when 01 debug port non existent 10 Reserved when 11 debug port is on PCMCIA channel II pins 00 R W 13 14 EBDF 0 1 External Bus Division Factor Value during Hard Reset determines the factor upon which the CLKOUT of the MPC external bus is divided with respect to its internal MPC clock When 00 CLKOUT is GCLK2 divided by 1 when 01 CLKOUT is GCLK2 divided by 2 00 R W 15 Reserved Implemented 0 R W 16 31 Reserved Un Implemented a May be read and written as any other fields and are presented at their associated data pins during Hard Reset b Applicable for MPC s revision A or above Otherwise have no influence 411 3 BCSH1 Board Control Register 1 The BCSR serves as a control register on the FADS It is accessed at offset 4 BCSR base address It ma
54. 54 23 PCMCIA Address line 23 55 24 PCMCIA Address line 24 56 PCCA25 O PCMCIA Address line 25 57 VS2 Voltage Sense 2 from PC Card Indicates in conjunction with VS1 the operation voltage for the PC Card 58 RESET Reset signal for PC Card 59 WAITA Cycle Wait from PC Card Active low 60 INPACK Input Port Acknowledge Active low Indicates that the Pc Card can respond to access for a certain address 61 PCREG O Attribute Memory or I O Space Select Active low Used to select either attribute card configuration memory or space 62 BVD2 Battery Voltage Detect 2 Used in conjunction with BVD1 to indicate the condition of the PC Card s battery 63 BVD1 Battery Voltage Detect 1 Used in conjunction with BVD2 to indicate the condition of the PC Card s battery 64 PCCD8 PCMCIA Data line 8 65 PCCD9 PCMCIA Data 9 66 PCCD10 y o PCMCIA Data line 10 79 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 4 P4 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 67 CD2 Card Detect 2 Active low Indicates in conjunction with CD1 that a PC Card is placed correctly in socket 68 GND Ground 5 1 5 P5 External Debug Port Controller Input Interconnect The debug port connector P5 is a 10 pin Male header connector signals of which are described in TABLE 5 5 P5 Intercon
55. Buffer Control 1 F EN _ 18 1 019 29 CETA 16 1020 30 2 15 RAS1DD FCFCEN 17 651184 262 RIP 1 RAS2DD DRMPDi 2015 7922 52 863 75 DRMA10 F CS _ 49 1 023133 AK 2 RIO ORMAS CLK1 balises 1702436 A30 2 8641 DRMH W 51 2 17925 37 PCOEN DRAMEN 54 17 1 026 38 A19 17027 39 BATO 2 2010 2 oo 7938 di REUS UBUFEN 3 o1 1 029 CEDAT 74LCX541 F_PD 1 4 417 1 030 807 184 44 2 DRMPD2 lt gt LBUFEN 8 05 806 17 2 3 DRMPD3 i TA 6 o4 805 16 5 34 DRMPDA Sats F PD1 7 05 1 033 04_15 4 A4 5 BCSRORA4 ROR 9 og 42 AEA 803 talys 6 ABRO 10 2 036 T 802 13 6 4172 F P2 UD 5102 ABR1 11 1 036 SS 801 127 FPD c F CS 12159 17037 86 800 F PD4 3 RSTO 13 1 038 EE eli 215 PCEEN 141 018 1 039 58 er RMPD 1 nC talion 029185 messcs epe gt a cuo 0 1 182 U31 ILL 62 PCR W TE SOF R S m 1 014 52 63 ORVCNF 74LCX541 BCSR2 28 015 54 8015 ta 1 2 2 DBREV 0 2 22117016 5 65 02 8074 17 2 3 5 on 7017 66 _ MODCK 8073 16 4 4314 DBREVO lt 1 018 67 RSTCNF BD12 15 5 EXTOLIS EXTOLI 0 3 2 81 1 047 YA AA gt ORNS 8014 14 516 _ EXTOLI2
56. HE PHHH OE HHH HH P d ego do HH O 4 Hon dd Odo do d PH Hh dodo HHH K K K LL H L X Z 1 0 X 27 C D U C D U SIMULATION 1 SLOW PLL 1 DRAM 8 OPERATION 1 oe oe Signal groups A27 A29 Data 0 0 15 145 Release 0 1 MPCSXXFADS User s Manual Support Information ConfigReg ERB IP RSV2 BDIS BPSO BPS1 RSV6 ISBO ISBI DBGCO DBGCI DBPCO DBPC1 RSV13 RSV14 RSV15 BPS BPSO BPS1 boot port size ISB ISBO ISB1 Initial Internal Space Base DBGC DBGC0 DBGC1 Debug Pins Configuration DBPC DBPCO DBPCI Debug port location ContReg FlashEn DramEn EthEn InfRedEn FlashCfgEn CntRegEnProtect CntRegEn RS232En1 PccEn PecVcc0 PccVpp0 PccV pp1 HalfWord RS232En2 SdramEn Pcc Vccl EthLoop TPFLDL TPSQEL SignaLamp UsbFethEn UsbSpeed UsbVcc0 UsbVcc1 VideoOn VideoExtClkEn VideoRst ModemEn Modem_Audio ReadBesr1 FlashEn DramEn EthEn InfRedEn FlashCfgEn CntRegEnProtect fb CntRegEn RS232En1 PecEn PccVcc0 PccVpp0 PccVpp1 HalfWord RS232En2 SdramEn PccVcc 1 ReadBcesr4 EthLoop TPFLDL TPSQEL SignaLamp UsbFethEn UsbSpeed UsbVcc0 UsbVecl VideoOn VideoExtClkEn VideoRst
57. ModemEn Modem_Audio DrivenContReg FlashEn DramEn EthEn InfRedEn FlashCfgEn CntRegEn RS232En1 PccEn Pec Vcc0 PccV pp0 Pcc V pp1 HalfW ord RS232En2 SdramEn PccVccl EthLoop TPFLDL TPSQEL SignaLamp UsbFethEn UsbSpeed UsbVcc0 UsbVcc1 VideoOn VideoExtClkEn VideoRst ModemEn Modem_Audio 0 1 0 146 Release 0 1 MPCSXXFADS User s Manual Support Information WideContReg FlashEn DramEn EthEn InfRedEn FlashCfgEn CntRegEnProtect CntRegEn RS232En1 PccEn Pec Vcc0 Pcc Vpp0 Pcc V pp1 HalfWord RS232En2 SdramEn PccVcc1 EthLoop TPFLDL TPSQEL SignaLamp UsbFethEn UsbSpeed UsbVcc0 UsbVcc1 VideoOn VideoExtClkEn VideoRst ModemEn Modem_Audio Besr2_3Cs Bcsr2Cs Becsr3Cs K K Kk K K K K K K K K Power On Reset definitions k sk sk sk k SC FLASH_CFG_ENABLE 0 A PON RESET ACTIVE 1 RESET CONFIG ACTIVE 0 changed due to long lock delay of the pda 17 7 95 ak ifndef SLOW PON RESET RGPORIn K A PON RESET ACTIVE Gifdef SLOW PLL LOCK PON DEFAULT ACTIVE 0 KA PON RESET PonDefault PON DEFAULT ACTIVE of change RESET CONFIG DRIVEN ResetConf RESET ACTIVE 4 FlashCfgEn
58. SDRAM ENABLED KA PON RESET amp SDRAM ENABLE PON DEFAULT _ then SDRAM ENABLED else ISDRAM ENABLED SE EE SE eoo ceo cR SEE eek BCSRA State Machines KOR HR ig ig KOR ER ERROR R 2k eo K k K K K state_diagram UsbFethEn state USB_FETH_ENABLED if MPC_WRITE_BCSR_4 amp USB FETH EN DATA BIT pin USB FETH ENABLED amp PON RESET USB FETH EN PON DEFAULT USB FETH ENABLED KA PON RESET amp USB FETH EN PON DEFAULT USB_FETH_ENABLED then USB FETH ENABLED else USB FETH ENABLED state USB FETH ENABLED if MPC WRITE BCSR 4 amp USB FETH EN DATA BIT pin USB FETH ENABLED amp PON RESET USB FETH EN PON DEFAULT USB FETH ENABLED PON RESET amp USB FETH PON DEFAULT USB FETH ENABLED then USB FETH ENABLED else IUSB FETH ENABLED EL state diagram UsbSpeed 173 Release 0 1 MPCSXXFADS User s Manual Support Information state USB FULL SPEED if MPC WRITE BCSR 44 USB SPEED DATA BIT pin USB FULL SPEED amp PON RESET USB SPEED PON DEFAULT USB FULL SPEED PON RESET amp USB SPEED PON DEFAULT USB FULL SPEED then USB FULL SPEED else USB FULL SPEED state USB FULL SPEED if MPC WRITE
59. When asserted low the Infra Red transceiver connected to SCC2 is enabled When negated the Infra Red transceiver is put in shutdown mode And SCC2 pins are available for off board use via the expansion connectors R W FLASH_CFG_EN Flash Configuration Enable When this bit is asserted low A the Hard Reset configuration held in BCSRO is NOT driven on the data bus during Hard Reset and B configuration data held at the 1 st word of the flash memory is driven to the data bus during Hard Reset R W CNT_REG_EN_P ROTECT Control Register Enable Protect When this bit is active low the BCSR EN bit in that register can not be written When in active BCSR_EN may be written to remove the BCSR from the memory map After any write to BCSR1 this bit becomes active again This bit is a read only bit on that register BCSR EN BCSR Enable When this bit is active low the Board Control amp Status Register is enabled on the local memory map When inactive the BCSR may not be read or written and its associated 51 is available for use via the expansion connectors This bit may be written with 1 only if negated 1 When the BCSR is disabled it still continues to configure the board according the last data held in it even during Hard Reset CNT REG EN PROTECT bit is R W RS232EN_1 RS232 port 1 Enable When asserted low the RS232 transceiver for port 1 is enabled When negated
60. k k Reset Status K PdaRst clk 136 Release 0 1 MPCSXXFADS User s Manual Support Information PdaRst PdaHardReset PdaSoftReset amp AdsSelect fb BOARD 15 SELECTED synchronized inside n debug Mode InDebugMode clk when FRZ IS SELECTED amp CHIP IS IN SOCKET then InDebugMode Freeze else when FRZ IS SELECTED amp CHIP IS IN SOCKET then InDebugMode VFLSO amp VFLS1 else when SOCKET then InDebugMode VflsPO pin amp VflsP1 pin K K Kk K K K K K K K K TxError This bit of the status register is set 1 when the MPC8XX internally resets during data transmission over the debug port When this bit is writen 1 by the adi port control the status bit is cleared Writing 0 has no influence on that bit K kk K Kk KK K k K K K K K K equations TxError clk ICIk TxError ar Reset state diagram TxError state TX DONE OK iffSTATE TX ENABLED amp PdaRst fb then TX INTERRUPTED else TX DONE OK state TX INTERRUPTED if HOST WRITE ADI CONTROL amp BndTmrExp fb amp PD6 pin HOST WRITE ADI DATA amp BndTmrExp fb amp PdaRst fb then 137 Release 0 1 MPCSXXFADS User s Manual Support Information TX DONE OK else TX INTERRUPTED
61. 15 88 GND 89 14 I T S MPC s Address line 14 90 GND 91 13 I T S MPC s Address line 13 92 GND 93 A6 I T S MPC s Address line 6 94 GND 95 12 I T S MPC s Address line 12 96 GND 97 A11 I T S MPC s Address line 11 98 GND 85 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 8 PD1 Interconnect Signals Pin No Signal Name Attribute Description 99 A19 I T S MPC s Address line 19 100 GND 101 A9 T S MPC s Address line 9 102 GND 103 A18 T S MPC s Address line 18 104 GND 105 A10 I T S MPC s Address line 10 106 GND 107 A17 I T S MPC s Address line 17 108 GND 109 A16 I T S Address line 16 110 GND 111 A8 T S MPC s Address line 8 112 GND 113 A29 I T S MPC s Address line 29 114 115 27 I T S MPC s Address line 27 116 GND 117 A28 I T S MPC s Address line 28 118 GND 119 A26 I T S MPC s Address line 26 120 GND 121 A25 T S MPC s Address line 25 122 GND 123 A24 I T S MPC s Address line 24 124 GND 125 A22 I T S MPC s Address line 22 126 GND 127 A3 I T S MPC s Address line 3 Not used on the FADS 128 GND 129 A23 I T S MPC s Address line 23 86 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 8 PD1 Interconnect Signals
62. 34 GND Ground 35 GND Ground 36 CD1 Card Detect 1 Active low Indicates in conjunction with CD2 that a PC Card is placed correctly in socket 37 PCCD11 PCMCIA Data line 11 38 PCCD12 Data line 12 39 PCCD13 yo PCMCIA Data line 13 40 PCCD14 PCMCIA Data line 14 41 PCCD15 PCMCIA Data line 15 78 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 4 P4 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 42 BCE2A PCMCIA Chip Enable 2 Active low Enables ODD numbered address bytes 43 VS1 Voltage Sense 1 from PC Card Indicates in conjunction with VS2 the operation voltage for the PC Card 44 IORD O Read Active low Drives data bus during l O Cards read cycles 45 IOWR Write Active low Strobes data to the PC Card during Card write cycles 46 PCCA17 PCMCIA Address line 17 47 18 PCMCIA Address line 18 48 19 PCMCIA Address line 19 49 20 PCMCIA 5 line 20 50 21 PCMCIA 5 line 21 51 PCCVCC for the PC Card Switched by the MPC8XXFADS 5 1 52 12V 5V VPP for the PC Card programming 12V available only if12V is applied to P8 Controlled by the MPC8XXFADS via 5 1 53 22 PCMCIA Address line 22
63. 4 022 8010 13 6 Ag 7 EXTOL aos 1277 7 8 EXTOLIO 808 11 4 Ag 9 1 GT 1 19 1 042 74LCX541 800 18 2 BCSR3RO 5 607 801 17 v K 3 BCSR3R1 CK 18 1 01929 BD11 BD2 telys 4514 i c1 1 0203 8012 803 15 42 5 8427 172 8013 804 1445 4516 BA28 2015 922 32 8014 805 alye 4417 BCSRCS 49 17023133 BD4 806 1215 7 8 BR W2 50 17024136 BCSREN 219 29 57 ons 37 FCFGEN i er R PORI 54 yore 38 VDOEXTC alt 027 55 Peten 021 6 USBVECT 2129 1 028 7 RIENE _ 5176 2 74LCX541 SGLAMP 41 2 43 8015 taly VDORST 51 5 A AES 8074 17 2 A5 ETHEN 6 04 032 25 ea 8073 telys 45 BCSR3R13 i DRAMEN 71755 1 033 p gt 8012 15 BREV1 8015 3 06 TAB BCSR3CS 8014 141 800 111 07 AUD 1 8010 13 vg 801 Tii 25 BD9 12197 A7 802 12 1 037 36 BD8 lg Ag 7 502 13 17038 158 ORMH_W e Ix 141 011 ous M 52 8014 21 04 1 040 ETHLOOP 809 22117013 104152 FEN 28 014 1 042753 RS ENT 807 24 1 015 043 76 806 26 10445 ENTE Board Control amp Status Reg 1250 26 1017 1045 PCCVPP1 MODEMEN 28 yora 04667 MOTOROLA INC 8 PROJECT MPCBXXFADS REV PILOT SHEET 3 OF 14 BCSRO ENG YAIR LIEBMAN BLOCK BCSR amp MISC CONTROL C
64. 8 state BOOT PORT 16 if MPC WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT 32 amp PON RESET BPS PON DEFAULT BOOT PORT 16 st KA PON RESET amp BPS PON DEFAULT BOOT PORT 32 then BOOT PORT 32 else if MPC WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT 8 amp PON RESET BPS PON DEFAULT BOOT PORT 16 KA PON RESET amp BPS PON DEFAULT BOOT PORT 8 then BOOT PORT 8 else if MPC WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT RESERVED amp PON RESET BPS PON DEFAULT BOOT PORT 16 KA PON RESET amp BPS PON DEFAULT BOOT PORT RESERVED then BOOT PORT RESERVED else BOOT PORT 16 state BOOT PORT RESERVED if WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT 32 amp PON RESET BPS PON DEFAULT BOOT PORT RESERVED KA PON RESET amp BPS PON DEFAULT BOOT PORT 32 then BOOT PORT 32 else if MPC WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT 16 amp PON RESET BPS PON DEFAULT BOOT PORT RESERVED KA PON RESET amp BPS PON DEFAULT BOOT PORT 16 then BOOT PORT 16 else if MPC WRITE BCSR 0 amp BPS DATA BIT pin BOOT PORT 8 amp PON RESET BPS PON DEFAULT BOOT PORT RESERVED KA PON RESET amp BPS PON DEFAULT BOOT PORT 8 then BOOT PORT 8 else BOOT PORT RESERVED I F k kok k kok k state diagram RSV6 state IRSV6 ACTIVE 157 Release 0 1 MPCSXXFAD
65. ACTIVE ISB PON DEFAULT INT SPACE BASE OxFF000000 149 Release 0 1 MPCSXXFADS User s Manual Support Information DBGC PON DEFAULT DEBUG PINS PCMCIA 2 DBPC PON DEFAULT PORT ON JTAG RSV13 DEFAULT RSV13 ACTIVE RSV14 DEFAULT RSV14 ACTIVE RSV15 DEFAULT 8 15 ACTIVE Data Bits Assignments ERB DATA BIT D0 DATA D1 RSV2 DATA BIT D2 BDIS DATA BIT D3 BPS DATA D4 D5 RSV6 DATA BIT D6 ISB DATA D7 D8 DBGC DATA BIT D9 D10 DBPC DATA D11 D12 RSV13 DATA 013 RSV14 DATA D14 5 15 DATA D15 BCSR 1 definitions k K K K HALF WORD 0 ENABLED 0 DRAM ENABLED 0 CONT REG ENABLE 0 RS232 1 ENABLE 0 RS232 2 ENABLE 0 PCC ENABLE 0 PCC VCC CONT 0 0 VCC CONT 1 1 _ 1 PCC_VPP1 1 FLASH ENABLED 0 150 Release 0 1 MPCSXXFADS User s Manual Support Information INF RED ENABLE 0 FLASH ENABLE 0 needed to be defined ealier DRAM 5 0 DRAM 5V CNT REG EN PROTECT 0 inadvertant write protect SDRAM ENABLED 1 Power On Defaults Assignments
66. B 15 Appears also at P8 but otherwise unused 96 RS EN1 O L RS232 port 1 Enable Connected to BCSR1 See TABLE 4 10 BCSR1 Description on page 57 97 PB14 X MPC PI O port B 14 Appears also at P8 but otherwise unused 98 PC4 X MPC PI O port C 4 Appears also at P8 but otherwise unused 99 PC5 X MPC PI O port C 5 Appears also at P8 but otherwise unused 98 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 10 PD3 Interconnect Signals Pin No Signal Name Attribute Description 100 PC6 X port C 6 Appears also at P8 but otherwise unused 101 GND 102 RS EN2 O L RS232 port 1 Enable Connected to BCSR1 See TABLE 4 10 BCSR 1 Description on page 57 103 SHIFT C X MPC821 s or MPC823 s PD3 SHIFT CLK or MPC860s PD3 RRJECT4 Not used on the FADS Appears also at P8 MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as Video Clock input 104 105 GND 106 HSYNC X MPC821 s or MPC823 s PDA LOAD HSYNC or MPC860s PD4 RRJECT3 Not used on the FADS Appears also at P8 MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as HSYNC for the video encoder 107 VSYNC I O X MPC821 s or MPC823 s PD5 FRAME VSYNC or MPC860s PD5 RRJECT2 Not u
67. B E D E F G H J 2 DAGCLK N ZA TT VFLS 0 1 0SDO 2222 100 otk sec MACH220 12n T 7415244 R38 2 BD C 2 18 ICLK 15 29 191 10 CLKO 1 019 J23 0500 0500 21 BHSTACK 41442 1 2 116 DBGCLK _ 16 ck 1 020 39 J21 c BADSSRST 6 443 4y3 14 ADSSRST 172 021 31 ADSACK BADSHRST 81444 vy4 12 HSTREQ 2015 02282 J18 VELA vere 3 ot i6 HSIVCC 49 1 023 33 DhgCIkDut 23 BADIA2 11 5 1 2919 ADSSEL2 ADSHRST 50 1 024136 J12 VFLS0 VFLS0 ot BADIA1 13 545 ADSSEL D C 5116 025 37 _ VFL P1 AQ CONN 5 24 5 2 3 2va B _ ADSSELO HSTACK 4 17026 38 VFLSPO 4 aes 2 4 2948 1 021 3 564 4 419176 21 00 1 028 m HRESE 15 566 CN HSTEN 3 1 029 s 7 8 050 pm E m SES E BHSTVCC 22 ADSADR2 _ 51 03 10825 ia GND 9 at ADSADR1 61704 1 032 43 P5 HRESET 4 71 05 1 033 42 2 22 ADSSEL O 2 ADSSELO 3 1 034 4709301 10 BADSREQ 1 06 48 DSCK DSCK T vrtso 10 1 035 gt po R17 1 07 55 PDQ 22 11 1 036 1 BADSACK lt 1 08 56 PD1 CHINS 12 1 037 o HSTEN R20 1K 1 09 57 PD2 lt VFLSFRZ 13 1 038 O 4 J32 14 e 1 039 158 PDS o 4 GND ADSSELI 21 3 1 049 82 ___PD4 13 012 60 PD6 03 ADSSELO 221043 1K RUN 23 1 042 2 5 14 1 014 63 7 5 FRZ 24 645 osa
68. CHK DESCRIP L A B C D E G H 4 tmp_mnt net prince yair 8xx fads m brd pilot sc h 5 drw 07 MAY 97 16 54 last updote 07 MAY 97 16 54 74ACT375 74 373 74 373 74 373 Bae 3 p 1012 2 BAB afin 102 2 Baie 3 1012 24 s ig 10 2 420 208 24 BA9 4920 208 22 BA17 4120 2018 BA26 4920 208 713 30 6 BAID 71 3016 PCCA21 BAIB 71 3018 BA26 71 308 4019 BAI1 81 409 2 BAIS Blan 409 PCCA12 BA27 Blan 409 1350 5012 12 13 40 501
69. F ook ok equations AdsReq clk AdsReq ar Reset AdsReq oe ADS IS SELECTED S HstAck clk 06 HstAck clk S HstAck HstAck DS HstAck HstAck amp 5 HstAck double synced state diagram AdsReq state ADS REQ ACTIVE if TXEn fb amp TxWordEnd end of data shift to MPC8XX ADS SEND STATUS then end of control write and status required ADS REQ ACTIVE else ADS REQ ACTIVE state ADS REQ ACTIVE if HOST READ ADI amp BndTmrExp fb then ADS REQ ACTIVE else ADS REQ ACTIVE K k k kK ADI control register The ADI control register is written upon host to ADI write with a D C line is in control mode It also may be read when StatusRequest bit is active 134 Release 0 1 MPCSXXFADS User s Manual Support Information Control register bits description DebugEntry 0 When this bit is active L MPC8XX will enter debug mode immediately after reset i e DSCK will be held high after the rising edge of SRESET When negated DSCK will be held low after the rising edge of SRESET so the MPC8XX will start running instantly DiagLoopBack 1 When active L the interface is in Diagnostic Loopback mode Le the source for the Rx shift register is the output of the Tx shift register During that mod
70. OFF CONSIDERED if END OF OTHER CYCLE DSyncHardReset fb then NO HOLD OFF else HOLD OFF CONSIDERED pcc data buffers enable 194 Release 0 1 MPCSXXFADS User s Manual Support Information equations PccDataBufEn oe 3 IPccEvenEn PccCE1 PccCE2 amp ENABLED amp IHARD RESET ASSERTED amp STATE HOLD OFF CONSIDERED amp HOLD OFF PERIOD STATE NO HOLD OFF PecOddEn PccCE1 PccCE2 amp ENABLED amp HARD RESET ASSERTED amp STATE HOLD OFF CONSIDERED amp HOLD OFF PERIOD STATE NO HOLD OFF E E k K K K pcc data buffers direction k K Kk K K K K K K K K equations PccR_W oe H PccR W R_W K kk K Kk K K kk K k K K K K K K Dram Address lines These lines are conencted to the dram high order address lines A9 and A10 if available These lines change value according to the dram size and port size The dram size is encoded from the presence detect lines see definitions above and the port size is determined by the control register k k K k k K k k k kk k kk k kk k KK k k equations DramAdd oe 3 when IS_HALF_WORD IS_HALF_WORD amp SIMM36400 SIMM36800 then DramAdd9 A20 else DramAdd9 A30 when SIMM36400 SIMM36800 amp 18 HALF WORD then DramAdd10 A19 else when SIMM36
71. ON then DEBUG PORT ON JTAG else if MPC WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT RESERVED amp PON RESET DBPC PON DEFAULT DEBUG PORT NON EXISTANT KA PON RESET amp DBPC PON DEFAULT DEBUG PORT RESERVED then DEBUG PORT RESERVED 162 Release 0 1 163 MPCSXXFADS User s Manual Support Information else if WRITE BCSR 0 amp DBPC DATA BIT pin PORT ON DEBUG PINS amp PON RESET PON DEFAULT DEBUG PORT NON EXISTANT PON RESET amp DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS then DEBUG PORT ON DEBUG PINS else DEBUG PORT NON EXISTANT state PORT RESERVED if MPC WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT ON JTAG amp PON RESET DBPC PON DEFAULT DEBUG PORT RESERVED KA PON RESET amp DBPC PON DEFAULT DEBUG PORT ON then DEBUG PORT ON JTAG else if MPC WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT NON EXISTANT amp PON RESET DBPC PON DEFAULT DEBUG PORT RESERVED KA PON RESET amp DBPC PON DEFAULT DEBUG PORT NON EXISTANT then DEBUG PORT NON EXISTANT else if WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT ON DEBUG PINS 4 PON RESET DBPC PON DEFAULT DEBUG PORT RESERVED KA PON RESET amp DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS then DEBUG PORT ON DEBUG PINS else DEBUG PORT
72. PULL UPS E B D E G H J K mnt net prince yoir 8xx fads m brd pilot sch 12 drw Q7 MAY 97 17 00 last update 07 MAY 97 17 00
73. RESERVED state DEBUG PORT ON DEBUG PINS if WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT ON JTAG amp PON RESET DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS PON RESET amp DBPC PON DEFAULT DEBUG PORT ON then DEBUG PORT ON JTAG else if MPC WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT NON EXISTANT amp PON RESET DBPC PON DEFAULT DEBUG PORT ON DEBUG PINS PON RESET amp DBPC PON DEFAULT DEBUG PORT NON EXISTANT then DEBUG PORT NON EXISTANT else if MPC WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT RESERVED amp Release 0 1 MPCSXXFADS User s Manual Support Information PON RESET PON DEFAULT DEBUG PORT ON DEBUG PINS PON RESET amp DBPC PON DEFAULT DEBUG PORT RESERVED then DEBUG PORT RESERVED else DEBUG PORT DEBUG K kk K k KK k KK k state_diagram RSV13 state RSV13_ACTIVE if MPC_WRITE_BCSR_0 amp RSV13 DATA BIT pin RSV13 ACTIVE amp PON RESET RSVI3 PON DEFAULT RSV13 ACTIVB PON RESET amp RSVI3 PON DEFAULT RSV13_ACTIVE then RSV13 ACTIVE else IRSV13 ACTIVE state RSVI3 ACTIVE if WRITE BCSR 0 amp RSV13 DATA BIT pin 5 13 ACTIVE amp PON RESET RSVI3 PON DEFAULT RSV13_ACTIVE KA PON RESET amp RSV13 PON DEFAULT RSV13 ACTIVB then IRSV13 ACTIVE
74. Select Generator DRAM DRAM 16 Bit Operation DRAM Performance Figures Refresh Control Variable Bus Width Control Flash Memory SIMM Synchronous Dram SDRAM Programming SDRAM Initializing Procedure SDRAM Refresh Communication Ports Ethernet Port Infra Red Port Infra Red Port Rate Range Selection RS232 Ports RS 232 Ports Signal Description PCMCIA Port PCMCIA Power Control Board Control amp Status Register BCSR BCSR Disable Protection Logic BCSRO Hard Reset Configuration Register BCSR1 Board Control Register 1 BCSR2 Board Control Status Register 2 16 17 17 17 17 17 17 17 18 19 29 29 29 29 29 29 29 30 30 30 30 31 31 31 32 32 33 34 35 37 39 40 41 41 42 42 42 43 43 43 44 46 46 47 47 48 52 Release 0 1 11 5 11 6 4 12 4 12 1 44124141 44122 44193 44124341 4 12 3 2 4 12 3 3 4 12 344 4 12 3 5 4 12 3 6 Q t t aA Su was PECES E 52 5 3 5 3 1 53 2 5 3 3 APPENDIX B 1 Be2 B 2 1 B 3 B 3 1 MPCSXXFADS User s Manual TABLE OF CONTENTS BCSR Board Control Status Register BCSRA Board Control Status Register 4 Debug Port Controller MPC8XXFADS As Debug Port Controller For Target System Debug Port Connection Target System Requirements Debug Port Control Status Register Standard MPCXXX Debug Port Connector Pin Description VFLS 0 1 HRESE
75. a flat cable A IBM AT is a trademark of International Business Machines Inc 20 Release 0 1 MPCSXXFADS User s Manual Hardware Preparation and Installation FIGURE 2 10 PA2 PB2 RS 232 Serial Port Connectors CD TX RX DTR GND DSR RTS CTS N C O WN NOTE The RTS line pin 7 is not connected on the MPC8XXFADS 2 4 9 Memory Installation MPC8XXFADS is supplied with two types of memory SIMM Dynamic Memory SIMM Flash Memory SIMM To avoid shipment damage these memories are packed aside rather than being installed in their sockets Therefore they should be installed on site To install a memory SIMM it should be taken out of its package put diagonally in its socket no error can be made here since the Flash socket has 80 contacts while the DRAM socket has 72 and then twisted to a vertical position until the metal lock clips are locked See FIGURE 2 11 Memory SIMM Installation below CAUTION The memory SIMMs have alignment nibble near their 1 pin It is important to align the memory correctly before itis twisted otherwise damage might be inflicted to both the memory SIMM and its socket FIGURE 2 11 Memory SIMM Installation 1 2 SIMM Metal Lock Clip A SIMM Socket 21 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS 3 OPERATING INSTRUCTIONS 331 INTRODUCTION This chapter provides necessary in
76. amp A28 amp A29 amp CntRegEn READ BCSR 4 BrdContRegCs amp W amp A27 amp A28 amp 29 amp CntRegEn BCSR 0 definitions R SE EE EO kK K KK K K K K k K K K INTERNAL_ARBITRATION 0 EXTERNAL ARBITRATION INTERNAL ARBITRATION AT OxFFF00000 0 active low 0x00000000 OxFFF00000 148 Release 0 1 MPCSXXFADS User s Manual Support Information RSV2 ACTIVE 1 BOOT DISABLE 1 BOOT ENABLE BOOT DISABLE BOOT PORT 32 0 BOOT PORT 8 1 BOOT PORT 16 2 BOOT PORT RESERVED 3 RSV6 1 INT SPACE BASE 0x00000000 0 INT SPACE BASE 0x00F00000 1 INT SPACE BASE OxFF000000 2 INT SPACE BASE OxFFF00000 3 DEBUG PINS PCMCIA 2 0 DEBUG PINS WATCH POINTS 1 DEBUG PINS RESREVED 2 DEBUG PINS FOR SHOW z3 DEBUG PORT ON JTAG 0 DEBUG PORT NON EXISTANT 1 DEBUG PORT RESERVED 2 DEBUG PORT ON DEBUG PINS 3 RSV13_ACTIVE 1 RSV14_ACTIVE 1 RSV15_ACTIVE 1 Meek Power On Defaults Assignments ERB PON DEFAULT INTERNAL ARBITRATION IP PON DEFAULT IP 0x00000000 5 2 PON DEFAULT RSV2 ACTIVE 15 PON DEFAULT BOOT ENABLE 5 PON DEFAULT BOOT PORT 32 5 PON DEFAULT RSV6
77. and a data register The control status register hold I F related control status functions while the data register serves as the parallel side of the Transmit Receive shift register The control status register is accessed when D_C bit is low while the data register is accessed when is driven high by the host via the ADI port 41221 MPC8XXFADS As Debug Port Controller For Target System The FADS may be used as a debug port controller for a target system provided that the target system has A Le debug port controller outputs are tri stated allowing debug port to be driven by an external debug tool B Depended on H W settings 68 Release 0 1 MPCSXXFADS User s Manual Functional Description a 10 pin header connector matching the one on the FADS In this mode of operation the on board debug port controller is connected to the target system s debug port connector see 4 12 1 1 Debug Port Connection Target System Requirements below Since DSDO signal is driven by the MPC itis a must to remove the local from its socket to avoid contention over this line When either the local MPC is removed from its socket or the daughter board is removed from the FADS all FADS s modules are inaccessible except for the debug port controller All module enable indications are darkened regardless of their associated enable bits in the BCSR Pull up resistors are connected to Chip Select lines so they do not float
78. applied by depressing BOTH Soft Reset amp ABORT buttons C Unless a 12V supply is required for a PCMCIA card or for a 12V programmable Flash SIMM D Implemented on Daughter Board 11 Release 0 1 MPCSXXFADS User s Manual General Information FIGURE 1 1 MPC8XXFADS Motherboard Block Diagram SDRAM 4 MBytes DATA amp ADDRESS BUFFERS FLASH SIMM Reset Interrupts 2 8MByte amp Clock gt lt DRAM SIMM 4 32 Mbyte DAUGHTER BOARD CONN Fast IrDA Port Control amp Status Register Debug Port et Connector E lt 2 DEBUG PORT CONTROLLER EEST ADI I F ETHERNET PORT PCMCIA Buffering amp ADI PORT Control PCMCIA PORT May be on a separate board 1 9 MPC8XXFADS Goals The MPC8XXFADS is meant to become a general platform for s w and h w development around the family Using its on board resources and its associated debugger the developer is able to load his code run it set breakpoints display memory and registers and connect his own proprietary h w via the expansion connectors to be incorporated to a system with the MPC This board could also be used as a demonstration tool i e application s w may be programmed into its flash memory and ran in exhibitions etc A Either on or off board 12 Release 0 1 MPCSXXFA
79. at any time by writing 1 0 to the EthEn bit in BCSR1 4 9 2 Infra Red Port An infra Red communication port is provided with the FADS the Temic s TFDS 6000 integrated transceiv er which incorporates both the receiver and transmitter optical devices with the translating logic and supports Fast IrDA upto 4 Mbps The comm port over which this port resides is determined according A Except for the MPC801 which does not have Ethernet support Le routing is done on the daughter board 49 Release 0 1 MPCSXXFADS User s Manual Functional Description to the MPC type To allow alternative use of the I R s SCC or its pins the infra red transceiver may be disabled enabled at any time by writing 1 O to the IrdEn bit in BCSR1 while all pins appear on the daughter board expan sion connector as well as on P8 of this board 4 9221 Infra Red Port Rate Range Selection The TFDS6000 has 2 bit rate ranges 1 9600 Bps to 1 2 MBps 2 1 2MBps to 4 MBps Selection between the 2 ranges is determined by the state of the transceiver s TX input on the falling edge of IrdEn When TX input is LOW at least 200 nsec before the falling edge of IrdEn then the LOWER range is se lected If TX is HIGH for that period of time then the HIGHER range is selected 4 9 3 RS232 Ports To assist user s applications and to provided convenient communication channels with both a terminal and a host computer two identical R
80. brdctl 12 ILL 197 Release 0 1 MPCSXXFADS User s Manual Support Information APPENDIX A ADI I F The ADI parallel port supplies parallel link from the MPC8XXFADS to various host computers This port is connected via a 37 line cable to a special board called ADI Application Development Interface installed in the host computer Four versions of the ADI board are available to support connection to IBM PC XT AT MAC II VMEbus computers and SUN 4 SPARC stations It is possible to connect the MPC281ADS board to these computers provided that the appropriate software drivers are installed on them Each MPC281ADS can have 8 possible slave addresses set for its ADI port enabling up to 8 MPC281ADS boards to be connected to the same ADI board The ADI port connector is a 37 pin male D type connector The connection between the MPC281ADS the host computer is by a 37 line flat cable supplied with the ADI board FIGURE A 1 below shows the pin configuration of the connector FIGURE A 1 ADI Port Connector Gnd 20 1 NC Gnd 21 2 Gnd 22 3 HST ACK Gnd 22 4 ADS SRESET Gnd 54 5 ADS HRESET Gnd 25 6 ADS SEL2 412v N C 26 7 ADS HOST VCG 27 2 ADS SEL 9 HOST_REQ HOST VCC 28 10 ADS REQ HOST VCC 29 11 ADS ACK HOST ENABLE 30 x 12 Gnd 31 13 Gnd 32 15 PDO 34 16 PD1 PD2 35 Poe 36 121 003 37 19 PD7 NOT
81. by LINEAR TECHNOLOGY This device controlled by BCSR1 switches 12V VPP for card programming and controls gates of external MOSFET transistors through which the PC Card is switched When is inserted while the channel is enabled via BCSR1 i e both of the CD 1 2 Card Detect lines are asserted low the status of the voltage select lines VS 1 2 should be read to determine the PC Card s operation voltage level according to which PCCVCC 0 1 bits in BCSR1 should be set to drive the correct 5 to the PC Card When is being removed from the socket while the channel is enabled BCSR1 the negation of CD1 and CD2 may be sensed by the and power supply to the card may be cut WARNNING Any application S W handling the PCMCIA channel must check the Voltage Sense lines before Power is applied to the PC Card Otherwise if 5V power is applied to a 3 3V Only card permanent damage will be inflicted to the PC Card 4 11 gt Board Control amp Status Register Most of the hardware options on the MPC8XXFADS are controlled or monitored by the BCSR which is a 32P bit wide read write register file The BCSR is accessed via the MPC s CS1 region and in fact includes 5 registers BCSRO to BCSR4 Since the minimum block size for a CS region is 32KBytes BCSRO BCSRA are multiply duplicated within that region See also TABLE 3 1 MPC8XXADS Main Memory Map on page 25 The following
82. clk SYSCLK SyncHardReset HardReset DSyncHardReset SyncHardReset fb SyncTEA clk SYSCLK SyncTEA TEA LocDataBufEn oe 3 UpperHalfEn IDramBank1Cs amp DRAM ENABLED DramBank2Cs amp SIMM36200 SIMM36800 amp DRAM ENABLED FlashCs amp FLASH ENABLED IContRegCs amp CONTROL REG ENABLED 1 amp ENABLED IPccCE2 amp PCC ENABLED ConfigHoldEnd fb STATE HOLD OFF CONSIDERED amp HOLD OFF PERIOD STATE NO HOLD OFF LowerHalfEn DramBank1Cs amp DRAM ENABLED amp IS HALF WORD IDramBank2Cs amp SIMM36200 SIMM36800 amp 15 HALF WORD amp DRAM ENABLED FlashCs amp FLASH ENABLED ConfigHoldEnd fb amp FLASH CONFIGURATION ENABLED amp STATE HOLD OFF CONSIDERED amp HOLD OFF PERIOD STATE NO HOLD 193 Release 0 1 MPCSXXFADS User s Manual Support Information local data buffers disable data contention protection IL equations HoldOffConsidered clk SYSCLK D FlashOe FlashOe DD FlashOe D FlashOe fb TD FlashOe DD FlashOe fb OD FlashOe TD_FlashOe fb PD FlashOe QD FlashOe fb Gifdef DEBUG equations HoldOffConsidered HOLD OFF CONSIDERED ifndef DEBUG state_diagram HoldOffConsidered state NO HOLD OFF if END OF FLASH READ amp DSyncHardReset fb then HOLD OFF CONSIDERED else NO HOLD OFF state HOLD
83. contains all control register s bits 4 0 with the addition of the following InDebugMode Bit 5 When this bit is active H the mpc is in debug mode 1 either Freeze or VFLS 0 1 lines are driven high When mpc is not in socket VflsP 0 1 coming from the debug port selected TxError Bit 6 When this bit is active H it signals that MPC8XX was reset internally during data transmission 1 data received during that trnasmission is corrupted This bit is reset L when either happens 1 The interface is reset by the host both AdsHardReset and AdsSoftReset are asserted H by the host while the board is selected 2 The host writes the interface with D C signal low control and with data bit 6 high 3 a new data word is written to the Tx shift register Le error is not kept indefinitely PdaRst Bit 7 When this bit is active H it means that either SRESET or HRESET or both are driven by the MPC8XX The host have to wait until this bit negates so that data may be wrriten to the debug port oe equations PDOe DATA BUFFERS ENABLE PD oe PDOe when READ DATA WORD ON ADI BUS then PD RxReg fb elsewhen STATUS WORD ON ADI BUS then PD PdaRst fb TxError fb InDebugMode fb DbgCIkDivSell fb DbgCIkDivSelO fb StatusRequest fb DiagLoopBack fb DebugEntry fb
84. erratic behavior is likely to be demonstrated resulting in a system crash 4 6 2 DRAM Performance Figures The projected performance figures for the dram are shown in TABLE 4 2 Regular DRAM Performance A Normal i e Single Read Single Write Burst Read amp Burst Write B Taking into account support for narrower bus widths 40 Release 0 1 MPCSXXFADS User s Manual Functional Description Figures on page 41 and in TABLE 4 3 EDO DRAM Performance Figures on page 41 TABLE 4 2 Regular DRAM Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 25 DRAM Delay nsec 60 70 60 70 Single Read 6 6 3 4 Single Write 4 4 3 3 Burst Read 6 2 3 2 6 3 2 3 3 2 2 2 4 2 2 2 Burst Write 4 2 2 2 4 2 2 2 3 1 2 2 3 2 2 2 Refresh 213P 2525 1385 1385 a Four beat refresh burst b Not including arbitration overhead TABLE 4 3 EDO DRAM Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 25 DRAM Delay nsec 60 70 60 70 Single Read 6 6 3 4 Single Write 4 4 2 3 Burst Read 6 2 2 2 6 3 2 2 3 1 1 1 4 1 2 2 Burst Write 4 2 2 2 4 2 2 2 2 1 1 1 3 2 2 2 Refresh 213P 253b 133b 132 a Four beat refresh burst b Not including arbitration overhead 4 6 3 Refresh Control The refresh to the dram is a CAS before RAS refresh which is controlled by UPMA as well The refresh logic is clock
85. match Tn this file 7 BundleDelay field in the control register is changed to debug port clock frquency select according to the following values 0 divide by 8 1 25 Mhz divide by 4 2 5 Mhz 2 divide by 2 5 Mhz 3 divide by 1 10 Mhz default Added clock divider for 2 4 8 output of which is routed externaly tothe i f clock input k k k K k k K n this file 6 RUN siganl polarity was changed to active high this to support other changes for revision PILOT of the fads Tn this file 5 added protection against spikes on the reset lines so that the interface will not be reset by an accidental spike D C signal was synchronized to avoid accidental write to control during data write DSDI is given value H prior to negation of SRESET to comply with 5XX family 113 Release 0 1 MPCSXXFADS User s Manual Support Information n this file 4 the polarity of address selection lines is reversed so that ON the switch represent address line at high and vice versa 1 s k gt F gt F k oF F F F Tn this 3 the is not reseted at all so it can be used to sync MPC8XX reset signals inside Added consideration for reset generated by the MPC8XX when
86. of MPC823 850 daughter boards connected to IP B7 signal of the MPC 99 GND 100 101 102 X DP3 IRQ6 Data line 3 or Interrupt Request 6 generate and receive parity data for D 24 31 bits connected to the DRAM SIMM May also be configured as IRQ6 input for the MPC 103 GND 104 BVS2 O X Buffered PCMCIA slot A Voltage Sense 2 In fact IP Used in conjunction with BVS1 to determine the operation voltage of a PCMCIA In case of MPC823 or MPC850 daughter boards connected to IP B1 signal of the MPC 105 GND 106 BCD1 O L Buffered PCMCIA slot A Card Detect 1 In fact IP_A4 Input Port 4 of PCMCIA slot A Used as Card Detect indication in conjunction with BCD2 In case of MPC823 or MPC850 daughter boards connected to IP_B4 signal of the MPC 107 GND 108 MODIN O X This signal selects between clock generator and the 32768 Hz crystal as clock sources for the MPC Its is driven by DS2 4 See 2 3 2 Clock Source Selection on page 15 109 GND 110 BBVD1 O X Buffered PCMCIA slot A Battery Voltage Detect 1 In fact IP_A6 Used in conjunction with BBVD2 to determine the battery status of a PC Card In case of MPC823 or MPC850 daughter boards connected to 6 signal of the 111 GND 112 BCD2 O L Buffered PCMCIA slot A Card Detect 2 In fact IP_A3 Input Port 3 of PCMCIA slot A Used as Card Detect indication in conjunction with BCD1 In case of MPC823 or MPC850 daugh
87. of this register is to provide safe clock transitions i e that a trasition will not cause races over the clockout E g in a transition between divide by 1 and divide by any bigger order a possible race may occur since the divided outputs are delayed with respect to DbgCIk Therefore a safe transition may be performed only when all clocks are LOW equations Cstr clk DbgClk Cstr ar Reset when SELECT CHANGE ALLOWED then Cstr DbgCIkDivSel fb else Cstr Cstr fb 127 Release 0 1 MPCSXXFADS User s Manual Support Information Clock selector Controlled by the CSTR sek F F F equations DbgClkOut oe 1 when DEBUG DIV 1 then DbgClkOut DbgClk else when DEBUG DIV BY 2 then DbgClkOut DbgCIkDivBy2 fb else when DEBUG CLOCK BY 4 then DbgClkOut DbgCIkDivBy4 fb else when DEBUG DIV BY 8 then DbgClkOut DbgClkDivBy8 fb k divided by 2 k KK k equations CIK2 clk ClkOut oe 3 ClkOut ar Reset Clk2 amp HOST IS ON divide by 2 Bundle delay timer This timer ensures data validity in the following casses 1 Host write to adi In that case AdsAck is
88. or the control register Acknowledge is released when the host removes its write control line HstReq The machine steps through these states 0 1 5 ACTIVE 1 ADS ACTIVE equations AdsAck clk AdsAck ar Reset AdsAck oe ADS IS SELECTED 5 HstReq clk DS HstReq clk S HstReq HstReq DS HstReq 5 HstReq fb amp HstReq double synced S_D_C clk ICIk synchronizing D C selector 129 Release 0 1 MPCSXXFADS User s Manual Support Information S D state diagram AdsAck state ADS ACK ACTIVE if HOST WRITE ADI CONTROL HOST WRITE ADI DATA amp PdaRst fb amp BndTmrExp fb then ADS ACK ACTIVE else ADS ACTIVE state ADS ACTIVE if DS HstReq fb HOST REQ ACTIVE then ADS ACTIVE else ADS ACTIVE Transmit Enable logic Enables transmit of serial data over DSDI and generation of serial clock over DSCK Transmission begins immediately after data written by the host is latched into the transmit shift register and ends after 7 shifts were made to the tx shift register Termination is done using a 4 bit counter TxWordLength which has a terminal count and reset Tx WordEnd kK K Kk K k K K K K K K equations TxEn ar Reset TxEn clk IClk to provide 1 2 clock reso
89. placed between positions 2 3 of J1 2 FRZ signal is selected FIGURE 2 3 J1 VELS FRZ Selection J1 J1 4 VFLS 0 1 Selected FRZ Selected 2 4 INSTALLATION INSTRUCTIONS When the MPC8XXFADS has been configured as desired by the user it can be installed according to the required working environment as follows Host Controlled Operation Debug Port Controller for Target System Stand Alone 2 4 1 Host Controlled Operation In this configuration the MPC8XXFADS is controlled by a host computer via the ADI through the debug port This configuration allows for extensive debugging using on host debugger 16 Release 0 1 MPCSXXFADS User s Manual Hardware Preparation and Installation FIGURE 2 4 Host Controlled Operation Scheme Host Computer 37 Wire Flat Cable P1 rca gk Bm 5V Power Suppl n p 2 5 H E um bs P6 4 icone P T BE Pal A 2 4 2 Debug Port C
90. reset i e no use is possible with the MPC s internal HARD reset configuration defaults The system parameters to which BCSRO defaults during power on reset and are driven at hard reset are listed below 1 Arbitration internal arbitration is selected 2 Interrupt Prefix The internal default is interrupt prefix at OxFFFOOOOO It is overridden to provide interrupt prefix at address 0 which is located within the DRAM 3 Boot Disable Boot is enabled 4 Boot Port Size 32 bit boot port size is selected 5 Initial Internal Space Base Immediately after HARD reset the internal space is located at FF000000 6 Debug pins configuration PCMCIA port Bo pins become PCMCIA port B pins 7 Debug port pins configuration Debug port pins are on the JTAG port 8 External Bus Division Factor 1 1 internal to external clocks frequencies ratio is selected 4 1 6 3 Soft Reset Configuration The rising edge of SRESET is used to configure the development port Before the negation of DSCKP is sampled to determine for debug mode enable disable After SRESET is negated if debug A The MODCK lines are in fact driven longer by HRESET line B With respect the FADS s power on defaults C Where they exist 37 Release 0 1 MPCSXXFADS User s Manual Functional Description mode was enabled DSCK is sampled again for debug mode entry non entry DSDI is used to determine the debug port clock mode and is sampled
91. s Bus Busy signal Pulled up on the FADS 2 VCC 3 DRM_W LL MPC s GPLO lines used as R W signal for the DRAM simm or as A10 line for the SDRAM 4 5V Bus 5 L Transfer Error Acknowledge Pulled up not driven on board O D 6 7 BR MPC s Bus Request signal Pulled up the FADS but otherwise unused 8 VCC 9 BURST L MPC s Burst indication Pulled on the FADS but otherwise unused 10 VCC 11 GPL4A XL UPMA general purpose line 4 Not used on the FADS 12 VCC 13 TA MPC s transfer Acknowledge signal Indicates end of bus cycle used with FADS logic 14 VCC 15 TS MPC s Transfer Start indication Pulled up but otherwise unused on the FADS 16 VCC 17 GPL5B O L General Purpose Line 5 of UPMB Not used on the FADS 18 VCC 19 BG I O L MPC s Bus grant signal Pulled up on the FADS but otherwise unused 20 VCC 21 GPL4B O L General Purpose Line 4 of UPMB Not used on the FADS 22 VCC 23 R_W L MPC s Read Write indication Pulled up on the FADS and used by FADS logic 24 VCC 82 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 8 PD1 Interconnect Signals Pin No Signal Name Attribute Description 25 BCSRCS L In fact CS1 of the MPC Used as chip select for the BCSRs Pulled up When BCSR is
92. station for target system D If necessary E Depended on dram SIMM s internal structure 38 Release 0 1 MPCSXXFADS User s Manual Functional Description ered Use is done with 74L CX buffers which are 3 3V operated and are 5V tolerant This type of buffers reduces noise on board due to reduced transitions amplitude To further reduce noise and reflections series resistors are placed over dram s address and strobe lines The data transceivers open only if there is an access to a valid P board address or during Hard Reset configuration That way data conflicts are avoided in case an off board memory is read provided that it is not mapped to an address valid on board It is the users responsibility to avoid such errors 4 5 Chip Select Generator The memory controller of the MPC is used as a chip select generator to access on board memories saving board s area reducing cost power consumption and increasing flexibility To enhance off board ap plication development memory modules including the BCSRx may be disabled via BCSR1F in favor of an external memory connected via the expansion connectors That way a CS line may be used off board via the expansion connectors while its associated local memory is disabled When CS region is disabled via BCSR1 the local data transceivers do not open during access to that region avoiding possible contention over data lines The MPC s chip selects assignment to the va
93. the RS232 transceiver for port 1 is in standby mode and the relevant MPC communication port pins are available for off board use via the expansion connectors R W PCCEN PC Card Enable When asserted low the on board PCMCIA channel is enabled i e address and strobe buffers are enabled to from the card When negated all buffers to from the PCMCIA channel are disabled allowing off board use of its associated lines R W 57 Release 0 1 MPCSXXFADS User s Manual Functional Description TABLE 4 10 BCSR1 Description BIT MNEMONIC Function DEF ATT 9 PCCVCCO Pc VCC Select 0 These signal in conjunction with PCCVCC1 0 RW determine the voltage applied to the PCMCIA card s VCC Possible values are 0 3 3 5 V For the encoding of these lines and their associated voltages see TABLE 4 11 PCCVCC 0 1 Encoding on page 59 10 11 0 PC Card VPP These signals determine the voltage applied to the PCMCIA 11 RW card s VPP Possible values are 0 5 12 V For the encoding of these lines and their associated voltages see TABLE 4 12 PCCVPP 0 1 Encoding on page 59 12 Dram Word Dram Half Word When this bit is active low and the steps listed 4 6 1 1 RW DRAM 16 Bit Operation on page 40 are taken the DRAM becomes 16 bit wide When inactive the DRAM is 32 bit wide 13 RS232bN 2 RS232 port 2 Enab
94. the board to seat the connector firmly Close the system unit Connect the 37 pin interface flat cable to the ADI board and secure Turn power on to the system unit and check for proper operation Release 0 1 tmp mnt net prince yair Bxx fads m brd pilot sch 1 drw 07 MAY 97 16 49 last updote 07 MAY 97 16 49 B D E F H KM416S1120A KM416S1120A 2 2 5 015 49 07 A4 0015 49 024 A5 00148 06 A5 14 48 022 A6 0013 46 m 6 001346 D21 0012 4 001246 020 ag 00118 03 A8 0911 ata cPLe A9 0010 A9 0010 DRM W A10 009 48 017 A11 008 A11 00839 016 e wav oo7l2 28 2 02 4 LDQM 006 006 nos 9 210 5 9 026 15 on 151 00418027 012 pose 028 iB les 0028213 18 lt pora _ 029 Wars poi 014 hess 0013 030 16 0082 015 2 031 060 54 ce 5 CLK 35 043 u23 WE2 0 31 5 CPL3 i SDRMCS EDOOE GPLI CPL2 1 SDRAMEN i 6 8 PROJECT MPCBXXFADS REV PILOT SHEET 1 14 ENG YAIR LIEBMAN BLOCK SDRAM CHK DESCRIP B C D E H mnt ne
95. when the MPC is removed from its socket avoiding possible conten tion over data bus lines 4 12 1 1 Debug Port Connection Target System Requirements In order for a target system may be connected to the FADS as a debug port controller few measures need to be taken on the target system 1 10 pin header connector should be made available with electrical connections matching FIG URE 4 8 Standard Debug Port Connector on page 71 2 Pull down resistors of app 1KQ should be connected over DSDI and DSCK signals These resistors are to provide normal operation when a debug port controller is not connected to the target system 3 The debug port should be enabled and routed to the desired pins See the DBGC and DBPC fields within the HARD RESET configuration word 41222 Debug Port Control Status Register The control status register is an 8 bit register bit 7 stands for MSB For the description of the ADI control A Remember that the location of DSDI and DSCK is determined by the HARD Reset configuration B Normal i e boot via CSO 69 Release 0 1 MPCSXXFADS User s Manual Functional Description status register see TABLE 4 24 Debug Port Control Status Register on page 70 TABLE 4 24 Debug Port Control Status Register BIT MNEMONIC Function VF Res et DEF ATT MpcRst Mpc Reset When this status only bit indicates when active high that either a SOFT or a HAR
96. when the next Hard Reset is issued to the MPC regardless of the Hard Reset source The description of BCSRO bits is shown in TABLE 4 9 BCSRO Description on page For the MPC823 daughter board B For the MPC860SAR daughter board C For the MPC860T daughter board D It may be written but will not be influenced E Provided that BCSR is not disabled F Le when VDDH to the MPC is powered 54 Release 0 1 55 MPCSXXFADS User s Manual Functional Description TABLE 4 9 BCSRO Description BIT MNEMONIC FUNCTION PON DEF ATT ERB External Arbitration When 0 during Hard Reset Arbitration is performed internally When 1 during Hard Reset Arbitration is performed externally R W IP Interrupt Prefix When 0 during Hard Reset Interrupt prefix set to OxFFF00000 if 1 Interrupt Prefix set 0 R W Reserved Implemented R W BDIS Boot Disable When 0 during Hard Reset 50 region is enabled for boot When 717 50 region is disabled for boot R W BPS 0 1 Boot Port Size Determines the port size for CSO at boot 00 32 bit 01 8 bit 10 16 bit 11 reserved 00 R W Reserved Implemented R W 158 0 1 Initial Space Base Value during Hard Reset determines the initial base address of the internal memory map When 00 initial space at 0 when 01 initial space at 0 00 00000 when 10
97. 00000 then INT SPACE BASE 0x00F00000 else if MPC WRITE BCSR 0 amp 15 DATA BIT pin INT SPACE BASE 0 00000 amp PON RESET ISB PON DEFAULT INT SPACE BASE OxFF000000 PON RESET amp ISB PON DEFAULT INT SPACE BASE 0 00000 then INT SPACE BASE OxFFF00000 else INT SPACE BASE OxFF000000 state INT SPACE BASE OxFFF00000 if WRITE BCSR 0 amp ISB DATA BIT pin INT SPACE BASE 0x00000000 amp PON RESET ISB PON DEFAULT INT SPACE BASE OxFFF00000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00000000 then INT SPACE BASE 0x00000000 Release 0 1 MPCSXXFADS User s Manual Support Information else if MPC WRITE BCSR 0 amp ISB DATA BIT pin INT SPACE BASE 0x00F00000 amp PON RESET ISB PON DEFAULT INT SPACE BASE OxFFF00000 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00F00000 then INT SPACE BASE 0x00F00000 else if MPC WRITE BCSR 0 amp ISB DATA BIT pin INT SPACE BASE OxFF000000 PON RESET ISB PON DEFAULT INT SPACE BASE OxFFF00000 KA PON RESET ISB PON DEFAULT INT SPACE BASE 0 000000 then INT SPACE BASE 0 000000 else INT SPACE BASE 0 00000 state diagram DBGC state DEBUG PINS PCMCIA 2 if MPC WRITE 5 0 amp DBGC DATA BIT pin DEBUG PINS WATCH POINTS amp PON RESET DBGC P
98. 1 8W TYOHM 1206 OE 1 R92 R93 R94 R95 C6 R43 Resistor 510 1 SMD 1206 BOURNS CR1206 JW 472bE 1 8W R49 R52 R55 R56 R62 R82 R96 Resistor 150 5 SMD 1206 1 BOURNS CR1206 JW 151 E R97 R100 R101 R79 Resistor 5 1 KO 196 SMD 1206 RODERSTEIN D25 5K1 FCS 1 8W R86 Resistor 47 KO 1 SMD 1206 KYOCERA CR32 473JT 1 8W RN1 RN2 RN4 RN5 RN8 RN9 Resistor Network 10 KO 596 13 DALE SOMC 14 01 103J RN10 resistors 14 pin RN3 Resistor Network 22 0 596 8 16 03 220J resistors 16 pin RN6 RN7 Resistor Network 75 0 596 8 BOURNS 4816P 001 750J resistors 16 pin SK1 Speaker piazo Sealed SOUNDTECH SEP 1162 Swi SPDT push button BLACK C amp K KS12R23 CQE Sealed SW2 SPDT push button RED Sealed C amp K KS12R22 CQE T1 T2 T3 Transistor TMOS Dual 3A Motorola Release 0 1 110 MPCSXXFADS User s Manual Support Information TABLE 5 12 MPC8XXFADS Part List Reference Designation Part Description Manufacturer Part U1 Infra Red Transceiver Telefunken TFDS3000 U2 U11 022 MACH220 10 programmable AMD 220 10 logic device U3 10 Base T Filter network Pulse PE 68026 Engineering 04 Enhanced Ethernet Serial Motorola MC68160FB Transceiver 05 06 85232 Transceiver 3 X 3 Motorola MC145707DW 07 4 MByte EDO DRAM SIMM Motorola MB321BTO8TASN60 organ
99. 13 31 Reserved Un implemented a Shaded areas are additions with respect to the MPC8XXFADS b MPC823 Daughter Board function c MPC860T Daughter Board function d Le on the negative edge 4 12 Debug Port Controller The debug port of the MPC8XXFADS is implemented on board connected to the MPC via the JTAG port Since the location of the debug port is determined via the Hard Reset configuration It is important that the relevant configuration bits see 4 1 6 Reset Configuration on 37 are not changed if working with the local debug port is desired The debug port controller is interfaced to host computer via Motorola s ADI port which is an 8 bit wide parallel port Since the debug port is serial conversion is done by hardware between the parallel and serial protocols The MPC s debug port is configured at SOFT Reset to Asynchronous Clock Mode i e the debug port generates the debug clock DSCK which is asynchronous with the MPC system clock The debug port controller block diagram is shown in FIGURE 4 7 Debug Port Controller Block Diagram on page 68 A The debug port location is determined by the HARD Reset configuration B In terms of MPC pins 67 Release 0 1 MPCSXXFADS User s Manual Functional Description FIGURE 4 7 Debug Port Controller Block Diagram ADI Port Connector Debug Port Conn Daughter Board Connector
100. 2 9 BA20 1360 5012 PCCA11 BA28 13 40 5012 PCCAS 14160 60 19 BA13 14 20 60115 21 1460 6018 PCCA10 8429 14 60 6015 PCCA2 12120 7016 1720 70 16 22 1713 70 16 9 50 17 3 70 16 PCCA1 18188 20119 18 ap 20119 16 25 18 ap go 9 PCCAB 18 ap 8019 11 c 11 11 ttle 1 OC 1 1 1 WADE CR U16 U36 ut ug 0 25 PCCVPP PCCD 0 15 PCCVCC 1 90 CQ j O pecao 29 58 88 030 26608 28 gt gt gt gt 441351 PCCDI 74ACT245 74ACT245 PCCA2 27 po 32 Pcco2 RDY 1851 A1 2 _ PCCDO 8015 18 61 1 2 Pccpa 26 os 2 PCCD3 w _ 8x 580001 8514 1752 2 3 PCCD9 PCCA4 251 4 p4 3 04 az 2 8015 1663 4 010 PCCAS 241 6 05 4____ 05 INPACK B4 48 PCCD3 8012 1684 4415 PCCD11 pecas 231 6 De 5 Pccb6 vst as A5 6 PCCD4 801 14 55 gle PCCD12 PCCA7 2245 7 6 PCCD7 VS2 86 ag Z PCCDS 8010 136 ag Z PCCD13 pecas 12 BVD1 87 A7 8 _PCcCD6 4282 ay 8 PCCD14 pecao 11146 0884 Pecos 02 9 BD8 1188 Ag 9 PCCD15 PCCA10 81 16 09 65 __ 9 CD2 oig PCCA11 101 11 010166 018 01 c 19 PCCA12 211 19 11 37_ 11 PCCA13 13 4 012158 12 SEEN U34 U32 141 4 n13 32 PCCDI3 20 40 PCCD14 A15 D14 74LCX541 PCOEN PCCAT6 19 pig 41 PCCDTS x
101. 3 E tn our Ven a 03 Our LS our els 124K 3 gt 75 gt R39 P6 4D 3 ot 5 I TAB IS GROUNDED GND lt 2 VPPIN 2 ke ZAMMDF3NO3HD lt AVCCIN G FUSE 18 8 2 BVCCIN BSHDN x 5 2 1 PCCVPP I 5 25 L PCCVC i F1 1A TERS MBRD620CT 6 avec 19 3 20 2 ADRV3 Bl Dvds 1 n QUE 1UF Le 1uF 02 B 74 14 LTC1315 N C4 cio 2 17 v Y I 2 BDRV5 12 ORM3V 128 BEN BDRV3 MMDF3N0O3HD 1 3 BEN1 a Cl GND 5 130 1 R83 vec 5 Sno E L4 4 74 14 RUN 1 LED GREEN 15 w RUN qu 2 R PORIP Ep 2 4 5V POWER via vcc 1011 V3 V3 3 1246 x 7K R22 055 2102 74 14 74LCX125 LED YELLOW gt R86 5 SDRAMEN 5 6 as Ag wE S 8052ANY NH X lt 74 714 12 fer 4 1016 2 7 200 RESETE ie R_PORI EE 028 2 595 5 2 805 Tle 126 d DRMPWR LED_GREEN 150 uae i dae lt BELT A SIGNAL LAMP 2 58 1013 65 0402 LED YELLOW PRAET DRAM ON ROT TET MDF3N JHD 6 15 2 2 pt 4 V L Re Sag
102. 32 bit port size no parity GPCM supported 30 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS TABLE 3 6 Memory Controller Initializations For 20Mhz Register Device Type Init Value hex Description ORO 29 020 90 0020 2MByte block size all types access CS early negate 2 w S 29 040 90 FFCOOD20 4 block size all types access CS early negate SM732A1000A 9 2 5 29 080 90 FF800920 8MByte block size all types access CS early negate SM732A2000 9 2 w s Timing relax MCM29F020 12 FFEO0D30 2MByte block size all types access CS early negate 3 w s MCM29F040 12 FFCOODS30 4 block size all types access CS early negate SM732A1000A 12 W S MCM29F 080 12 FF800930 8MByte block size all types access CS early negate SM732A2000 12 w s BR1 BCSR 02100001 Base at 2100000 32 bit port size no parity GPCM OR1 FFFF8110 32 KByte block size all types access CS early negate 1 w s BR2 All Dram SIMMs 00000081 Base at 0 32 bit port size no parity UPMA Supported OR2 MB321 2BTO8TASN60 FFCO00800 4MByte block size all types access initial address multiplexing according to AMA MB324 8CTOOTBSN60 FF000800 16MByte block size all types access initial address multiplexing according to AMA MB322BT08TASN60 00400081 Base at 400000 32 bit port size no parity UPMA MB328C
103. 32En1 state RS232 1 ENABLE if MPC WRITE BCSR 1 amp RS232 1 ENABLE DATA BIT pin RS232 1 ENABLE amp PON RESET RS232 1 ENABLE PON DEFAULT RS232 1 KA PON RESET amp RS232 1 ENABLE PON DEFAULT RS232 1 then 185232 1 ENABLE else RS232 1 ENABLE state RS232 1 ENABLE if MPC WRITE BCSR 1 amp RS232 1 ENABLE DATA RS232 1 ENABLE amp PON RESET RS232 1 ENABLE PON DEFAULT RS232 1 KA PON RESET amp RS232 1 ENABLE PON DEFAULT RS232 1 then RS232 1 ENABLE else 5232 1 ENABLE tk sk sk sk ok sk sk kok ak state diagram PccEn state PCC ENABLE if MPC WRITE BCSR 1 amp PCC ENABLE DATA BIT pin PCC ENABLE amp PON RESET ENABLE PON DEFAULT ENABLB KA PON RESET amp ENABLE PON DEFAULT PCC_ENABLE then ENABLE else PCC ENABLE state PCC ENABLE if MPC WRITE BCSR 1 amp ENABLE DATA BIT pin ENABLE amp 169 Release 0 1 MPCSXXFADS User s Manual Support Information PON RESET ENABLE PON DEFAULT PCC_ENABLE PON RESET amp ENABLE PON DEFAULT ENABLE then PCC ENABLE else ENABLE state diagram 0 state CONT 0 if WRITE BCSR 1 amp PCC VCC 0 DATA BIT pin PCC VCC CONT 0 amp PON RESET
104. 400 SIMM36800 amp IS HALF WORD then 195 Release 0 1 MPCSXXFADS User s Manual Support Information DramAdd10 A30 else 10 0 k K KK K K K K K K K K RAS generation Since the dram simm requires RAS signals to be split due to high capacitive load and to allow 16 bit operation When working with 16 bit port size the double drive RAS signals are disabled equations RAS oe hf IRas1 DramBank1Cs amp DramBank2Cs amp DRAM ENABLED Ras2 DramBank2Cs amp DramBank1Cs amp DRAM ENABLED amp SIMM36200 SIMM36800 IRasIDD DramBank1Cs amp DramBank2Cs amp DRAM ENABLED Ras2DD DramBank2Cs amp DramBank1Cs amp DRAM ENABLED amp SIMM36200 SIMM36800 Flash Chip Select k kK kk K k KK k K K K equations FlashCsOut oe hf FlashCs1 FLASH ENABLED amp FlashCs amp FLASH BANKI FlashCs2 FLASH ENABLED amp FlashCs amp FLASH BANK2 FlashCs3 FLASH ENABLED amp FlashCs amp FLASH BANK3 HashCs4 FLASH ENABLED amp FlashCs amp FLASH BANKA FlashOe oe H FlashOe FLASH ENABLED amp R_W K kk K k KK k KK k Auxiliary functions k K K K equations 196 Release 0 1 MPCSXXFADS User s Manual Support Information KeepPinsConnected TA end
105. 413 3 12V Bus The sole purpose of the 12V bus is to supply VPP programming voltage for the PCMCIA card and for the Flash SIMM It is connected to a dedicated input connector via a fuse 1A and protected from over reverse voltage application If the 12V supply is not required for either the PC Card and for the flash SIMM the 12V input to the FADS may be omitted A At full speed When lower performance is needed the internal logic may be powered from the 2V bus B If necessary 74 Release 0 1 MPCSXXFADS User s Manual Support Information 5 Support Information In this chapter all information needed for support maintenance and connectivity to the MPC8XXFADS is provided 5 1 Interconnect Signals The MPC8XXFADS interconnects with external devices via the following set of connectors O 9 P1 ADI Port connector PA2 RS232 port 1 PB2 RS232 port 2 P3 Ethernet port P4 PCMCIA port P5 External Debug port controller input output P6 5V Power In P7 12V Power In P8 Serial Ports Expansion connector 10 PD1 PD2 PD3 amp PD4 Daughter Board Connectors P1 ADI Port Connector The ADI port connector P1 is a 37 pin Male 909 D Type connector signals of which are described in TABLE 5 1 P1 ADI Port Interconnect Signals below TABLE 5 1 P1 ADI Port Interconnect Signals 5 1 1
106. 47 MPCSXXFADS User s Manual Functional Description FIGURE 4 4 SDRAM Connection Scheme CS4 CS CS GPL RAS RAS GPL AS CAS GPL3 W A10 ____ _ 11 GPLO A11 m n 20 21 9 8 9 8 22 29 7 0 7 0 SDRAMEN kp CKE J SYSUIK ik CLK BS0B B DQML DQ 15 0 DQ 15 0 D 0 15 BS2 B BS3 B D 16 31 4 8 1 SDRAM Programming After power up the sdram needs to be initialized by means of programming to establish its mode of oper ation The Sdram is programmed by issuing a Mode Register Set command During that command data is passed to the Mode Register through the Sdram s address lines This command is fully supported by the UPM by means of a dedicated Memory Address Register and the UPM command run option Mode Register programming values are shown in TABLE 4 7 SDRAM s Mode Register Programming Release 0 1 48 below 4 8 1 1 MPCSXXFADS User s Manual Functional Description TABLE 4 7 SDRAM s Mode Register Programming Value Frequency SDRAM Option 50MHz 25MHz Burst Length 4 4 Burst Type Sequential Sequential CAS Latency 2 1 Write Burst Length Burst Burst SDRAM Initializing Procedure After Power up the SDRAM needs to be initialized in a certain manner described below 1 4 8 2 UPMB should be programmed wit
107. 6004025 41612 909 WW PD1 PD2 PD4 Connector Board to Board 140 MOLEX 52760 1409 pin receptacle SMD R1 Resistor 10 0 1 SMD 1206 1 RODERSTEIN D25 10R FCS R2 R15 R44 R48 R50 R51 R57 Resistor 1 KO 5 SMD 1206 1 AVX CR32 102F T R4 R80 Resistor 2 kO 196 SMD 1206 1 BOURNS CR1206 FX 2001E R5 R21 R31 Resistor 100 0 1 SMD 1206 1 RODERSTEIN D25 100R FCS 109 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 12 MPC8XXFADS Part List Reference Designation Part Description Manufacturer Part R6 R53 R54 R63 R64 R70 R71 Resistor 75 5 SMD 1206 1 DRALORIC CR1206 100 75RJ R72 R73 ew R7 R8 R9 R18 R24 R25 R26 Resistor 10 KO 196 SMD 1206 RODERSTEIN D25 010K FC5 R27 R28 R29 R35 R36 R37 R38 1 8W R41 R42 R47 R58 R59 R60 R61 R66 R67 R74 R81 R84 R85 R87 R88 R89 R90 R91 R98 R99 R10 R11 R12 R14 R19 Resistor 330 5 SMD 1206 RODERSTEIN D25 332R FC5 1 8W R13 Resistor 243 0 1 SMD 1206 1 RODERSTEIN D25 243R FCS R16 R17 R20 Resistor 22 0 5 SMD 1206 1 RODERSTEIN D25 24R FCS 8W R22 R23 R39 R40 Resistor 124 KO 596 SMD 1206 RODERSTEIN D25 124K FCS 1 8W R30 Resistor 294 O 196 SMD 1206 TYOHM RMC 1206 294E 196 1 8W R32 R33 Resistor 39 1 0 1 SMD 1206 TYOHM RMC 12061 8W 39E 1 8W 342 R65 R75 R76 R77 R83 Resistor 0 Q SMD 1206
108. 63 104 DBID2 X Daughter Board ID Code 2 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 63 105 BCSR3R13 X Reserved signal 13 in BCSR3 See TABLE 4 19 BCSR3 Description on page 63 106 DBID4 X Daughter Board ID Code 4 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 63 107 CHINS L Chip In Socket When this signal is active low FADS logic is noticed that the evaluated MPC8XX resides in its socket If inactive either the MPC is out of socket or a daughter board is not connected in which case the FADS becomes a debug station 108 GND 109 110 N C 111 112 GND 113 114 N C 115 116 GND 117 118 N C 119 120 GND 121 122 N C 123 124 GND 125 126 N C 127 106 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 11 PD4 Interconnect Signals Pin No Signal Name Attribute Description 128 GND 129 130 N C 131 132 GND 133 134 N C 135 136 GND 137 138 N C 139 140 GND 107 Release 0 1 5 2 MPCSXXFADS User s Manual Support Information MPC8XXFADS Part List In this section the MPC8XXFADS s bill of material is listed according to their reference designation TABLE 5 12 MPC8XXFADS List
109. 7ALCX541 741 541 74LCX541 74LCX541 A6 2 v 18 8 6 2 4 18 Bag 16 ya Baie A22 2 1118 22 A7 3 A8 vo 17 17 yo 17 BA17 A23 3 2 17 21 ajas 16 10 alaz va 16 0 A18 alaz 3 16 18 24 ajag 3116 24 POE A 5 val 15 BPOE A A11 Slaa 05 19 5 vali amp BA19 25 Slaa ya 15 BA25 ALE_A elas 5 14 BALE A 12 9514 12 20 6 5 5 14 20 26 6 5 14 8426 4 EDOOE 7 ve 3 BEDOOE J A13 7146 y 3 13 21 7146 velii 21 27 7146 veli 27 8 7 712 14 alaz 7112 14 A30 alaz y7 12 0 A28 ala7 9712 BA28 CE2A Slag 11 BCE2A A15 9 valli A31 valli BAS 29 1 BA29 1 1 1 1 19 5 19 19 75 19 e GND GND GND GND 012 014 013 015 BA 6 31 DRMAB L gt 5 2 Rea 74LCX541 A29 2 18 1 15 16 74LCXB41 AT Y1 2 m A28 5207 2 15 DRMA1 A1 27 3 16 3 14 _ DRMA2 A2 Y2 26 15 4 13 DRMAS A4 YA RU 1 2 ys Hg W SPKROUT 2 3 HSPKOUT gt 25 alie 4 5 12 DRMAA x 4 Y4 ANP 1 24 7 15 6 11 DRMAB TEA 6 14 R55 6 Y6 345 Mir 28 23 alay y7 12 7 10 DRMAG 6 Y6 6 R_w 8147 7 12 __ 1 22 ve H 5 BM 27 Gi var gt 19 c5 Je CND 1
110. 8 devices by Intel The flash SIMM resides on an 80 pin SIMM socket To minimize use of MPC s chip select lines only one chip select line CSO is used to select the flash as a whole while distributing chip select lines among the internal banks is done via on board programmable 44 Release 0 1 MPCSXXFADS User s Manual Functional Description logic according to the Presence Detect lines of the Flash SIMM inserted to the FADS FIGURE 4 3 Flash Memory SIMM Architecture Flash Presence Detect Lines M29F040 M29F040 or M29F040 M29F040 or 1MX8 1M X8 1MX8 1 8 MEA or M29F040 M29F040 M29F040 M29F040 M29F040 29 080 me The access time of the Flash memory provided with the FADS is 90 nsec however 120 nsec devices may be used as well Reading the delay section of the Flash SIMM Presence Detect lines the debugger tablishes via ORO the correct number of wait states considering 50MHz system clock frequency CS2 29 040 or cso FADS s Logic F CS3 29 040 29 040 29 040 29 020 29 040 5 73218 5 73228 The Motorola SIMMS built of 5 Am29F0X0 devices which programmable i e there is no need for external programming voltage and the flash may be written almost as a regular memory The SMART parts how
111. 952 035 CND DRMA 0 8 U38 0 8 V EXTOLI 0 3 Poem 1 75 BWE 3 7 A1 1 8 EXTOL Ax op 2 15 BWE2 5 a3 3 E TRE i exon 4 15 4 13 BBS2A B3 4 Y4 5 15 SEO 84 5 EXTOUS _ A5 5 14 6 11 BBSQA a Ag CY 2 7 10 BBS SA GND age valti 8 9 BBS1A a S W OPTIONS SELECTOR MOTOROLA INC 8 m PROJECT MPC amp XXFADS REV PILOT SHEET 2 OF 14 U37 ENG YAIR LIEBMAN BLOCK CHK DESCRIP ADDRESS DATA amp STROBE BUFFERS B D E F G H J K tmp_mnt net prince yair 8xx fads m brd pilot sch 3 drw 07 MAY 97 16 54 last updote 07 MAY 97 16 51 A B C D E F G J K 220 ite Memory amp
112. ASSERTED only after that timer expired 2 Host read from adi In that case AdsReq is NEGATED after that timer expired ensuring enough time for data propgation over the bundle The timer is async reset when both soft and hard reset is applied to the i f timer is sync reset a clock after it expires Count starts when either HstReq or HstAck are detected asserted after proper synchronization value upon which the terminal count is assereted is in the control register When the interface is reset by the host this value defaults to its upper bound Using the diagnostic loop back mode this value may be re established for optimal performance by means of test amp error 128 Release 0 1 MPCSXXFADS User s Manual Support Information equations BndDly ar Reset BndDly clk when HOST WRITE ADI CONTROL HOST READ ADI CONTROL HOST WRITE ADI DATA HOST READ ADI DATA amp PdaRst fb amp BndTmrExp fb then BndDly BndDly fb 1 else BndDly 0 BndTmrExp BndDly fb BUNDLE DELAY amp AdsAck delay field active low AdsAck Host write to ads ack This state machine generates an automatic ADS during a host to ADS write When the host access the ADS data control register an automatic acknowledge is generated after data has been latched into either the tx shift register
113. AdsAddr2 AdsAddr1 AdsAddr0 AdsRst AdsHardReset AdsSoftReset Rst PdaHardReset PdaSoftReset ClkOut CIK2 DbgClkDiv DbgCIKkDivBy8 DbgCIkDivBy4 DbgCIkDivBy2 DbgClkDivSel DbgCIkDivSell DbgCIkDivSel0 Cstr Cstr1 Cstr0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 VFLS VFLSO VFLS1 VflsP VflsPO VflsP 1 BndDly BundleDelay1 BundleDelay0 bundle delay compensation timer TxReg TxReg7 TxReg0 RxReg TxReg6 TxReg5 TxReg4 TxReg3 TxReg2 TxReg1 TxReg0 RxReg0 AdiCtrlReg DbgCIkDivSell DbgClkDivSel0 StatusRequest DiagLoopBack DebugEntry AdiStatReg PdaRst TxError nDebugMode DbgCIkDivSell DbgClkDivSel0 StatusRequest DiagLoopBack DebugEntry TxWordLen TxWordLen3 TxWordLen2 TxWordLen1 TxWordLen0 PortEn AdsSel2 AdsSel1 AdsSel0 AdsAddr2 AdsAddr1 AdsAddr0 HostVcc HstEn k k Select Logic definitions K K K K HOST VCC ACTIVE 1 HOST ACTIVE 0 HOST IS ON HstEn HOST ACTIVE amp HostVcc HOST VCC ACTIVB HOST IS OFF HOST IS ON BOARD IS SELECTED 0 ADS IS SELECTED AdsSelect fb BOARD IS SELECTED Data Cntrl line levels 121 Release 0 1 MPCSXXFADS User s Manual Support Information DATA 1 CONTROL DATA Reset Logic definitions ADS HARD RESET l ADS SOFT RESET AC
114. BCSR 4 amp USB SPEED DATA USB SPEED amp PON RESET 4 USB SPEED PON DEFAULT 05 FULL SPEED KA PON RESET amp USB SPEED PON DEFAULT USB FULL SPEED then USB FULL SPEED else USB FULL SPEED k k state diagram UsbVccO state USB CONT 0 if MPC WRITE BCSR 4 amp USB 0 DATA BIT pin VCC CONT 0 amp PON RESET USB 0 CONT PON DEFAULT USB CONT 0 KA PON RESET amp USB VCC 0 CONT PON DEFAULT USB VCC CONT 0 then VCC CONT 0 else USB VCC CONT 0 state USB CONT 0 if MPC WRITE BCSR 44 USB VCC 0 DATA BIT pin VCC CONT 0 amp PON RESET USB 0 CONT PON DEFAULT USB CONT 0 KA PON RESET amp USB 0 CONT PON DEFAULT USB VCC CONT 0 then USB VCC CONT 0 else IUSB CONT 0 sek sk eoe se F coke ok state diagram UsbVccl state USB CONT 0 if MPC WRITE BCSR 4 amp 174 Release 0 1 MPCSXXFADS User s Manual Support Information USB 1 DATA BIT pin USB CONT 0 amp PON RESET USB 1 CONT PON DEFAULT USB CONT 0 st PON RESET amp USB 1 CONT PON DEFAULT USB CONT 0 then CONT 0 else USB VCC CONT 0 state USB VCC CONT 0 if WRITE BCSR 44 USB VCC 1 DATA BIT pin
115. CSR base address BCSR3 gets its defaults during Power On reset and may be read or written at any time The de 62 Release 0 1 MPCSXXFADS User s Manual Functional Description scription of BCSR3 is shown in TABLE 4 19 BCSR3 Description on page 63 TABLE 4 19 BCSR3 Description BIT MNEMONIC Function PON DEF ATT 0 1 Reserved Implemented 00 2 7 DBID 0 5 Daughter Board ID This field holds a code for the daughter board ID Each Daughter board carries a unique ID code For the specific daughter boards codes see TABLE 4 20 Daughter Boards ID Codes on page 63 5a CNT REG EN P ROTECT Control Register Enable Protect When this bit is active low the BCSR EN bit in that register can not be written When in active BCSR EN may be written to remove the BCSR from the memory map After any write to BCSR1 this bit becomes active again This bit is write only bit on that register Reserved Un Implemented BREVNO Board Revision Number 0 This is the MS bit of the Board Revision Number See TABLE 4 18 MPC8XXFADS Daughter Boards Revision Encoding on page 62 for the interpretation of the Board Revision Number 9 11 FLASH PD 7 5 Flash Presence Detect 7 5 These lines are connected to the Flash SIMM presence detect lines which encode the Delay of Flash SIMM mounted on the Flash SIMM socket U15 There are additional 4 presence detect lines whic
116. CT PON DEFAULT REG EN PROTECT then REG EN PROTECT else CNT REG EN PROTECT state REG EN PROTECT if WRITE 3 amp REG EN PROTECT DATA BIT pin CNT EN amp PON RESET REG EN PROTECT PON DEFAULT CNT REG EN PROTECT PON RESET amp REG EN PROTECT PON DEFAULT CNT REG EN PROTECT WRITE BCSR 1 then any write to control reg 1 CNT REG EN PROTECT else ICNT REG PROTECT protected by CntRegEnProtect to prevent from inadvertant write state diagram CntRegEn state CONT REG ENABLE if WRITE 1 amp CntRegEnProtect fb CNT EN 4 CONT REG ENABLE DATA BIT pin REG ENABLE 4 PON RESET CONT REG ENABLE PON DEFAULT CONT REG ENABLB PON RESET amp CONT REG ENABLE PON DEFAULT REG ENABLB then ICONT REG ENABLE else 168 Release 0 1 MPCSXXFADS User s Manual Support Information CONT REG ENABLE state CONT REG ENABLE in fact not applicable if WRITE BCSR 1 amp CONT REG ENABLE DATA BIT pin CONT REG ENABLE amp PON RESET CONT REG ENABLE PON DEFAULT CONT REG ENABLB KA PON RESET amp CONT REG ENABLE PON DEFAULT CONT REG then CONT REG ENABLE else REG ENABLE k sk sk sk sk sk 9k 9k oR 9k I kok k kok ak state diagram RS2
117. CTIONS Width 32 Bit 16 Bit Depth Depth Dram ADD 4M 1M 4M 1M 0 29 29 29 29 1 28 28 28 28 2 27 27 27 27 26 26 26 26 4 25 25 25 25 5 24 24 24 24 BA23 BA23 BA23 BA23 A7 BA22 BA22 BA22 BA22 A8 21 21 21 21 9 20 20 20 0 10 19 0 As can seen from the table above most of the address lines remain fixed while only 2 lines the shaded cells need switching The switching scheme is shown in FIGURE 4 2 DRAM Address Lines Switching Scheme on page 44 The switches on that figure are implemented by active multiplexers controlled by the BCSR1 Dram Half Word bit A Consequent addresses lead to adjacent memory cells 43 Release 0 1 MPC8XXFADS User s Manual Functional Description FIGURE 4 2 DRAM Address Lines Switching Scheme DRAM BA 21 29 BA20 19 4 7 Flash Memory SIMM The MPC8XXFADS is provided with 2Mbyte of 90 nsec flash memory SIMM the MCM29020 by Motorola Support is given also to 4MBytes MCM29F040 8 MBytes MCM29F080 4 MBytes 5 73218 and to 8 MBytes SM73228 by Smart Technology The Motorola SIMMs are internally composed of 1 2 or 4 banks of 4 Am29F040 compatible devices while the Smart SIMMs are arranged as 1 or 2 banks of four 28F00
118. D reset is driven by the MPC TxError Transmit Error When this status only bit is active high it indicates that the last transmission towards the MPC was cut by an internal MPC8XX reset source This bit is updated for each byte sent InDebug In Debug Mode When this status only bit is active high it indicates that the MPC is in debug mode DebugClockFreq Debug Clock Frequency Select This field controls a frequency divider which divides DSCK For the division factors and associated DSCK frequencies see TABLE 4 25 DSCK Frequency Select below 00 R W StatusRequest Status Request When the host writes this bit active low the I F will issue a status read request to the host by asserting ADS_REQ line to the host When the host writes the control register with this bit negated no status read request is issued Upon I F reset this bit wakes up active R W DiagLoopBack Diagnostic Loopback Mode When this control bit is active low the I F is placed in Diagnostic Loopback Mode l e DSDI is connected internally to DSDO 0501 is tri stated and each data byte sent to the data register is sampled back into the receive shift register This mode allows for complete ADI I F test upto transmit and receive shift registers Upon reset this bit wakes up active R W DebugEntry Debug Mode Entry When this bit is active low the MPC will enter debug mode instantly after SO
119. DS User s Manual Hardware Preparation and Installation 2 Hardware Preparation and Installation 241 INTRODUCTION This chapter provides unpacking instructions hardware preparation and installation instructions for the MPC8XXFADS 2 2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt request carriers agent to be present during unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are present Save packing material for storing and reshipping of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY STATIC DISCHARGE DAMAGE CIRCUITS 2 3 HARDWARE PREPARATION To select the desired configuration and ensure proper operation of the MPC8XXFADS board changes of the Dip Switch settings may be required before installation The location of the switches LEDs Dip Switches and connectors is illustrated in FIGURE 2 1 The board has been factory tested and is shipped with Dip Switch settings as described in the following paragraphs Parameters can be changed for the following conditions ADI port address Clock Source Power On Reset Source Keep Alive Power Source e Internal Logic Supply Source Debug Mode Indication Source 13 Release 0 1 MPCSXXFADS User s Manual Hardware Preparation and Installation FIGURE 2 1 MPC8XXFADS Top Side Part Location diagram
120. Dip Switch This switch is connected over EXTOLI 0 3 lines which are available at BCSR S W options may be manually selected according to DS1 state FIGURE 3 1 DS1 Description EXTOLIO Pulled 7 EXTOLIO Driven to 0 EXTOLI1 Pulled to 1 EXTOLI1 Driven to 0 EXTOLI2 Pulled to 1 EXTOLI2 Driven to 0 Pulled to 1 EXTOLI3 Driven to 0 0 1 3 2 5 GND Bridges There are 3 GND bridges on the MPC8XXFADS They are meant to assist general measurements and 22 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS logic analyzer connection Warning When connecting to a GND bridge use only INSULATED GND clips Failure in doing so might result in perma nent damage to the MPC8XXFADS 3 2 ETH ON LD1 When the yellow ETH ON led is lit it indicates that the ethernet port transceiver the MC68160 EEST is active When it is dark it indicates that the EEST is in power down mode enabling the use of its asso ciated SCC pins off board via the expansion connectors 3 2 7 LD2 When the yellow IRD ON led is lit it indicates that the Infra Red transceiver the 0 56000 is active and enables communication via that medium When it is dark the transceiver is in shutdown mode enabling the use of its associated SCC pins off board via the expansion connectors 3 2 8 65232 Port 1 ON 103 When the yellow 85232 Port 1 ON led is lit it des
121. E amp HstReq z HOST REQ ACTIVE amp D DATA Vfls Frz select definitions CHIP SOCKET 0 CHIP IS IN SOCKET ChinS CHIP IN SOCKET oe Equations state diagrams k k k k K Kk k Kk K HHHO H HHHH HHHO H HHH 8 HH Ogg AHHH HHE H H H HHH HEHHEHE HHHH dg H dg Wo gg HOS Ho Hg og H H HEHE HHEH 1 HHH K k K K k K K K 125 Release 0 1 MPCSXXFADS User s Manual Support Information AdsSelect ADS selection indicator At low state when host accesses ADS equations AdsSelect HOST IS ON amp AdsSel AdsAddr AdsAddr is already inverted k kk k kk k K kk K k KK k KK k Internal Logic Reset K kk K Kk Kk K K K K K K K K equations PrimReset HOST_IS_OFF internal logic reset AdsHardReset ADS_HARD_RESET_ACTIVE amp AdsSoftReset ADS_SOFT_RESET_ACTIVE amp ADS IS SELECTED D PrimReset PrimReset fb DD PrimReset D PrimReset fb Reset PrimReset fb amp D PrimReset fb amp DD PrimReset fb spike filter
122. E Pin 26 on the ADI is connected to 12 v power supply but it is not used in the MPC281ADS 1 ADI Port Signal Description The ADI port on the MPC281ADS was slightly modified to generate either hard reset or soft reset This feature was added to comply with the MPC s reset mechanism In the list below the directions O and l O are relative to the MPC8XXFADS board I E means input to the MPC8XXFADS NOTE Since the ADI was originated for the DSP56001ADS some of its signals throughout the boards it was used with were designated with the prefix ADS This convention is kept with this design also ADS SEL 0 2 1 198 Release 0 1 MPCSXXFADS User s Manual Support Information These three input lines determine the slave address of the MPC8XXFADS being accessed by the host computer Up to 8 boards can be addressed by one ADI board ADS_SRESET F This input is used to generate Soft Reset for the MPC When ads is selected and this line is asserted by the host computer Soft Reset will be generated to the MPC along with the Soft Reset configuration applied during that sequence HOST ENABLE This line is always driven low by the ADI board When an ADI is connected to the MPC8XXFADS this signals enabled the operation of the debug port controller Otherwise the debug port controller is disabled and its outputs are tri stated ADS I When host is connected this line is us
123. EFAULT DEBUG FOR SHOW then DEBUG PINS FOR SHOW else DEBUG PINS WATCH POINTS state PINS RESREVED if WRITE 0 amp DBGC DATA BIT pin DEBUG PINS PCMCIA 2 amp PON RESET PON DEFAULT DEBUG PINS RESREVED KA PON RESET amp DBGC PON DEFAULT DEBUG PINS PCMCIA 2 then DEBUG PINS PCMCIA 2 else if MPC WRITE BCSR 0 amp DBGC DATA PINS WATCH POINTS 4 PON RESET PON DEFAULT DEBUG PINS RESREVED KA PON RESET amp DBGC PON DEFAULT DEBUG PINS WATCH POINTS then DEBUG PINS WATCH POINTS else if MPC WRITE BCSR 0 amp DBGC DATA BIT pin DEBUG PINS FOR SHOW amp PON RESET DBGC PON DEFAULT DEBUG PINS RESREVED KA PON RESET amp DBGC PON DEFAULT DEBUG PINS SHOW then DEBUG PINS FOR SHOW else DEBUG 5 RESREVED state DEBUG PINS SHOW if WRITE BCSR 0 amp DBGC DATA BIT pin DEBUG PINS PCMCIA 2 amp PON RESET PON DEFAULT DEBUG PINS SHOW KA PON RESET amp DBGC PON DEFAULT DEBUG PINS PCMCIA 2 then DEBUG PINS PCMCIA 2 else if MPC WRITE BCSR 0 amp DBGC DATA DEBUG PINS WATCH POINTS 4 PON RESET PON DEFAULT DEBUG PINS FOR SHOW KA PON RESET amp DBGC PON DEFAULT DEBUG PINS WATCH POINTS then Release 0 1 MPCSXXFADS User s Manual Support Informatio
124. ENABLE DATA D14 1 DATA 015 BCSR 4 definitions kK K Kk K K K K K K K K k k kk k K kk K k KK k KK k ETH_LOOP 1 ETH_FULL_DUP 0 ETH_CLSN_TEST 0 SIGNAL_LAMP_ON 0 USB FETH ENABLED 0 USB FULL SPEED 1 USB VCC CONT 0 0 VIDEO ENABLED 0 VIDEO EXT CLK ENABLED 1 VIDEO RESET ACTIVE 0 MODEM ENABLED FOR 823 0 MODEM 1 Power On Defaults Assignments LOOP PON DEFAULT ETH LOOP FULL DUP PON DEFAULT ETH FULL DUP CLSN TEST PON DEFAULT ETH CLSN TEST SIGNAL LAMP PON DEFAULT SIGNAL LAMP ON USB FETH EN PON DEFAULT USB FETH ENABLED USB SPEED DEFAULT USB FULL SPEED USB VCC 0 CONT DEFAULT USB CONT 0 USB VCC 1 CONT PON DEFAULT USB CONT 0 VIDEO ENABLE DEFAULT VIDEO ENABLED VIDEO EXT EN PON DEFAULT VIDEO EXT ENABLED VIDEO RESET PON DEFAULT VIDEO RESET ACTIVE MODEM ENABLE PON DEFAULT MODEM ENABLED FOR 823 MODEM FUNC SEL PON DEFAULT MODEM Data Bits Assignments 152 Release 0 1 MPCSXXFADS User s Manual Support Information DATA D0 FULL DUP DATA BIT DI ETH CLSN TEST DATA D2 SIGNAL LAMP DATA BIT D3
125. ENABLE DATA BIT pin ENABLED amp PON RESET ETH ENABLE PON DEFAULT ENABLED PON RESET amp ENABLE PON DEFAULT ETH ENABLED then ETH ENABLED else ETH ENABLED state ETH ENABLED if MPC WRITE BCSR 1 amp ETH ENABLE DATA BIT pin ENABLED amp PON RESET ETH ENABLE PON DEFAULT ENABLED 166 Release 0 1 MPCSXXFADS User s Manual Support Information KA PON RESET amp ENABLE PON DEFAULT ETH ENABLED then ETH ENABLED else IETH ENABLED 3k sk sk sk sk I 9k I kok 8k kok 3k state diagram InfRedEn stateINF RED ENABLE if WRITE BCSR 1 amp INF RED ENABLE DATA BIT pin RED ENABLE amp PON RESET RED ENABLE PON DEFAULT INF RED PON RESET INF RED ENABLE PON DEFAULT RED ENABLE then RED ENABLE else INF RED ENABLE state RED ENABLE if WRITE BCSR 1 amp INF RED ENABLE DATA INF RED ENABLE amp PON RESET RED ENABLE PON DEFAULT RED ENABLB KA PON RESET amp INF RED ENABLE PON DEFAULT INF RED ENABLB then INF RED ENABLE else RED ENABLE 3k sk sk sok sk sk PER PE PER R k kok I state diagram FlashCfgEn state FLASH CFG ENABLE if MPC WRITE BCSR 1 am
126. En PIN 6 istype reg buffer ethernet port enable InfRedEn PIN 41 istype reg buffer infra red port enable FlashCfgEn PIN 37 istype reg buffer flash configuration enable CntRegEn PIN 36 istype reg buffer control register access enable RS232En1 PIN 63 istype reg buffer RS232 port 1 enable PccEn PIN 40 istype reg buffer PCMCIA port enable PccVccOPIN 65 istype reg buffer PCMCIA operation voltage select 0 PccVppOPIN 59 istype reg buffer PCMCIA programming voltage select PccVpp1PIN 66 istype reg buffer PCMCIA programming voltage select HalfWord PIN 58 istype reg buffer 32 16 bit dram operation select 142 Release 0 1 MPCSXXFADS User s Manual Support Information RS232En2 PIN 64 istype reg buffer RS232 port 2 enable SdramEn PIN 56 istype reg buffer sdram enable 57 istype reg buffer PCMCIA operation voltage select 1 EthLoop PIN 60 istype reg buffer 68160 internal loop back TPFLDL PIN 43 istype 68160 full duplex TPSQEL PIN 44 istype reg buffer 68160 colission circuitry test SignaLamp PIN 4 istype reg buffer status lamp for misc s w visual signaling UsbFethEn PIN 67 istype reg buffer Usb or Fast ethernet port enable UsbSpeedPIN 46 istype reg buffer Usb speed control UsbVccOPIN 3 istype reg buffer Usb VCC select 0 line UsbVcc1PIN 2 istype reg buffer Usb VCC select 1 line VideoOn PIN 39 istype Video encode
127. FT reset When inactive the MPC will start executing normally and will enter debug mode only after exception Upon I F reset this bit wakes up active R W a Provided that the PCMCIA channel II pins are configured as debug pins i e VFLS 0 1 signals are available not the debug port can not be operated correctly 70 TABLE 4 25 DSCK Frequency Select DSCK DebugClockFreq Frequency MHz 00 10 01 5 10 2 5 Release 0 1 If MPCSXXFADS User s Manual Functional Description TABLE 4 25 DSCK Frequency Select DSCK DebugClockFreq Frequency MHz 11 1 25 FIGURE 4 8 Standard Debug Port Connector 4 12 3 gt Standard MPCXXX Debug Port Connector Pin Description The pins on the standard debug port connector are the maximal group needed to support debug port con trollers for both the MPC5XX and MPC8XX families Some of the pins are redundant for the MPC8XX family but are necessary for the MPC5XX family 4 12 3 1 VFLS 0 1 These pins indicate to the debug port controller whether or not the MPC is in debug mode When both VFLS 0 1 are at 1 the MPC is in debug mode These lines may serve alternate functions with the MPC in which case FRZ needs to selected on either the FADS or target system 4122322 HRESET This is the Hard Reset bidirectional signal of the MPC When this signal is asserted low the MPC enters hard reset sequence which include hard re
128. GND 65 EDOOE LL In fact UPMA or UPMB General Purpose Line 1 Used for Output Enable with EDO Dram simms which have this input most of them don t Used also as RAS signal for the SDRAM 66 GND 67 50 LL Byte Select 0 from UPMA Selects offset 0 Bytes within a word Used as one of the CAS lines for Dram access 68 GND 69 BS3A LL Byte Select 3 from UPMA Selects offset 3 Bytes within a word Used as one of the CAS lines for Dram access 84 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 8 PD1 Interconnect Signals Pin No Signal Name Attribute Description 70 GND 71 A31 T S MPC s Address line 31 72 GND 73 BS1A LL Byte Select 1 from UPMA Selects offset 1 Bytes within a word Used as one of the CAS lines for Dram access 74 GND 75 TSIZ1 x T S Transfer Size 1 Used in conjunction with TSIZO to indicate the number of bytes remaining in an operand transfer Not used on the FADS 76 GND 77 REG 1 IS In fact TSIZO REG Transfer Size 0 or PCMCIA slot A REG Used with the PCMCIA port as Attribute memory select or 1 space select 78 GND 79 A30 I T S MPC s Address line 30 80 GND 81 21 T S MPC s Address line 21 82 GND 83 A20 I T S MPC s Address line 20 84 GND 85 A7 I T S MPC s Address line 7 86 GND 87 A15 I T S MPC s Address line
129. HTER BOARD CONNECTOR DESCRIP tmp_mnt net prince yair 8xx fads m brd pilot sch 14 drw 15 JUL 97 14 05 last updote 15 JUL 97 14 05 QUADS COMPATIBLE EXPANSION CONNECTOR vec N TOREM P831 B1 ETHRX A1 PB30 82710 ETHTX A2 P829 IRDRXD O TO PB28 IRDTXD 9827 04 a5 9 at 3 RS_EN2 26 LD3 A6 Epp RSTXD1 s LD2 t RSDTR2 ETHRCK cupo RSTXD2 1219 RSRXD2 12 12 Crs E TENA 813 A13 C14 PRIR B14 mI uslo 17 15 G 1 5 4 LD7 5 PB16 816 16 O LD6 C17 1 817 A17 105 1 PB14 B18 11 18 LDO lt 819 G PA10 5 LOE 20 BINPAK 820 20 5 4 C21 14 821 A21 HRESET c22 5 PC13 822
130. KEEP ALIVE PON RESET 0 REGULAR PON RESET ACTIVE 0 HARD RESET ACTIVE 0 SOFT RESET ACTIVE 0 HARD CONFIG HOLD VALUE 4 DRIVE MODCK TO PDA HardReset HARD RESET ACTIVB have modck stable during hard reset REGULAR POWER ON RESET RegPORIn REGULAR PON RESET ACTIVE HARD RESET ASSERTED SyncHardReset fb HARD RESET ACTIVE 189 Release 0 1 MPCSXXFADS User s Manual Support Information HARD RESET NEGATES SyncHardReset fb HARD RESET ACTIVE amp DSyncHardReset fb HARD RESET ACTIVE detecting hard reset negation kK k Kk K K K K K K K K data buffers enable BUFFER DISABLED 1 BUFFER ENABLED BUFFER DISABLED CONTROL REG ENABLE ACTIVE 0 FLASH CONFIG ENABLED ACTIVE 0 PCMCIA ENABLE ACTIVE 0 GPL ACTIVE 0 ASSERTS amp SyncTEA fb first clock of TEA asserted CONTROL REG ENABLED ContRegEn CONTROL REG ENABLE ACTIVE FLASH CONFIGURATION ENABLED FlashCfgEn FLASH CONFIG ENABLED ACTIVE PCC ENABLED PccEn PCMCIA ENABLE ACTIVE NO HOLD OFF 0 HOLD OFF CONSIDERED 1 STATE HOLD OFF CONSIDERED HoldOffConsidered fb HOLD OFF CONSIDERED STATE NO HOLD OFF HoldOffConsidered fb NO HOLD OFF END OF FLASH READ TA amp FlashCs amp W end of flash read cycle END OF OTHER CYCLE TA amp FlashCs another
131. LECTED amp STATE DSDI ENABLED amp PdaSoftReset then DSDI L else when ADS_IS_SELECTED amp STATE_DSDI_ENABLED then DSDI TxReg7 fb else DSDI L Debug Port VFLS pins KK K K Kk K k K equations VflsP oe 5_ IS SELECTED when FRZ 15 SELECTED then VflsP VFLSO VFLS 1 else when FRZ IS SELECTED then VfIsP Freeze Freeze kk K k K Run Led k ag k k Run oe H IS_IN_DEBUG_MODE when 1 lits a led end dbg_prt7 139 Release 0 1 MPCSXXFADS User s Manual Support Information 5 3 2 U11 Board Control amp Status Register n this file 6 Added board revision at BCSR3 0 ENG 1 PILOT Flash Presence detect lines added FlashPD 7 5 Changed polarity of Power On Reset now active high DramEn becomes active low to enhance debug station support changes 1 F gt F see ok F o ook F oe oe Tn this file 7 Board revisiob code 9 BCSR3 is changed to 2 Rev A n this file 8 Board revisiob code 9 BCSR3 is changed to 3 Rev B Added RS232En2 for 2 nd RS232 port oe soe n this file 9 status bits except CntRegEnProtect are removed for external buffers Added address line A27 A
132. Logic o o o kk eoe eoe eo TxWordLen3 TxWordLen2 TxWordLenl TxWordLenONODE istype reg buffer Counter counts on fast clock to gain 1 2 clock resolution transmission length TxWordEndNODE istype com Terminal count sets transmission length TxEn NODE istype buffer Transmit Enable TxCIKSnsNODE istype buffer transmit clock polarity 118 Release 0 1 MPCSXXFADS User s Manual Support Information Rx Shift Register RxRegONODE istype buffer receive shift register and latch k k kk K k K K k K K k Rx Control Logic X DsdiEnNODE istype enables dsdi towards ADI control amp status register bits 2 StatusRequest NODE istype buffer Status request DebugEntry NODE istype buffer Debug enable after reset L DiagLoopBack NODE istype reg buffer diagnostic loopback mode L DbgCIkDivSelO NODE istype reg buffer DbgCIkDivSell NODE istype buffer DbgClk division select InDebugMode NODE istype reg buffer sync VFLSs became pin TxError NODE istype buffer tx interrupted by MPC8XX internal reset 119 Release 0 1 MPCSXXFADS User s Manual Support Information
133. M ENABLED FOR 823 then MODEM ENABLED FOR 823 else ENABLED FOR 823 178 Release 0 1 MPCSXXFADS User s Manual Support Information state diagram Modem Audio state MODEM if MPC WRITE BCSR 44 MODEM FUNC SEL DATA BIT pin MODEM amp PON RESET MODEM FUNC SEL PON DEFAULT MODEM PON RESET amp MODEM FUNC SEL PON DEFAULT MODEM then IMODEM else MODEM state if WRITE BCSR 4 amp MODEM FUNC SEL DATA BIT pin amp PON RESET MODEM FUNC SEL PON DEFAULT KA PON RESET amp MODEM FUNC SEL PON DEFAULT then MODEM else IMODEM External Read Registers Chip Selects k K kk K k KK k K K K equations Besr2 3Cs 0e 3 Besr2Cs READ BCSR 2 Bcsr3Cs READ BCSR 3 kK K Kk K k KK K K K K Read Registers registers have read capabilty K K k k equations DataOe READ BCSR 0 READ BCSR 1 READ BCSR 4 179 Release 0 1 MPCSXXFADS User s Manual Support Information RESET CONFIG DRIVEN Data oe DataOe Data oe hffff when READ BCSR 0 RESET CONFIG D
134. MCIA Address line 9 12 PCCA8 PCMCIA Address line 8 13 PCCA13 PCMCIA Address line 13 14 PCCA14 PCMCIA Address line 14 77 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 4 P4 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 15 WE PGM O PCMCIA Memory Write Strobe Active low Strobes data to PC Card during memory write cycles 16 RDY Ready Busy signal from PC Card Allows PC Card to stall access from the host in case a previous access s processing is not completed 17 PCCVCC 5V VCC for the PC Card Switched by the MPC8XXFADS BCSR1 18 12 5 VPP for the PC Card programming 12V available only if12V is applied to P8 Controlled by the MPC8XXFADS BCSR1 19 PCCA16 PCMCIA Address line 16 20 15 PCMCIA Address line 15 21 PCCA12 PCMCIA Address line 12 22 7 PCMCIA Address line 7 23 6 PCMCIA Address line 6 24 5 PCMCIA Address line 5 25 4 PCMCIA Address line 4 26 PCCAS3 O PCMCIA Address line 3 27 PCCA2 O PCMCIA Address line 2 28 PCCA1 PCMCIA Address line 1 29 PCCAO PCMCIA Address line 0 30 PCCDO PCMCIA Data line 0 31 PCCD1 PCMCIA Data line 1 32 PCCD2 y o PCMCIA Data line 2 33 WP Write Protect indication from the PC Card
135. MPC s Data line 11 53 GND 54 D10 X Data line 10 55 GND 56 D9 X MPC s Data line 9 57 GND 58 D8 X MPC s Data line 8 103 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 11 PD4 Interconnect Signals Pin No Signal Name Attribute Description 59 GND 60 61 62 D7 X MPC s Data line 7 63 GND 64 D6 X MPC s Data line 6 65 GND 66 D5 X MPC s Data line 5 67 GND 68 D4 X Data line 4 69 GND 70 71 72 D3 X MPC s Data line 3 73 GND 74 D2 I O X Data line 2 75 GND 76 D1 X Data line 1 77 GND 78 DO X MPC s Data line 0 79 GND 80 81 DRMH_W O L Dram Half Word Sets the Dram to 16 bit data bus width See TABLE 4 10 BCSR1 Description on page 57 82 DRAMEN O L Dram Enable Enables Dram to the FADS memory map See TABLE 4 10 BCSR1 Description on page 57 83 FCFGEN O L Flash Configuration Enable Allows for Hard Reset Configuration to be obtained from the Flash memory provided that this option is supported by the MPC See TABLE 4 10 5 1 Description on page 57 84 F_EN O L Flash Enable Enables the Flash memory to the FADS memory map See TABLE 4 10 BCSR1 Description on page 57 85 SDRAMEN O H Sdram Enable Enables the Synchronous Dram to the FADS memo
136. ODE istype reg buffer Boot Port Size RSV6NODB istype reg buffer reserved config bit 6 ISBO ISBINODE istype reg buffer Internal Space Base DBGCO DBGCINODE istype reg buffer Debug pins Config DBPCO DBPCINODEBE istype reg buffer Debug Port pins Config RSV13 NODE istype reg buffer reserved config bit 13 RSV14 NODE istype reg buffer reserved config bit 14 RSV15 NODE istype reg buffer reserved config bit 15 DataOeNODE istype com data bus output enable on read K K KK K K K K K K K K Control Register Enable Protection K ER K kk K Kk k K kk K k KK k K K K CntRegEnProtect NODE istype reg buffer K k K K k K K K Control Register Write space saving Mach 10 required for 52Mhz k k k k k Kk k K Kk K Kk K BesrOWrite NODE istype com BesrIWrite NODE istype Besr4Write NODE istype 144 Release 0 1 MPCSXXFADS User s Manual Support Information kK k kk K k KK k K K k HHO O GHHUHE Sh 4 HEH EE BOUE HH 3 9 HHA EE AE SU HHE GHUHE HO H HHE 8 4 HOO HHHHHHE Udo d GHHHHHE HOO OH HHH eE AFO HH 4 4 GHHHHHE
137. ON DEFAULT DEBUG PINS PCMCIA 2 PON RESET amp DBGC PON DEFAULT DEBUG PINS WATCH POINTS then PINS WATCH POINTS else if MPC WRITE BCSR 0 amp DBGC DATA BIT pin DEBUG PINS RESREVED amp PON RESET DBGC PON DEFAULT DEBUG PINS PCMCIA 2 KA PON RESET amp DBGC PON DEFAULT DEBUG PINS RESREVED then DEBUG PINS RESREVED else if MPC WRITE BCSR 0 4 DBGC DATA BIT pin DEBUG PINS FOR SHOW amp PON RESET DBGC PON DEFAULT DEBUG PINS PCMCIA 2 KA PON RESET amp DBGC PON DEFAULT DEBUG PINS FOR SHOW then PINS FOR SHOW else DEBUG PINS PCMCIA 2 state DEBUG PINS WATCH POINTS if WRITE BCSR 0 amp DBGC DATA BIT pin DEBUG PINS PCMCIA 2 amp PON RESET PON DEFAULT DEBUG PINS WATCH POINTS KA PON RESET amp DBGC PON DEFAULT DEBUG PINS PCMCIA 2 then DEBUG PINS PCMCIA 2 else if WRITE BCSR 0 amp 160 Release 0 1 161 MPCSXXFADS User s Manual Support Information DBGC DATA DEBUG PINS RESREVED amp PON RESET PON DEFAULT DEBUG PINS WATCH POINTS PON RESET amp DEFAULT DEBUG PINS RESREVED then DEBUG PINS RESREVED else if WRITE BCSR 0 amp DBGC DATA DEBUG PINS FOR SHOW amp PON RESET PON DEFAULT PINS WATCH POINTS PON RESET amp PON D
138. Open Drain gate only 85 GND 86 RSTCNF O L Hard Reset Configuration output Driven during Hard Reset to the daughter board to signal the MPC that it should sample Hard Reset configuration from the data bus 87 GND 88 R_PORI O L Main battery power on reset Generated as a result of main 3 3V bus going through power up or power down Drives on board logic as well either HARD RESET or Power On reset to the MPC 89 GND 90 91 92 BWAITA O L Buffered PCMCIA slot A WAIT signal Used to prolong cycles to slow PC Cards In case of MPC823 or MPC850 daughter boards connected to WAIT_B signal of the MPC 93 GND 94 BWP O H Buffered PCMCIA slot A Write Protect In fact A2 IOIS16A Used as PC card write protect indication or as 16 bit I O capability indication for PCMCIA slot A In case of MPC823 or MPC850 daughter boards connected to B2 signal of the MPC 95 GND 96 BVS1 Buffered PCMCIA slot A Voltage Sense 1 In fact IP 0 Used in conjunction with BVS2 to determine the operation voltage of a PCMCIA card In case of MPC823 or MPC850 daughter boards connected to BO signal of the 97 GND 92 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 9 PD2 Interconnect Signals Pin No Signal Name Attribute Description 98 BRDY O H Buffered PCMCIA slot A Ready signal In fact IP A7 Used as PCMCIA port A Card Ready indication In case
139. PCCA17 461 47 4 2 i bi 18 47 16 vaz ewe Peena Alang Roy asy 16 1 4144 yg 06 BWATA 19 WP 15 _ BINPAK PCCA20 491 war 59 4 Y4 PCCA21 50 60 Slag ve 14 PCCA22 53 45 TRES Zing ve 15 PCCA23 54422 62 1 712 BBVD1 A23 02 PCCA24 55 423 802 53 9 11 02 BCE2A PCCA25 561 24 vs 43 TI 1962 2 var t 7 PCMCIA CON2 1 VS2 37 1 Y1 CE m v 42 67 n 740 125 BWE3 alas val18 PCREG 61 9 8 __ 01 BWE2 5 15 BWEQ elis 15 10 5 WE PCM 28 BWE 1 PEE olo RESETA 1 44 7 TORD 74LCX125 a 7X8 OR 12 11 BCD2 gt RESET CN 5868 BPOE A 040 sale P4 BSPKOUT 1 261 SPEAKER GND u 0 1UF an SEP 1162 MOTOROLA INC 2 co PROJECT MPCBXXFADS REV PILOT SHEET 5 OF 14 GND il eua SK1 ENG YAIR LIEBMAN BLOCK PCMCIA I F V CHK DESCRIP 8 D E F G H J tmp _mnt net prince yair 8xx fads m brd pilot sch 6 drw 07 MAY 97 16 55 lost update 07 MAY 97 16 55
140. PUT when the ADI bundle is disconnected from the FADS INPUT V3 3 3 3V Power indication This line is merely for indication No significant power may be drawn from this line 10 DSDO Debug Serial Data Output from the Configured on the MPC s JTAG port When the debug port controller is on the local MPC or when the ADI bundle is disconnected from the FADS OUTPUT when the FADS is a debug port controller for a target system INPUT 80 Release 0 1 MPCSXXFADS User s Manual Support Information 5 1 6 5V Power Connector The 5V power connector P6 is a 3 lead two part terminal block The male part is soldered to the pcb while the receptacle is connected to the power supply That way fast connection disconnection of power is facilitated and physical efforts are avoided on the solders which therefore maintain solid connection over time TABLE 5 6 P6 Interconnect Signals iid Signal Name Description Number 1 input from external power supply 2 GND GND line from external power supply 3 GND GND line from external power supply 517 P7 12V Power Connector The 12V power connector P7 is a two lead 2 part terminal block connector identical in type to the 5V connector P7 supplies when necessary programming voltage to the Flash SIMM and or to the PCMCIA TABLE 5 7 P7 Interconnect Signals
141. RIVEN then Data ERB fb IP fb RSV2 fb BDIS fb BPSO fb BPS1 fb RSV6 fb ISBO fb ISB1 fb DBGCO fb DBGCI fb DBPCO fb DBPCI fb RSV13 fb RSV14 fb RSV15 fb else when READ BCSR 1 then Data 1 else when READ BCSR 4 then Data UsbFethEn UsbSpeed UsbVcc0 UsbVcc1 VideoOn VideoExtCIkEn VideoRst SignaLamp EthLoop TPFLDL TPSQEL Modem_Audio 0 0 0 0 Data EthLoop TPFLDL TPSQEL SignaLamp UsbFethEn Usb Speed UsbV UsbVccl VideoOn VideoExtClkEn VideoRst ModemEn Modem_Audio 0 0 0 end bcsr11 180 Release 0 1 MPCSXXFADS User s Manual Support Information 5 3 3 022 Auxiliary Board Control n this file 5 1 The use of BCLOSE is removed This due to the assignment to GPLAA In order of using of GPLAA bit in the upm to determine data sampling edge GPL4A may not be used as a GPL Therefore DramBankXCs must envelope the cycle so that data buffers remain open throughout the cycle 2 Removed CS support for flash configuration Le FlashCs1 will not be asserted during hard reset Flash configuration will be supported on silicon next revisions data buffers will still open for flash configuration when hard reset asserted and flash configuration option bit asserted 3 Since Bclose is no longer available the data
142. Reg oe hfffffff state_diagram FlashEn state FLASH_ENABLED if MPC WRITE BCSR 1 amp FLASH ENABLE DATA BIT pin ENABLED amp PON RESET FLASH ENABLE PON DEFAULT FLASH ENABLED KA PON RESET amp FLASH ENABLE PON DEFAULT FLASH ENABLED then IFLASH ENABLED else FLASH ENABLED state FLASH ENABLED 165 Release 0 1 MPCSXXFADS User s Manual Support Information if MPC WRITE BCSR 1 amp FLASH ENABLE DATA BIT pin FLASH ENABLED amp PON RESET FLASH ENABLE PON DEFAULT ENABLED PON RESET FLASH ENABLE PON DEFAULT FLASH ENABLED then FLASH ENABLED else IFLASH ENABLED I R PER R k kok ak kok ak state diagram DramEn state ENABLED if WRITE BCSR 1 amp DRAM ENABLE DATA BIT pin DRAM ENABLED amp PON RESET DRAM ENABLE PON DEFAULT DRAM ENABLED RESET amp DRAM ENABLE PON DEFAULT ENABLED then IDRAM ENABLED else DRAM ENABLED state DRAM ENABLED if MPC WRITE BCSR 1 amp DRAM ENABLE DATA BIT pin DRAM ENABLED 4 PON RESET DRAM ENABLE PON DEFAULT ENABLED PON RESET amp DRAM ENABLE PON DEFAULT DRAM ENABLED then DRAM ENABLED else IDRAM ENABLED K K kK K K k K K k K K K state_diagram EthEn state if MPC WRITE BCSR 1 amp ETH
143. S User s Manual Support Information if MPC WRITE 0 amp RSV6 DATA BIT pin RSV6 ACTIVE amp PON RESET RSV6 PON DEFAULT RSV6_ACTIVE KA PON RESET amp RSV6 PON DEFAULT RSV6 ACTIVE then RSV6 ACTIVE else IRSV6 ACTIVE state 2 ACTIVE if WRITE BCSR 0 amp RSV6 DATA BIT pin RSV6 ACTIVE amp PON RESET st RSV6 PON DEFAULT RSV6 ACTIVB PON RESET amp RSV6 PON DEFAULT RSV6 then ACTIVE else RSV6 ACTIVE 2 I CSE k kok k kok ak state diagram ISB state INT SPACE BASE 0x00000000 if MPC WRITE 0 amp ISB DATA BIT pin INT SPACE BASE 0x00F00000 amp PON RESET ISB DEFAULT INT SPACE BASE 0x00000000 PON RESET amp ISB PON DEFAULT INT SPACE BASE 0x00F00000 then INT SPACE BASE 0x00F00000 else if MPC WRITE BCSR 0 amp ISB DATA BIT pin INT SPACE BASE OxFF000000 amp PON RESET ISB DEFAULT INT SPACE BASE 0x00000000 PON RESET amp ISB PON DEFAULT INT SPACE BASE 0 000000 then INT SPACE BASE OxFF000000 else if MPC WRITE BCSR 0 amp ISB DATA BIT pin INT SPACE BASE 0xFFF00000 amp PON RESET ISB PON DEFAULT INT SPACE BASE 0x00000000 4 KA PON RESET amp ISB PON DEFAULT INT SPACE BASE 0 00000 then INT SPACE BASE OxFFF00000 else INT SPACE BASE 0x00000000
144. S Part List 87 100 Release 0 1 MPCSXXFADS User s Manual General Information 1 General Information 1 1 Introduction This document is an operation guide for the MPC8XXFADS board It contains operational functional and general information about the FADS The MPC8XXFADS is meant to serve as a platform for s w and h w development around the MPC8XX family processors Using its on board resources and its associated de bugger a developer is able to download his code run it set breakpoints display memory and registers and connect his own proprietary h w via the expansion connectors to be incorporated to a desired system with the MPC8XX processor This board could also be used as a demonstration tool i e application s w may be burned into its flash memory and ran in exhibitions etc 1 2 MPC8XX Family Support The MPC8XXFADS supports the following MPC8XX family members o MPC801 821 823 850 o MPC860 8605 o MPC860T 13 Abbreviations List 5 the MPC8XXFADS the subject of this document UPM User Programmable Machine General Purpose Chip select Machine GPL General Purpose Line associated with the R Infra Red BCSR Board Control amp Status Register ZIF Zero Input Force BGA Ball Grid Array SIMM Single In line Memory Module 1 4 Related Documentation MPC8XX User s Man
145. S232 ports are provided on the FADS The MPC s communication ports to which these RS232 ports is routed is established according to the type of MPC residing on the daughter board Use is done with MC145707 transceivers which generates RS232 levels internally using a single supply and are equipped with OE and shutdown mode When the RS232EN1 RS232EN2 bits in BCSR1 are asserted low the associated transceiver is enabled When negated the associated transceiv er enters standby mode in which the receiver outputs are tri stated enabling use of the associated port s pins off board via the expansion connectors Use is done with 9 pins female D Type stacked connector configured to be directly via a flat cable con nected to a standard IBM PC like RS232 connector FIGURE 4 5 85232 Serial Ports Connector TX TX DTR GND DSR RTS CTS N C ON 4 9 3 1 5 232 Ports Signal Description In the list below the directions O and 1 are relative to the FADS board l e l means input to the FADS CD O Data Carrier Detect This line is always asserted by the FADS e TX O Transmit Data RX I Receive Data 1 Data Terminal Ready This signal be used by the software on the FADS to detect if a terminal is connected to the FADS board Data Set Ready This line is always asserted by the FADS RTS I Request To Se
146. SDRAM is provided on board The SDRAM is unbuffered from the MPC bus and is configured as 2 X 512K X 32 Use is done with two MB811171622A 100 chips by Fujitsu or compatibles To enhance performance the SDRAM is unbuffered from the MPC saving the delay associated with address and data buffers Since only 2 memory chips are involved it does not adversely effect overall system performance The SDRAM does not reside a SIMM but is soldered directly to the FADS pcb SDRAM may be enabled disabled at any time by writing 1 0 to the SDRAMEN bit in BCSR1 See TABLE 4 10 BCSR1 Description on page 57 The SDRAM s timing is controlled by UPMB via its assigned CS See TABLE 4 1 MPC8XXFADS Chip Selects Assignment on page 39 line Unlike a regular dram the synchronous dram has a CS input in addition to the RAS and CAS signals The sdram connection scheme is shown in FIGURE 4 4 SDRAM Connection Scheme on page 47 The SDRAM s performance figures are shown in TABLE 4 6 Estimated SDRAM Performance Figures TABLE 4 6 Estimated SDRAM Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 258 Single Read 5 3 Single Write 3415 2 1 Burst Read 5 1 1 1 3 1 1 1 Burst Write 3 1 1 1 2 1 1 1 1 Refresh 21 135 a In fact upto 32MHz b One additional cycle for RAS precharge c 4 beat Refresh Burst not including arbitration overhead 46 Release 0 1
147. SET amp VPPI1 PON DEFAULT PCC_VPP1 then VPPI else VPPI state if WRITE BCSR 1 amp PCC VPP1 DATA BIT pin PCC 4 PON RESET 1 PON DEFAULT PCC_VPP1 KA PON RESET amp VPP1 PON DEFAULT VPP1 then 1 else IPCC VPPI PER A CSCO k kok ICO state diagram HalfWord state HALF WORD if MPC WRITE BCSR 1 amp HALF WORD DATA BIT pin WORD amp PON RESET HALF WORD PON DEFAULT HALF WORD PON RESET amp HALF WORD PON DEFAULT WORD then WORD else HALF WORD state HALF WORD if MPC WRITE BCSR 1 amp HALF WORD DATA BIT pin HALF WORD amp PON RESET HALF WORD PON DEFAULT HALF WORD PON RESET amp HALF WORD PON DEFAULT HALF WORD then HALF WORD else WORD state diagram RS232En2 171 Release 0 1 MPCSXXFADS User s Manual Support Information state RS232 2 ENABLE if WRITE BCSR 1 amp RS232 2 ENABLE DATA BIT pin RS232 2 ENABLE amp PON RESET RS232 2 ENABLE PON DEFAULT RS232 2 ENABLEB PON RESET amp RS232 2 ENABLE PON DEFAULT RS232 2 ENABLE then RS232 2 ENABLE else RS232 2 ENABLE state RS232 2 ENABLE if MPC WRITE BCSR 1 amp RS232 2 ENABLE DATA BIT pin RS232 2 ENABLE am
148. T SRESET DSDI Debug port Serial Data In DSCK Debug port Serial Clock DSDO Debug port Serial Data Out Power Bus 3 3V Bus 12V Bus Support Information Interconnect Signals P1 ADI Port Connector PA2 PB2 RS232 Ports Connectors P3 Ethernet Port Connector PCMCIA Port Connector P5 External Debug Port Controller Input Interconnect P6 5V Power Connector P7 12V Power Connector P8 Serial Ports Expansion Connector PD1 Daughter Boards Connectors Interconnect Signals MPC8XXFADS Part List Programmable Logic Equations U2 Debug Port Controller U11 Board Control amp Status Register U22 Auxiliary Board Control ADI I F ADI Port Signal Description ADI Installation INTRODUCTION IBM PC XT AT to MPC8XXFADS Interface ADI Installation in IBM PC XT AT SUN 4 to MPC8XXFADS Interface ADI Installation in the SUN 4 194 195 Release 0 1 FIGURE 1 1 FIGURE 2 1 FIGURE 2 2 FIGURE 2 3 FIGURE 2 4 FIGURE 2 5 FIGURE 2 6 FIGURE 2 7 FIGURE 2 8 FIGURE 2 9 FIGURE 2 10 FIGURE 2 11 FIGURE 3 1 FIGURE 4 1 FIGURE 4 2 FIGURE 4 3 FIGURE 4 4 FIGURE 4 5 FIGURE 4 6 FIGURE 4 7 FIGURE 4 8 FIGURE 4 1 FIGURE A 1 FIGURE B 1 FIGURE B 2 FIGURE B 3 MPCSXXFADS User s Manual LIST OF FIGURES MPC8XXFADS Motherboard Block Diagram MPC8XXFADS Top Side Part Location diagram Configuration Dip Switch DS2 J1 VFLS FRZ Selection Host Controlled Operation Scheme Debug Port Contro
149. T8 16D432 832X 6 7 multiplexing according to AMA MCM36200 60 70 00400081 Base at 400000 32 bit port size no parity UPMA MCM36800 60 70 01000081 Base at 1000000 32 bit port size no parity UPMA 160832 6 7 OR3 MCM36200 60 70 FFC00800 4MByte block size all types access initial address multiplexing according to AMA MCM36800 60 70 FF000800 16MByte block size all types access initial address MT16D832X 6 7 multiplexing according to AMA BR4 MB811171622A 100 030000C1 Base at 3000000 on UPM B OR4 FFC00A00 4 MByte block size all types access initial address multiplexing according to AMB 27 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS TABLE 3 3 Memory Controller Initializations For 50Mhz Register Device Type Init Value hex Description MPTPR All Dram SIMMs 0400 Divide by 16 decimal Supported MAMR MB321BTO8TASN60 40A211142 refresh clock divided by 402 or 600 or periodic 60A21114 timer enabled type 2 address multiplexing scheme 1 C0A21114 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB322BT08TASN60 20A211142 refresh clock divided by 208 or 30 or 60 periodic 304211149 timer 604211142 enabled type 2 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burs
150. TIVE l Clock Logic definitions k kk K k KK k K K K SELECT CHANGE ALLOWED DbgClkDiv fb 0 DEBUG CLOCK DIV BY 1 Cstr fb 0 DEBUG DIV BY 2 Cstr fb 1 DEBUG CLOCK DIV BY 4 Cstr fb 2 DEBUG DIV BY 8 Cstr fb 3 K k KK k K K K AdsAck Logic definitions kK kk K k KK k KK k BUNDLE_DELAY 2 HOST_REQ_ACTIVE l ADS ACTIVE 1 The other state 15 ADS_ACK ACTIVE HOST_ACK_ACTIVE l HOST_WRITE_ADI AdsSelect f b BOARD 15 SELECTED amp DS HstReq fb HOST_REQ_ ACTIVE amp AdsAck z ADS ACTIVE amp ACTIVE HOST WRITE ADI CONTROL AdsSelect fb BOARD IS SELECTED 4 DS HstReq fb HOST_REQ_ ACTIVE amp AdsAck z ADS ACTIVE amp D_C CONTROL amp S D C fb CONTROL amp HstAck z HOST ACTIVE 122 Release 0 1 MPCSXXFADS User s Manual Support Information HOST WRITE ADI DATA AdsSelect fb BOARD 15 SELECTED amp DS HstReq fb HOST ACTIVE amp AdsAck ADS ACTIVE amp D amp 5 D C fb DATA amp HstAck HOST ACTIVE HOST WRITE COMPLETE AdsSelect fb BOARD IS SELECTED amp DS HstReq fb HOST REQ ACTIVE amp 5 ACTIVE Control am
151. TOOTBSN60 01000081 Base at 1000000 32 bit port size no parity UPMA OR3 MB322BTO8TASN60 FFCO00800 4MByte block size all types access initial address multiplexing according to AMA MB328CTOOTBSN60 FF000800 16MByte block size all types access initial address multiplexing according to AMA BR4 MB811171622A 100 030000C1 Base at 3000000 on UPM B OR4 FFC00A00 4 block size all types access initial address multiplexing according to AMB MPTPR All Dram SIMMs 0400 Divide by 16 decimal Supported 31 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS TABLE 3 6 Memory Controller Initializations For 20Mhz Register Device Type Init Value hex Description MAMR 321 08 5 60 60421114 refresh clock divided by 60 periodic timer enabled type 2 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB322BT08TASN60 30A21114 refresh clock divided by 30 periodic timer enabled type 2 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB324CTOOTBSN60 60B21114 refresh clock divided by 60 periodic timer enabled type 3 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burs
152. TX ON RISING if HOST WRITE ADI DATA 6 BndTmrExp fb amp 2 then TX ON FALLING else TX ON RISING state TX ON FALLING if HOST WRITE ADI DATA amp BndTmrExp fb amp 2 then Release 0 1 MPCSXXFADS User s Manual Support Information TX ON RISING else TX ON FALLING sk ook ol ok oe oe Tx shift Register 8 bits shift register which either shifts data out MSB first or holds its data The edge in CIK2 terms upon which the above actions are taken 15 determined by TxClkSns The Tx shift register operates according to The Tx shift register is 1 st written by the host data cycle and along with write being acknowledged to the host data is shifted out via DSDI n order of saving logic the Tx shift register is shared with the Receive shift register this due to the fact that when a bit is shifted out a FF becomes available Since the Tx shift register is shifted MSB first its LSB FFs are grdualy becoming available for received data To provide a 1 2 DSCK hold time for DSDI a single FF receive SR is used which is the source for the Tx shift register if 0 hold is required for DSDI this FF may be ommited k KK k KK k equations TxReg clk ICIK TxReg ar Reset when HOST WRITE ADI DATA amp BndTmrExp fb amp STATE_TX_ENABLED then TxReg7 TxRegl PD7 PD1 pin latching ADI data
153. TYPE SIZE 7 MCM29040 4 MByte SIMM by Motorola 8 29020 2 MByte SIMM by Motorola 9 F Reserved TABLE 4 15 DRAM Presence Detect 2 1 Encoding DRAM PD 2 1 DRAM TYPE SIZE 00 36100 by Motorola or MT8D132X by Micron 4 MByte SIMM 01 36800 by Motorola or MT16D832X by Micron 32 MByte SIMM 10 36400 by Motorola or MT8D432X by Micron 16 MByte SIMM 11 MCM36200 by Motorola or MT16D832X by Micron 8 MByte SIMM TABLE 4 16 DRAM Presence Detect 4 3 Encoding DRAM PD 4 3 DRAM DELAY 00 Reserved 01 Reserved 10 70 nsec 11 60 nsec TABLE 4 17 EXTOOLI 0 3 Assignment EXTTOOLI 0 3 External Tool 0000 0111 Reserved 1000 1110 User Available 1111 Non Existent Release 0 1 MPCSXXFADS User s Manual Functional Description WARNING Since EXTOLI 0 3 lines be DRIVEN LOW 0 by the dip switch OFF BOARD tools should NEVER DRIVE them HIGH Failure in doing so might result in PERMA NENT DAMAGE to the FADS and or to OFF BOARD log ic TABLE 4 18 MPC8XXFADS Daughter Boards Revision Encoding Revision Number 0 3 MPC8XXFADS Daughter Hex Board Revision 0 ENG Engineering 1 PILOT 2 7 Reserved 4 11 5 5 Board Control Status Register 3 BCSR3 is an additional control status register which be accessed at offset OxC from B
154. ULT IP AT 0x00000000 st RESET amp IP PON DEFAULT IP AT 0 00000 then OxFFF00000 else IP AT 0x00000000 k sk sk sk ok F R F ook I kok k kok k state diagram RSV2 state RSV2 ACTIVE if WRITE BCSR 0 amp RSV2 DATA RSV2 ACTIVE amp PON RESET st RSV2 PON DEFAULT RSV2 ACTIVB KA PON RESET amp RSV2 PON DEFAULT RSV2 ACTIVE then RSV2 ACTIVE else IRSV2 ACTIVE state 2 ACTIVE if WRITE BCSR 0 amp RSV2 DATA BIT pin RSV2 ACTIVE amp PON RESET RSV2 PON DEFAULT RSV2 ACTIVB KA PON RESET amp RSV2 PON DEFAULT RSV2_ACTIVE then IRSV2 ACTIVE else RSV2 ACTIVE CS k kok k kok ak state diagram BDIS state BOOT ENABLE if MPC WRITE BCSR 0 amp BDIS DATA BIT pin BOOT DISABLE amp PON RESET BDIS PON DEFAULT BOOT_ENABLE KA PON RESET amp BDIS PON DEFAULT BOOT_DISABLE then BOOT DISABLE else BOOT ENABLE state BOOT DISABLE if MPC WRITE BCSR 0 amp BDIS DATA BIT pin BOOT ENABLE amp PON RESET BDIS PON DEFAULT BOOT DISABLB KA PON RESET amp BDIS PON DEFAULT _ then 155 Release 0 1 MPCSXXFADS User s Manual Support Information BOOT ENABLE else BOOT DISABLE k sk sk sok
155. XFADS User s Manual OPERATING INSTRUCTIONS UART for terminal or host computer connection a Ethernet controller Infra Red Port Controller 7 General Purpose signals The internal registers of the MPC must be programmed after Hard reset as described in the following paragraphs The addresses and programming values are in hexadecimal base For better understanding the of the following initializations refer to the MPC821 or to the MPC860 User s Manual for more information TABLE 3 2 SIU REGISTERS PROGRAMMING Register Init Value hex Description SIUMCR 01012440 Internal arbitration External master arbitration priority 0 External arbitration priority 0 PCMCIA channel pins PCMCIA Debug Port on JTAG port pins FRZ IRQ6 FRZ debug register locked No parity for non CS regions DP 0 3 IRQ 3 6 pins DP 0 3 reservation disabled SPKROUT Tri stated BS 0 3 WE 0 3 are driven just on their dedicated pins GPL B5 enabled GPL A 2 3 function as GPLs SYPCR FFFFFF88 Software watchdog timer count FFFF Bus monitor timing FF Bus monitor Enabled S W watch dog Freeze S W watch dog disabled S W watch dog if enabled causes NMI S W if enabled not prescaled TBSCR 00C2 No interrupt level reference match indications cleared interrupts disabled no freeze time base disabled RTCSC 00C2 Interrupt request level 0 32768 Hz source second in
156. XXFADS Connection Terminal to MPC8XXFADS RS 232 Connection Memory Installation OPERATING INSTRUCTIONS INTRODUCTION CONTROLS AND INDICATORS ABORT Switch SW1 SOFT RESET Switch SW2 HARD RESET Switches SW1 amp SW2 051 Software Options Switch GND Bridges ETH LD1 IRD ON LD2 85232 Port 1 ON 103 RS232 Port 2 ON LD4 Ethernet RX Indicator LD5 Ethernet TX Indicator LD6 Ethernet JABB Indicator LD7 Ethernet CLSN Indicator LD8 Ethernet PLR Indicator LD9 Ethernet LIL Indicator LD10 O O OO O0 O gt O O O S N NS HHH Release 0 1 4 2 4 4 4 5 4 6 4 7 4 8 4 9 3 2 16 3 2 17 3 2 18 3 2 19 3 2 20 3 2 21 3 2 22 O gt O 4 6 1 4 62 4 6 3 4 64 4 8 1 4 811 4 8 2 4 9 1 4 92 4 92 1 4 9 3 4593 1 MPCSXXFADS User s Manual TABLE OF CONTENTS 5V Indicator LD11 RUN Indicator LD12 AUXILARY Indicator LD13 FLASH ON LD14 DRAM ON LD15 SDRAM ON LD16 PCMCIA ON LD17 MEMORY MAP MPC Registers Programming Memory Controller Registers Programming Functional Description Reset amp Reset Configuration Keep Alive Power On Reset Regular Power On Reset Manual Soft Reset Manual Hard Reset Internal Sources Reset Configuration Power On Reset Configuration Hard Reset Configuration Soft Reset Configuration Local Interrupter Clock Generator Buffering Chip
157. YAIR LIEBMAN BLOCK T P ETHERNET PORT CHK DESCRIP 8 6 D E F G H J K tmp_mnt net prince yair 8xx fads m brd pilot sc h 7 drw 07 MAY 97 16 56 last update 07 MAY 97 16 56 A B C D E F G H J K 1 74 157 SYSCLK 5 18 tour 25 cuc 0 1UF T C23 C24 xE 59 4413 S I CHINS 1 2 41 24154 2 cz H 61518 10UF 629 4 22 8 JJ Lat 039 7 Tai 2 3 DI2 Tx2 R1T O 2 7 CLK g DBGCLK RSTXD1 135 12 TxD1 a DU lt Ae T O U33 26002 ral A 3 lt malt omi 41 2 cd 20 neile CLOCK GENERATOR RS 5 18 O sta NC2 H3 GND a 2 lt 4 10UF 1UF T e 4 C12 p AR 2 eR GND v Aire R4 cN 3 65232 PORTS lt _ _
158. a Refresh Period 16 msec Number Of Beats Per Refresh Cycle on the FADS it is 4 Number Of Rows To Refresh 1024 T BRG 20 nsec system clock 50 Mhz MPTPR arbitrarily chosen to be 16 Number Of Banks 2 for that SIMM If we assign the figures to the PTA formula we get the value of PTA should be 97 decimal or 61 hex 4 6 4 Variable Bus Width Control Since a port s width determines its address lines connection scheme i e the number of address lines required for byte selection varies 1 for 16 bit port and 2 for 32 bit port according to the port s width it is necessary to change address connections to a memory port if its width is to be changed E g if a certain memory is initially configured as a 32 bit port the list significant address line which is connected to that memory s A0 line should be the MPC s A29 Now if that port is to be reconfigured as 16 bit port the LS address line becomes A30 If a linear address scheme is to be maintained all address lines connected to that memory are to be shifted one bit this obviously involves extensive multiplexing passive or active If linear addressing 42 Release 0 1 MPCSXXFADS User s Manual Functional Description scheme is not a must than only minimal multiplexing is required to support variable port width In TABLE 4 4 DRAM ADDRESS CONNECTIONS below the FADS s dram address connection scheme is presented TABLE 4 4 DRAM ADDRESS CONNE
159. access or ITA amp FlashCs amp W flash write HOLD OFF PERIOD W amp PD FlashOe fb HOLD OFF PERIOD R_W amp TD_FlashOe fb 190 Release 0 1 MPCSXXFADS User s Manual Support Information k KK k Equations state diagrams K K K K K HHH H HHHH HHHO H HHHO EE H S dg HH HF HHE H H go ogg H HHH HEHEHE HHHH H EE Hg og H og H go gd UFGHHHHHHE HHEH HHE HHH k Reset Logic ILLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLELELLLELLLELLLLLLLLLLLLLLLLLLLLLLLELLLLELELLELDLELLLLLILEL equations Reset oe Reset 0 open drain RstDebl Rstl amp RstDebl fb amp Rst0 Reset push button debouncer AbrDebl amp AbrDebl fb amp Abr0 Abort push button debouncer HardResetEn RstDeb1 fb amp AbrDebl fb both buttons are depressed REGULAR POWER ON RESET SoftResetEn RstDeb1 fb amp AbrDeb1 fb only reset button depressed k K K K Power On reset configuration k k k K k k K Kk k Kk K equations Modck oe ModckOe ModckOe DRIVE MODCK TO PDA 191 Release 0 1 MPCSXXFADS User s Manual Support Information Modck2 L ifndef SLOW_32K_LOCK Modck2
160. after the negation of SRESET The Soft Reset configuration is provided by the debug port controller via the ADI I F Option is given to enter debug mode directly or only after exception 42 Local Interrupter The only external interrupt which is applied to the MPC via its interrupt controller is the ABORT NMI which is generated by a push button When this button is depressed the NMI input to the MPC is asserted The purpose of this type of interrupt is to support the use of resident debuggers if any is made available to the FADS other interrupts to the MPC are generated internally by the MPC s peripherals and by the debug port To support external off board generation of an NMI the IRQO line which is routed as an NMI input is driven by an open drain gate This allows for external h w to also drive this line If an external h w indeed does so it is compulsory that IRQO is driven by an open drain or open collector gate 4 3 Clock Generator There are 2 ways to clock the MPC on the MPC8XXFADS 1 3 5MHz Clock generator connected to CLKAIN input 1 5 PLL mode 2 32 768 KHz crystal resonator via EXTAL XTAL pair of the MPC 1 513 initial PLL multiplication factor The selection between the above modes is done using Dip switch DS2 4 with dual functionality it is re sponsible to the combination driven to the MODCK lines during power on reset and to the connection of the appropriate capacitor between MPC s XFC and VDDSYN l
161. all parts Therefore the below initializations are liable to CHANGE throughout the testing period TABLE 3 3 Memory Controller Initializations For 50Mhz Register Device Type Init Value hex Description BRO All Flash SIMMs 02800001 Base at 2800000 32 bit port size no parity GPCM supported ORO MCM29F020 90 00034 2MByte block size types access CS early negate 6 w s Timing relax 29 040 90 FFCOOD34 4 block size all types access CS early negate 5 732 1000 9 6 w s Timing relax 29 080 90 FF800D34 8MByte block size all types access CS early negate SM732A2000 9 6 w s Timing relax MCM29F 020 12 FFE00D44 2MByte block size all types access CS early negate 8 w s Timing relax MCM29F040 12 FFCO0D44 4 block size all types access CS early negate 5 732 1000 12 8 w s Timing relax MCM29F 080 12 FF800D44 8MByte block size all types access CS early negate 5 732 2000 12 8 w s Timing relax BR1 BCSR 02100001 Base at 2100000 32 bit port size no parity GPCM OR1 FFFF8110 32 KByte block size all types access CS early negate 1 w s BR2 All Dram SIMMs 00000081 Base at 0 32 bit port size no parity UPMA Supported OR2 MCM36100 200 60 70 FFC00800 4MByte block size all types access initial address multiplexing according to AMA MCM36400 800 60 70 FF000800 16MByte block size all types access initial address M
162. and remains on while the EEST has automatically corrected for the reversed wires 3 2 15 Ethernet LIL Indicator 010 The yellow Ethernet Twisted Pair Link Integrity LED indicator LIL lights to indicate good link integrity on the TP port The LED is off when the link integrity fails 3 2 16 5V Indicator LD11 The yellow led indicates the presence of the 5 supply at P6 23 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS 3 2 17 RUN Indicator 1012 When the green RUN led LD12 is lit it indicates that the MPC is in debug mode i e VFLSO amp VFLS1 0 or FRZ 0 which ever selected by J1 3 2 18 AUXILARY Indicator 1013 This indication has no dedicated function over the FADS It is meant to provide some visibility for program behavior It is controlled by the Signal Lamp bit in BCSR4 3 2 19 FLASH ON 1014 When the yellow FLASH ON led is lit it indicates that the FLASH SIMM is enabled in the BCSR1 register l e any access done to the 50 address space will hit the flash memory When it is dark the flash is disabled and CS0 may be used off board via the expansion connectors 3 2221 DRAM ON LD15 When the yellow DRAM ON led is lit it indicates the DRAM SIMM is enabled in BCSR1 Therefore any access made to CS2 or CS3 will hit on the DRAM When it is dark it indicates that either the DRAM is disabled in BCSR1 enabling the use of CS2 and CS3 off board via the expansio
163. anual Support Information n this file 9 The addressing scheme of the flash is changed so that the bank does not occupy a space bigger than its real size Le A9 and A10 use is conditioned with the module type In this 10 A bug is fixed in Smart flash memories presence detect encoding forSM732A1000A F PD 5 was 2 forSM732A2000 F PD 4 was 3 n this 11 power on reset input line is removed It was unused previously Instead of the the above PD4 input is added so excact identification may be given to any flash memory Number of delay stages for flash turn off time protection is decreased This to avoid possible problem in write to 0 w s memories In This file 12 Added ATA support for PCMCIA I e PecEvenEn and PecOddEn become identical enabled by logic OR of CE1 and CE2 module brdctl12 title MPC821ADS Board Misc Control Functions Originated for MPC821ADS Yair Liebman MSIL April 10 1995 Device declaration 022 device mach220a K K Kk K K K K K K K K E HHHO HHHH THHHHHE HHHH HR HHH H oS SE OH S HHH Hg og og HHHH HE HHHH
164. as no influence since the USB power is not operational there but for rev Pilot and up 823DB it is important K K K K module bcsr11 MPC8XXFADS Board Control and Status Register K K kk K K K K K K K K Device declaration 011 device 220 K k K K K K HHHO EE HHHH HHHHH HHH HR HHHO HHN H HN HHE H Hg HH H HHHH EE HE HHHH H HHHH H H gd UFGHHHHHHE H 8 HHHH H H H oH H HHHH HHH Pins declaration System i f pins k k kk K k KK K K K K SYSCLKPIN 15 RGPORInPIN 54 ResetConf PIN 45 141 Release 0 1 MPCSXXFADS User s Manual Support Information BrdContRegCs PIN 49 TA PIN 16 W PIN 50 27 17 28 20 29 51 DO 10 D1 11 D2 12 PIN 13 4 PIN 33 D5 PIN 14 D6 PIN 25 D7 PIN 24 D8 PIN 23 D9 PIN 22 10 PIN 21 11 29 D12 PIN 30 D13 PIN 31 D14 PIN 32 D15 PIN 9 Board Control Pins Read Write FlashEn PIN 62 istype reg buffer flash enable DramEn PIN 7 istype reg buffer dram enable Eth
165. ation 1 8 MPC8XXFADS Features 4 MByte Unbuffered Synchronous Dram On Board 4 MByte EDO 60nsec delay DRAM SIMM Support for 4 32 MByte FPM EDO Dram SIMM with Automatic Dram SIMM identification 16 Bit Data Bus Width Support 2 Flash SIMM Support for upto 8 MByte or 12V Programmable with Automatic Flash SIMM identification o Memory Disable Option for each local memory map slaves o Board Control amp Status Register BCSR Controlling Board s Operation o Programmable Hard Reset Configuration via BCSR o PCMCIA Socket With Full Buffering Power Control and Port Disable Option Com plies with PCMCIA 2 1 Standard o Module Enable Indications o 10 Base T Port On Board with Stand By Mode o Fast IrDA 4 Port with Stand By Mode o Dual RS232 port with Low Power Option per each port On Board Debug Port Controller with ADI I F MPC8XXFADS Serving as Debug Station for Target System option o Optional Hard Reset Configuration Burned in Flash o External Tools Identification Capability via BCSR o Soft Hard Reset Push Button o ABORT Push Button Single 5V Supply Reverse Over Voltage Protection for Power Inputs o 3 38V 2V MPC Internal Logic Operation 3 3V MPC I O Operation o Power Indications for Each Power Bus o Software Option Switch provides 16 S W options via BCSR A Available only if supported also on the MPC8XX B Hard reset is
166. bort P B Abril PIN 11 connected to of Abort P B NMIEnNODE istype enables T S NMI pin NMI PIN 44 istype Actual NMI pin O D k k Power On Reset Configuration Support K K Kk K K K K K K K K 64 MODCK dip switch Modck2PIN 60 istype com MODCK2 output Modck1PIN 66 istype output ModckOeNODE istype com enables MODCKs towards MPC8XX during Hard Reset k k k k k k R K K ER K kk K Kk k kK kk K k K K K K K K Data Buffers Enables and Reset configuration support K ER K kk K Kk Kk Kk K K K K K K 6 transfer Acknowledge TEA PIN 47 Transfer Error Acknowledge FlashCfgEn PIN 17 flash configuration enable from control register PccEn PIN 4 PCMCIA channel enable from control reg 1 16 PccCE2 PIN 43 UpperHalfEn PIN 3 istype com invert bits 0 15 data buffer enable LowerHalfEn PIN 5 istype com nvert bits 16 31 data buffer enable PccEvenEn PIN 14 istype com invert pcc upper byte data buffer enable PecOddEn PIN 37 istype comjnvert pcc lower byte data buffer enable 185 Release 0 1 MPCSXXFADS User s Manual Support Information PccR W PIN 62 istype com pcmcia data buffers direction HEHEHE HHHBHHE HHHH HHH i
167. buffers will open asynchronously driven directly by the various chip selects to provide data hold 0 on write cycles to flash CSNT bit in the OR should be programmed active while ACS 00 n This 6 A12 and A11 are removed from the flash selection equation since they can select only a 1 2 Mbyte of flash rather then 2Mbyte selection needed Therefore only one bank of 2 Mbyte flash may be used MCM29F020 The rest of the CS are driven high constantly oe oe n this 7 Pon Reset Out is removed Pon Reset is driven directly to MPC Modck0 becomes Modck2 A9 and A10 replace A11 and A12 in flash bank selection Optional BufClose is removed DramEn becomes active low to support debug station support changes Added F PD 1 3 to support SMART Flash SIMMs Support for 32KHz crystal renewed 1 s F gt F see s F R n this file 8 Added protection against data contention for write cycles after Flash read cycle This is achieved using a state machine which identifies end of flash read and a chain of internal gates serving as a delay line This kind of solution guaranties a fixed delay over the data buffer enable signal that is only after a flash read cycle 181 Release 0 1 MPCSXXFADS User s M
168. button is provided SW2 Depressing that button asserts the SRESET pin of the MPC generating a SOFT RESET sequence When SRESET line is asserted to the MPC the Soft Reset configuration is made available to the MPC by the debug port controller See 4 1 6 3 Soft Reset Configuration on page 37 4 1 4 Manual Hard Reset To support application development not around the debug port a Hard Reset push button is provided When the Soft Reset push button SW2 is depressed in conjunction with the ABORT push button SW1 the HRESET line is asserted generating a HARD RESET sequence The button sharing is for economy and board space saving and does not effect in any way functionality 4 1 5 MPC Internal Sources Since the HRESET and lines of the are open drain and the on board reset logic drives these lines with open drain gates the correct operation of the internal reset sources of the is facilitat ed As a rule an internal reset source asserts HRESET and or SRESET for a minimum time of 512 system clocks It is beyond the scope of this document to describe these sources however Debug Port Soft Hard Resets which are part of the development system are regarded as such A In fact generated on the daughter board B Again not directly C It is not a dedicated button D And therefore mentioned 36 Release 0 1 MPCSXXFADS User s Manual Functional Description 4 1 6 Reset Con
169. d as AT1 Not used on the FADS May be configured to any alternate function 45 GND 46 ATO B6 DSDI ATO Input Port B 6 or Debug Serial Data Input or Address Type 0 Configured on the as ATO May be used for alternate function 47 GND 48 POE A LL In fact OP1 of the PCMCIA Enables address buffers towards the PC Card 49 GND 50 51 52 BADDR30 I O X Burst Address Line 30 Dedicated for external master support Used to generate Burst address during external master burst cycles Pulled up but otherwise unused on the FADS 53 GND 90 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 9 PD2 Interconnect Signals Pin No Signal Name Attribute Description 54 ALE A H Address Latch Enable for PCMCIA slot A Latches address in external latches at the beginning of access to a PC Card 55 GND 56 BADDR29 I O X Burst Address Line 29 Dedicated for external master support Used to generate Burst address during external master burst cycles Pulled up but otherwise unused on the FADS 57 GND 58 AS I O L Asynchronous external master Address Strobe signal When asserted L by the external master the MPC recognizes an asynchronous cycle in progress Pulled up but otherwise unused on the FADS 59 GND 60 MODCK1 OP2 MODCK1 STS PCMCIA Output Port 2 or Mode Clock 1 input or Special Transfer Start output Us
170. dded BCSR2CS and BCSR3CS for external status registers Added controls on besr1 SdramEn 1 Added BCSR4 with following controls UsbFethEn bit 0 enables Usb or Fast Ethernet ports UsbSpeed bit 1 Usb speed control 1 full speed x UsbVccO bit 2 enables VCC for Usb channel UsbVccl bit 3 reserved for possible 3 3V usb power x VideoOn bit 4 enables video transceiver VideoExtClkEn bit 5 enables ext 27Mhz clock for video encoder VideoRst bit 6 resets the video encoder SignaLamp bit 7 used for s w signaling to user sk o coke F o oleo n this file 10 Added ethernet transceiver control signals to BCSR4 EthLoop bit 8 sets the transceiver to internal loopback H x TPFFLDL bit 9 sets the trans to full duplex mode L TPSQEL bit 10 allows for testing the colission ciruitry a of the 68160 bit 11 enables the modem tool with the MPC823FADSDB 140 Release 0 1 MPCSXXFADS User s Manual Support Information Modem Audio bit 12 selects between modem audio function for s modem tool with 823 daughter board oe oe K k k K n this 11 Corrected bug with UsbVccO and UsbVccl they were writen according to 0 and 1 data bits instead of UsbVccO and UsbVcc1 data bits For Eng 823DB it h
171. e DSCK DSDI are tri stated so no arbitrary data is sent to the debug port When inactive the interface is in normal mode i e DSCK and DSDI are driven and source of the Rx shift register is DSDO StatusRequest Bit 2 When active L any write to the control register will be followed by a status read cycle initiated by the debug port controller i e AdsReq will be asserted after the write cycle ends When inactive a write to the control register will not be followed by a read from status register DbgClkDivSel 1 0 Bits 4 3 This field selects the division of the DbgCIk input Division factors are set as follows 0 byl 5 by2 2 4 3 by8 Important bits wake up active L after reset kK Kk k Kk kK equations AdiCtrlReg clk AdiCtrlReg ar Reset All active low when HOST WRITE ADI CONTROL amp BndTmrExp fb then AdiCtrlReg d PD4 pin PD3 pin PD2 pin PD1 pin PDO pin else AdiCtrlReg d AdiCtrlReg fb 135 Release 0 1 MPCSXXFADS User s Manual Support Information ADI Data Bus The Adi data bus is driven towards the host when the host reads the i f When D C line is high data the Rx shift register contents is driven If D C is low control the status register contents is driven The status register
172. e 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 11 PD4 Interconnect Signals Pin No Signal Name Attribute Description 1 GND 2 D31 X MPC s Data line 31 3 GND 4 D30 X MPC s Data line 30 5 GND 6 D29 X MPC s Data line 29 7 GND 8 D28 X MPC s Data line28 9 GND 10 11 12 D27 X Data line 27 13 GND 14 D26 X MPC s Data line 26 15 GND 16 D25 X MPC s Data line 25 17 GND 18 D24 X MPC s Data line 24 19 GND 20 21 22 D23 X MPC s Data line 23 23 GND 24 D22 X Data line 22 25 GND 26 D21 X MPC s Data line 21 27 GND 28 D20 X MPC s Data line 20 102 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 11 PD4 Interconnect Signals Pin No Signal Name Attribute Description 29 GND 30 31 32 D19 X MPC s Data line 191 33 GND 34 D18 X MPC s Data line 18 35 GND 36 D17 X MPC s Data line 17 37 GND 38 D16 X MPC s Data line 16 39 GND 40 41 42 D15 X MPC s Data line 15 43 GND 44 D14 X MPC s Data line 14 45 GND 46 D13 X MPC s Data line 13 47 GND 48 D12 X MPC s Data line 12 49 GND 50 51 52 D11 X
173. e disabled in favor of external hardware the enable signals for these modules are presented at both the daughter board connec tor and at the expansion connector over the daughter board so that off board hardware may be mutually exclusive enabled with on board modules 4 11 1 BCSR Disable Protection Logic The BCSR itself may be disabled in favor of off board logic To avoid accidental disable of the BCSR event from which only power re appliance recovers protection logic is provided The BCSR EN bit resides on BCSR1 This bit wakes up active low during power up and may not be changed unless BCSR_EN_PROTECT bit in BCSR3 is written with 1 previously After the BCSR PROTECT is written with 1 to unprotect the BCSR EN bit there is only one shot at disabling the since immediately after any write to BCSR1 BCSR EN is re activat ed and BCSR is re protected and the disabling procedure has to be repeated if desired 4 11 2 gt BCSRO Hard Reset Configuration Register BCSRO is located at offset 0 on BCSR space It may be read or written at any timeF BCSRO gets its defaults upon MAIN Power On reset During Hard Reset data contained in BCSRO is driven on the data bus to provide the Hard Reset configuration for the MPC this if the Flash_Configuration_Enable bit in 5 1 is not active BCSRO may be written at any time to change the Hard Reset configuration of the MPC The new values become valid
174. ed this input selects operating speed bit 0 13 When this signal is high 100Mbps is selected 0 13 1 when low 10Mbps is selected 0 13 0 This signal has no function with any daughter boards R W A Provided that BCSR is not disabled 65 Release 0 1 MPCS8XXFADS User s Manual Functional Description TABLE 4 23 BCSRA Description BIT MNEMONIC Function PON DEF ATT USB FETHFDE USB Port EN Fast Ethernet Full Duplex EN When a MPC823 or a MPC850 daughter board is attached to the FADS this signal controls the power applied to the USB bus Master Mode support When this signal is active low 5V power is applied to the USB Bus When inactive power to the USB port is disconnected When a MPC821 860 860SAR 860T daughter board is attached to the FADS MPC860T resides it this signal controls the Full Duplex mode of the Fast Ethernet Transceiver LXT970 When auto negotiation is enabled this signal determines the full duplex advertisement capability of the LXT970 in conjunction with MF4 and CFG1 See the LXT970 documentation When auto negotiation is disabled this signal effects full duplex mode directly by setting the value of bit 0 8 Duplex Mode When this signal is high Full Duplex in Enabled 0 8 1 When this pin is low Full Duplex is Disabled 0 8 0 This signal has no function with any daughter board R W Reserved Imp
175. ed at Power On reset as MODCK1 For MPC823 or MPC850 daughter boards configured afterwards as a OP2 for all other daughter boards configured afterwards STS 61 GND 62 RESETA LH PC Card reset signal 63 GND 64 65 66 BADDR28 I O X Burst Address Line 28 Dedicated for external master support Used to generate Burst address during external master burst cycles Pulled up but otherwise unused on the FADS 67 GND 68 TEXP X X MPC Timer Expired Not used on the FADS 69 GND 70 _ L This signal is PCMCIA slot B wait signal Pulled up but otherwise not used on the FADS 71 GND 72 MODCK2 OPS MODCK2 DSDO PCMCIA Output Port 3 or Mode Clock 2 input or Special Transfer Start output Used at Power On reset as MODCK2 and configured afterwards as a be used with alternate function 73 GND 74 75 91 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 9 PD2 Interconnect Signals Pin No Signal Name Attribute Description 76 N C 77 GND 78 79 80 SRESET L MPC Soft Reset Driven by on board logic and may be driven by O D off board logic with Open Drain gate only 81 GND 82 PORST X L Power On reset for the MPC Not used on the FADS generated on the daughter boards 83 GND 84 HRESET L Hard Reset Driven by on board logic and may be driven by O D off board logic with
176. ed by the MPC s BRG clock which is not influenced by the MPC s low power divider 4 Release 0 1 MPCSXXFADS User s Manual Functional Description FIGURE 4 1 Refresh Scheme BRG Clock oy PTB UPMB 5 1 DRAM BANKS As seen in FIGURE 4 1 Refresh Scheme above the BRG clock is twice divided once by the PTP Pe riodic Timer Prescaler and again by another prescaler the PTA dedicated for each UPM If there are more than one dram banks than refresh cycles are performed for consecutive banks therefore refresh should be made faster The formula for calculation of the is given below Refresh Period X Number Of Beats Per Refresh Cycle Number Of Rows To Refresh X T X MPTPR X Number Of Banks PTA Where PTA Periodic Timer A filed in MAMR The value of the 2 nd divider Refresh Period is the time usually in msec required to refresh a dram bank Number Of Beats Per Refresh Cycle using the looping capability it is possible to perform more than one refresh cycle per refresh burst in fact upto 16 Number Of Rows To Refresh the number of rows in a dram bank T the cycle time of the clock MPTPR the value of the periodic timer prescaler 2 to 64 Number Of Banks number of dram banks to refresh If we take for example a MCM36200 SIMM which has the following dat
177. ed in TABLE 5 3 P3 Ethernet 76 Release 0 1 MPCSXXFADS User s Manual Support Information Port Interconnect Signals below TABLE 5 3 P3 Ethernet Port Interconnect Signals Pin No Signal Name Description 1 TPTX Twisted Pair Transmit Data positive output from the MPC8XXFADS 2 Twisted Pair Transmit Data negative output the MPC8XXFADS 3 TPRX Twisted Pair Receive Data positive input to the MPC8XXFADS 4 Not connected 5 Not connected 6 TPRX Twisted Pair Receive Data negative input to the MPC8XXFADS 7 Not connected 8 Not connected 5 1 4 PCMCIA Port Connector The PCMCIA port connector P4 is a 68 pin Male 909 PC Card type signals of which are presented in TABLE 5 4 P4 PCMCIA Connector Interconnect Signals below TABLE 5 4 P4 PCMCIA Connector Interconnect Signals Pin No Signal Name Attribute Description 1 GND Ground 2 PCMCIA Data line 3 3 4 PCMCIA Data line 4 4 PCCD5 y o PCMCIA Data line 5 5 PCCD6 PCMCIA Data line 6 6 PCCD7 PCMCIA Data line 7 7 BCE1A PCMCIA Chip Enable 1 Active low Enables EVEN numbered address bytes 8 10 PCMCIA Address line 10 9 OE PCMCIA Output Enable signal Active low Enables data outputs from PC Card during memory read cycles 10 PCCA11 Address line 11 11 PCCA9 PC
178. ed in conjunction with the addressing lines to generate a Hard Reset to the MPC8XXFADS board When this signal is driven in conjunction with the ADS SRESET signal the ADI I F state machines and registers are reset HOST REQ l This signal initiates a host to MPC8XXFADS write cycle ADS ACK O This signal is the MPC8XXFADS response to the HOST REQ signal indicating that the board has detected the assertion of HOST REQ ADS REQ O This signal initiates an MPC8XXFADS to host write cycle This signal serves as the host s response to the ADS REQ signal HOST VCC l three lines These lines are power lines from the host computer In the MPC8XXFADS these lines are used by the hardware to determine if the host computer is powered on PD 0 7 These eight I O lines are the parallel data bus This bus is used to transmit and receive data from the host computer 199 Release 0 1 MPCSXXFADS User s Manual Support Information APPENDIX B ADI Installation 1 INTRODUCTION This appendix describes the hardware installation of the ADI board into various host computers The installation instructions cover the following host computers 1 IBM PC XT AT 2 SUN 4 SBus interface Be2 IBM PC XT AT to MPC8XXFADS Interface The ADI board should be installed in one of the IBM PC XT AT motherboard system expansion slots A single ADI can control up to eight MPC8XXFADS boards The ADI address in the co
179. egCs amp TA amp R_W amp A27 amp A28 amp A29 amp CntRegEn Besr1 Write BrdContRegCs amp TA amp amp A27 amp A28 amp A29 amp CntRegEn Besr4Write BrdContRegCs amp TA amp R_W amp A27 amp A28 6 A29 amp CntRegEn ConfigReg clk SYSCLK state diagram ERB state INTERNAL ARBITRATION if WRITE 0 amp DATA EXTERNAL ARBITRATION 4 PON RESET PON DEFAULT INTERNAL ARBITRATION KA PON RESET amp ERB PON DEFAULT EXTERNAL ARBITRATION then EXTERNAL ARBITRATION else INTERNAL ARBITRATION state EXTERNAL ARBITRATION if WRITE BCSR 0 amp DATA BIT pin INTERNAL ARBITRATION amp PON RESET PON DEFAULT EXTERNAL ARBITRATION KA PON RESET amp ERB PON DEFAULT INTERNAL ARBITRATION then INTERNAL ARBITRATION else EXTERNAL ARBITRATION k kok k kok ak state diagram IP state IP OxFFF00000 if MPC WRITE BCSR 0 amp IP DATA BIT pin IP AT 0x00000000 amp PON RESET IP PON DEFAULT AT OxFFF00000 PON RESET amp IP PON DEFAULT IP AT 0x00000000 then IP AT 0x00000000 else IP OxFFF00000 state IP AT 0x00000000 154 Release 0 1 MPCSXXFADS User s Manual Support Information if WRITE 0 amp IP DATA BIT pin IP AT OxFFF00000 amp PON RESET IP PON DEFA
180. else when STATE TX ENABLED amp STATE TX ON RISING amp CIK2 STATE TX ENABLED amp STATE TX ON FALLING amp 2 then TxReg7 TxRegl TxReg6 TxReg0 fb shifting MSB I st else TxReg7 TxReg1 TxReg7 TxReg1 fb Holding value when HOST WRITE ADI DATA amp BndTmrExp fb amp STATE TX ENABLED then TxReg0 PDO pin else when STATE TX ENABLED amp STATE TX ON RISING amp CIK2 STATE TX ENABLED amp STATE TX ON FALLING amp 2 then TxReg0 RxReg0 fb else TxReg0 TxReg0 fb 132 Release 0 1 MPCSXXFADS User s Manual Support Information Receive Shift Register A single stage shift register used as a source for the Tx shift register n normal mode the input for the Rx shift register is the MPC8XX s DSDO while in diagnostic loopback mode data is taken directly from the Tx shift serial output output of the Rx shift register is fed to the input of the Tx shift register When transmission and reception is done the received data word is compossed of the Rx shift register LSB concatenated with the 7 LSBs of the Tx shift register The edge in CIK2 terms upon which data is shifted is determined by TxClkSns as with the Tx shift register but on opposite edges 1 data is shifted Out from the Tx shift register on the Falling edge of DSCK while is shifted In to the Rx shift register on the Risi
181. es FED YELLOW 180 4 FLASH ENABLED 7 gt gt 2 R56 4 07 2 025 0 1UF 13 L4D_YELLOW Cag C80 74 541 2 82 V SGLAMP alae 1017 EN DRAMEN 3 A2 Y2 17 LED YE W FEN alas 316 2 4 5252 PORT 1 ENABLED tB 103 RS ENT 5 vali4 RA IRD_EN 7 1 LED_YELIQW ETHER alae e SR 1 2 INFRA RED ENABLED A7 Y7 2 1 102 RS 2 olaa va at LED YELIQW ETHERNET ENABLED CHINS 19 75 MOTOROLA INC 8 R71 R72 4 R75 are not LED YELtQUW 2 85232 PORT 2 ENABLED PROJECT MPCBXXFADS REV PILOT SHEET 9 OF 14 assembeled Left as contingency 2 RIO for 012 104 YAIR LIEBMAN BLOCK POWER amp INDICATORS R29 should be installed for 3 3V DRAM SIMMs only CHK 3 DESCRIP A B D E G H J K tmp_mnt net prince yair 8xx fads m brd pilot sc h 10 drw 07 MAY 97 16 59 lost update 07 MAY 97 16 58
182. ever require 12V 0 5 programming voltage to be applied for programming If on boards programming of such device is required a 12V supply needs to be connected to the FADS P7 Otherwise for normal Flash operation 12V supply is not required The control over the flash is done using the GPCM and a dedicated 50 region controlling the whole bank During hard reset initializations the debugger reads the Flash Presence Detect lines via BCSR2 and decides how to program BRO amp ORO registers within which the size and the delay of the region are determined The performance of the flash memory is shown in TABLE 4 5 Flash Memory Performance Figures A manufacturer specific dedicated programming algorithm should be implemented during flash programming B I e Read Only 45 Release 0 1 MPCSXXFADS User s Manual Functional Description below TABLE 4 5 Flash Memory Performance Figures Number of System Clock Cycles System Clock Frequency MHz 50 25 Flash Delay nsec 90 120 90 120 Read Write Access Clocks 8 10 4 5 a The figures in the table refer to the actual write access The write operation continues internally and the device has to be polled for operation completion The Flash module may disabled enabled at any time by writing 1 0 the FlashEn bit in BCSR1 48 Synchronous Dram To enhance performance especially in higher operation frequencies 4 MBytes of
183. figuration During reset the MPC device samples the state of some external pins to determine its operation modes and pin configuration There are 3 kinds of reset levels to the MPC each level having its own configuration sampled 1 Power On Reset configuration 2 Hard Reset configuration 3 Soft Reset Configuration 4 1 6 1 Power On Reset Configuration Just before PORESET is negated by the external logic the power on reset configuration which include the MODCK 1 2 pins is sampled These pins determine the clock operation mode of the MPC Two clock modes are supported on the MPC8XXFADS 1 1 5 PLL operation via on board clock generator In this mode MODCK 1 2 are driven with 711 during power on reset 2 1 513 PLL operation via on board clock generator In this mode MODCK 1 2 are driven with 00 during power on reset 4 1 6 2 Hard Reset Configuration During HARD reset sequence when RSTCONF is asserted the data bus state is sampled to acquire the MPC s hard reset configuration The reset configuration word is driven by BCSRO register defaults of which are set during power on reset The BCSRO drives half of the configuration word i e data bits D 0 15 in which the reserved bits are designated RSRVxx If the hard reset configuration is to be changed BCSRO may be written with new values which become valid after HARD reset is applied to the MPC On the FADS the RSTCONF line is always driven during HARD
184. formation to use the MPC8XXFADS in host controlled and stand alone configurations This includes controls and indicators memory map details and software initialization of the board 3 2 CONTROLS AND INDICATORS The MPC8XXFADS has the following switches and indicators 3 2 1 ABORT Switch SW1 The ABORT switch is normally used to abort program execution this by issuing a level 0 interrupt to the MPC If the FADS is in stand alone mode it is the responsibility of the user to provide means of handling the interrupt since there is no resident debugger with the MPC8XXFADS The ABORT switch signal is debounced and can not be disabled by software 3 2 2 SOFT RESET Switch SW2 The SOFT RESET switch SW2 performs Soft reset to the MPC internal modules maintaining MPC s configuration clocks amp chip selects Dram and SDram contents The switch signal is debounced and it is not possible to disable it by software At the end of the Soft Reset Sequence the Soft Reset Configuration is sampled and becomes valid 3 2 3 HARD Switches SW1 amp SW2 When BOTH switches SW1 and SW2 are depressed simultaneously HARD reset is generated to the MPC When the MPC is HARD reset all its configuration is lost including data stored in the DRAM or SDRAM and the MPC has to be re initialized At the end of the Hard Reset sequence the Hard Reset Configuration stored BCSRO becomes valid 3 2 4 051 Software Options Switch DS1 is a 4 switches
185. functions are controlled monitored by the BCSR MPOC s Hard Reset Configuration Flash Module Enable Disable Dram Module Enable Disable Dram port width 32 bit 16 bit SDRAM Module Enable Disable Ethernet port Enable Disable N Infra Red port Enable Disable 85232 port 1 Enable Disable RS232 port 2 Enable Disable 10 BCSR Enable Disable c 11 Hard Reset Configuration Source BCSRO Flash Memory 12 PCMCIA control which include Channel Enable Disable A Le card insertion when the FADS is powered B In fact only the upper 16 bits D 0 15 are used but the BCSR is mapped as a 32 bit wide register and should be accessed as such C Provided that support is provided also within the MPC 53 Release 0 1 MPCSXXFADS User s Manual Functional Description Card VCC appliance PC Card VPP appliance USB Port Enable or Utopia Port Enable or 100 Port Enable USB Power Control Video Port Enable Video Port Clock Select Ethernet Port Control Flash Size Delay Identification External off board tools identification or S W option selection switch DS1 status Daughter Board ID 18 Dram Type Size and Delay Identification Mother Board Revision code 23 Daughter Board Revision code Since all of the FADS s modules are controlled by the BCSR and since they may b
186. ghter Board Revision Code Signal 2 The LMSB of the D B revision Code See TABLE 4 13 BCSR2 Description on page 60 96 EXTOLI3 X External Tool Identification 3 Connected to BCSR2 See 4 11 4 BCSR2 Board Control Status Register 2 on page 59 97 BCSR3R1 X Reserved signal 1 BCSR3 See TABLE 4 19 BCSR3 Description on page 63 98 DBREV1 X Daughter Board Revision Code Signal 1 See TABLE 4 13 BCSR2 Description on page 60 99 DBID1 X Daughter Board ID Code 1 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 63 100 BCSR3RO X Reserved signal 0 in BCSR3 See TABLE 4 19 BCSR3 Description on page 63 101 DBID3 X Daughter Board ID Code 3 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 63 102 DBIDO X Daughter Board ID Code 0 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page 63 105 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 11 PD4 Interconnect Signals Pin No Signal Name Attribute Description 103 DBID5 X Daughter Board ID Code 5 Part of the field which designates the type of daughter board connected See TABLE 4 19 BCSR3 Description on page
187. h 10Mbps link test is disabled 19 8 1 When this pin is low 10Mbps link test is enabled 19 8 0 This signal has no function with any daughter board R W 10 VIDEO RST FETHRST Video Port Reset Fast Ethernet Txcvr Reset When a MPC823 daughter board is attached to the FADS this signal resets the Video Encoder When this active low signal is being asserted the Video Encoder located on MPC823FADSDB is being reset For further informations see 4 4 VIDEO Support on page 13 of the MPC823FADSDB User s Manual When a MPC821 860 860SAR 860T daughter board is attached to the FADS and a 860 resides on it this signal resets the LXT970 Fast Ethernet transceiver When active low the LXT970 transceiver is reset This signal has no function with any other daughter board R W 66 Release 0 1 MPC8XXFADS User s Manual Functional Description TABLE 4 23 BCSRA Description PON BIT MNEMONIC Function DEF ATT 11 MODEM EN Modem Enable for MPC823 When this signal is active low while an 1 RW MPC823FADSDB is connected to the FADS it is possible to operate the MPC821 Modem Tool This signal has no function with any other daughter board 12 DATA VOICE Modem Tool Function Select Effective only with MPC823AFDSDB When 1 This signal is high the DATA function of the modem tool is selected When low the VOICE function of the modem tool is selected
188. h encode the SIMM s Type but appear in BCSR2 For the encoding of FLASH PD 7 5 see TABLE 4 22 FLASH Presence Detect 7 5 Encoding on page 64 BREVN1 Board Revision Number 1 Second bit of the Board Revision Number See TABLE 4 18 MPC8XXFADS Daughter Boards Revision Encoding on page 62 for the interpretation of the Board Revision Number Reserved Implemented 14 15 BREVN 2 3 Board Revision Number 2 3 The LS bits of the Board Revision Number See TABLE 4 18 MPC8XXFADS Daughter Boards Revision Encoding on page 62 for the interpretation of the Board Revision Number a This is a WRITE ONLY bit so it does not conflict with the DBID filed which is READ ONLY 63 TABLE 4 20 Daughter Boards ID Codes MPC8XX On D B DBID 0 5 HEX 0 Reserved Release 0 1 MPCSXXFADS User s Manual Functional Description TABLE 4 20 Daughter Boards ID Codes DBID 0 5 MPC8XX On HEX D B 1 2 Reserved 3 MPC823 4 1F Reserved 20 MPC801 21 MPC850 22 MPC821 MPC860 860SAR 860T 23 MPC860SAR 24 860 23 3F Reserved For MPC821 860ADS Revision Number 0 3 sapcgxxFADS Revision Hex 0 Reserved 1 ENG Engineering 1 PILOT l 2 F Reserved a There is no electrical difference between revi TABLE 4 21 MPC8XXFADS Revision Number Convers
189. h values described in TABLE 3 8 UPMB Initializations for MB811171622A 100 upto 32MHzZ on page 34 or in TABLE 3 9 UPMB Initializations for MB811171622A 100 324 MHz on page 35 Memory controllers MPTPR MBMR 4 and registers should be programmed according to TABLE 3 6 Memory Controller Initializations For 20Mhz on page 30 or TABLE 3 3 Memory Controller Initializations For 50Mhz on page 27 MAR should be set with proper value 0x48 for upto 32 2 or 0x88 for 32 50 MHz MCR should be written with 0x80808105 to run the MRS command programmed in locations 5 8 of UPMB MBMR s TLFB field should be changed to 8 to constitute 8 beat refresh Bursts MCR should be written with 0x80808130 to run the refresh sequence 8 refresh cycles are per formed now MBMR s TLFB field should be restored to 4 to provide 4 beat refresh Bursts for normal opera tion The SDRAM is initialized and ready for operation SDRAM Refresh The SDRAM is refreshed using its auto refresh mode l e using UMPB s periodic timer a burst of four auto refresh commands is issued to the SDRAM every 62 4 usec so that all 2048 SDRAM rows are freshed within specified 32 8 msec Release 0 1 MPC8XXFADS User s Manual Functional Description 4 9 Communication Ports Since the FADS platform is meant to serve all the MPC8XX family it only contains modules that are common to all family members The various communication ports for t
190. he EEST so the collision detection circuitry within the EEST may be tested R W SIGNAL_LAMP Signal Lamp When this signal is active low a dedicated LED illuminates When in active this led is darkened This led is used for S W signalling to user R W USB USB port Enable or Fast Ethernet Port Enable When this signal is active low it enables the USB port transceiver in case an MPC823 daughter board is attached to the FADS or it enables the Fast Ethernet Transceiver LXT970 if 860 chip resides on the 821 860 8605 860 daughter board attached to the FADS This signal has no function with the MPC801 daughter board neither with MPC821 860 860SAR chips residing MPC821 860 860SAR 860T daughter boards R W USB_SPEED FETHCFG0 USB Port Speed or Fast Ethernet Txcvr Config 0 When a MPC823 daughter board is attached to the MPC8XXFADS this signal controls the speed of the USB transceiver When this signal is active high the USB transceiver is in full speed mode When inactive the USB transceiver is in low speed mode When MPC821 860 860SAR 860T daughter board is attached to the FADS and a 860 resides on it this signal controls the auto negotiation mode of the LXT970 Fast Ethernet transceiver When the LXT970 is in auto negotiation mode a low to high transition of this signal causes an auto negotiate to re start When auto negotiation is disabl
191. he present and future family members are shown in TABLE 4 8 MPC8XX Family Comm Ports below TABLE 4 8 MPC8XX Family Comm Ports Family Member MPC ein 801 823 821 860 860SAR 860T ort SCCI IrDA USB 3 Enet 3 Enet 3 Enet 3 Enet SCC2 Uart IrDA 3 Enet 3 IrDA 3 Enet 3 Enet 3 Enet Fast IrDA IrDA IrDA SCC3 3 Enet 3 Enet 3 Enet SCC4 3 Enet 3 Enet 3 Enet SMCI 3 Uart 3 Uart 3 Uart 3 Uart 3 Uart SMC2 3 TDM 3 Uart 3 Uart 3 Uart 3 Uart Only SPP 3 3 3 3 3 3 3 3 3 9 3 3 Fast Enet 3 Utopia 3 a This is an interchip protocol and therefore will not be supported for evaluation As be seen from the above table the Ethernet and Uart 5232 support are common to ali family members Therefore the FADS is equipped with 2 port of 85232 each with independent enable via BCSR and an IRDA transceiver supporting Fast IRDA 4 9 1 Ethernet Port An Ethernet port with 10 Base T I F is provided on the MPC8XXFADS The comm port over which this port resides is determined according to MPC type Use is done with the MC68160 EEST 10 base T transceiver used also with the MPC8XXFADS To allow alternative use of the Ethernet s SCC pins they appear at the expansion connectors over the daughter board and over the Comm Ports expansion connector P8 of the this board while the Ethernet transceiver may be Disabled Enabled
192. ignates that the RS232 transceiver connected to PA2 is active and communication via that medium is allowed When darkened it designates that the transceiver is in shutdown mode so its associated MPC pins may be used off board via the expansion connectors 3 2 9 65232 Port 2 ON 104 When the yellow 85232 Port 2 ON led is lit it designates that 5232 transceiver connected to PB2 is active and communication via that medium is allowed When darkened it designates that the transceiver is in shutdown mode so its associated MPC pins may be used off board via the expansion connectors 3 2 10 Ethernet RX Indicator 05 The green Ethernet Receive LED indicator blinks whenever the EEST is receiving data from one of the Ethernet port 3 2 11 Ethernet TX Indicator 106 The green Ethernet Receive LED indicator blinks whenever the EEST is transmitting data via the Ethernet port 3 2 12 Ethernet JABB Indicator LD7 The red Ethernet TP Jabber LED indicator JABB lights whenever a jabber condition is detected on the TP ethernet port 3 2 13 Ethernet CLSN Indicator 108 The red Ethernet Collision LED indicator CLSN blinks whenever a collision condition is detected on the ethernet port i e simultaneous receive and transmit 3 2 14 Ethernet PLR Indicator LD9 The red Ethernet TP Polarity LED indicator PLR lights whenever the wires connected to the receiver input of the ethernet port are reversed The LED is lit by the EEST
193. ines to match the PLL s multiplication factor When 1 5 mode is selected a capacitor of 5nF is connected while when 1 513 mode is selected 0 68uF capacitor is connected parallel to it via a TMOS gate The capacitors values are calculated to support a wider range of multiplication factors as possible When mode 2 above is selected the output of the clock generator is gated from EXTCLK input and driven to 0 constantly so that a jitter free system clock is generated On board logic is clocked by the MPC s CLKOUT coming from the Daughter board This clock is multi plexed with the debug port s clock generator so that on board logic is always clocked even when the MPC is removed from its socket 4 4 Buffering As the FADS meant to serve also as a hardware development platform it is necessary to buffer the MPC from the local bus so the MPC s capacitive drive capability is not wasted internally and remains available for user s off board applications via the expansion connectors Buffers are provided for address and strobe lines while transceivers are provided for data Since the ca pacitive load over dram s address lines mightF exceed 200 pF the dram address lines are separately buff D DSCK is configured at hard reset to reside on the JTAG port A Although this module resides on the DAUGHTER boards it is described here as it is common to all MPC8XX supported B Located On the Daughter Board C When the FADS serves a debug
194. insConnected node istype com K K K K Udo dbOGHHHE HH Sh HHH d S HEH HH 4 HHH 4 HH SU HHA GHUHE HOO dGHHHHHE HHR b H He Hik 4 4 GHHHHHE Hit HHH PHHH HORE HHH odd dO odo do HH p 4 4 Hon dd eA A d HH Hh Vd HHH k KK k H L X Z 1 0 X 27 C D U C D U K K Kk K k K K k K K K SLOW_32K_LOCK 1 K k k k k k k kk k kk k kK kk K k KK k Signal groups K Kk K K K K K K K K PdaAdd A9 A10 A19 A20 A30 187 Release 0 1 MPCSXXFADS User s Manual Support Information DramAdd DramAdd10 DramAdd9 DramCS DramBank2Cs DramBank1Cs RAS Rasl Ras1 DD Ras2 Ras2DD SD SizeDetect1 SizeDetect0 FlashCsOut FlashCs4 FlashCs3 FlashCs2 FlashCs1 Reset HardReset SoftReset ResetEn HardResetEn SoftResetEn Rst Rst1 Rst0 Abr Abr1 Abr0 Debounce RstDebl AbrDebl DramCs DramBank2Cs DramBank1Cs Cs ContRegCs FlashCs DramBank1Cs DramBank2Cs PccCs PccCE1 PccCE2 LocDataBufEn Up
195. ion Table sion PILOT to Revision ENG of the MPC8XXFADS mother board TABLE 4 22 FLASH Presence Detect 7 5 Encoding FLASH 7 5 Flash Delay nsec 000 Not Supported 001 150 010 120 011 90 100 111 Not Supported 64 Release 0 1 MPC8XXFADS User s Manual Functional Description 4116 BCSR4 Board Control Status Register 4 The 5 4 serves as a control register on the FADS It is accessed at offset 10H from BCSR base address It may be read or written at any time BCSR4 gets its defaults upon Power On reset Most of BCSRA pins are available at the daughter board connectors and on the expansion connectors residing over the daughter boards providing visibility towards daughter boards and external logic BCSRA fields are de scribed in TABLE 4 23 5 4 Description 65 TABLE 4 23 BCSRA Description BIT MNEMONIC Function PON DEF ATT ETHLOOP Ethernet port Diagnostic Loop Back When active high the MC68160 EEST is configured into diagnostic Loop Back mode where the transmit output is internally fed back into the receive section R W TFPLDL Twisted Pair Full Duplex When active low the MC68160 EEST is put into full duplex mode where simultaneous receive and transmit are enabled R W TPSQEL Twisted Pair Signal Quality Error Test Enable When active low a simulated collision state is generated within t
196. is designed to accept 14 to 22 AWG wires It is recommended to use 14 to 18 AWG wires 2 46 ADI Installation For ADI installation on various host computers refer to APPENDIX B ADI Installation on page 200 2 4 7 Host computer to MPC8XXFADS Connection The MPC8XXFADS ADI interface connector P1 is a 37 pin male D type connector The connection between the MPC8XXFADS and the host computer is by a 37 line flat cable supplied with the ADI board FIGURE 2 9 below shows the pin configuration of the connector FIGURE 2 9 P1 ADI Port Connector 1 NC Gnd 20 Gnd 21 2 Gnd 22 3 Gnd 125 4 ADS SRESET Gnd 24 5 ADS HRESET Gnd 55 6 ADS SEL2 12 N C 26 7 ADS HOST VCC 9 HOST REQ HOST VCC 28 10 ADS REQ HOST VCC 29 11 ADS ACK HOST ENABLE 30 12 31 13 32 14 Gnd 33 15 PDO 34 16 PD1 PD2 35 36 17 PDS 37 19 PD NOTE Pin 26 on the ADI is connected to 12 v power supply but it is not used in the MPC8XXFADS 2 4 8 Terminal to MPC8XXFADS 5 232 Connection A serial RS232 terminal or any other RS232 equipment may be connected to the RS 232 connectors PA2 and PB2 The RS 232 connectors is a 9 pin female Stacked D type connector as shown in FIGURE 2 10 The connectors are arranged in a manner that allows for 1 1 connection with the serial port of an IBM AT or compatibles i e via
197. its or Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does any liability arising out of the application or use of any product or circuit and specifically disclaims any and orola assume all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s echnical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola produc 5 for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable a
198. ized as 1 M X 4 60 nsec delay U8 2 MByte Flash SIMM 90 nsec Motorola MCM29020S90 delay U9 U16 U17 U36 Octal CMOS Latch Motorola 74ACT373D U10 012 013 014 015 021 031 Octal CMOS Buffer Motorola 74LCX541D U35 U37 U38 U41 U42 018 3 3V Linear Voltage regulator 5A Micrel MIC29500 3 3BT output U19 U20 U24 U44 Octal CMOS Bus Transceiver Motorola 74LCX245D U23 U43 SDRAM 2 X 2 X 512K X 16 Fujitsu MB811171622A 100 U25 Schmitt Trigger Hex Inverter Motorola 74ACT14D U26 Voltage level detector Range Seiko 5 8052 2 595V to 2 805V output U27 Octal Tri State Buffer Motorola 74ACT541D U28 Quad CMOS buffer with individual Motorola 74LCX125D Output Enable U29 Buffer Schmitt Trigger Motorola MC74LS244D U30 Dual Channel PCMCIA Power Linear LTC1315cG Controller Technology U32 U34 Octal CMOS Bus Transceiver Motorola 74ACT245D U33 Clock generator 20MHz Jauch VX 3A 100ppM 5V HCMOS output SMD 039 Dual CMOS 4 gt 1 MUX Motorola 74ACT157D Release 0 1 111 MPCSXXFADS User s Manual Support Information TABLE 5 12 MPC8XXFADS Part List Reference Designation Part Description Manufacturer Part Y1 Crystal resonator 20 MHz MEC Modern HC 49 U SM 3 Fundamental Oscillation mode Enterprise Frequency tolerance 50 ppm Corporation Drive level 1mW 0 2 mW Shunt capacitance 7pF Max Load capacitance 32pF Equivalent Series Resistance 500 Max Insulation Resista
199. le When asserted low the RS232 transceiver for port 1 R W 2 is enabled When negated the RS232 transceiver for port 2 is in standby mode and the relevant MPC communication port pins are available for off board use via the expansion connectors 14 SDRAMEN SDRAM Enable When this bit is active high the SDRAM module is 1 enabled on the local memory map When in active the DRAM is place in low power mode in fact removed from the local memory map allowing its associated CS line to be used off board via the expansion connectors 15 PCCVCC1 Pc Card VCC Select 1 These signal in conjunction with PCCVCCO 0 RW determine the voltage applied to the PCMCIA card s VCC Possible values are 0 3 3 5 V For the encoding of these lines and their associated voltages see TABLE 4 11 PCCVCC 0 1 Encoding on page 59 16 31 Reserved Un implemented a Shaded areas are additions with respect to the MPC8XXFADS b In case a Single Bank DRAM SIMM is used CS3 is free as well c Provided that this option is supported by the MPC by driving address lines low and asserting CSO during Hard Reset d It is written in BCSR3 58 Release 0 1 MPCSXXFADS User s Manual Functional Description TABLE 4 11 PCCVCC 0 1 Encoding P VEG 00 0 01 5 10 3 3 11 0 TABLE 4 12 PCCVPP 0 1 Encoding 0 1 7 VIS 00 0 01 5 10 128 11 Hi Z
200. lemented R W VIDEO_ON Video Port Enable When this signal is active low the Video On Led on the MPC823FADSDB is lit When inactive the led is darkened This is merely an indication that should be set by application S W to indicate activity of the Video Port after it has been enabled the port This signal has no function with any daughter board other the MPC823 daughter board R W VDO_EXT_CLK_ EN FETHCFG1 Video Port Clock Enable Fast Ethernet Txcvr Config 0 When a MPC823 daughter board is attached to the FADS and this signal enables the on board Video Clock Generator When this signal is active high it enables an on board 27MHz clock generator as a source for both the video encoder and the video port controller of the MPC823 The system programmer should avoid asserting this signal until it is assured that the MPC823 is set to accept external video clock Failure in doing so might result in permanent damage to the MPC823 and the on board 27 MHz clock generator When a MPC821 860 860SAR 860T daughter board is attached to the FADS and a MPC860T resides on it this signal controls the CFG1 input of the LXT970 When the LXT970 is in auto negotiation mode this pin determines operating speed advertisement capability in conjunction with MF4 See the LXT970 documentation When auto negotiation is disabled this signal enables 10Mbps link test function and directly effects bit 19 8 When this pin is hig
201. line Pulled up but otherwise not used on the FADS 131 V3 3 132 N C 133 V3 3 134 NMI L Non Makable Interrupt In fact IRQ0 of the MPC Driven by on board logic by O D gate Pulled up May be driven off board by O D gate only 135 V3 3 136 N C 137 V3 3 138 N C 139 V3 3 140 N C 94 a Be aware that TRST is connected to GND with a zero ohm resistor Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 10 PD3 Interconnect Signals Pin No Signal Name Attribute Description 1 ETHRX O X Ethernet port Receive Data When the ethernet port is disabled BCSRt1 tri stated Appears also at P8 2 GND 3 4 UUFEN O L Usb Port Enable or Utopia Port enable or Fast Ethernet port Enable Generated by BCSR4 See TABLE 4 23 BCSR4 Description on page 65 5 ETHTX LX Ethernet Port Transmit Data Appears also at P8 6 GND 7 8 PC9 X X MPC s C 9 pin Appears also at P8 but otherwise unused the FADS 9 IRDRXD O X InfraRed Port Receive Data When the I R port is disabled via BCSR1 tri stated Appears also at P8 10 GND 11 IRDTXD LX InfraRed Port Transmit Data Appears also at P8 12 GND 13 14 PC8 X port C 8 Appears also at P8 but otherwise unused 15 PA11 X port A 11 Appears also at P8 but otherwise unused 16 GND 17 PA10
202. ller For Target System Operation Scheme Stand Alone Configuration P6 Power Connector P7 12 Power Connector P1 ADI Port Connector PA2 PB2 RS 232 Serial Port Connectors Memory SIMM Installation DS1 Description Refresh Scheme DRAM Address Lines Switching Scheme Flash Memory SIMM Architecture SDRAM Connection Scheme RS232 Serial Ports Connector PCMCIA Port Configuration Debug Port Controller Block Diagram Standard Debug Port Connector MPC8XXFADS Power Scheme ADI Port Connector Physical Location of jumper JG1 and JG2 JG1 Configuration Options ADI board for SBus Release TABLE 1 1 TABLE 3 1 TABLE 3 2 TABLE 3 3 TABLE 3 4 TABLE 3 5 TABLE 3 6 TABLE 3 7 TABLE 3 8 TABLE 3 9 TABLE 4 1 TABLE 4 2 TABLE 4 3 TABLE 4 4 TABLE 4 5 TABLE 4 6 TABLE 4 7 TABLE 4 8 TABLE 4 9 TABLE 4 10 TABLE 4 11 TABLE 4 12 TABLE 4 13 TABLE 4 14 TABLE 4 15 TABLE 4 16 TABLE 4 17 TABLE 4 18 TABLE 4 19 TABLE 4 20 TABLE 4 21 TABLE 4 22 TABLE 4 23 TABLE 4 24 TABLE 4 25 TABLE 4 26 TABLE 5 1 TABLE 5 2 TABLE 5 3 TABLE 5 4 TABLE 5 5 TABLE 5 6 TABLE 5 7 TABLE 5 8 TABLE 5 9 MPCSXXFADS User s Manual LIST OF TABLES MPC8XXFADS Specifications MPC8XXADS Main Memory SIU REGISTERS PROGRAMMING Memory Controller Initializations For 50Mhz UPMA Initializations for 60 DRAMs 50MHz UPMA Initializations for 0 EDO DRAMs 50MHz Memory Contro
203. ller Initializations For 20Mhz UPMA Initializations for 0 EDO DRAMs 20MHz UPMB Initializations for MB811171622A 100 upto 32MHz Initializations for MB811171622A 100 32 MHz 50MHz MPC8XXFADS Chip Selects Assignment Regular DRAM Performance Figures EDO DRAM Performance Figures DRAM ADDRESS CONNECTIONS Flash Memory Performance Figures Estimated SDRAM Performance Figures SDRAM s Mode Register Programming MPC8XX Family Comm Ports BCSRO Description BCSR 1 Description PCCVCC 0 1 Encoding PCCVPP 0 1 Encoding BCSR2 Description Flash Presence Detect 4 1 Encoding DRAM Presence Detect 2 1 Encoding DRAM Presence Detect 4 3 Encoding EXTOOLI 0 3 Assignment MPC8XXFADS Daughter Boards Revision Encoding BCSR3 Description Daughter Boards ID Codes MPC8XXFADS Revision Number Conversion Table FLASH Presence Detect 7 5 Encoding BCSRA Description Debug Port Control Status Register DSCK Frequency Select Off board Application Maximum Current Consumption P1 ADI Port Interconnect Signals PA2 PB2 Interconnect Signals P3 Ethernet Port Interconnect Signals P4 PCMCIA Connector Interconnect Signals P5 Interconnect Signals P6 Interconnect Signals P7 Interconnect Signals PD1 Interconnect Signals PD2 Interconnect Signals Release 0 1 TABLE 5 10 TABLE 5 11 TABLE 5 12 MPCSXXFADS User s Manual LIST OF TABLES PD3 Interconnect Signals PDA Interconnect Signals MPC8XXFAD
204. lution state_diagram TxEn state TX_DISABLED if HOST_WRITE_ADI_DATA amp BndTmrExp fb amp PdaRst fb then TX_ENABLED else TX DISABLED state TX ENABLED if TxWordEnd PdaRst fb then TX DISABLED else TX ENABLED 130 Release 0 1 MPCSXXFADS User s Manual Support Information Transmit Length Counter This counter determines the length of transmission towards the MPC The fast clock is used here to allow 1 2 clock resolution with the negation of TxEn which enables DSCK outside equations TxWordLen ar Reset TxWordLen clk TxWordEnd TxWordLen fb TX WORD LENGTH when STATE TX ENABLED amp TxWordEnd amp PdaRst fb then TxWordLen d TxWordLen fb 1 else TxWordLen d 0 kK K Kk K k K K k K K K TxClkSns Transmit Clock Sense Since Host req is synced acc to ICIk and may be detected active when CIK2 is either 1 or 0 DSCK and the clock according to which DSDI is sent and DSDO is sampled should be changed When TxClkSns is 0 DSCK will be CIK2 while transmit will be done according to 2 and recieve by 2 When TxClkSns is 1 DSCK will be CIK2 while transmit will be done TR according to 2 and recieve by CIK2 k K K K equations TxClkSns clk TxClkSns ar Reset state diagram TxClkSns state
205. mputer is configured to be at I O memory addresses 100 102 hex but it may be reconfigured for an alternate address space CAUTION BEFORE REMOVING OR INSTALLING ANY EQUIPMENT IN THE IBM PC XT AT COMPUTER TURN THE POWER OFF AND REMOVE THE POWER CORD B 2 1 ADI Installation in IBM PC XT AT Refer to the appropriate Installation and Setup manual of the IBM PC XT AT computer for instructions on removing the computer cover The ADI board address block should be configured at a free address space in the computer The address must be unique and it must not fall within the address range of another card installed in the computer The ADI board address block can be configured to start at one of the three following addresses e 100 This address is unassigned in the IBM PC e 200 This address is usually used for the game port e 300 This address is defined as a prototype port The ADI board is factory configured for address decoding at 100 102 hex in the IBM PC XT AT address map These are undefined peripheral addresses 200 Release 0 1 MPCSXXFADS User s Manual Support Information FIGURE B 1 Physical Location of jumper JG1 and JG2 JG1 JG2 NOTE Jumper JG2 should be left unconnected The following figure shows the required jumper connection for each address configuration Address 0 hex is not recommended and its usage might cause problems FIGURE 2 JG1 Configuration Op
206. n PINS WATCH POINTS else if MPC WRITE BCSR 0 4 DBGC DATA BIT pin DEBUG PINS RESREVED amp PON RESET DBGC PON DEFAULT DEBUG PINS SHOW st KA PON RESET amp DBGC PON DEFAULT DEBUG PINS RESREVED then DEBUG PINS RESREVED else DEBUG PINS FOR SHOW I 8 9k 9k oR I kok state diagram DBPC state DEBUG PORT ON JTAG if WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT NON EXISTANT amp PON RESET DBPC PON DEFAULT DEBUG PORT ON KA PON RESET amp DBPC DEFAULT DEBUG PORT NON then PORT NON EXISTANT else if MPC WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT RESERVED amp PON RESET DBPC PON DEFAULT DEBUG PORT ON st KA PON RESET amp DBPC PON DEFAULT DEBUG PORT RESERVED then DEBUG PORT RESERVED else if MPC WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT DEBUG PINS amp PON RESET DBPC PON DEFAULT DEBUG PORT ON st PON RESET amp DBPC PON DEFAULT DEBUG PORT DEBUG PINS then DEBUG PORT ON DEBUG PINS else DEBUG PORT ON JTAG state DEBUG PORT NON EXISTANT if WRITE BCSR 0 amp DBPC DATA BIT pin DEBUG PORT ON JTAG amp PON RESET DBPC PON DEFAULT DEBUG PORT NON EXISTANT PON RESET amp DBPC PON DEFAULT DEBUG PORT
207. n connectors 3 2 21 SDRAM ON LD16 When the yellow SDRAM ON led is lit it indicates the SDRAM is enabled in BCSR1 Therefore any access made to CS4 will hit on the SDRAM When it is dark it indicates that either the SDRAM is disabled in BCSR1 enabling the use of CS4 off board via the expansion connectors 3 2 22 PCMCIA ON 1017 When the yellow PCMCIA ON led is lit it indicates the following 1 Address amp strobe buffers are driven towards the PCMCIA card 2 Data buffers are driven to from the PCMCIA card whenever or CE2A signals are asserted 3 Card status lines are driven towards the MPC from the PCMCIA card When it is dark it indicates that all the above buffers are tri stated and the pins associated with PCMCIA channel may be used off board via the expansion connectors 3 3 All accesses to MPC8XXFADS s memories are controlled by the MPC s memory controller Therefore the memory map is reprogrammable to the desire of the user After Hard Reset is performed by the debug station the debugger checks to see the size delay and type of the DRAM and FLASH SIMMs mounted on A Connected to CEIB for MPC823FADSDB B Connected to CE2B for MPC823FADSDB C Or B for MPC823FADSDB 24 Release 0 1 25 OPERATING INSTRUCTIONS MPCSXXFADS User s Manual board and initializes the chip selects accordingly The DRAM SDRAM and the FLASH memory respond to all types of memor
208. nate function 35 GND 89 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 9 PD2 Interconnect Signals Pin No Signal Name Attribute Description 36 SPKROUT LX KR IRQ4 SPKROUT Kill Reservation input or Interrupt Request 4 input or PCMCIA Speaker Output Configured on the FADS as SPKROUT May be configured to alternate function 37 GND 38 VFLS1 B1 IWP1 VFLS1 PCMCIA slot B Input 1 or Instruction Watchpoint 1 or Visible history Flushes Status 1 For the MPC823 or MPC850 daughter boards configured as B1 For all other daughter boards configured as VFLSO May be configured Indicates in conjunction with VFLS1 the number of instructions flushed from the core s history buffer Indicates also whether the MPC is in debug mode If not using the debug port may be configured for alternate function 39 GND 40 41 42 VF1 IP B5 LWP1 VF1 PCMCIA slot B Input Port 5 or Load Store Watch Point 1 or Visible Instruction Queue Flushes Status 1 For MPC823 or MPC850 configured as IP B5 for all other daughter boards configured as VF1 May be configured to any alternate function as no use is done with it on the FADS 43 GND 44 AT1 ALE B DSCK AT1 Address Latch Enable for PCMCIA slot B or Debug Serial Clock or Address Type 1 For MPC823 or MPC850 daughter boards configured as ALE B for all other daughter boards configure
209. nce 500 MQ at 100 VDC 3 X Socket 68 Pin PLCC AMP 822279 1 72 pin SIMM Socket AMP 822032 4 80 pin SIMM Socket AMP 822032 5 a Not Assembled b C6 is bypassed by 0 resistor 5 3 Programmable Logic Equations The MPC8XXFADS has 3 programmable logic devices on it Use is done with MACH220 10 by AMD These device support the following function on the FADS 1 U7 Debug Port Controller 2 010 auxiliary board control functions e g buffers control local interrupter reset logic etc 3 U11 the BCSR 112 Release 0 1 MPCSXXFADS User s Manual Support Information 5 3 1 02 Debug Port Controller k k MPC8XX FADS Debug Port Controller Mach controller for an interface between Sun ADI port at one side to debug port at the other H n this file 8 Added support for VFLS FRZ switching for both normal operation and external debug station connected to the FADS Support includes separating vfls between MPC and debug port Selection between frz vfls default is done by VflsFrz input pin Selection between on board off board vfls frz is done by ChinS coming from the expansion connectors VFLS 0 1 are driven towards the debug port connector when board is not selected i e either ADI is disconnected or addresses don t
210. nd This line is not connected in the FADS CTS O Clear To Send This line is always asserted by the FADS A Since there are only 3 RS232 transmitters in the device DSR is connected to CD 50 Release 0 1 MPCSXXFADS User s Manual Functional Description 4 10 PCMCIA Port To enhance PCMCIA i f development a dedicated PCMCIA port is provided on the FADS Support is given to 5V only PC Cards PCMCIA standard 2 1 compliant All the necessary control signals are generated by the MPC itself To protect MPC signals from external hazards and to provide sufficient drive capability a set of buffers and latches is provided over PC Card s address data amp strobe lines To conform with the design spirit of the FADS i e making as much as possible MPC resources available for external application development input buffers are provided for input control signals controlled by the EN bit in BCSR1 so the PCMCIA port may be Disabled Enabled at any time by writing 1 0 to that bit When the PCMCIA channel is disabled its associated pins are available for off board use via the expansion connectors A loudspeaker is provided on board and connected to SPKROUT line of the MPC The speaker is buffered from the MPC and low pass filtered When the EN bit in BCSR1 is negated high the speaker buffer is tri stated so the SPKROUT signal of the MPC may be used for alternate function Since it is not desirable to apply cont
211. nect Signals below TABLE 5 5 P5 Interconnect Signals Pin No Signal Name Attribute Description VFLSO O Visible history FLushes Status 0 Indicates in conjunction with VFLS1 the number of instructions flushed from the core s history buffer Indicates also whether the 15 in debug mode not using the debug port may be configured for alternate function When the FADS is disconnected from the ADI bundle it may be FRZ signal depended on 1 5 position SRESET Soft Reset of the Active low Open Drain GND Ground DSCK Debug Serial Clock Over the rising edge of which serial date is sampled by the MPC from DSDI signal Over the falling edge of which DSDI is driven towards the MPC and DSDO is driven by the MPC Configured on the MPC s JTAG port When the debug port controller is on the local MPC or when the FADS is a debug port controller for a target system OUTPUT when the FADI bundle is disconnected from the FADS INPUT GND Ground VFLS1 See VFLSO When the FADS is disconnected from the ADI bundle it may be FRZ signal depended on J1 s position HRESET Hard Reset of the Active low Open Drain DSDI Debug Serial Data In of the debug port Configured the MPC s JTAG port When the debug port controller is on the local MPC or when the FADS is a debug port controller for a target system OUT
212. ng edge DSCK DSCK terms are constant in that regard K K K K K equations RxReg0 clk RxReg0 ar Reset when STATE TX ENABLED amp STATE TX ON RISING amp STATE TX ENABLED amp STATE TX ON FALLING amp 2 amp DIAG LOOP BACK then RxReg0 d DSDO shift in ext data else when STATE TX ENABLED amp STATE TX ON RISING amp CIK2 STATE TX ENABLED amp STATE TX ON FALLING amp DIAG LOOP BACK then RxReg0 d TxReg7 fb shift in from transmit reg else RxReg0 d RxReg0 fb hold value K k K AdsReq Host from ads read acknowledge This state machine generates an automatic ADS read request from the host when either a byte of data is received in the Rx shift register or the status request bit in the control register is 133 Release 0 1 MPCSXXFADS User s Manual Support Information active during a previous host write to the control register When the host detectes AdsReq asserted it assertes HstAck in return HstAck double synchronized from the ADI port and delayed using the bundle delay compensation timer to negate AdsReq When the host detects AdsReq negated jt knows that data is valid to be read After the host reads the data it negates HstAck machine steps through these states 0 ADS REQ ACTIVE 1 ADS REQ ACTIVE 1 sk k gt F see ok
213. o CHK DESCRIP A B 6 D E F G H l J K tmp mnt net prince yair 8xx fads m brd pilot sc h 4 drw 07 MAY 97 16 53 lost update 07 MAY 97 16 52 DRMPWR gt BA 7 29 DRMA 0 10 IN ele 2 Ee 60n BA29 BA29 52 70 807 807 599 36 000 10 2 37 511 1 55 E 69 806 806 12 gt gt gt noo BD37 BA27 BA27 50 68 805 805 J96 1 001 vec 38 2 zz 002 13 DRMA2 14 6 8029 8426 40 BA26 _ 49113 003 67 804 804 14 194 2 0022 2558 T BA25 41 BA28 48 4 04 66 __803 803 15 492 16155 0035S 8027 4 7 BA24 42 BA24 47 5 pos 65 802 802 17 J90 BRMAB 43 54 0045 55 R69 BA23 BA23 46 64 BDI 801 J88 A5 005 44 006 19 DRMAG 18 24 8025 S4 7K BA22 BA22 45 63 BDO ade 86 006 46 7 007 20 DRMA7 28 26 BD24 R 3 BA21 48 BA21 441 4 J75 EAT 7 25 327 79 20 51 BA20 43 poa 628015 8015 22 471 008 BA19 53 BA19 42 10 poo 61 8014 8014 24 469 9 dol BUR BA18 55 411 44 0010 80 8013 8013 26 DQ9 22 974 17 58 BAI7 401 42 0011 59 8012 8012 427 1 To 001015 8010 16 59 BA16 5391 4 0012 58 __8011 8011 28 J84 122 D011 2 57
214. oding on page 62 6 Added functions description for MPC821 860 860SAR 860T Daughter board with 860 TABLE 4 23 page 65 7 Changed Mach equations for U11 Bug correction Irrelevant for 091 boards See 5 3 2 U11 Board Control amp Status Register on page 140 1 7 SPECIFICATIONS MPC8XXFADS specifications are given in TABLE 1 1 TABLE 1 1 MPC8XXFADS Specifications CHARACTERISTICS SPECIFICATIONS Power requirements no other boards attached 5Vdc 1 7 A typical A maximum 12Vdc 91A Microprocessor running upto 50 MHz Addressing Total address range 4 GigaBytes Flash Memory 2 MByte 32 bits wide expandable to 8 MBytes Dynamic RAM 4 MByte 32 bits wide EDO SIMM Support for up to 32 MByte EDO or FPM SIMM Synchronous DRAM 4 MBytes organized as 1 Meg X 32 bit Operating temperature 096 309C Storage temperature 25 C to 85 C Relative humidity 5 to 90 non condensing A The only implication of that bug is that 0001 0090 may not connect to MPC823FADSDB of revision PILOT 0091 and up may 9 Release 0 1 MPCSXXFADS User s Manual General Information TABLE 1 1 MPC8XXFADS Specifications CHARACTERISTICS SPECIFICATIONS Dimensions Length 9 173 233 mm Width 6 3 160 mm Thickness 0 063 1 6 mm 10 Release 0 1 MPCSXXFADS User s Manual General Inform
215. on See 4 1 6 3 Soft Reset Configuration on 37 4 12 3 5 DSCK Debug port Serial Clock During asynchronous clock mode the serial data is clocked into the MPC according to the DSCK clock The DSCK serves also a role during soft reset configuration See 4 1 6 3 Soft Reset Configuration page 37 4 12 3 6 DSDO Debug port Serial Data Out DSDO is clocked out by the MPC according to the debug port clock in parallel with the DSDI being clocked in The DSDO serves also as READY signal for the debug port controller to indicate that the debug port is ready to receive controller s command or data 4 13 Power There are 4 power buses with the MPC8XXs 1 VO 2 Internal Logic 3 Keep Alive 4 PLL and there are 3 power buses on the MPC8XXFADS 1 5V bus 2 3 3V bus 3 12V bus A Le DSDI must meat setup hold time to from rising edge of the DSCK B Le full duplex communication 72 Release 0 1 MPCSXXFADS User s Manual Functional Description FIGURE 4 1 MPC8XXFADS Power Scheme FADS Logic amp Peripherals Daughter Board Con PCMCIA Vcc Control PC Card Socket MOTHER BOARD VDDSYN VD MPC8XX DAUGHTER BOARD Expansion Con DL VDDH To support off board application development the power buses are connected to the expansion connec tors so that external logic may be powered directly f
216. ontroller For Target System This configuration resembles the previous but here the local MPC is removed from its socket while the FADS is connected via a 10 lead Flat Cable between P5 and a matching connector on a target system WARNNING When connecting the FADS to a target system via P5 and a 10 lead flat cable the MPC MUST be REMOVED from its SOCKET Otherwise PERMANENT DAMAGE might be inflicted to either the Local MPC or to the Tar get MPC With this mode of operation all on board modules are disabled and can not be accessed in anyway except for the debug port controller Also all indications except for 5V power 3 3V Power and RUN are dark ened debugger commands and debugging features are available in this mode including s w download breakpoints etc The target system may be reset or interrupted by the debug port or reset by the FADS s RESET switches It is the responsibility of the target system designer to provide Power On Reset and HARD Reset configurations while SOFT Reset configuration is provided by the debug port controller See also 4 12 1 MPC8XXFADS As Debug Port Controller For Target System page 68 A On Daughter Board 17 Release 0 1 18 MPCSXXFADS User s Manual Hardware Preparation and Installation FIGURE 2 5 Debug Port Controller For Target System Operation Scheme Target System 10 Wire
217. ormation TABLE 5 10 PD3 Interconnect Signals Pin No Signal Name Attribute Description 74 PA2 X MPC port A 2 Appears also at P8 but otherwise unused 75 PB17 X MPC port B 17 Appears also at P8 but otherwise unused 76 PB18 X port 18 Appears also at P8 but otherwise unused 77 E TENA H Ethernet port Transmit Enable Connected to the SCC s RTS signal When active transmit is enabled via the MC68160 EEST When the ethernet port is disabled via BCSR1 may be used off board for any alternate function 78 GND 79 N C 80 81 82 O L Ethernet Port Enable Connected to BCSR1 See TABLE 4 10 5 1 Description on page 57 83 N C 84 IRD EN O L Infra Red Enable Connected to BCSR1 See TABLE 4 10 BCSR1 Description on page 57 85 PA1 X port A 1 Appears also at P8 but otherwise unused 86 GND 87 88 N C 89 X MPC port A 0 Appears also at P8 but otherwise unused 90 GND 91 92 TMS X JTAG port Test Mode Select input Used to select test through the JTAG port Pulled up but otherwise not used on the FADS 93 PB16 VO X MPC PI O port B 16 Appears also at P8 but otherwise unused 94 TRST O L JTAG port Reset Pulled down with a zero ohm resistor so that the JTAG logic is constantly reset Otherwise unused on the FADS 95 PB15 X MPC PI O port
218. p PON RESET RS232 2 ENABLE PON DEFAULT RS232 2 KA PON RESET amp RS232 2 ENABLE PON DEFAULT RS232 2 then RS232 2 ENABLE else 185232 2 ENABLE IC state diagram PccVcc1 state CONT 0 if MPC WRITE BCSR 1 amp VCC 1 DATA PCC VCC CONT 0 amp PON RESET VCC 1 PON DEFAULT VCC CONT 0 KA PON RESET amp 1 PON DEFAULT VCC CONT 0 then IPCC CONT 0 else PCC VCC CONT 0 state CONT 0 if MPC WRITE BCSR 1 amp VCC 1 DATA BIT pin VCC CONT 0 amp PON RESET VCC 1 PON DEFAULT CONT 0 PON RESET amp 1 PON DEFAULT VCC CONT 0 then PCC VCC CONT 0 else VCC CONT 0 kok k state diagram SdramEn state SDRAM ENABLED if MPC WRITE BCSR 1 amp SDRAM ENABLE DATA BIT pin SDRAM ENABLED 4 PON RESET SDRAM ENABLE PON DEFAULT SDRAM ENABLED 172 Release 0 1 MPCSXXFADS User s Manual Support Information PON RESET amp SDRAM ENABLE PON DEFAULT SDRAM_ENABLED then ISDRAM ENABLED else SDRAM ENABLED state SDRAM ENABLED if WRITE BCSR 14 SDRAM ENABLE DATA BIT pin SDRAM ENABLED amp PON RESET SDRAM ENABLE PON DEFAULT
219. p FLASH ENABLE DATA BIT pin ENABLE amp PON RESET FLASH ENABLE PON DEFAULT FLASH ENABLB PON RESET amp FLASH ENABLE PON DEFAULT FLASH IFLASH ENABLE else FLASH CFG ENABLE state FLASH ENABLE if MPC WRITE BCSR 1 amp FLASH ENABLE DATA BIT pin FLASH ENABLE amp PON RESET FLASH ENABLE PON DEFAULT ENABLEB PON RESET amp FLASH ENABLE PON DEFAULT FLASH ENABLB then FLASH CFG ENABLE else IFLASH ENABLE 167 Release 0 1 MPCSXXFADS User s Manual Support Information eoe To avoid in advertant write to the Control Register Enable bit which might result in a need to re power the board protection logic is provided n order of writing the Control Register Enable this bit in the status register must be negated After any write to the control register this bit asserts again to protected mode kK kk K k KK k KK k equations CntRegEnProtect clk SYSCLK state diagram CntRegEnProtect state CNT REG EN if MPC WRITE BCSR 3 amp CNT EN PROTECT DATA BIT pin CNT REG EN amp PON RESET REG EN PROTECT PON DEFAULT REG EN PROTECT KA PON RESET amp REG EN PROTE
220. p Status register definitions ILLLLLLLLELLLLLLLLLLLLLLLLLLLLLLLLELELLLELLLELLLLLLLLLLLLLLLLLLLLLLLELLLLELELLELDLELLLLLILEL STATUS REQUEST 0 DEBUG_ENTRY 0 DIAG LOOP 0 IN DEBUG MODE 1 TX DONE 0 TX INTERRUPTED DONE OK FRZ SELECTED 0 IS STATUS REQUEST StatusRequest fb STATUS REQUEST DEBUG MODE ENTRY DebugEntry fb DEBUG ENTRY LOOP BACK DiagLoopBack fb DIAG LOOP BACK IS IN DEBUG MODE InDebugMode fb IN DEBUG MODE FRZ IS SELECTED VflsFrz FRZ SELECTED DSDI ENABLE Logic definitions DSDI ENABLED 1 DSDI DISABLED 0 STATE DSDI ENABLED DsdiEn fb DSDI ENABLED 123 Release 0 1 MPCSXXFADS User s Manual Support Information enable state machine o R _ DISABLED 0 STATE TX ENABLED TxEn fb TX ENABLED STATE TX DISABLED TxEn fb TX DISABLED TX WORD LENGTH 14 In 1 2 ICIk clocks K K KK K k K TxClkSns state machine k k k k k k k TX_ON_RISING 0 TX ON FALLING 1 STATE TX ON RISING TxClkSns fb TX ON RISING STATE TX ON FALLING TxClkSns fb TX ON FALLING ILL AdsReq machine definitions
221. pansion connectors 46 GND 83 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 8 PD1 Interconnect Signals Pin No Signal Name Attribute Description 47 SDRMCS L In fact MPC s chip select line 4 Used as chip select for the Synchronous Dram Pulled up When the SDRAM is disabled via BCSR may be used off board via the daughter board 48 GND 49 GPL3 L UPMA or UPMB general purpose line 3 Used as WR signal for the SDRAM 50 GND 51 GPL2 LL General Purpose Line 2 for UPMA or UPMB Used with the SDRAM as a CAS signal 52 GND 53 LL Write Enable 3 or PCMCIA WE Selects the LSB within word for the Flash Simm or qualifies Writes for the PC Card 54 GND 55 WE2 LL Write Enable 2 or PCMCIA OE Selects the offset 2 Byte within a word for the Flash Simm or open data buffers for read from PC Card 56 GND 57 WE1 LL GPCM Write Enable1 or PCMCIA I O Write Used to qualify write cycles to the Flash memory and as Write for the PCMCIA channel 58 GND 59 BS2A LL Byte Select 2 for UPMA Selects offset 2 bytes within Word Used for Dram access 60 GND 61 WEO LL GPCM Write Enable 0 or PCMCIA I O Read Used to qualify write cycles to the Flash memory and as Reads from PC Card 62 GND 63 SPARE1 10 L MPC spare line 1 Pulled up but otherwise unused on the FADS 64
222. perHalfEn LowerHalfEn PccDataBufEn PccEvenEn PccOddEn ModuleEn DramEn FlashEn PccEn ContRegEn SyncReset SyncHardReset DSyncHardReset RstCause Rst1 Rst0 Abr1 Abr0 RegPORIn Stp TA Modck Modck2 Modck1 ConfigHold ConfigHold2 ConfigHold1 ConfigHold0 F_PD4 F_PD3 F_PD2 PDIJ k K KK K k K K k K K K Dram Declarations DRAM ENABLE 0 DRAM ENABLED DramEn DRAM ENABLE ACTIVE SIMM36100 SD 0 SIMM36200 SD 3 SIMM36400 SD 2 SIMM36800 SD 1 IS HALF WORD HalfWord 0 Flash Declarations k k kk K k K FLASH ENABLE ACTIVE 0 188 Release 0 1 MPCSXXFADS User s Manual Support Information FLASH ENABLED FlashEn FLASH ENABLE ACTIVE 29020 F PD 8 MCM29040 PD 7 29080 F PD 6 SM732A1000A PD 5 SM732A2000 F PD 4 FLASH BANKI MCM29020 SM732A1000A 29040 amp A10 29080 amp A9 amp A10 5 732 2000 amp A9 FLASH BANK2 MCM29040 amp A10 29080 amp A9 amp A10 SM732A2000 amp A9 FLASH BANKS A9 amp A10 amp MCM29080 FLASH BANKA A9 amp A10 amp MCM29080 ILL Reset Declarations
223. port Data Output Used on the FADS as debug port serial data If the ADI bundle is not connected to the FADS may be used by an external debug JTAG port controllers 12 13 GND 14 AT2 B2 IOIS16 AT2 PCMCIA slot B Input Port 2 or PCMCIA 16 bit capability indication or Address Type 2 For MPC823 or MPC850 daughter boards configured as B2 IOIS16 For all other daughter boards configured as AT2 but may be configured to alternate function as no use is done with AT2 on the FADS 15 GND 16 VF2 IP BS IWP2 VF2 PCMCIA slot B Input 3 or Instruction Watch Point 2 or Visible Instruction Queue Flushes Status 2 For MPC823 or MPC850 daughter boards configured as IP B3 For all other daughter boards configured as VF2 but may be configured to alternate function as no use is done with VF2 on the FADS 17 GND 88 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 9 PD2 Interconnect Signals Pin No Signal Name Attribute Description 18 VFO IP B4 LWPO VFO PCMCIA slot B Input Port 4 or Data Watch Point O or Visible Instruction Queue Flushes Status 0 For MPC823 MPC850 daughter boards configured as B4 For all other daughter boards configured as but may be configured to alternate function as no use is done with VFO on the FADS
224. ption 47 N C 48 GND 49 50 PB27 X MPC port 27 Appears also at P8 but otherwise unused 51 PB28 1 0 X port B 28 Appears also at P8 but otherwise unused 52 GND 53 PC12 1 0 X MPC port C 12 Appears also at P8 but otherwise unused 54 PB26 VO X port C 26 Appears also at P8 but otherwise unused 55 GND 56 57 5 X port A 5 Appears also at P8 but otherwise unused 58 GND 59 60 4 X port A 4 Appears also at P8 but otherwise unused 61 E CLSN H Ethernet Port Collision indication signal Connected to the SCC s 5 signal When the ethernet port is disabled via BCSR1 may be used off board for any alternate function 62 E RENA H Ethernet Receive Enable Connected to the SCC s CD signal Active when there is network activity When the ethernet port is disabled via BCSR1 may be used off board for any alternate function 63 SPARE2 VO X MPC spare line 2 Pulled up but otherwise unused on the FADS 64 O L Applies only for MPC823 daughter board Video Encoder Enable Indication Generated by BCSR4 See TABLE 4 23 BCSR4 Description on page 65 65 GND 66 67 SYSCLK LX System Clock In fact the CLKOUT of the MPC 68 GND 69 70 71 X port A 3 Appears also at P8 but otherwise unused 72 GND 73 97 Release 0 1 MPCSXXFADS User s Manual Support Inf
225. r enable VideoExtClkEn PIN 38 istype reg buffer Enable external clock gen for video encoder VideoRst PIN 5 istype reg buffer Video Encoder reset ModemEn PIN 28 istype reg buffer modem tool enable for MPC823FADSDB Modem Audio 55 istype reg buffer Modem Audio functions select for modem tool with MPC823 d b Board Status Pins Read only k E removed to external buffers K K kk K K K K K K K K Board Status Registers Chip Selects NV oie fe fs fs fe kK k k k k k k K k k K Kk k Kk K Besr2Cs PIN 47 istype com Besr3Cs PIN 48 istype Auxiliary Pins K k KK k OR k K K K UR HHH HHHHH HHHH Hh HHHO FF HF SH HO H HHH HHHH S HO H HHH 4 HHHHH H HHH dg HH E H HHH HR HH HHH 143 Release 0 1 MPCSXXFADS User s Manual Support Information K k KK k KK k System Hard Reset Configuration K kk K Kk K K KK K K K K K K K K ERBNODE istype reg buffer External Arbitration IP NODE istype reg buffer Interrupt Prefix in MSR BDISNODE istype reg buffer Boot Disable RSV2NODE istype reg buffer reserved config bit 2 BPSO BPS1N
226. rd reset IN AdsSoftReset PIN 17 Host to ADS Soft reset IN HstEn PIN 3 Host connected to ADS HostVcc PIN 49 Host to ADS host is on IN D C PIN 51 Host to ADS select data or control access IN AdsSel0 PIN 22 AdsSell PIN 21 AdsSel2 PIN 9 Host to ADS card addr IN 7 AdsAddr1 PIN 6 AdsAddr2 PIN 5 ADS board address switch IN AdsSelect NODE ISTYPE buffer ADS selection indicator OUT K K K K MPC pins Including debug port kk k kK kk K k KK k KK k PdaHardReset PIN 40 Pda s hard reset input I O o d PdaSoftReset PIN 65 Pda s soft reset output I O o d VFLSO PIN 10 VFLS1 PIN 11 Debug Trap mode report IN Freeze PIN 24 Alternative debug mode report IN DSCK PIN 48 istype com Pda s debug port clock Out 115 Release 0 1 MPCSXXFADS User s Manual Support Information DSDI PIN 47 istype Pda s debug serial data in DSDO 4 debug serial data output In K K K K Dedicated Debug Port pins VflsPO PIN 38 istype VflsP1 PIN 37 istype com VflsFrz PIN 13 selectes between VFLS FRZ from k k Mach to ADI data bus PD7 PD6 PDS PD4 PD3 PD2 PD1 PDO PIN 66 60 67 59 58 57 56 55 ADI data bus I O
227. rd used as video data 0 121 LD8 X MPC821 s or MPC823 s PD15 LD8 or MPC860s PD15 L1TSYNCA Not used on the FADS Appears also at P8 On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector 122 123 GND 124 ETHLOOP Ethernet Transceiver Diagnostic Loop Back Control Generated BCSR4 See TABLE 4 23 BCSR4 Description on page 65 125 TPFLDL Twisted Pair Full Duplex Allows for full duplex operation over the Ethernet Twisted Pair channel See TABLE 4 23 BCSR4 Description on page 65 126 TPSQEL Twisted Pair Signal Quality Error Test Enable See TABLE 4 23 BCSRA Description on page 65 127 MDM AUD Applies only for MPC823 daughter board Selects between the Data Voice paths of the MPC821 Modem Tool See TABLE 4 23 BCSR4 Description on page 65 100 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 10 PD3 Interconnect Signals Pin No Signal Name Attribute Description 128 MODEMEN O L Applies only for MPC823 daughter board Enables the 821 Modem Tool as well as a multiplexer for data voice signals on the MPC823 daughter board See TABLE 4 23 BCSR4 Description on page 65 129 N C 130 GND 131 132 N C 133 134 135 136 137 138 139 140 VCC 101 Releas
228. removed from the local map may be used off board via the daughter board s expansion connectors 26 5V Bus 27 GPL5A X L UPMA general purpose line 5 Not used on the FADS 28 5V Bus 29 Bl MPC s Burst Inhibit input Pulled up but otherwise unused the FADS 30 N C Not Connected Reserved 31 CS7 32 GND x FADS Ground plane 33 CS5 MPC s Chip Select line 5 Unused on the FADS 34 GND 35 CE1A LL PC Card Enable 1 for PCMCIA slot A Enables the EVEN address bytes Used by on board PCMCIA port 36 GND 37 F CS In fact MPC s chip select line 0 Used as chip select for the Flash Simm Pulled up When the Flash is disabled via BCSR may be used off board via the daughter board s expansion connectors 38 GND 39 CS6 MPC s Chip Select line 6 Unused on the FADS 40 GND 41 CE2A LL PC Card Enable 2 for PCMCIA slot A Enables the ODD address bytes Used by on board PCMCIA port 42 GND 43 DRMCS2 L In fact MPC s chip select line 3 Used as chip select line for the 2 nd bank of the Dram Simm Pulled up When the Dram is disabled via BCSR or when a single bank Dram Simm is being used may be used off board via the daughter board s expansion connectors 44 GND 45 DRMCS1 L In fact MPC s chip select line 2 Used as chip select line for the 1 st bank of the Dram Simm Pulled up When the Dram is disabled via BCSR may be used off board via the daughter board s ex
229. rious memories registers on the FADS are as shown in TABLE 4 1 MPC8XXFADS Chip Selects Assignment below TABLE 4 1 MPC8XXFADS Chip Selects Assignment Chip Select Assignment CS0 Flash Memory CS1 BCSR CS2 DRAM Bank 1 CS3 DRAM Bank 22 CS4 SDRAM CS 5 7 Unused user available a If exists 4 6 DRAM The MPC8XXFADS is provided with 4 MBytes of 60nsec delay EDO Dram SIMM Support is given to any 5V powered FPM EDO Dram SIMM configured as 1M X32 upto 2 X 4M X 32 with 60 nsec or 70nsec delay All dram configurations are supported the Board Control Status Register BCSR i e DRAM size 4M to 32M and delay 60 70 nsec are read from BCSR2 and the associated registers including the A An address which covered in a Chip Select region B Except for SDRAM which is Unbuffered C To allow a configuration word stored in Flash memory become active D And off board See further E After the BCSR is removed from the local memory map there is no way to access it but to re apply power to the FADS F During read cycles 39 Release 0 1 MPCSXXFADS User s Manual Functional Description UPM are programmed accordingly Dram timing control is performed by UPMA of the MPC via CS2 and CS3 for a dual bank SIMM region s i e RAS and CAS signals generation during normal access as well as during refresh cycles and the nec essary address multiplexing are perfo
230. rmed using UPMA CS2 and CS3 signals are buffered from the DRAM and each is split to 2 to overcome the capacitive load over the Dram SIMM RAS lines The DRAM module may enabled disabled at any time by writing the DRAMEN bit in BCSR1 See TABLE 4 10 BCSR1 Description on page 57 4 6 1 DRAM 16 Bit Operation To enhance evaluation capabilities support is given to Dram with 16 bit and 32 bit data bus width That way users can tailor dram configuration to get best fit to their application requirements When the DRAM is in 16 bit mode half of it can not be used i e the memory portion that is connected to data lines D 16 31 To configure the DRAM for 16 bit data bus width operation the following steps should be taken 1 Setthe Dram Half Word bit in BCSR1 to Half Word See TABLE 4 10 BCSR1 Description on page 57 2 The Port Size bits of BR2 and of BR3 for a 2 bank DRAM simm should be set to 16 bits 3 AM bits in OR2 register should be set to 1 2 of the nominal single bank DRAM simm vol ume or to 1 4 of the nominal dual bank DRAM simm volume If a Dual Bank DRAM simm is being used 4 Base Address bits in register should be set to DRAM BASE 1 4 Nominal Volume that is if a contiguous block of DRAM is desired 5 AM bits of OR3 register should be set to 1 4 Nominal Volume If the above is executed out of running code than this code should not reside on the DRAM while exe cuting otherwise
231. rol signals to unpowered PC Card the strobe data signal buffers transceivers are tri stated and may be driven only when the PC Card is powered The block diagram of the PCMCIA port is shown in FIGURE 4 6 PCMCIA Port Configuration on page 52 As the MPC801 does not have a PCMCIA port this port is not operational with an MPC801 daughter board B This since the PC Card might have protection diodes on its inputs which will force down input signals regardless of their driven level 51 Release 0 1 52 MPCSXXFADS User s Manual Functional Description FIGURE 4 6 PCMCIA Port Configuration PCMCIA SOCKET PCCVCC PCCVPP PCMCIA POWER NTROL Power Logic From BCSR 2 LTC1315 or equiv D 8 15 gt Data A 15 8 From BCSR PCMCIA Data A 7 0 R W 1 A B cnm WE PGM OE IORD IOWR IORD IOWR RESET_A B MPC8XX POE A B On Daughter Board Transparent latch with OE Address A 25 0 ALE A B WAIT A B 01516 A B A B BVD 1 2 A B CD 1 2 _A B VS 1 2 _A B SPKROUT gt LPF lt Release 0 1 MPCSXXFADS User s Manual Functional Description 4 101 PCMCIA Power Control To support hot insertion the socket s power is controlled via a dedicated PCMCIA power controller the LTC1315 made
232. rom the board The maximum current allowed to be drawn from the board on each bus is shown in TABLE 4 26 Off board Application Maximum Current Con sumption below TABLE 4 26 Off board Application Maximum Current Consumption Power BUS Current 5V 2A 3 3V 2A 2V 0 5A 12V 100 mA To protect on board devices against supply spikes decoupling capacitors typically 0 1uF are provided between the devices power leads and GND located as close as possible to the power leads 73 Release 0 1 MPCSXXFADS User s Manual Functional Description 4 13 1 5V Bus Some of the FADS peripherals reside on the 5V bus Since the MPC is friendly it may operate with 5V levels on its lines with no damage The 5V bus is connected to an external power connector via a fuse 5A To protect against reverse voltage or over voltage being applied to the 5V inputs a set of high current diodes and zener diode is connected between the 5V bus GND When either over or reverse voltage is applied to the FADS the protection logic will blow the fuse while limiting the momentary effects on board 4 13 2 3 3V Bus The MPC itself as well as the SDRAM the address and data buffers are powered by the 3 bus which is produced from the 5V bus using a special low voltage drop linear voltage regulator made by Micrel the MIC29500 3 3BT which is capable of driving upto facilitating operation of external logic as well 4
233. ry See TABLE 4 10 BCSR1 Description on page 57 104 Release 0 1 MPC8XXFADS User s Manual Support Information TABLE 5 11 PD4 Interconnect Signals Pin No Signal Name Attribute Description 86 BCSREN O L BCSR Enable Enables the BCSR to the FADS memory map See TABLE 4 10 BCSR1 Description page 57 87 USBVCCO O X Applies only for MPC823DB USB Power Drives VCC on the USB bus when the MPC823 functions as USB host See TABLE 4 23 BCSR4 Description on page 65 88 PCCEN O L PC Card Enable Enables the PC Card to be accessed by the FADS 89 EXTOLIO X External Tool Identification 0 Connected to BCSR2 See 4 11 4 BCSR2 Board Control Status Register 2 on page 59 90 SGLAMP O L Signaling Lamp Used for misc s w signaling purpose See TABLE 4 23 BCSR4 Description page 65 91 EXTOLI2 X External Tool Identification 2 Connected to BCSR2 See 4 11 4 BCSR2 Board Control Status Register 2 on page 59 92 USBVCC1 O X Applies only for MPC823DB Reserved Signal for USB Power See TABLE 4 23 BCSR4 Description on page 65 93 DBREVO LX Daughter Board Revision Code Signal 0 The MSB of the D B revision Code See TABLE 4 13 BCSR2 Description on page 60 94 EXTOLI1 X External Tool Identification 1 Connected to BCSR2 See 4 11 4 BCSR2 Board Control Status Register 2 on page 59 95 DBREV2 LX Dau
234. sed on the FADS Appears also at P8 MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as FIELD signal for the video encoder 108 109 GND 110 LOE I O X MPC821 s or MPC823 s PD6 LCD AC LOE or MPC860s PD6 RTS4 Not used on the FADS Appears also at On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On the MPC823 daughter board used also as BLANK signal for the video encoder 111 VDORST Applies only for MPC823 daughter board Video Encoder Reset This signal resets on its trailing edge the ADV7176 video encoder See TABLE 4 23 BCSR4 Description on page 65 112 VDOEXTCK O H Applies only for MPC823 daughter board 113 LDO I O X MPC821 s or MPC823 s PD7 LDO MPC860s PD7 RTS3 Not used on the FADS Appears also at P8 On MPC823 or MPC821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as video data 7 114 LD1 MPC821 s or PD8 LD1 or MPC860s PD8 TXD4 Not used on the FADS Appears also at On MPC823 or 821 daughter boards appears also at a dedicated LCD connector On MPC823 daughter board used as video data 6 99 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 10 PD3 Interconnect Signals Pin No Signal Name Attribute Description 115 LD2
235. set configuration This signal is made redundant with the MPC8XX debug port controller since there is a hard reset command integrated within the debug port pro tocol However the local debug port controller uses this signal for compatibility with MPC5XX existing boards and s w 4 12 3 3 SRESET This is the Soft Reset bidirectional signal of the MPC8XX On the MPC5XX it is an output The debug port configuration is sampled and determined on the rising edge of SRESET for both processor families On the MPC8XX it is a bidirectional signal which may be driven externally to generate soft reset sequence This signal is in fact redundant regarding the MPC8XX debug port controller since there is a soft reset command integrated within the debug port protocol However the local debug port controller uses this signal for compatibility with MPC5XX existing boards and s w 4 12 3 4 050 Debug port Serial Data Via the DSDI signal the debug port controller sends its data to the MPC The DSDI serves also a role A If a target system needs to use VFLS 0 1 alternate function then FRZ line should be connected to both VFLS 0 1 pins on the debug port connector B In fact that configuration is divided into 2 parts the first is sampled 3 system clock cycles prior to the rising edge of SRESET and the second is sampled 8 clocks after that edge 71 Release 0 1 MPCSXXFADS User s Manual Functional Description during soft reset configurati
236. supply for operation Connect the 5V power supply to connector P6 as shown below FIGURE 2 7 P6 5V Power Connector V 109 GND 20 GND S mw 30 P6 is a 3 terminal block power connector with power plug The plug is designed to accept 14 to 22 AWG wires It is recommended to use 14 to 18 AWG wires To provide solid ground two terminals are supplied It is recommended to connect both Gnd wires to the common of the power supply while is connected with a single wire NOTE Since hardware applications may be connected to the MPC8XXFADS the Daughter Boards expansion connectors PX1 2 PX4 or FADS s P8 the additional power consumption should be taken into consideration when a power supply is connected to the MPC8XXFADS 2 4 5 12 Power Supply Connection The MPC8XXFADS requires 12 1 A max power supply for the PCMCIA channel Flash programming capability or for 12V programmable Flash SIMM The MPC8XXFADS can work properly without the 12 power supply if there is no need to program either a 12V programmable PCMCIA flash card or a 12V programmable Flash SIMM Connect the 12V power supply to connector P7 as shown below 19 Release 0 1 MPCSXXFADS User s Manual Hardware Preparation and Installation FIGURE 2 8 P7 12V Power Connector 121 w 10 20 P7 is a 2 terminal block power connector with power plug The plug
237. switch 4 is in the OFF position while the FADS is powered up the on board 4PMHz clock generator becomes the clock source while the PLL multiplication factor becomes 1 5 2 3 3 Power On Reset Source Selection As there are differences between MPC revisions regarding the functionality of the Power On Reset logic A Located on the Daughter Board B A 5MHz clock generator is packed as well 15 Release 0 1 MPCSXXFADS User s Manual Hardware Preparation and Installation it is therefore necessary to select different sources for Power ON reset generation The above selection is done on the Daughter Board and therefore documented in the specific Daughter Board user s manual 2 3 4 VDDL Source Selection This selection is done on the Daughter Board and therefore documented in the specific Daughter Board user s manual 235 Keep Alive Power Source Selection This selection is done on the Daughter Board and therefore documented in the specific Daughter Board user s manual 2 3 6 Debug Mode Indication Source Selection Jumper J1 selects between VFLS 0 1 signals and FRZ signal of the MPC as an indication for debug mode state Since with the MPC8XXs each of these signals has alternate function it may be necessary to switch between the two sources in favor of alternate function being used When a jumper is positioned between pins 1 and 2 of J1 VFLS 0 1 are selected towards the debug port controller When a jumper is
238. t MB328CTOOTBSN60 30B21114 refresh clock divided by 30 periodic timer enabled type 3 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MBMR MB811171622A 100 428021149 refresh clock divided by 42 periodic timer enabled type 0 address multiplexing scheme 1 cycle disable timer GPL4 enabled 1 loop read 1 loop write 4 beats refresh burst a BR3 is not initialized for MB321xx or MB324xx EDO DRAM SIMMs b Assuming 16 67MHz BRGCLK 32 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS TABLE 3 7 UPMA Initializations for 60nsec EDO DRAMs 0 20MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C Contents 0 8FFFCCO4 8FFFCCO4 8FEFCCOO 8FEFCCOO 80FFCC84 33FFCCO7 1 O8FFCCOO 08FFCCO8 39BFCC47 O9AFCC48 17 04 X 2 S3FFCC47 08FFCCO8 X O9AFCC48 FFFFCC86 X 3 X 08FFCC08 X O9AFCC48 05 X 4 X 08FFCC00 X 39BFCC47 X 5 X 3FFFCC47 X X X 6 X X X X X 7 X X X X X 8 X X X 9 X X X A X X X B X X X C X X D X X E X X F X X 33 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS TABLE 3 8 UPMB Initializations for MB811171622A 100 upto 32MHz
239. t MB324CTOOTBSN60 408211148 refresh clock divided by 402 600 periodic 608211149 timer C0B21114 enabled type 3 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MB328CTOOTBSN60 20B211142 refresh clock divided by 20 309 or 60 periodic 30 211149 timer 60B21114 enabled type 3 address multiplexing scheme 1 cycle disable timer GPL4 disabled for data sampling edge flexibility 1 loop read 1 loop write 4 beats refresh burst MBMR MB811171622A 100 D0802114 refresh clock divided by DO or 80 periodic timer 808021144 enabled type 0 address multiplexing scheme 1 cycle disable timer GPL4enabled 1 loop read 1 loop write 4 beats refresh burst a Assuming 16 67 MHz BRGCLK b Assuming 25MHz BRGCLK c For 5 0MHz BRGCLK d Assuming 32MHz BRGCLK 28 Release 0 1 TABLE 3 4 UPMA Initializations for 0 DRAMs 50MHz MPCSXXFADS User s Manual OPERATING INSTRUCTIONS Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C Contents 0 8FFFEC24 8FFFEC24 8FAFCC24 8FAFCC24 COFFCC84 7 1 OFFFECO4 4 OFAFCCOA 4 OOFFCC04 X 2 OCFFECOA 4 OCAFCCOO OCAFCCOO 07 4 X 3 00FFEC04
240. t Used to qualify FADS selection by the host When host is off the debug port controller is disabled 30 HOST ENABLE HOST Enable input signal from the host Active low Indicates that the host computer is connected to FADS Used in conjunction with HOST and ADS SEL 2 0 to qualify FADS selection by the host 31 33 GND Ground 34 PDO Bit of the ADI port data bus 35 PD2 Bit 2 of the ADI port data bus 36 PD4 Bit 4 of the ADI port data bus 37 PD6 Bit 6 of the ADI port data bus 5 1 2 PA2 PB2 15232 Ports Connectors The RS232 ports connectors and PB2 are 9 pin 90 female D Type Stacked connectors signals of which are presented in TABLE 5 2 PA2 PB2 Interconnect Signals below TABLE 5 2 PA2 PB2 Interconnect Signals Pin No Signal Name Description 1 CD Carrier Detect output from the MPC8XXFADS 2 TX Transmit Data output from the MPC8XXFADS 3 RX Receive Data input to the MPC8XXFADS 4 DTR Data Terminal Ready input to the MPC8XXFADS 5 GND Ground signal of the MPC8XXFADS 6 DSR Data Set Ready output from the MPC8XXFADS 7 RTS N C Request To Send This line is not connected in the MPC8XXFADS 8 CTS Clear To Send output from the MPC8XXFADS 9 Not connected 5 1 3 P3 Ethernet Port Connector The Ethernet connector on the MPC8XXFADS P3 is a Twisted Pair 10 Base T compatible connector Use is done with 909 8 pin RJ45 connector signals of which are describ
241. t prince yoir 8xx fads m brd pilot sch 2 drw 07 MAY 97 16 50 lost update 07 MAY 97 16 50 741 245 74LCX245 741 245 74LCX245 00 1 2 BDO 08 1881 1 2 808 016 18 4 44 2 8016 031 tela 4412 8031 01 17 213 801 09 17 a5 2 3 809 017 _17 82 Ao i __8017 D30 1742 2 5 02 1663 4314 802 010 1664 4 8010 018 1683 4314 8018 022 168 434 03 15 48 805 Di 1664 415 BD11 019 154 A4 5 8019 028 _ 1564 415 04 4 55 6 804 012 145 6 8012 022 14 5 A5 6 020 027 _14 86 ag S 05 asl 805 672243822227 8013 021 _13 86 Ag 7 8021 026 156 Z 2 06 12 87 4718 806 014 1267 5 8 8014 022 12187 7 8___8022 025 1217 5 8 07 11a 9 807 015 11 Agl9 8015 023 ipa Ag 9 8023 D24 ia H H DIR H 1 ze ze 19 1 024 020 044 UBUFEN I LBUFEN 5 A
242. te function 35 X port B 30 Appears also at P8 but otherwise unused 36 GND 37 PB29 X port 29 Appears also at P8 but otherwise unused 38 RSTXD1 LX RS232 Port 1 Transmit Data When RS232 port 1 is disabled via BCSR1 may be used for any alternate function Appears also at P8 39 RSRXD1 O X RS232 Port 1 Receive Data When RS232 port 1 is disabled via BCSR1 tri stated and may be used for any alternate function Appears also at P8 40 RSDTR1 O L RS232 port 1 DTR signal When RS232 port 1 is disabled via BCSR1 tri stated and may be used for any alternate function Appears also at P8 41 GND 42 RSTXD2 LX RS232 Port 2 Transmit Data When RS232 port 2 is disabled via BCSR 1 may be used for any alternate function Appears also at P8 43 RSRXD2 O X RS232 Port 2 Receive Data When RS232 port 2 is disabled via BCSR1 tri stated and may be used for any alternate function Appears also at P8 44 RSDTR2 O L RS232 port 2 DTR signal When RS232 port 2 is disabled via BCSR1 tri stated and may be used for any alternate function Appears also at P8 45 PC14 X port 14 Appears also at P8 but otherwise unused 46 GND 96 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 10 PD3 Interconnect Signals Pin No Signal Name Attribute Descri
243. tended to serve as tools identifier or as S W option selection On board s w may check these lines to detect The presence of various tools h w expansions at the expansion connectors or the state of a dedicated 4 switches dip switch which resides over the same lines or a combination of both Half of the available combinations is reserved while the other half is available to users applications For the external tools codes and their associated combinations see TABLE 4 17 EXTOOLI 0 3 Assignment on page 61 13 15 DBREVN 0 2 Daughter Board Revision Number 0 2 This field represents the revision code hard assigned to each daughter board This is a production revision which may be identical for different types of daughter boards See TABLE 4 18 MPC8XXFADS Daughter Boards Revision Encoding on page 62 for revisions encoding 13 31 Reserved Un implemented a Shaded areas are additions with respect to the MPC812 860ADS 60 TABLE 4 14 Flash Presence Detect 4 1 Encoding FLASH PD 4 1 FLASH TYPE SIZE 0 3 Reserved 4 SM732A2000 SM73228 8 Mbyte SIMM by SMART Modular Technologies 5 5 732 1000 SM73218 4 Mbyte SIMM by SMART Modular Technologies 6 29080 8 MByte SIMM by Motorola Release 0 1 61 MPCSXXFADS User s Manual Functional Description TABLE 4 14 Flash Presence Detect 4 1 Encoding FLASH PD 4 1 FLASH
244. ter boards connected to IP_B3 signal of the MPC 113 GND 114 BBVD2 O X Buffered PCMCIA slot A Battery Voltage Detect 2 In fact IP_A5 Used in conjunction with BBVD1 to determine the battery status of a PC Card In case of MPC823 or MPC850 daughter boards connected to IP B5 signal of the 115 GND 116 93 Release 0 1 MPCSXXFADS User s Manual Support Information TABLE 5 9 PD2 Interconnect Signals Pin No Signal Name Attribute Description 117 N C 118 DPO DPO IRQ3 Data line 0 or Interrupt Request 3 generate and receive parity data for D 0 7 bits connected to the DRAM SIMM not be configured as IRQ3 119 V3 3 120 DP2 DP2 IRQ5 Data line 2 or Interrupt Request 5 generate and receive parity data for D 16 23 bits connected to the DRAM SIMM May not be configured as IRQ5 121 V3 3 122 DP1 DP1 IRQ4 Data line1 or Interrupt Request 4 generate and receive parity data for D 8 15 bits connected to the DRAM SIMM May not be configured as IRQ4 123 V3 3 124 N C 125 V3 3 126 IRQ1 L Interrupt Request 1 Pulled up but otherwise not used on the FADS 127 V3 3 128 SPARE3 X MPC s spare line 3 Pulled up but otherwise unused on the FADS 129 V3 3 130 IRQ7 L Interrupt Request 7 The lowest priority interrupt request
245. terrupt disabled Alarm interrupt disabled Real time clock FREEZE Real time clock enabled PISCR 0082 No level for interrupt request Periodic interrupt disabled clear status interrupt disabled FREEZE periodic timer disabled 3 4 1 Memory Controller Registers Programming The memory controller on the MPC8XXFADS is initialized to 50 MHz operation l e registers program ming is based on 50 MHZ timing calculation except for refresh timer which is initialized to 16 67Mhz the lowest frequency at which the FADS may wake up Since the FADS may be made to wake up at 25MHz as well the initializations are not efficient since there are too many wait states inserted Therefore addi tional set of initialization is provided to support efficient 25MHz operation The reason for initializing the FADS for 50Mhz is to allow proper although not efficient FADS operation through all available FADS clock frequencies A The only parameter which is initialized to the start up frequency is the refresh rate which would have been inad equate if initialized to 50Mhz while board is running at a lower frequency Therefore for best bus bandwidth avail ability refresh rate should be adapted to the current system clock frequency 26 Release 0 1 MPCSXXFADS User s Manual OPERATING INSTRUCTIONS Warning Due to availability problems with few of the supported memory components the below initializations were not tested with
246. tions a D O O 0 100 200 300 To properly install the ADI board position its front bottom corner in the plastic card guide channel at the front of the IBM PC XT AT chassis Keeping the top of the ADI board level and any ribbon cables out of the way lower the board until its connectors are aligned with the computer expansion slot connectors Using evenly distributed pressure press the ADI board straight down until it seats in the expansion slot Secure the ADI board to the computer chassis using the bracket retaining screw Refer to the computer Installation and Setup manual for instructions on reinstalling the computer cover Be3 SUN 4 to MPC8XXFADS Interface The ADI board should be installed in one of the SBus expansion slots in the Sun 4 SPARCstation computer A single ADI can control up to eight MPC8XXFADS boards 201 Release 0 1 MPCSXXFADS User s Manual Support Information CAUTION BEFORE REMOVING OR INSTALLING ANY EQUIPMENT IN THE SUN 4 COMPUTER TURN THE POWER OFF AND REMOVE THE POWER CORD Be3e1 ADI Installation in the SUN 4 There are no jumper options on the ADI board for the Sun 4 computer The ADI board can be inserted into any available SBus expansion slot on the motherboard Refer to the appropriate Installation and Setup manual for the Sun 4 computer for instructions on removing the computer co
247. ttorn ey fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office All other prodi uct or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 1998 MPC860FADSUM D Rev 0 1 1 1998
248. uals ADI Board Specification A Either on or off board B Same Daughter Board C Not to be mistaken for the M683X X Family Ads 8 Release 0 1 MPCSXXFADS User s Manual General Information 1 5 Revision ENG to Revision PILOT Changes The only electrical change between the two revisions is a bug correction in BCSR This bug was irrelevant to ENG 0091 and up boards The rest are production associated changes which were meant to improve boards reliability and manufacturability such as changes in SMD pad sizes drill sizes and so on and are of no interest to any user 1 6 Changes to This Document from Previous Issue Draft 0 0 1 Daughter Board s for MPC821 MPC860 MPC860SAR MPC860T are identical 1 2 on page 8 2 Typo error in TABLE 3 1 MPC8XXADS Main Memory Map on page 25 was fixed BCSR oc cupies 32KByte space rather than 16KByte as implied from this table 3 Typo Error in TABLE 3 3 Memory Controller Initializations For 5OMhz on page 27 and in TA BLE 3 6 Memory Controller Initializations For 20Mhz on page 30 was fixed BRO is set 02800001 Flash base address is 0x2800000 rather than 0x2200000 4 Changed Daughter Board Codes MPC821 MPC860 860SAR 860T share the same code now 0x22 See TABLE 4 20 Daughter Boards ID Codes on page 63 5 Mother Board revsion codes are changed 0 is now reserved ENG amp PILOT share the same code 1 See TABLE 4 18 MPC8XXFADS Daughter Boards Revision Enc
249. ver and installing the board in an expansion slot FIGURE B 3 ADI board for SBus SBus Connector ADI Connector Following is a summary of the Instructions in the Sun manual 202 1 Turn off power to the system but keep the power cord plugged in Be sure to save all open files and then the following steps should shut down your system hostname bin su Password mypasswd usr etc halt wait for the following messages Syncing file systems done Halted Program Terminated Type b boot c continue command mode When these messages appear you can safely turn off the power to the system unit Open the system unit Be sure to attach a grounding strap to your wrist and to the metal casing of the power supply Follow the instructions supplied with your system to gain access to the SBus slots Remove the SBus slot filler panel for the desired slot from the inner surface of the back panel of the system unit Note that the ADI board is a slave only board and thus will function in any available SBus slot Slide the ADI board at an angle into the back panel of the system unit Make sure that the mounting plate on the ADI board hooks into the holes on the back panel of the system unit Release 0 1 203 MPCSXXFADS User s Manual Support Information Push the ADI board against the back panel and align the connector with its mate and gently press the corners of
250. y access i e user supervisory program data and DMA TABLE 3 1 MPC8XXADS Main Memory Map ADDESS RANGE Memory Type Device Type ae 00000000 003FFFFF DRAM SIMM MB321Bx 08 MB322Bx 08 MC324Cx 00 MB328Cx 00 32 00400000 007FFFFF 32 00800000 00FFFFFF 32 01000000 01FFFFFF 32 02000000 020FFFFF Empty Space 02100000 02107FFF BCSR 0 4 P 32 02100000 02107FE3 BCSRO 2100004 02107FE7 BCSR1 2100008 02107FEB BCSR2 210000C 02107FEF BCSR3 2100010 02107FF3 BCSR4 02108000 021FFFFF Empty Space 02200000 02207FFF MPC Internal 32 02208000 027FFFFF Empty Space 02800000 029FFFFF Flash SIMM 29 020 MCM29F040 MCM29F080 32 5 732 1000 SM732A2000 E 02C00000 O2FFFFFF 32 03000000 033FFFFF SDRAM 32 03400000 FFFFFFFF Empty Space a x B T b The device appears repeatedly in multiples of its size BCSRO appears at memory locations 2100000 2100020 2100040 while BCSR1 appears at 2100004 2100024 2100044 and so on c Only upper 16 bit 20 0215 are in fact used d Refer to the relevant MPC User s Manual for complete description of the MPC internal memory map 3 4 MPC Registers Programming The MPC provides the following functions on the MPC8XXFADS 1 DRAM Controller 2 SDRAM Controller 3 Chip Select generator Release 0 1 MPCSX
251. y be read or written at any time BCSR1 gets its defaults upon Power On reset Most of BCSR1 pins are available at the daughter board connectors and on the expansion connectors residing over the A Provided that BCSR is not disabled 55 Release 0 1 MPCSXXFADS User s Manual Functional Description daughter boards providing visibility towards daughter boards and external logic BCSR1 fields are de 56 Release 0 1 MPCSXXFADS User s Manual Functional Description scribed in TABLE 4 10 BCSR1 Description page 57 TABLE 4 10 BCSR1 Description BIT MNEMONIC Function PON DEF ATT FLASH EN Flash Enable When this bit is active low the Flash memory module is enabled on the local memory map When in active the Flash memory is removed from the local memory map and 50 to which the Flash memory is connected may be used off board via the expansion connectors R W DRAM_EN Dram Enable When this bit is active low the DRAM module is enabled on the local memory map When in active the DRAM is removed from the local memory map and CS2 and 53 2 to which the DRAM is connected may be used off board via the expansion connectors R W ETHEN Ethernet Port Enable When asserted low the EEST connected to SCC1 is enabled When negated high that EEST is in standby mode while all its system i f signals are tri stated R W IRDEN Infra Red Port Enable

MPC8XXFADS User`s Manual - Freescale Semiconductor

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