Correction for Incorrect Description Notice RL78/G12 Descriptions in
Contents
1. 5 5 V voltage Note This depends on the POR detection voltage For a falling voltage data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated STOP mode a Operation mode STOP instruction execution Standby release signal interrupt request E A Page 13 of 16 RENESAS TECHNICAL UPDATE TN RL A E 8 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Page 818 Old 29 7 Data Memor TOP Mode Low only Voltage Data Retention Characteristics Ta 40 to 105 C Vss 0 V Symbol Data retention supply VDDDR 144 5 5 voltage Note The value depends on the POR de ion voltage When the voltage drop data is retained before a POR reset is affected but data ng ined when a POR reset is affected STOP mode lt Operation mode Data retention mode gt Vpop STOP instruction execution N Standby release signal interrupt request c 2014 Renesas Electronics Corporation All rights reserved tENESAS Date Nov 26 2014 New 29 7 RAM Data Retention Characteristics Ta 40 to 105 C Vss 0 V Data retention supply VDDDR 144 5 5 V voltage Note This depends on the POR detection voltage For a falling voltage data in RAM are retained until the voltage reaches the level that triggers a PO2. PageS register HIOTRM Pade Vee ragana 11 5 7 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Pages 404 and 406 Pages 6 and 7 Figure 11 71 and Figure 11 73 11 6 3 SNOOZE mode function Page 429 11 6 3 SNOOZE mode function 5 Timing Chart of SNOOZE Mode Operation i 431 432 and pages 9 to 11 Figure 11 90 Figure 11 91 and Figure 11 93 19 2 Configuration of Power on reset Circuit Figure 19 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit Paga ees Page Ag and Voltage Detector 1 28 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Page 776 Page 13 29 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics page ole Page Ia CHAPTER 28 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 C PARLA Pageta CHAPTER 29 ELECTRICAL SPECIFICATIONS 0 G TA 40 to 105 C Ragas page ae Incorrect Bold with underline Correct Gray hatched Revision History RL78 G12 User s Manual Hardware Rev 2 00 Correction for Incorrect Description Notice Document Number TN RL A027A E May 12 2014 First edition issued No 1 to 8 in corrections TN RL A027B E Nov 26 2014 Second edition issued No 9 to 10 in corrections This notice c 2014 Renesas Electronics Corporation All rights reserved Page 2 of 16 sCENESAS RENESAS TECHNICAL UPDATE TN RL A E 1 1 4 Pin Configuration Top View 1 4 2 24 pin products and 1 4 3 30 pin products Pages
3. 9 and 10 Incorrect 24 pin plastic HWOFWN 4 4 mm 0 5 mm pitch Lo a uo x uoi BEO ne g RELEE 32 EOR aS 5 PERS et SS E E E 222222 fp aanraai amp 7OOO00 exposed die pad 1817 16 15 14 13 72 _P61 KR5 SDAA00 RxDO O Psa KR4 SCLAGNTXDO O PozikKRal scko1 scLo1j POWKR7 S001 sDa01 J POOKRE S101 P22 ANI2 P 1 ANI1 AVrerm C P20ANIQAVREFF C PAJAN SCK Schm 03 TOO0IO P4vaANi22 so01 spao1 To2 TOO2INTP1O P4Q KROTOOLO INDEX MARK FIs VINTPOS Waac Voo O PI2aKRAX EXCLEMTIOZVUINTP2 P125KR1 510m RESET PAZ VERE VITO SVINTP A C Note Provided only in the R5F102 products Remarks 1 For pin identification see 1 5 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 8 Format of Peripheral VO Redirection Register PIOR 3 itis recommended to connect an exposed die pad to Wss c 2014 Renesas Electronics Corporation All rights reserved 2tENESAS Date Nov 26 2014 Correct 24 pin plastic HWOFN 4 x 4 mm 0 5 mm pitch Q 2 ge TEM not 8 S z oOo Oak wy 5S 2058 SSE FEE avy Bee oe S 222242 Toran int t i OG l O O exposed die pad 18 17 16 P22 ANI2 O P2 ANIWAVRerm O P20 ANIQAVREF gt P42 ANIZUSCKO1 SCLO1 TIO3 TOO i 0 POZ KRa SCcKo1 ScLo1 P4 ANI2Z2 500
4. Shift hH Shift PF sO Feception 8 amp shift operation cp Reception amp hift shift operation EEE INTCSIOO Data reception Data reception TSF00 TSFOO Data reception lt 5 gt lt 6 gt lt gt SS00 lt 3 gt Wila sToo lt 1 gt STOO lt 1 gt f a Data reception lt 2 gt omitted omitted c 2014 Renesas Electronics Corporation All rights reserved Page 6 of 16 sENESAS RENESAS TECHNICAL UPDATE TN RL A IE Date Nov 26 2014 It is correction of CPU operation status Clock request signal internal signal INTCSI00 and TSF00 in this Figure Correct Figure 11 73 Timing Chart of SNOOZE Mode Operation continuous startup Type 1 DAPOO 0 CKP00 0 Incorrect Figure 11 73 Timing Chart of SNOOZE Mode Operation continuous startup Type 1 DAPOO 0 CKP0O0 0 CPU operation status Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode lt 4 gt eT eg CPU operation status Normal operation STOP mode lt 3 gt SS00 a O o so STOO a oH SEDO se es Swoo SWCO lt 10 fi el son sseco Lb ee Clock request signal FS henl ne SS a es Receive data 1 e SDROO eee ae 7 cewe cata innnan hnnan nnna ee SCKOO pin ne ee ee oc Po Ree Ee 100 pin or Shift Eee 5 Saas _ __ Shift Po R ception amp shi amp shift op ft operation Reception fion amp shift operation q regist
5. time when the external reset is released is shown below Release from the first external reset following release from the POR state 0 672 ms typ 0 832 ms max when the LVD is in use 0 399 ms typ 0 519 ms max when the LVD is off 4 Reset times in cases of release from an external reset other than the above are listed below Release from the reset state for external resets other than the above case 0 531 ms typ 0 675 ms max when the LVD is in use 0 259 ms typ 0 362 ms max when the LVD is off omitted Page 12 of 16 RENESAS TECHNICAL UPDATE TN RL A E 7 28 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Page 776 Old 28 7 Data Memor TOP Mode Low only Voltage Data Retention Characteristics Ta 40 to 85 C Vss 0 V Symbol Data retention supply VDDDR 1 46 5 5 voltage Note The value depends on the POR de ion voltage When the voltage drop data is retained before a POR reset is effected but data ng ined when a POR reset is affected STOP mode lt Operation mode Data retention mode gt Vpop STOP instruction execution N Standby release signal interrupt request c 2014 Renesas Electronics Corporation All rights reserved tENESAS Date Nov 26 2014 New 28 7 RAM Data Retention Characteristics Ta 40 to 85 C Vss 0 V Data retention supply VDDDR 1 46
6. 1 SDA01 TIO2 TOOZ INTP1 POVKRT7S5001 spam P4Q KROTOOLO 4 24 7 Poo KRe s101 INDEX MARK E FPLSTIN TRO Was Vion PIZzZ KRAXZ EXCLETIOZVIINTP2 PI2Z5 KRISSION PIZVKR3X ViITIOZINTP A O Note Provided only in the RSF 102 products Remarks 1 For pin identification see 1 5 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 8 Format of Peripheral I O Redirection Register PIOR 3 itis recommended to connect an exposed die pad to Wss Page 3 of 16 RENESAS TECHNICAL UPDATE TN RL A Incorrect e 30 pin plastic LSSOP 7 62 mm 300 0 65 mm pitch P20 ANIO AVrere O PO1 ANI16 TO00 RxD1 O POO ANI17 TO00 TxD1 O P120 ANI19 O P40 TOOLO O RESET P137 INTP0 O P122 X2 EXCLK P121 X1 0O REGC O Vss O Voo O P60 SCLA0 O P61 SDAA0 O P31 TI03 TOO3 INTP4 PCLBUZO O Note Provided only in the R5F102 products 1 2 3 4 S 6 7 8 9 O E O P21 ANI1AVrerm O P22 ANI2 P23 ANI3 O P147 ANI18 O P10 SCKOO SCLOO T107 TOO7 O P11 S100 RxD0 TOOLRxD SDA00 T106 TO06 P12 SO00 TxDO TOOLTxD TI05 TO0S5 O P13 TxD2 SO20 SDAA0 T104 TO04 O P14 RxD2 S120 SDA20 SCLAO T103 TO03 O P15 PCLBUZ1 SCK20 SCL20 T102 TO02 O P16 TI01 TOO1 INTP5 RxDO O P17 T102 TO02 TxDO O PS50 INTP1 S11 1 O P51 INTP2 SO11 SDA11 P30
7. CO 0 CPU operation status Normal operation STOP mode SNOOZE mode Sso1 lt 3 gt ST01 lt 1 gt el ee ee e SWCO lt 2 gt EOCO1 SSECO L Normal operation Date Nov 26 2014 Correct Figure 11 91 Timing Chart of SNOOZE Mode Operation EOC01 1 SSECO 0 CPU operation status Normal operation STOP mode Normal operation SS01 lt 3 gt ST01 lt 1 gt ee cet A SWCO lt 12 gt Clock request signal internal signal EOCO01 SSECO L Receive data 2 Clock request signal internal signal Receive data 2 SDRO1 1 Receive data 1 PAO PID s Receive data1 X P SP ST Receive data 2 p sp Shift register 01 TOY Stir ogerdfonX YX E a INTSRO g Do INTSREO L H Data reception lt 7 gt fo Data reception ee TSFO1 lt 5 gt lt 6 gt lt 8 gt omitted c 2014 Renesas Electronics Corporation All rights reserved tENESAS SDRO1 Ooo d Receive data 1 Receive data 1 X P SP ST Receive data 2 P SP RxDO pin Shift o register 01 PX Shift operation K_ XE Shifttoperation XX INTSRO Ld INTSREO L Pe lt 2 gt lt 8 gt omitted Page 10 of 16 RENESAS TECHNICAL UPDATE TN RL A IE It is correction of CPU operation status Clock request signal internal signal INTSRO and TSF01 in this Figure Incorrect Figure 11 93 Timing Chart of SNOOZE Mode Operation EOC01 1 SSECO 1 Error interrupt INTSREO generation is
8. Date Nov 26 2014 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPU MCU Document Category No TN RL A027B E Rev 2 00 Correction for Incorrect Description Notice Information Technical Notification Category Title RL78 G12 Descriptions in the Hardware User s Manual RL78 G12 User s Manual Hardware Rev 2 00 Changed Rev 2 00 All lots Pocument R01UHO0200EJ0200 Aug 2013 Applicable RL78 G12 Product R5F102xxx R5F103xxx Reference This document describes misstatements found in the RL78 G12 User s Manual Hardware Rev 2 00 RO1UHO200EJ0200 Corrections Applicable Item CHAPTER 28 ELECTRICAL SPECIFICATIONS 737 ere A D Ta 40 to 85 C 9 9 CHAPTER 29 ELECTRICAL SPECIFICATIONS oo 778 Content change G Ta 40 to 105 C Document Improvement The above corrections will be made for the next revision of the User s Manual Hardware c 2014 Renesas Electronics Corporation All rights reserved Page 1 of 16 stEN ESAS RENESAS TECHNICAL UPDATE TN RL Date Nov 26 2014 Corrections in the User s Manual Hardware Corrections and Applicable Items Pages in this document English RO1UH0200EJ0200 for corrections 1 4 Pin Configuration Top View 1 4 2 24 pin products Pages 9 and 10 Pages 3 and 4 1 4 3 30 pin products 5 3 9 High speed on chip oscillator trimming Page128
9. INTP3 SCK11 SCL11 Caution Connect the REGC pin to Vss via capacitor 0 47 to 1 uF Remarks 1 For pin identification see 1 5 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 8 Format of Peripheral I O Redirection Register PIOR c 2014 Renesas Electronics Corporation All rights reserved tENESAS Date Nov 26 2014 Correct e 30 pin plastic LSSOP 7 62 mm 300 0 65 mm pitch P20 ANIO AVrere O P01 ANI16 TOOO RxD1 O P00 ANI17 TI00 TxD1 O P120 ANI19 O P40 TOOLO O RESET P137 INTPO O P122 X2 EXCLK C P121 X1 O REGC O Vss O Voo O P60 SCLA0 O P61 SDAA0 O P31 T103 TOO3 INTP4 PCLBUZO O Note Provided only in the R5F102 products 1 2 3 4 5 6 T 8 9 O OO OO O O O P21 ANI1 AVrerm P22 ANI2 P23 ANI3 P147 ANI18 P10 SCK00 SCLOO T107 TOO7 P11 S100 RxD0 TOOLRxD SDA00 T106 TO06 P12 SO00 TxDO TOOLTxD TI05 TO05 P13 TxD2 SO020 SDAAO T104 TO04 P14 RxD2 S120 SDA20 SCLAO T103 TO03 P15 PCLBUZ1 SCK20 SCL20 T102 TO02 P16 T101 TOO1 INTP5 RxDO P17 T102 TO02 TxDO O P51 INTP2 SO118 Caution Connect the REGC pin to Vss via capacitor 0 47 to 1 uF Remarks 1 For pin identification see 1 5 Pin Identification P50 INTP1 SI11 SDA11 P30 INTP3 SCK11 SCL11 2 Functions in parentheses in the above
10. R reset but not once it reaches the level at which a POR reset is generated STOP mode a Operation mode STOP instruction execution Standby release signal interrupt request E A Page 14 of 16 RENESAS TECHNICAL UPDATE TN RL A027B E 9 CHAPTER 28 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 C omitted c 2014 Renesas Electronics Corporation All rights reserved CENESAS Date Nov 26 2014 New CHAPTER 28 ELECTRICAL SPECIFICATIONS TA 40 to 85 C This chapter describes the following electrical specifications Target products A Consumer applications Ta 40 to 85 C R5SF102xxAxx R5F103xxAxx D Industrial applications Ta 40 to 85 C R5F102xxDxx R5F103xxDxx G Industrial applications when Ta 40 to 105 C products is used in the range of Ta 40 to 85 C RSF 102xxGxx omitted Page 15 of 16 RENESAS TECHNICAL UPDATE TN RL A027B E 10 CHAPTER 29 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C Old CHAPTER 29 ELECTRICAL SPECIFICATIONS G TA 40 to 105 C This chapter describes the electrical specifications for the products G Industrial applications Ta 40 to 105 C omitted There are following differences between the products G Industrial applications Ta 40 to 105 C and the products A Consumer applications and D Industrial applications omitted Remark The electrical characteristics of the products G Industr
11. RM2 HIOTRM1 HIOTRMO HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO High speed on chip oscillator Minimum speed Minimum speed a a Note The value after reset is the value adjusted at shipment Remarks 1 The HIOTRM register holds a six bit value used to adjust the high speed on chip oscillator with an increment of 1 corresponding to an increase of frequency by about 0 05 2 For the usage example of the HIOTRM register see the application note for RL78 MCU series High speed On chip Oscillator HOCO Clock Frequency Correction RO1AN0464 Page 5 of 16 RENESAS TECHNICAL UPDATE TN RL A E Date Nov 26 2014 3 11 5 7 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Figure 11 71 and Fi 11 73 Pages 404 and 406 It is correction of CPU operation status INTCSI00 and TSF00 in this Figure Correct Incorrect h L Figure 11 71 Timing Chart of SNOOZE Mode Operation once startup Ae a cei a a a Type 1 DAP00 0 CKP00 0 YPE hs CPU operation status Normal peration Teran CPU operation status Normal operation STOP mo Normal operation lt 4 gt SS00 SE00 DE SWCO lt 2 gt lt 103 s 00 L Sere ee Oodkreques signal Clock request signal internal signal Receive data 2 SDROO Ff csi at oe E ee Receive data 1 a as ARa Pannan anann r M SCKOO pin S100 pin la Receive data 1 a _Receivedata2 sd S100 pin Receive data 1 __ __ Receive data 2
12. TSRO and TSF01 in this Figure Incorrect Figure 11 90 Timing Chart of SNOOZE Mode Operation EOC01 0 SSECO 0 1 CPU operation status Normal operation STOP mode SNOOZE mode lt 4 gt SS01 lt 3 gt lt 12 gt 1 gt O j ST01 E a ee SWCO lt 2 gt ee E L EOCO01 Normal operation SSECO L dereud C Cee internal signal gnal i Receive data 2 SDRO1 PP Received lt 9 gt A Read RxDO pin ____ Receive data1 P SP ST ___ Receive data2 _ P SP Sie IDo CTT TOO E YX ANN E iL INTSREO 1 TSF01 lt 5 gt lt 6 gt lt 8 gt omitted c 2014 Renesas Electronics Corporation All rights reserved tENESAS Date Nov 26 2014 Correct Figure 11 90 Timing Chart of SNOOZE Mode Operation EOC01 0 SSECO 0 1 CPU operation status Normal operation STOP mode lt 4 gt ji Normal operation SS01 lt 3 gt ST01 lt 1 gt SPN A SWCO EOCO1 L PP SSECO L SDRO1 ee Receive data 1 RxDO pin ae ST Receive data2 P SP Shift Clock request signal internal signal H9 gt A Read Nt Receive data 1 X P SP register 01 Oo A A Sogea XT XX Spero OO I lt 2 gt lt 8 gt omitted Page 9 of 16 RENESAS TECHNICAL UPDATE TN RL IE It is correction of CPU operation status Clock request signal internal signal INTSRO and TSF01 in this Figure Incorrect Figure 11 91 Timing Chart of SNOOZE Mode Operation EOC01 1 SSE
13. er 00 lt a SS register 00 CD ae INTCSIOO INTCSI00 ee ee Data reception Data reception TSFOO TSF00 lt 2 gt lt 7 gt lt 2 gt lt 5 gt lt 6 gt lt 7 gt lt 2 gt lt 5 gt lt 6 gt omitted omitted c 2014 Renesas Electronics Corporation All rights reserved Page 7 of 16 tENESAS RENESAS TECHNICAL UPDATE TN RL A E 4 11 6 3 SNOOZE mode function Page 429 Incorrect 11 6 3 SNOOZE mode function SNOOZE mode makes UART operate reception by RxDO pin input detection while the STOP mode Normally the UART stops communication in the STOP mode However using the SNOOZE mode enables the UART to perform reception operations without CPU operation Only UARTO can be set to the SNOOZE mode omitted Cautions 1 The SNOOZE mode can only be used when the high speed on chip oscillator clock fix is selected for fcuk omitted 4 If a parity error framing error or overrun error occurs while the SSECO bit is set to 1 the PEF01 FEF01 or OVF01 flag is not set and an error interrupt INTSREO is not generated Therefore when the setting of SSECO 1 is made clear the PEF01 FEF01 or OVF01 flag before setting the SWCO bit to 1 and read the value in bits 7 to 0 RxDO register of the SDR01 register c 2014 Renesas Electronics Corporation All rights reserved tENESAS Date Nov 26 2014 Correct 11 6 3 SNOOZE mode function SNOOZE mode makes UART operate reception by RxDO pin input detection whi
14. figure can be assigned via settings in the peripheral I O redirection register PIOR See Figure 4 8 Format of Peripheral I O Redirection Register PIOR Page 4 of 16 RENESAS TECHNICAL UPDATE TN RL A E register HIOTRM Page 2 5 3 9 High speed on chip oscillator trimmin 128 Incorrect 5 3 9 High speed on chip oscillator trimming register HIOTRM omitted Figure 5 10 Format of High Speed On Chip Oscillator Trimming Register HIOTRM Address FOOAQOH After reset undefined N R W Symbol HIOTRM Pica HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO High speed on chip oscillator Minimum speed Minimum speed a lile o poo J o olofin f poo o o 1 o o f a S E The value after reset is the value adjusted at shipment Note 1 Ihe HIOTRM register the high speed on chip illat lock ithin about 0 05 2 For the usage example of the HIOTRM register see the application note for RL78 MCU series High speed On chip Oscillator HOCO Clock Frequency Correction RO1AN0464 Remark c 2014 Renesas Electronics Corporation All rights reserved CENESAS Date Nov 26 2014 Correct 5 3 9 High speed on chip oscillator trimming register HIOTRM omitted Figure 5 10 Format of High Speed On Chip Oscillator Trimming Register HIOTRM Address FOOAOH After reset undefined R W Symbol HIOTRM res HIOTRM5 HIOTRM4 HIOTRM3 HIOT
15. ial applications Ta 40 to 105 C are different from those of the products A Consumer applications and D Industrial applications For details refer to 29 1 to 29 10 c 2014 Renesas Electronics Corporation All rights reserved CENESAS Date Nov 26 2014 New CHAPTER 29 ELECTRICAL SPECIFICATIONS G INDUSTRIAL APPLICATIONS TA 40 to 105 C This chapter describes the following electrical specifications Industrial applications Ta 40 to 105 C R5F102xxGxx Target products G omitted Remark When RL78 G14 is used in the range of Ta 40 to 85 C see CHAPTER 28 ELECTRICAL SPECIFICATIONS Ta 40 to 85 C omitted Operation of products rated G Industrial applications TA 40 to 105 C at ambient operating temperatures above 85 C differs from that of products rated A Consumer applications and D Industrial applications in the ways listed below omitted Remark The electrical characteristics of products rated G Industrial applications TA 40 to 105 C at ambient operating temperatures above 85 C differ from those of products rated A Consumer applications and D Industrial applications For details refer to 29 1 to 29 10 Page 16 of 16
16. le the STOP mode Normally the UART stops communication in the STOP mode However using the SNOOZE mode enables the UART to perform reception operations without CPU operation Only UARTO can be set to the SNOOZE mode omitted Cautions 1 The SNOOZE mode can only be used when the high speed on chip oscillator clock fix is selected for fcLk omitted 4 If a parity error framing error or overrun error occurs while the SSECO bit is set to 1 the PEF01 FEF01 or OVFO1 flag is not set and an error interrupt INTSREO is not generated Therefore when the setting of SSECO 1 is made clear the PEF01 FEF01 or OVF01 flag before setting the SWCO bit to 1 and read the value in bits 7 to 0 RxDO register of the SDR01 register 5 The CPU shifts from the STOP mode to the SNOOZE mode on detecting the valid edge of the RxDO signal Note however that transfer through the UART channel may not start and the CPU may remain in the SNOOZE mode if an input pulse on the RxDO pin is too short to be detected as a start bit In such cases data may not be received correctly and this may lead to a framing error or parity error in the next UART transfer Page 8 of 16 RENESAS TECHNICAL UPDATE TN RL A E 5 11 6 3 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Figure 11 90 Figure 11 91 and Figure 11 93 Pages 431 432 and 434 It is correction of CPU operation status Clock request signal internal signal IN
17. or 1 3 1 When the external reset input via RESET pin is used omitted Notes 3 ime until normal operation starts includes the following processing time whe e external reset is released after the first release of POR after the RESET signal_is driven high 1 as well as the voltage tabilizati it ti fter VPOR 1 51 V typ i hed Reset processing time when the external reset is released is shown below After the first release of POR 0 672 ms typ 0 832 ms max when the LVD is in use 0 399 ms typ 0 519 ms max when the LVD is off 4 Reset essing time when the external r fter th second release of POR is shown below After the second release of POR 0 531 ms typ 0 675 ms max when the LVD is in use 0 259 ms typ 0 362 ms max when the LVD is off omitted c 2014 Renesas Electronics Corporation All rights reserved CENESAS Date Nov 26 2014 Correct Figure 19 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 3 1 When the external reset input via RESET pin is used omitted The time until normal operation starts includes the following reset processing time when the external reset is released release from the first external reset following release from the POR state after the RESET signal is driven high 1 as well as the voltage stabilization wait time after VPOR 1 51 V typ is Notes 3 reached Reset processing
18. stopped Normal operation CPU operation status Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode A SS01 lt 3 gt stot lt i gt lt 10 gt so M o SWCO EOC01 SSECO internal signal gnal Receive data 2 SDR01 SS eS RxDO pin ___Receivedatai__ X P SP Shift register 01 iam INTSRO a A O TSF01 lt 2 gt lt 5 gt lt 6 gt lt gt lt 5 gt lt 6 gt Data reception lt gt lt 11 gt lt 8 gt omitted c 2014 Renesas Electronics Corporation All rights reserved tENESAS Date Nov 26 2014 Correct Figure 11 93 Timing Chart of SNOOZE Mode Operation EOC01 1 SSECO 1 Error interrupt INTSREO generation is stopped Normal operation STOP mode CPU operation status STOP mode SS01 ST01 SE01 SWCO EOC01 SSECO Clock request signal internal signal SDR01 e Receive data 1 A a D RxDO pin Receive data 1 X P SP Shift register 01 INTSRO INTSREO L reception D reception TSF01 La lt 2 gt lt 5 gt lt 7 gt lt 5 gt lt 7 gt lt 11 gt lt 8 gt omitted Page 11 of 16 RENESAS TECHNICAL UPDATE TN RL E 6 19 2 Configuration of Power on reset Circuit Figure 19 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 Page 639 Incorrect Figure 19 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detect
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