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SED1374 TECHNICAL MANUAL

1. E 1374 register names defin REG_REVISION_CODE 0x00 defin REG_MODE_REGISTER_0O 0x01 defin REG_MODE_REGISTER_1 0x02 defin REG_MODE_REGISTER_2 0x03 defin REG_HORZ_PANEL_SIZE 0x04 defin REG_VER PANEL_SIZE_LSB 0x05 defin REG_VER PANEL_SIZE_MSB 0x06 defin REG_FPLINE_START_POS 0x07 defin REG_HORZ_NONDISP_PERIOD 0x08 defin REG_FPFRAME_START_POS 0x09 defin REG_VERT_NONDISP_PERIOD Ox0A defin REG_MOD_RATE Ox0B defin REG_SCRN1_START_ADDR_LSB Ox0C defin REG_SCRN1_START_ADDR_MSB Ox0D defin REG_RESERVED_1 Ox0E defin REG_SCRN2_START_ADDR_LSB Ox0F defin REG_SCRN2_START_ADDR_MSB 0x10 define REG_RESERVED_2 0x11 defin REG PITCH_ADJUST 0x12 defin REG_SCRN1_VERT_SIZE_LSB 0x13 defin REG_SCRN1_VERT_SIZE_MSB 0x14 defin REG_LUT_ADDR 0x15 defin REG_LUT_BANK_SELECT 0x16 define REG_LUT_DATA 0x17 defin REG_GPIO_CONFIG 0x18 defin REG_GPIO_STATUS 0x19 defin REG_SCRATCHPAD Ox1A defin REG_PORTRAIT_MODE Ox1B defin REG LINE _ BYTE COUNT 0x1C define REG_NOT_PRESENT_1 Ox1D defin REG FRAMING Ox1E define REG_TEST_MODE 0x1F WARNING MAX_REG must be the last available register ER define MAX
2. le VDP sta VNDP gt FPFRAME MEM o M sn ss no DRDY MOD X X FPDAT 7 0 LINE1 X LINE2 X LINES X LINE4 XLINE479XLINE480 LINE1 X LINE2 X _ a FPLINE DRDY MOD P HDP si HNDP gt aia AAN A eee Ti FPDAT7 1 R1 X 1 83 Y 1 66 X Y X X18 FPDAT6 K161 X 1 R4 X 1 B6 X X X YX X1 B638 Y FPDATS 1 81 X 1 G4 X 1 R7 X X X1 R639 FPDAT4 1R2 X 1 B4X 1 G7X X X XO X X FPDAT3 o AR ASA 1 87 Y X a X1 B639 FPDAT2 MEE KERA X FPDAT1 N 1 R3 X 1 B5 X 1 G8 X X 1 G640 FPDATO X13 X 1 R6 X 1 B8 X X X 1 B640 X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 18 Single Color 8 Bit Panel Timing Format 2 VDP Vertical Display Period VNDP Vertical Non Display Period HDP Horizontal Display Period HNDP Horizontal Non Display Period Hardware Functional Specification Issue Date 99 04 29 REG 06h bits 1 0 REG O5h bits 7 0 1 Lines REG OAh bits 5 0 Lines REG 04h bits 6 0 1 x 8Ts REG 08h 4 x 8Ts SED1374 X26A A 001 02 Page 46 Epson Research and Development Vancouver Design Center e 1 Sync Timing ie Frame Pulse nt t3 Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 t7 gt Shift Pulse FPDAT 7 0 Figure 7 19 Single Color 8 Bit Pane
3. ef define MEM_OFFSET 0x01374B0B Location is platform dependent define REG_OFFSET MEM_OFFSET OxFFE0 Memory offset 64K 0x20 kj define MEM_SIZE 0xA000 40 kb display buffer XJ typedef unsigned char BYTE Some usefule typedefs typedef BYTE far LPBYTE typedef unsigned short WORD define LOBYTE w BYTE w define HIBYTE w BYTE WORD w gt gt 8 OxFF define SET_REG idx val LPBYTE REG_OFFSET idx val 3 7 void main void RO a a a E a E E A Programming Notes and Examples Issue Date 99 04 27 PBYTE pRegs LPBYTE REG_OFFSET PBYTE pMem LPBYTE MEM_OFFSET PBYTE pLUT nt LUTcount RGBcount nt x y tmp nt BitsPerPixel 4 nt Width 320 nt Height 240 nt OffsetBytes SED1374 X26A G 002 02 Page 66 Check the revision code if 0x18 pRegs return k k Initialize the chip Exit if we don t find an SI Epson Research and Development Vancouver Design Center ED1374 Each register is individually programmed to make comments clearer mi Register 01h Mode Register 0 Color 8 bit format 2 El SET_REG 0x01 0x23 Register 02h Mode Register 1 4BPP High Performance CLKi 2 SET_REG 0x02 OxBO Register 03h Mode Register 2 Normal power
4. ee 11 3 1 Bus Interface Modes 2 2 ee ee 11 3 2 Generic 1 Interface Mode 2 0 0 0 0 a eee 1 4 MCF5307 To SED1374 Interface 2 2 2 eee es 13 4 1 Hardware Description 0 0 000022 13 4 2 SED1374 Hardware Configuration 14 4 3 MCF5307 Chip Select Configuration 2 ee ee ee 1S SOFTWARE Be ae ase ane ea ae 16 Referentes fin cs is ea Sela E e A ig e eee Re ee Pet is eee 17 Hb Doctiments de o ie eB ae a we ts Se od eA A eee whe he AO 6 2 DocumentSources a a ie E a a e an e aa 17 7 Technical Support assa e Se ee a eS 18 7 1 EPSON LCD Controllers SED1374 2 2 a ee ee 18 7 2 Motorola MCF5307 Processor 2 1 ee ee ee ee 18 Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1374 Issue Date 99 01 05 X26A G 01 1 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 011 02 Issue Date 99 01 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 11 Table 4 1 Summary of Power On Reset Options e 14 Table 4 2 Host Bus Interface Selection 0 a 14 List of Figures Figure 2 1 MCF5307 Memory Read Cycle 002 000 00000000008 9
5. VDP VNDP i l l Jl l l l l l l l X eS X LINE X LINE2 X LINES X LINE4 X XLINE479XLINE480 A LINET XLINE2 X ea i HDP gt HNDP gt ESPA ME MESA a ee 1 R1X 1 G2 X 1 B3 X x X XO Xi B319 7 1 G1X 1 B2 X 1 R4 x X X_ YXi R320 ERAS OA 1 R2 X_1 G3X_1 B4 gt O X B820 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP VNDP HDP HNDP Vertical Display Period Vertical Non Display Period Horizontal Display Period Horizontal Non Display Period Figure 7 14 Single Color 4 Bit Panel Timing REG OAh bits 5 0 Lines REG 04h bits 6 0 1 x 8Ts REG 08h 4 x 8Ts Hardware Functional Specification Issue Date 99 04 29 REG 06h bits 1 0 REG 05h bits 7 0 1 Lines SED1374 X26A A 001 02 Page 42 Epson Research and Development Vancouver Design Center tl 2 Sync Timing gt Es Frame Pulse p t4 la 8 gt Line Pulse ES DRDY MOD Data Timing Line Pulse t6 t8 t9 t7 t14 t11 t10 lt gt gt Shift Pulse t12 t13 FPDAT 7 4 a x Figure 7 15 Single Color 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts 13 Line Puls
6. Philips Address Size GARD ACERO EARDRO EN 0800 0000h 64M byte Card 1 Attribute Card 1 IO 0C00 0000h 64M byte Card 2 Attribute Card 2 IO 6400 0000h 64M byte Card 1 Memory 6400 0000h 64M byte Card 2 Memory When the PR31500 PR31700 accesses the PC Card slots buffered through the ITE IT8368E bits CARDIIOEN and CARD2I0EN are ignored and the attribute IO space of the PR31500 PR31700 is divided into Attribute I O and SED1374 access Table 3 2 PR31500 PR31700 to PC Card Slots Address Remapping Using the IT8368E provides all details of the Attribute IO address reallocation by the IT8368E Table 3 2 PR31500 PR31700 to PC Card Slots Address Remapping Using the IT8368E IT8368E Uses PC Card Slot Philips Address Size Function 0800 0000h 16M byte Card 1 IO 4 0900 0000h 16M byte SED1374 aliased 256 times at 64K byte intervals 0A00 0000h 32M byte Card 1 Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 IO 2 0D00 0000h 16M byte SED1374 aliased 256 times at 64K byte intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory SED1374 X26A G 012 01 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 98 11 09 EPSON Research and Development Page 13 Vancouver Design Center 3 4 SED1374 Configuration The SED1374 is configured at power up by latching the state of the CNF 4 0 pins Pin BS also plays a role in host
7. Created 1998 Vancouver Design Centre Copyright c 1998 Epson Research and Development Inc All Rights Reserved k k ifndef _HAL_H_ define _HAL_H_ pragma warning disable 4001 Disable the single line comment warning include hal_regs h aes ia typedef unsigned char BYTE typedef unsigned short WORD typedef unsigned long DWORD typedef unsigned int UINT typedef int BOOL ifdef INTEL typedef BYTE far LPBYTE typedef WORD far LPWORD typedef UINT far LPUINT typedef DWORD far LPDWORD ls typedef BYTE LPBYTE typedef WORD LPWORD typedef UINT LPUINT typedef DWORD LPDWORD ndif ifndef LOBYTE define LOBYTE w BYTE w ndif ifndef HIBYTE define HIBYTE w BYTE UINT w gt gt 8 OXFF ndif ifndef LOWORD define LOWORD 1 WORD DWORD 1 ndif ifndef HIWORD define HIWORD 1 WORD DWORD 1 gt gt 16 amp OXFFFF ndif SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Page 73 Vancouver Design Center ifndef define endif ifndef define endif ifndef define endif ifndef define endif defi defi defi defi MA MA EWORD EWORD lo hi WORD WORD MA M
8. YX 1 8636 K X FPDAT5 a A 1 62 X 1 82 Y 187 X 1 R8 RIA X TGA X FPDAT4 1 R3 X 1 63 X_ 1 68 X_ 1 88 X 1 B13X RIE Y 1 R638 i FPDAT3 D 1 B3 X 1 R4 X _1 R9 X 1 G9 X1 G14X 1 B14 X 1 B6389_ FPDAT2 A 1 64 1 84 YX 1 89 Y FRIOY TRIS 1 G15 YX 1 G639 x X FPDAT1 o TRS 1 65 X 1 G10X 1 810 11 815 RIA Y TRE OOO x Y FPDATO on 1 85 X 1 R6 X 1 R11X 1 G11X1 G16X 1 B16 X 18640 Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 16 Single Color 8 Bit Panel Timing Format 1 VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 44 Epson Research and Development Vancouver Design Center Sync Timing P a Bis Frame Pulse t4 p t3 Line Pulse l Data Timing Line Pulse t6a tob t8 t9 t7a t14 t11 t10 gt 4 gt lt _ gt Shift Pulse 2 t7b Shift Pulse A J ge Shes E SS t12 t13 t12 t13 ld bd gt FPDAT 7 0 A A X Figure 7 17 Single Color 8 Bit Panel A C Timing Format 1 Symbol Para
9. 4 6 Red Bank Select REG 1 6h bits 5 4 Bank Select Logic Green Look Up Table 0 gt i 2 de e 4 6 Green Bank Select REG 16h bits 3 2 Bank Select Logic Blue Look Up Table 0 0 2 e 3 e 4 6 de Blue Bank Select REG 16h bits 1 0 Bank Select Logic aie 2 Color Data Format 7 6 5 4 3 2 1 0 AO A1 A2 A3 A4 A5 A6 A7 See Section 10 4 bit Red display data output 4 bit Green display data output 5 4 bit Blue display data output Figure 11 5 2 Level Color Look Up Table Architecture Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Page 76 4 Level Color Mode Epson Research and Development Vancouver Design Center 4 Color Data Format Red Bank Select REG 16h bits 5 4 Pa Green Look Up Table REG 16h bits 3 2 K Blue Look Up Table Bank 0 0 gt 1 3 Bank 1 o e gt gt Bank 4 bit Green display data output 3 Select Bank 2 Log
10. REG 15h Look Up Table Address Register Read Write n a n a RGB Index RGB Index LUT Address LUT Address LUT Address LUT Address bit 1 bit O Bit 3 Bit 2 Bit 1 Bit 0 SED1374 X26A G 002 02 RGB Index The RGB Index bits determine how the SED1374 will handle automatic LUT Address updates When the RGB Index is set to auto increment 00 then three consecutive accesses of REG 17h will read write the red green and then the blue elements at the Look Up Table index specified by the LUT Address After three accesses of REG 17h the LUT Address is incremented The next access of REG 17h will be the red element from the new Look Up Table address By altering the RGB Index the sequence can be changed such that three accesses of REG 17h will affect just the reds or just the greens or just the blues at three different LUT addresses When configured for monochrome panels the mechanism in which writes are handled is slightly different One to three reads are still required to update the LUT Address depending on the setting of the RGB Index bits If the RGB Index bits are set to auto increment then three writes to REG 17h are required to bump the LUT Address Only the last write will affect the display appearance it is copied across all three RGB elements If the RGB Index is set to access just red just green or just blue then a single write to REG 17h is copied to the red green and blue elements o
11. a aay S1 pe H UIPFOPIEZD uoTIeNTeAg Q T A Y Sng our Epson Research and Development Vancouver Design Center OT ONOW HOTOD A Figure 8 2 SED1374B0C Schematic Diagram 2 of 4 SED1374 X26A G 005 01 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 Vancouver Design Center Epson Research and Development Page 22 g L 9 S y y A Toyo REGA BO ASAOTDO E SITET ro Ayl ayoped Tva pue sng sI PIPOBTRANI SUT yoaeasay wsdgl Lasd lt y SZTSTUbL 2 vo rasau x usauaay 9 TSOWAN lt wie z o lt ITSIMAN 20 1 MOT ETA MOT MOT ras TTA antro ODA 919 tells aan8r aaa ODA s 3 N09 I s gt o an STWT 61 T OZWI 1ZWI 2 bal ZZWT 20 EZWI adAor 9 TSO
12. dde Generic 2 Description AB 15 1 A 15 1 Address 15 1 ABO AO Address AO DB 15 0 D 15 0 Data WE1 BHE Byte High Enable CS External Decode Chip Select BCLK BCLK Bus Clock BS n c Must be tied to lO Vpp RD WR n c Must be tied to IO Vpp RD RD Read WEO WE Write WAIT WAIT RESET RESET For details on configuration refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx Interfacing to an 8 bit Processor Issue Date 99 05 04 SED1374 X26A G 013 01 Page 10 Epson Research and Development Vancouver Design Center 3 2 Generic 2 Interface Mode SED1374 X26A G 013 01 Generic 2 Host Bus Interface is a general non processor specific interface mode on the SED 1374 that is ideally suited to interface to an 8 bit processor bus The interface requires the following signals e BUSCLK is a clock input which synchronizes transfers between the host CPU and the SED1374 It is separate from the input clock CLKI and is typically driven by the host CPU system clock If the host CPU bus does not provide this clock an asynchronous clock can be provided e The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low or
13. e System design using one ITE IT8368E PC Card GPIO buffer chip see Section 3 System Design Using the ITE ITS368E PC Card Buffer on page 10 Interfacing to the Toshiba MIPS TX3912 Processor SED1374 Issue Date 98 11 09 X26A G 004 01 Page 8 EPSON Research and Development Vancouver Design Center 2 Direct Connection to the Toshiba TX3912 2 1 General Description In this example implementation the SED 1374 occupies the TX3912 PC Card slot 1 The SED 1374 is easily interfaced to the TX3912 with minimal additional logic The address bus of the TX3912 PC Card interface is multiplexed and can be demultiplexed using an advanced CMOS latch e g 74 ACT373 The direct connection approach makes use of the SED 1374 in its Generic Interface 2 configuration The following diagram demonstrates a typical implementation of the interface SED1374 X26A G 004 01 SED1374 3 3V Tx3912 O AP ie gt RD ME gt WE CARD1CSL CARD1CSH gt BHE IO Vopt____ Bs 10 Voor____ RD WR ENDIAN System RESET RESET Latch ay ALE La gt CS ae AB 15 13 AB 12 0 D 31 24 e gt DB 7 0 D 23 16 e gt DB 15 8 Vop pull up CARD1WAIT te 4 Ma DCLKOUT See text a L p Glock divider gt Ore Oscillator H BCLK Figure 2 1 SED1374 to TX3912 Direct Connection The G
14. 02 aa e a AE ee 34 LCD Panel Power On Reset Timing 0 0000000002 eee 35 Power Down Up Timing ooe cooo c ee 36 Single Monochrome 4 Bit Panel TiMin8 o o a 37 Single Monochrome 4 Bit Panel A C Timing 04 4 38 Single Monochrome 8 Bit Panel TiMin8 o o e e 39 Single Monochrome 8 Bit Panel A C TiMiN8 o 40 Single Color 4 Bit Panel TiMing e 41 Single Color 4 Bit Panel A C Timing e e 42 Single Color 8 Bit Panel Timing Format l o 43 Single Color 8 Bit Panel A C Timing Formatl o ooo 44 Single Color 8 Bit Panel Timing Format 2 o o e 45 Single Color 8 Bit Panel A C Timing Format2 o o 46 Dual Monochrome 8 Bit Panel Timing e 47 Dual Monochrome 8 Bit Panel A C TiMid8 o 48 Dual Color 8 Bit Panel TiMidg8 a 49 Dual Color 8 Bit Panel A C TiMing8 a 50 12 Bit TFT MD TFD Panel Timing e 51 TPIYMD TFD A C Timing i into a d e 52 Screen Register Relationship Split Screen o o o 64 1 2 4 8 Bit Per Pixel Display Data Memory Organization 71 2 Level Gray Shade Mode Look Up Table Architecture o 72 4 Level Gray Shade Mode Look Up Table Architecture 73 Spec
15. 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1374 X26A G 012 01 Page 16 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 01 Issue Date 98 11 09 EPSON SED1374 75 Embedded Memory Color LCD Controller SDU1374 75 TMPR3912 22U CPU Module Document Number X00A G 004 01 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your ownuse in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SDU1374 75 TMPR3912 22U CPU Module X00A G 004 01 Issue Date 98 12 23 EPSON Research and Development Vancouver Design Ce
16. 3 2 IT8368E Configuration The IT8368E provides eleven multi function IO pins MFIO The IT8368E must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the SED1374 host bus interface and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the SED1374 When accessing the SED1374 the associated card side signals are disabled in order to avoid any conflicts For mapping details refer to section 3 3 Memory Mapping and Aliasing For connection details see Figure 3 1 SED1374 to PR31500 PR31700 Connection Using an IT8368E on page 10 For further information on the IT8368E refer to the JT8368E PC Card GPIO Buffer Chip Specification Note When a second IT8368E is used that circuit should not be set in VGA mode Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1374 Issue Date 98 11 09 X26A G 012 01 Page 12 3 3 Memory Mapping and Aliasing EPSON Research and Development Vancouver Design Center When the PR31500 PR31700 accesses the PC Card slots without the ITE IT8368E its system memory is mapped as in Table 3 1 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping Note Bits CARDIIOEN and CARD2IOEN need to be set in PR31500 PR31700 Memory Configuration Register 3 Table 3 1 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping
17. See pin has multiple functions For SH 3 SH 4 mode this pin inputs the bus start signal BS For MC68K 1 this pin inputs the address strobe AS For MC68K 2 this pin inputs the address strobe AS For Generic 1 this pin must be tied to Vss For Generic 2 this pin must be tied to lO Vpp Host Bus Interface Pin Mapping for summary RD WR l 79 CS Input This See pin has multiple functions For SH 3 SH 4 mode this pin inputs the RD WR signal The SED1374 needs this signal for early decode of the bus cycle For MC68K 1 this pin inputs the R W signal For MC68K 2 this pin inputs the R W signal For Generic 1 this pin inputs the read command for the upper data byte RD1 For Generic 2 this pin must be tied to IO Vpp Host Bus Interface Pin Mapping for summary Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Page 20 Epson Research and Development Vancouver Design Center Pin Names Type Pin Cell RESET State Description RD 76 CS Input This pin has multiple functions e For SH 3 SH 4 mode this pin inputs the read signal RD e For MC68K 1 this pin must be tied to IO Vpp e For MC68K 2 this pin inputs the bus size bit 1 SIZ1 e For Generic 1 this pin inputs the read command for the lower data byte RDO For Generic 2 this pin inputs the read comm
18. fl l fl DRDY MOD X nt X FPDAT 7 0 LINE 1 241 X Line 2 242 LINE 3 243 LINE 4 244 E LINE 239 479XLINE 240 480 K LINE 1 241 LINE 2 242 r FPLINE l DRDY MOD X l HDP jia HNDP Y id m m ig an oa eta OT FPDAT7 o 11 X15 A Y X 1 637 X FPDAT6 gt Kk 12 X 16 X o Y X 1 638 X FPDATS en 13X17 X X X X X Ke A X FPDAT4 2 v4 ra X X X X X Xw KX FPDAT3 o 241 1 241 5 X Y X 241 63 k y FPDAT2 241 2 X 241 6 X SS X X 241 638 X FPDAT1 241 3 241 7 ts Y X 241 639 X FPDATO _ 241 4 241 8 X k Y X 241 640 X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 20 Dual Monochrome 8 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG 0Ah bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 48 Epson Research and Development Vancouver Design Center Sync Timing i gt Big Frame Pulse nl 13 5 Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 t8 t9 4 ud gt Shift Pulse FPDAT 7 0 Figure 7 21 Dual Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti Frame Pulse setup to
19. 2 ee eee ee US 53 ITB TES3 08 Bae o a bogie E Bate BOR en Be a EBay he do wee ee NO Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1374 Issue Date 98 11 09 X26A G 012 01 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 01 Issue Date 98 11 09 Issue Date 98 11 09 EPSON Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 SED1374 Configuration for Direct Connection a 9 Table 2 2 SED1374 Generic 2 Interface Pin Mapping oaa 9 Table 3 1 PR31500 PR31700 to Unbuffered PC Card Slots System Address Mapping 12 Table 3 2 PR31500 PR31700 to PC Card Slots Address Remapping Using the IT8368E 12 Table 3 3 SED1374 Configuration Using the IT8368E o 13 Table 3 4 SED1374 Generic 1 Interface Pin Mappidg e 13 List of Figures Figure 2 1 SED1374 to PR31500 PR31700 Direct Connection o 8 Figure 3 1 SED1374 to PR31500 PR31700 Connection Using anIT8368E 10 Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1374 X26A G 012 01 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 01 Issue Date 98 11 09 EPSON Resear
20. 2 Interfacing to the MCF5307 2 1 The MCF5307 System Bus 2 1 1 Overview The MCF5200 5300 family of processors feature a high speed synchronous system bus typical of modern microprocessors This section is an overview of the operation of the CPU bus to establish interface requirements The MCF5307 microprocessor family uses a synchronous address and data bus very similar in architecture to the MC68040 and MPC8xx All outputs and inputs are timed with respect to a square wave reference clock called BCLKO Master Clock This clock runs at a software selectable divisor rate from the machine cycle speed of the CPU core typically 20 to 33 MHz Both the address and the data bus are 32 bits in width All IO accesses are memory mapped there is no separate IO space in the Coldfire architecture The bus can support two types of cycles normal and burst Burst memory cycles are used to fill on chip cache memories and for certain on chip DMA operations Normal cycles are used for all other data transfers 2 1 2 Normal Non Burst Bus Transactions SED1374 X26A G 011 02 A data transfer is initiated by the bus master by placing the memory address on address lines A31 through AO and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e SIZ 1 0 Transfer Size which indicate whether the bus cycle is 8 16 or 32 bits in width e R W which is high for read cycles and low for
21. Figure 2 2 MCF5307 Memory Write Cycle 2 o o e e o 9 Figure 4 1 Typical Implementation of MCF5307 to SED1374 Interface 13 Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1374 Issue Date 99 01 05 X26A G 011 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 011 02 Issue Date 99 01 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to provide an interface between the SED1374 Embedded Memory LCD Controller and the Motorola MCF5307 Processor The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1374 Issue Date 99 01 05 X26A G 011 02 Page 8 Epson Research and Development Vancouver Design Center
22. Maximum operating clock CLK frequency of 25MHz Operating clock CLK is derived from CLKI input CLK CLKI or CLK CLKI 2 Pixel Clock PCLK and Memory Clock MCLK are derived from CLK 2 6 Miscellaneous 2 7 Package Hardware Software Video Invert Software Power Save mode Hardware Power Save mode LCD power down sequencing 5 General Purpose Input Output pins are available e GPIOO is available if Hardware Power Save is not required e GPIO 4 1 are available if upper LCD data pins FPDAT 11 8 are not required for TFT MD TED support or Hardware Video Invert IO Operates from 3 0 volts to 5 5 volts Core operates from 3 0 volts to 3 6 volts 80 pin QFP14 package Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 12 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Oscillator z SH 4 3 BUS CSnkt p csi A 15 0 gt AB 15 0 D 15 0 gt DB 15 0 a Sa FPSHIFT veg pleis FPSHIFT Ja ed SED1374 FPFRAME FPFRAME Sa RD WR P RD WR UNO ae LCD RD P RDF DRY MOR Display WEO gt Weo RDY WAIT LCDPWR CkIO gt BCLK RESETA P RESET Figure 3 1 Typical System Diagram SH 4 Bus Oscillator z x SH 3 O BUS CSnkt p csi A 15 0 gt AB 15 0 D 15 0 gt DB 15 0
23. PCIk 2 MCIk PClk 8 bit per pixel MClk PClk High Performance 1 bit per pixel 0 2 bit per pixel i 4 bit per pixel x oj o 1 X When this bit 1 MCLK is fixed to the same frequency as PCLK for all bit per pixel modes This provides a faster screen update performance in 1 2 4 bit per pixel modes but also increases power consumption This bit can be set to 1 just before a major screen update then set back to 0 to save power after the update This bit has no effect in Swivel View mode Refer to REG 1Bh Swivel View Mode Register on page 68 for Swivel View mode clock selection Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Epson Research and Development Page 57 Vancouver Design Center bit 4 Input Clock Divide When this bit 0 the operating clock CLK is same as the input clock CLKI When this bit 1 CLK CLKI 2 In landscape mode PCLK CLK and MCLK is selected as per Table 8 3 High Perfor mance Selection In Swivel View mode MCLK and PCLK are derived from CLK as shown in Table 8 9 Selection of PCLK and MCLK in SwivelView Mode on page 69 bit 3 Display Blank This bit blanks the display image When this bit 1 the display is blanked FPDAT lines to the panel are driven low When this bit 0 the display is enabled bit 2 Frame Repeat EL support This feature is used to improve Frame Rate Modulation of EL pan
24. SETA 1 the SED1374 generates an external transfer acknowledge using the WAIT line TRLX 0 normal timing EHTR 0 normal timing Interfacing to the Motorola MPC821 Microprocessor SED1374 Issue Date 99 01 05 X26A G 010 02 Page 20 4 5 Test Software BR4 OR4 MemStart address RevCodeReg ter Start registers enable bits clock mem space Loop end SED1374 X26A G 010 02 Epson Research and Development Vancouver Design Center The test software to exercise this interface is very simple It configures chip select 4 on the MPC821 to map the SED1374 to an unused 64k byte block of address space and loads the appropriate values into the option register for CS4 At that point the software runs in a tight loop reading the 1374 Revision Code Register REG 00h which allows monitoring of the bus timing on a logic analyzer The source code for this test routine is as follows equ equ equ equ mfspr andis andis oris ori stw andis oris ori stw andis oris lbz 120 124 40 FFEO r1 IMMR rl r1 Sffff EDO 0 r2 r2 MemStart r2 r2 0801 r2 BR4 11 EA ord 0 62 02 SFECO r2 r2 0708 r2 OR4 r1 El 60 70 r1 r1 MemStart r0 RevCodeReg r1 Loop CS4 base register CS4 option register upper word of SED1374 start address of Revision Code Regis get base address of internal clear lower 16 bits to 0 clear r2 write b
25. Table 4 1 Summary of Power On Reset Options SED1374 value on this pin at the rising edge of RESET is used to configure 1 0 Pin Name 0 1 CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Little Endian CNF4 Active low LCDPWR signal Active high LCDPWR signal configuration for MC68328 support Table 4 2 Host Bus Interface Selection CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 X SH 4 interface 0 0 1 X SH 3 interface 0 1 0 X reserved 0 1 MC68K 1 1 0 0 X reserved 1 0 1 X MC68K 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 Generic 2 16 bit configuration for MC68328 using Generic 1 host bus interface configuration for MC68328 using MC68K 1 host bus interface 4 3 MC68328 Chip Select Configuration SED1374 X26A G 007 02 The SED1374 requires a 64K byte address space for the display buffer and its internal registers To accommodate this block size it is preferable but not required to use one of the chip selects from groups A or B Virtually any chip select other than CSAO or CSD3 would be suitable for the SED1374 interface In the example interface chip select CSB3 is used to control the SED1374 A 64K byte address space is used with the SED1374 control registers mapped into the top 32 bytes of the 64K byte block and the 40K bytes of display buffer mapped to the startin
26. 8 ay pMem LPBYTE MEM_OFFSET y 320 BitsPerPixel 8 0 for x 0 x lt 100 x 2 pMem 0x44 Draws 2 pixels with LUT color 4 pMem Pause here y getch Clear the display and all of video memory by writing 40960 bytes of 0 Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 70 SED1374 This is do switch to El Epson Research and Development Vancouver Design Center ne because an image in display memory is not rotated with the about to make SwivelView mode w ar pMem LPBYTE MEM_OFFSET do pMem 0 pMem while pMem lt LPBYTE MEM_OFFSET MEM_SIZE SwivelView mode E We will use the default SwivelView mode scheme so we have to adjust the ROTATED width to be a power of 2 NOTE current height will become the rotated width tmp 1 while Height gt 1 lt lt tmp tmp Height 1 lt lt tmp OffsetBytes Height BitsPerPixel 8 ER Set 1 Line Byte Count to size of the ROTATED width i e current height 2 Start Address to the offset of the width of the ROTATED display EX in SwivelView mode the start address registers point to bytes SET_REG 0x1C OffsetBytes SET_REG 0x0C S BYTE OffsetBytes r LOBYTE
27. A Frame rate must be entered in order for 1374CFG to complete the frame rate calcula tions If no frame rate is entered or the frame rate is set to 0 then the following dialog box will inform the user when they try to save the configuration 1374CFG MN ERROR Frame rate must be greater than zero Figure 6 ERROR Zero Frame Rate e Input Clock this field specifies the clock rate being applied to the SED1374 in kHz LUT Control The items in this section control the color depth for the SED1374 after initialization m LookUp Table C 1BPP C 2BPP C 4BPP C 8BPP I Bypass LUT Figure 7 LUT Control The color depth selections in this section will become enabled or disabled in response to the panel dimensions entered i e there is only enough memory to operate a 640x480 panel at 1 bit per pixel so the selections for 2 BPP 4 BPP and 8 BPP would be disabled if this size pane was selected e 1 BPP sets the color depth to 1 bit per pixel e 2 BPP sets the color depth to 2 bit per pixel e 4 BPP sets the color depth to 4 bit per pixel e 8 BPP sets the color depth to 8 bit per pixel SED1374 1374CFG EXE Configuration Program X26A B 001 01 Issue Date 98 10 27 Epson Research and Development Page 13 Vancouver Design Center Bypass LUT when selected this option causes the lookup table to be bypassed Selecting to bypass the lookup table results in a power saving as the lookup table section of the SED
28. I fl l fl L T fl l fl DRDY MOD X Ea X FPDAT 7 0 LINEI XLINE2 X LINES X LINE4 X XLINE479XLINE480 LINE X LINE2 e FPLINE EN DRDY MOD X H l HDP wl HNDP Ri FPSHIFT fe she tai tert a an 7 FPDAT7 o 14 1 XX X X 1 633 X FPDAT6 p EN O a a an EN E FPDAT5 EN 13 X11 XX aS X KSA KX FPDAT4 Ja MD MED X i X X X Xss KX FPDAT3 pe 15 Y 113 Y YX Y Y 1 637 X FPDAT2 2 A 16 X 1 14 X X X Y X 1 638 KK FPDAT1 mn 17 1 15 X X x X 639 KK FPDATO o A 18 X 1 46 X X X Y X Y 1 640 KX Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 12 Single Monochrome 8 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 40 Epson Research and Development Vancouver Design Center Sync Timing A Frame Pulse gt t4 t3 gt Line Pulse t5 MOD Data Timing Line Pulse t6 t8 t9 t7 t14 t11 t10 ye o gt Shift Pulse t12 t13 FPDAT 7 0 X Note For this timing diagram Mask FPSHIFT REG 01h bit
29. IO address FFEDh RW Bit 9 Bit 8 REG 1Ch Line BYTE COUNT REGISTER IO address FFFCh RW Line Byte Count 4 Panel Data Format X26A R 001 02 TETISTN olor Single width wath i Maoa REGo Palon REGIO REGIO iii bit 1 bit 0 0 Mono Single 4 bit LCD E 1 Mono Single 8 bit LCD 9 0 reserved 1 reserved E 0 reserved 3 1 Mono Dual 8 bit LCD i 0 reserved i 1 reserved 9 0 Color Single 4 bit LCD e 1 Color Single 8 bit LCD Format 1 0 reserved i 1 Color Single 8 bit LCD Format 2 i 0 reserved a 1 Color Dual 8 bit LCD l 0 reserved 1 1 reserved y decal 0 9 bit TFT Panel al 12 bit TFT Panel 5 High Performance Selection Bit Per Pixel Bit Per Pixel High Performance Bit 1 Bit 0 Display Modes REG 02 bit7 REG 02 bit 6 0 MCIk PCIk 8 1 bit per pixel i 1 MCIk PCIk 4 2 bit per pixel 2 0 MCIk PCIk 2 4 bit per pixel k 1 MCIk PCIk 8 bit per pixel 1 x X MCIk PCIk 6 Power Save Mode Selection E 7 a y o y 3 y Power Save Bit 1 Power Save Bit 0 Mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Software Power Save Mode Notes 1 These bits are used to identify the SED1373 at power on reset ys reserved 2 10 addresses are relative to the beginning of display memory 1 reserved 3 Gray Shade Color Mode Selection 1 Normal Operation Color Mono
30. OffsetBytes ET_REG 0x0D HIBYTE OffsetBytes Jx Set SwivelView mode Use the non X2 default scheme so we don t have to re calc the frame xx rate MCLK will be lt 25 MHz so we can leave auto switch enabled E SET_REG 0x1B 0x80 Draw a sol Starting c A 320 100 a for y 70 X26A G 002 02 id blue 100x100 rectangle centered on the display o ordinates assuming a 320x240 display are 2 240 100 2 110 70 y lt 180 y Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center xk S Page 71 et the memory pointer at the start of each line Pointer MEM_OFFS ET Y Line Width BPP 8 X BPP 8 NOTICE that in SwivelView mode we will use a value of 256 KK f af x pMem for or the line width value 11 03 LPBYTE MEM_OFFSET x 110 x lt 210 x 2 pMem 0x11 pMem Programming Notes and Examples Issue Date 99 04 27 not 240 y 256 BitsPerPixel 8 x BitsPerPixel 8 Draws 2 pixels in LUT color 1 SED1374 X26A G 002 02 Page 72 Epson Research and Development Vancouver Design Center 10 1 3 Header Files The header files included here are the required for the HAL sample to compile correctly HAL H Typical HAL header file for use with programs written to py use the SED1374 HAL
31. WE0 connect to lO Vpp SIZO WEO0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 23 Vancouver Design Center 5 5 LCD Interface Pin Mapping Table 5 3 LCD Interface Pin Mapping Monochrome Passive Panel Color Passive Panel Color TFT MD TFD SED1374 A 8 bit 8 bit Pin Name Sale a 8 bit Dual a Single Single 8 bit Dual 9 bit 12 bit Format 1 Format 2 FPFRAME FPFRAME FPLINE FPLINE FPSHIFT FPSHIFT DRDY MOD MOD MOD MOD FPSHIFT2 MOD MOD DRDY FPDATO driven 0 DO LDO driven 0 DO DO LDO R2 R3 FPDAT1 driven 0 D1 LD1 driven 0 D1 D1 LD1 R1 R2 FPDAT2 driven 0 D2 LD2 driven 0 D2 D2 LD2 RO R1 FPDAT3 driven 0 D3 LD3 driven 0 D3 D3 LD3 G2 G3 FPDAT4 DO D4 UDO DO D4 D4 UDO G1 G2 FPDAT5 D1 D5 UD1 D1 D5 D5 UD1 GO G1 FPDAT6 D2 D6 UD2 D2 D6 D6 UD2 B2 B3 FPDAT7 D3 D7 UD3 D3 D7 D7 UD3 B1 B2 FPDAT8 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 BO B1 FPDAT9 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 RO FPDAT10 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GO GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 FPDAT11 HW Video HW Video HW Video HW Video HW Video HW Video HW Video GPIO4 BO Invert Invert Invert Invert Invert Invert Invert Note 1 Unused GPIO pins must be connected
32. Writes value specified in Value to the register specified by Index Parameters DevID registered device ID Index register index to set Value value to write to the register Return Value ERR_OK operation completed with no problems int seReadDisplayByte int DevID DWORD Offset BYTE pByte Description Reads a byte from the display buffer at the specified offset and returns the value in pByte Parameters DevID registered device ID Offset offset in bytes from start of the display buffer to read from pByte pointer to a BYTE to return the value in Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr is greater 40 kb Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 56 SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center int seReadDisplayWord int DevID DWORD Offset WORD pWord Description Reads a word from the display buffer at the specified offset and returns the value in pWord Parameters DevID registered device ID Offset offset in bytes from start of the display buffer to read from pWord pointer to a WORD to return the value in Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr is greater than 40 kb int seReadDisplayDword int DevID DWORD Offset DWORD pDword Description Reads a dword from the display buffer at the specified offse
33. gt RDH OE gt gt RD WR WE gt CE1 gt gt WEO CE2 gt gt WE1 REG gt gt CS RESET gt gt RESET A 15 0 gt AB 15 0 D 15 0 gt DB 15 0 15K pull up WAIT WAIT O BUSCLK Oscillator CLKI SED1374 X26A G 009 02 Figure 4 1 Typical Implementation of PC Card to SED1374 Interface Interfacing to the PC Card Bus Issue Date 98 12 10 Epson Research and Development Page 13 Vancouver Design Center 4 2 SED1374 Hardware Configuration The SED1374 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx for details The tables below show only those configuration settings important to the PC Card host bus interface Table 4 1 Summary of Power On Reset Options Signal Low High CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF4 Active low LCDPWR signal Active high LCDPWR signal configuration for PC Card host bus interface Table 4 2 Host Bus Interface Selection CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 X SH 4 bus interface 0 0 1 X SH 3 bus interface 0 1 0 X reserved 0 1 1 X MC68K bus interface 1 16 bit 1 0 0 X reserved 1 0 1 x MC68K bus interface 2 16 bit 1 1
34. their controller ERR_OK operation completed with no problems ERR_UNKNOWN_DEVICE the HAL was unable to identify the display controller Returned when pID returns ID_UNKNOWN void seGetHalVersion const char pVersion const char pStatus const char pStatusRevision Description Parameters Return Value Programming Notes and Examples Issue Date 99 04 27 Retrieves the HAL library version information The return values are ASCII strings A typical return would be 1 01 B 5 HAL version 1 01 B is the beta designator this example would be Beta 5 If pStatus is NULL then pStatusRevision should be NULL too pVersion Pointer to string to return the version in must point to an allocated string of size VER_SIZE pStatus Pointer to a string to return the release status in must point to an allocated string of size STATUS_SIZE pStatusRevision Pointer to return the current revision of status must point to an allocated string of size STAT_REV_SIZE None SED1374 X26A G 002 02 Page 50 SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center int seSetBitsPerPixel int DevID int BitsPerPixel Description Parameter Return Value This routine sets the color depth the SED1374 displays in After performing validity checks to ensure the requested video mode can be set the appropriate registers are changed and the Look Up table is set its default values appropriate t
35. 0 0 reserved 1 1 0 1 reserved 1 1 1 1 Generic 2 16 bit a configuration for PC Card host bus interface Interfacing to the PC Card Bus SED1374 Issue Date 98 12 10 X26A G 009 02 Page 14 Epson Research and Development Vancouver Design Center 4 3 PAL Equations The PAL equations for the implementation presented in this document are as follows PAL device 16L8 OE PI 1 WE PI a CE1 PIN 3 CE2 PIN 4 REG PIN 5 PCRESET PIN 6 RESET PIN 14 WEO PIN oe WE1 PIN 16 RD PIN 17 RDWR PIN 18 ES PIN 19 equations WEO WE CEl amp REG IWE1 WE amp CE2 REG CS REG amp RD RDWR WEO WE1 IRD OE CEl amp REG IRDWR OE CE2 amp REG IRESET PCRESET 4 4 Register Memory Mapping The SED1374 is a memory mapped device The SED1374 memory may be addressed starting at 0000h or on consecutive 64K byte blocks and its internal registers are located in the upper 32 bytes of the 64K byte block i e REG 0 FFEOh While the PC Card socket provides 64M bytes of address space the SED1374 only needs a 64K byte block of memory to accommodate its 40K byte display buffer and its 32 byte register set For this reason only address bits A 15 0 are used while A 25 16 are ignored Because the entire 64M bytes of memory is available the SED1374 s memory and registers will
36. 01 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374CFG EXE Configuration Program X26A B 001 01 Issue Date 98 10 27 Epson Research and Development Vancouver Design Center Table of Contents introduci n ss aceras a a aa e Program Requirements 2 ee ee mm 4 Installation Usage 1374CFG Panel Information Miscellaneous Options System LUT Control Open Save Help Exit Comments 3 3 5 dias a ad is a A BA ye ee List of Figures Figure 1 1374CFG Window e Figure 2 Panel Information e Figure 3 Miscellaneous Options o e Figure 4 System Options e Figure 5 ERROR Frame Rate o e e Figure 6
37. 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Address Address Address Address Address Address Address Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG ODh bit 6 0 REG OCh bit 7 0 REG 0Dh bit 7 Screen 1 Start Address Bits 14 0 These bits determine the word address of the start of Screen 1 in landscape modes or the byte address of the start of Screen 1 in Swivel View modes Hardware Functional Specification Issue Date 99 04 29 Screen 1 Start Address Bit 15 This bit is for Swivel View mode only and has no effect in Landscape mode SED1374 X26A A 001 02 Page 62 Epson Research and Development Vancouver Design Center REG OFh Screen 2 Start Address Register LSB Address FFEFh Read Write Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Address Address Address Address Address Address Address Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 10h Screen 2 Start Address Register MSB Address FFFOh Read Write Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Address Address Address Address Address Address Address Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 10h bit 6 0 REG OFh bit 7 0 REG 10h bit 7 Screen 2 Start Ad
38. 10 ns 2 One Software WAIT State Required Note Page 29 CKIO may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Page 30 Epson Research and Development Vancouver Design Center 7 1 3 Motorola M68K 1 Interface Timing Telk o CT A eT e A 15 1 CS VALID R WH tl t2 AS UDS LDS INVALID B t4 et y t5 DTACK PEZ gt m Hi Z 18 t7 gt D 15 0 o lt E write a a VALID ue 19 t10 t11 D 15 0 i read HZ dl VALID Hind Figure 7 3 M68K 1 Bus Timing MC68000 Table 7 3 M68K 1 Bus Timing MC68000 Symbol Parameter Min Max Units foLk Bus Clock Frequency 0 33 MHz ToLk Bus Clock period 1 fcLK ti A 15 1 CS valid before AS falling edge 0 ns t2 A 15 1 CS hold from AS rising edge 0 ns 13 ASH low to DTACK driven high 16 ns t4 CLK to DTACK low 15 ns t5 AS high to DTACK high 20 ns t6 AS high to DTACK high impedance Telk t7 UDS LDS falling edge to D 15 0 valid write cycle TeLk t8 D 15 0 hold from AS rising edge write cycle 0 ns t9 UDS LDS falling edge to D 15 0 driven read cycle 15 ns t10 D 15 0 valid to DTACK falling edge read cycle 0 ns t11 UDS LDS rising edge to D 15 0 high impedanc
39. 15 0 See Host Bus Interface Pin Mapping for summary SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Page 19 Pin Names Type Pin Cell RESET State Description WE0 l 77 CS Input This See pin has multiple functions For SH 3 SH 4 mode this pin inputs the write enable signal for the lower data byte WEO For MC68K 1 this pin must be tied to IO Vpp For MC68K 2 this pin inputs the bus size bit 0 SIZO For Generic 1 this pin inputs the write enable signal for the lower data byte WEO For Generic 2 this pin inputs the write enable signal WE Host Bus Interface Pin Mapping for summary WE1 l 78 CS Input This See pin has multiple functions For SH 3 SH 4 mode this pin inputs the write enable signal for the upper data byte WE1 For MC68K 1 this pin inputs the upper data strobe UDS For MC68K 2 this pin inputs the data strobe DS For Generic 1 this pin inputs the write enable signal for the upper data byte WE1 For Generic 2 this pin inputs the byte enable signal for the high data byte BHE Host Bus Interface Pin Mapping for summary CS l 74 Input This pin inputs the chip select signal BCLK l 71 Input This pin inputs the system bus clock BS l 75 CS Input This
40. 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to an 8 bit Processor X26A G 013 01 Issue Date 99 05 04 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T introduction fort Scere mela ce Acca Bes Go ae IAS bree ee A A a Gud o 7 2 Interfacing to an 8 bit Processor 8 2 1 The Generic 8 bit Processor System Bus 2 ee eee eee 8 3 SED1374 BUS Interface 2 22 02 40 ee Ree A ee 9 3 1 Host Bus Pin Connection e Yd 3 2 Generic 2 Interface Mode 2 a ee ee O 4 8 Bit Processor to SED1374 Interface lt lt 11 4 1 Hardware Description 2 2 2 11 4 22 SED1374 Hardware Configuration 2 e LA 4 3 Register Memory Mapping LA SoftWare s ee Oe ee SESE a A ER A a bee 8 13 Referenc Si soe a ee tetas E ees ate eee et he de es 14 Ol Doctiments 1005 4 as la Bh Choe acto ae te amp A ee ae a ea dS 6 2 DocumentSources 2 ee 14 7 Technical Support lt s 2340426544 2460 ARA 15 7 1 Epson LCD CRT Controllers SED1374 2 2 a a eee 1S Interfacing to an 8 bit Processor SED1374 Issue Date 99 05 04 X26A G 013 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to an 8 bit Processor X26A G 013 01 Issue Date 99 05 04 Epson Research a
41. 25MHz is the maximum CLK so PCLK cannot be higher than 12 5MHz in this mode Power Consumption Lowest power consumption Typically 20 higher than Default Mode Panning Vertical panning in 2 line increments Vertical panning in 1 line increments Performance Nominal performance Slightly higher performance than Default Mode Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 42 7 6 Examples SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center Example 6 Enable default SwivelView mode for a 320x240 panel at 4 bpp Before switching to SwivelView mode from landscape mode display memory should be cleared to make the user perceived transition smoother Images in display memory are not rotated automatically by hardware and the garbled image would be visible for a short period of time if video memory is not cleared In this example we will bypass having to recalculate the horizontal and vertical non display times frame rate by selecting the default Swivel View mode scheme 1 Calculate and set the Screen 1 Start Word Address register OffsetBytes Width x BitsPerPixel 8 1 256 x 4 8 1 127 007Fh Width is the width of the Swivel View mode display in this case the next power of two greater than 240 pixels or 256 Set Screen Display Start Word Address LSB REG 0Ch to 7Fh and Screen1 Dis play Start Word Address MSB REG ODh to 00h 2 Calculate the Li
42. 3 is set to 1 Figure 7 13 Single Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 4 Ts t9 Shift Pulse period 8 Ts t10 Shift Pulse pulse width low 4 Ts t11 Shift Pulse pulse width high 4 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 4 Ts t13 FPDAT 7 0 hold to Shift Pulse falling edge 4 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 tlmin t3min 9Ts 3 t3min REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 4 Ts 5 tYmin REG O8h bits 4 0 x 8 13 Ts SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center 7 3 5 Single Color 4 Bit Panel Timing Page 41 FPFRAME FPLINE DRDY MOD FPDAT 7 4 FPLINE DRDY MOD FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4
43. 37 Vancouver Design Center 7 3 3 Single Monochrome 4 Bit Panel Timing VDP VNDP FPFRAME o FPLINE f l f Ll fl l f l J DRDY MOD A FPDAT 7 4 XLINE1 X LINE2 X LINES X LINE4 X XLINE239XLINE240 LINE1 X LINE2 FPLINE I DRDY MOD y e HDP HNDP FPSHIFT e i 3 LJ LJ L MA ale ae oe J FPDAT7 YA 1 1 15 X X Y X 1 317 X FPDAT6 o 12 X 16 X X X Xaas X FPDAT5 E 13 X 17 X Y y 4319 x FPDAT4 a 14 Y 1 8 X t Y 1 320 X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 10 Single Monochrome 4 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 38 Epson Research and Development Vancouver Design Center t2 Sync Timing b lt Frame Pulse t4 a 8 gt Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 t8 t9 t7 t14 t11 t10 lt gt gt Shift Pulse t12 t13 a FPDAT 7 4 1 2 x Note For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 11 Single Monochrome 4 B
44. 53 Vancouver Design Center Symbol Parameter Min Typ Max Units t Shift Pulse period 1 note 1 t2 Shift Pulse pulse width high 0 5 Ts 13 Shift Pulse pulse width low 0 5 Ts 14 Data setup to Shift Pulse falling edge 0 5 Ts t5 Data hold from Shift Pulse falling edge 0 5 Ts t6 Line Pulse cycle time note 2 t7 Line Pulse pulse width low 9 Ts t8 Frame Pulse cycle time note 3 t9 Frame Pulse pulse width low 2t6 t10 Horizontal display period note 4 t11 Line Pulse setup to Shift Pulse falling edge 0 5 Ts t2 a A to Line Pulse falling 16 18Ts t13 DRDY to Shift Pulse falling edge setup time 0 5 Ts t14 DRDY pulse width note 5 t15 DRDY falling edge to Line Pulse falling edge note 6 t16 DRDY hold from Shift Pulse falling edge 0 5 Ts t17 Line Pulse Falling edge to DRDY active note 7 250 1 Ts pixel clock period 2 t6min REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 3 t8min REG O6h bits 1 0 REG O5h bits 7 0 1 REG OAh bits 6 0 Lines 4 t10min REG 04h bits 6 0 1 x 8 Ts 5 ti4min REG 04h bits 6 0 1 x 8 Ts 6 ti5min REG O7h bits 4 0 x 8 16 Ts 7 t17min REG 08h bits 4 0 REG 07 x 8 16 Ts Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 54 Epson Research and Development Vancouver Design Center 8 Registers 8 1 Register Mapping The SED 1374 registers are located in the upper 32 bytes of the 64K byte SED1374 address range The registers are acc
45. 99 04 29 Epson Research and Development Page 81 Vancouver Design Center 12 2 Alternate SwivelView Mode Alternate SwivelView Mode may be used when the virtual image size of Default SwivelView Mode cannot be contained in the 40kByte integrated frame buffer For example the panel size is 240x160 and the display mode is 8 bit per pixel The minimum virtual image size for Default Swivel View Mode would be 240x256 which requires 60K bytes Alternate Swivel View Mode requires a panel size of only 240x160 which needs only 38 400 bytes Alternate Swivel View Mode requires the memory clock MCLK to be at least twice the frequency of the pixel clock PCLK i e MCLK gt 2 x PCLK Because of this the power consumption in Alternate Swivel View Mode is higher than in Default SwivelView Mode The following figure shows how the programmer sees a 240x160 image and how the image is being displayed The application image is written to the SED1374 in the following sense A B C D The display is refreshed by the SED1374 in the following sense B D A C physical memory start Eo address HITA B m a SwivelView z window display gt E o start SE 2 address 55 lt a O C D v 240 lt gt 160 image seen by programmer image refreshed by SED1374 image in display buffer Figure 12 2 Relationship Between The Screen Image and the Image Refreshed by SED1374 Hardware Functional Specification SED1374 Iss
46. Bit 0 bit 7 bit 3 bit 2 bits 1 0 SED1374 X26A A 001 02 Look Up Table Bypass When the Look Up Table Bypass bit 0 the Green Look Up Table is used for display data output in gray shade modes When this bit 1 the Look Up Table is bypassed for dis play data output in gray shade modes for power save purposes See Look Up Table Architecture on page 72 There is no effect on changing this bit in color modes In color display mode the Look Up Table cannot be bypassed LCDPWR Override This bit is used to override the panel on off sequencing logic When this bit 0 LCDPWR and the panel interface signals are controlled by the sequencing logic When this bit 1 LCDPWR is forced to off and the panel interface signals are forced low immediately upon entering power save mode See Section 7 3 2 Power Down Up Timing on page 36 for further information Hardware Power Save Enable When this bit 1 GPIOO is used as the Hardware Power Save input pin When this bit 0 GPIOO operates normally Table 8 5 Hardware Power Save GPIOO Operation Hardware Power GPIOO NESEN Save Enable GPSA Config Status Control GPIOO Operation State REG 18h bit 0 REG 03h bit 2 REG 19h bit 0 0 X X X GPIOO Input 1 0 0 reads pin status high impedance 1 0 1 0 GPIOO Output 0 1 0 1 1 GPIOO Output 1 Hardware Power Save i 1 x a Input active high Software Power Save Bi
47. Bit Per Pixel Bit 1 Bit Per Pixel Bit 0 n REG 01 bit 5 REG 02 bit 7 REG 02 bit 6 Display Mode 7 Look Up Table Access 0 2 Colors 1 Bit Per Pixel Color Mono REG 15h 0 REG 01h Look Up Table Selected Pointer S 1 4 Colors 2 Bit Per Pixel el 5 1 bit5 bit 4 A AS 1 y o 16 Colors 4 Bit Per Pixel 0 x x Green Gray Look Up Table G n G n 1 G n 2 1 256 Colors 8 Bit Per Pixel 1 0 0 Auto Increment Rin G n Bin R n 1 G n 1 y 2 Gray Shade 1 Bit Per Pixel 1 0 1 Red Look Up Table Rin R n 1 R n 2 o 1 4 Gray Shade 2 Bit Per Pixel 1 1 0 Green Gray Look Up Table G n G n 1 G n 2 1 o 16 Gray Shade 4 Bit Per Pixel 1 1 1 Blue Look Up Table Bin B n 1 B n 2 1 reserved REG 0Fh SCREEN 2 START WORD ADD Screen 2 Stat Bit 5 Bit 4 Bit 3 Bit 2 REG 10h SCREEN 2 START WORD ADDRESS REGISTER MSB IO address FFF RESS REGISTER LSB IO address FFEFh RW rt Word Address REG OF REG 10h Bit 15 Bit 14 REG 12h Memory ADDR Bit 13 ESS OFFSET REGISTER Screen 2 Start Bit 12 Word Address Bit 11 Bit 10 1O address FFF2h RW Bit 7 Bit 6 Bit 5 Page 1 Bit 4 Memory Address Offset Bit 3 Bit 2 99 04 23 SED 1374 Register Summary X26A R 001 02 Page 2 99 04 23 EPSON SED1374 Embedded Memory Color LCD Controller 1374CFG EXE Configuration Program Document No X26A B 001
48. Bus The MC68328 is an integrated controller for handheld products based upon the MC68EC000 microprocessor core It implements a 16 bit data bus and a 32 bit address bus The bus interface consists of all the standard MC68000 bus interface signals plus some new signals intended to simplify the task of interfacing to typical memory and peripheral devices The MC68000 bus control signals are well documented in Motorola s user manuals and will not be described here A brief summary of the new signals appears below Output Enable OE is asserted when a read cycle is in process it is intended to connect to the output enable control of a typical static RAM EPROM or Flash EPROM device e Upper Write Enable and Lower Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus they may be directly connected to the write enable inputs of a typical memory device The SED 1374 implements the MC68000 bus interface using its MC68K 1 mode so this mode may be used to connect the MC68328 directly to the SED1374 with no glue logic However several of the MC68000 bus control signals are multiplexed with IO and interrupt signals on the MC68328 and in many applications it may be desirable to make these pins available for these alternate functions This requirement may be accommodated through use of the Generic 1 interface mode on the SED1374 2 2 Chip Select Module SED1374 X26A G 007
49. DIP socketed 32 1 U8 74ALS125 SO 20 TI74ALS125 33 1 U9 RD 0412 Xentek RD 0412 positive PS 34 1 U10 EPNOO1 Xentek EPNO01 negative PS SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 SED1374 X26A G 005 01 Page 20 8 Schematic Diagrams Epson Research and Development Vancouver Design Center 7 E a a A l E al a 2 2 m E A 28 i E E E x E o o 5 a8 l d 3 Be ait 4 g 3 8 ae E E Pl za E Ole o 4 t RI gt i el E z f B 4 a s a x a E E at A E 3 8 E ES 2 a El l pi 28 LGA PA O 4 E 3 E E ne Self 5 ih a Ea 2 os oe f er ee Ff e ES 3 E Hke ls Es 2 z E E Hb I 4 5 U iy fy e a 4 H Elo 8 ss 83 Q HH HHI S A a re Hee a aksa NS man s Be by a 8 E ks l AN pets E a a lo O o Z o x t a BE E o 8 3 2 E t aan 3 7 3 3 E E Ill o E 3 3 dls a 5 SED1374 X26A G 005 01 Figure 8 1 SED1374B0C Schematic Diagram 1 of 4 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 Page 21 Boor 60 1990190 Mepa ered
50. FFE8h Read Write Horizontal Horizontal Horizontal Horizontal Horizontal n a n a n a Non Display Non Display Non Display Non Display Non Display Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0 bits 4 0 Horizontal Non Display Period These bits specify the horizontal non display period in 8 pixel resolution HorizontalNonDisplayPeriod pixels REG 08h 4 x 8 REG 09h FPFRAME Start Position Address FFE9h Read Write FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME n a n a Start Position Start Position Start Position Start Position Start Position Start Position Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 5 0 FPFRAME Start Position These bits are used in TFT MD TFD mode to specify the position of the FPFRAME pulse These bits specify the number of lines between the last line of display data FPDAT and the leading edge of FPFRAME This register is effective in TFT MD TFD mode only REG O1h bit 7 1 FPFRAMEposition lines REG 09h The contents of this register must be greater than zero and less than or equal to the Vertical Non Display Period Register i e 1 lt REG 09h lt REG OAh SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Page 61 REG OAh Vertical Non Display Period Address FFEAh Read Write Vertical Non Vertical Non Vertical Non Ve
51. For example the panel size is 320x240 and the display mode is 4 bit per pixel The virtual image size is 320x256 which can be contained within the 40k Byte display buffer Default Swivel View Mode also requires memory clock MCLK gt pixel clock PCLK Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 37 The following figures show how the programmer sees a 240x320 image and how the image is displayed The application image is written to the SED1374 in the following sense A B C D The display is refreshed by the SED1374 in the following sense B D A C physical memory start address 4 Ra p 256 A A B E w A m a Si at we gt 8 window display 23 o start 5g N address 3 3 lt 7 o C D y y lt 320 x 240 gt image seen by programmer image refreshed by SED1374 image in display buffer Figure 7 1 Relationship Between The Screen Image and the Image Refreshed by SED1374 7 3 Alternate SwivelView Mode Programming Notes and Examples Issue Date 99 04 27 Alternate Swivel View Mode may be used when the virtual image size of Default SwivelView Mode cannot be contained in the 40k Byte integrated frame buffer For example when the panel size is 240x160 and the display mode is 8 bit per pixel the minimum virtual image size for Default Swivel View Mode would be 240x256 which requires 60K bytes Alterna
52. HAL The HAL currently can manage only one device ERROR Could not register 1374 device A 1374 device was not found at the configured addresses Check the configuration address using the 1374CFG configuration program ERROR Did not detect 1374 The HAL was unable to read the revision code register on the SED 1374 Ensure that the SED1374 hardware is installed and that the hardware platform has been set up correctly 1374VIRT Display Utility SED1374 Issue Date 98 10 20 X26A B 004 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374VIRT Display Utility X26A B 004 01 Issue Date 98 10 20 EPSON SED1374 Embedded Memory Color LCD Controller 1374PLAY Diagnostic Utility Document No X26A B 005 02 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Devel
53. Installation 1374SPLT Display Utility Issue Date 98 10 20 1374SPLT has been tested with the following SED1374 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the SED1374 Programming Notes and Examples manual document number X26A G 002 xx PC platform Copy the file 1374SPLT EXE to a directory that is in the DOS path on your hard drive Embedded platform Download the program 1374SPLT to the system SED1374 X26A B 003 01 Page 4 Epson Research and Development Vancouver Design Center Usage PC platform at the prompt type 1374SPLT a 1 p Embedded platform execute 1374sp1t and at the prompt type the command line argument Where no argument enables manual split screen operation a enables automatic split screen operation a timer is used to move screen 2 n display the help screen After starting 1374SPLT the following keyboard commands are available Manual mode u move Screen 2 up Jl d move Screen 2 down HOME covers Screen 1 with Screen 2 END displays only Screen 1 Automatic mode any key change the direction of split screen movemen
54. Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse falling edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 5 t7 Shift Pulse falling edge to Line Pulse falling edge note 6 t8 Line Pulse falling edge to Shift Pulse falling edge t14 4 Ts t9 Shift Pulse period 8 Ts t10 Shift Pulse pulse width low 4 Ts t11 Shift Pulse pulse width high 4 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 4 Ts t13 FPDATT 7 0 hold to Shift Pulse falling edge 4 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 39 Ts 1 Ts pixel clock period 2 tlmin t3min 9Ts 3 83min REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 x 2 Ts 5 t6min REG 08h bits 4 0 x 2 x 8 20 Ts 6 tmin REG 08h bits 4 0 x 2 x 8 29 Ts SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center 7 3 9 Dual Color 8 Bit Panel Timing Page 49 P VDP rie VNDP gt FPFRAME ae AE FPLINE l l l f l I ll l f l l fl DRDY MOD y H X FPDAT 7 0 LINE 1 241 X une 2 242 X LINE 239 479XLINE 240 480 LINE 1 241 X FPLINE DRDY MOD y P HDP dia HNDP gt i RE
55. MPC8xxSystemBus 2 2 2 eee ee ee 8 2 2 MPC821 Bus Overview ia me ren a a i i a ae a a a a ee e r 2 2 1 Normal Non Burst Bus Transactions e 9 2 22 Burst Cy less rt ti a AE A a E AC a a 10 2 3 Memory Controller Module A 2 3 1 General Purpose Chip Select Module le GPCM Aa DA A dd 11 2 3 2 User Programmable Machine UPM o o e 12 3 SED1374 Host Bus Interface 13 3 1 Host Bus Interface Modes o 13 3 2 Generic 1 Host Bus Interface Mode 2 2 2 202202222242042424 14 4 MPC821 to SED1374 Interface o 15 4 1 Hardware Description 2 0 0 0 000022 LS 4 2 Hardware Connections sin i Bae te Ge e GaN Petes AS esta he eee NO 4 3 SED1374 Hardware PEN a niati ton gaat aia Sera th ak dy abe ap ok Gad ah Se ee he S 4 4 MPC821 Chip Select Configuration 2 2 eee 19 45 Test Software ios 46 a ee Oe a ee ne we a a ce oe 20 5 SoftWare a Se E a Se A ADA DE ee a 22 Reference se nai eek ao ee dal Oa ye ae eed aoe GO a ee ew ea ea Gee Rees 23 6 1 DOCUMENT 2 ara a Seer ce a ee ele en a ee ie a 28 6 2 DocumentSources e 23 Technical Support dal a E e a ia ee a 24 7 1 EPSON LCD CRT Controllers SED1374 ww 24 7 2 Motorola MPC821 Processor ee ee A Interfacing to the Motorola MPC821 Microprocessor SED1374
56. Mapping Note Bits CARDIIOEN and CARD2IOEN need to be set in TX3912 Memory Configuration Register 3 Table 3 1 TX3912 to Unbuffered PC Card Slots System Address Mapping Function Function TASIE Addrass nize CARDnIOEN 0 CARDnIOEN 1 0800 0000h 64M byte Card 1 Attribute Card 1 IO 0C00 0000h 64M byte Card 2 Attribute Card 2 IO 6400 0000h 64M byte Card 1 Memory 6400 0000h 64M byte Card 2 Memory When the TX3912 accesses the PC Card slots buffered through the ITE IT8368E bits CARDIIOEN and CARD2IOEN are ignored and the attribute IO space of the TX3912 is divided into Attribute T O and SED 1374 access Table 3 2 TX3912 to PC Card Slots Address Remapping Using the IT8368E provides all details of the Attribute IO address reallocation by the IT8368E Table 3 2 TX3912 to PC Card Slots Address Remapping Using the IT8368E IT8368E Uses PC Card Slot TX3912 Address Size Function 0800 0000h 16M byte Card 1 IO 4 0900 0000h 16M byte SED1374 aliased 256 times at 64K byte intervals 0A00 0000h 32M byte Card 1 Attribute 6400 0000h 64M byte Card 1 Memory 0C00 0000h 16M byte Card 2 IO o 0D00 0000h 16M byte SED1374 aliased 256 times at 64K byte intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory SED1374 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 01 Issue Date 98 11 09 EPSON Research and Development Page 13 V
57. Organization This register is where the 4 bit red green blue data value is written read With each successive read or write the internal RGB selector is incremented Depending on the RGB Index setting one to three access of this register will result in the Look Up Table Address incrementing Color and monochrome operation is slightly different Both Look Up Table schemes are described here The Look Up Table treats the value of a pixel as an index into an array of colors or gray shades For example a pixel value of zero would point to the first LUT entry a pixel value of 7 would point to the eighth LUT entry shade This intensity can range in value between 00 and OFh The value inside each LUT entry represents the intensity of the given color or gray The following table shows how many elements from each Look Up Table index are used at the different color depths Table 4 4 Look Up Table Configurations 4 Bit Wide Look Up Table Display Mode Red Green Blue 1 Bpp Gray 4 banks of 2 2 Bpp Gray 4 banks of 4 4 Bpp Gray 1 bank of 16 1 Bpp Color 4 banks of 2 4 banks of 2 4 banks of 2 2 Bpp Color 4 banks of 4 4 banks of 4 4 banks of 4 4 Bpp Color 1 bank of 16 1 bank of 16 1 bank of 16 8 Bpp Color 2 banks of 8 2 banks of 8 4 banks of 4 Programming Notes and Examples Issue Date 99 04 27 Indicates the Look Up Table is not used for that display mode SED1374 X26A G
58. Position 8 REG O7h 2 REG 19h GPIO STATUS REG 1Ah SCRATCH PAD CONTROL RE REGISTER lO GPIO4 Pin IO Status GPIO3 Pin IO Status address FFFAh RW GISTER IO address FFF9h RW GPIO2 Pin 10 Status GPIO1 Pin IO Status GPIOO Pin IO Status Bit 7 Bit 6 Bit 5 Scratch Pad Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 08h HORIZONTAL NON DISPLAY PERIOD O add REG 09h FPFRAME START POSITION IO address FFE9h RW ress FFE8h RW orizontal Non Display Perio Bit 3 Bit 2 REG 1Bh SwiveLView MODE REGISTER IO address SwivelView Mode Sel SwivelView Mode En n a FFFBh RW n a n a reserved Mode PCLK SwivelView Select Bit 1 Bit O n a n a Bit5 Bit 4 REG OAh VERTICAL NON DISPLAY PERIOD REGISTER FPFrame Start Position Bit 3 Bit 2 lO address FFEAh RW Vert Non Disp Status n a REG OBh MOD Rate REGISTER lO ad Bit 5 Bit 4 dress FFEBh RW Vertical Non Display Period Bit 3 Bit 2 n a n a Bit 5 Bit 4 MOD Bit 3 Rate Bit 2 REG 0Ch SCREEN 1 STA Bit 7 Bit 6 Bit 5 Bit 4 RT WORD ADDRESS REGISTER LSB IO address FFE Screen 1 Start Word Address REG 0Ch REG ODh Bit 3 Bit 2 Ch RW Bit 1 Bit 0 REG 0Dh SCREEN 1 STAI reserved a Bit 14 Bit 13 Screen Bit 12 1 Start Word Address Bit 11 Bit 10 RT WORD ADDRESS REGISTER MSB
59. Power Save bits are used to set the software power save mode The two valid states are 00 for power save and 11 for normal operation Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 35 Vancouver Design Center 6 3 LCD Enable Disable The descriptions below cover manually powering the LCD panel up and down Use them only if the power supply connected to the panel requires more than 127 frames to discharge on power down or if the panel requires starting the LCD logic well in advance of enabling LCD power Power On Enable Sequence The following is the recommended sequence for manually powering up an LCD panel These steps would be used if LCD power had to be applied later than LCD logic 1 2 Set REG 03h bit 3 LCDPWR Override to 1 ensures that LCD power is disabled Enable LCD logic This is done by either setting GPIOO to 0 for hardware power save mode and or by setting REG 03h bits 1 0 software power save to 11 Count x Vertical Non Display Periods x corresponds the length of time LCD logic must be enabled before LCD power up converted to the equivalent vertical non display periods For example at 72 HZ count ing 36 non display periods results in a one half second delay Set REG 03h bit 3 to 0 enable LCD Power Power Off Disable Sequence The following is the recommended sequence for manually powering down an LCD panel These steps would be used 1f po
60. RD RD RD connect to lO Vpp SIZ1 RDO RD WE0 WE0 WE0 connect to lO Vpp SIZO WEO0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET SED1374 Interfacing to the PC Card Bus X26A G 009 02 Issue Date 98 12 10 Epson Research and Development Page 11 Vancouver Design Center Two other configuration options CNF 4 3 are also made at time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host bus interface offers more flexibility in configuring the SED1374 with other CPUs For details on configuration refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx 3 2 Generic 1 Interface Mode Generic 1 interface mode is the most general and least processor specific interface mode on the SED1374 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the SED1374 host interface It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order d
61. Read Write Vertical Vertical n a n a n a n a n a n a Panel Size Panel Size Bit 9 Bit 8 REG 05h bits 7 0 REG 06h bits 1 0 Vertical Panel Size Bits 9 0 programmed with a value calculated as follows VerticalPanelSizeRegister VerticalPanelResolution lines 1 This 10 bit register determines the vertical resolution of the panel This register must be 3FFh is the maximum value of this register for a vertical resolution of 1024 lines Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Page 60 Epson Research and Development Vancouver Design Center REG 07h FPLINE Start Position Address FFE7h Read Write Ma A ra FPLINE Start FPLINE Start FPLINE Start FPLINE Start FPLINE Start Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit 0 bits 4 0 FPLINE Start Position These bits are used in TFT MD TFD mode to specify the position of the FPLINE pulse These bits specify the delay in 8 pixel resolution from the end of a line of display data FPDAT to the leading edge of FPLINE This register is effective in TFT MD TFD mode only REG O1h bit 7 1 This register is programmed as follows FPLINEposition pixels REG 07h 2 x8 The following constraint must be satisfied REG 07h lt REG 08h REG 08h Horizontal Non Display Period Address
62. Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 02 Issue Date 99 01 05 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T INTRODUCTION aora ea ce A es A OA bree wd av ate doe Guest 7 2 Interfacing to the MC68328 2 0 2 ee es 8 2 1 The MC68328 System Bus e e ee ee 8 2 2 Chip Select Module sr a 468 pi eae er ee ae ea a ee ee a 8 3 SED1374 Host Bus Interface o 9 3 1 Bus Interface Modes 2 2 ee ee Yd 3 2 Generic l Interface Mode 0 2 2 4 6 6 10 3 3 MC68K 1 Interface Mode 2 2 ee ee 11 4 MC68328 To SED1374 Interface es 12 4 1 Hardware Description boa du ee ee ee LA
63. Table 3 2 SED1374 75 Generic 2 Interface Pin Mapping Pin Name Pin Function WE1 BHE BS Connect to lO Vpp RD WR Connect to lO Vpp RD RD WEO WE SDU1374 75 TMPR3912 22U CPU Module Issue Date 98 12 23 X00A G 004 01 Page 12 EPSON Research and Development Vancouver Design Center 4 CPU Module Description 4 1 Clock Signals 4 1 1 BUSCLK 4 1 2 CLKI This section will describe the various parts of the CPU module that pertain to the SED1374 75 LCD Controller Because the bus clock for the SED1374 75 does not need to be synchronous with the bus interface control signals a lot of flexibility is available in the choice for BUSCLK In this CPU module BUSCLK is a divided by two version of the SDRAM clock signal DCLKOUT Since DCLKOUT equals 73 728MHz BUSCLK 36 864MHz The pixel clock for the SED1374 75 CLKI is also asynchronous with respect to the interface control signals This clock is selected based upon panel frame rates power vs performance budget and maximum input frequencies The maximum CLKI input is 25MHz if the internal CLKI 2 isn t used and if it is used the maximum input is 5OMHz On the CPU module CLKI s default input is a divided by four version of DCLKOUT which gives a CLKI 18 432MHZ This frequency gives good performance for 320x240 resolution panels for both portrait and landscape modes If power saving is desired the CLKI can be reduced by using the int
64. Vv 28 1 l 0 1 20 ES E 0 5 sll 0 18 0 05 A y g I pl i f ee A 0 10 y 0 0 5 5 1 0 Figure 14 1 Mechanical Drawing QFP14 SED1374 X26A A 001 02 Hardware Functional Specification Issue Date 99 04 29 EPSON SED1374 Embedded Memory Color LCD Controller Programming Notes and Examples Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction iio aoe es ht ke Se ei a 7 2 Initialization 2 3 4 00d A Gk AA ae he a a A Se ho a 8 2 1 Frame Rate Calculation 2 Dd 3 Memory Models lt a s s soaa 000 a A RAR ew el ee we
65. WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the SED1374 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the SED1374 These signals must be generated by external hardware based on the control outputs from the host CPU e WAIT is a signal output from the SED1374 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1374 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1374 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the SED1374 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 01 05 Epson Research and Development Vancouver Design Center 4 MPC821 to SED1374 Interface 4 1 Hardware Description Page 1
66. WR RD WR RD WR R W R W RD1 connect to lO Vpp RD RD RD connect to lO Vpp SIZ1 RDO RD WEO WEO0 WE0 connect to lO Vpp SIZO WE0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET Interfacing to the Motorola MC68328 Dragonball Microprocessor SED1374 Issue Date 99 01 05 X26A G 007 02 Page 10 Epson Research and Development Vancouver Design Center Two other configuration options CNF 4 3 are also made at time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host bus interface offers more flexibility in configuring the SED1374 with other CPUs For details on configuration refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx 3 2 Generic 1 Interface Mode SED1374 X26A G 007 02 Generic 1 interface mode is the most general and least processor specific interface mode on the SED1374 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the SED1374 host interface It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respect
67. X26A G 013 01 Page 14 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Epson Research and Development Inc SED1374 Embedded Memory LCD Controller Hardware Functional Specification Document Number X26A A 002 xx e Epson Research and Development Inc SDU 374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx e Epson Research and Development Inc Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e Epson Electronics America Website http www eea epson com SED1374 Interfacing to an 8 bit Processor X26A G 013 01 Issue Date 99 05 04 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD CRT Controllers SED1374 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Interfacing to an 8 bit Processor Issue Date 99 05 04 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http vww eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Page 15 Taiwan R O C Ep
68. and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft Windows and the Windows CE Logo are registered trademarks of Microsoft Corporation ey X26A C 001 05 05 EPSON SED1374 Embedded Memory LCD Controller Hardware Functional Specification Document Number X26A A 001 02 Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introd
69. at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com 1 2 Overview Description The SED1374 is a color monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer The high integration of the SED1374 provides a low cost low power single chip solution to meet the requirements of embedded markets such as Office Automation equipment Mobile Communications devices and Hand Held PCs where board size and battery life are major concerns Products requiring a Portrait display can take advantage of the Swivelview 90 Hardware Rotate feature of the SED1374 Virtual and Split Screen are just some of the display modes supported The above features combined with the Operating System independence of the SED 1374 make it the ideal solution for a wide variety of applications Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 10 Epson Research and Development Vancouver Design Center 2 Features 2 1 Integrated Frame Buffer e Embedded 40K byte SRAM display buffer 2 2 CPU Interface e Direct support of the following interfaces Hitachi SH 3 Hitachi SH 4 Motorola M68K MPU bus interface using WAIT signal e Direct memory mapping of internal registers e Single level CPU write buffer e Registers are mapped into upper 32
70. be aliased every 64K bytes for a total of 1024 times Note If aliasing is not desirable the upper addresses must be fully decoded SED1374 Interfacing to the PC Card Bus X26A G 009 02 Issue Date 98 12 10 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1374 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1374CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1374 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www erd epson com Interfacing to the PC Card Bus SED1374 Issue Date 98 12 10 X26A G 009 02 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents PC Card PCMCIA Standard March 1997 e Epson Research and Development Inc SED 374 Embedded Memory Color LCD Controller Hardware Functional Specification Document Number X26A A 001 xx e Epson Research and Development Inc SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx Epson Research and Development Inc SED1374 Programming Notes and Example
71. bus architectures the SDU1374B0C board also provides CPU Bus interface connectors For more information regarding the SED1374 refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx 80 pin QFP14 package SMT technology for all appropriate devices 4 8 bit monochrome and color passive LCD panel support 9 12 bit LCD TFT D TFD panel support Selectable 3 3V or 5 0V LCD panel support Oscillator support for CLKI up to 5OMHz with internal clock divide or 25MHz with no internal clock divide Embedded 40K byte SRAM display buffer for 1 2 4 bit per pixel bpp 2 4 16 level gray shade display and 1 2 4 8 bpp 2 4 16 256 level color display Support for software and hardware power save modes On board adjustable LCD bias positive power supply 23V to 40V On board adjustable LCD bias negative power supply 14V to 24V 16 bit ISA bus support CPU Bus interface header strips for non ISA bus support SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1374 Issue Date 98 10 26 X26A G 005 01 Page 8 Epson Research and Development Vancouver Design Center 2 Installation and Configuration The SED 1374 has five configuration inputs CNF 4 0 which are read on the rising edge of RESET and are fully configurable on this evaluation board One six position DIP switch is provided on the board to configure these five configuration inputs and to enable disable hardware power save mode The fo
72. bus interface configuration For details on configuration refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx The table below shows those configuration settings relevant to this specific interface Table 3 3 SED1374 Configuration Using the IT8368E SED1374 Value hard wired on this pin is used to configure Configuration Pin 1 10 Vpp 0 Vss BS Generic 2 CNF3 Big Endian CNF 2 0 configuration for connection using ITE IT8368E When the SED 1374 is configured for Generic 1 interface the host interface pins are mapped as in the table below Table 3 4 SED1374 Generic 1 Interface Pin Mapping Pin Name Pin Function WE1 WE1 BS connect to Vsg RD WR RD1 RD RDO WEO WEO Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1374 Issue Date 98 11 09 X26A G 012 01 Page 14 4 Software SED1374 X26A G 012 01 EPSON Research and Development Vancouver Design Center Test utilities and Windows CE v2 0 display drivers are available for the SED 1374 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1357CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source T
73. by one of two types of timing generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in value to the least significant bit For example the most significant bits of the address bus and data bus are AO and DO while the least significant bits are A31 and D31 The MPC8xx uses both a 32 bit address and data bus A parity bit is supported for each of the four byte lanes on the data bus Parity checking is done when data is read from external memory or peripherals and generated by the MPC8xx bus controller on write cycles All IO accesses are memory mapped meaning there is no separate IO space in the Power PC architecture Support is provided for both on chip DMA controllers and off chip other processors and peripheral controllers bus masters For further information on this topic refer to Section 6 References on page 23 The bus can support both normal and burst cycles Burst memory cycles are used to fill on chip cache memory and for certain on chip DMA operations Normal cycles are used for all other data transfers SED1374 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 02 Iss
74. da e Wwe pwei FPSHIFT FPSHIFT P Phe SED1374 FPFRAME FPFRAME ce RD WR P RD WR LCD FPLINE FPLINE RD P RD DADY ee Display WEO P WEO WAIT WAIT LCDPWR CkIO gt BCLK RESET gt RESET SED1374 Hardware Functional Specification X26A A 001 02 Figure 3 2 Typical System Diagram SH 3 Bus Issue Date 99 04 29 Epson Research and Development Page 13 Vancouver Design Center Oscillator MC68000 BUS FCO pote B Decoder 0 gt CS a A 15 1 DP AB 15 1 D 15 0 4 P DB 15 0 rio E FPSHIFT gt FPSHIFT Los gt asor SED1374 A bit UDS gt WEI FPFRAME FPFRAME LCD aby p Es FPLINE FPLINE Display R w gt RDWR DRDY P MOD DTACK lt WAIT h LCDPWR CLK gt BCLK RESET P RESET Figure 3 3 Typical System Diagram M68K 1 Bus Oscillator MC68030 BUS roo ap EA o A 5 A 15 0 gt AB 15 0 D 31 16 k P DB 15 0 O go pee pl we FPSHIFT gt gt FPSHIFT Bes dias SED1 374 FPFRAME FPFRAME pos RIWH P RD WR LCD siz A FPLINE gt _ _ FPLINE Display sizo gt Weo DRDY mop DSACK1 d WAITH LCDPWR GLK gt BCLK RESET P RESETH Figure 3 4 Typical System Diagram M68K 2 Bus Hardware Functional Specification SED1374 Issue Date 99 0
75. ed ee a A a Ge eh ee we oe de ae A 7 65 CB xamipless ar Te 0 Sect Ay Ale Se es BA Ge ke ek Ge ye bet aga See A ate eM A2 Identifying the SED1374 22524244 6248 s eaeeeG ee eee ee ee 46 9 Hardware Abstraction Layer HAL lt lt 47 91 Introductorio a a AT Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 4 Epson Research and Development Vancouver Design Center 9 2 APT Tor 13 74HAD oe ok oe he Be dl ce eB ee ee as Be AT 9 2 1 Initialization sacs ural kre ee aa eGo A Saves We Pace darker 47 9 2 2 Miscellaneous HAL Support 20 2 0 20 00000000004 49 9 2 3 Advanced HAL Functions 2 0 2 0 a 52 9 2 4 Register Memory Access 2 0 0 ee ee 55 O 2 5 Power Save oda Gao Palas biog ap aod Ge eee pua ce a Gee 58 O20 DIA WS 34 72 Shee te eee oh nea a ee me Sub he eed be de ee See ee 58 9 2 7 LUT Manipulation pure fare died Ware Sa Sw Barba aa park Sas 59 10 Sample Code sms o bk ore alee a Sa SA ee eS 61 10 1 Introduction sti Sa cee ar Go he oe oe eh ae oe ah a a te ee ee a ae te eed oe 01 10 1 1 Sample code using the SED1374 HAL API o o 61 10 1 2 Sample code without using the SED1374 HAL API 64 10 1 3 Header FUES oe Vas OA OA Bee ade edly eae eb ad Pe ee 72 SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Vancouver De
76. ee EAE ee ele eS 21 5 24 Miscellaneous ic 5 40 ayes ae Se Ao eel KORE BORN do Baar a E a 21 9 25 Power Supply rica ti ta a a a A ae Oe AAA ad os 21 5 3 Summary of Configuration Options 22 5 4 Host Bus Interface Pin Mapping 2 22 5 5 LCD Interface Pin Mapping 2 0 0 2 23 D C Ch r cteristi s 4 cio ta a A A ee ek ee A ae 24 AG Characteristics e c Gad a Ge Se ek wl a 26 7 1 BusInterfaceTiming 2 aa ee 26 7 1 1 SH 4 Interface Timing 0 00 2000 0000000000 26 7 1 2 SH 3 Interface Timing a 600 2 pe ee ee 28 7 1 3 Motorola M68K 1 Interface Timing e 30 Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 4 10 11 12 13 14 SED1374 7 1 4 Motorola M68K 2 Interface Timing 7 1 5 7 1 6 Generic 2 Interface TiMiNg 7 2 Clock Input Requirements 7 3 Display Interface 7 3 1 Power On Reset Timing 7 3 2 Power Down Up Timing 7 3 3 Single Monochrome 4 Bit Panel Timing 7 3 4 Single Monochrome 8 Bit Panel Timing 7 3 5 Single Color 4 Bit Panel Timing 7 3 6 Single Color 8 Bit Panel Timing Format 1 7 3 7 Single Color 8 Bit Panel Timing Format 2 7 3 8 Dual Monochrome 8 Bit Panel Timing 7 3 9 Dual Color 8 Bit Panel Timing 7 3 10 9 12 Bit TFT MD TED P
77. for 2 Bpp 4 Colors Gray Shades in One Byte of Display Buffer 3 1 3 4 Bit Per Pixel 16 Colors Gray Shades Four bit pixels support 16 color gray shades In this memory format each byte of display buffer contains two adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the upper or lower nibble 4 bits and setting the appropriate bits to 1 For color panels the 16 colors are derived by indexing into the first 16 positions of the Look Up Table For monochrome panels the gray shades are generated by indexing into the first 16 elements of the green component of the Look Up Table Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 0 Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 1 Pixel 1 Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 Figure 3 3 Pixel Storage for 4 Bpp 16 Colors Gray Shades in One Byte of Display Buffer SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Page 13 Vancouver Design Center 3 1 4 Eight Bit Per Pixel 256 Colors In eight bit per pixel mode one byte of display buffer represents one pixel on the display At this color depth the read modify write cycles required by the lessor pixel depths are eliminated Each byte of display memory consists of three pointers into the Look Up Table The three most significant bits form an index into the first eight red values The next t
78. for screen 1 must be 6400 bytes 6400 bytes 3200 words C80h words Set the Screen 1 Start Word Address MSB REG ODh to OCh and the Screen 1 Start Word Address LSB REG OCh to 80h Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 33 Vancouver Design Center 3 Calculate the Screen 2 Start Word Address register values Screen 2 display data is coming from the very beginning of the display buffer All there is to do here is ensure that both the LSB and MSB of the Screen 2 Start Word Address registers are set to zero Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 34 Epson Research and Development Vancouver Design Center 6 LCD Power Sequencing and Power Save Modes 6 1 LCD Power Sequencing 6 2 Registers LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD logic signals Power sequencing is required to prevent long term damage to the panel and to avoid unsightly lines on power down and power up The SED 1374 performs automatic power sequencing when the LCD is enabled or disabled through the Power Save bits in REG 03h or in response to a hardware power save request For most applications the internal power sequencing is the appropriate choice Proper LCD power sequencing dictates there must be a time delay between the LCD power being disabled and the LCD signals being shut down During power up the LC
79. host bus interfaces that may be used to implement the interface to the MC68328 3 1 Bus Interface Modes The SED 1374 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Six bus interface modes are supported Hitachi SH 4 Hitachi SH 3 Motorola MC68000 using Upper Data Strobe Lower Data Strobe Motorola MC68020 MC68030 MC683xx using Data Strobe DSACKx Generic 1 Chip Select plus individual Read Enable Write Enable for each byte Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte The SED 1374 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping ee SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vss connect to IO Vpp RD
80. in One Byte of Display Buffer Viewport Inside a Virtual Display o o o Memory Address Offset Register o o Screen 1 Start Address Registers o o e 320x240 Single Panel For Split Screen o o Screen 1 Vertical Size i ek ed de ed a a de o Screen 2 Start Address Registers o o e Relationship Between The Screen Image and the Image Refreshed by SED1374 Relationship Between The Screen Image and the Image Refreshed by SED1374 Programming Notes and Examples Issue Date 99 04 27 Page 5 SED1374 X26A G 002 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This guide describes how to program various features of the SED1374 Embedded Memory Color LCD controller The demonstrations include descriptions of how to calculate register values and explanations of how or why you might want to do certain procedures This guide also introduces the Hardware Abstraction Layer HAL which is designed to simplify the programming of the SED1374 Most SED135x SED137x and 138x products support the HAL allowing OEMs to switch chips with relative ease Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 8 Eps
81. mode ek SET_REG 0x03 0x03 JE Register 04h Horizontal Panel Size 320 pixels 320 8 1 39 27h a SET_REG 0x04 0x27 Register 05h Vertical Panel Size LSB 240 pixels Register 06h Vertical Panel Size MSB 240 1 239 EFh SET_REG 0x05 OXEF SET_REG 0x06 0x00 Register 07h FPLINE SET_REG 0x07 0x00 Register 08h Horizontal Non Display Period SED1374 X26A G 002 02 PCLK Start Position not used by STN HNDP and VNDP are calculated to achieve the desired frame rate according to Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 67 Vancouver Design Center xx Frame Rat Ek HDP HNDP VDP VNDP SET_REG 0x08 0x1E 5 Register 09h FPFRAME Start Position not used by STN e SET_REG 0x09 0x00 Register OAh Vertical Non Display Register ER CAlculated in conjunction with register 08h HNDP to EK achieve the desired frame rate SET_REG 0x0A Ox3B Register OBh MOD Rate not used by this panel E SET_REG 0x0B 0x00 J Register OCh Screen 1 Start Word Address LSB Register ODh Screen 1 Start Word Address MSB EK Start address should be set to 0 SET_REG 0x0C 0x00 SET_REG 0x0D 0x00 Register OFh Scre
82. not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374SHOW Demonstration Program X26A B 002 01 Issue Date 98 10 20 Epson Research and Development Page 3 Vancouver Design Center 1374SHOW 1374SHOW demonstrates SED 1374 display capabilities by drawing a pattern image at different pixel depths 1 2 4 and 8 bits per pixel on the display 1374SHOW must be configured to work with each different hardware platform Consult documentation for the program 1374CFG EXE which can be used to configure 1374SHOW This software is designed to work in a variety of embedded and personal computer PC environments For embedded environments the model employed is that of host target It is assumed that the system has a means of downloading software from the host to the target platform Typically this is done by a serial communication link Alternative methods include EPROM parallel port connection or network connection It is beyond the scope of this document to provide support for target host configurations
83. products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows is a registered trademark of Microsoft Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Windows CE Display Drivers X26A E 001 01 Issue Date 98 11 11 Epson Research and Development Page 3 Vancouver Design Center 1 WINDOWS CE DISPLAY DRIVERS The Windows CE display drivers are designed to support the SED1374 Embedded Memory LCD Controller running under the Microsoft Windows CE operating system Available drivers include 4 bit per pixel landscape mode and 4 bit per pixel portrait mode For updated source code visit Epson Research and Development on the World Wide Web at www erd epson com or contact your Seiko Epson sales representative 1 1 Program Requirements Video Controller SED1374 Display Type LCD Windows Version CE Version 2 0 2 1 1 2 Example Driver Build Build For CEPC X86 Version 2 0 2 1 To build a Windows CE v2 0 2 1 display driver for the CEPC X86 platform using a SDU1374B0C evaluation board follow the instr
84. property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374SPLT Display Utility X26A B 003 01 Issue Date 98 10 20 Epson Research and Development Page 3 Vancouver Design Center 1374SPLT 1374SPLT demonstrates SED 1374 split screen capability by showing two different areas of display memory on the screen simultaneously Screen 1 memory is located at the start of the display buffer and is filled with horizontal bars Screen 2 memory is located immediately after Screen 1 in the display buffer and is filled with vertical bars On either user input or elapsed time the line compare register value is changed to adjust the amount of display area taken up by each screen 1374SPLT must be configured to work with each different hardware platform Consult documentation for the program 1374CFG EXE which can be used to configure 1374SPLT This software is designed to work with a variety of embedded and personal computer PC environments For embedded environments the model employed is that of host target It is assumed that the system has a means of downloading software from the host to the target platform Typically this is done by a serial communication link Alternative methods include EPROM parallel port connection or network connection It is beyond the scope of this document to provide support for target host configurations SED1374 Supported Evaluation Platforms
85. read as a starting point in configuring this or other files or to check on the current configuration If 1374CFG is unable locate the HAL information in the selected file the following dialog box is displayed 1374CFG ERROR Unable to locate HAL information this file is not configurable Figure 9 ERROR Unable to read HAL Save Click on the Close button to save the current configuration settings When clicked the standard Windows file Save As dialog box is displayed Save As Save in a intel ex se BH 1374BMP exe F 1374VIRT exe 1374MEM exe 1374PLAY exe 1374REG exe 1374SHOW exe 13745PLT exe Save as type Executable Files exe s9 y Cancel Figure 10 1374CFG Save As Dialog From the save as dialog box first select the type of file to save to in the Save as type edit field 1374CFG currently saves in three file formats e EXE files are binary images containing a HAL structure for execution on Intel plat forms e S9 files are ASCII binary format files used by several embedded systems The S9 file is a variation of S19 files H files are ASCII C header files which can be included in other programs SED1374 1374CFG EXE Configuration Program X26A B 001 01 Issue Date 98 10 27 Epson Research and Development Page 15 Vancouver Design Center If an executable file EXE or S9 is selected as the type of file to save to the file being saved to must alr
86. registers become offsets to bytes In this mode the step rate for the start address registers if halved making for smoother panning Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 28 5 2 1 Registers Epson Research and Development Vancouver Design Center REG 0Ch Screen 1 Display Start Address 0 LSB Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 0Dh Screen 1 Display Start Address 1 MSB r s ived Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Figure 5 3 Screen 1 Start Address Registers In landscape mode these two registers form the offset to the word in display memory to be displayed in the upper left corner of the screen Screen 1 is always the top of a display frame starting in the upper left corner and descending downward Changing these registers by one will shift the display 2 to 16 pixels depending on the current color depth In SwivelView mode these registers form the offset to the byte in display memory from where screen 1 will start displaying Changing these registers in SwivelView mode will result in a shift of 1 to 8 pixels depending on the color depth Refer to Table 5 1 Number of Pixels Panned Using Start Address to see the minimum number of pi
87. requiring more address space must use an external device to latch A 25 13 The IT8368E s MFIO pins can be configured to provide this latched address SED1374 3 3V PR31500 PR31700 10 Vpp CORE Vpn HA 12 0 AB 12 0 ENDIAN 1 gt AB 15 13 HD 31 24 DB 7 0 HD 23 16 4 gt DB 15 8 a System RESET gt RESET DD pull up CARDXWAIT e WAIT DCLKOUT See text i gt CLKI LHA 23 MFIO 10 gt WE1 LHA 22 MFIO 9 WEO LHA 21 MFIO 8 gt RD1 LHA 20 MFIO 7 gt RDO LHA 19 MFIO 6 CS LHA 15 13 MFIO 2 0 sli Ber Figure 3 1 SED1374 to PR31500 PR31700 Connection Using an IT8368E SED1374 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 01 Issue Date 98 11 09 EPSON Research and Development Page 11 Vancouver Design Center The Generic 1 host interface control signals of the SED1374 are asynchronous with respect to the SED1374 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum SED1374 clock frequencies The SED1374 also has internal clock dividers providing additional flexibility
88. the expense of performance or as with the SED1374 it can be done by hardware with no CPU penalty There are two SwivelView modes Default SwivelView and Alternate Swivel View 12 1 Default Swivel View Mode Default Swivel View Mode requires the portrait image width be a power of two e g a 240 line panel requires a minimum virtual image width of 256 This mode should be used whenever the required virtual image can be contained within the integrated display buffer i e virtual image size lt 40k bytes as it consumes less power than the Alternate SwivelView mode For example the panel size is 320x240 and the display mode is 4 bit per pixel The virtual image size is 320x256 which can be contained within the 40k Byte display buffer Default Swivel View Mode also requires memory clock MCLK gt pixel clock PCLK The following figure shows how the programmer sees a 240x320 image and how the image is displayed The application image is written to the SED1374 in the following sense A B C D The display is refreshed by the SED1374 in the following sense B D A C physical 320 memory start Se lt address A 256 gt A B E WW A SwivelView m z a co window A os A display gt 0 o start o g A address 5 lt o o Q D b 320 240 1 image seen by programmer image refreshed by SED1374 image in display buffer Figure 12 1 Relationship Between The Screen Image and t
89. these two types of panels A positive power supply for panels requiring a positive bias voltage is supplied to header J4 by the LCD module through the 50 pin LCD module connector J3 No negative power supply is available on the LCD module therefore only panels which have their own bias voltage supply or those that use a positive supply can be connected to J4 The LCD module can only support these panels as well Header J4 and its associated buffers and components have been left unpopulated on the CPU module These parts can be added by the user if desired 4 3 LCD Controller 4 3 1 SED1374 vs SED1375 The LCD controller used in conjunction with the TMPR3912 22U microprocessor can either be a SED1374 or aSED1375 If a SED1374 is used jumper JP7 must be set to position 1 2 This setting allows CNF4 to be configured for the SED1374 CNF4 controls the polarity of the LCDPWR signal and can be set either high or low with jumper JP11 If a SED1375 is used jumper JP7 must be set to position 2 3 This setting allows pin 45 of the LCDC to be used as address bit AB16 which is needed on the SED 1375 to accom modate the larger display memory 4 3 2 LCDPWR Polarity The power supply on the LCD module used LCDON an active low signal to turn on the supply This signal is connected to LCDPWR Since LCDPWR is configurable on the SED1374 and is set active high on the SED1375 a facility must be provided to invert this signal if it is active high s
90. this example implementation the SED 1374 occupies the PR31500 PR31700 PC Card slot 1 The SED 1374 is easily interfaced to the PR31500 PR31700 with minimal additional logic The address bus of the PR31500 PR31700 PC Card interface is multiplexed and can be demultiplexed using an advanced CMOS latch e g 74 ACT373 The direct connection approach makes use of the SED1374 in its Generic Interface 2 configuration The following diagram demonstrates a typical implementation of the interface SED1374 X26A G 012 01 SED1374 3 3V PR31500 PR31700 t IO Vpp CORE Vpp RD RD WE WE CARD1CSL CARD1CSH BHE IO Voor RD WR ENDIAN System RESET gt RESET Latch A ALE gt PES A 12 0 i gt AB 15 13 AB 12 0 D 31 24 gt DB 7 0 D 23 16 gt DB 15 8 Von pull up CARD1WAIT 4 WAIT DCLKOUT See text CLKI gt gt Clock divider gt 2 Oscillator y BOLK Figure 2 1 SED1374 to PR31500 PR31700 Direct Connection The Generic 2 host interface control signals of the SED1374 are asynchronous with respect to the SED1374 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desi
91. time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host bus interface offers more flexibility in configuring the SED1374 with other CPUs For details on configuration refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx 3 2 Generic 1 Host Bus Interface Mode SED1374 X26A G 010 02 Generic 1 host bus interface mode is the most general and least processor specific host bus interface mode on the SED1374 The Generic 1 host bus interface mode was chosen for this interface due to the simplicity of its timing The host bus interface requires the following signals e BUSCLK is a clock input which is required by the SED1374 host interface It is separate from the input clock CLKI and is typically driven by the host CPU system clock e The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset e Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space e
92. to be driven low when the host CPU is reading or writing data to the SED1374 These must be generated by external decode hardware based upon the control outputs from the host CPU RD WRF is the read write signal that is driven low when the CPU writes to the SED1374 and is driven high when the CPU is doing a read from the SED1374 This signal must be generated by external decode hardware based upon the control output from the host CPU WAIT is a signal which is output from the SED1374 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1374 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1374 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS signal indicates that the address on the address bus is valid This signal must be generated by external decode hardware based upon the control outputs from the host CPU The WEO signal is not used in the bus interface for MC68K 1 and must be tied high tied to IO Vpp Interfacing to the Motorola MC68328 Dragonball Microprocessor SED1374 Issue Date 99 01 05 X26A G 007 02 Page 12 4 MC68328 To SED1374 Interface 4 1 Hardware Description Epson Research and Development Vancouver Design Center The interface betwe
93. to lO Vpp RD WR RD WR RD WR R W R W RD1 connect to lO Vpp RD RD RD connect to lO Vpp SIZ1 RDO RD WE0 WE0 WE0 connect to lO Vpp SIZO WEO0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET SED1374 Interfacing to the NEC VR4102 Microprocessor X26A G 008 04 Issue Date 99 01 05 Epson Research and Development Page 11 Vancouver Design Center Two other configuration options CNF 4 3 are also made at time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host bus interface offers more flexibility in configuring the SED1374 with other CPUs For details on configuration refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx 3 2 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the SED1374 The Generic 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the VR4102 control signals The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the SED1374 It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU ad
94. 002 02 Page 20 Color Modes SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center 1 Bpp Color When the SED1374 is configured for 1 bit per pixel color mode only the first two colors from the active bank are displayed The two entries can be set to any color but are typically set to black and white Each byte in the display buffer contains 8 bits each bit represents an individual pixel A bit value of 0 results in the Look Up Table 0 value being displayed A bit set to 1 results in the Look Up Table index 1 value displayed The following table shows the recommended values for 1 bpp on a color panel Table 4 5 Recommended LUT Values for 1 Bpp Color Mode Index Red Green Blue 00 00 00 00 01 OF OF OF 02 OF Normally unused entries 2 Bpp Color When the SED1374 is configured for 2 bit per pixel color mode only the first four colors from the active bank are displayed The four entries can be set to any color Each byte in the display buffer contains 4 adjacent pixels Each pair of bits in the byte are used as an index into the LUT The following table shows example values for 2 bpp color mode Table 4 6 LUT Values for 2 Bpp Color Mode Index Red Green Blue 00 00 00 OF 01 OF 00 00 02 00 OF 00 03 OF OF OF 04 OF Normally unused entries Programming Notes and Examples Issue Date
95. 02 The MC68328 can generate up to 16 chip select outputs organized into four groups A through D Each chip select group has a common base address register and address mask register to set the base address and block size of the entire group In addition each chip select within a group has its own address compare and address mask register to activate the chip select for a subset of the group s address block Finally each chip select may be individually programmed to control an 8 or 16 bit device and each may be individually programmed to generate from 0 through 6 wait states internally or allow the memory or peripheral device to terminate the cycle externally through use of the standard MC68000 DTACK signal Groups A and B can have a minimum block size of 64K bytes so these are typically used to control memory devices Chip select AO is active immediately after reset so it is typically used to control a boot EPROM device Groups C and D have a minimum block size of 4K bytes so they are well suited to controlling peripheral devices Chip select D3 is associated with the MC68328 on chip PCMCIA control logic Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 99 01 05 Epson Research and Development Vancouver Design Center 3 SED1374 Host Bus Interface Page 9 This section is a summary of the host bus interface modes available on the SED1374 and offers some detail on the Generic 1 and MC68K 1
96. 1 93mW 25 72mW 3 09mW 2 71mW Input Clock 25MHz 7 LCD Panel 640x480 9 bit TFT 2 Colors 16 48mW 8 07mW 24 55mW 3 09mw 2 71mW Note 1 Conditions for Software Power Save e CPU interface active signals toggling e CLKI active 2 Conditions for Hardware Power Save e CPU interface inactive high impedance e CLKI active SED1374 Power Consumption X26A G 006 01 Issue Date 98 10 27 Epson Research and Development Page 5 Vancouver Design Center 2 Summary Power Consumption Issue Date 98 10 27 The system design variables in Section 1 SED1374 Power Consumption and in Table 1 1 SED 1374 Total Power Consumption show that SED 1374 power consumption depends on the specific implementation Active Mode power consumption depends on the desired CPU perfor mance and LCD frame rate whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state In a typical design environment the SED1374 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility SED1374 X26A G 006 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Power Consumption X26A G 006 01 Issue Date 98 10 27 EPSON SED1374 Embedded Memory Color LCD Controller Interfacing to the Motorola MC68328 Dragonball Microprocessor Document Number X26A G 007 02 Copyright 1998 1999 Epson Research and Development Inc All
97. 1 Microprocessor SED1374 Issue Date 99 01 05 X26A G 010 02 Page 18 4 3 SED1374 Hardware Configuration Epson Research and Development Vancouver Design Center The SED 1374 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx for details The tables below show only those configuration settings important to the MPC821 interface The settings are very similar to the ISA bus with the following exceptions e the WAIT signal is active high rather than active low e the Power PC is big endian rather than little endian Table 4 2 Configuration Settings Signal Low High CNFO CNF1 CNF2 See Host Bus Selection table below CNF3 Little Endian CNF4 Active low LCDPWR signal See Host Bus Selection table below Active high LCDPWR signal se configuration for MPC821 host bus interface Table 4 3 Host Bus Selection CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 X SH 4 interface 0 0 1 X SH 3 interface 0 1 0 X reserved 0 1 1 X MC68K 1 16 bit 1 0 0 X reserved 1 0 1 X MC68K 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 Generic 2 16 bit configuration for MPC821 host bus interface SED1374 X26A G 010 02 Interfacing to the Motorola MPC821 Micro
98. 11 3 1 Display Buffer Location wo se A a o MA 3 1 1 1 Bit Per Pixel 2 Colors Gray Shades iD ip siaaa tataa DA el rr dad 11 3 1 2 2 Bit Per Pixel 4 Colors Gray Shades o e 12 3 1 3 4 Bit Per Pixel 16 Colors Gray Shades o o a 12 3 1 4 Eight Bit Per Pixel 256 Colors o o e e 13 4 Look Up Table CUT ci a ee eee ee ae ht 14 4 1 Look Up Table Registers Ds Seen A ete hy oe os St ge dete A 4 2 Look Up Table LUT iaa AR e ee a Pa y HO 5 Advanced Techniques o 4 25 Sil Virtual Display oes a a a A a ey Sy AS SEE A O 26 LD Examples 2 a AR NE A A AS 26 5 2 Panning and Scrolling ee 2 S221 RESISTENS ste a A A Di Ad e 28 5 22 Examples ii et Ye A A AS PR A a E 28 S3 PESTE es y a oe a a a A A AA 30 A AAA A O a hrade 31 9 332 LEXAMPLES ii A A AL eS 32 6 LCD Power Sequencing and Power Save ModeS 34 6 1 LCD PowerSequencing 34 6 2 Registers A rin cic Oe ata A ii ie ay nl is OA 6 5 ECD Enable Disable i s te cas ar e a a a we a ee ea BS de SWivelView a AAA TADA AAA 36 7 1 Introduction To SwivelView eee ee ee ee ee 36 7 2 Default SwivelView Mode 0 0 6 424644 36 7 3 Alternate SwivelView Mode 2 1 ee ee 37 TA RESIS ETS wok dir o ch AOR te Wow ee Boe At ee ah a BO CES O ue a lt a sae te Eo
99. 1374 X26A A 001 02 Page 36 Epson Research and Development Vancouver Design Center 7 3 2 Power Down Up Timing LCDPWR Override REG 03h bit 3 HW Power Save or Software Power Save REG O3h bits 1 0 11 00 11 00 11 E t1 t2 FP Signals Active Inactive Active Inactive Active 13 gt t4 e t5 t6 gt t7 _ LCDPWR Active Inactive Active a Inactive Active polarity set by CNF4 Figure 7 9 Power Down Up Timing Table 7 8 Power Down Up Timing Symbol Parameter Min Typ Max Units u HW Power Save active to FPLINE FPFRAME FPSHIFT FPDAT DRDY 4 patie inactive LCDPWR Override 1 2 HW Power Save inactive to FPLINE FPFRAME FPSHIFT FPDAT DRDY 4 Frame active LCDPWR Override 1 13 HW Power Save active to FPLINE FPFRAME FPSHIFT FPDAT DRDY 4 Frame inactive LCDPWR Override 0 t4 LCDPWR low to FPLINE FPFRAME FPSHIFT FPDAT DRDY inactive 127 Frame LCDPWR Override 0 5 HW Power Save inactive to FPLINE FPFRAME FPSHIFT FPDAT DRDY 0 oe LCDPWR active LCDPWR Override 0 t6 LCDPWR Override active 1 to LCDPWR inactive 1 Frame t7 LCDPWR Override inactive 1 to LCDPWR active 1 Frame SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page
100. 1374 X26A G 002 02 Epson Research and Development Vancouver Design Center Plugging the values into the frame rate calculations yields R ENA PCLK ramesate HDP HNDP x VDP VNDP 16 000 000 FrameRate cA A 80 69 320 88 x 240 3 For this example the Horizontal Non Display register REG 08h needs to be set to 07h and the Vertical Non Display register REG OAh needs to be set to 03h The 16 000 000 2 in the formula above represents the input clock being divided by two when this alternate Swivel View mode is selected With the values given for this example we must ensure the Input Clock Divide bit REG 02h b4 is reset with the given values it was likely set as a result of the frame rate calculations for landscape display mode No other registers need to be altered The display is now configured for SwivelView mode use Offset zero of display memory corresponds to the upper left corner of the display Display memory is accessed exactly as it was for landscape mode As this is the alternate Swivel View mode the power of two stride issue encountered with the default SwivelView mode is no longer an issue The stride is the same as the SwivelView mode width In this case 120 bytes Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 45 Vancouver Design Center Example 8 Pan the above SwivelView mode image to the right by 4 pixels then scroll it up by 6 pixels To pan by fo
101. 1374 is powered down when this option is selected This option is only applicable for monochrome displays If a color panel is selected this option is disabled When the lookup table is not enabled then display intensities are dependent on the values in the lookup table A smaller numerical value in display memory may be displayed with a greater intensity than a larger value When the lookup table is bypassed the colors displayed on the panel are directly propor tional to their memory value i e at 4 bit per pixel 00h will display as black and OFh will display as full intensity Open Click on the Open button to read the settings saved in an executable program based on the SED1374 hardware abstraction layer Clicking the Open button brings up the standard Windows file open dialog Open Look in E Cd_rom D c iit 1374Cfg exe intel Fie pame Files of type Executable Files exe s9 y Cancel Figure 8 1374CFG File Open Dialog From here the user selects the file to be opened 1374CFG is capable of opening executable files based on the SED1374 HAL Typically the file extension for these file are EXE for intel platform executables and S9 for 68k and SH3 platform executables 1374CFG EXE Configuration Program SED1374 Issue Date 98 10 27 X26A B 001 01 Page 14 Epson Research and Development Vancouver Design Center Opening a file reads that files HAL configuration information Use the data
102. 26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center 5 Pins 5 1 Pinout Diagram Page 17 Figure 5 1 Pinout Diagram Note Package type 80 pin surface mount QFP14 Hardware Functional Specification Issue Date 99 04 29 6d 59 58 57 5 59 54 53 52 51 50 49 48 47 49 49 44 493 42 41 lt Z gt DDDDODDOSOS o OoO lt QOQ0Q0Q0Q00HRF00 QRamannngnergezzzzzZ2ngao0 e oanonage SISA 2pA 23 Uy 61 i 40 ST COREVDD vss H 2 ABg FPFRAME 63 any FPLINE 8 EA FPDATO 65 aps FPDAT1 Pa 86 AB4 FPDAT2 LS 87 aps FPDAT3 4 68 33 2 AB2 FPDAT4 H 69 32 AB1 FPDATS Fay ABO FPDAT6 30 1 BCLK SED1374 FPDAT7 Ho a IOVDD E 74 RESET FPSHIFT ES 21 cs vss HS 2 Bs FPDAT8 Z8 aoe FPDAT9 2 gt A WEO FPDATIO 24 78 Wer FPDATI1 2S P RDwR GPIoo 2 80 21 vss o COREVDD O mg UUUUUOU o lt gt lt lt SILLON DORIA O FO_ARAON Oo00o UOXNXOoUumn_ 0MNnN 0Oo0 E E la E ie 7 E o hof jizhalahisheli7lts 19 20 SED1374 X26A A 001 02 Page 18 Epson Research and Development Vancouver Design Center 5 2 Pin Description Key CS COx TSx TSxD CNx Input Output Bi Directional Input Output Power pin CMOS level input CMOS level input with pull down resistor typical values of 100KQ 180KQ at 5V 3 3V respectively CMOS level Schmitt input CMOS output driver x denotes driver type 1 3 1 5mA 2 6 3mA 3 12
103. 3 1 Panel On Off Sequence After chip reset LCDPWR is inactive and the rest of the panel interface output signals are held low Software initializes the chip i e programs the registers and then as a last step set programs REG 03h bits 1 0 to 11 This starts the power up sequence as shown The power up power down sequence delay is 127 frames The power up power down sequence also occurs when exiting entering Software Power Save Mode BCLK may be turned off held low between accesses if the following rules are observed 1 BCLK must be turned off on in a glitch free manner 2 BCLK must continue for a period equal to 8Tgc K 12TycLk after the end of the access RD Y asserted or WAIT deasserted 3 BCLK must be present for at least one Tc k before the start of an access Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Vancouver Design Center 13 6 Clock Requirements Page 87 The following table shows what clock is required for which function in the SED1374 Table 13 5 SED1374 Internal Clock Requirements Function BCLK CLKI Register Read Write Is required during register accesses BCLK can be shut down between accesses allow eight BCLK pulses plus 12 MCLK pulses 8Tgc k 12 Tuck after the last access before shutting BCLK off Allow one BCLK pulse after starting up BCLK before the next access Not Required Memory Read Write Is required
104. 374 Interfacing to the NEC VR4102 Microprocessor X26A G 008 04 Issue Date 99 01 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 10 Table 4 1 Summary of Power On Reset Opti0MS o o 14 Table 4 2 Host Bus Selection 2 2 dasa tae Pal a ana a e E a eu ata hey uoaa ard a 14 List of Figures Figure 2 1 NEC VR4102 Read Write Cycles oaoa a 9 Figure 4 1 Typical Implementation of VR4102 to SED1374 Interface 13 Interfacing to the NEC VR4102 Microprocessor SED1374 Issue Date 99 01 05 X26A G 008 04 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the NEC VR4102 Microprocessor X26A G 008 04 Issue Date 99 01 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to provide an interface between the SED1374 Embedded Memory LCD Controller and the NEC Vr4102 Microprocessor uPD30102 The NEC Vr4102 Microprocessor is specifically designed to support an external LCD controller and the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be u
105. 3912 22U s PC Card slot 1 Therefore this slot cannot be used for other devices on the main board The Generic 2 bus mode of the SED 1374 75 is used to interface to this PC Card slot 1 The SED1374 75 is interfaced to the TMPR3912 22U with minimal glue logic Since the address bus of the TMPR3912 22U is multiplexed it is demultiplexed using an advanced CMOS latch 74ACT373 to obtain the higher address bits needed for the SED1374 75 The following diagram demonstrates the implementation of the interface SED1374 3 3V TMPR3912 22U 10 Vpp CORE Vpp RD gt RD WE WE10 CARD1CSL CARD1CSH WE1 3 3V 1__ psy 3 3V ___ RD WR ENDIAN System RESET RESET Latch FA ALE gt CS A 12 0 gt AB 15 13 gt AB 12 0 D 31 24 4 gt DBI7 0 D 23 16 gt DB 15 8 3 3V 10k pull up CARD1WAIT e WAIT DCLKOUT Clock divider or Oscillator CLKI L Clock divider 12 BUSCLK y X00A G 004 01 Figure 3 1 SED1374 to TMPR3912 22U Interface SDU1374 75 TMPR3912 22U CPU Module Issue Date 98 12 23 EPSON Research and Development Page 11 Vancouver Design Center 3 2 Memory Mapping and Aliasing The SED1374 requires an addressing space of 64K bytes while the SED1375 requires 128K The on chip display memory occupies the range 0 through 9FFFh The registers occu
106. 4 1 1 Using The MC68K 1 Host Bus Interface o o 12 4 1 2 Using The Generic 1 Host Bus Interface o 13 4 2 SED1374 Hardware Configuration 14 4 3 MC68328 Chip Select Configuration 14 Software a a Mb oe ap eee a ae ane ara are 15 Referentes oe Si ela E e ars aa eg et alee Ee he decid fae e 16 Hb Doctimentss a 4 ek ee A Ae ba Se oh a Eee eee cee he a TO 6 2 DocumentSources o 16 7 Technical Support 0 e e ee a a eos 17 7 1 EPSON LCD Controllers SED1374 a TT 7 2 Motorola MC68328 Processor 2 ee ee ee ee 17 Interfacing to the Motorola MC68328 Dragonball Microprocessor SED1374 Issue Date 99 01 05 X26A G 007 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 02 Issue Date 99 01 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2 2 020000000 2 eee 9 Table 4 1 Summary of Power On Reset Options e 14 Table 4 2 Host Bus Interface Selection o o a 14 List of Figures Figure 4 1 Typical Implementation of MC68328 to SED1374 Interface MC68K 1 12 Figure 4 2 Typical Implementation of MC68328 to SED1374 Interface Generic 1 13 Inter
107. 4 29 X26A A 001 02 Page 14 Epson Research and Development Vancouver Design Center Oscillator CLKI GENERIC 1 oo BUS 3 CSn D cs A 15 0 gt gt AB 15 0 D 15 0 DB 15 0 Neale P PBS FPDAT 1 1 0 gt 11 0 FPSHIFT gt _ FPSHIFT WEO P WEO SED1 374 12 bit ER P wets FPFRAME FPFRAME TFT Aboi RD FPLINE gt FPLINE Display RD1 P RD WR Po gt DADY WAIT 4 WAIT LCDPWR BCLK gt BCLK RESET P RESET Figure 3 5 Typical System Diagram Generic 1 Bus Oscillator cLKI BS ISA REFRESH p BUS sar19 16 p Decoder D p cst SA 15 0 B AB 15 0 SD 15 0 iole Py PBLS FPDAT 8 0 __ 78 0 SMEMW gt WEO FPSHIFT _ FPSHIFT SMEMR gt RD SED1374 9 bit FPFRAME gt FPFRAME TFT SBHE P WE1 FPLINE FPLINE Display DRDY prpy IOCHRDY ie WAIT Al LCDPWR BCLK bp BCLK RESET Do P RESET Figure 3 6 Typical System Diagram Generic 2 Bus e g ISA Bus SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 15 Vancouver Design Center 4 Functional Block Diagram 20k x 16 bit SRAM j Memory Power Save Regis
108. 5 Epson Research and Development Vancouver Design Center Table of Contents INTRODUCTION SED1374 Embedded Memory Color LCD Controller Product Brief SPECIFICATION SED1374 Hardware Functional Specification PROGRAMMER S REFERENCE SED 1374 Programming Notes and Examples SED 1374 Register Summary UTILITIES 1374CFG EXE File Configuration Program 1374SHOW Demonstration Program 1374SPLT Display Utility 1374VIRT Display Utility 1374PLAY Diagnostic Utility 1374BMP Demonstration Program 1374PWR Power Save Utility DRIVERS SED1374 Windows CE Display Drivers EVALUATION SDU1374B0C Rev 1 ISA Bus Evaluation Board User Manual APPLICATION NOTES Interfacing to the Toshiba MIPS TX3912 Processor Power Consumption Interfacing to the Motorola MC68328 Microprocessor Interfacing to the NEC VR4102 Microprocessor Interfacing the SED1374 to the PC Card Bus Interfacing to the Motorola MPC821 Microprocessor Interfacing to the Motorola MCF5307 Microprocessor Interfacing to the Philips MIPS PR31500 PR31700 Processor SDU1374 75 TMPR3912 22U CPU Module Interfacing to an 8 Bit Processor TECHNICAL MANUAL Issue Date 99 05 05 Page 5 SED1374 X26A Q 001 04 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 TECHNICAL MANUAL X26A Q 001 04 Issue Date 99 05 05 EPSON amp GRAPHICS SED1374 October 1998 SED1374 EMBEDDED MEMORY COLOR LCD CONTROLLER mM DESCRIPTION The SED13
109. 5 The interface between the SED1374 and the MPC821 requires minimal glue logic One inverter is required to change the polarity of the WAIT signal an active low signal to insert wait states in the bus cycle The MPC821 Transfer Acknowledge signal TA is an active low signal which ends the current bus cycle The inverter is enabled using CS so that TA is not driven by the SED1374 during non SED1374 bus cycles A single resistor is used to speed up the rise time of the WAIT TA signal when terminating the bus cycle BS bus start is not used in this implementation and should be tied low connected to GND The following diagram shows a typical implementation of the MPC821 to SED1374 interface MPC821 A 16 31 D 0 15 CS4 470 SYSCLK RESET SED1374 AB15 ABO DB 15 D0 CS WAIT WE1 WEO RD WR RD BUSCLK RESET Figure 4 1 Typical Implementation of MPC821 to SED1374 Interface Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 01 05 SED1374 X26A G 010 02 Page 16 4 2 Hardware Connections SED1374 X26A G 010 02 Epson Research and Development Vancouver Design Center The following table details the connections between the pins and signals of the MPC821 and the SED 1374 Table 4 1 List of Connections from MPC821ADS to SED1374 MPC821 Signal Name MPC821ADS Connector and Pin Name
110. 68328 Dragonball Microprocessor Issue Date 99 01 05 Page 17 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1374 X26A G 007 02 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 02 Issue Date 99 01 05 EPSON SED1374 Embedded Memory Color LCD Controller Interfacing to the NEC VR4102 Microprocessor Document Number X26A G 008 04 Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your ownuse in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Ce
111. 6mA Tri state CMOS output driver x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA Tri state CMOS output driver with pull down resistor typical values of 100KQ 180KQ at 5V 3 3V respectively x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA CMOS low noise output driver x denotes driver type 1 3 1 5mA 2 6 3mA 3 12 6mA 5 2 1 Host Interface p RESET ee Pin Names Type Pin Cell State Description This pin has multiple functions e For SH 3 SH 4 mode this pin inputs system address bit O AO For MC68K 1 this pin inputs the lower data strobe LDS ABO l 70 CS Input e For MC68K 2 this pin inputs system address bit O AO For Generic 1 this pin inputs system address bit 0 AO For Generic 2 this pin inputs system address bit 0 AO See Host Bus Interface Pin Mapping for summary 53 54 55 56 57 58 oe AB 15 1 59 62 63 c Input Pee input the system address bits 15 through 1 64 65 66 ae 67 68 69 These pins have multiple functions e For SH 3 SH 4 mode these pins are connected to D15 0 a o For MC68K 1 these pins are connected to D 15 0 PA High For MC68K 2 these pins are connected to D 31 16 for DB 15 0 VO 18518 19 CAS2 1 inedance a 32 bit device e g MC68030 or D 15 0 for a 16 bit 16 vA 18 device e g MC68340 For Generic 1 these pins are connected to D 15 0 For Generic 2 these pins are connected to D
112. 70 210 170 2 TRUE Done exit 0 Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 64 Epson Research and Development Vancouver Design Center 10 1 2 Sample code without using the SED1374 HAL API This second sample demonstrates exactly the same sequence as the first howerver the HAL is not used all manipulation is done by manually adjusting the registers SAMPLE2 C Sample code demonstating a direct access of the SED1374 Created 1998 Vancouver Design Centre Copyright c 1998 Epson Research and Development Inc All Rights Reserved The sample code using direct SED1374 access will configure for the following 320x240 Single Color 8 bit STN High Performance enabled Notes format 2 4 bpp 70 Hz Frame Rate 25 MHz CLKi 1 This code is pseudo C code intended to show technique d It is assumed that pointers can access the relevant memory addresses 2 Register setup is done with discreet writes rather than being table KR driven This allows for clearer commenting It is more efficient to RA loop through the array writing each element to a control register 3 The array of register values as produced by 1374CFG EXE is included ER here I used the values directly rather than refer to the register EN array in the sample code kk kk include lt conio
113. 74 is a color monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer The high integration of the SED1374 provides a low cost low power single chip solution to meet the requirements of embedded markets such as Office Automation equipment Mobile Communications devices and Hand Held PCs where board size and battery life are major concerns Products requiring a Portrait display can take advantage of the Hardware Portrait Mode feature of the SED1374 Virtual and Split Screen are just some of the display modes supported The above features combined with the Operating System independence of the SED1374 make it the ideal solution for a wide variety of applications E FEATURES Memory Interface e Embedded 40K byte SRAM display buffer CPU Interface e Direct support of the following interfaces Hitachi SH 3 Hitachi SH 4 Motorola M68K MPU bus interface with programmable READY e Direct memory mapping of internal registers e CPU write buffer Display Support e 4 8 bit monochrome LCD interface e 4 8 bit color LCD interface e 16 bit color LCD interface with minimal external curcuitry e Single panel single drive passive displays e Dual panel dual drive passive displays e Active Matrix TFT TFD interface e Example resolutions 640x480 at a color depth of 1 bpp 640x240 at a color depth of 2 bpp 320x240 at a color depth of 4 bpp 240x160 at a color depth of 8 bpp Clock Source e Single c
114. 74 to accommodate the need for power reduction in the hand held devices market These modes are enabled as follows Table 13 1 Power Save Mode Selection Hardware Power Software Power Software Power Save Save Bit 1 Save Bit 0 Not Configured or 0 Mode Software Power Save Mode Not Configured or 0 reserved 0 0 Not Configured or 0 1 1 X reserved Not Configured or 0 Normal Operation x oj o Hardware Power Save Mode Configured and 1 13 1 Software Power Save Mode Software Power Save Mode saves power by powering down the panel and stopping display refresh accesses to the display buffer Table 13 2 Software Power Save Mode Summary e Registers read write accessible e Memory read write accessible LCD outputs are forced low 13 2 Hardware Power Save Mode Hardware Power Save Mode saves power by powering down the panel stopping accesses to the display buffer and registers and disabling the Host Bus Interface Table 13 3 Hardware Power Save Mode Summary e Host Interface not accessible e Memory read write not accessible LCD outputs are forced low SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 85 Vancouver Design Center 13 3 Power Save Mode Function Summary Table 13 4 Power Save Mode Function Summary Hardware Software Norm
115. 98 10 26 Epson Research and Development Page 15 Vancouver Design Center 6 2 Non ISA Bus Support The SDU1374B0C board is specifically designed to support the standard 16 bit ISA bus however the SED1374 directly supports many other host bus interfaces Header strips H1 and H2 are provided and contain all the necessary IO pins to interface to these host buses See CPU Bus Interface Connector Pinouts on page 11 Table 2 1 Configuration DIP Switch Settings on page 8 and Table 2 3 Jumper Settings on page 9 for details When using the header strips to provide the bus interface observe the following All IO signals on the ISA bus card edge must be isolated from the ISA bus do not plug the card into a computer Voltage lines are provided on the header strips U7 a TIBPAL16L8 15 PAL is currently used to provide the SED1374 CS pin 74 RESET pin 73 and other decode logic signals for ISA bus use This functionality must now be provided externally remove the PAL from its socket to eliminate conflicts resulting from two different outputs driving the same input Refer to Table 5 1 Host Bus Interface Pin Mapping for connection details Note When using a 3 3V host bus interface IOVDD must be set to 3 3V by setting jumper JP1 to the 2 3 position Refer to Table 2 3 Jumper Settings on page 9 6 3 Embedded Memory Support The SED 1374 contains 40K bytes of 16 bit SRAM used for the display buffer The SRAM sta
116. 99 04 27 Epson Research and Development Vancouver Design Center 4 Bpp Color Page 21 When the SED1374 is configured for 4 bit per pixel operation all sixteen Look Up Table entries are used Each byte in the display buffer contains two adjacent pixels The upper and lower nibbles of the byte are used as indices into the LUT The following table shows LUT values that simulate those of a VGA operating in 16 color mode Table 4 7 Suggested LUT Values to Simulate VGA Default 16 Color Palette Index Red Green Blue 00 00 00 00 01 00 00 0A 02 00 0A 00 03 00 0A 0A 04 0A 00 00 05 0A 00 0A 06 OA 0A 00 07 0A 0A 0A 08 00 00 00 09 00 00 OF 0A 00 OF 00 0B 00 OF OF 0C OF 00 00 0D OF 00 OF OE OF OF 00 OF OF OF OF Programming Notes and Examples Issue Date 99 04 27 SED1374 X26A G 002 02 Page 22 SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center 8 Bpp Color When the SED1374 is configured for 8 bit per pixel color mode 8 colors from red and green and 4 colors from the blue active banks are displayed The eight red eight green and four blue entries can be set to any color The SED1374 LUT has four bits 16 levels of intensity control per primary color while a standard VGA RAMDAC has six bits 64 levels This four to one difference has to be considered when attempting to match colors between a VGA RAMDAC and
117. A ONG ELONG 1 T o hi Long WORD TRUI TRU d E FAL FAL Y OFF 0 ON SCR SCRI T EN1 1 EN22 Consta Kf define nts for HW rotate support EFAULTO define define PO ifndef NULL ifdef __ define N else define endif endif N void 0 lo WORD hi lt lt 8 lo DWORD WORD hi lt lt 16 xk F SIZE SIZI SIZE ERSION is the size of the versi TATUS is the size of the statu EVISION is the size of the statu x k E _V PD _R k k xy defi defi defi F ne SIZE ne SIZE ne SIZE ifdef i ERSION5 TATUS 2 EVISION3 DPE Debug_printf PF exp printf texp n PF1 exp exp sn PF2 expl printf expl PFL exp V S _R F ENABLE D Af define define printf define exp2 D D define D printf exp xin else U defi defi defi endif void void PF exp PF1 exp PFL exp U 0 0 0 o void on string eg 1 00 eg b for beta s revision string eg 00 s string exp exp2 exp Sd n expl exp2 SED1374 Programming Notes and Examples Issue Date 99 04 27 X26A G 002 02 Page 74 Epson Research and Development
118. ACKx e Generic 1 Chip Select plus individual Read Enable Write Enable for each byte e Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte The SED 1374 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After releasing reset the host bus interface signals assume their selected configuration The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping teehee SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vgg connect to IO Vpp RD WR RD WR RD WR R W R W RD1 connect to lO Vpp RDA RDA RDA connect to lO Vpp SIZ1 RDO RD WEO WEO0 WE0 connect to lO Vpp SIZO WE0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET Interfacing to the Motorola MPC821 Microprocessor SED1374 Issue Date 99 01 05 X26A G 010 02 Page 14 Epson Research and Development Vancouver Design Center Two other configuration options CNF 4 3 are also made at
119. D signals must be active prior to or when power is applied to the LCD The time intervals vary depending on the power supply design One frame after a power save mode has been enabled the SED1374 disables LCD power One hundred and twenty seven frames later the LCD logic signals are disabled There may be situations where the internal time delay is insufficient to discharge the LCD power supply before the LCD signals are shut down This section details the sequences to manually power up and power down the LCD interface During the power up sequence the LCD power should not be applied before the LCD logic signals Usually the power and logic can begin at the same time There may be times when the LCD logic signals must begin before LCD power is applied REG 03h Mode Register 2 LCDPWR Hardware Software Software Override Power Save Power Save Power Save Enable bit 1 bit O SED1374 X26A G 002 02 The LCD Power LCDPWR Override bit forces LCD power to inactive one frame after being toggled The LCD logic signals to the panel are still active and are controlled by enabling or disabling a power save mode After enabling a power save mode there are still 128 frames before LCD logic signals are disabled The Hardware Power Save Enable bit must be set in order for a hardware power save request on GPIOO to have any affect Without enabling this bit toggling GPIOO will have no power save effect The Software
120. D1374 X26A G 013 01 The SED 1374 needs a 64K byte block of memory to accommodate its 40K byte display buffer and its 32 byte register set The starting memory address is located at 0000h of the 64K byte memory block while the internal registers are located in the upper 32 bytes of this memory block i e REG O FFEOh An external decoder can be used to decode the address lines and generate a chip select for the SED1374 whenever the selected 64K byte memory block is accessed If the processor supports a general chip select module its internal registers can be programmed to generate a chip select for the SED1374 whenever the SED1374 memory block is accessed Interfacing to an 8 bit Processor Issue Date 99 05 04 Epson Research and Development Page 13 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1374 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1374CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1374 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to an 8 bit Processor SED1374 Issue Date 99 05 04
121. Design Center Table 4 11 Suggested LUT Values for 4 Bpp Gray Shade Index Red Green Blue 00 01 02 03 04 05 06 07 08 09 OA 0B 0c 0D OE OF Normally unused entries Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 25 Vancouver Design Center 5 Advanced Techniques This section contains information on the following e virtual display e panning and scrolling e split screen display 5 1 Virtual Display Virtual display refers to the situation where the image to be viewed is larger than the physical display The difference can be in the horizontal vertical or both dimensions To view the image the display is used as a window into the display buffer At any given time only a portion of the image is visible Panning and scrolling are used to view the full image The Memory Address Offset register determines the number of horizontal pixels in the virtual image The offset register can be used to specify from 0 to 255 additional words for each scan line At 1 bpp 255 words span an additional 4 080 pixels At 8 bpp 255 words span an additional 510 pixels The maximum vertical size of the virtual image is the result of dividing 40960 bytes of display memory by the number of bytes on each line i e at 1 bpp with a 320x240 panel set for a virtual width of 640x480 there is enough memory for 512 lines Figure 5 1 Viewport Inside a
122. Dh REG OCh Words Line 0 Last Pixel Address REG ODh REG OCh Line O Last Pixel Address REG 12h Words 8 REG 04h 1 X BPP 16 Words Line 0 K Line 1 Image 1 REG 06h REG 05 1 Lines Line REG 14h REG 13h x Image 2 REG 1 0h REG OFh Words 8 REG 04h 1 Pixels REG 12h Words Where REG ODh REG OCh is the Screen 1 Start Word Address BPP is Bits per Pixel as set by REG 02h bits 7 6 REG 12h is the Address Pitch Adjustment in Words REG 10h REG OFh is the Screen 2 Start Word Address REG 14h REG 13h is the Screen 1 Vertical Size REG 06h REG 05h is the Vertical Panel Size Virtual Image Figure 8 1 Screen Register Relationship Split Screen Consider an example where REG 14h REG 13h OCEh for a 320x240 display system The upper 207 lines CEh 1 of the panel show an image from the Screen 1 Start Word Address The remaining 33 lines show an image from the Screen 2 Start Word Address SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 65 Vancouver Design Center Address FFF5h REG 15h Look Up Table Address Register Read Write n a n a Look Up Look Up Look Up Look Up RGB Index RGB Index Table Table Table Table Bit 1 Bit O Address Address Address Address Bit 3 Bit 2 Bit 1 Bit O bits 5 4 bits 3 0 The SED1374 has three 16 positi
123. EPSON SED1374 Embedded Memory Color LCD Controller SED1374 TECHNICAL MANUAL Issue Date 99 05 05 Document Number X26A Q 001 04 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your ownuse in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 TECHNICAL MANUAL X26A Q 001 04 Issue Date 99 05 05 Epson Research and Development Page 3 Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems Evaluation Demonstration Board e Assembled and fully tested graphics evaluation board with installation guide and sche matics e To borrow an evaluation board please contact your local Seiko Epson Corp sales repre sent
124. ERROR Zero Frame Rate e e e Fis ret LUT Control acs picar a ra Ba Figure 8 1374CFG File Open Dialog o o Figure 9 ERROR Unable to read HAL o Figure 10 1374CFG Save As Dial08 o Figure 11 ERROR Unable to read HAL o o 1374CFG EXE Configuration Program Issue Date 98 10 27 Page 3 SED1374 X26A B 001 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374CFG EXE Configuration Program X26A B 001 01 Issue Date 98 10 27 Epson Research and Development Page 5 Vancouver Design Center Introduction 1374CFG is a Win 32 program which gives developers an easy means to modify panel types clock rates color depths etc for SED1374 demonstration programs 1374CFG can e Read programs based on the 1374 Hardware Abstraction Layer HAL modify the settings and write the changes back to the file The ability to read modify and write bypasses having to recompile after every change e Write C header files containing register settings which can be used to initialize the 1374 registers in programs which do not use the HAL 1374CFG EXE Configuration Program SED1374 Issue Date 98 10 27 X26A B 001 01 Page 6 Epson Research and Development Vancouver Design Center Program Requirements Installation Usage SED1374 X26A B 001 01 This program is designed to
125. Embedded Memory Color LCD Controller Interfacing to the Toshiba MIPS TX3912 Processor Document Number X26A G 004 01 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your ownuse in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 01 Issue Date 98 11 09 EPSON Research and Development Page 3 Vancouver Design Center Table of Contents 1 IntrOdUCHON lt gt 2 at Pag ae ah a Sa A GE EN sa Gee hata sa yee ae Stone ghee hea ae 7 1 1 General Description a ane ay var ae A a Go eee ea 2 Direct Connection to the Toshiba TX3912 es 8 2 1 General Description ep ee ek oa B hod Ps b han woe bond He D ach oS 2 2 Memory Mapping and Alinne E AA AM Bae ok wa e e 2 3 SED1374 Configuration and Pin Mapping 2 e 9 3 Syste
126. Enable T High Performance P Portrait Mode Figure 3 Miscellaneous Options Miscellaneous options are several items which do not fit into any other category e HW Video Invert Enable the SED1374 supports inverted color output The color inversion can be toggled by software or in response to a signal applied to pin FPDAT11 In order for the hardware color inversion to succeed this option must be selected The color inversion is performed on the output from the LUT HW Video Invert is not availlable for TFT operation HW Power Save Enable the SED1374 supports two power save modes One is initi ated by software the second in response to input on the GPIOO pin In order for the hardware power save mode to function this option must be selected High Performance improves chip throughput at the expense of power consumption When not selected the internal MCLK signal is divided down version of the internal PCLK signal Table 1 depicts the ratios when high performance is not selected The slower MCLKs result in lower power use Table 1 MCLK to PCLK ratios Color Depth bpp Ratio 1 MCLK PCLK 8 2 MCLK PCLK 4 4 MCLK PCLK 2 8 MCLK PCLK When this option is selected MCLK PCLCK at all pixel depths Running MCLK at higher frequencies results in greater power use SED1374 1374CFG EXE Configuration Program X26A B 001 01 Issue Date 98 10 27 Epson Research and Development Page 11 Vanco
127. F5307 ColdFire Microprocessor Document Number X26A G 011 02 Copyright 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 011 02 Issue Date 99 01 05 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T py INTRODUCTION is s ota er eee fa ce ce es A OA ree ed av Ree de Guat 7 2 Interfacing to the MCF5307 2 ee ee 4 8 2 1 The MCF5307 System Bus e ee ee 8 Dilek eeN A at vig Seed ae a A Sard a Aad 8 2 1 2 Normal Non Burst Bus Transactions o 8 241 3 NBU CY CleS ac ip ta a a St AI a a 9 22 Chip Select Module s s ur a ala ca a ee a a a as a A ee 10 3 SED1374Buslnterface
128. H 4 Wait State Control Register for the area in which the SED1374 resides must be set to a non zero value The SH 4 read to write cycle transition must be set to a non zero value with ref erence to BUSCLK SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Table 7 1 SH 4 Timing Symbol Parameter Min Max Units fckio Bus Clock frequency 0 50 MHz Tokio Bus Clock period 1 fckio t2 Clock pulse width high 17 ns t3 Clock pulse width low 16 ns t4 A 15 0 RD WR setup to CKIO 0 ns t5 A 15 0 RD WR hold from CS 0 ns t6 BS setup 5 ns t7 BS hold 5 ns t8 CSn setup 0 ns t9 Falling edge RD to DB 15 0 driven 25 ns t10 Rising edge CSn to RDY high impedance t1 ns t11 Falling edge CSn to RDY driven 20 ns t12 CKIO to RDY low 20 ns t13 Rising edge CSn to RDY high 20 ns t14 DB 15 0 setup to 2 CKIO after BS write cycle ns t15 DB 15 0 hold write cycle ns t16 DB 15 0 valid to RDY falling edge setup time read cycle ns t17 Rising edge RD to DB 15 0 high impedance read cycle 10 ns Note Page 27 CKIO may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Page 28 7 1 2 SH 3 Interface Timing Epson Research and Deve
129. Issue Date 99 01 05 X26A G 010 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 02 Issue Date 99 01 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 13 Table 4 1 List of Connections from MPC821ADS to SED1374 16 Table 4 2 Configuration Settings 2 a 18 Table 4 3 Host Bus Selection e acid aA e ke a a e el a a e a o a ala 18 List of Figures Figure 2 1 Power PC Memory Read Cycle uoaa aaa 00 0000 00000 9 Figure 2 2 Power PC Memory Write Cycle ooa 0000000000 0004 10 Figure 4 1 Typical Implementation of MPC821 to SED1374 Interface 15 Interfacing to the Motorola MPC821 Microprocessor SED1374 Issue Date 99 01 05 X26A G 010 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 02 Issue Date 99 01 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the SED1374 Embedded Memory LCD Controller and the Motorola MPC821 Processor The designs described in this document are presented only as examples of how such interfaces might b
130. MSB reserved bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 The start address registers must be set for SwivelView mode In SwivelView mode the offset contained in the start address points to a byte REG 1Ch Line Byte Count Register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 The line byte count register informs the SED1374 of the stride in bytes between two consecutive lines of display in SwivelView mode The Line Byte Count register only affects SwivelView mode operation The contents of this register are ignored when the SED1374 is in landscape display mode SwivelView Mode Enable REG 1Bh SwivelView Mode Register SwivelView SwivelView SwivelView n a nja tila resend Mode Pixel Mode Pixel Mode Select Clock Select Clock Select Bit 1 Bit O Programming Notes and Examples Issue Date 99 04 27 The SwivelView mode register contains several items for SwivelView mode support The first is the Swivel View Mode Enable bit When this bit is 0 the SED 1374 is in landscape mode and the remainder of the settings in this register as well as the Line Byte Count in REG 1Ch are ignored When this bit is a 1 Swivel View mode is enabled There are two SwivelView mode display schemes available The Swivel View mode select bit selects between the Default Mode and the Alternate Mode The default mode offers the l
131. Manual X26A G 005 01 Issue Date 98 10 26 Epson Research and Development Vancouver Design Center List of Tables Table 2 1 Configuration DIP Switch Settings 0 Table 2 2 Host Bus Selection 2 2 2 ek ee Table 2 3 Jumper Settings o e e Table 3 1 LCD Signal Connector J5 Pinout o Table 4 1 CPU BUS Connector H1 Pinout Table 4 2 CPU BUS Connector H2 Pinout Table 5 1 Host Bus Interface Pin Mapping List of Figures Figure 8 1 SED1374B0C Schematic Diagram 1 of 4 Figure 8 2 SED1374B0C Schematic Diagram 2 of 4 Figure 8 3 SED1374B0C Schematic Diagram 3 of 4 Figure 8 4 SED1374B0C Schematic Diagram 40f4 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 Page 5 SED1374 X26A G 005 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 01 Issue Date 98 10 26 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction 1 1 Features This manual describes the setup and operation of the SDU1374B0C Rev 1 0 Evaluation Board Implemented using the SED1374 Embedded Memory Color LCD Controller the SDU1374B0C board is designed for the 16 bit ISA bus environment To accommodate other
132. Mode SwivelView SwivelView Mode Enable Mode Select Mode REG 1Bh bit 7 REG 1Bh bit 6 0 X Landscape 1 0 Default SwivelView 1 1 Alternate SwivelView bit 2 reserved reserved bits must be set to 0 bits 1 0 SwivelView Mode Pixel Clock Select Bits 1 0 These two bits select the Pixel Clock PCLK source in SwivelView Mode these bits have no effect in Landscape Mode The following table shows the selection of PCLK and MCLK in SwivelView Mode see Section 12 Swivel View on page 79 for details SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Table 8 9 Selection of PCLK and MCLK in SwivelView Mode Page 69 SwivelView SwivelView Pixel Clock PCLK Select Mode Enable Mode Select REG 1Bh bits 1 0 PCLK MCLK REG 1Bh bit 7 REG 1Bh bit 6 Bit 1 Bit O 0 X X X CLK See Reg 02h bit 5 1 0 0 0 CLK CLK 1 0 0 1 CLK 2 CLK 2 1 0 1 0 CLK 4 CLK 4 1 0 1 1 CLK 8 CLK 8 1 1 0 0 CLK 2 CLK 1 1 0 1 CLK 2 CLK 1 1 1 0 CLK 4 CLK 2 1 1 1 CLK 8 CLK 4 Where CLK is CLKI ua REG 02h bit 4 0 or CLKI 2 REG 02h bit 4 1 REG 1Ch Line Byte Count Register for SwivelView Mode Address FFFCh Read Write Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Count bit 7 Count bit 6 Co
133. O Connected to the WEO signal of the SED1374 30 WAIT Connected to the WAIT signal of the SED1374 31 CS Connected to the CS signal of the SED1374 32 NC Not connected 33 WE1 Connected to the WE1 signal of the SED1374 34 NC Not connected SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1374 Issue Date 98 10 26 X26A G 005 01 Page 12 SED1374 X26A G 005 01 Epson Research and Development Table 4 2 CPU BUS Connector H2 Pinout Vancouver Design Center Connector CPU BUS Comm nts Pin No Pin Name 1 SAO Connected to ABO of the SED1374 2 SA1 Connected to AB1 of the SED1374 3 SA2 Connected to AB2 of the SED1374 4 SA3 Connected to AB3 of the SED1374 5 SA4 Connected to AB4 of the SED1374 6 SA5 Connected to AB5 of the SED1374 7 SA6 Connected to AB6 of the SED1374 8 SA7 Connected to AB7 of the SED1374 9 GND Ground 10 GND Ground 11 SA8 Connected to AB8 of the SED1374 12 SA9 Connected to AB9 of the SED1374 13 SA10 Connected to AB10 of the SED1374 14 SA11 Connected to AB11 of the SED1374 15 SA12 Connected to AB12 of the SED1374 16 SA13 Connected to AB13 of the SED1374 17 GND Ground 18 GND Ground 19 SA14 Connected to AB14 of the SED1374 20 SA15 Connected to AB14 of the SED1374 21 SA16 Connected to AB16 of the SED1374 22 SA17 Connected to AB17 of the SED1374 23 SA18 Connected to AB18 of the SED1374 24 SA19 Connect
134. Off BCLK Between Accesses on page 86 Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 32 Epson Research and Development Vancouver Design Center 7 1 5 Generic 1 Interface Timing Tack BCLK EN fr EN NU Y A 15 0 VALID CS fa t2 WE0 WE1 RDO RD1 Pe eee t5 D 15 0 Hi Z write VALID t4 gt 16 t7 D 15 0 Hi Z Hi Z read VALID 18 19 t10 WAIT Hi Z Hi Z Figure 7 5 Generic 1 Timing Table 7 5 Generic 1 Timing Symbol Parameter Min Max Units fBCLK Bus Clock frequency 0 50 MHz Teck Bus Clock period 1 fBcLK MHz A 15 0 CS valid to WE0 WE1 low write cycle or RDO RD1 low read 0 nS cycle WEO WE1 high write cycle or RDO RD1 high read cycle to A 15 0 t2 z 0 ns CS invalid t3 WEO WE1 low to D 15 0 valid write cycle TBCLK t4 RDO RD1 low to D 15 0 driven read cycle 17 ns t5 WEO WE1 high to D 15 0 invalid write cycle 0 ns t6 D 15 0 valid to WAIT high read cycle 0 ns t7 RDO RD1 high to D 15 0 high impedance read cycle 10 ns 8 WEO WE1 low write cycle or RDO RD1 low read cycle to WAIT 16 nS driven low t9 BCLK to WAIT high 16 ns WEO WE1 high write cycle or RDO RD1 high read cycle to WAIT t10 scp 11 ns high impedance Note BCLK may be turned off held low between accesses see Sec
135. P 10 29 52 P IO Vop 20 27 40 VSS P 50 60 72 P Common Vss 80 Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Page 22 5 3 Summary of Configuration Options Epson Research and Development Vancouver Design Center Table 5 1 Summary of Power On Reset Options Configuration Power On Reset State Pin 1 0 CNF4 Active high On LCDPWR polarity Active low On LCDPWR polarity CNF3 Big Endian Little Endian Select host bus interface as follows CNF2 CNF1 CNFO BS Host Bus 0 0 0 xX SH 4 interface 0 0 1 Xx SH 3 interface 0 1 0 x reserved CNF 2 0 0 1 1 X MC68K 1 16 bit 1 0 0 x reserved 1 0 1 Xx MC68K 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 Generic 1 16 bit 1 1 1 1 Generic 2 16 bit 5 4 Host Bus Interface Pin Mapping Table 5 2 Host Bus Interface Pin Mapping ti n SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vss connect to IO Vpp RD WR RD WR RD WR R W R W RD1 connect to lO Vpp RD RD RD connect to lO Vpp SIZ1 RDO RD WE0 WE0
136. PP1374 under wince platform cepc drivers display Copy the source code to the 4BPP1374 subdirectory Add an entry for the 4BPP1374 in the file wince platform cepc drivers display dirs Modify the file CONFIG BIB using any text editor such as NOTEPAD to set the system RAM size the SED1374 IO port and display buffer address mapping Note that CONFIG BIB is located in X wince platform cepc files where X is the drive letter Since the SDU1374B0C maps the 64K byte region from D0000h to DFFFFh make sure no other devices occupy this area The following lines should be in CON FIG BIB NK 80200000 00500000 RAMIMGE RAM 80700000 00500000 RAM Note DISPDRVR C should include the following define PhysicalPortAddr O0xOOODFOOOL define PhysicalVmemAddr 0x000D0000L 5 Edit the file PLATFORM BIB located in X wince platform cepc files to set the de fault display driver to the file 4BPP1374 DLL 4BPP1374 DLL will be created during the build in step 13 You may replace the following lines in PLATFORM BIB IF CEPC_DDI_VGA2BPP ddi dll _FLATRELEASEDIR ddi_vga2 dll NK SH ENDIF IF CEPC_DDI_VGA8BPP ddi dll _FLATRELEASEDIR ddi_vga8 dll NK SH ENDIF IF CEPC_DDI_VGA2BPP IF CEPC_DDI_VGA8BPP ddi dll _FLATRELEASEDIR ddi_s364 d1l NK SH ENDIF ENDIF with this line adi arll _FLATRELEASEDIR 4BPP1374 dll NK SH Windows CE Display Dri
137. Requirements Clock Input Waveform tpwH ai tw tS 90 ViH VIL 10 tel E gt o ti TeLKI gt Figure 7 7 Clock Input Requirements Table 7 7 Clock Input Requirements Symbol Parameter Min Max Units foLKI Input Clock Frequency CLKI 0 50 MHz Toki Input Clock period CLKI Wer town Input Clock Pulse Width High CLKI 8 ns tow Input Clock Pulse Width Low CLKI 8 ns t Input Clock Fall Time 10 90 5 ns t Input Clock Rise Time 10 90 5 ns Note When CLKI is gt 25MHz it must be divided by 2 REG 02h bit 4 1 SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center 7 3 Display Interface 7 3 1 Power On Reset Timing Page 35 RESET REG 03h bits 1 0 LCDPWR CNF4 1 LCDPWR CNF4 0 FPLINE FPSHIFT FPDAT FPFRAME DRDY 00 11 ACTIVE Figure 7 8 LCD Panel Power On Reset Timing Symbol Parameter Min Typ Max Units H active REG 03h to FPLINE FPFRAME FPSHIFT FPDAT DRDY TEPFRAME ns t2 LCDPWR FPLINE FPFRAME FPSHIFT FPDAT DRDY active to Frames Note Where TrprERAME is the period of FPFRAME and Tpcyz x is the period of the pixel clock Hardware Functional Specification Issue Date 99 04 29 SED
138. SED1374 Signal Name Vcc P6 A1 P6 B1 Vcc A16 P6 B24 SA15 A17 P6 C24 SA14 A18 P6 D23 SA13 A19 P6 D22 SA12 A20 P6 D19 SA11 A21 P6 A19 SA10 A22 P6 D28 SA9 A23 P6 A28 SA8 A24 P6 C27 SA7 A25 P6 A26 SA6 A26 P6 C26 SA5 A27 P6 A25 SA4 A28 P6 D26 SA3 A29 P6 B25 SA2 A30 P6 B19 SA1 A31 P6 D17 SAO DO P12 A9 SD15 D1 P12 C9 SD14 D2 P12 D9 SD13 D3 P12 A8 SD12 D4 P12 B8 SD11 D5 P12 D8 SD10 D6 P12 B7 SD9 D7 P12 C7 SD8 D8 P12 A15 SD7 D9 P12 C15 SD6 D10 P12 D15 SD5 D11 P12 A14 SD4 D12 P12 B14 SD3 D13 P12 D14 SD2 D14 P12 B13 SD1 D15 P12 C13 SDO SRESET P9 D15 RESET SYSCLK P9 C2 BUSCLK CS4 P6 D13 CS Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 01 05 Epson Research and Development Page 17 Vancouver Design Center Table 4 1 List of Connections from MPC821ADS to SED1374 Continued MPC821 Signal Name MPC821ADS Connector and Pin Name SED1374 Signal Name TA P6 B6 to inverter enabled by CS WAIT WEO P6 B15 WE1 WE1 P6 A14 WE0H OE P6 B16 RD WR RDA P12 A1 P12 B1 P12 A2 P12 B2 P12 A3 P12 B3 P12 A4 P12 B4 P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 GND Vss Note The bit numbering of the Power PC bus signals is reversed from the normal convention e g the most significant address bit is AO the next is Al A2 etc Interfacing to the Motorola MPC82
139. SED1374 Supported Evaluation Platforms 1374SHOW has been tested with the following SED1374 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the SED1374 Programming Notes and Examples manual document number X26A G 002 xx Installation PC platform copy the file 1374SHOW EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 1374SHOW to the system 1374SHOW Demonstration Program SED1374 Issue Date 98 10 20 X26A B 002 01 Page 4 Usage Epson Research and Development Vancouver Design Center PC platform at the prompt type 1374show a b n 1 p vertical noinit Embedded platform execute 1374 show and at the prompt type the command line argument s Where a automatically cycle through all video modes b starts 1374SHOW at a user specified bit per pixel bpp level where can be 1 2 4 8 1 set landscape mode p set portrait mode vertical displays vertical line pattern noinit bypass register initialization and use values which are currently in the registers es displays
140. SHIT L LTIS ela o A AA TS FPDAT7 TA 1 R1 1 G2 1 B3 X 1 R5 1 G6 1 B7 E ae A X1 B639 FPDAT6 oe 1 41 X 1 82 X 1 R4 X 1 45 X 1 86 X 1 R8 E K1 R640 Oo FPDAT5 en 1181 X 1 R3 X 1 44 X 1 B5 X 1 R7 X 1 G8 ne X Y1 G640 FPDAT4 f 1 R2 X 1 63 X 1 84 X 1 R6 X 1 67 X 1 B8 X 1 B640 FPDAT3 7 241 1X241 62241 83 241 R5X241 G0 241 B7E X K ON FPDAT2 2 fear as 1 B2x241 R4X241 G5 X241 86X241 R8X X EHA X FPDAT1 a 241 81 241 R9X241 G4X241 85241 R7 241 684 ESE FPDATO E 241 R2X241 G3X241 B4X241 R6X241 G7X241 B8 X EHR x Y Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 22 Dual Color 8 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 50 Epson Research and Development Vancouver Design Center Sync Timing p gt D Frame Pulse gt t4 t3 gt Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 t9 t7 t11 t10 Shift Pulse voo FPDAT 7 0 1 2 1 Figure 7 23 Dual Color 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Uni
141. Specification document number X26A A 001 xx 3 2 Generic 1 Interface Mode SED1374 X26A G 011 02 Generic 1 interface mode is the most general and least processor specific interface mode on the SED1374 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the SED1374 host interface It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the SED1374 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is readin
142. U wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the SED1374 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 99 01 05 Epson Research and Development Page 11 Vancouver Design Center 3 3 MC68K 1 Interface Mode The MC68K 1 Interface Mode can be used to interface to the MC68328 microprocessor if the previously mentioned multiplexed bus signals will not be used for other purposes The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the SED1374 It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs AB1 through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space AO and WE1 are the enables for the low order and high order bytes respectively
143. Up Table Data aed Write 16 RGB triplets to setup the LUT for 4BPP operation ps The LUT is 16 elements deep 4BPP uses all the idices a pLUT Color_4BPP for LUTcount 0 LUTcount lt 16 LUTcount for RGBcount 0 RGBcount lt 3 RGBcount SET_REG 0x17 pLUT pLUT Register 18h GPIO Configuration set to 0 KA 0 configures the GPIO pins for input power on default Ay SET_REG 0x18 0x00 Register 19h GPIO Status set to O ER This step has no reason other than it programs the GPIO Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Page 69 Vancouver Design Center EX values low should the pins get configured as outputs SET_REG 0x19 0x00 Register 1Ah Scratch Pad set to 0 tf SET_REG Ox1A 0x00 Register 1Bh SwivelView Mod set to 0 disable SwivelView mod SET_REG 0x1B 0x00 Register 1Ch Line Byte Count set to 0 Not used by landscape mode E SET_REG 0x0C 0x00 Register 1Fh TestMod set to 0 SET_REG 0x1F 0x00 Draw a 100x100 red rectangle in the upper left corner 0 0 of the display Ay for y 0 y lt 100 y Set the memory pointer at the start of each line KR Pointer MEM_OFFSET Y Line_Width BPP 8 X BPP
144. Vancouver Design Center enum e ERR_FAILE ERR_UNKNOWN_DEVICE ERR_INVALID_PARAMETER PE ERR_HAL_BAD_ARG ERR_TOOMANY_DEVS D yl No error call was successful General purpose failure x Function was called with invalid parameter BOR KKK KK KK KR RARA RR RRA RA kkk k kkk Definitions for seGetId KARA RARA I RARA RARA RR RR KARA RRA RARAS define PRODUCT_ID 0x18 enum ID_UNKNOWN ID_SED1374 ID_SED1374F0A define MAX MEM ADDR 40960 1 define FORTY_K define MAX DEVICE 10 define SE_RSVD 40960 DetectEndian is used to determine whether the most significant and least significant bytes ar Ey define ENDIAN define REV_ENDIAN 0x1234 0x3412 reversed by the given compiler BOK KKK KKK KK kk kkk kk kkk kkk k kkk k kkk k kkk Definitions for Internal calculations FAK AK I I I A I I I I RARAS define MIN_NON_DISP_X 32 define MAX_NON_DISP_X 256 define MIN_NON_DISP_Y 2 define MAX_NON_DISP_Y 64 KOK KKK KKK KK I I I KK eK Definitions for seSetFont Fe AK I I A I I I RRA RARAS enum HAL STDOUT HAL STDIN HAL_DEVICE F ERR r define FONT_NOR SED1374 X26A G 002 02 AL 0x00 Programming Notes and Examples Issue Date 99 04 27 Eps
145. Virtual Display depicts a typical use of a virtual display The display panel is 320x240 pixels an image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling 320x240 gt Viewport 640x480 Virtual Display Figure 5 1 Viewport Inside a Virtual Display Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 26 5 1 1 Registers Epson Research and Development Vancouver Design Center REG 12h Memory Address Offset Register Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Offset Offset Offset Offset Offset Offset Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 1 2 Examples SED1374 X26A G 002 02 Figure 5 2 Memory Address Offset Register REG 12h forms an 8 bit value called the Memory Address Offset This offset is the number of additional bytes on each line of the display If the offset is set to zero there is no virtual width Note This value does not represent the number of words to be shown on the display The dis play width is set in the Horizontal Display Width register Example 1 In this example we go through the calculations to display a 640x480 im age on a 320x240 panel at 2 bpp Step 1 Calculate the number of pixels per word for this color depth At 2 bpp each byte is c
146. WAN 3H8S otu i gt ram ED 0 LTIVT INS Lost ols g8 NOD Lv NOD a ATISNE lt HSTUAIA K o z r sau T Hom anog aor rom spa amor Sb pto adAoI adaor MOT 6a li asu ADHOOI T TT aaaor OTIS lt sT Olas an 8 9 y Fa Figure 8 3 SED1374B0C Schematic Diagram 3 of 4 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1374 Issue Date 98 10 26 X26A G 005 01 Epson Research and Development Page 23 Vancouver Design Center gt les a le ES u g 5 3 a 8 E 2 p a al E q 3 E a Ea o a 2 Lo Pa c 3 a 8 E 2 z E E a g 8 H a 3 a 3 i o ls EA a f gt a a a E EN Le 8 E 5 EA E Ss FF E i a B E A z E E a gt a o P 3 2S S E 2 a ae a 2 2 E ao Da a E 3 Ba po pe a aE Ja gt fd o ll la 8 g S o a 8 2 E E tS E a a 3 2 3 z g l a i E E y a 3 fa 8 S A a m Ly E Figure 8 4 SED1374B0C Schematic Diagram 4 of 4 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1374 Issue Date 98 10 26 X26A G 005 01 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 01 Issue Date 98 10 26 EPSON SED1374
147. Write Cycle Burst Cycles Burst cycles are very similar to normal cycles except that they occur as a series of four back to back 32 bit memory reads or writes with the TIP Transfer In Progress output asserted continuously through the burst Burst memory cycles are mainly intended to facil itate cache line fill from program or data memory they are typically not used for transfers to or from IO peripheral devices such as the SED1374 The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not able to support them Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 99 01 05 SED1374 X26A G 011 02 Page 10 Epson Research and Development Vancouver Design Center 2 2 Chip Select Module SED1374 X26A G 011 02 In addition to generating eight independent chip select outputs the MCF5307 Chip Select Module can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MCF5307 bus controller also provides a Read Write R W signal which is compatible with most 68K peripherals Chip selects O and 1 can be programmed independently to respond to any base address and block size Chip select 0 can be active immediately after reset and is typically used to control a boot ROM Chip select 1 is likewise typically used to control a large static or dynamic RAM block Chip selects 2 through 7 have fixed blo
148. _REG Ox1F ndif HAL_REGS_H SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Page 79 Vancouver Design Center Appendix A Supported Panel Values A 1 Introduction Future versions of this document will supply example tables for programming the SED1374 for different panels Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 80 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 SED 1374 Register Summary REG 00h REVISION CODE REGISTER O address FFEOh 2 RO REG 13h SCREEN 1 VERTICAL SIZE REGISTER LSB IO address FFF3h RW Bit 5 Bit 4 Product Code 000110 Bit 3 Bit 2 Bit 1 Bit 1 Revision Code 00 Bit 0 Bit 7 Bit 6 Screen 1 Vertical Size REG 13h REG 14h Bit 5 Bit 4 Bit 3 Bit 2 REG 01h Mobe REGISTER 0 IO address FFE1h RW REG 14h SCREEN 1 VERTICAL SIZE REGISTER MSB 1O address FFF4h RW TFT STN Dual Single Color Mono FPLine Polarity FPFrame Polarity Mask FPSHIFT Bit 1 Data Width Bit 0 n a n a n a n a n a n a Screen 1 Vertical Size Bit 9 Bit 8 REG 02h MoDE REGISTER 1 IO address FFE2h RW Pixel Bit 0 REG 03h MODE REGISTER 2 IO address FFE3h RW High Performance Input Clock Div CLKI 2 Displa
149. a A o YG CO FPDAT 11 gt E A E ait FPDAT 8 6 Note DRDY is used to indicate the first pixel Example Timing for 640x480 panel Figure 7 24 12 Bit TFT MD TFD Panel Timing VDP Vertical Display Period VNDP Vertical Non Display Period VNDP1 Vertical Non Display Period 1 VNDP2 Vertical Non Display Period 2 HDP Horizontal Display Period HNDP Horizontal Non Display Period HNDP1 Horizontal Non Display Period 1 HNDP2 Horizontal Non Display Period 2 Hardware Functional Specification Issue Date 99 04 29 REG O6h bits 1 0 REG O5h bits 7 0 1 Lines VNDP1 VNDP2 REG OAh bits 5 0 Lines REG 09h bits 5 0 Lines REG 0Ah bits 5 0 REG O9Ah bits 5 0 Lines REG 04h bits 6 0 1 x 8Ts HNDP1 HNDP2 REG 08h 4 x 8Ts REG 07h bits4 0 x 8 16Ts REG 08h bits4 0 REG 07h bits 4 0 x 8 16Ts SED1374 X26A A 001 02 Page 52 Epson Research and Development Vancouver Design Center t9 lt Frame Pulse p 12 we UY UY U UU o i n E L FPDAT 11 0 4 gt Note DRDY is used to indicate the first pixel Figure 7 25 TFT MD TFD A C Timing SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page
150. a eel AE A ea 16 6 1 Documents a 16 6 2 Document Sources a i srein d ar 2 ee ee ee ee 16 YT Technical Support a a s 2 20 22 ae ee ee A ee Ee os 17 7 1 EPSON LCD Controllers SED1374 a TT Ta PCCard Standards o auio 8 dora ca de Be ee a a as ee oe a DY Interfacing to the PC Card Bus SED1374 Issue Date 98 12 10 X26A G 009 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the PC Card Bus X26A G 009 02 Issue Date 98 12 10 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2 2 a 10 Table 4 1 Summary of Power On Reset Options 0 0 00 0000200048 13 Table 4 2 Host Bus Interface Selection 2 2 2 ee ee 13 List of Figures Pieu re 2 1 PC Card Read Cycles e sase tS Seem ana Har ee ay ie Bay BoP A EE 9 Figure 2 2 PC Card Write Cycle o 9 Figure 4 1 Typical Implementation of PC Card to SED1374 Interface 12 Interfacing to the PC Card Bus SED1374 Issue Date 98 12 10 X26A G 009 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the PC Card Bus X26A G 009 02 Issue Date 98 12 10 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide
151. able LUT If the first two LUT elements are set to black RGB 0 0 0 and white RGB F F F then each 0 bit of display memory will display as a black pixel and each 1 bit will display as a white pixel The two LUT entries can be set to any desired colors for instance red green or cyan yellow Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Figure 3 1 Pixel Storage for 1 Bpp 2 Colors Gray Shades in One Byte of Display Buffer Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 12 Epson Research and Development Vancouver Design Center 3 1 2 2 Bit Per Pixel 4 Colors Gray Shades 2 bit pixels support four color gray shades In this memory format each byte of display buffer contains four adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the appropriate bits and if necessary setting bits to 1 For color panels the four colors are derived by indexing into positions 0 through 3 of the Look Up Table For monochrome panels the four gray shades are generated by indexing into the first four elements of the green component of the Look Up Table Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 2 Pixel 2 Pixel 3 Pixel 3 Bit 1 Bit O Bit 1 Bit O Bit 1 Bit O Bit 1 Bit O Figure 3 2 Pixel Storage
152. age 10 Epson Research and Development Vancouver Design Center Figure 2 2 Power PC Memory Write Cycle illustrates a typical memory write cycle on the Power PC system bus sr eb Tbh el ee Te Ed TS TA Alo 31 XxX x TSIZ 0 1 AT O 3 l x Dlo 31 00000 valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 Power PC Memory Write Cycle If an error occurs TEA Transfer Error Acknowledge is asserted and the bus cycle is aborted For example a peripheral device may assert TEA if a parity error is detected or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus time out period For 32 bit transfers all data lines D 0 31 are used and the two low order address lines A30 and A31 are ignored For 16 bit transfers data lines DO through D15 are used and address line A30 is ignored For 8 bit transfers data lines DO through D7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 2 2 Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry out certain on chip DMA operations They are very similar to normal bus cycles with the following exceptions e Always 32 bit e Always attempt to transfer four 32 bit words sequentially e Always address long
153. al Power Save Power Save IO Access Possible No Yes Yes Memory Access Possible No Yes Yes Sequence Controller Running No No Yes Display Active No No Yes LCDPWR Inactive Inactive Active FPDAT 11 0 FPSHIFT see note Forced Low Forced Low Active FPLINE FPFRAME DRDY Forced Low Forced Low Active Note When FPDAT 11 8 are designated as GPIO outputs the output state prior to enabling the Power Save Mode is maintained When FPDAT 11 8 are designated as GPIO in puts unused inputs must be tied to either IO Vpp or GND see Table 5 3 LCD Inter face Pin Mapping on page 23 13 4 Panel Power Up Down Sequence After chip reset or when entering exiting a power save mode the Panel Interface signals follow a power on off sequence shown below This sequence is essential to prevent damage to the LCD panel Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 86 Epson Research and Development Vancouver Design Center RESET Software Power Save REG 03h bits 1 0 or Hardware Power Save LCDPWR CNF4 Low LCDPWR CNF4 Hi Panel Interface Output Signals except LCDPWR x 00 Power Save Mode gt 4 O frame power up 127 frames power down gt 0 frame power up 13 5 Turning Off BCLK Between Accesses SED1374 X26A A 001 02 Figure 1
154. ally a programmer has only to concern themselves with calls to seRegisterDevice and seSetInit int seRegisterDevice const LPHAL_STRUC IpHallnfo int pDeviD Description Registers the SED1374 device parameters with the HAL library The device param eters have been configured with address range register values desired frame rate etc and have been saved in the HAL_STRUCT structure pointed to by IpHalInfo Parameters IpHalInfo pointer to HAL_STRUCT information structure pDevice pointer to the integer to receive the device ID Return Value ERR_OK operation completed with no problems ERR_UNKNOWN_DEVICE the HAL was unable to find an SED1374 Note No SED1374 registers are changed by calling seRegisterDevice Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 48 SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center seSetInit int DevID Description Parameters Configures the SED1374 for operation This function sets all the SED1374 control registers to their default values Initialization of the SED1374 was made a stand alone step to accommodate those programs e g 1374PLAY EXE which needed the ability to start and examine the system before changing register contents DevID registered device ID Return Value ERR_OK operation completed with no problems Note After this call the Look Up Table will be set to a default state appropriate to
155. am Document No X26A B 006 01 Copyright O 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374BMP Demonstration Program X26A B 006 01 Issue Date 98 10 20 Epson Research and Development Page 3 Vancouver Design Center 1374BMP Installation Usage Comments 1374BMP demonstrates SED1374 display capabilities by rendering bitmap images on the display The 1374BMP display utility is designed to operate in a personal computer DOS environment and must be configured to work with your display hardware Consult documentation for the program 1374CFG EXE which can be used to configure 1374BMP 1374BMP is not supported on non PC platforms Copy the file 1374BMP EXE to a directory that is in the DOS path on your hard drive At the prompt type 1374bm
156. an interface between the SED1374 Embedded Memory LCD Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the PC Card Bus SED1374 Issue Date 98 12 10 X26A G 009 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2 1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness This section is an overview of the operation of the 16 bit PC Card interface conforming to the PCMCIA 2 0 JEIDA 4 1 Standard or later 2 1 1 PC Card Overview The 16 bit PC Card provides a 26 bit address bus and additional control lines which allow access to three 64M byte address ranges These ranges are used for common memory space IO space and attribute memory space Common memory may be accessed by a host system for memory read and write operations Attribute memory is used for defining card specific information such as configuration registers card capabilities and card u
157. an internal LCD controller or the CPU board must have an LCD controller on it that interfaces to the microprocessor For the TMPR3912 22U microprocessor the SED1374 or SED1375 LCDC is used to provide support for LCD panels The LCDC is socketed so that it can be interchanged between the SED1374 and the SED1375 These controllers are very similar with the main differences being the amount of embedded display memory and the lookup table archi tecture LUT The SED1374 has 40K bytes of display memory and the SED1375 has 80K bytes The Toshiba TMPR3912 22U processor supports two PC Card PCMCIA slots on the TX RISC Reference Platform The SED1374 or SED1375 LCD controller uses the PC Card slot 1 to interface to the TMPR3912 22U therefore this slot is unavailable for use on the TX RISC Reference Platform SDU1374 75 TMPR3912 22U CPU Module Issue Date 98 12 23 X00A G 004 01 Page 8 EPSON Research and Development Vancouver Design Center 2 SED1374 75 Bus Interface This section is summary of the bus interface modes available on the SED1374 and SED1375 LCDCs and offers some detail on the Generic 2 bus mode used to implement the interface to the TMPR3912 22U 2 1 Bus Interface Modes X00A G 004 01 The SED 1374 75 implements a general purpose 16 bit interface to the host micropro cessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Bus interface mode selections are
158. ancouver Design Center 3 4 SED1374 Configuration The SED1374 is configured at power up by latching the state of the CNF 4 0 pins Pin BS also plays a role in host bus interface configuration For details on configuration refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx The table below shows those configuration settings relevant to this specific interface Table 3 3 SED1374 Configuration Using the IT8368E SED1374 Value hard wired on this pin is used to configure Configuration Pin 1 10 Vpp 0 Vss BS Generic 2 CNF3 Big Endian CNF 2 0 configuration for connection using ITE IT8368E When the SED 1374 is configured for Generic 1 interface the host interface pins are mapped as in the table below Table 3 4 SED1374 Generic 1 Interface Pin Mapping Pin Name Pin Function WE1 WE1 BS connect to Vsg RD WR RD1 RD RDO WEO0 WEO0 Interfacing to the Toshiba MIPS TX3912 Processor SED1374 Issue Date 98 11 09 X26A G 004 01 Page 14 4 Software SED1374 X26A G 004 01 EPSON Research and Development Vancouver Design Center Test utilities and Windows CE v2 0 display drivers are available for the SED 1374 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1357CFG or by directly modifying the so
159. and RD See Host Bus Interface Pin Mapping for summary WAIT TS2 High Impedance This pin has multiple functions For SH 3 mode this pin outputs the wait request signal WAIT For SH 4 mode this pin outputs the device ready signal RDY For MC68K 1 this pin outputs the data transfer acknowledge signal DTACK For MC68K 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 For Generic 1 this pin outputs the wait signal WAIT For Generic 2 this pin outputs the wait signal WAIT See Host Bus Interface Pin Mapping for summary RESET 73 CS Active low input to set all internal registers to the default state and to force all signals to their inactive states 5 2 2 LCD Interface Pin Name Type Pin Cell RESET State Description FPDAT 7 0 30 31 32 33 34 35 36 37 CN3 Panel Data FPDAT 10 8 24 25 26 CN3 Input These pins have multiple functions Panel Data bits 10 8 for TFT MD TFD panels General Purpose Input Output pins GPIO 3 1 These pins should be connected to lO Vpp when unused See LCD Interface Pin Mapping for summary FPDAT11 1 0 23 CN3 Input This pin has multiple functions Panel Data bit 11 for TFT MD TFD panels General Purpose Input Output pin GPIO4 e Inverse Video select pin This pin should be
160. and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374PWR Power Save Utility X26A B 007 01 Issue Date 98 10 27 Epson Research and Development Page 3 Vancouver Design Center 1374PWR The 1374PWR Power Save Utility is a tool to assist in the testing of the software and hardware power save modes Refer to the section titled Power Save Modes in the SED1374 Programming Notes and Examples manual document number X26A G 002 xx and the SED1374 Functional Hardware Specification document number X26A A 001 xx for further information The 1374PWR utility must be configured and or compiled to work with your hardware platform Consult documentation for the program 1374CFG EXE which can be used to configure 1374PWR This software is designed to work in both embedded and personal co
161. and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Epson Research and Development Page 10 Vancouver Design Center This routine first performs a formula rearrangement so that HNDP or VNDP can be solved for Start with VNDP set to a small value Loop increasing VNDP and solving the equation for HNDP until satisfactory HNDP and VNDP values are found If no satisfactory values are found then divide CLKI and repeat the process If a satisfactory frame rate still can t be reached return an error In C the code looks like the following snip for int loop 0 loop lt 2 loop VNDP 2 VNDP lt 0x3F VNDP 3 Solve for HNDP HNDP PCLK FrameRate VDP VNDP HDP if HNDP gt 32 amp amp HNDP lt 280 Solve for VNDP VNDP PCLK FrameRate HDP HNDP VDP If we have satisfied VNDP then we re don if VNDP gt 0 amp amp VNDP lt 0x3F goto DoneCalc Divide C1k1 and try again Reg 02 allows us to dived CLKI by 2 PCLK 2 If we still can t hit the frame rat throw an error if VNDP lt 0 VNDP gt 0x3F HNDP lt 32 HNDP gt 280 sprintf ERROR Unable to set the desired frame rate n exit 1 SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 11 3 Memory Models The SED1374 is capable of operating at four differ
162. anel Timing Registers 8 1 Register Mapping 8 2 Register Descriptions Frame Rate Calculation Display Data Formats Look Up Table Architecture 11 1 Gray Shade Display Modes 11 2 Color Display Modes SwivelView 12 1 Default SwivelView Mode 12 1 1 How to Set Up Default SwivelView Mode 12 2 Alternate SwivelView Mode a ase 12 2 1 How to Set Up Alternate Swivel View Mode 12 3 Comparison Between Default and Alternate SwivelView Modes 12 4 SwivelView Mode Limitations Power Save Modes 0 0080 ee ee eee eee 13 1 13 2 13 3 13 4 13 5 13 6 Mechanical Data Software Power Save Mode Hardware Power Save Mode Power Save Mode Function Summary Panel Power Up Down Sequence Turning Off BCLK Between Accesses Clock Requirements X26A A 001 02 Generic 1 Interface TiMing Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Table 5 1 Table 5 2 Table 5 3 Table 6 1 Table 6 2 Table 6 3 Table 6 4 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 7 7 Table 7 8 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Table 8 9 Table 11 1 Table 12 1 Table 13 1 Table 13 2 Table 13 3 Table 13 4 Table 13 5 List of Tables Summary of Power On Reset Options Host Bu
163. anks of 4 16 color 1 bank of 16 1 bank of 16 1 bank of 16 256 color 2 banks of 8 2 banks of 8 4 banks of 4 Indicates the Look Up Table is not used for that display mode The following figures are intended to show the display data output path only The CPU R W access to the individual Look Up Tables is not affected by the various banking configurations SED1374 1 bit pixel data Green Look Up Table Green Bank Select REG 16h bits 3 2 gt gt 2 gt gt 3 Bank Select Logic gt E gt gt 2 gt 2 Gray Data Format 7 6 5 4 3 2 1 AO A1 A2 A3 A4 A5 A6 A7 See Section 10 4 bit display data output Figure 11 1 2 Level Gray Shade Mode Look Up Table Architecture X26A A 001 02 Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Page 73 Vancouver Design Center 4 Level Gray Shade Mode 4 Gray Data Format 7 6 54 3 2 1 0 A0 BO A1 B1 A2 B2 A3 B3 Green Look Up Table See Section 10 Bank 0 2 bit pixel data 0 gt 2 3 Bank 1 0 ar Bank 3 Select 4 bit display data output 5 Bank 2 Logic 0 gt 1 2 3 Bank 3 0 gt gt 3 Green Bank Select REG 16h b
164. ardware power save mode needs to be enabled by 1374PWR and then activated by DIP switch SW1 6 See Table 2 1 Configuration DIP Switch Settings on page 8 for details on setting this switch 6 11 Adjustable LCD Panel Negative Power Supply Most monochrome passive LCD panels require a negative power supply to provide between 18V and 23V Ipy 45mA For ease of implementation such a power supply has been provided as an integral part of this design The VLCD power supply can be adjusted by R21 to give an output voltage from 14V to 23V and is enabled disabled by the SED1374 control signal LCDPWR LCDPWR is an SED 1374 output signal which is configurable as active high or active low by the CNF4 signal status on the rising edge of the RESET signal For the proper operation of the VLCD power supply LCDPWR must be configured as active low Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel 6 12 Adjustable LCD Panel Positive Power Supply Most color passive LCD panels and most single monochrome 640x480 passive LCD panels require a positive power supply to provide between 23V and 40V I 45mA For ease of implementation such a power supply has been provided as an integral part of this design The Vppx power supply can be adjusted by R15 to provide an output voltage from 23 V to 40V and is enabled disabled by the SED1374 control signal LCDPWR LCDPWR is an SED 1374
165. ase address port size 16 bits select GPCM write value to base register clear r2 address mask use upper 10 normal CS negation delay CS inhibit burst write to option register clear rl point rl to start of SED1374 read revision code into rl branch forever Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 01 05 Epson Research and Development Page 21 Vancouver Design Center This code was entered into the memory of the MPC821ADS using the line by line assembler in MPC8BUG the debugger provided with the ADS board It was executed on the ADS and a logic analyzer was used to verify operation of the interface hardware Note MPC8BUG does not support comments or symbolic equates these have been added for clarity It is important to note that when the MPC821 comes out of reset its on chip caches and MMU are disabled If the data cache is enabled then the MMU must be set up so that the SED1374 memory block is tagged as non cacheable to ensure that accesses to the SED1374 will occur in proper order and also to ensure that the MPC821 does not attempt to cache any data read from or written to the SED1374 or its display buffer Interfacing to the Motorola MPC821 Microprocessor SED1374 Issue Date 99 01 05 X26A G 010 02 Page 22 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1374 Full source code is
166. ask FPSHIFT when selected the panel clocking signal FPSHIFT is masked off This option is required for most newer monochrome panels When color panel type is selected this option is disabled This option is STN specific and is disabled if TFT is selected 1374CFG EXE Configuration Program Issue Date 98 10 27 Epson Research and Development Page 9 Vancouver Design Center Format 2 There are two data clocking formats in use by 8 bit color panels The orig inal clocking scheme was designated to be format 1 and the newer scheme was desig nated format 2 Select this option for most 8 bit color panels To date all color panels smaller than 640x480 have been found to be format 2 Setting this attribute incorrectly will result in a garbled display but will not damage the panel The display may appear cut in half or possibly horizontally skewed This option is STN specific and is disabled if TFT is selected It is also disabled if the panel type is selected to be 4 bit or monochrome Frame Repeat is a feature for EL panel support EL panels use a frame of repeated data as the cue to change their polarization Without this change in polarization panel quality deteriorates When Frame Repeat is selected an internal counter causes the periodic repeat of one frame of modulated panel At a frame rate of 72 Hz the repeat period is roughly one hour When not selected the modulated image is never consecutively repeated This option
167. ata lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the SED1374 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the SED1374 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the SED1374 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1374 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1374 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1
168. ative Chip Documentation e Technical manual includes Data Sheet Application Notes and Programmer s Refer ence Software e User Utilities OEM Utilities e Evaluation Software e To obtain these programs contact Application Engineering Support Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 TECHNICAL MANUAL Issue Date 99 05 05 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http Awww eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1374 X26A Q 001 04 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 TECHNICAL MANUAL X26A Q 001 04 Issue Date 99 05 0
169. available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1374CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1374 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www erd epson com SED1374 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 02 Issue Date 99 01 05 Epson Research and Development Page 23 Vancouver Design Center 6 References 6 1 Documents Motorola Inc Power PC MPC821 Portable Systems Microprocessor User s Manual Motorola Publication no MPC821UM AD available on the Internet at http www mot com SPS ADC pps _subpgs _documentation 821 821UM html Epson Research and Development Inc SED1374 Embedded Memory LCD Controller Hardware Functional Specification Document Number X126A A 002 xx Epson Research and Development Inc SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx Epson Research and Development Inc Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website http www mot com e Epson Research and Development Website http www
170. be the same and whether to use DCLKOUT divided as clock source should be based on pixel and frame rates power budget part count and maximum SED 1374 respective clock frequencies Also internal SED 1374 clock dividers provide additional flexibility 3 2 IT8368E Configuration The IT8368E provides eleven multi function IO pins MFIO The IT8368E must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the SED1374 host bus interface and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the SED1374 When accessing the SED1374 the associated card side signals are disabled in order to avoid any conflicts For mapping details refer to section 3 3 Memory Mapping and Aliasing For connection details see Figure 3 1 SED1374 to TX3912 Connection Using an IT8368E on page 10 For further infor mation on the IT8368E refer to the T8368E PC Card GPIO Buffer Chip Specification Note When a second IT8368E is used that circuit should not be set in VGA mode Interfacing to the Toshiba MIPS TX3912 Processor SED1374 Issue Date 98 11 09 X26A G 004 01 Page 12 EPSON Research and Development Vancouver Design Center 3 3 Memory Mapping and Aliasing When the TX3912 accesses the PC Card slots without the ITE IT8368E its system memory is mapped as in Table 3 1 TX3912 to Unbuffered PC Card Slots System Address
171. bytes of 64K byte address space e The complete 40K byte frame buffer is directly and contiguously available through the 16 bit address bus 2 3 Display Support e 4 8 bit monochrome LCD interface e 4 8 bit color LCD interface e Single panel single drive passive displays e Dual panel dual drive passive displays e Active Matrix TFT MD TFD interface e Register level support for EL panels e Example resolutions 640x480 at a color depth of 1 bpp 640x240 at a color depth of 2 bpp 320x240 at a color depth of 4 bpp 240x160 at a color depth of 8 bpp SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 11 Vancouver Design Center 2 4 Display Modes 2 5 Clock Source SwivelView direct 90 hardware rotation of display image for portrait mode display 1 2 4 bit per pixel bpp 2 4 16 level grayshade display 1 2 4 8 bit per pixel 2 4 16 256 level color display Up to 16 shades of gray by FRM on monochrome passive LCD panels a 16x4 Look Up Table is used to map 1 2 4 bpp modes into these shades 256 simultaneous of 4096 colors on color passive and active matrix LCD panels three 16x4 Look Up Tables are used to map 1 2 4 8 bpp modes into these colors Split screen display for all landscape panel modes allows two different images to be simultaneously displayed Virtual display support displays images larger than the panel size through the use of panning
172. calling seSplitScreen Programming Notes and Examples Issue Date 99 04 27 SED1374 X26A G 002 02 Page 54 SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center int seVirtInit int DevID DWORD VirtX DWORD VirtY Description This function prepares the system for virtual screen operation The programmer passes the desired virtual width in pixels as VirtX When the routine returns VirtY will contain the maximum number of line that can be displayed at the requested virtual width Parameter DevID registered device ID VirtX horizontal size of virtual display in pixels Must be greater or equal to physical size of display VirtY pointer to an integer to receive the maximum number of displayable lines of VirtX width Return Value ERR_OK operation completed with no problems ERR _HAL_BAD_ARG returned in three situations 1 the virtual width VirtX is greater than the largest possible width VirtX varies with color depth and ranges from 4096 pixels wider than the panel at bit per pixel down to 512 pixels wider than the panel at 8 bit per pixel 2 the virtual width is less than the physical width or 3 the maximum number of lines becomes less than the physical number of lines Note The system must have been properly initialized prior to calling seVirtInit int seVirtMove int DeviID int Screen int x int y Description This routine pans and scrolls the display after a virtual displa
173. can line 199 and image 2 displaying from scan line 200 to scan line 239 Although this example picks specific values the split between image 1 and image 2 can occur anywhere on the display Scan Line 0 Image 1 Scan Line 199 Scan Line 200 Image 2 Scan Line 239 Figure 5 4 320x240 Single Panel For Split Screen In split screen operation Image 1 is taken from the display memory location pointed to by the Screen 1 Start Address registers and always is located at the top of the screen Image 2 is taken from the display memory location pointed to by the Screen 2 Start Address registers and begins after Screen 1 Vertical Size lines Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center 5 3 1 Registers Page 31 The other registers required for split screen operations REG OCh through REG ODh Screen 1 Start Word Address and REG OFh through REG 10h Screen 2 Start Word Address are described in Section 5 2 1 on page 28 REG 13 Screen 1 Vertical Size LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 14 Screen 1 Vertical Size MSB n a n a n a n a n a n a Bit 9 Bit 8 Figure 5 5 Screen 1 Vertical Size These two registers form a ten bit value which determines the size of screen 1 When the vertical size is equal to or greater than the physical number of lines being displayed there is no visible eff
174. case the DTACK signal must be made available for the SED1374 since it inserts a variable number of wait states depending upon CPU LCD synchronization and the LCD panel display mode WAIT must be inverted using an inverter enabled by CS to make it an active high signal and thus compatible with the MC68328 architecture A single resistor is used to speed up the rise time of the WAIT DTACK signal when terminating the bus cycle The following diagram shows a typical implementation of the MC68328 to SED 1374 using the Generic 1 host bus interface MC68328 A 15 0 D 15 0 CSB3 DTACK UWE LWE OE CLKO RESET SED1374 470 e AB 15 0 DB 15 0 CS WAIT WE1 WEO RD WR RD BUSCLK RESET Figure 4 2 Typical Implementation of MC68328 to SED1374 Interface Generic 1 Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 99 01 05 SED1374 X26A G 007 02 Page 14 Epson Research and Development Vancouver Design Center 4 2 SED1374 Hardware Configuration The SED 1374 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx for details The tables below show those configuration settings important to the MC68K 1 and Generic 1 host bus interfaces
175. ch and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the SED 1374 Embedded Memory Color Graphics LCD Controller and the Philips MIPS PR31500 PR31700 Processor For further information on the SED 1374 refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx For further information on the PR31500 PR31700 contact Philips or refer to the Philips website at http www philips com For further information on the ITE IT8368E refer to the IT8368E PC Card GPIO Buffer Chip Specification 1 1 General Description The Philips MIPS PR31500 PR31700 processor supports up to two PC Card PCMCIA slots It is through this host bus interface that the SED1374 connects to the PR31500 PR31700 processor The SED1374 can be successfully interfaced using one of two configurations e Direct connection to PR31500 PR31700 see Section 2 Direct Connection to the Philips PR31500 PR31700 on page 8 e System design using one ITE IT8368E PC Card GPIO buffer chip see Section 3 System Design Using the ITE ITS368E PC Card Buffer on page 10 Interfacing to the Philips MIPS PR31500 PR31700 Processor SED1374 Issue Date 98 11 09 X26A G 012 01 Page 8 EPSON Research and Development Vancouver Design Center 2 Direct Connection to the Philips PR31500 PR31700 2 1 General Description In
176. ck sizes of 2M bytes each Each has a unique fixed offset from a common programmable starting address These chip selects are well suited to typical IO addressing requirements Each chip select may be individually programmed for port size 8 16 32 bits 0 15 wait states or external acknowledge address space type burst or non burst cycle support and write protect Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 99 01 05 Epson Research and Development Vancouver Design Center 3 SED1374 Bus Interface Page 11 This section is a summary of the host bus interface modes available on the SED1374 and offers some detail on the Generic 1 host bus interface used to implement the interface to the MCF5307 3 1 Bus Interface Modes The SED 1374 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Six bus interface modes are supported Hitachi SH 4 Hitachi SH 3 Motorola MC68000 using Upper Data Strobe Lower Data Strobe Motorola MC68020 MC68030 MC683xx using Data Strobe DSACKx Generic 1 Chip Select plus individual Read Enable Write Enable for each byte Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte The SED 1374 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After re
177. connected to IO Vpp when unused See LCD Interface Pin Mapping for summary FPFRAME 39 CN3 Frame Pulse SED1374 X26A A 001 02 Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Page 21 i l RESET ae Pin Name Type Pin Cell State Description FPLINE O 38 CN3 0 Line Pulse FPSHIFT O 28 CN3 0 Shift Clock 0 if CNF4 1 LCDPWR O 43 CO1 1 if CNF4 0 LCD Power Control This pin has multiple functions TFT MD TFD Display Enable DRDY DRDY O 42 CN3 0 LCD Backplane Bias MOD e Second Shift Clock FPSHIFT2 See LCD Interface Pin Mapping for summary 5 2 3 Clock Input Pin Name Type Pin Driver Description CLKI 51 C Input Clock 5 2 4 Miscellaneous s RESET er Pin Name Type Pin Cell State Description These inputs are used to configure the SED1374 see CNF 4 0 45 46 47 As setby Summary of Configuration Options 48 49 hardware Must be connected directly to IO Vpp or Vss vo es This pin has multiple functions see REG O3h bit 2 GPIOO i 22 181 Input e General Purpose Input Output pin e Hardware Power Save TESTEN l 44 CD High Test Enable input This input must be connected to Vss Impedance 5 2 5 Power Supply Pin Name Type Pin Driver Description COREVDD P l ze th P Core Vpp IOVDD
178. crolling is performed manually defaults to virtual width physical width x 2 and maximum virtual height panning and scrolling is performed automatically specifies the virtual display width which includes both on screen and off screen size the maximum virtual display width for each display mode is 1 bpp 4096 pixels 2 bpp 2048 pixels 4 bpp 1024 pixels 8 bpp 512 pixels The following keyboard commands are for navigation within the program Manual mode Automatic mode any key Both modes 2 y ES En HOME END b ESC scrolls up scrolls down pans to the left pans to the right moves the display screen so that the upper right of the virtual screen shows in the upper right of the display moves the display screen so that the lower left of the virtual screen shows in the lower left of the display changes the direction of screen changes the color depth bits per pixel exits 1374VIRT 1374VIRT Display Utility Issue Date 98 10 20 Epson Research and Development Page 5 Vancouver Design Center 1374VIRT Example 1 Type 1374virt a to automatically pan and scroll 2 Press b to change the bits per pixel from 1 bit per pixel to 2 bits per pixel 3 Repeat steps 1 and 2 for the remaining color depths 4 and 8 bit per pixel 4 Press lt ESC gt to exit the program Program Messages ERROR Too many devices registered There are too many display devices attached to the
179. cted See Table 8 1 Panel Data Format below SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Page 55 bit 4 FPLINE Polarity This bit controls the polarity of FPLINE in TTFT MD TFD mode no effect in passive panel mode When this bit 0 FPLINE is active low When this bit 1 FPLINE is active high bit 3 FPFRAME Polarity This bit controls the polarity of FPFRAME in TFT MD TFD mode no effect in passive panel mode When this bit 0 FPFRAME is active low When this bit 1 FPFRAME is active high bit 2 Mask FPSHIFT FPSHIFT is masked during non display periods if either of the following two criteria is met 1 Color passive panel is selected REG O1h bit 5 1 2 This bit REG O1h bit 2 1 bits 1 0 Data Width Bits 1 0 These bits select the display data format See Table 8 1 Panel Data Format below Table 8 1 Panel Data Format Data Width Data Width Alea escena e G Function REG 01h bit 1 REG O1h bit 0 F 0 Mono Single 4 bit passive LCD 1 Mono Single 8 bit passive LCD 0 reserved 1 reserved g 0 reserved 1 Mono Dual 8 bit passive LCD f 0 reserved 1 reserved 0 0 Color Single 4 bit passive LCD 1 Color Single 8 bit passive LCD format 1 j 0 reserved 1 Color Single 8 bit passive LCD format 2 0 reserved a j 1 Color Dual 8 bit passive LCD f 0 reserve
180. d 1 reserved 0 9 bit TFT MD TFD panel 1 X don t care 1 12 bit TFT MD TFD panel Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Epson Research and Development Vancouver Design Center Page 56 REG 02h Mode Register 1 Address FFE2h Read Write Hardware Video Invert Enable Input Clock divide CLKI 2 Software Video Invert Frame Repeat Bit Per Pixel Bit 1 Bit Per Pixel Bit O High Performance Display Blank bits 7 6 Bit Per Pixel Bits 1 0 These bits select the color or gray shade depth Display Mode Table 8 2 Gray Shade Color Mode Selection Color Mono REG 01h bit 6 Bit Per Pixel Bit 1 REG 02h bit 7 Bit Per Pixel Bit 0 Display Mode REG 02h bit 6 0 0 2 Gray shade 1 bit per pixel 4 Gray shade 2 bit per pixel 16 Gray shade 4 bit per pixel reserved 2 Colors 1 bit per pixel 4 Colors 2 bit per pixel 16 Colors 4 bit per pixel alO 2a O O _ 256 Colors 8 bit per pixel bit 5 High Performance Landscape Modes Only When this bit 0 the internal Memory clock MCLK is a divided down version of the Pixel clock PCLK The denominator is dependent on the bit per pixel mode see the table below Table 8 3 High Performance Selection BPP Bit 1 BPP Bit 0 Display Modes MCIk PCIk 8 MCIk PCIk 4 MCIk
181. d on this pin is used to configure Configuration Pin 1 10 Vpp 0 Vss Generic 1 Big Endian CNF 2 0 configuration for Philips PR31500 PR31700 host bus interface When the SED 1374 is configured for Generic 2 interface the host interface pins are mapped as in the table below Table 2 2 SED1374 Generic 2 Interface Pin Mapping Pin Name Pin Function WE1 BHE BS Connect to lO Vpp RD WR _ Connect to lO Vpp RD RD WEO WE Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 98 11 09 SED1374 X26A G 012 01 Page 10 EPSON Research and Development Vancouver Design Center 3 System Design Using the ITE IT8368E PC Card Buffer If the system designer uses the ITE IT8368E PC Card and multiple function I O buffer the SED1374 can be interfaced so that it shares a PC Card slot The SED1374 is mapped to a rarely used 16M byte portion of the PC Card slot buffered by the IT8368E This makes the SED 1374 virtually transparent to PC Card devices that use the same slot 3 1 Hardware Description The ITE8368E has been specially designed to support EPSON LCD controllers The ITE IT8368E provides eleven Multi Function IO pins MFIO Configuration registers may be used to allow these MFIO pins to provide the control signals required to implement the SED1374 CPU interface The PR31500 PR31700 processor only provides addresses A 12 0 therefore devices
182. dd data byte appears on data bus lines D 7 0 If both CE1 and CE2 are driven low a 16 bit word transfer takes place If only CE2 is driven low an odd byte transfer occurs on data lines D 15 8 Interfacing to the PC Card Bus X26A G 009 02 Issue Date 98 12 10 Epson Research and Development Page 9 Vancouver Design Center During a read cycle OE output enable is driven low A write cycle is specified by driving OE high and driving the write enable signal WE low The cycle can be lengthened by driving WAIT low for the time needed to complete the cycle Figure 2 1 and Figure 2 2 illustrate typical memory access cycles on the PC Card bus A 25 0 REG CE1 CE2 OE WAIT D 15 0 ADDRESS VALID Hi Z Hi Z DATA VALID Transfer Start Transfer Complete Figure 2 1 PC Card Read Cycle A 25 0 REG CE1 CE2 OE WE WAIT D 15 0 ADDRESS VALID Hi Z Hi Z DATA VALID Transfer Start Transfer Complete Figure 2 2 PC Card Write Cycle Interfacing to the PC Card Bus SED1374 Issue Date 98 12 10 X26A G 009 02 Page 10 3 SED1374 Bus Interface Epson Research and Development Vancouver Design Center This section is a summary of the host bus interface modes available on the SED1374 and offers some detail on the Generic 1 host bus interface used to implement the inte
183. ddr Bit 10 Start Addr Bit 9 Start Addr Bit 8 Figure 5 6 Screen 2 Start Address Registers In landscape mode these two registers form the offset to the word in display memory to be displayed immediately after the screen 1 area of display memory Changing these registers by one will shift the display 2 to 16 pixels depending on the current color depth Split screen operation is not supported in SwivelView mode leaving this register un used Refer to Table 5 1 Number of Pixels Panned Using Start Address on page 28 to see the minimum number of pixels affected by a change of one to these registers 5 3 2 Examples SED1374 X26A G 002 02 Example 5 Display 200 scanlines of image 1 and 40 scanlines of image 2 Image 2 is located first offset 0 in the display buffer followed immediately by im age 1 Assume a 320x240 display and a color depth of 4 bpp Calculate the Screen 1 Vertical Size register values vertical_size 200 C8h Write the Vertical Size LSB REG 13h with C8h and Vertical Size MSB REG 14h with a OOh Calculate the Screen 1 Start Word Address register values Screen 2 is located first in display memory therefore we must calculate the number of bytes taken up by the screen 2 data bytes_per_line pixels_per_line pixels_per_byte 320 2 160 total bytes bytes_per_line x lines 160 x 40 6400 Screen 2 requires 6400 bytes 0 to 6399 therefore the start address offset
184. der data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Note In an 8 bit environment D 7 0 must also be connected to D 15 8 respectively see Figure 4 1 Typical Implementation of an 8 bit Processor to the SED 1374 Generic 2 Interface e Chip Select CS is driven by decoding the high order address lines to select the proper memory address space BHE WE1 is the high byte enable for both read and write cycles Note In an 8 bit environment this signal is driven by inverting address line AO thus indicating that odd addresses are to be R W on the high byte of the data bus e WEO is the enable signal for a write access to be driven low when the host CPU is writing the 1374 memory or registers e RD is the read enable for the SED1374 to be driven low when the host CPU is reading data from the SED1374 e WAIT is a signal which is output from the SED1374 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1374 may occur asynchronously to the display update it is possible that contention may occur in accessing the 1374 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high e The Bus Statu
185. dress Bits 14 0 These bits determine the word address of the start of Screen 2 in landscape modes or the byte address of the start of Screen 2 in Swivel View modes Screen 2 Start Address Bit 15 This bit is for Swivel View mode only and has no effect in Landscape mode REG 12h Memory Address Offset Register Address FFF2h Read Write Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3 Offset Bit 2 Offset Bit 1 Offset Bit 0 bits 7 0 Memory Address Offset Bits 7 0 Landscape Modes Only This register is used to create a virtual image by setting a word offset between the last address of one line and the first address of the following line If this register is not equal to zero then a virtual image is formed The displayed image is a window into the larger vir tual image See Figure 8 1 Screen Register Relationship Split Screen on page 64 This register has no effect in Swivel View modes See REG 1Ch Line Byte Count Regis ter for SwivelView Mode on page 69 SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Page 63 REG 13h Screen 1 Vertical Size Register LSB Address FFF3h Read Write Screen 1 Screen 1 Scre
186. dress and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space WE1F is the high byte enable for both read and write cycles and WEO is the enable signal for a write access These must be generated by external decode hardware based upon the control outputs from the host CPU RD is the read enable for the SED1374 to be driven low when the host CPU is reading data from the SED1374 RD must be generated by external decode hardware based upon the control outputs from the host CPU WAIT is a signal which is output from the SED1374 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1374 may occur asynchronously to the display update it is possible that contention may occur in accessing the 1374 internal registers and or Interfacing to the NEC VR4102 Microprocessor SED1374 Issue Date 99 01 05 X26A G 008 04 Page 12 SED1374 X26A G 008 04 Epson Research and Development Vancouver Design Center refresh memory The WAIT line resolves these contentions by forcing the
187. during memory accesses BCLK can be shut down between accesses allow eight BCLK pulses plus 12 MCLK pulses 8Tecik 12Tucux after the last access before shutting BCLK off Allow one BCLK pulse after starting up BCLK before the next access Required Can be stopped after 128 frames from Software Power Save Required entering Software Power Save i e after REG 03h bits 1 0 11 Uardware Power Save Not Required Can be stopped after 128 frames from entering Hardware Power Save Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Page 88 14 Mechanical Data Epson Research and Development Vancouver Design Center QFP14 80 pin PEA 0 4 e 14 0 R 0 1 le 12 0 i 60 41 A A 61 40 Y o o o a oe Index 80 21 y
188. e 10 ns Note CLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 31 Vancouver Design Center 7 1 4 Motorola M68K 2 Interface Timing Telk r pf TE E E A 15 0 CS VALID SIZO SIZ1 R W AS t3 gt t4 t6 t5 A gt j DSACK1 ae HA t7 18 D 31 16 Hi Z Hi Z write VALID t9 t10 lt _____ gt D 31 16 Hi Z ry Hi Z read VALID Figure 7 4 M68K 2 Timing MC68030 Table 7 4 M68K 2 Timing MC68030 Symbol Parameter Min Max Units folk Bus Clock frequency 0 33 MHz TeLk Bus Clock period Ye t1 A 15 0 CS SIZO SIZ1 valid before AS falling edge 0 ns t2 A 15 0 CS SIZO SIZ1 hold from ASH DS rising edge 0 ns t3 AS low to DSACK1 driven high 22 ns t4 CLK to DSACK1 low 18 ns t5 AS high to DSACK1 high 26 ns t6 AS high to DSACK1 high impedance TeLk t7 DS falling edge to D 31 16 valid write cycle Tetk 2 t8 AS DS rising edge to D 31 16 invalid write cycle 0 ns t9 D 31 16 valid to DSACK1 low read cycle 0 ns t10 AS DS rising edge to D 31 16 high impedance 20 ns Note CLK may be turned off held low between accesses see Section 13 5 Turning
189. e configuration For details on configuration refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx The table below shows those configuration settings relevant to the direct connection approach Table 2 1 SED1374 Configuration for Direct Connection SED1374 Value hard wired on this pin is used to configure Configuration Pin 1 10 Vpp 0 Vss Generic 1 Big Endian CNF 2 0 configuration for Toshiba TX3912 host bus interface When the SED 1374 is configured for Generic 2 interface the host interface pins are mapped as in the table below Table 2 2 SED1374 Generic 2 Interface Pin Mapping Pin Name Pin Function WE1 BHE BS Connect to lO Vpp RD WR _ Connect to lO Vpp RD RD WEO WE Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 98 11 09 SED1374 X26A G 004 01 Page 10 EPSON Research and Development Vancouver Design Center 3 System Design Using the ITE IT8368E PC Card Buffer If the system designer uses the ITE IT8368E PC Card and multiple function I O buffer the SED1374 can be interfaced so that it shares a PC Card slot The SED1374 is mapped to a rarely used 16M byte portion of the PC Card slot buffered by the IT8368E This makes the SED 1374 virtually transparent to PC Card devices that use the same slot 3 1 Hardware Description The ITE8368E has been specially designed to sup
190. e following line only device c himem sys 3 Edit AUTOEXEC BAT on the hard drive to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c wince release nk bin 4 Confirm that NK BIN is located in c wince release 5 Reboot the system from the hard drive Windows CE Display Drivers SED1374 Issue Date 98 11 11 X26A E 001 01 Page 6 Epson Research and Development Vancouver Design Center 1 4 Comments e At the time of this printing the drivers have been tested on the x86 CPUs and have only been run with version 2 0 of the ETK We are constantly updating the drivers so please check our website at www erd epson com or contact your Seiko Epson or Epson Electronics America sales representative SED1374 Windows CE Display Drivers X26A E 001 01 Issue Date 98 11 11 EPSON SED1374 Embedded Memory Color LCD Controller SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 01 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your ownuse in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and o
191. e implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the Motorola MPC821 Microprocessor SED1374 Issue Date 99 01 05 X26A G 010 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2 1 The MPC8xx System Bus The MPC8xx family of processors feature a high speed synchronous system bus typical of modern RISC microprocessors This section provides an overview of the operation of the CPU bus in order to establish interface requirements 2 2 MPC821 Bus Overview The MPC8xx microprocessor family uses a synchronous address and data bus All IO is synchronous to a square wave reference clock called MCLK Master Clock This clock runs at the machine cycle speed of the CPU core typically 25 to 50 MHz Most outputs from the processor change state on the rising edge of this clock Similarly most inputs to the processor are sampled on the rising edge Note The external bus can run at one half the CPU core speed using the clock control register This is typically used when the CPU core is operated above 50 MHz The MPC821 can generate up to eight independent chip select outputs each of which may be controlled
192. e period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 0 5 Ts t9 Shift Pulse period 1 Ts t10 Shift Pulse pulse width low 0 5 Ts t11 Shift Pulse pulse width high 0 5 Ts t12 FPDAT 7 4 setup to Shift Pulse falling edge 0 5 Ts t13 FPDAT 7 4 hold to Shift Pulse falling edge 0 5 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 tmin t8min 9TS 3 t3min REG 04h bits 6 0 1 x 8 REG 08h bits 4 0 4 x 8 Ts 4 t6min REG 08h bits 4 0 x 8 0 5 Ts 5 t min REG 08h bits 4 0 x 8 9 5 Ts SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 43 Vancouver Design Center 7 3 6 Single Color 8 Bit Panel Timing Format 1 r VDP gt VNDP FPFRAME pE FPLINE __ l ll j e l l l l FPDAT 7 0 LINE1 X LINE2 X LINES X LINE4 X XLINE479XLINE480 LINE1 X LINE2 X FPLINE l FPSHIFT ei A eee a HDP HNDP ja lt FPSHIFT 2 E FPDAT7 B TRI 1G1 Y 1G6 X 1B6 X1B1X 1R Y RBA FPDAT6 e 181 X 1 R2 X 1 R7 X 1 07 X1 G12X 1 B12 4
193. eady exist and be an SED1374 HAL based program 1374CFG is cannot save to a non existent program If 1374CFG is unable to locate the HAL information in the file being saved to the following dialog box is displayed 1374CFG ERROR Unable to locate HAL information this file is not configurable Figure 11 ERROR Unable to read HAL Help Clicking on the Help button will start the help file for SED1374CFG Exit Clicking on the Exit button exits 1374CFG immediately The user is not prompted to save any changes they may have made 1374CFG EXE Configuration Program SED1374 Issue Date 98 10 27 X26A B 001 01 Page 16 Comments SED1374 X26A B 001 01 Epson Research and Development Vancouver Design Center It is assumed that the 1374CFG user is familiar with SED1374 hardware and software Refer to the SED1374 Functional Hardware Specification drawing office number X22A A 001 xx and the SED 1374 Programming Notes and Examples manual drawing office number X22A G 002 xx for information 1374CFG EXE Configuration Program Issue Date 98 10 27 EPSON SED1374 Embedded Memory Color LCD Controller 1374SHOW Demonstration Program Document No X26A B 002 01 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may
194. econds time to delay in seconds ERR_OK operation completed with no problems ERR_FAILED returned on non PC platforms when the SED 1374 registers have not bee initialized int seGetLastUsableByte int DeviD long plLastByte Description Parameters Programming Notes and Examples Issue Date 99 04 27 This functions returns a pointer as a long integer to the last byte of usable display memory This function is a holdover from 135X products which support different amounts of memory DevID registered device ID plLastByte pointer to a long integer to receive the offset to the last byte of display memory SED1374 X26A G 002 02 Page 52 Return Value Epson Research and Development Vancouver Design Center ERR_OK operation completed with no problems int seSetHightPerformance int DeviD BOOL OnOff Description Parameters Return Value This function call enables or disable the high performance bit of the SED1374 When high performance is enabled then MCIk equals PCIk for all video display resolutions In the high performance state CPU to video memory performance is improved at the cost of higher power consumption When high performance is disabled then MClk ranges from PCIk 1 at 8 bit per pixel to PCIK 8 at 1 bit per pixel Without high performance CPU to video memory accessed speeds are slower but the SED1374 uses less power DevID registered device ID OnOff a boolean value defined in HAL H to i
195. ect an passive Single Color panel with a data width of 4 bits 02 1010 0000 BO Select 4 bpp color depth and high performance 03 0000 0011 03 Select normal power operation 04 0010 0111 27 Horizontal display size Reg 04 1 8 39 1 8 320 pixels 05 11101111 EF Vertical display size Reg 06 05 1 06 0000 0000 00 0000 0000 1110 1111 1 239 1 240 lines 07 0000 0000 00 FPLINE start position not used by STN Horizontal non display period Reg 08 4 8 p 08 0001 1110 1E 30 4 8 272 pixels Frame Rate Calculation 09 0000 0000 00 FPFRAME start position not used by STN 0A 0010 0110 26 Vertical non display period REG OA 38 lines Frame Rate Calculation 0B 0000 0000 00 MOD rate not required for this panel 0C 0000 0000 00 ee fetes oe Screen 1 Start Address set to 0 for initialization Split Screen on page 30 OD 0000 0000 00 OF 0000 0000 00 a Screen 2 Start Address set to 0 for initialization 10 0000 0000 00 SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Table 2 1 SED1374 Initialization Sequence Continued Page 9 Register Value hex Notes See Also 12 0000 0000 00 Memory Address offset not virtual setup so set to O 13 1111 1111 FF f Set the vertical size to the maximum value Split Sc
196. ect on the display When the vertical size value is less than the number of physically displayed lines display operation works like this 1 From the end of vertical non display beginning of a frame to the number of lines in dicated by vertical size the display data will come from the memory pointed to by the Screen 1 Display Start Address 2 After vertical size lines have been displayed the system will begin displaying data from Screen 2 Display Start Address memory Screen 1 memory is always displayed at the top of the screen followed by screen 2 memory The start address for the screen 2 image may be lower in memory than that of screen 1 i e screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located several thousand bytes into the display buffer While not particu larly useful it is even possible to set screen 1 and screen 2 to the same address Programming Notes and Examples Issue Date 99 04 27 SED1374 X26A G 002 02 Page 32 Epson Research and Development Vancouver Design Center REG 0Fh Screen 2 Display Start Address 0 LSB Start Addr Bit 7 Start Addr Bit 6 Start Addr Bit 5 Start Addr Bit 4 Start Addr Bit 3 Start Addr Bit 2 Start Addr Bit 1 Start Addr Bit 0 REG 10h Screen 2 Display Start Address 0 LSB reserved Start Addr Bit 14 Start Addr Bit 13 Start Addr Bit 12 Start Addr Bit 11 Start A
197. ed to AB19 of the SED1374 25 GND Ground 26 GND Ground 27 VCC 5 volt supply 28 VCC 5 volt supply 29 RD WR Connected to the R W signal of the SED1374 30 BS Connected to the BS signal of the SED1374 31 BUSCLK Connected to the BCLK signal of the SED1374 32 RD Connected to the RD signal of the SED1374 33 NC Not connected 34 NC Not connected SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 Epson Research and Development Vancouver Design Center 5 Host Bus Interface Pin Mapping Table 5 1 Host Bus Interface Pin Mapping Page 13 SED1374 SH 3 SH 4 MC68K 1 MC68K 2 Generic Bus 1 Generic Bus 2 Pin Names AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO BCLK BCLK BCLK BCLK BS BS BS AS AS Connect to Vss pe to IO DD RD WR RD WR RD WR R WH R WH RD1 2e 210 DD RD RD RD ome 10 19 SIZ1 RDO RD DD WEO WEO WEO surer ae SIZO WEO WE DD WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 SED1374 X26A G 005 01 Page 14 Epson Research and Development Vancouver Design Cent
198. een 1 Start Word Address register OffsetBytes Width x BitsPerPixel 8 1 240 x 4 8 1 119 0077h Set Screen Display Start Word Address LSB REG 0Ch to 77h and Screen1 Dis play Start Word Address MSB REG ODh to 00h 2 Calculate the Line Byte Count LineByteCount Width x BitsPerPixel 8 240 x 4 8 120 78h Set the Line Byte Count REG 1C to 78h 3 Enable SwivelView mode This example uses the alternate SwivelView mode scheme We will not change the Pixel Clock Select settings Write COh to the SwivelView Mode register REG 1Bh 4 Recalculate the frame rate dependents This example assumes the alternate SwivelView mode scheme In this scheme without touching the Pixel Clock Select bits the PCLK value will be equal to CLK 2 Note These examples don t use the Pixel Clock Select bits The ability to divide the PCLK value down further than the default values was added to the SED1374 to support SwivelView mode on very small panels The Pixel Clock value has changed so we must calculate horizontal and vertical non display times to reach the desired frame rate Rather than perform the frame rate calculations here I will refer the reader to the frame rate calculations in Frame Rate Calculation on page 9 and simply arrive at the following Horizontal Non Display Period 88h Vertical Non Display Period 03h Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 44 SED
199. egister selects Auto Increment mode and sets the pointer to R 3 Subsequent accesses to the Look Up Table Data Register move the pointer onto G 3 B 3 R 4 etc Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 66 Epson Research and Development Vancouver Design Center Address FFF6h REG 16h Look Up Table Bank Select Register Read Write n a n a Red Bank Select Bit 1 Red Bank Select Bit 0 Green Bank Select Bit 1 Green Bank Select Bit 0 Blue Bank Select Bit 1 Blue Bank Select Bit 0 bits 7 6 bits 5 4 bits 3 2 bit 1 0 SED1374 X26A A 001 02 n a Red Bank Select Bits 1 0 In 1 bit per pixel bpp color mode the lower 8 positions of the Red Look Up Table is arranged into four banks each with two positions These two bits select which bank is used for display data In 2 bpp color mode the 16 position Red Look Up Table is arranged into four banks each with four positions These two bits select which bank is used for display data These bits have no effect in 4 bpp color gray modes In 8 bpp color mode the 16 position Red Look Up Table is arranged into two banks each with eight positions Red Bank Select bit 0 selects which bank is used for display data Green Bank Select Bits 1 0 In 1 bit per pixel bpp color gray mode the lower 8 positions of the Green Look Up Table is arranged into four banks each wi
200. ek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1374 X26A G 009 02 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the PC Card Bus X26A G 009 02 Issue Date 98 12 10 EPSON SED1374 Embedded Memory Color LCD Controller Interfacing to the Motorola MPC821 Microprocessor Document Number X26A G 010 02 Copyright O 1998 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 02 Issue Date 99 01 05 Epson Research and Development Page 3 Vancouver Design Center Table of Contents At introduction aretes es Gee OA dee ed O de Guest 7 2 Interfacing to the MPG821 ocio e Bee a Re eS es 8 2 1 The
201. els When this bit 1 an internal frame counter runs from 0 to 3FFFFh When the frame counter rolls over the modulated image pattern is repeated every 1 hour when the frame rate is 72Hz When this bit 0 the modulated image pattern is never repeated bit 1 Hardware Video Invert Enable In passive panel modes REG O1h bit 7 0 FPDAT11 is available as either GPIO4 or hardware video invert When this bit 1 Hardware Video Invert is enabled via the FPDAT11 pin When this bit 0 FPDAT11 operates as GPIO4 See Table 8 4 Inverse Video Mode Select Options below Note Video data is inverted after the Look Up Table bit 0 Software Video Invert When this bit 1 Inverse video mode is selected When this bit 0 standard video mode is selected See Table 8 4 Inverse Video Mode Select Options below Note Video data is inverted after the Look Up Table Table 8 4 Inverse Video Mode Select Options Software Video FPDAT11 Hardware Video Invert 5 Passive Panels Video Data Invert Enable Passive and Only Active Panels y 0 0 x Normal 0 1 x Inverse 1 X 0 Normal 1 X 1 Inverse Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 58 Epson Research and Development Vancouver Design Center REG 03h Mode Register 2 Address FFE3h Read Write Hardware Software Software Beem n a n a n a bi Power Save Power Save Power Save yp Enable Bit 1
202. em Qty board Designation Part Value Description 1 13 C1 C11 C15 C16 0 1uF 5 50V 0805 ceramic capacitor 2 1 C12 1uF 10 16V Tantalum capacitor size A 3 2 C13 C14 10uF 10 25V Tantalum capacitor size D 4 2 C17 C21 47uF 10 16V Tantalum capacitor size D 5 3 C18 C20 4 7uF 10 50V Tantalum capacitor size D 6 1 C22 56uF 20 63V Electrolytic radial low ESR 7 2 H1 H2 CON34A Header 0 1 17x2 header PTH 8 4 JP1 JP4 HEADER 3 0 1 1x3 header PTH 9 1 J1 AT CON A ISA Bus gold fingers 10 1 J2 AT CON B ISA Bus gold fingers 11 1 J3 AT CON C ISA Bus gold fingers 12 1 J4 AT CON D ISA Bus gold fingers 13 1 J5 CON40A Shrouded header 2x20 PTH center key 14 1 L1 1uH MCI 1812 inductor 15 3 L2 L4 Ferrite bead Philips BDS3 3 8 9 4S2 16 1 Q1 2N3906 PNP signal transistor SOT23 17 1 Q2 2N3903 NPN signal transistor SOT23 18 6 R1 R6 15K 5 0805 resistor 19 7 R7 R13 10K 5 0805 resistor 20 1 R14 470K 5 0805 resistor 21 1 R15 200K 200K Trim POT Spectrol 683S204T607 or equivalent 22 1 R16 14K 1 0805 resistor 23 2 R17 R18 1K 5 0805 resistor 24 2 R19 R20 100K 5 0805 resistor 25 1 R21 100K 100K Trim POT Spectrol 683S104T607 or equivalent 26 1 S1 SW DIP 6 6 position DIP switch 27 1 U1 SED1374F0A QFP14 80 80 pin SMT 28 1 U2 25 0 MHz oscillator FOX 25MHz oscillator or equiv 14 pin DIP socketed 29 3 U3 U5 74AHC244 SO 22 TI74AHC244 30 1 U6 LT1117CM 3 3 Linear Technology 5V to 3 3V regulator 8300mA 31 1 U7 TIBPAL16L8 15 TI PAL 20 Pin
203. en 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 14h Screen 1 Vertical Size Register MSB Address FFF4h Read Write Screen 1 Screen 1 n a n a n a n a n a n a Vertical Size Vertical Size Bit 9 Bit 8 REG 14h bits 1 0 REG 13h bits 7 0 Hardware Functional Specification Screen 1 Vertical Size Bits 9 0 This register is used to implement the Split Screen feature of the SED1374 These bits determine the height in lines of Screen 1 On reset this register is set to Oh In landscape modes if this register is programmed with a value n where n is less than the Vertical Panel Size REG 06h REG O5h then lines 0 to n of the panel contain Screen 1 and lines n 1 to REG 06h REG 05h of the panel contain Screen 2 See Figure 8 1 Screen Register Relationship Split Screen on page 64 If Split Screen is not desired this register must be programmed greater than or equal to the Vertical Panel Size REG 06h and REG 05h In Swivel View modes this register must be programmed greater than or equal to the Verti cal Panel Size REG 06h and REG O5h See SwivelView M on page 79 Issue Date 99 04 29 SED1374 X26A A 001 02 Page 64 Epson Research and Development Vancouver Design Center REG O
204. en 2 Start Word Address LSB Register 10h Screen 2 Start Word Address MSB KK Set this start address to 0 too xy SET_REG 0x0F 0x00 SET_REG 0x10 0x00 Register 12h Memory Address Offset EX Used for setting memory to a width greater than the KK display size Usually set to 0 during initialization KK and programmed to desired value later E SET_REG 0x12 0x00 Register 13h Screen 1 Vertical Size LSB Register 14h Screen 1 Vertical Size MSB Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 68 SED1374 Epson Research and Development Vancouver Design Center ER Set to maximum i e Ox3FF This register is used Ke for split screen operation and should be set to 0 ate during initialization ia SET_REG 0x13 OxFF SET_REG 0x14 0x03 Look Up Table In this example the LUT will be programmed in the register sequenc In practice the LUT would probably be done after the other registers El Register 15h Look Up Table Address Es Set to 0 to start RGB sequencing at the first LUT entry E SET_REG 0x15 0x00 Register 16h Look Up Table Bank Select ae Set all the banks to 0 AS At 4BPP this makes no difference however it will affect ER appearance at other color depths ek SET_REG 0x16 0x00 Register 17h Look
205. en the MC68328 and the SED 1374 can be implemented using either the MC68K 1 or Generic 1 host bus interface of the SED1374 4 1 1 Using The MC68K 1 Host Bus Interface The MC68328 multiplexes dual functions on some of its bus control pins specifically UDS LDS and DTACK In implementations where all of these pins are available for use as bus control pins then the SED 1374 interface is a straightforward implementation of the MC68K 1 host bus interface For further information on this host bus interface refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx The following diagram shows a typical implementation of the MC68328 to SED1374 using the MC68K 1 host bus interface MC68328 SED1374 A 15 0 AB 15 1 D 15 0 DB 15 0 CSB3 CS Vcc 470 DTACK WAIT AS BS UDS WE1 LDS ABO R W RD WR R RD CLKO BUSCLK RESET RESET TS Figure 4 1 Typical Implementation of MC68328 to SED1374 Interface MC68K 1 SED1374 X26A G 007 02 Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 99 01 05 Epson Research and Development Vancouver Design Center 4 1 2 Using The Generic 1 Host Bus Interface Page 13 If UDS and or LDS are required for their alternate IO functions then the MC68328 to SED1374 interface may be implemented using the SED1374 Generic 1 host bus interface Note that in either
206. eneric 2 host interface control signals of the SED1374 are asynchronous with respect to the SED1374 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum SED1374 clock frequencies The SED1374 also has internal clock dividers providing additional flexibility Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 98 11 09 EPSON Research and Development Vancouver Design Center 2 2 Memory Mapping and Aliasing Page 9 The SED1374 requires an addressing space of 64K bytes The on chip display memory occupies the range 0 through 9FFFh The registers occupy the range FFEOh through FFFFh The TX3912 demultiplexed address lines A16 and above are ignored thus the SED 1374 is aliased 1024 times at 64K byte intervals over the 64M byte PC Card slot 1 memory space In this example implementation the TX3912 control signal CARDREG is ignored the SED 1374 also takes up the entire PC Card slot 1 configuration space Note If aliasing is undesirable additional decoding circuitry must be added 2 3 SED1374 Configuration and Pin Mapping The SED 1374 is configured at power up by latching the state of the CNF 4 0 pins Pin BS also plays a role in host bus interfac
207. ent Number X26A A 001 xx e Epson Research and Development Inc SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx Epson Research and Development Inc SED1374 Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola Website http www mot com e Epson Research and Development Website http www erd epson com SED1374 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 02 Issue Date 99 01 05 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers SED1374 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http vww eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MC68328 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor Interfacing to the Motorola MC
208. ent color depths The data format for each color depth is packed pixel SED1374 packed pixel modes can range from one byte containing eight adjacent pixels 1 bpp to one byte containing just one pixel 8 bpp Packed pixel data memory may be envisioned as a stream of data Pixels fill this stream with one pixel packed in adjacent to the next If a pixel requires four bits then it will be located in the four most significant bits of a byte The pixel to the immediate right on the display will occupy the lower four bits of the same byte The next two pixels to the immediate right are located in the following byte etc 3 1 Display Buffer Location The SED1374 contains 40 kilobytes of internal display memory External support logic must be employed to determine the starting address for this display memory in CPU address space On the SDU1374BO0C PC platform evaluation boards the address is usually fixed at DO0000h 3 1 1 1 Bit Per Pixel 2 Colors Gray Shades 1 bit pixels support two color gray shades In this memory format each byte of display buffer contains eight adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out appropriate bits and if necessary setting bits to 1 With color panels the two colors are derived by indexing into positions 0 and 1 of the Look Up Table For monochrome panels the two gray shades are generated by indexing into the first two elements of the green component of the Look Up T
209. ent to the file results Example 1 The script file dumpregs scr can be created with and text editor and will look like the following This file initializes the SED1374 and reads the registers i i Initialize the registers Xa Dump all the registers la And the LUT q Exit e All numeric values are considered to be hexadecimal unless identified otherwise For example 10 10h 16 decimal 10t 10 decimal 010b 2 decimal e Redirecting commands from a script file PC platform allows those commands to be executed as though they were typed 1374PLAY Diagnostic Utility Issue Date 99 11 29 Epson Research and Development Page 7 Vancouver Design Center Program Messages 1374PLAY Diagnostic Utility Issue Date 99 11 29 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 1374 device A 1374 device was not found at the configured addresses Check the configuration address using the 1374CFG configuration program WARNING Did not detect 1374 The HAL did not detect an SED 1374 however 1374PLAY will continue to function SED1374 X26A B 005 02 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374PLAY Diagnostic Utility X26A B 005 02 Issue Date 99 11 29 EPSON SED1374 Embedded Memory Color LCD Controller 1374BMP Demonstration Progr
210. enter 1 SED1374 Power Consumption Power Consumption Issue Date 98 10 27 SED1374 power consumption is affected by many system design variables Input clock frequency CLKI the CLKI frequency and the internal clock divide register deter mine the operating clock CLK frequency of the SED1374 The higher CLK is the higher the frame fate performance and power consumption CPU interface the SED1374 current consumption depends on the BUSCLK frequency data width number of toggling pins and other factors the higher the BUSCLK the higher the CPU performance and power consumption Vpp Voltage levels Core and IO the voltage level of the Core and IO sections in the SED1374 affects power consumption the higher the voltage the higher the consumption Display mode the resolution panel type and color depth affect power consumption The higher the resolution color depth and number of LCD panel signals the higher the power consumption Note If the High Performance option is turned on the power consumption increases to that of 8 bit per pixel mode for all color depths There are two power save modes in the SED1374 Software and Hardware Power Save The power consumption of these modes is affected by various system design variables e CPU bus state during Power Save the state of the CPU bus signals during Power Save has a substantial effect on power consumption An inactive bus e g BUSCLK low Addr low etc reduces ov
211. er 6 Technical Description 6 1 ISA Bus Support This board has been designed to support the 16 bit ISA bus environment and can be used in conjunction with either a VGA or a monochrome display adapter card There are 5 configuration inputs associated with the Host Interface CNF 3 0 and BS Refer to Table 2 3 Jumper Settings and Table 5 1 Host Bus Interface Pin Mapping for complete details 6 1 1 Display Adapter Card Support When using the SDU1374B0B in conjunction with another primary Display Adapter VGA or Monochrome the following applies ISA or VL Bus VGA Display Adapter When the SDU1374B0B board is used with an ISA or VL Bus VGA display adapter the VGA card must have a 16 bit BIOS to prevent conflicts during 16 bit accesses MEMCS 16 If an 8 bit VGA adapter card is installed in the system being used it must be removed and the screen display routed through a COM port to a terminal display device PCI Bus VGA Display Adapter All PCI based VGA display adapters can be used in conjunction with the SDU1374B0C board Monochrome Display Adapter All monochrome display adapters can be used in conjunction with the SDU1374B0C board 6 1 2 Expanded Memory Manager If a memory manager is being used for system memory the address range DOOOOh to DFFFFh must be excluded from use as this range is used by the SDU1374B0C SED1374 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 01 Issue Date
212. erall system power consumption e CLKI state during Power Save disabling the CLKI during Power Save has substantial power savings SED1374 X26A G 006 01 Page 4 Epson Research and Development Vancouver Design Center 1 1 Conditions Table 1 1 SED1374 Total Power Consumption below gives an example of a specific environment and its effects on power consumption Table 1 1 SED1374 Total Power Consumption Test Condition Re ere Power Consumption Core Vpp 3 3V IO Vpp 3 3V oret Active Power Save Mode PUSOLK Ae Core IO Total Software Hardware Input Clock 6MHz Black and White 5 29mW 0 3mW 5 59mW 1 LCD Panel 320x240 4 bit Single 4 Gray Shades 6 88mW 0 43mW 7 29mW 1 58mw 1 19mw Monochrome 16 Gray Shades 8 15mW 0 55mW 8 70mW Input Clock 6MHz 2 Colors 6 82mW 1 13mW 7 95mW 2 LCD Panel 320x240 4 bit Single Color 4 Colors 7 58mW 2 29mW 9 86mW 1 58mw 1 19mw 16 Colors 8 98mW 2 25mW 11 23mW Input Clock 25MHz 3 LCD Panel 640x480 8 bit Single Black and White 21 38mW 0 92mW 22 30mW 3 09mw 2 71mW Monochrome Input Clock 25MHz 1 2 4 LCD Panel 640x480 8 bit Single Color 2 Colors 23 66mW 2 40mW 26 07mW 3 09mW 2 71mW Input Clock 25MHz 5 LCD Panel 640x480 8 bit Dual Black and White 20 93mW 0 88mW 21 81mW 3 09mw 2 71mW Monochrome Input Clock 25MHz 6 LCD Panel 640x480 8 bit Dual Color 2 Colors 23 78mW
213. eration completed with no problems The Drawing routines cover HAL functions that deal with displaying pixels lines and shapes int seDrawLine int DevID int x1 int y1 int x2 int y2 DWORD Color Description This routine draws a line on the display from the endpoints defined by x1 y1 to the endpoint x2 y2 in the requested Color Currently seDrawLine only draws horizontal and vertical lines Parameters Device registered device ID xl yl first endpoint of the line in pixels x2 y2 second endpoint of the line in pixels see note below Color color to draw with Color is an index into the LUT Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 59 int seDrawRect int DeviD long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill Description Parameters This routine draws and optionally fills a rectangular area of display buffer The upper right corner is defined by x1 y1 and the lower right corner is defined by x2 y2 The color defined by Color applies both to the border and to the optional fill DevID registered device ID xl yl top left corner of the rectangle in pixels x2 y2 bottom right corner of the rectangle in pixels Color The color to draw the rectangle outline and fill with Color is an index into the Look Up Table SolidFill Flag whether to f
214. erd epson com Interfacing to the Motorola MPC821 Microprocessor SED1374 Issue Date 99 01 05 X26A G 010 02 Page 24 7 Technical Support 7 1 EPSON LCD CRT Controllers SED1374 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http Awww eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MPC821 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor SED1374 X26A G 010 02 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MPC821 Microprocessor Issue Date 99 01 05 EPSON SED1374 Embedded Memory Color LCD Controller Interfacing to the Motorola MC
215. ernal CLKI 2 and the various PCLK and MCLK dividers for portrait mode A socket for an external oscillator is also provided if a different frequency is required This option is selected by positioning jumper JP8 in the 2 3 position and adding a standard 14 DIP type oscillator in the socket U10 4 2 LCD Connectors 4 2 1 50 pin LCD Module Connector J3 X00A G 004 01 The standard connector used on Toshiba s CPU Modules to connect to the LCD module is included in this CPU module All twelve LCD data lines FPDAT 11 0 from the SED1374 75 as well as the five video control signals FPFRAME FPSHIFT FPLINE DRDY LCDPWR are passed through this connector Through this connector the SED 1374 75 supports monochrome and color STN panels up to a resolution of 640x480 as well as color TFT D TFT up to a resolution of 640x480 All touch panel signals from the main board have also been routed through this connector SDU1374 75 TMPR3912 22U CPU Module Issue Date 98 12 23 EPSON Research and Development Page 13 Vancouver Design Center 4 2 2 Standard Epson LCD Connector J4 A shrouded 40 pin header J4 is also added to the CPU module to connect to LCD panels This header is the standard LCD connector used on Epson Research and Development evaluation boards and can be used to directly connect LCD panels to the SED1374 75 controller All LCD signals are buffered to allow 3 3V or 5 0V logic LCD panels to be connected Jumper JP9 selects between
216. esign Center 2 Interfacing to an 8 bit Processor 2 1 The Generic 8 bit Processor System Bus SED1374 X26A G 013 01 Although the SED1374 does not directly support an 8 bit CPU with minimal external logic an 8 bit interface can be achieved Typically the bus of an 8 bit microprocessor is straight forward with minimal CPU and system control signals To connect a memory mapped device such as the SED 1374 only the write read and wait control signals as well as the data and address lines need to be interfaced Since the SED1374 is a 16 bit device some external logic is required Interfacing to an 8 bit Processor Issue Date 99 05 04 Epson Research and Development Page 9 Vancouver Design Center 3 SED1374 Bus Interface This section is a summary of the host bus interface modes available on the SED1374 and offers some detail on the Generic 2 Host Bus Interface used to implement the interface to an 8 bit processor The SED1374 provides a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The bus interface mode used in this example is e Generic 2 this bus interface is ISA like and can easily be modified to support an 8 bit CPU 3 1 Host Bus Pin Connection The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping
217. essible when CS 0 and AB 15 0 are in the range FFEOh through FFFFh 8 2 Register Descriptions Unless specified otherwise all register bits are reset to O during power up REG 00h Revision Code Register Address FFEOh Read Only Product Code Product Code Product Code Product Code Product Code Product Code Revision Revision Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Code Bit 1 Code Bit 0 bits 7 2 Product Code This is a read only register that indicates the product code of the chip The product code is 000110 bits 1 0 Revision Code This is a read only register that indicates the revision code of the chip The revision code is 00 REG 01h Mode Register 0 Address FFE1h Read Write FPLine FPFrame Mask Data Width Data Width TEESE i DuarSingie i Polarity Polarity FPSHIFT Bit 1 Bit 0 bit 7 TFT STN When this bit 0 STN passive panel mode is selected When this bit 1 TFT MD TFD panel mode is selected If TFT MD TFD panel mode is selected Dual Single REG 01h bit 6 and Color Mono REG 01h bit5 are ignored See Table 8 1 Panel Data Format below bit 6 Dual Single When this bit 0 Single LCD panel drive is selected When this bit 1 Dual LCD panel drive is selected See Table 8 1 Panel Data Format below bit 5 Color Mono When this bit 0 Monochrome LCD panel drive is selected When this bit 1 Color LCD panel drive is sele
218. f the lookup address and the LUT Address is incre mented Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Look Up Table Address Page 15 The Look Up Table LUT consists of 16 indexed entries each consisting three 4 bit elements red green blue The LUT Address bits select which of the 16 entries is accessed Upon setting the LUT Address an internal pointer is set to the red element Dependent on the RGB Index setting one to three accesses of the Look Up Table Data register cause the LUT Address to automatically increment to the next index REG 16h Look Up Table Bank Select Register Read Write aia wa Red Bank Red Bank Green Bank Green Bank Blue Bank Blue Bank Select bit 1 Select bit 0 Select bit 1 Select bit 0 Select bit 1 Select bitO Look Up Table Bank Select The Look Up Table Bank Select register affects displayed colors Depending on the color mode not all of the sixteen Look Up Table LUT entries are required This register determines which entries will be displayed At 1 bpp only the lower eight Look Up Table addresses are used These are further divided into four banks of two colors The bank selects determine which of the four red green and blue banks the displayed colors will come from For instance Assume the Look Up Table Bank Select register was set to 18h 0001 1000 b Red pixels would come from the 2nd red lookup ban
219. facing to the Motorola MC68328 Dragonball Microprocessor SED1374 Issue Date 99 01 05 X26A G 007 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Motorola MC68328 Dragonball Microprocessor X26A G 007 02 Issue Date 99 01 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to provide an interface between the SED1374 Embedded Memory LCD Controller and the Motorola MC68328 Dragonball Microprocessor By implementing a dedicated display refresh memory the SED1374 can reduce system power consumption improve image quality and increase system perfor mance as compared to the Dragonball s on chip LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the Motorola MC68328 Dragonball Microprocessor SED1374 Issue Date 99 01 05 X26A G 007 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MC68328 2 1 The MC68328 System
220. g address of the block The chip select should have its RO Read Only bit set to 0 and the WAIT field Wait states should be set to 111b to allow the SED 1374 to terminate bus cycles externally Interfacing to the Motorola MC68328 Dragonball Microprocessor Issue Date 99 01 05 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1374 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1374CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1374 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www erd epson com Interfacing to the Motorola MC68328 Dragonball Microprocessor SED1374 Issue Date 99 01 05 X26A G 007 02 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Motorola Inc MC68328 DragonBall Integrated Microprocessor User s Manual Motorola Publication no MC68328UM AD available on the Internet at http www mot com SPS WIRELESS products MC68328 html e Epson Research and Development Inc SED1374 Hardware Functional Specification Docum
221. g data from the SED1374 These signals must be generated by external hardware based on the control outputs from the host CPU e WAIT is a signal output from the SED1374 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1374 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1374 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the SED1374 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 99 01 05 Epson Research and Development Page 13 Vancouver Design Center 4 MCF5307 To SED1374 Interface 4 1 Hardware Description The SED1374 is interfaced to the MCF5307 with a minimal amount of glue logic One inverter is required to change the polarity of the WAIT signal which is an active low signal to insert wait states in the bus cycle while the MCF5307 s Transfer Acknowledge signal TA is an active low signal to end the current bus cycle The inverter is enabled by CS so that TA is n
222. gnificant bits form the product revision From reset power on the steps to identifying the SED1374 are as follows 1 Read REG 00h Mask off the lower two bits the revision code to obtain the product code 2 The product code for the SED1374 is 018h SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Page 47 Vancouver Design Center 9 Hardware Abstraction Layer HAL 9 1 Introduction The HAL is a processor independent programming library provided by Epson with support for several different computing platforms The HAL was developed to aid implementation of internal test programs and provides an easy consistent method of programming SED135x SED137x and SED138x products on different processor platforms The HAL keeps sample code simpler although end programmers may find the HAL functions to be limited in their scope and may wish to ignore the HAL 9 2 API for 1374HAL The following is a description of the HAL library Updates and revisions to the HAL may include new functions not included in the following documentation The original design philosophy of the HAL was that function return values would be status of the call Most functions simple return ERR_OK If a value had to be returned then a pointer of the appropriate type was passed to the function 9 2 1 Initialization The following section describes the HAL functions dealing with SED1374 initialization Typic
223. h gt Look up table for 4 bpp color e unsigned char Color_4BPP 16 3 0x00 0x00 Ox00 BLACK 0x00 0x00 Ox0A BLUE 0x00 Ox0A 0x00 GREEN 0x00 Ox0A 0Ox0A CYAN Ox0A 0x00 0x00 RED Ox0A 0x00 0Ox0A PURPLE Ox0A OxOA 0x00 YELLOW OxOA Ox0A Ox0A WHITE 0x00 0x00 Ox00 BLACK SED1374 X26A G 002 02 xy EY Ay af ES Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center y 0x00 0x00 Ox0F 0x00 0x0F 0x00 L 0x00 OxOF OxOF L OxOF 0x00 0x00 L OxOF 0x00 0x0F L OxOF Ox0F 0x00 BLUE GREEN CYAN xd RED T PURPLE YELLOW OxOF OxOF OxOF LT WHITE Page 65 Register data for the configuratin described above Thes ay va le code uses thes unsigned char Reg 0x20 0x23 OxBO 0x03 0x00 Ox3B 0x00 0x00 0x00 OxFF 0x00 0x00 0x00 0x00 Ox1E 0x00 0x00 y Useful definitions easier to follow lues were generated using 1374CFG EXE The sampl values but does not refer to this array 0x27 OxEF 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 constants and macros to make the sample code
224. hat provide an easy interface to the CPU A 16M byte block of memory is assigned for the LCD controller with its own chip select and ready signals available Word or byte accesses are controlled by the system high byte signal SHB Interfacing to the NEC VR4102 Microprocessor X26A G 008 04 Issue Date 99 01 05 Epson Research and Development Vancouver Design Center Page 9 2 1 2 LCD Memory Access Cycles TCLK ADD 25 0 SHB LCDCS WR RD D 15 0 write D 15 0 read E A A AY E Figure 2 1 NEC VR4102 Read Write Cycles on page 9 shows the read and write cycles to the LCD Controller Interface Once an address in the LCD block of memory is placed on the external address bus ADD 25 0 the LCD chip select LCDCS is driven low The read or write enable signals RD and WR are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle The high byte enable is driven low for 16 bit transfers and high for 8 bit transfers VALID VALID Hi Z i VALID y LCDRDY Figure 2 1 NEC VR4102 Read Write Cycles Interfacing to the NEC VR4102 Microprocessor SED1374 Issue Date 99 01 05 X26A G 008 04 Page 10 3 SED1374 Host Bus Interface Epson Research and Development Vancouver Design Center This section is a summary of the host bus interface modes available on the SED1374 and offers some de
225. hat the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Philips MIPS PR31500 PR31700 Processor X26A G 012 01 Issue Date 98 11 09 EPSON Research and Development Page 3 Vancouver Design Center Table of Contents 1 IntrOdUCHON a oa ss a aie ea a ah a a asa i CR GE EN sak a Sto ghee Shea ae 7 1 1 General Description E a O A Gee ee Hy aN 2 Direct Connection to the Philips PR31500 PR31700 8 2 1 General Description diy pueri Ge a Bho BA A E a oS 2 2 Memory Mapping and Ninne I ataa Se ELM GSE AM Baek Dk wa a e 2 3 SED1374 Configuration and Pin Mapping a a 9 3 System Design Using the ITE IT8368E PC Card Buffer 10 3 1 Hardware Description e LO 3 2 IT8368E Configuration a a a 11 3 3 Memory Mapping and Aliasing a a a aaa LA 3 4 SED1374 Configuration oa a a a 13 S fiWale s ieu ea aaa a eh i a y aar a a ida E ET ANa et a a 14 Technical Support ee sos a wes o ee ee ee ee a ee ee 15 5 1 EPSON LCD Controllers SED1374 o a a 2 2 2 2 ee 15 5 2 Philips MIPS PR31500 PR31700 Processor
226. he Image Refreshed by SED1374 Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 80 Epson Research and Development Vancouver Design Center 12 1 1 How to Set Up Default SwivelView Mode The following describes the register settings needed to set up Default Swivel View Mode for a 240x320x4 bpp image e Select Default Swivel View Mode REG 1Bh bit 7 1 and bit 6 0 e The display refresh circuitry starts at pixel B therefore the Screen 1 Start Address register must be programmed with the address of pixel B i e REG 0Dh REG OCh AddressOfPixelB AddressOfPixelA ByteOffset 240pixels x 4bpp 8bpb E AddressOfPixelA AddressOfPixelA 77h Where bpp is bits per pixel and bpb is bits per byte e The Line Byte Count Register for Swivel View Mode must be set to the virtual image width in bytes i e 256 256 _ 198 80h REG ICh ud 2 Where bpb is bits per byte and bpp is bits per pixel e Panning is achieved by changing the Screen 1 Start Address register e Increment the register by 1 to pan horizontally by one byte e g two pixels in 4 bpp mode e Increment the register by twice the value in the Line Byte Count register to pan verti cally by two lines e g add 100h to pan by two lines in the example above Note Vertical panning by a single line is not supported in Default SwivelView Mode SED1374 Hardware Functional Specification X26A A 001 02 Issue Date
227. he SED 1374 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or www erd epson com Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 98 11 09 EPSON Research and Development Vancouver Design Center 5 Technical Support 5 1 EPSON LCD Controllers SED1374 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 5 2 Philips MIPS PR31500 PR31700 Processor Philips Semiconductors Handheld Computing Group 4811 E Arques Avenue M S 42 P O Box 3409 Sunnyvale CA 94088 3409 Tel 408 991 2313 http www philips com 5 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 98 11 09 Page 15 Taiwan R O C Epson Taiwan Technology 8 Trading Ltd
228. host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the SED1374 for Generic 2 mode and should be tied high connected to IO Vpp RD WR should also be tied high Interfacing to the NEC VR4102 Microprocessor Issue Date 99 01 05 Epson Research and Development Page 13 Vancouver Design Center 4 VR4102 to SED1374 Interface 4 1 Hardware Description The NEC Vr4102 Microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary By using the Generic 2 interface only one inverter is required to change the polarity of the system reset signal to active low A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle The following diagram shows a typical implementation of the VR4102 to SED1374 interface NEC VR4102 SED1374 WR gt WEO SHB WE1 RD gt RD LCDCS Pulbup gt CS TE LCDRDY WAIT RSTOUT gt gt RESET ADD 15 0 AB 15 0 DATA 15 0 DB 15 0 BUSCLK gt BUSCLK Vcc tT BS Vcc t RD WR Figure 4 1 Typical Implementation of VR4102 to SED1374 Interface Interfacing t
229. hree bits are an index into the first eight green values The last two bits form an index into the first four blue Look Up Table entries Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Red bit 2 Red bit 1 Red bit 0 Green bit 2 Green bit 1 Green bit 0 Blue bit 1 Blue bit 0 Figure 3 4 Pixel Storage for 8 Bpp 256 Colors in One Byte of Display Buffer Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 14 Epson Research and Development Vancouver Design Center 4 Look Up Table LUT This section is supplemental to the description of the Look Up Table LUT architecture found in the SED1374 Hardware Functional Specification Covered here is a review of the LUT registers recommendations for the color and monochrome LUT values and additional programming considerations for the LUT The SED1374 Look Up Table consists of sixteen 4 bit wide entries for each of red green and blue The Look Up Table is controlled by three registers REG 15h forms the index into the table REG 16h determines which bank is active during display REG 17h is the register where the Look Up Table data is read and written The currently configured color depth affects how many indices will be used for image display In color modes pixel values are used as indices to an RGB value stored in the Look Up Table In monochrome modes only the green component of the LUT is used 4 1 Look Up Table Registers
230. i Vpp 50 100 300 kQ SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Table 6 4 Output Specifications Page 25 Symbol Parameter Condition Min Typ Max Units Low Level Output Voltage Type 1 TS1 CO1 lo 3mA VoL Type 2 TS2 CO2 lo 6mA On y Type 3 TS3 CO3 lo 12mA High Level Output Voltage Type 1 TS1 CO1 lo 1 5 mA Vou Type 2 TS2 CO2 lo 3 mA IO Vpop 0 4 y Vop MAX loz Output Leakage Current Vou Vpp 1 1 uA VoL Vss Cout Output Pin Capacitance 10 pF Cpip Bidirectional Pin Capacitance 10 pF Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 26 Epson Research and Development Vancouver Design Center 7 A C Characteristics Conditions IO Vpp 3 3V 10 or IO Vpp 5V 10 Ta 40 C to 85 C Tise and Ty for all inputs must be lt 5 nsec 10 90 C 60pF Bus MPU Interface C 60pF LCD Panel Interface 7 1 Bus Interface Timing 7 1 1 SH 4 Interface Timing Teko t2 t3 re CKIO t4 t5 2 gt A 16 0 RD WR t6 t7 BS rl t8 CSn t9 t10 WEn RD _ pet 412 t13 RDY t14 t15 gt 4 gt D 15 0 write t16 t17 t gt gt D 15 0 read X VALID Figure 7 1 SH 4 Timing Note The S
231. ic 0 e L gt 1 2 3 Bank 3 o gt gt Green Bank Select 3 Blue Bank Select REG 16h bits 1 0 Pa Bank 0 0 e gt 2 3 Bank 1 0 a E X Bank 4 bit Blue display data output 3 Select Bank 2 Logic 0 _ gt 1 2 3 Bank 3 0 ar 3 Red Look Up Table 7 6 5 4 3 2 1 0 Banko A0 BO A1 B1 A2 B2 A3 B3 2 bit pixel data g ap See Section 10 3 Bank 1 9 e Bank 4 bit Red display data output 3 Select k Bank 2 Logic 0 e gt 1 2 3 Bank 3 1 a 3 Figure 11 6 4 Level Color Mode Look Up Table Architecture SED1374 X26A A 001 02 Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Page 77 Vancouver Design Center 16 Level Color Mode 16 Color Data Format 7 6 5 4 3 2 1 0 Red Look Up Table 16x4 AO BO C0 DO A1 B1 C1 Di 0 See Section 10 a 4 bit pixel data 3 4 bit Red display data output gt gt C D E F Green Look Up Table 16x4 gt 4 bit Green display data output e gt gt moO Blue Look Up Table 16x4 wWN 0 a 4 bit Blue display data output gt moO Figure 11 7 16 Level Color Mode Look Up Table Architecture Hardware Functional Specificat
232. ica Seiko Epson Corporation Epson Electronics America Inc Electronic Devices Marketing Division 150 River Oaks Parkway 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Europe Epson Hong Kong Ltd Epson Europe Electronics GmbH 20 F Harbour Centre Riesstrasse 15 25 Harbour Road 80992 Munich Germany Wanchai Hong Kong Tel 089 14005 0 Tel 2585 4600 Fax 089 14005 110 Fax 2827 4346 Copyright 1998 Epson Research and Development Inc All rights reserved FOR SYSTEM INTEGRATION SERVICES FOR WINDOWS CE CONTACT Epson Research amp Development Inc Suite 320 11120 Horseshoe Way Richmond B C Canada V7A 5H7 Tel 604 275 5151 Ene Fax 604 275 2167 Email wince erd epson com Microsoft http www erd epson com Windows CE Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 VDC Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Ep son EPSON products You may not modify the document Epson Research
233. ice ID pLUT pointer to an array of BYTE lut 16 3 pLUT must point to enough memory to hold Count x 3 bytes of data Count the number of LUT elements to read Return Value ERR_OK operation completed with no problems int seSetLutEntry int DevID int Index BYTE pEntry Description Parameters This routine writes one LUT entry Unlike seSetLut the LUT entry indicated by Tndex can be any value from 0 to 15 A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four least significant bits of each byte DevID registered device ID Index index to LUT entry 0 to 15 pLUT pointer to an array of three bytes Return Value ERR_OK operation completed with no problems int seGetLutEntry int DeviD int index BYTE pEntry Description Parameters This routine reads one LUT entry from any index A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four least significant bits of each byte DevID registered device ID Index index to LUT entry 0 to 15 pEntry pointer to an array of three bytes Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center 10 Sample Code 10 1 Introduction Page 61 Included in the sample code section are two examples of pr
234. ification SED1374 X26A A 001 02 Page 8 Epson Research and Development Vancouver Design Center Figure 11 3 16 Level Gray Shade Mode Look Up Table Architecture 73 Figure 11 4 Look Up Table Bypass Mode Architecture o o 74 Figure 11 5 2 Level Color Look Up Table Architecture o o e 75 Figure 11 6 4 Level Color Mode Look Up Table Architecture o o 76 Figure 11 7 16 Level Color Mode Look Up Table Architecture o o 77 Figure 11 8 256 Level Color Mode Look Up Table Architecture o ae 78 Figure 12 1 Relationship Between The Screen Image and the Image Refreshed by SED1374 79 Figure 12 2 Relationship Between The Screen Image and the Image Refreshed by SED1374 81 Figure 13 1 Panel On Off Sequence e 86 Figure 14 1 Mechanical Drawing QFP14 0 0 00 0000 e 88 SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 9 Vancouver Design Center 1 Introduction 1 1 Scope This is the Functional Specification for the SED1374 Embedded Memory LCD Controller Chip Included in this document are timing diagrams AC and DC characteristics register descriptions and power management descriptions This document is intended for two audiences Video Subsystem Designers and Software Developers Please check the Epson Electronics America website
235. ilable from your sales support contact or on the internet at http www erd epson com SED1374 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 01 1 02 Issue Date 99 01 05 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MCF5307 ColdFire Integrated Microprocessor User s Manual Motorola Publication no MCF5307UM AD available on the Internet at http www mot com SPS HPESD prod coldfire 5307UM html Epson Research and Development Inc SED1374 Hardware Functional Specification Document Number X26A A 002 xx Epson Research and Development Inc SDU I374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx Epson Research and Development Inc SED1374 Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola Website http www mot com e Epson Research and Development Website http www erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1374 Issue Date 99 01 05 X26A G 01 1 02 Page 18 7 Technical Support 7 1 EPSON LCD Controllers SED1374 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Cen
236. ill the rectangle or simply draw the border Set to 0 for no fill set to non 0 to fill the inside of the rectangle Return Value ERR_OK operation completed with no problems 9 2 7 LUT Manipulation These functions deal with altering the color values in the Look Up Table int seSetLut int DevID BYTE pLut int Count Description Parameters This routine writes one or more LUT entries The writes always start with Look Up Table index 0 and continue for Count entries A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four least significant bits of each byte DevID registered device ID pLut pointer to an array of BYTE lut 16 3 lut x 0 RED component lut x 1 GREEN component lut x 2 BLUE component Count the number of LUT entries to write Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 99 04 27 SED1374 X26A G 002 02 Page 60 SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center int seGetLut int DevID BYTE pLUT int Count Description Parameters This routine reads one or more LUT entries and puts the result in the byte array pointed to by pLUT A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four least significant bits of each byte DevID registered dev
237. ion X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 4 1 Figure 5 1 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Figure 7 18 Figure 7 19 Figure 7 20 Figure 7 21 Figure 7 22 Figure 7 23 Figure 7 24 Figure 7 25 Figure 8 1 Figure 10 1 Figure 11 1 Figure 11 2 Hardware Functional Issue Date 99 04 29 Page 7 List of Figures Typical System Diagram SH 4 Bus 2 2 2 o o ee 12 Typical System Diagram SH 3 Bus 2 2 ee 12 Typical System Diagram M68K 1 BUS o e e e 13 Typical System Diagram M68K 2 BUS o o e 13 Typical System Diagram Generic 1 Bus o o 14 Typical System Diagram Generic 2 Bus e g ISA Bus 14 System Block Diagram Showing Data Paths o 15 Pinout DidgraM eos ea a Be a E a BB ee 4 17 NA A A edo aoe Shs 26 SH 3 Bus Timing g ich a A ad A A ia A ds SLES 28 M68K 1 Bus Timing MC68000 2 2 ee 30 M68K 2 Timing MC68030 saasaa ee 31 Generic 1 LUMINOSA hg SMa O E ew ak Ga Me a ak a 32 Generic 2 Timing i se be Bo a EY Re Eb ba ee a 33 Clock Input Requirements
238. ion SED1374 Issue Date 99 04 29 X26A A 001 02 Page 78 Epson Research and Development Vancouver Design Center 256 Level Color Mode 256 Color Data Format Red Look Up Table 71 6 5 4 3 2 1 0 Bank 0 R2 R1 RO G2 G1 G0 B1 Bo 9 7 2 See Section 10 3 bit pixel data gt 3 4 5 S Bank Select Bank 1 Logic oe 0 1 2 3 4 5 6 7 Red Bank Select REG 16h bit 4 Green Look Up Table Bank 0 0 1 3 bit pixel data 3 gt 4 5 5 Bank Select gt p Bank 1 Logic 0 1 2 3 4 5 6 7 Green Bank Select REG 16h bit 2 Blue Look Up Table Bank 0 2 bit pixel data 9 gt 2 3 Bank 1 o a Bank 3 Select _ Bank 2 Logic 0 L gt 1 2 3 Bank 3 0 iar 3 Blue Bank Select REG 16h bits 1 0 Figure 11 8 256 Level Color Mode Look Up Table Architecture SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 79 Vancouver Design Center 12 SwivelView Many of todays applications use the LCD panel in a portrait orientation In this case it becomes necessary to rotate the displayed image This rotation can be done by software at
239. is STN specific and is disabled if TFT is selected MOD Count the mod count value specifies the number of FPLINEs between toggles of the MOD output signal When set to 0 default the MOD output signal toggles every FPFRAME This field is for passive panels only and is generally only required for older mono chrome panels FPLINE Start this field specifies the delay in an 8 pixel resolution from the end of a line of display data FPDAT to the leading edge of FPLINE This field is a TFT specific setting and is disabled if an STN panel is chosen FPFRAME Start this field specifies the number of lines between the last line of display data FPDAT and the leading edge of FPFRAME This field is a TFT specific setting and is disabled if an STN panel is chosen FPLINE FPFRAME Polarity these settings control the sync pulse direction of the FPLINE and FPFRAME pulses in TFT modes Select the appropriate pulse direction for the panel being connected Selecting Lo results in an active low sync pulse while Hi results in an active high pulse These settings are TFT specific and are disabled when STN panel is selected When STN panel type is selected the pulse directions are preset to ve ve 1374CFG EXE Configuration Program SED1374 Issue Date 98 10 27 X26A B 001 01 Page 10 Epson Research and Development Vancouver Design Center Miscellaneous Options Misc Options TT HW Video Invert Enable I HW Power Save
240. it Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 4 Ts t10 Shift Pulse pulse width low 2 Ts t11 Shift Pulse pulse width high 2 Ts t12 FPDAT 7 4 setup to Shift Pulse falling edge 2 Ts t13 FPDAT 7 4 hold to Shift Pulse falling edge 2 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 Umin t8min 9TS 3 tBmin REG 04h bits 6 0 1 x 8 REG O08h bits 4 0 4 x 8 Ts 4 t6nin REG 08h bits 4 0 x 8 2 Ts 5 t min REG O8h bits 4 0 x 8 11 Ts SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 39 Vancouver Design Center 7 3 4 Single Monochrome 8 Bit Panel Timing VDP VNDP FPFRAME A FPLINE
241. its 3 2 Figure 11 2 4 Level Gray Shade Mode Look Up Table Architecture 16 Level Gray Shade Mode 16 Gray Data Format 7166 5 4 3 2 1 0 AO BO CO DO A1 B1 C1 DI Green Look Up Table 16x4 See Section 10 wWN 0 4 bit pixel data 4 bit display data output muUo Figure 11 3 16 Level Gray Shade Mode Look Up Table Architecture Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 74 Epson Research and Development Vancouver Design Center Look Up Table Bypass Mode Look Up Tables 1 bit pixel data Ap 1 bit display data output An 2 bit pixel data A Bn 4 bit display data output An Bn An Bn 4 bit pixel data An Bn Cn Dn 4 bit display data output An Bn Cn Dn Figure 11 4 Look Up Table Bypass Mode Architecture Note In 1 bit per pixel display mode Look Up Table Bypass mode will turn off the FRM circuitry and place the SED1374 in Black and White mode In 2 bit per pixel mode the Display Data Output values are 0 5 A and F in hex SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center 11 2 Color Display Modes 2 Level Color Mode Page 75 Red Look Up Table 1 bit pixel data 0 2 e 3
242. ively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the SED1374 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the SED1374 These signals must be generated by external hardware based on the control outputs from the host CPU e WAIT is a signal output from the SED1374 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1374 may occur asynchronously to the display update it is possible that contention may occur in accessing the SED1374 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CP
243. k red LUT Addresses 2 and 3 Green would be taken from the 3rd green lookup bank green LUT addresses 4 and 5 Blue pixels would be taken from the 1st blue lookup bank blue LUT addresses 0 and 1 Programming Notes and Examples Issue Date 99 04 27 SED1374 X26A G 002 02 Page 16 SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center At 2 bpp sixteen Look Up Table addresses are used The Look Up Table is a now arranged into four banks of four colors each As with 1 bpp the bank select bits determine the initial offset into the Look Up Table Incrementing a bank select by one bumps the Look Up Table offset by four Table 4 1 2 Bpp Banking Scheme Bank Red LUT Green LUT Blue LUT Addresses Addresses Addresses 0 0 0 1 1 1 0 2 2 2 3 3 3 4 4 4 5 5 5 4 6 6 6 7 7 7 8 8 8 9 9 9 2 A A A B B B C C C D D D 3 E E E F F F Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 17 Vancouver Design Center At 4 bpp the pixel data is a direct index to the color to be displayed At this color depth the Look Up Table Bank Select bits have no effect on the display colors For instance If the data was 7Bh then the first pixel color would be from the RGB values of the 8th Look Up Table address The second pixel would be the colored by the RGB value at the 12th OBh Look Up Table addre
244. l A C Timing Format 2 Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t44 2 Ts t9 Shift Pulse period 2 Ts t10 Shift Pulse pulse width low 1 Ts t11 Shift Pulse pulse width high 1 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 1 Ts t13 FPDATT 7 0 hold to Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 tlmin t3min 9Ts 3 83min REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 1 Ts 5 t7min REG O08h bits 4 0 x 8 10 Ts SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 47 Vancouver Design Center 7 3 8 Dual Monochrome 8 Bit Panel Timing r VDP VNDP FPFRAME He EPLINE _ I LJ l l
245. leasing reset the bus interface signals assume their selected configuration The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping ee SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vss connect to IO Vpp RD WR RD WR RD WR R W R W RD1 connect to lO Vpp RD RD RD connect to lO Vpp SIZ1 RDO RD WEO WEO0 WE0 connect to lO Vpp SIZO WE0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1374 Issue Date 99 01 05 X26A G 011 02 Page 12 Epson Research and Development Vancouver Design Center Two other configuration options CNF 4 3 are also made at time of hardware reset e endian mode setting big endian or little endian e polarity of the LCDPWR signal The capability to select the endian mode independent of the host bus interface offers more flexibility in configuring the SED1374 with other CPUs For details on configuration refer to the SED1374 Hardware Functional
246. llowing settings are recommended when using the SDU1374B0C with the ISA bus Table 2 1 Configuration DIP Switch Settings Switch Signal Closed 0 or low Open 1 or high SW1 1 CNFO SW1 2 CNF1 See Host Bus Selection table below See Host Bus Selection table below SW1 3 CNF2 SW1 4 CNF3 Big Endian SW1 5 CNF4 Active high LCDPWR signal SW1 6 GPIOO Hardware Suspend Enable L l recommended settings configured for ISA bus support Table 2 2 Host Bus Selection Host Bus Interface SH 4 bus interface SH 3 bus interface reserved MC68K bus interface 1 16 bit reserved MC68K bus interface 2 16 bit reserved wn oo wn N w Q S reserved Generic 1 16 bit L l recommended settings configured for ISA bus support O CO CO CO a a e Oo o O o 0O 0 Oo oO o O Oo x x x x gt x gt o SED1374 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 01 Issue Date 98 10 26 Epson Research and Development Vancouver Design Center SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 Page 9 Table 2 3 Jumper Settings Description 1 2 2 3 JP1 IOVDD Selection 3 3V IOVDD JP2 BS Signal Selection No Connection JP3 RD WR Signal Selection No Connection JP4 LCD Panel V
247. lock input for both pixel and memory clocks e The SED1374 clock source can be internally divided down for a higher frequency clock input e Dynamic switching of memory clocks in portrait mode Display Modes e Hardware Portrait Mode direct hardware rotation of display image for portrait mode display e 1 2 4 bit per pixel bpp 2 4 16 level grayscale display e 1 2 4 8 bit per pixel 2 4 16 256 level color display e Up to 16 shades of gray by FRM on monochrome passive LCD panels e 256 simultaneous of 4096 colors on color passive and active matrix LCD panels e Split screen display for all panel modes allows two different images to be simultaneously displayed e Virtual display support displays images larger than the panel size through the use of panning Power Down Modes e Hardware and software Suspend modes e LCD power down sequencing General Purpose IO Pins e Five General Purpose Input Output pins are available Operating Voltage e 2 7 volts to 5 5 volts Package 80 pin QFP14 surface mount package X26A C 001 05 05 1 SED1374 E SYSTEM BLOCK DIAGRAM Data and Digital Out EPSON CPU lt gt Control Signals SED1374 Flat Panel Actual Size CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS e SED1374 Technical Manual e SDU1374 Evaluation Boards e Windows CE Display Driver e CPU Independent Software Utilities Japan North Amer
248. lopment Vancouver Design Center Teko t2 t3 pi CkKIO t4 t5 A 16 0 M R RD WR A t6 t7 BS i t8 CSn t9 y t10 WEn RD t11 t12 gt gt WAITH Hi Z Hi Z t13 gt t14 D 15 0 Hi Z Hi Z write 415 t16 D 15 0 Hi Z Hi Z read VALID Figure 7 2 SH 3 Bus Timing Note The SH 3 Wait State Control Register for the area in which the SED1374 resides must be set to a non zero value SED1374 X26A A 001 02 Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Table 7 2 SH 3 Bus Timing Symbol Parameter Min Max Units fckio Bus Clock frequency 0 50 MHz Tokio Bus Clock period Yckio t2 Clock pulse width high 17 ns t3 Clock pulse width low 16 ns t4 A 15 0 RD WR setup to CKIO 0 ns t5 A 15 0 RD WR hold from CS 0 ns t6 BS setup 5 ns t7 BS hold 5 ns 18 CSn setup 0 ns t9 Falling edge RD to DB 15 0 driven 25 ns t10 Rising edge CSn to WAIT high impedance 10 ns t11 Falling edge CSn to WAIT driven 15 ns t12 CKIO to WAIT delay 20 ns t13 DB 15 0 setup to 2 CKIO after BS write cycle 0 ns t14 DB 15 0 hold from rising edge of WEn write cycle 0 ns t15 DB 15 0 valid to RDY falling edge setup time read cycle 0 ns t16 Rising edge RD to DB 15 0 high impedance read cycle
249. m Design Using the ITE IT8368E PC Card Buffer 10 3 1 Hardware Description e LO 3 2 IT8368E Configuration a a a 11 3 3 Memory Mapping and Aliasing eee LA 3 4 SED1374 Configuration e 3 SOMWANC s iva A Ca gee ae a a Sides Seat AS O Bas 14 Technical Support lt oes so a ie a ee ee ee a ee Be ee a a A 15 5 1 EPSON LCD Controllers SED1374 o a a 2 2 2 ee 1S 5 2 Toshiba MIPS TX3912 Processor 2 2 2 2 ee eee ee US 9 30 ITETESSOSE o 2 23 aegis ee ee eh eR Boe wl BR Pe Bee ed Interfacing to the Toshiba MIPS TX3912 Processor SED1374 Issue Date 98 11 09 X26A G 004 01 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 01 Issue Date 98 11 09 EPSON Research and Development Table 2 1 Table 2 2 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Figure 2 1 Figure 3 1 Issue Date 98 11 09 Page 5 Vancouver Design Center List of Tables SED1374 Configuration for Direct Connection e 9 SED1374 Generic 2 Interface Pin Mapping 0 00000 2 000 4 9 TX3912 to Unbuffered PC Card Slots System Address Mapping 12 TX3912 to PC Card Slots Address Remapping Using the IT8368E 12 SED1374 Configuration Using the IT8368E o 13 SED1374 Generic 1 Interface Pin Mappidg e 13 List of Figure
250. made during reset by sampling the state of the configu ration pins CNF 2 0 and the BS line Table 5 1 in the SED1374 or SED1375 Hardware Functional Specification details the values needed for the configuration pins and BS to select the desired mode SDU1374 75 TMPR3912 22U CPU Module Issue Date 98 12 23 EPSON Research and Development Page 9 Vancouver Design Center 2 2 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the SED1374 75 The Generic 2 interface mode was chosen for this interface due to its compatibility with the PC Card interface The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the SED1374 75 BUSCLK is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper memory address space WE1F is the high byte enable for both read and w
251. mber of words in one virtual scan line To scroll up decrease the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line Step 1 Determine the number of words in one virtual scanline bytes_per_line pixels_per_line pixels_per_byte 320 2 160 words_per_line bytes_per_line 2 160 2 80 Step 2 Scroll up or down To scroll up StartWord GetStartAddress StartWord words_per_line if StartWord lt 0 StartWord 0 SetStartAddress StartWord To scroll down StartWord GetStartAddress StartWord words_per_line SetStartAddress StartWord long GetStartAddress void return REG OD 256 REG OC void SetStartAddress long StartWord REG OC StartWord OXFF REG OD StartWord 256 Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 30 5 3 Split Screen SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center Occasionally the need arises to display two different but related images For example a game where the main play area requires rapid updates and game status displayed at the bottom of the screen The status area updates far less often than the main play area The Split Screen feature of the SED1374 allows a programmer to setup a display for such an application The figure below illustrates setting a 320x240 panel to have Image 1 displaying from scan line 0 to s
252. meter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t6a Shift Pulse falling edge to Line Pulse rising edge note 4 t6b Shift Pulse 2 falling edge to Line Pulse rising edge note 5 t7a Shift Pulse 2 falling edge to Line Pulse falling edge note 6 t7b Shift Pulse falling edge to Line Pulse falling edge note 7 t8 Line Pulse falling edge to Shift Pulse rising Shift Pulse 2 falling edge t14 2 Ts t9 Shift Pulse 2 Shift Pulse period 4 Ts t10 Shift Pulse 2 Shift Pulse pulse width low 2 Ts t11 Shift Pulse 2 Shift Pulse pulse width high 2 Ts t12 FPDAT 7 0 setup to Shift Pulse 2 Shift Pulse falling edge 1 Ts t13 FPDAT 7 0 hold to Shift Pulse 2 Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 Umin t8min 9TS 3 t3min REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6amin REG O8h bits 4 0 x 8 t13 t10 Ts 5 t6bmin REG 08h bits 4 0 x 8 t13 Ts 6 t7amin REG O8h bits 4 0 x 8 11 Ts 7 t70min REG O8h bits 4 0 x 8 11 t10 Ts SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center 7 3 7 Single Color 8 Bit Panel Timing Format 2 Page 45
253. mode However BS is used to configure the SED1374 for Generic 1 mode and should be tied low connected to GND Interfacing to the PC Card Bus SED1374 Issue Date 98 12 10 X26A G 009 02 Page 12 Epson Research and Development Vancouver Design Center 4 PC Card to SED1374 Interface 4 1 Hardware Connections The SED1374 is interfaced to the PC Card interface with a minimal amount of glue logic A PAL is used to decode the write and read signals of the PC Card bus to generate RD RD WR WE0 WE1 and CS for the SED1374 The PAL also inverts the reset signal of the PC card since it is active high and the SED1374 uses an active low reset For PAL equations for this implementation refer to Section 4 3 PAL Equations on page 14 In this implementation the address inputs AB 15 0 and data bus DB 15 0 connect directly to the CPU address A 15 0 and data bus D 15 0 The PC Card interface does not provide a bus clock so one must be supplied for the SED1374 Since the bus clock frequency is not critical nor does it have to be synchronous to the bus signals it may be the same as CLKI BS bus start is not used by Generic 1 mode but is used to configure the SED1374 for Generic 1 and should be tied low connected to GND The following diagram shows a typical implementation of the PC Card to SED1374 interface PC Card socket PAL16L8 15 SED1374
254. mputer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection SED1374 Supported Evaluation Platforms 1374PWR has been designed to work with the following SED1374 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the SED1374 Programming Notes and Examples manual document number X26A G 002 xx Installation PC platform copy the file 1374PWR EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 1374PWR to the system 1374PWR Power Save Utility SED1374 Issue Date 98 10 27 X26A B 007 01 Page 4 Usage Epson Research and Development Vancouver Design Center PC platform at
255. n 1374PLAY Example 1 Type 1374PLAY to start the program 2 Type for help 3 Type i to initialize the registers 4 Type xa to display the contents of the registers 5 Type x 5 to read register 5 6 Type x 3 10 to write 10 hex to register 3 7 Type f0 400 aa to fill the first 400 hex bytes of display memory with AA hex 8 Type f 0 a000 aa to fill 40k bytes of display memory 9 Type r 0 ff to read the first 100 hex bytes of display memory 10 Type q to exit the program 1374PLAY Diagnostic Utility SED1374 Issue Date 99 11 29 X26A B 005 02 Page 6 Scripting Comments SED1374 X26A B 005 02 Epson Research and Development Vancouver Design Center 1374PLAY can be driven by a script file This is useful when e there is no standard display output to monitor command entry and results e various registers must be quickly changed faster than can achieved by typing e The same series of keystrokes is being entered time and again A script file is an ASCII text file with one 1374PLAY command per line All scripts must end with a q quit command in order to return control to the operating system The semi colon is used as a comment delimitor Everything on a line after the semi colon will be ignored On a PC platform a typical script command line is 1374PLAY lt dumpregs scr gt results This causes the script file dumpregs scr to be interpreted and the results to be s
256. n completed with no problems ERR_HAL_BAD_ARG if the value for Addr or if Addr plus Count is greater than 40 kb int seWriteDisplayDwords int DevID DWORD Offset DWORD Value DWORD Count Description Parameters Return Value Programming Notes and Examples Issue Date 99 04 27 Writes one or more DWORDS to the display buffer at the offset specified by Addr If a count greater than one is specified all DWORDSs will have the same value DevID registered device ID Offset offset from start of the display buffer Value DWORD value to write Count number of dwords to write ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr or if Addr plus Count is greater than 40 kb SED1374 X26A G 002 02 Page 58 9 2 5 Power Save 9 2 6 Drawing SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center This section covers the HAL functions dealing with the Power Save features of the SED1374 int seSetPowerSaveMode int DeviD int PwrSaveMode Description This function sets on the SED1374 s software selectable power save modes Parameters DevID aregistered device ID PwrSaveMode integer value specifying the desired power save mode Acceptable values for PwrSaveMode are 0 software power save mode in this mode registers and memory are read writable LCD output is forced low 3 normal operation all outputs function normally Return Value ERR_OK op
257. nal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the base address the block size of the chip select and controls the following timing parameters The ACS bit field allows the chip select assertion to be delayed with respect to the address bus valid by 0 4 or Ya clock cycle The CSNT bit causes chip select and WE to be negated 1 2 clock cycle earlier than normal The TRLX relaxed timing bit will insert an additional one clock delay between asser tion of the address bus and chip select This accommodates memory and peripherals with long setup times The EHTR Extended hold time bit will insert an additional 1 clock delay on the first access to a chip select Up to 15 wait states may be inserted or the peripheral can terminate the bus cycle itself by asserting TA Transfer Acknowledge Any chip select may be programmed to assert BI Burst Inhibit automatically when its memory space is addressed by the processor core Interfacing to the Motorola MPC821 Microprocessor SED1374 Issue Date 99 01 05 X26A G 010 02 Page 12 Epson Research and Development Vancouver Design Center 2 3 2 User Programmable Machine UPM The UPM is typically used to control memory types such as Dynamic RAMs which have complex control or address multiplexing requirements The UPM is a general
258. nd Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2 2 020000000 22 eee 9 Table 4 1 Configuration Settings 2 2 0 a 12 Table 4 2 Host Bus Selectii oed a ale aure aeta ee a a 12 List of Figures Figure 4 1 Typical Implementation of an 8 bit Processor to the SED1374 Generic 2 Interface 11 Interfacing to an 8 bit Processor SED1374 Issue Date 99 05 04 X26A G 013 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to an 8 bit Processor X26A G 013 01 Issue Date 99 05 04 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware environment required to provide an interface between the SED1374 Embedded Memory LCD Controller and a generic 8 bit micropro cessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America Website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to an 8 bit Processor SED1374 Issue Date 99 05 04 X26A G 013 01 Page 8 Epson Research and Development Vancouver D
259. ndicate whether to enable of disable high performance ERR_OK operation completed with no problems 9 2 3 Advanced HAL Functions Advanced HAL functions include the functions to support split virtual and rotated displays While the concept for using these features is advanced the HAL makes actually using them easy int seSetHWRotate int DevID int Rotate Description Parameters Return Value SED1374 X26A G 002 02 This function sets the rotation scheme according to the value of Rotate When Swivel View mode is selected as the display rotation the scheme selected is the non X2 scheme DevID registered device ID Rotate the direction to rotate the display Valid arguments for Rotate are LANDSCAPE and PORTRAIT ERR_OK operation completed with no problems ERR_FAILED the operation failed to complete The most likely reason for failing to set a SwivelView mode is an inability to set the desired frame rate when setting the mode Other factors which can cause a failure include having configured for a 0 Hz frame rate or specifying something other than LANDSCAPE or PORTRAIT for the rotation scheme Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 53 int seSplitInit int DevID WORD Scrn1 Addr WORD Scrn2Addr Description Parameters Return Value Note This function prepares the system for split screen operation In order for split
260. ne Byte Count The Line Byte Count also must be based on the power of two width LineByteCount Width x BitsPerPixel 8 256 x 4 8 128 80h Set the Line Byte Count REG 1C to 80h 3 Enable SwivelView mode This example uses the default Swivel View mode scheme If we do not change the SwivelView Mode Pixel Clock Select bits then we will not have to recalculate the non display timings to correct the frame rate Write 80h to the Swivel View Mode Register REG 1Bh The display is now configured for SwivelView mode use Offset zero into display memory will corresponds to the upper left corner of the display The only thing to keep in mind is that the count from the first pixel of one line to the first pixel of the next line refered to as the stride is 128 bytes Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 43 Vancouver Design Center Example 7 Enable alternate SwivelView mode for a 320x240 panel at 4 bpp Note As we have to perform a frame rate calculation for this mode we need to know the fol lowing panel characteristics 320x240 8 bit color to be run at 80 Hz with a 16 MHz in put clock As in the previous example before switching to Swivel View mode display memory should be cleared Images in display memory are not rotated automatically by hardware and the garbled image would be visible for a short period of time if video memory is not cleared 1 Calculate and set the Scr
261. ng Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 51 int seGetScreenSize int DevID int Width int Height Description Retrieves the width and height in pixels of the display surface The width and height are derived by reading the horizontal and vertical size registers and calculating the dimensions Virtual dimensions are not taken into account for this calculation When the display is in Swivel View mode the dimensions will be swapped i e a 640x480 display in Swivel View mode will return a width and height of 480 and height of 640 Parameters DevID registered device ID Width pointer to an integer to receive the display width Height pointer to an integer to receive the display height Return value ERR_OK the operation completed successfully int seDelay int MilliSeconds Description Parameters Return Value This function will delay for the length of time specified in MilliSeconds before returning to the caller This function was originally intended for non PC platforms Information about how to access the timers was not always available however we do know frame rate and can use that for timing calculations The SED 1374 registers must be initialized for this function to work correctly On the PC platform this is simply a call to the C timing functions and is therefore independent of the register settings DevID registered device ID MilliS
262. ng and scrolling allow viewing the entire image a portion at a time Panning describes the horizontal side to side motion of the viewport When panning to the right the image in the viewport appears to slide to the left When panning to the left the image to appears to slide to the right Scrolling describes the vertical up and down motion of the viewport Scrolling down causes the image to appear to slide up and scrolling up causes the image to appear to slide down Both panning and scrolling are performed by modifying the start address register Start address refers to the word offset in the display buffer where the image will start being displayed from The start address registers in the SED1374 are an offset to the first word to be displayed in the top left corner of every frame Keep in mind that the start address is a word offset Changing the start address by one means a change of one words worth of pixels The number of pixels in word varies according to the color depth At 1 bit per pixel a word contains sixteen pixels At 2 bit per pixel there are eight pixels at 4 bit per pixel there are four pixels and at 8 bit per pixel there are two pixels The number of pixels in each word represent the finest panning step the SED1374 is capable of i e at 4 bit per pixel the display will move sideways by four pixels for each change to the start address registers When SwivelView mode see SwivelView on page 36 is enabled the start address
263. nology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1374 X26A G 004 01 Page 16 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 01 Issue Date 98 11 09 EPSON SED1374 Embedded Memory Color LCD Controller SED1374 Power Consumption Document Number X26A G 006 01 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your ownuse in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Power Consumption X26A G 006 01 Issue Date 98 10 27 Epson Research and Development Page 3 Vancouver Design C
264. nter THIS PAGE LEFT BLANK SED1374 Interfacing to the NEC VR4102 Microprocessor X26A G 008 04 Issue Date 99 01 05 Epson Research and Development Page 3 Vancouver Design Center Table of Contents Al introduction i s 100 Ke Rie ce fee es Game IO arte ae Ree A AA A a 7 2 Interfacing to the NEC VR4102 12 2 ee 8 2 1 The NEC VR4102SystemBus e 8 A A A ANO 8 2 1 2 LCD Memory Access Cycles o o ee 9 3 SED1374 Host Bus Interface lt lt lt lt o 10 3 1 Bus Interface Modes no s gt s y boak 2 ee ee ee LO 3 2 Generic 2 Interface Mode a aous ana he i opaa e 11 4 VR4102 to SED1374 Interface 13 4 1 Hardware Description 0 000022 13 4 2 SED1374 Hardware Configuration 14 4 3 NEC VR4102 Configuration 2 a ee WS 5 DOUWOIE ging oe tes eee ee ee ee ee ae AS ELA 16 References ias e a aca ee a me le Ee a del an ae 17 6 DochMents 2 vr Ao aw a A ee A a i es AO de OT 6 2 Document Sources 17 Technical Support is hes cos Rs A a a RS oe aS 18 7 1 Epson LCD Controllers SED1374 2 a a a aa ee 18 7 2 NEC Electronics Inc s e d P et pa ee 18 Interfacing to the NEC VR4102 Microprocessor SED1374 Issue Date 99 01 05 X26A G 008 04 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1
265. nter Table of Contents 1 introduction ia a ee eee eee ee ee Pa ey es ah Se es Ba te 1 1 General Description 2 SED1374 75 Bus Interface 0 000 0c ee eee ee 2 1 Bus Interface Modes 2 2 Generic 2 Interface Mode 3 TMPR3912 22U and SED1374 75 Interface 3 1 Hardware Connections 3 2 Memory Mapping and Aliasing 6 3 3 SED1374 75 Configuration and Pin Mapping 4 CPU Module Description lt lt eee 4 1 Clock Signals 4 1010 BUSCLE att a Sa ee lo oes Dee AS AAD CER sip a eae et pect eS RP OL at ee ats E 4 2 LCD Connectors 4 2 1 50 pin LCD Module Connector J3 00 0 4 2 2 Standard Epson LCD Connector J4 2 000 4 3 LCD Controller 43 1 SED1374 Vs SEDISTS uo rc He Se Ee a 4 32 ECDPWR Polarity cios 2 Piece E eee a 43 3 SED1374 75 Chip Select o o A SDU1374 75 TMPR3912 22U CPU Module Issue Date 98 12 23 Page 3 X00A G 004 01 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SDU1374 75 TMPR3912 22U CPU Module X00A G 004 01 Issue Date 98 12 23 EPSON Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 SED1374 75 Configuration for Generic 2 Bus Interface o 11 Table 3 2 SED1374 75 Generic 2 Interface Pin Mapping e 11 List of Figures Figure 3 1 SED1374 to TMPR3912 22U In
266. o that LCDON will be the right polarity to turn on the LCD power supply Jumper JP10 must be set to position 1 2 if LCDPWR is active low and to position 2 3 if LCDPWR is active high 4 3 3 SED1374 75 Chip Select Minimal glue logic is used on the CPU module to provide the chip select signal CS for the LCDC A simple AND gate activates the SED1374 75 whenever the PC Card slot 1 is accessed whether it be memory space or attribute space SDU1374 75 TMPR3912 22U CPU Module Issue Date 98 12 23 X00A G 004 01 Page 14 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SDU1374 75 TMPR3912 22U CPU Module X00A G 004 01 Issue Date 98 12 23 EPSON SED1374 Embedded Memory Color LCD Controller Interfacing to an 8 bit Processor Document Number X26A G 013 01 Copyright O 1999 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page
267. o the NEC VR4102 Microprocessor SED1374 Issue Date 99 01 05 X26A G 008 04 Page 14 Epson Research and Development Vancouver Design Center 4 2 SED1374 Hardware Configuration The SED 1374 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx for details The tables below show those configuration settings important to the Generic 2 host bus interface Table 4 1 Summary of Power On Reset Options Signal value on this pin at the rising edge of RESET is used to configure 0 1 0 1 CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Big Endian CNF4 Active low LCDPWR signal Active high LCDPWR signal ES configuration for NEC VR4102 support Table 4 2 Host Bus Selection CNF2 CNF1 CNFO w Q Host Bus Interface 0 o 0 SH 4 interface SH 3 interface reserved MC68K 1 16 bit reserved MC68K 2 16 bit reserved reserved 0 0 0 1 1 1 1 1 aj ajaj G O ajaj O lt O O oO m O 1 oj O X X XxX x x Xx Generic 1 16 bit Eee configuration for NEC VR4102 support SED1374 X26A G 008 04 Interfacing to the NEC VR4102 Microprocessor Issue Date 99 01 05 Epson Research and De
268. o the color depth This call is similar to a mode set call on a standard VGA DevID registered device ID BitsPerPixel desired color depth in bits per pixel Valid arguments are 1 2 4 and 8 ERR_OK operation completed with no problems ERR_FAILED possible causes for this error include 1 the desired frame rate may not be attainable with the specified input clock 2 the combination of width height and color depth may require more memory than is available on the SED1374 int seGetBitsPerPixel int DeviD int pBitsPerPixel Description Parameters Return Value This function reads the SED1374 registers to determine the current color depth and returns the result in pBitsPerPixel DevID registered device ID pBitsPerPixel pointer to an integer to receive current color depth return values will be 1 2 4 or 8 ERR_OK operation completed with no problems int seGetBytesPerScanline int DeviD int pBytes Description Parameters Return Value Returns the number of bytes use by each scan line in the integer pointed to by pBytes The number of bytes per scanline will include the number of non displayed bytes if applicable Prior to calling seGetBytesPerScanline the SED 1374 control registers must have been correctly initialized DevID registered device ID pBytes pointer to an integer to receive the number of bytes per scan line ERR_OK operation completed with no problems Programmi
269. ograming the SED1374 The first sample uses the HAL to draw a red square wait for user input then rotates to SwivelView mode and draws a blue square The second sample code performs the same procedures but directly accesses the registers of the SED1374 These code samples are for example purposes only 10 1 1 Sample code using the SED1374 HAL API xk SAMPLE1 C Sample code demonstating a program using the SED1374 HAL Created 1998 Vancouver Design Centre Copyright c 1998 Epson Research and Development Inc All Rights Reserved The HAL API code is configured for the following 320x240 Single Color 8 bit STN format 2 4 bpp 70 Hz Frame Rate 25 MHz CLKi High Performance enabled k k inclu inclu inclu inclu inclu inclu de de de de de de lt conio h gt lt stdio h gt lt stdlib h gt lt string h gt haL A Structures constants and prototypes appcfg h HAL configuration information ES void m ain void int Chipld int Device JR Initialize the HAL The call to seRegisterDevice actually prepares the HAL library for use The SED1374 is not accessed if ERR_OK seRegisterDevice amp HalInfo amp Device Programming Notes and Examples Issue Date 99 04 27 El SED1374 X26A G 002 02 Page 62 SED1374 Epson Research and Developmen
270. ok Up Table Data Bits 3 0 This register is used to read write the RGB Look Up Tables This register is an aperture into the three 16 position Look Up Tables The Look Up Table Address Register REG 16h selects which Look Up Table position is accessible See REG 16h Look Up Table Bank Select Register on page 66 REG 18h GPIO Configuration Control Register Address FFF8h Read Write aid aa n a GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIOO Pin IO Configuration Configuration Configuration Configuration Configuration bits 4 0 GPIO 4 0 Pin IO Configuration These bits determine the direction of the GPIO 4 0 pins When GPIOn Pin IO Configuration bit 0 the corresponding GPIOn pin is configured as an input The input can be read at the GPIOn Status Control Register bit See REG 19h below When GPIOn Pin IO Configuration bit 1 the corresponding GPIOn pin is configured as an output The output can be controlled by writing the GPIOn Status Control Register bit Note These bits have no effect when the GPIOn pin is configured for a specific function i e as FPDAT 11 8 for TFT MD TFD operation All unused GPIO pins must be tied to 10 Vpp REG 19h GPIO Status Control Register Address FFF9h Read Write Wa nja A GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIOO Pin IO Status Status Status Status Status bits 4 0 GPIO 4 0 S
271. oltage Selection 3 3V LCD Panel L recommended settings configured for ISA bus support SED1374 X26A G 005 01 Page 10 Epson Research and Development Vancouver Design Center 3 LCD Interface Pin Mapping Table 3 1 LCD Signal Connector J5 Pinout Connector Single Passive Panel Dual Passive Panel Color TET D TFD Color Mono Color Mono F 8 bit Pin Name Pin abit s bit Alternate abit sbit sbit sbit obit 12 bit Format BFPDATO 1 DO DO DO LDO LDO R2 R3 BFPDAT1 3 D1 D1 D1 LD1 LD1 R1 R2 BFPDAT2 5 D2 D2 D2 LD2 LD2 RO R1 BFPDAT3 7 D3 D3 D3 LD3 LD3 G2 G3 BFPDAT4 9 DO D4 D4 DO D4 UDO UDO G1 G2 BFPDAT5 11 D1 D5 D5 D1 D5 UD1 UD1 GO G1 BFPDAT6 13 D2 D6 D6 D2 D6 UD2 UD2 B2 B3 BFPDAT7 15 D3 D7 D7 D3 D7 UD3 UD3 B1 B2 BFPDAT8 17 BO B1 BFPDAT9 19 RO BFPDAT10 21 GO BFPDAT11 23 BO BFPSHIFT 33 FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT BFPSHIFT2 35 FPSHIFT2 BFPLINE 37 FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE BFPFRAME 39 FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME 2 26 GND Even GND GND GND GND GND GND GND GND GND Pins N C 28 VLCD 30 LCD panel negative bias voltage 18V to 23V LCDVCC 32 3 3V or 5V selectable with JP4 12V 34 12V 12V 12V 12V 12V 12V 12V 12V 12V VDDH 36 LCD panel positive bias voltage 24V
272. omprised of 4 pixels therefore each word contains 8 pixels pixels_per_word 16 bpp 16 2 8 Step 2 Calculate the Memory Address Offset register value We require a total of 640 pixels The horizontal display register will account for 320 pixels this leaves 320 pixels for the Memory Address Offset register to account for offset pixels pixels_per_word 320 8 40 28h The Memory Address Offset register REG 12h will have to be set to 28h to satisfy the above condition Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 27 Vancouver Design Center Example 2 From the above what is the maximum number of lines our image can contain Step 1 Calculate the number of bytes on each line bytes_per_line pixels_per_line pixels_per_byte 640 4 160 Each line of the display requires 160 bytes Step 2 Calculate the number of lines the SED1374 is capable of total_lines memory bytes_per_line 40960 160 256 The the maximum number of lines which can be accommodated by our image can contain is 256 This example will not fit in available display memory We must reduce either the color depth or the virtual image size 5 2 Panning and Scrolling Panning and scrolling describe the actions of appearing to move the image in a virtual display so that all the image can be viewed After correctly setting up a virtual display see above and loading an image into display memory panni
273. on 4 bit wide Look Up Tables one each for red green and blue Refer to Look Up Table Architecture for details This register selects which Look Up Table position is read write accessible through the Look Up Table Data Register REG 17h RGB Index Bits 1 0 These bits select between the Red Green and Blue Look Up Tables and Auto Increment mode The Green Look Up Table is used in monochrome mode with these bits set to 10b See Note below Look Up Table Address Bits 3 0 These 4 bits select one of the 16 positions in the selected Look Up Table These bits are automatically changed as the Look Up Table Data Register is accessed See Note below Note Accesses to the Look Up Table Data Register automatically increment a pointer into the RGB Look Up Tables The pointer sequence varies as shown in the table below Table 8 7 Look Up Table Access REG 01h REG 15h Look Up Table bit 5 bit 5 bit 4 Selected Pointer Sequence Green Gray Look Up Table 1 0 0 Auto Increment R n G n Bin R n 1 G n 1 1 0 1 Red Look Up Table Rin R n 1 R n 2 Green Gray Look Up Table 1 1 1 Blue Look Up Table B n B n 1 B n 2 0 1 0 Gin G n 1 G n 2 1 1 0 Gin G n 1 G n 2 In Auto Increment mode writing the Look Up Table Address Register automatically sets the pointer to the Red Look Up Table For example writing a value 03 into the Look Up Table Address R
274. on Research and Development Vancouver Design Center define FONT_DOUBLE_WIDTH 0x01 define FONT_DOUBLE_HEIGHT 0x02 enum RED GREEN BLUE y Page 75 PARAR ARA RIA RRA RRA RARA RAR RARA RRA RRA RRA RARA RRA RRA RR ARA RAR RARAS typedef struct tagHalStruct char szIdString 16 WORD wDetectEndian WORD wSize BYTE Reg MAX_REG 1 DWORD dwC1kI DWORD dwDispMem WORD wFrameRate HAL STRUCT typedef HAL STRUCT PHAL STRUCT ifdef INTEL typedef HAL_S else typedef HAL_S endif RUCT far LPHAL STRUCT RUC LPHAL STRUCT Input Clock Frequency in kHz LR RS hes FUNCTION PROTO TYP E E Initialization int seRegisterDevice seSetInit int device seInitHal int int void const LPHAL_ STRUCT lpHalInfo y int Device Miscellaneous seGetId pra Jy oid seGetHalVersion const char pVersion sRevision nt int nDevID int ar t seSetBitsPerPixel int nDevID int int t seGetBytesPerScanline int nDevID t seG nSize int nDevID int width id seDelay int nMilliSeconds t seGetLastUsableByte nDevID t seSetHighPerformance int nDevID t seGetBitsPerPixel int nDevID P P YP DVD COCE O p int Por bob B e tg po Advanced const char pStatus int pB
275. on Research and Development Vancouver Design Center 2 Initialization This section describes the register settings and steps needed to initialize the SED1374 The first step toward initializing the SED 1374 is to set the control registers The SED 1374 then generates the proper control signals for the display After setting the control registers the Look up Table must be programmed with meaningful values This section does not cover setting Look Up Table values See Section 4 on page 14 of this manual for Look up Table programming details The following initialization presented in table form provides the sequences and values to set the registers The notes column comments the reason for the particular value being written This example writes to all the control registers In practice it may be possible to write to only a subset of the registers When the SED 1374 is first powered up all registers unless noted otherwise in the specification are set to zero This example programs these registers to zero to establish a known state The initialization enables the SED 1374 to control a panel with the following specifications e 320x240 color dual passive panel at 75Hz e Color Format 2 8 bit data interface e 4 bit per pixel bpp 16 colors e 25 MHz input clock CLKD Table 2 1 SED1374 Initialization Sequence Register Value hex Notes See Also 01 0010 0000 20 Sel
276. ontrol over landscape mode One reason for the additional support is to maintain a register set that was backward compatible with previous Epson LCD controllers When setting SwivelView mode it is possible that the horizontal and vertical non display time must be recalculated as a result of PCLK changing in response to the Swivel View mode selected or the clock selection method Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 41 Vancouver Design Center 7 5 Limitations The only limitation to using Swivel View mode on the SED 1374 is that split screen operation is not supported A comparison of the two SwivelView modes is as follows Table 7 1 Default and Alternate Swivel View Mode Comparison Item Default SwivelView Mode Alternate SwivelView Mode The width of the rotated image must be a power of 2 In most cases a virtual image is required where the right hand side of the virtual image is unused and memory is wasted For example a 160x240x8bpp image would normally require only 38 400 bytes possible within the 40K byte address space but the virtual image is 256x240x8bpp which needs 61 440 bytes not possible Memory Requirements Does not require a virtual image MCLK and hence CLK need to be 2x PCLK For example if the panel requires a 3MHz CLK need only be as fast as the required B01 then CLK must be 6MHz Note that Clock Requirements aa
277. opment Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374PLAY Diagnostic Utility X26A B 005 02 Issue Date 99 11 29 Epson Research and Development Page 3 Vancouver Design Center 1374PLAY 1374PLAY is a utility which allows the user to easily read write the SED1374 registers Look up Table and display memory The user interface for 1374PLAY is similar to the DOS DEBUG program commands are received from the standard input device and output is sent to the standard output device console for Intel and terminal for embedded platforms This utility requires the target platform to support standard I O 1374PLAY commands can be entered interactively using a keyboard monitor or they can be executed from a script file Scripting is a powerful feature which allows command sequences played back from a file thus avoiding having to retype lengthy sequences 1374PLAY must be configured to work with each different hardware platform Consult documentation for the program 1374CFG EXE which can be used to configure 1374PLAY This software is designed to work with a variety of embedded and personal computer PC environments For embedded environments the model employed is that of host target It is assumed that the system has a means of downloading software from the host to the target platform Typically this is done by a serial communication link Alternative methods include EPROM parallel port connection or network connection It is beyond
278. ot driven by the SED1374 during non SED1374 bus cycles A single resistor is used to speed up the rise time of the WAIT TA signal when terminating the bus cycle The following diagram shows a typical implementation of the MCF5307 to SED1374 interface MCF5307 SED1374 A 16 31 AB 15 0 D 0 15 DB 15 0 CS4 CS Vcc 470 TA WAIT WES WE1 WE2 WEO OE RD WR CM RDA BCLKO BUSCLK RESET RESET Figure 4 1 Typical Implementation of MCF 5307 to SED1374 Interface Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1374 Issue Date 99 01 05 X26A G 01 1 02 Page 14 Epson Research and Development Vancouver Design Center 4 2 SED1374 Hardware Configuration The SED 1374 uses CNFO through CNF4 and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Table 4 1 Summary of Power On Reset Options and Table 4 2 Host Bus Interface Selection shows the settings used for the SED1374 in this interface Table 4 1 Summary of Power On Reset Options SED1374 value on this pin at the rising edge of RESET is used to configure 0 1 Pin Name 0 1 CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Little Endian CNF4 Active low LCDPWR signal Active high LCDPWR signal configuration for MFC5307 support Table 4 2 Host Bu
279. otect e AM 0 enable alternate bus master access to the SED1374 e C I 1 disable CPU space access to the SED1374 e SC 1 disable Supervisor Code space access to the SED1374 e SD 0 enable Supervisor Data space access to the SED1374 e UC 1 disable User Code space access to the SED1374 e UD 0 enable User Data space access to the SED1374 e V 1 global enable Valid for the chip select The following options should be selected in the chip select control registers CSCR4 5 e WS0 3 0 no internal wait state setting e AA 0 no automatic acknowledgment e PS 1 0 1 0 memory port size is 16 bits e BEM 0 Byte enable write enable active on writes only e BSTR 0 disable burst reads e BSTW 0 disable burst writes Interfacing to the Motorola MCF5307 ColdFire Microprocessor SED1374 Issue Date 99 01 05 X26A G 011 02 Page 16 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1374 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1374CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1374 test utilities and Windows CE v2 0 display drivers are ava
280. output signal which is configurable as active high or active low by the CNF4 signal status on the rising edge of the RESET signal For the proper operation of the VDDH power supply LCDPWR must be configured as active low Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1374 Issue Date 98 10 26 X26A G 005 01 Page 18 Epson Research and Development Vancouver Design Center 6 13 CPU Bus Interface Header Strips SED1374 X26A G 005 01 All of the CPU Bus interface pins of the SED1374 are connected to the header strips H1 and H2 for easy interface to a CPU Bus other than ISA Refer to Table 4 1 CPU BUS Connector H1 Pinout on page 11 and Table 4 2 CPU BUS Connector H2 Pinout on page 12 for specific settings Note These headers only provide the CPU Bus interface signals from the SED1374 When another host bus interface is selected by CNF 3 0 and BS appropriate external decode logic MUST be used to access the SED1374 Refer to Table 5 1 Host Bus Interface Pin Mapping on page 13 for connection details SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 Epson Research and Development Vancouver Design Center 7 Parts List Page 19 It
281. owest power consumption with some display mode limitations The alternate mode uses more power but offers greater display flexibility SED1374 X26A G 002 02 Page 40 SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center In return for using less power the default SwivelView imposes the restriction that the SwivelView display width must be a power of two e g 64 128 256 512 The physical display does not need to be a power of two wide The difference can be treated as a virtual width In addition scrolling in default Swivel View mode is restricted to two lines Alternate SwivelView mode requires more power as the internal clocks are run faster In return for a higher power consumption the power of two width restriction is removed Also the display can be scrolled one line at a time One benefit to removing the power of two width restriction is that panels which might not have been able to be used in SwivelView mode due to a lack of memory may now be used Clocking for the SED1374 works as follows An external clock source supplies CLKI the input clock CLKI is routed through the Input Clock Divide from Mode Register 1 REG 02h bit 4 and is either divided by two or passed on This signal is now the Operating Clock CLK from which PCLK and MCLK are derived In Swivel View mode the CLK signal may be divided down by 0 2 4 or 8 before PCLK and MCLK are derived SwivelView mode offers additional clocking c
282. p bmp_file a time 1 p 1 Where bmp_file the name of the file to display a time automatic mode returns to the operating system after time seconds If time is not specified the default is 5 seconds This option is intended for use with batch files to automate displaying a series of images 1 override default configuration settings and set landscape display mode p override default configuration settings and set portrait display mode displays the Help screen e 1374BMP currently views only Windows BMP format images 1374BMP Demonstration Program SED1374 Issue Date 98 10 20 X26A B 006 01 Page 4 Epson Research and Development Vancouver Design Center Program Messages SED1374 X26A B 006 01 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 1374 device A 1374 device was not found at the configured addresses Check the configuration address using the 1374CFG configuration program ERROR Did not detect 1374 The HAL was unable to read the revision code register on the SED1374 Ensure that the SED 1374 hardware is installed and that the hardware platform has been set up correctly 1374BMP Demonstration Program Issue Date 98 10 20 EPSON SED1374 Embedded Memory Color LCD Controller 1374PWR Power Save Utility Document Number X26A B 007 01 Copyright 1998 Epson Research
283. pdated as appropriate Please check the Epson Research and Development Website at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs erd epson com Interfacing to the NEC VR4102 Microprocessor SED1374 Issue Date 99 01 05 X26A G 008 04 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 2 1 The NEC VR4102 System Bus 2 1 1 Overview SED1374 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4102 offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR4102 is designed around the RISC architecture developed by MIPS This microprocessor is designed around the 66MHz VR4100 CPU core which supports 64 bit processing The CPU communicates with the Bus Control Unit BCU with its internal SysAD bus The BCU in turn communicates with external devices with its ADD and DAT buses that can be dynamically sized to 16 or 32 bit operation The NEC VR4102 has direct support for an external LCD controller Specific control signals are assigned for an external LCD controller t
284. port EPSON LCD controllers The ITE IT8368E provides eleven Multi Function IO pins MFIO Configuration registers may be used to allow these MFIO pins to provide the control signals required to implement the SED1374 CPU interface The TX3912 processor only provides addresses A 12 0 therefore devices requiring more address space must use an external device to latch A 25 13 The IT8368E s MFIO pins can be configured to provide this latched address SED1374 3 3V TX3912 t lO Vpp CORE Vpp HA 12 0 gt AB 12 0 ENDIAN gt AB 15 13 HD 31 24 4 gt DB 7 0 HD 23 16 le gt DB 15 8 a System RESET gt RESET DD pull up CARDxWAIT e WAIT DCLKOUT See text i gt CLKI LHA 23 MFIO 10 gt WE1 LHA 22 MFIO 9 WEO LHA 21 MFIO 8 gt RD1 LHA 20 MFIO 7 gt RDO LHA 19 MFIO 6 gt CS LHA 15 13 MFIO 2 0 sll ld Figure 3 1 SED1374 to TX3912 Connection Using an IT8368E SED1374 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 01 Issue Date 98 11 09 EPSON Research and Development Page 11 Vancouver Design Center The Generic 1 host interface control signals of the SED1374 are asynchronous with respect to the SED1374 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should
285. presentation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the PC Card Bus X26A G 009 02 Issue Date 98 12 10 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T introduction 500 ci Re ce ene Bee Game SCTE arte ae Re AA dws Gawd A 7 2 Interfacing tothe PC CardBus 2 2 2 2 ee eee es 8 2 1 ThePCCardSystemBus 2 2 25 2 5 8 ZA gt PC CardiOverview cc 6 Ane a Bee eed Hn ie Se be Ba OE 8 2 1 2 Memory Access Cycles o o ee ee 8 3 SED1374 Bus Interface o E A a a ewe 10 3 1 Bus Interface Modes 2 E ee ee LO 3 2 Generic H Interface Mode 2 2 2 0 2 0 86 11 4 PC Card to SED1374 Interface 12 4 1 Hardware Commnections dee A e oa a o aae aaa n a 4 2 SED1374 Hardware Configuration oa aoa a a a a eee 13 4 3 PAL Equations oos 30 20 aa e a a ee a E Aa ee 14 4 4 Register Memory Mapping aaa 14 SoftWa re ps ra cng twee ee es She ee AA A a ees 15 Referenc s aora i yon o a oR ee ee ee ee a
286. processor Issue Date 99 01 05 Epson Research and Development Page 19 Vancouver Design Center 4 4 MPC821 Chip Select Configuration The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh so the SED1374 is addressed starting at 40 0000h The SED1374 uses a 64K byte segment of memory starting at this address with the first 40K bytes used for the display buffer and the upper 32 bytes of this memory block used for the SED 1374 internal registers Chip select 4 is used to control the SED1374 The following options are selected in the base address register BR4 BA 0 16 0000 0000 0100 0000 0 set starting address of SED1374 to 40 0000h AT 0 2 0 ignore address type bits PS 0 1 1 0 memory port size is 16 bits PARE 0 disable parity checking WP 0 disable write protect MS 0 1 0 0 select General Purpose Chip Select module to control this chip select V 1 set valid bit to enable chip select The following options were selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits SED1374 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS assertion by 1 2 clock cycle from address lines BI 1 assert Burst Inhibit SCY 0 3 0 wait state selection this field is ignored since external transfer acknowledge is used see SETA below
287. purpose RAM based pattern generator which can control address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application note the GPCM is used instead of the UPM since the GPCM has enough flexibility to accommodate the SED 1354 and it is desirable to leave the UPM free to handle other interfacing duties such as EDO DRAM SED1374 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 02 Issue Date 99 01 05 Epson Research and Development Vancouver Design Center 3 SED1374 Host Bus Interface Page 13 This section is a summary of the host bus interface modes available on the SED1374 and offers some detail on the Generic 1 host bus interface used to implement the interface to the MPC821 bus 3 1 Host Bus Interface Modes The SED 1374 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Six host bus interface modes are supported e Hitachi SH 4 e Hitachi SH 3 e Motorola MC68000 using Upper Data Strobe Lower Data Strobe e Motorola MC68020 MC68030 MC683xx using Data Strobe DS
288. py the range FFEOh through FFFFh The TMPR3912 22U demultiplexed address lines A16 and above are ignored if the SED 1374 is used thus it is aliased 1024 times at 64K byte intervals over the 64M byte PC Card slot 1 memory space If the SED1375 is used address lines A17 and above are ignored therefore the SED1375 is aliased 512 times at 128K byte intervals The TMPR3912 22U control signal CARDREG is ignored therefore the SED 1374 also takes up the entire PC Card slot 1 configuration space Note If aliasing is undesirable additional decoding circuitry must be added 3 3 SED1374 75 Configuration and Pin Mapping The SED1374 75 host bus interface is configured at power up by latching the state of the CNF 3 0 pins Pin BS also plays a role in host bus interface configuration One additional configuration pin for the SED1374 CNF4 is also used to set the polarity of the LCDPWR signal The table below shows the configuration pin connections to configure the SED1374 75 for use with the TMPR3912 22U microprocessor Table 3 1 SED1374 75 Configuration for Generic 2 Bus Interface SED1374 Value hard wired on this pin is used to configure Configuration Pin 1 IO Vpp 0 Vss Generic Generic 1 CNF 2 0 1 Big Endian configuration for Toshiba TMPR3912 22U host bus interface When the SED1374 75 is configured for Generic 2 bus interface mode the host interface pins are mapped as in the table below
289. r International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 01 Issue Date 98 10 26 Epson Research and Development Vancouver Design Center 1 Introduction 1 1 o a A W KN 6 1 6 1 1 Display Adapter Card Support 6 1 2 Expanded Memory Manager 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 6 10 6 11 6 12 6 13 7 Parts List 8 Schematic Diagrams Installation and Configuration LCD Interface Pin Mapping CPU Bus Interface Connector Pinouts Host Bus Interface Pin Mapping Technical Description Table of Contents Features ISA Bus Support Non ISA Bus Support Embedded Memory Support Decode Logic Clock Input Support LCD Panel Voltage Setting Monochrome LCD Panel Support Color Passive LCD Panel Support Color TFT D TFD LCD Panel Support Power Save Modes Adjustable LCD Panel Negative Power Supply Adjustable LCD Panel Positive Power Supply CPU Bus Interface Header Strips SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 Page 3 SED1374 X26A G 005 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User
290. ration Program Issue Date 98 10 27 SED1374 X26A B 001 01 Page 8 Epson Research and Development Vancouver Design Center Panel Information C Mono Color Single Dual I Mask FPSHIFT Tl Format 2 J Frame Repeat Mod Count C STN TFT C 4Bit C 8Bit FPLine Start FPFrame Start Polarity Hi Lo FPLine FPFrame C Dimensions E Figure 2 Panel Information This section of the 1374CFG dialog describes the panel connected to the SED1374 Each of the settings are described briefly below Mono Color select mono for monochrome panels or color for color panels This option is STN specific and is disabled if TFT is selected Single Dual select single when connected to a single panel or dual for connection to a dual panel This option is STN specific and is disabled if TFT is selected e STN TFT select STN for passive panels or TFT for active panels Switching between these two panel types causes visible changes to take place to the configuration dialog box e 4 Bit 8 Bit here the panel data width is selected When STN panel types are selected the options are 4 bit and 8 bit When TFT panels are selected the options will be 9 bit and 12 bit e Dimensions in the left selection box horizontal pixels can be chosen from the list or typed in in the right selection box vertical lines in pixels can be selected from the list or typed in e M
291. rectly supports 4 and 8 bit dual and single monochrome passive LCD panels All necessary signals are provided on the 40 pin ribbon cable header J5 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J5 Pinout on page 10 for specific connection information 6 8 Color Passive LCD Panel Support The SED 1374 directly supports 4 and 8 dual and single color passive LCD panels All the necessary signals are provided on the 40 pin ribbon cable header J5 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J5 Pinout on page 10 for specific connection information 6 9 Color TFT D TFD LCD Panel Support SED1374 X26A G 005 01 The SED 1374 directly supports 9 and 12 bit active matrix color TFT D TFD panels All the necessary signals can also be found on the 40 pin LCD connector J5 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J5 Pinout on page 10 for connection infor mation SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 98 10 26 Epson Research and Development Page 17 Vancouver Design Center 6 10 Power Save Modes The SED 1374 supports one hardware and one software power save mode These modes are controlled by the utility 1374PWR The h
292. red e pixel and frame rates e power budget e part count e maximum SED1374 clock frequencies The SED1374 also has internal clock dividers providing additional flexibility Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 98 11 09 EPSON Research and Development Vancouver Design Center 2 2 Memory Mapping and Aliasing Page 9 The SED1374 requires an addressing space of 64K bytes The on chip display memory occupies the range 0 through 9FFFh The registers occupy the range FFEOh through FFFFh The PR31500 PR31700 demultiplexed address lines A16 and above are ignored thus the SED 1374 is aliased 1024 times at 64K byte intervals over the 64M byte PC Card slot 1 memory space In this example implementation the PR31500 PR31700 control signal CARDREG is ignored the SED 1374 also takes up the entire PC Card slot 1 configuration space Note If aliasing is undesirable additional decoding circuitry must be added 2 3 SED1374 Configuration and Pin Mapping The SED 1374 is configured at power up by latching the state of the CNF 4 0 pins Pin BS also plays a role in host bus interface configuration For details on configuration refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx The table below shows those configuration settings relevant to the direct connection approach Table 2 1 SED1374 Configuration for Direct Connection SED1374 Value hard wire
293. reen on page 30 14 0000 0011 03 15 0000 0000 00 16 00000000 00 SetLUT control registers to 0 for this example ps Tove eee 17 0000 0000 00 18 0000 0000 00 i GPIO control and status registers set to 0 19 0000 0000 00 1A 0000 0000 00 Set the scratch pad bits to 0 1B 0000 0000 00 We are not setting up SwivelView mode so set this register to 0 1C 0000 0000 00 Line Byte Count is only required for SwivelView mode 1E 1F 0000 0000 00 These registers are reserved and should not be written to 2 1 Frame Rate Calculation The system the SED1374 is being configured for dictates certain physical constraints such as the width and height of the panel and the video system input clock The following are the formulae for determining the frame rate of a panel The frame rate for a single passive or TFT panel is calculated as follows PCLK FrameRate DPF ANDP x VDP VNDP for a dual passive panel the formula is FrameRate AE gt eee 2 x HDP HNDP x VNDP where PCLK Pixel clock in Hz HDP Horizontal Display Period in pixels HNDP Horizontal Non Display Period in pixels VDP Vertical Display Period in lines VNDP Vertical Non Display Period in lines To achieve the desired frame rate the HNDP and VNDP values can be manipulated The example below is a generic routine to calculate HNDP and VNDP from a desired frame rate Programming Notes
294. rface to the PC Card bus 3 1 Bus Interface Modes The SED 1374 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Six bus interface modes are supported Hitachi SH 4 Hitachi SH 3 Motorola MC68000 using Upper Data Strobe Lower Data Strobe Motorola MC68020 MC68030 MC683xx using Data Strobe DSACKx Generic 1 Chip Select plus individual Read Enable Write Enable for each byte Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte The SED 1374 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping Eta che SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vgs connect to lO Vpp RD WR RD WR RD WR R W R W RD1 connect to lO Vpp
295. rite cycles and WEO is the enable signal for a write access These must be generated by external decode hardware based upon the control outputs from the host CPU RD is the read enable for the SED1374 75 to be driven low when the host CPU is reading data from the SED 1374 75 RDA must be generated by external decode hard ware based upon the control outputs from the host CPU WAIT is a signal which is output from the SED 1374 75 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the SED1374 75 may occur asynchronously to the display update it is possible that contention may occur in accessing the 1374 75 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the SED1374 75 for Generic 2 mode and must be tied high connected to IOVDD 3 3V RD WR must also be tied high SDU1374 75 TMPR3912 22U CPU Module Issue Date 98 12 23 X00A G 004 01 Page 10 EPSON Research and Development Vancouver Design Center 3 TMPR3912 22U and SED1374 75 Interface 3 1 Hardware Connections The SED1374 75 occupies the TMPR
296. rnate Swivel View Mode Comparison Item Default SwivelView Mode Alternate SwivelView Mode Memory Requirements The width of the rotated image must be a power of 2 In most cases a virtual image is required where the right hand side of the virtual image is unused and memory is wasted For example a 160x240x8bpp image would normally require only 38 400 bytes possible within the 40K byte address space but the virtual image is 256x240x8bpp which needs 61 440 bytes not possible Does not require a virtual image Clock Requirements CLK need only be as fast as the required PCLK MCLK and hence CLK need to be 2x PCLK For example if the panel requires a 3MHz PCLK then CLK must be 6MHz Note that 25MHz is the maximum CLK so PCLK cannot be higher than 12 5MHz in this mode Power Consumption Lowest power consumption Higher than Default Mode Panning Vertical panning in 2 line increments Vertical panning in 1 line increments Performance Nominal performance Higher performance than Default Mode 12 4 SwivelView Mode Limitations The only limitation to using Swivel View mode on the SED1375 is that split screen operation is not supported Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Page 84 Epson Research and Development Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the SED13
297. rtical Non Vertical Non Vertical Non Vertical Non Display n a Display Display Display Display Display Display Status Period Bit5 Period Bit4 Period Bit3 Period Bit2 Period Bit 1 Period Bit 0 bit 7 Vertical Non Display Status This bit 1 during the Vertical Non Display period bits 5 0 Vertical Non Display Period These bits specify the vertical non display period VerticalNonDisplayPeriod lines REG OAh Note This register should be set only once on power up during initialization REG OBh MOD Rate Register Address FFEBh Read Write ia na MOD Rate MOD Rate MOD Rate MOD Rate MOD Rate MOD Rate Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O bits 5 0 MOD Rate Bits 5 0 When the value of this register is 0 the MOD output signal toggles every FPFRAME For a non zero value the value in this register 1 specifies the number of FPLINEs between toggles of the MOD output signal These bits are for passive LCD panels only REG 0Ch Screen 1 Start Address Register LSB Address FFECh Read Write Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Address Address Address Address Address Address Address Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 0Dh Screen 1 Start Address Register MSB Address FFEDh Read Write Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen
298. rting address is set at DOOOOh Starting at this address the board design decodes a 64K byte segment accommodating both the 40K byte display buffer and the SED1374 internal register set The SED1374 registers are mapped into the upper 32 bytes of the 64K byte segment DFFE0h to DFFFFh 6 4 Decode Logic All the required decode logic is provided through a TIBPAL16L8 15 PAL U7 socketed This PAL contains the following equations ICS Address gt hD0000 amp Address lt hDFFFF amp REFRESH RESET IMEMCS16 Addressl gt h0C0000 amp Addressl lt hODFFFF RESET_ RESET SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual SED1374 Issue Date 98 10 26 X26A G 005 01 Page 16 Epson Research and Development Vancouver Design Center 6 5 Clock Input Support The input clock CLKD frequency can be up to 50 0MHz for the SED1374 if the internal clock divide by 2 is set If the clock divide is not used the maximum CLKI frequency is 25MHz A 25 0MHz oscillator U2 socketed is provided as the default clock source 6 6 LCD Panel Voltage Setting The SDU1374B0C board supports both 3 3V and 5 0V LCD panels through the single LCD connector J5 The voltage level is selected by setting jumper J4 to the appropriate position Refer to Table 2 3 Jumper Settings on page 9 for setting this jumper 6 7 Monochrome LCD Panel Support The SED 1374 di
299. run under Windows 95 98 or Windows NT 4 0 There is no installation program for 1374CFG Installation to a local drive is done by copying 1374CFG EXE and 1374CFG HLP to your hard drive and optionally creating a link on the Windows desktop for easy access to the program Open the drive and folder where you copied 1374CFG EXE and double click the icon to start the program Optionally if you created a link to the program on your desktop double click the link icon 1374CFG EXE Configuration Program Issue Date 98 10 27 Epson Research and Development Vancouver Design Center 1374CFG Page 7 The 1374CFG window has four main sections Panel information includes Dimensions LookUp Table Miscellaneous Options and System settings Bm ES gt 1374 Config Mono C Singe C STN C 4Bit C Color C Dual C TFT C Bit Dimensions H I Mask FPSHIFT I Format 2 FT Frame Repeat Mod Count FPLine Start FPFrame Start Misc Options I HW Video Invert Enable T HW Power Save Enable I High Performance J Portrait Mode Polarity Hi Lo FPLing f FPFrame C System Memory Location Frame Rate fps Input Clock kHz m LookUp Table C 1BPP C 2BPP C 4BPP C 8BPP I Bypass LUT Open Save Exit Help Figure 1 1374CFG Window The following sections describe each of the main sections of the configuration dialog box 1374CFG EXE Configu
300. s Document Number X26A G 002 xx 6 2 Document Sources e PC Card web page http www pc card com e EPSON Research and Development web page http www erd epson com SED1374 Interfacing to the PC Card Bus X26A G 009 02 Issue Date 98 12 10 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers SED1374 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 PC Card Standard PCMCIA North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http vww eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Personal Computer Memory Card International Association 2635 North First Street Suite 209 San Jose CA 95134 Tel 408 433 2273 Fax 408 433 9558 http www pc card com Interfacing to the PC Card Bus Issue Date 98 12 10 Page 17 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temas
301. s BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the SED1374 for Generic 2 mode and should be tied high connected to IO Vpp RD WR should also be tied high Interfacing to an 8 bit Processor Issue Date 99 05 04 Epson Research and Development Page 11 Vancouver Design Center 4 8 Bit Processor to SED1374 Interface 4 1 Hardware Description Note Generic 8 bit Bus SED1374 A 15 0 gt AB 15 0 D 7 0 e 1 gt DB 7 0 gt DB 15 8 Decoder gt cs WAIT WAIT WE gt WEO RD RD AO o BHE WE1 10 Vop RD WR BS BUSCLK BUSCLK System RESET y RESET When connecting the SED1374 RESET pin the system designer should be aware of all conditions that may reset the SED1374 e g CPU reset can be asserted during wake up from power down modes or during debug states The interface between the SED1374 and an 8 bit processor requires minimal glue logic A decoder is used to generate the chip select for the SED1374 based on where the SED1374 is mapped into memory Alternatively if the processor supports a chip select module it can be programmed to generate a chip select for the SED1374 without the need of an address decoder An inverter inverts AO to generate the Byte High Enable signal for the SED1374 If the 8 bit host interface has an active high WAIT signal it must be inverted as well In order to suppor
302. s SED1374 to TX3912 Direct Connection 00200000000 0000 8 SED1374 to TX3912 Connection Using an IT8368E o o 10 Interfacing to the Toshiba MIPS TX3912 Processor SED1374 X26A G 004 01 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to the Toshiba MIPS TX3912 Processor X26A G 004 01 Issue Date 98 11 09 EPSON Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the SED1374 Embedded Memory Color Graphics LCD Controller and the Toshiba MIPS TX3912 Processor For further information on the SED 1374 refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx For further information on the TX3912 contact Toshiba or refer to the Toshiba website under semiconductors at http www toshiba com taec nonflash indexproducts html For further information on the ITE IT8368E refer to the IT8368E PC Card GPIO Buffer Chip Specification 1 1 General Description The Toshiba MIPS TX3912 processor supports up to two PC Card PCMCIA slots It is through this host bus interface that the SED1374 connects to the TX3912 processor The SED1374 can be successfully interfaced using one of two configurations e Direct connection to TX3912 see Section 2 Direct Connection to the Toshiba TX3912 on page 8
303. s Interface Pin Mapping LCD Interface Pin Mapping Absolute Maximum Ratings Recommended Operating Conditions Input Specifications o oo Output Specifications o SH 4 Timing sao a a E e SH 3 Bus Timing M68K 1 Bus Timing MC68000 M68K 2 Timing MC68030 Generic 1 Timing 00 Generic 2 Timing 0 Clock Input Requirements Power Down Up Timing Panel Data Format 0 Gray Shade Color Mode Selection High Performance Selection Inverse Video Mode Select Options Hardware Power Save GPIOO Operation Software Power Save Mode Selection Look Up Table Access o Selection of SwivelView Mode Selection of PCLK and MCLK in SwivelView Mode Look Up Table Configurations Default and Alternate Swivel View Mode Comparison Power Save Mode Selection Software Power Save Mode Summary Hardware Power Save Mode Summary Power Save Mode Function Summary SED1374 Internal Clock Requirements Hardware Functional Specification Issue Date 99 04 29 Page 5 SED1374 X26A A 001 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Hardware Functional Specificat
304. s Interface Selection CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 X SH 4 bus interface 0 0 1 X SH 3 bus interface 0 1 0 X reserved 0 1 1 X MC68K bus interface 1 16 bit 1 0 0 X reserved 1 0 1 X MC68K bus interface 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 1 Generic 2 16 bit configuration for MFC5307 support SED1374 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X26A G 011 02 Issue Date 99 01 05 Epson Research and Development Page 15 Vancouver Design Center 4 3 MCF5307 Chip Select Configuration Chip Selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes However these chip selects would normally be needed to control system RAM and ROM Therefore one of the IO chip selects CS2 through CS7 is required to address the entire address space of the SED1374 These IO chip selects have a fixed 2M byte block size In the example interface chip select 4 is used to control the SED1374 The SED1374 only uses a 64K byte block with its 40K byte display buffer residing at the start of this 64K byte block and its internal registers occupying the last 32 bytes of this block This 64K byte block of memory will be shadowed over the entire 2M byte space The CSBAR register should be set to the upper 8 bits of the desired base address The following options should be selected in the chip select mask registers CSMR4 5 e WP 0 disable write pr
305. s Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374VIRT Display Utility X26A B 004 01 Issue Date 98 10 20 Epson Research and Development Page 3 Vancouver Design Center 1374VIRT 1374VIRT demonstrates the virtual display capability of the SED1374 A virtual display is where the image to be displayed is larger than the physical display device The display surface is used a viewing window The entire image can be seen only by panning and scrolling 1374VIRT must be configured to work with each different hardware platform Consult documentation for the program 1374CFG EXE which can be used to configure 1374VIRT This software is designed to work with a variety of embedded and personal computer PC environments For embedded environments the model employed is that of host target It is assumed that the sys
306. screen to function the starting address in display buffer for the upper portion screen 1 and the lower portion screen 2 must be specified Screen 1 is always displayed above screen 2 on the display regardless of the location of their start addresses DevID registered device ID SernlAddr offset in bytes to the start of screen 1 Sern2Addr offset in bytes to the start of screen 2 ERR_OK operation completed with no problems It is assumed that the system has been properly initialized prior to calling seSplitInit int seSplitScreen int DevID int Screen int VisibleScanlines Description Parameters Return Value Note Changes the relevant registers to adjust the split screen according to the number of visible lines requested WhichScreen determines which screen 1 or 2 to base the changes on The smallest surface screen can display is one line This is due to the way the SED1374 operates Setting Screen 1 Vertical Size to zero results in one line of screen being displayed The remainder of the display will be screen 2 image DevID registered device ID Screen must be set to 1 or 2 or use the constants SCREEN1 or SCREEN2 VisibleScanlines number of lines to display for the selected screen ERR_OK operation completed with no problems ERR_HAL_BAD_ARG argument VisibleScanlines is negative or is greater than vertical panel size or WhichScreen is not SCREEN or SCREEN 2 seSplitInit must be called before
307. se IO space maintains software and hardware compatibility with hosts such as the Intel x86 architecture which address peripherals independently from memory space Bit notation follows the convention used by most micro processors the high bit is the most significant Therefore signals A25 and D15 are the most significant bits for the address and data bus respectively Support is provided for on chip DMA controllers To find further information on these topics refer to Section 6 References on page 16 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of either the CE1 and or the CE2 card enable signals The cycle ends once these signals are de asserted Bus cycles can be lengthened using the WAIT signal Note The PCMCIA 2 0 JEIDA 4 1 and later PC Card Standard support the two signals WAIT and RESET which are not supported in earlier versions of the standard The WAIT signal allows for asynchronous data transfers for memory attribute and IO ac cess cycles The RESET signal allows resetting of the card configuration by the reset line of the host CPU 2 1 2 Memory Access Cycles SED1374 A data transfer is initiated when the memory address is placed on the PC Card bus and one or both of the card enable signals CE1 and CE2 are driven low REG must be kept inactive If only CE1 is driven low 8 bit data transfers are enabled and AO specifies whether the even or o
308. seDrawLine Drawing DWORD color DWORD pVal int x2 int nDevID int x int y y At y 2y int nDevID int x int y int nDevID int xl int yl int seDrawRect till ys int seDrawCircle BYTE SolidFill int nDevID int xl int yl int x2 int y2 int nDevID int xCenter int yCenter if DWORD color DWORD col BOOL Solid or int radius DWORD color Text char fmt i DWORD background FontAttr int seDrawText int nDevID y int seSetCursor int row int col seSetColor DWORD foreground seSetFont BYTE BYTE int int FontSize Color pLut pLut int index seSetLut seGetLut int nDevID seSetLutEntry seGetLutEntry BYTE BYTE int int nDevID int E BYTE BYTE int int nDevID pEntry p int int nDevID int index Entry ndif _HAL H_ es Kk Af APPCFG H Application configuration information Created 1998 Vancouver Design Centre SED1374 X26A G 002 02 Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 77 Vancouver Design Center Copyright c 1998 Epson Research and Development Inc All Rights Reserved The data in this file was generated using 1374CFG EXE The config
309. sign Center Table 2 1 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 Table 4 9 Table 4 10 Table 4 11 Table 5 1 Table 7 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 7 1 Figure 7 2 List of Tables SED1374 Initialization Sequence o 02 02 0000 2 Bpp Banking Scheme o e 4 Bpp Banking Scheme o 0 000000 eee eee 8 Bpp Banking Scheme e Look Up Table Configurations e Recommended LUT Values for 1 Bpp Color Mode LUT Values for 2 Bpp Color Mode o o e Suggested LUT Values to Simulate VGA Default 16 Color Palette Suggested LUT Values to Simulate VGA Default 256 Color Palette Recommended LUT Values for 1 Bpp Gray Shade Suggested Values for 2 Bpp Gray Shade oo o Suggested LUT Values for 4 Bpp Gray Shade o Number of Pixels Panned Using Start Address o Default and Alternate SwivelView Mode Comparison List of Figures Pixel Storage for 1 Bpp 2 Colors Gray Shades in One Byte of Display Buffer Pixel Storage for 2 Bpp 4 Colors Gray Shades in One Byte of Display Buffer Pixel Storage for 4 Bpp 16 Colors Gray Shades in One Byte of Display Buffer Pixel Storage for 8 Bpp 256 Colors
310. son Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 NEC Electronics Inc NEC Electronics Inc U S A Santa Clara California Tel 800 366 9782 Fax 800 729 9288 http Awww nec com SED1374 X26A G 008 04 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http Awww eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the NEC VR4102 Microprocessor Issue Date 99 01 05 EPSON SED1374 Embedded Memory Color LCD Controller Interfacing to the PC Card Bus Document Number X26A G 009 02 Copyright O 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any re
311. son Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 SED1374 X26A G 013 01 Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 Interfacing to an 8 bit Processor X26A G 013 01 Issue Date 99 05 04
312. ss Table 4 2 4 Bpp Banking Scheme Red LUT Green LUT Blue LUT Addresses Addresses Addresses 0 0 0 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8 8 9 9 9 A A A B B B C C C D D D E E E F F F Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 18 SED1374 X26A G 002 02 Epson Research and Development Vancouver Design Center At 8 bpp the lookup scheme gets a little more complicated Each byte of display data contains 3 bits of red lookup 3 bits of green lookup and 2 bits of blue lookup The 16 addresses of the Look Up Table are divided into 2 eight element banks for the red and green components and 4 four element banks for the blue component Table 4 3 8 Bpp Banking Scheme Red Green Red LUT Green LUT Blue Blue LUT Bank Addresses Addresses Bank Addresses 0 0 0 1 1 1 0 2 2 2 3 3 3 0 4 4 4 5 5 5 1 6 6 6 7 7 7 8 8 8 9 9 9 2 A A A B B B 4 C C C D D D 3 E E E F F F Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 19 Vancouver Design Center REG 17h Look Up Table Data Register Read Write a i m nja LUT Data LUT Data LUT Data LUT Data a a 5 Bit 3 Bit 2 Bit 1 Bit 0 LUT Data 4 2 Look Up Table LUT
313. t for PC only Both modes b changes the color depth bits per pixel ESC exits 1374SPLT 1374SPLT Example 1 Type 1374splt a to automatically move the split screen 2 Press b to change the color depth from 1 bit per pixel to 2 bit per pixel 3 Repeat step 2 for the remaining color depths 4 and 8 bit per pixel 4 Press lt ESC gt to exit the program SED1374 1374SPLT Display Utility X26A B 003 01 Issue Date 98 10 20 Epson Research and Development Page 5 Vancouver Design Center Program Messages 1374SPLT Display Utility Issue Date 98 10 20 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 1374 device A 1374 device was not found at the configured addresses Check the configuration address using the 1374CFG configuration program ERROR Did not detect 1374 The HAL was unable to read the revision code register on the SED 1374 Ensure that the SED1374 hardware is installed and that the hardware platform has been set up correctly SED1374 X26A B 003 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SED1374 1374SPLT Display Utility X26A B 003 01 Issue Date 98 10 20 EPSON SED1374 Embedded Memory Color LCD Controller 1374VIRT Display Utility Document No X26A B 004 01 Copyright 1998 Epson Research and Development Inc All Right
314. t Vancouver Design Center printf nERROR Could not register SED1374 device exit 1 Get the product code to verify this is an SED1374 NOTE If the SED1374 design is modified then the ae product identification change Additional IDs ex will have to be checked for Bef seGetId Device Chipld if ID_SED1374F0A ChipId printf nERROR Did not detect an SED1374 exit 1 Initialize the SED1374 This step programs the registers with values taken from the HalInfo struct in appcfg h XZ if ERR_OK seSetInit Device printf nERROR Could not initialize device exit 1 The default initialization cleared the display Draw a 100x100 red rectangle in the upper left corner 0 0 of the display E7 seDrawRect Device 0 0 100 100 1 TRU E Pause here getch Clear the display Do this by writing 40960 bytes af seWriteDisplayBytes Device 0 0 FORTY_K Setup SwivelView mode ref Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Page 63 Vancouver Design Center seSetHWRotate Device PORTRAIT Draw a solid blue 100x100 rectangle in center of the display This starting co ordinates assuming a 320x240 display is 320 100 2 240 100 2 110 70 sy seDrawRect Device 110
315. t an 8 bit microprocessor with a 16 bit peripheral the low and high order bytes of the data bus must be connected together The following diagram shows a typical implementation of an 8 bit processor to SED1374 interface Figure 4 1 Typical Implementation of an 8 bit Processor to the SED1374 Generic 2 Interface Interfacing to an 8 bit Processor SED1374 Issue Date 99 05 04 X26A G 013 01 Page 12 Epson Research and Development Vancouver Design Center 4 2 SED1374 Hardware Configuration The SED 1374 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the SED1374 Hardware Functional Specification document number X26A A 001 xx for details The tables below show only those configuration settings important to the 8 bit processor interface The endian must be selected based on the 8 bit processor used Table 4 1 Configuration Settings Signal Low High CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Little Endian Big Endian CNF4 Active low LCDPWR signal Active high LCDPWR signal see configuration for 8 bit processor host bus interface Table 4 2 Host Bus Selection CNF2 CNF1 CNFO BS Host Bus Interface Sa required configuration for this application 4 3 Register Memory Mapping SE
316. t and returns the value in pDword Parameters DevID registered device ID Offset offset from start of the display buffer to read from pDword pointer to a DWORD to return the value in Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr is greater than 40 kb int seWriteDisplayBytes int DevID DWORD Offset BYTE Value DWORD Count Description This routine writes one or more bytes to display buffer at the offset specified by Addr If a count greater than one is specified all bytes will have the same value Parameters DevID registered device ID Offset offset from start of the display buffer to start writing at Value BYTE value to write Count number of bytes to write Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr or the value of Addr plus Count is greater than 40 kb Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 57 int seWriteDisplayWords int DevID DWORD Offset WORD Value DWORD Count Description Parameters Return Value Writes one or more WORDS to the display buffer at the offset specified by Addr If a count greater than one is specified all WORDS will have the same value DevID registered device ID Offset offset from start of the display buffer Value WORD value to write Count number of words to write ERR_OK operatio
317. tail on the Generic 2 host bus interface used to implement the interface to the VR4102 3 1 Bus Interface Modes The SED 1374 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Six bus interface modes are supported Hitachi SH 4 Hitachi SH 3 Motorola MC68000 using Upper Data Strobe Lower Data Strobe Motorola MC68020 MC68030 MC683xx using Data Strobe DSACKx Generic 1 Chip Select plus individual Read Enable Write Enable for each byte Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte The SED 1374 latches CNF 2 0 and BS to allow selection of the host bus interface on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping Eta che SH 3 SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 A 15 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vgs connect
318. tatus When the GPIOn pin is configured as an input the corresponding GPIO Status bit is used to read the pin input See REG 18h above When the GPIOn pin is configured as an output the corresponding GPIO Status bit is used to control the pin output SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Page 68 Epson Research and Development Vancouver Design Center REG 1Ah Scratch Pad Register Address FFFAh Read Write Scratch bit 7 Scratch bit 6 Scratch bit 5 Scratch bit 4 Scratch bit 3 Scratch bit 2 Scratch bit 1 Scratch bit 0 bits 7 0 Scratch Pad Register This register contains general use read write bits These bits have no effect on hardware REG 1Bh SwivelView Mode Register Address FFFBh Read Write SwivelView SwivelView SwivelView SwivelView HS nla na resewed Mode Pixel Mode Pixel Mode Enable Mode Select Clock Select Clock Select Bit 1 Bit O bit 7 Swivel View Mode Enable When this bit 1 SwivelView Mode is enabled When this bit 0 Landscape Mode is enabled bit 6 Swivel View Mode Select When this bit 0 Default Swivel View Mode is selected When this bit 1 Alternate SwivelView Mode is selected See Section 12 Swivel View on page 79 for further information on SwivelView Mode The following table shows the selection of Swivel View Mode Table 8 8 Selection of SwivelView
319. te Swivel View Mode requires a panel size of only 240x160 which needs only 38 400 bytes Alternate Swivel View Mode requires the memory clock MCLK to be at least twice the frequency of the pixel clock PCLK i e MCLK gt 2 x PCLK Because of this the power consumption in Alternate Swivel View Mode is higher than in Default SwivelView Mode The following figure shows how the programmer sees a 240x160 image and how the image is being displayed The application image is written to the SED1374 in the following sense A B C D The display is refreshed by the SED 1374 in the following sense B D A C SED1374 X26A G 002 02 Epson Research and Development Page 38 Vancouver Design Center physical memory start Ne address A TA B Q SwivelView o 3 a N i gt window display 2 Z o start EE address NES lt O C D M lt 240 gt 160 i image seen by programmer image refreshed by SED1374 image in display buffer Figure 7 2 Relationship Between The Screen Image and the Image Refreshed by SED1374 SED1374 Programming Notes and Examples X26A G 002 02 Issue Date 99 04 27 Epson Research and Development Vancouver Design Center 7 4 Registers This section describes the registers used to set SwivelView mode operation Page 39 REG OCh Screen 1 Start Word Address LSB bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit O REG ODh Screen 1 Start Word Address
320. tem has a means of downloading software from the host to the target platform Typically this is done by a serial communication link Alternative methods include EPROM parallel port connection or network connection It is beyond the scope of this document to provide support for target host configurations SED1374 Supported Evaluation Platforms Installation 1374VIRT Display Utility Issue Date 98 10 20 1374VIRT has been tested with the following SED1374 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the SED1374 Programming Notes and Examples manual document number X26A G 002 xx PC platform copy the file 1374VIRT EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 1374VIRT to the system SED1374 X26A B 004 01 Page 4 Usage SED1374 X26A B 004 01 Epson Research and Development Vancouver Design Center PC platform at the prompt type 1374virt a w Embedded platform execute 1374virt and at the prompt type the command line argument Where no argument a W panning and s
321. ter Controller Clocks LCD Generic MPU MC68K gt SH 3 SH 4 Look Up Table Sequence Controller Bus Clock Memory Clock Pixel Clock Figure 4 1 System Block Diagram Showing Data Paths 4 1 Functional Block Descriptions 4 1 1 Host Interface The Host Interface provides the means for the CPU MPU to communicate with the display memory and internal registers 4 1 2 Memory Controller The Memory Controller arbitrates between CPU accesses and display refresh accesses It also generates the necessary signals to control the SRAM frame buffer 4 1 3 Sequence Controller The Sequence Controller controls data flow from the Memory Controller through the Look Up Table and to the LCD Interface It also generates memory addresses for display refresh accesses Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 16 Epson Research and Development Vancouver Design Center 4 1 4 Look Up Table The Look Up Table contains three 16x4 Look Up Tables or palettes one for each primary color In monochrome mode only one of these Look Up Tables is used 4 1 5 LCD Interface The LCD Interface performs frame rate modulation for passive LCD panels It also generates the correct data format and timing control signals for various LCD and TFT MD TED panels 4 1 6 Power Save Power Save contains the power save mode circuitry SED1374 Hardware Functional Specification X
322. terface e 10 SDU1374 75 TMPR3912 22U CPU Module Issue Date 98 12 23 X00A G 004 01 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK SDU1374 75 TMPR3912 22U CPU Module X00A G 004 01 Issue Date 98 12 23 EPSON Research and Development Page 7 Vancouver Design Center 1 Introduction This manual describes the interface between the SED1374 75 LCD Controller LCDC and the TMPR3912 22U microprocessor as implemented on the Toshiba 3912 22 and SED1374 75 CPU Module This module is used in conjunction with the Toshiba TX RISC Reference Platform For more information regarding the SED1374 or SED1375 refer to their respective Hardware Functional Specification document number X26A A 001 xx and X27A A 001 xx respectively For more information regarding the TMPR3912 22U refer to the TMPR3912 22U 32 Bit MIPS RISC Processor User s Manual See the Toshiba website under semiconductors at http toshiba com taec nonflash indexproducts html 1 1 General Description The Toshiba TX RISC Reference Kit consists of 6 boards which include a main board a CPU board a EPROM board a FMEM board a debug board and an analog board The main board acts as the motherboard for all the other add on boards In addition to these boards there is an LCD module that connects to the CPU board In order to support the add on LCD panel that connects to the LCD module the CPU board microprocessor must have
323. th two positions These two bits select which bank is used for display data In 2 bpp color gray mode the 16 position Green Look Up Table is arranged into four banks each with four positions These two bits select which bank is used for display data These bits have no effect in 4 bpp color gray modes In 8 bpp color mode the 16 position Green Look Up Table is arranged into two banks each with eight positions Green Bank Select bit 0 selects which bank is used for display data Blue Bank Select Bits 1 0 In 1 bit per pixel bpp color mode the lower 8 positions of the Blue Look Up Table is arranged into four banks each with two positions These two bits select which bank is used for display data In 2 bpp color mode the 16 position Blue Look Up Table is arranged into four banks each with four positions These two bits select which bank is used for display data These bits have no effect in 4 bpp color gray modes In 8 bpp color mode the 16 position Blue Look Up Table is arranged into four banks each with four positions These two bits select which bank is used for display data Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Page 67 REG 17h Look Up Table Data Register Address FFF7h Read Write Look Up Look Up Look Up Look Up n a n a n a n a Table Data Table Data Table Data Table Data Bit 3 Bit 2 Bit 1 Bit 0 bits 3 0 Lo
324. the SED 1374 LUT i e VGA levels 0 3 map to LUT level 0 VGA levels 4 7 map to LUT level 1 etc The following table shows LUT values that approximate the default 256 color VGA palette Table 4 8 Suggested LUT Values to Simulate VGA Default 256 Color Palette Index Red Green Blue 00 00 00 00 01 02 02 05 02 04 04 0A 03 06 06 OF 04 09 09 05 0B 0B 06 0D 0D 07 OF OF HE Normally unused entries Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 23 Vancouver Design Center Gray Shade Modes 1 Bpp Gray Shade Black and White In 1 bpp gray shade mode only the first two entries of the green LUT are used All other LUT entries are unused Table 4 9 Recommended LUT Values for I Bpp Gray Shade Address Red Green Blue SS Normally unused entries 2 Bpp Gray Shade In 2 bpp gray shade mode the first four green elements are used to provide values to the panel The remaining indices are unused Table 4 10 Suggested Values for 2 Bpp Gray Shade Index Red Green Blue Normally unused entries Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 24 SED1374 X26A G 002 02 4 Bpp Gray Shade The 4 bpp gray shade mode uses all 16 LUT elements Epson Research and Development Vancouver
325. the display type int selnitHal void Description Parameters This function initializes variables used by the HAL library Call this function once when the application starts Normally programmers will never need to call seInitHal On PC platforms seReg isterDevice automatically calls seInitHal Consecutive calls to seRegister Device will not call selnitHal again On non PC platforms the start up code supplied by Seiko will call seInitHal If support code for a new CPU platform is written the programmer must ensure that seInitHAL is called prior to calling other HAL functions None Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Vancouver Design Center Page 49 9 2 2 Miscellaneous HAL Support Functions in this group do not fit into any specific category of support They provide a miscellaneous range of support for working with the SED1374 int seGetld int DevID int pld Description Parameters Return Value Reads the SED 1374 revision code register to determine the chip product and revisions The interpreted value is returned in pID DevID registered device ID pld pointer to an integer which will receive the controller ID SED1374 values returned in pID are ID_SED1374 ID_SED1374F0A ID_ UNKNOWN Other HAL libraries will return their respective controller IDs upon detection of
326. the help screen Program Messages SED1374 X26A B 002 01 ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 1374 device A 1374 device was not found at the configured addresses Check the configuration address using the 1374CFG configuration program ERROR Did not find a 1374 device The HAL was unable to read the revision code register on the SED 1374 Ensure that the SED 1374 hardware is installed and that the hardware platform has been set up correctly ERROR Could not initialize device The HAL failed to initialize the registers 1374SHOW Demonstration Program Issue Date 98 10 20 EPSON SED1374 Embedded Memory Color LCD Controller 1374SPLT Display Utility Document No X26A B 003 01 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the
327. the prompt type 1374pwr s0 s1 h0 h1 Embedded platform execute 1374pwr and at the prompt type the command line argument Where s0 resets software power save mode s1 sets software power save mode hO resets disables hardware power save mode REG 03h bit 2 h1 sets enables hardware power save mode REG 03h bit 2 displays this usage message Program Messages SED1374 X26A B 007 01 ERROR Unknown command line argument An invalid command line argument was entered Enter a valid command line argument ERROR Too many devices registered There are too many display devices attached to the HAL The HAL currently can manage only one device ERROR Could not register 1374 device A 1374 device was not found at the configured addresses Check the configuration address using the 1374CFG configuration program ERROR Did not detect 1374 The HAL was unable to read the revision code register on the SED1374 Ensure that the SED1374 hardware is installed and that the hardware platform has been set up correctly 1374PWR Power Save Utility Issue Date 98 10 27 EPSON SED1374 Embedded Memory Color LCD Controller Windows CE Display Drivers Document Number X26A E 001 01 Copyright O 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON
328. the scope of this document to provide support for target host configurations SED1374 Supported Evaluation Platforms 1374PLAY Diagnostic Utility Issue Date 99 11 29 1374PLAY has been tested with the following SED1374 supported evaluation platforms e PC system with an Intel 80x86 processor e M68332BCC Business Card Computer board revision B with a Motorola MC68332 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the SED1374 Programming Notes and Examples manual document number X26A G 002 xx SED1374 X26A B 005 02 Page 4 Installation Usage SED1374 X26A B 005 02 Epson Research and Development Vancouver Design Center PC platform copy the file 1374PLAY EXE to a directory that is in the DOS path on your hard drive Embedded platform download the program 1374PLAY to the system PC platform at the prompt type 1374play Embedded platform execute 1374play and at the prompt type the command line argument Where displays program revision information The following commands are valid within the 1374PLAY program X index data XA L index datal data2 data3 LA F W addrl addr2 data R W addr count W W addr data Reads writes the registers Writes data
329. the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED1374 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www erd epson com SED1374 Interfacing to the NEC VR4102 Microprocessor X26A G 008 04 Issue Date 99 01 05 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents e NEC Vr4102 64 32 bit Microprocessor Preliminary User s Manual Epson Research and Development Inc SED 374 Embedded Memory Color LCD Controller Hardware Functional Specification Document Number X26A A 001 xx e Epson Research and Development Inc SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx e Epson Research and Development Inc SED1374 Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources NEC web page http www nec com e Epson Research and Development web page http www erd epson com Interfacing to the NEC VR4102 Microprocessor SED1374 Issue Date 99 01 05 X26A G 008 04 Page 18 7 Technical Support 7 1 Epson LCD Controllers SED1374 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Ep
330. tion 13 5 Turning Off BCLK Between Accesses on page 86 SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Page 33 Vancouver Design Center 7 1 6 Generic 2 Interface Timing TBCLK A 15 0 BHE VALID CS tl t2 WE RD gS y t4 Hi Z D 15 0 iat write 8 gt gt 16 t7 Hi Z VALID Hi Z D 15 0 read 18 19 t10 WAIT Hi Z Hi Z Figure 7 6 Generic 2 Timing Table 7 6 Generic 2 Timing Symbol Parameter Min Max Units fBCLK Bus Clock frequency 0 50 MHz Teck Bus Clock period 1 fecLk t1 A 15 0 BHE CS valid to WE RD low 0 ns t2 WE RD high to A 15 0 BHE CS invalid 0 ns 13 WE low to D 15 0 valid write cycle TBCLK t4 WE high to D 15 0 invalid write cycle 0 ns t5 RD low to D 15 0 driven read cycle 16 ns t6 D 15 0 valid to WAIT high read cycle 0 ns t7 RD high to D 15 0 high impedance read cycle 10 ns t8 WE RD low to WAIT driven low 14 ns t9 BCLK to WAIT high 16 ns t10 WE RDA high to WAIT high impedance 11 ns Note BCLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 86 Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 34 Epson Research and Development Vancouver Design Center 7 2 Clock Input
331. to 38V BDRDY 38 MOD MOD MOD MOD MOD MOD DRDY DRDY BLCDPWR 40 LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR SED1374 SDU1374B0C Rev 1 0 ISA Bus Evaluation Board User Manual X26A G 005 01 Issue Date 98 10 26 Epson Research and Development Page 11 Vancouver Design Center 4 CPU Bus Interface Connector Pinouts Table 4 1 CPU BUS Connector H1 Pinout Connector CPU BUS Cominents Pin No Pin Name 1 SDO Connected to DBO of the SED1374 2 SD1 Connected to DB1 of the SED1374 3 SD2 Connected to DB2 of the SED1374 4 SD3 Connected to DB3 of the SED1374 5 GND Ground 6 GND Ground 7 SD4 Connected to DB4 of the SED1374 8 SD5 Connected to DB5 of the SED1374 9 SD6 Connected to DB6 of the SED1374 10 SD7 Connected to DB7 of the SED1374 11 GND Ground 12 GND Ground 13 SD8 Connected to DB8 of the SED1374 14 SD9 Connected to DB9 of the SED1374 15 SD10 Connected to DB10 of the SED1374 16 SD11 Connected to DB11 of the SED1374 17 GND Ground 18 GND Ground 19 SD12 Connected to DB12 of the SED1374 20 SD13 Connected to DB13 of the SED1374 21 SD14 Connected to DB14 of the SED1374 22 SD15 Connected to DB15 of the SED1374 23 RESET Connected to the RESET signal of the SED1374 24 GND Ground 25 GND Ground 26 GND Ground 27 12V 12 volt supply 28 12V 12 volt supply 29 WE
332. to IO Vpp 2 Hardware Video Invert is enabled on FPDAT11 by REG 02h bit 1 Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 24 6 D C Characteristics Table 6 1 Absolute Maximum Ratings Epson Research and Development Vancouver Design Center Symbol Parameter Rating Units Core Vop Supply Voltage Vss 0 3 to 4 6 V IO Vpp Supply Voltage Vss 0 3 to 6 0 V Vin Input Voltage Vss 0 3 to lO Vpp 0 5 V Vout Output Voltage Vss 0 3 to lO Vpp 0 5 V TsTG Storage Temperature 65 to 150 C Tso Solder Temperature Time 260 for 10 sec max at lead C Table 6 2 Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units Core Vop Supply Voltage Vss 0 V 3 0 3 3 3 6 V IO Vpp Supply Voltage Vss 0V 3 0 3 3 5 0 5 5 V Vin Input Voltage Vss IO Vop V Topr Operating Temperature 40 25 85 C Table 6 3 Input Specifications Symbol Parameter Condition Min Typ Max Units vA Low Level Input Voltage lOVpp 3 3 0 8 V CMOS inputs 5 0 1 0 V Viu High as IOVop 3 3 2 0 V inputs 5 0 3 5 V Ver Positive going Threshold lIOVpp 3 3 1 1 2 4 V CMOS Schmitt inputs 5 0 2 0 4 0 V Vr Negative going Threshold IOVop 3 3 0 6 1 8 V CMOS Schmitt inputs 5 0 0 8 3 1 V Vop Max liz Input Leakage Current Vin Vpp 1 1 LA Vit Vss Cin Input Pin Capacitance 10 pF HRpp Pull Down Resistance V
333. to the register specified by the index when data is specified otherwise the register is read Reads all registers Reads writes Look Up Table LUT values Writes data to the LUT index when data is specified otherwise the LUT index is read Data must consist of 3 bytes 1 red 1 green 1 blue and range in value from 0x00 to OxOF Reads all LUT values Fills bytes or words from address 1 to address 2 with data Data can be multiple values e g F 0 20 1 2 3 4 fills address O to 0x20 with a repeating pattern of 1 2 3 4 Reads count of bytes or words from the address specified by addr If count is not specified then 16 bytes words are read Writes bytes or words of data to address specified by addr Data can be multiple values e g W 0 1 2 3 4 writes the byte values 1 2 3 4 starting at address 0 Initializes the chip with user specified configuration 1374PLAY Diagnostic Utility Issue Date 99 11 29 Epson Research and Development Page 5 Vancouver Design Center M bpp Returns information about the current mode If bpp is specified then set the requested color depth P 0 1 2 Sets software power save mode 0 2 Power save mode 0 is normal operation H lines Halts after specified lines of display This feature halts the display during long read operations to prevent data from scrolling off the display Set 0 to disable Q Quits this utility Displays Help informatio
334. tre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http Awww eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MCF5307 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor SED1374 X26A G 011 02 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 99 01 05 EPSON SED1374 Embedded Memory Color LCD Controller Interfacing to the Philips MIPS PR31500 PR31700 Processor Document Number X26A G 012 01 Copyright 1998 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your ownuse in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation t
335. ts 1 0 These bits select the Power Save Mode as shown in the following table Table 8 6 Software Power Save Mode Selection Bit 1 Bit 0 Mode 0 0 Software Power Save 0 1 reserved 1 0 reserved 1 1 Normal Operation Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Refer to Power Save Modes on page 84 for a complete description Page 59 REG 04h Horizontal Panel Size Register Address FFE4h Read Write Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal n a Panel Size Panel Size Panel Size Panel Size Panel Size Panel Size Panel Size Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O bits 6 0 Horizontal Panel Size Bits 6 0 This register determines the horizontal resolution of the panel This register must be pro grammed with a value calculated as follows HorizontalPanelSizeRegister HorizontalPanelResolution pixels This register must not be set to a value less than 03h y REG 05h Vertical Panel Size Register LSB Address FFE5h Read Write Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical Panel Size Panel Size Panel Size Panel Size Panel Size Panel Size Panel Size Panel Size Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 06h Vertical Panel Size Register MSB Address FFE6h
336. ts tl Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse falling edge 1 Ts to Shift Pulse falling edge to Line Pulse rising edge note 5 t7 Shift Pulse falling edge to Line Pulse falling edge note 6 t8 Line Pulse falling edge to Shift Pulse falling edge t14 1 Ts t9 Shift Pulse period 2 Ts t10 Shift Pulse pulse width low 1 Ts t11 Shift Pulse pulse width high 1 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 1 Ts t13 FPDAT 7 0 hold to Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 39 Ts 1 Ts pixel clock period 2 tmn 18min 9Ts 3 Bmin REG O4h bits 6 0 1 x 8 REG 08h bits 4 0 4 x 8 x 2 Ts 5 t6min REG O8h bits 4 0 x 2 x 8 17 Ts 6 tmin REG O8h bits 4 0 x 2 x 8 26 Ts SED1374 Hardware Functional Specification X26A A 001 02 Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Page 51 7 3 10 9 12 Bit TFT MD TFD Panel Timing VNDP gt VDP VNDP FPFRAME P4 gt FPLINE Jo l i FPDAT 11 0 LINE480 LINE X X LINE480 i m FPLINE gt S HNDP HDP HNDP gt gt FUE L Meal NAM AS ple DRDY o oo l aes FPDAT 9 FPDAT 2 0 A RN a FPDAT 10
337. uction i eri a A ee a a i oS ee Od Base 9 LM S es ic ae E A A A AA A RR E as O 1 2 Overview Description e Dd 2 POTES oi ii A EE SB ia AA AAA A 10 2 1 Integrated Frame Buffer 2 eee LO 2 2 CRU Intertac s sario a do A do a A A ar a Ete at Se e AO 2 3 Display Support a s e e ace e a a 10 24 Display Modes s 4 0 43 te By ae da a da ee a 25 Clock Source ir ste fork BR a ee aa ee ee da Bre ar at eo ML 2 6 Miscellaneous 2 ee ee 11 Da Packages Sh oe Ae od ele Aaa ee ete PE ob a Oe a Me o a oT Typical System Implementation Diagrams 0o ooo uae 12 4 Functional Block Diagram 15 4 1 Functional Block Descriptions 2 eee eee 15 4 11 Host Interface sos cta doe tue ee ees ea ete Bs fae He eae 15 4 1 2 Memory Controller s i 6 2 seta a we haben we Ee LE Se 15 4 1 3 Sequence Controller ee 15 4 1 4 i Look Up Table s arne a aiy ie e OS eee de eee ee ga el a Mia 16 AES LCD Interface aaa hoiteli it Gos ee gh aaa ew ae ara AWS get 16 41 6 Power Save ii ea Pk te Be EE EP A ee A Bee OR Es 16 S PINS asa A AAA as a a a ee rs ea 17 5 1 Pinout Diagram iy etar eer ge ee ey gee ee a a Be ee TT 5 2 Pin Description s s e s 2 ee 18 SLk Host Merrie 00000 a nies ee BA ee Beets GO a A a A 18 9 2 2 LED AMETACe rer Aine Ware tet hae eae See Dae Se A a a 20 5 23 Clock Input hi ele bE a A ee oe a
338. uctions below 1 Install Microsoft Windows NT v4 0 2 Install Microsoft Visual C C v5 0 3 Install the Microsoft Windows CE Embedded Toolkit ETK by running SETUP EXE from the ETK compact disc 1 4 Create a new project by following the procedure documented in Creating a New Project Directory from the Windows CE ETK Alternately use the current DEMO project included with the ETK Follow the steps below to create a X86 DEMO shortcut on the Windows NT v4 0 desktop which uses the current DEMO7 project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu window will come up c Click on the icon Programs d Click on the icon Windows CE Embedded Development Kit e Drag the icon X86 DEMO1 onto the desktop using the right mouse button f Click on Copy Here g Rename the icon X86 DEMO1 on the desktop to X86 DEMO by right click ing on the icon and choosing rename Windows6 CE Display Drivers SED1374 Issue Date 98 11 11 X26A E 001 01 Page 4 SED1374 X26A E 001 01 Epson Research and Development Vancouver Design Center h Right click on the icon X86 DEMO7 and click on Properties to bring up the X86 DEMO7 Properties window i Replace the string DEMO1 under the entry Target with DEMO7 j Click on OK to finish Create a sub directory named 4B
339. ue Date 99 01 05 Epson Research and Development Page 9 Vancouver Design Center 2 2 1 Normal Non Burst Bus Transactions ss eri e re hel TS TA A 0 31 X RDWR XX AS TSIZ 0 1 AT O 3 x D 0 31 XXMAXMAXMAXKAMAXMAXMAKMAX XXX Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts A data transfer is initiated by the bus master by placing the memory address on address lines AO through A31 and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e TSIZ 0 1 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e RD WR set high for read cycles and low for write cycles e AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Figure 2 1 Power PC Memory Read Cycle illustrates a typical memory read cycle on the Power PC system bus Figure 2 1 Power PC Memory Read Cycle Interfacing to the Motorola MPC821 Microprocessor SED1374 Issue Date 99 01 05 X26A G 010 02 P
340. ue Date 99 04 29 X26A A 001 02 Page 82 Epson Research and Development Vancouver Design Center 12 2 1 How to Set Up Alternate SwivelView Mode SED1374 X26A A 001 02 The following describes the register settings needed to set up Alternate Swivel View Mode for a 160x240x8 bpp image Select Alternate Swivel View Mode REG 1Bh bit 7 1 and bit 6 1 The display refresh circuitry starts at pixel B therefore the Screen 1 Start Address register must be programmed with the address of pixel B or REG 0Dh REG OCh AddressOfPixelB AddressOfPixelA ByteOffset 160pixels x 2 1 AddressOfPixelA Sbpb AddressOfPixelA 9Fh Where bpp is bits per pixel and bpb is bits per byte The Line Byte Count Register for Swivel View Mode must be set to the image width in bytes i e 160 160 L 160 AOK REG ICh pb bpp T Where bpb is bits per byte and bpp is bits per pixel Panning is achieved by changing the Screen 1 Start Address register e Increment the register by 1 to pan horizontally by one byte e g one pixel in 8 bpp mode e Increment the register by the value in the Line Byte Count register to pan vertically by one line e g add AOh to pan by one line in the example above Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Vancouver Design Center Page 83 12 3 Comparison Between Default and Alternate SwivelView Modes Table 12 1 Default and Alte
341. unt bit 5 Count bit 4 Count bit 3 Count bit 2 Count bit 1 Count bit 0 bits 7 0 Line Byte Count Bits 7 0 This register is the byte count from the beginning of one line to the beginning of the next consecutive line commonly called stride by programmers This register may be used to create a virtual image in SwivelView mode REG 1Eh and REG 1Fh REG 1Eh and REG 1Fh are reserved for factory SED1374 testing and should not be written Any value written to these registers may result in damage to the SED1374 and or any panel connected to the SED1374 Hardware Functional Specification Issue Date 99 04 29 SED1374 X26A A 001 02 Page 70 Epson Research and Development Vancouver Design Center 9 Frame Rate Calculation SED1374 X26A A 001 02 The following formulae are used to calculate the display frame rate TFT MD TFD and Passive Single Panel modes fpcLK FrameRate 2 HDP HNDP x VDP VNDP Where fperk PCIk frequency Hz HDP Horizontal Display Period REG 04h bits 6 0 1 x 8 Pixels HNDP Horizontal Non Display Period REG 08h bits 4 0 4 x 8 Pixels VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines Passive Dual Panel mode f PCLK FrameRate 2 x HDP HNDP x oe VNDP Where fpc g PCIk frequency Hz HDP Horizontal Display Period REG 04h bits 6 0 1 x 8 Pixels HNDP Hori
342. ur pixels the start address needs to be advanced 1 Calculate the amount to change start address by Bytes Pixels x BitsPerPixel 8 4 x 4 8 2 bytes 2 Increment the start address registers by the just calculated value In this case the value writen to the start address register will be 81h 7Fh 2 81h To scroll by 4 lines we have to change the start address by the offset of four lines of display 1 Calculate the amount to change start address by BytesPerLine LineByteCount 128 Bytes Lines x BytesPerLine 4 x 128 512 200h 2 Increment the start address registers by the just calculated value In this case 281h 81h 200h will be written to the Screen 1 Start Word Address reg ister pair Set Screenl Display Start Word Address LSB REG OCh to 81h and Screen Display Start Word Address MSB REG ODh to 02h Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 46 Epson Research and Development Vancouver Design Center 8 Identifying the SED1374 As there are several similar products in the 135X and 137X LCD controller families which can for the most part share the same code base It may be important for a program to identify between products at run time Identification of the SED1374 can be performed any time after the system has been powered up by reading REG 00h the Revision Code register The six most significant bits form the product identification code and the two least si
343. urce The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The SED 1374 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or www erd epson com Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 98 11 09 EPSON Research and Development Vancouver Design Center 5 Technical Support 5 1 EPSON LCD Controllers SED1374 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 5 2 Toshiba MIPS TX3912 Processor http www toshiba com taec nonflash indexproducts html 5 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com Interfacing to the Toshiba MIPS TX3912 Processor Issue Date 98 11 09 Page 15 Taiwan R O C Epson Taiwan Tech
344. ureation parameters chosen were EK 320x240 Single Color 8 bit STN format 2 aoe 4 bpp 70 Hz Frame Rate 25 MHz CLKi KK High Performance enabled x k E KOR KR KR RK KK I KR AA 1374 HAL HDR do not remove HAL_STRUCT Information generated by 1374CFG EXE EJ Copyright c 1998 Seiko Epson Corp All rights reserved Pe Include this file ONCE in your primary source file E KOK KR KKK KK AA HAL STRUCT HalInfo 1374 HAL EXE ID string El 0x1234 Detect Endian sizeof HAL_STRUCT Size 0x00 0x23 OxBO 0x03 0x27 OxEF 0x00 0x00 0x1E 0x00 0x3B 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 OxFF 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 25000 C1kI kHz 0xD0000 Display Address 70 Panel Frame Rate Hz y Kf k k ER HAL_REGS H kK Created 1998 Epson Research Development KK Vancouver Design Center Copyright c Seiko Epson Corp 1998 All rights reserved kk ifndef HAL REGS_H define HAL REGS _H Programming Notes and Examples SED1374 Issue Date 99 04 27 X26A G 002 02 Page 78 Epson Research and Development Vancouver Design Center
345. uver Design Center e Portrait Mode selecting Portrait Mode causes register settings and timings to be saved for portrait mode operation The HAL is capable of performing rotations on the fly Most programs written for the HAL will ignore this setting and set Portrait or Landscape display modes as desired This setting is useful when the configuration is saved into a C header file to be used by non HAL programs System The options in the System section describe the items which are required for frame rate calculations and where in CPU address space the SED 1374 will be located System Memory Location Frame Rate fps Input Clock kHz Figure 4 System Options e Memory Location this describes where in CPU address space the SED1374 will be located This setting is required by the HAL to locate the SED1374 If the settings from 1374CFG will be saved to a C header file for use in a non HAL program this value does not have to be filled in e Frame Rate indicate the desired frame rate here 1374CFG will attempt to write register settings which result in the requested frame rate If the frame rate cannot be reached then the following dialog inform the user of the problem 1374CFG AN ERROR Unable to set the desired frame rate wrong clock value Figure 5 ERROR Frame Rate 1374CFG EXE Configuration Program SED1374 Issue Date 98 10 27 X26A B 001 01 Page 12 Epson Research and Development Vancouver Design Center
346. velopment Page 15 Vancouver Design Center 4 3 NEC VR4102 Configuration The NEC Vr4102 provides the internal address decoding necessary to map to an external LCD controller Physical address 0A000000h to OAFFFFFFh 16M bytes is reserved for an external LCD controller The SED1374 supports up to 40K bytes of display buffer memory and 32 bytes for internal registers Therefore the SED1374 will be shadowed over the entire 16M byte memory range at 64K byte segments The starting address of the display buffer is 0A000000h and register 0 of the SED1374 REG 00h resides at OAOOFFEOh The NEC Vr4102 has a 16 bit internal register named BCUCNTREG2 located at address 0B000002h It must be set to the value of 0001h to indicate that LCD controller accesses use a non inverting data bus The 16 bit internal register named BCUCNTREGI located at address 0B000000h must have bit D 13 SA LCD bit set to 0 to reserve the 16M bytes space 0A000000h to OAFFFFFFh for LCD use and not as ISA bus memory space Interfacing to the NEC VR4102 Microprocessor SED1374 Issue Date 99 01 05 X26A G 008 04 Page 16 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the SED1374 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1374CFG or by directly modifying
347. vers Issue Date 98 11 11 Epson Research and Development Page 5 Vancouver Design Center 6 Edit the file DISPDRVR C located in X wince platform odo drivers display 4BPP1374 to set the desired screen resolution color depth bpp and panel type The sample code defaults to a 320x240 color single passive 4 bit LCD panel To support one of the other listed panels change the define statement 7 Generate the proper building environment by double clicking on the sample project icon i e X86 DEMO7 8 Type BLDDEMO lt ENTER gt at the DOS prompt of the X86 DEMO7 window to gen erate a Windows CE image file NK BIN 1 3 Example Installation Installation for CEPC Environment Windows CE v2 0 can be loaded on a PC using a floppy drive or a hard drive The two methods are described below To load CEPC from a floppy drive 1 Create a DOS bootable floppy disk 2 Edit CONFIG SYS on the floppy disk to contain the following line only device a himem sys 3 Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c wince release nk bin 4 Copy LOADCEPC EXE from c wince public common oak bin to the bootable floppy disk 5 Confirm that NK BIN is located in c wince release 6 Reboot the system from the bootable floppy disk To load CEPC from a hard drive 1 Copy LOADCEPC EXE to the root directory of the hard drive 2 Edit CONFIG SYS on the hard drive to contain th
348. wer supply timing requirements were larger than the timings built into the SED1374 power disable sequence 1 Ze Programming Notes and Examples Issue Date 99 04 27 Set REG 03h bit 3 LCDPWR Override to 1 disables LCD Power Count x Vertical Non Display Periods x corresponds to the power supply discharge time converted to the equivalent verti cal non display periods Disable the LCD logic by setting the software power save in REG 03h or setting hardware power save via GPIOO SED1374 X26A G 002 02 Page 36 Epson Research and Development Vancouver Design Center 7 SwivelView 7 1 Introduction To SwivelView Many of todays applications use the LCD panel in a portrait orientation In this case it becomes necessary to rotate the displayed image This rotation can be done by software at the expense of performance or as with the SED 1374 it can be done by hardware with no performance penalty There are two hardware rotated modes Default Swivel View Mode and Alternate SwivelView Mode 7 2 Default Swivel View Mode SED1374 X26A G 002 02 Default Swivel View Mode requires the portrait image width be a power of two e g a 240 line panel requires a minimum virtual image width of 256 This mode should be used whenever the required virtual image can be contained within the integrated display buffer i e virtual image size lt 40k bytes as it consumes less power than the Alternate SwivelView mode
349. word aligned memory i e A30 and A31 are always 0 0 e Do not increment address bits A28 and A29 between successive transfers the addressed device must increment these address bits internally SED1374 Interfacing to the Motorola MPC821 Microprocessor X26A G 010 02 Issue Date 99 01 05 Epson Research and Development Page 11 Vancouver Design Center If a peripheral is not capable of supporting burst cycles it can assert Burst Inhibit BI simultaneously with TA and the processor will revert to normal bus cycles for the remaining data transfers Burst cycles are mainly intended to facilitate cache line fills from program or data memory They are normally not used for transfers to from IO peripheral devices such as the SED1354 therefore the interfaces described in this document do not attempt to support burst cycles However the example interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the SED1354 address space 2 3 Memory Controller Module 2 3 1 General Purpose Chip Select Module GPCM The General Purpose Chip Select Module GPCM is used to control memory and peripheral devices which do not require special timing or address multiplexing In addition to the chip select output it can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR sig
350. write cycles e A set of transfer type signals TT 1 0 which provide more detail on the type of transfer being attempted TIP Transfer In Progress which is asserted whenever a bus cycle is active When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle completing the bus transaction Once TA has been asserted the MCF5307 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Figure 2 1 illustrates a typical memory read cycle on the MCF5307 system bus and Figure 2 2 illustrates a memory write cycle Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 99 01 05 Epson Research and Development Vancouver Design Center Page 9 BCLKO TS TA TIP A st 0 XX X RW XX XXXXKX SIZ 1 0 TT 1 0 X A Dr31 0 XXXAXKAXMAXKAMKAXMAXMAKMAX MXN Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 MCF5307 Memory Read Cycle sexo ILL Udo TS TA TIP AI31 0 X l x RW XX _LXXXXX SIZ 1 0 TT 1 0 XX pi3t 0 XXXXXXX Valid XXX Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 MCF5307 Memory
351. xels affected by a change of one to these registers Table 5 1 Number of Pixels Panned Using Start Address Color Depth bpp SwivelView Mode Number of Pixels Panned Landscape Mode Pixels per Word Number of Pixels Panned 1 16 16 8 2 8 8 4 4 4 4 2 8 2 2 1 5 2 2 Examples SED1374 X26A G 002 02 For the following examples assume the display system has been set up to view a 320x240 4 bpp image in a 256x64 viewport Refer to Section 2 Initialization on page 8 and Section 5 1 Virtual Display on page 25 for assistance with these settings The examples are shown in a C like syntax Example 3 Panning Right and Left To pan to the right increase the start address value by one To pan to the left decrease the start address value Keep in mind that with the exception of 8 bit per pixel SwivelView mode the display will jump by more than one pixel as a result of changing the start address registers Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 29 Vancouver Design Center Panning to the right StartWord GetStartAddress StartWord SetStartAddress StartWord Panning to the left StartWord GetStartAddress StartWord if StartWord lt 0 StartWord 0 SetStartAddress StartWord Example 4 Scrolling Up and Down To scroll down increase the value in the Screen 1 Display Start Address Register by the nu
352. y Blank Hw Video Invert Enable Software Video Invert Look Up Table Bypass n a n a n a LCDPWR Override Hardware PS Enable REG 04h HORIZONTAL PANEL SIZE REGISTER IO address FFE4h RW Bit 1 Sw Power Save Bit 0 n a Bit 6 Bit 5 Horizontal Bit 4 REG 05h VERTICAL PANEL SIZE REGISTER LSB IO Panel Size 8 REG 1 Bit 3 Bit 2 address FFE5h RW Bit 7 Bit 6 Bit 5 Bit 4 Vertical Panel Size REG O5h REG O6h 1 Bit 3 Bit 2 REG 15h Look Up TABLE ADDRESS REGISTER IO address FFF5h RW n a n a RGB Bit 1 Index Bit 0 Bit 3 Bit 2 Look Up Table Address Bit 1 Bit 0 REG 16h Look Up TABLE BANK SELECT REGISTER IO address FFF6h RW n a n a Red Bank Select Bit 1 Bit 0 Bit 1 Green Bank Select Bit 0 Blue Bank Select Bit 1 Bit O REG 17h LOOK UP TABLE DATA REGISTER IO addre REG 18h GPIO CONFIGURATION CONTROL REGISTER ss FFF7h RW Look Up Bit 2 lO address FFF8h RW Table Data Bit 1 n a n a n a GPIO4 Pin 10 Config GPIO3 Pin 10 Config GPIO2 Pin 1O Config GPIO1 Pin IO Config GPIOO Pin 10 Config REG 06h VERTICAL PANEL SIZE REGISTER MSB IO address FFE6h RW n a n a n a n a n a n a Bit 9 Vertical Panel Size Bit8 REG 07h FPLINE START n a POSITION IO address FFE7h RW Bit 4 FPLine Start Bit 3 Bit 2
353. y has bee setup In the case where split screen operation is being used the WhichScreen argument specifies which screen to move The x and y parameters specify in pixels the starting location in the virtual image for the top left corner of the applicable display Parameter DevID registered device ID Screen must be set to 1 or 2 or use the constants SCREEN1 or SCREEN2 to identify which screen to base calculations on x new starting X position in pixels y new starting Y position in pixels Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG there are several reasons for this return value 1 WhichScreen is not SCREEN1 or SCREEN2 2 the y argument is greater than the last available line less the screen height Note seVirtInit must be been called before calling se VirtMove Programming Notes and Examples Issue Date 99 04 27 Epson Research and Development Page 55 Vancouver Design Center 9 2 4 Register Memory Access The Register Memory Access functions provide access to the SED1374 registers and display buffer through the HAL int seGetReg int DeviID int Index BYTE pValue Description Reads the value in the register specified by index Parameters DevID registered device ID Index register index to read pValue pointer to a BYTE to receive the register value Return Value ERR_OK operation completed with no problems int seSetReg int DevID int Index BYTE Value Description
354. ytes dh const char pSta nBitsPerPixel pBitsPerPixel y int height long LastByte BOOL OnOff int seSetHWRotate int nDevID int nMode Programming Notes and Examples Issue Date 99 04 27 SED1374 X26A G 002 02 Page 76 int int nDevID WORD ScrnlAddr int nDevID seSplitInit int seSplitScreen int WhichScreen WORD Scrn2Addr int VisibleScanlines Epson Research and Development Vancouver Design Center ie seVirtInit seVirtMove int int nDevID int xVirt long yVirt int nWhichScreen int int nDevID int x int y i Register Memory Access BYTE pValue int index BYTE value DWORD offset BYTE DWORD offset WOR DWORD offset DWORD addr DWORD addr DWORD addr int seGetReg seSetReg seReadDisplayByte seReadDisplayWord int nDevID int index i int int nDevID int int nDevID int int nDevID int seReadDisplayDword int nDevID int BYTE WOR seWriteDisplayBytes int nDevID val int seWriteDisplayWords int nDevID D val int seWriteDisplayDwords int nDevID pByte D pWord DWORD pDword DWORD val 2 i DWORD count DWORD count DWORD count Power Sav y int PowerSaveMode BOOL val int nDevID int seHWSuspend int nDevID int seSetPowerSaveMode y int seSetPixel int seGetPixel int
355. zontal Non Display Period REG 08h bits 4 0 4 x 8 Pixels VDP Vertical Display Period REG 06h bits 1 0 REG OSh bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines Hardware Functional Specification Issue Date 99 04 29 Epson Research and Development Page 71 Vancouver Design Center 10 Display Data Formats 1 bpp bit 7 bit O PoPyP2P3P4PsPgP7 Panel Display Host Address Display Memory 2 bpp bit 7 bit 0 PoP P2 P3P4PsP6P7 Panel Display Host Address Display Memory PoP4 P2 P3P4P5PeP7 Ph E An Bn Ch Dn Panel Display Host Address Display Memory 8 bpp 3 3 2 RGB PoP4 P2 P3P4P5PeP7 Go G4 Pa Rio Gn 20 Bp 19 Go Panel Display Host Address Display Memory Figure 10 1 1 2 4 8 Bit Per Pixel Display Data Memory Organization Hardware Functional Specification SED1374 Issue Date 99 04 29 X26A A 001 02 Page 72 11 Look Up Table Architecture 11 1 Gray Shade Display Modes 2 Level Gray Shade Mode Epson Research and Development Vancouver Design Center Table 11 1 Look Up Table Configurations Display Mode 4 bit wide Look Up Table RED GREEN BLUE 2 level gray 4 banks of 2 4 level gray 4 banks of 4 16 level gray 1 bank of 16 2 color 4 bank of 2 4 bank of 2 4 bank of 2 4 color 4 banks of 4 4 banks of 4 4 b

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