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1. a b Figure 3 4 Ground pickup to metal 1 a and VDD pickup to metal 1 b Figure 3 5 Active area and poly contacts to metal 1 cells 24 For large interconnection between metal layers one specific cell can be defined on setup for a semiautomatic matrix creation Figure 3 6 Cell ib con M1 M2 auto ib con M2 M3 auto ib con M3 M4 auto a b Figure 3 6 Setup definition of cells a for semiautomatic matrix creation b 3 3 Discrete devices and test structures The manufacturing of individual devices although they could be simulated is important for replication of the designed core circuit in a way that any node could be accessed measured and analysed as well as for new connections and circuit configurations that could be tested quickly without simulations or without manufacturing a new chip Furthermore photoelectric effects on diodes and transistors are not completely simulated on standard programs Several test structures of individual devices and complete circuits were implemented on the test chip to characterize each one and to reconstruct the unit cell with discrete components if necessary The test structures on top of the chip Figure 3 7 include e Two isolated internal pads for leakage and capacitance characterization e One poly capacitor for capacitance characterization e Seven types of photodiodes e Symmetric and asymmetric NMOS transistors 25 e Symmetric and as
2. es 1 00ms 1 00MS s Aux 20 10 10k points 4 00mV 13 Jan 2013 17 38 00 ibROIC 15 Resolution 1 00jus Figure 6 7 Biasing integration and hold signals on unit cell The separated unit cell also demonstrates the wide voltage range in its BIAS input from 0 04 V to 10 4 V 7 5 V related to 5 04 V on detector common node in the same Figure 6 8 that shows the correspondent output range from 5 0 V to 12 8 V related to VSS H i a i i i f f Y d Ch2 High H i E 13 2 V ee eere Hii Ch2 Low 5 04V TekRun fp trig Ch2 Low 5 00 V COMTE js XN Ch3 High y i KE 10 4 V i T f i 4 Ch3 High f A 14 8 Y E E D E 40 0mV i dele eeelee A AAN Pee TN RS 2 00 V 2 Oct 2012 2 00 V M2 00ms A Ch3 f 1 76 V hcic ch3 2 00V Ch4 2 00V 2 Oct 2012 u29 22 i3 29 60 13 22 53 2 800 15 00 44 ibBROIC OA buffer Vout Vin TDS 3054B 4 00 32 PM 10 2 2012 Figure 6 8 Input a bottom voltage range and output swing a top of unit cell Saturated output waveform b similar to simulation Increasing the input values one can observe that the output waveform turns similar to that one simulated 1n Section 3 7 95 6 6 ITP ROIC Two biases with correlated different integration rate are shown in F
3. fi 3 Figure 3 13 Spice code for simulation of VSG x ID curve 30 Tanner T Spice 15 16 CAUsersiG lau co Do cuments 0 New Mex ico 0 UN M 0 PhD 8 Lab 00 Projects 0 0 Glauco ibR OIC ib ROIC8 second chance Simulations ib_ HVMOS p Column Bias CHAR CURVE spc IDEE 100 55 95091 218 4187 a B sou cel source yos Amps Vdd ox ps Vdts Figure 3 14 Simulated source gate voltage versus drain current for the column bias transistors 3 6 Operational amplifier The two stage operational amplifier opamp was designed as part of the unit cell and its transistors were distributed as necessary to facilitate the interconnections After the completition of the unit cell design and layout verification a copy of the unit cell was made to delete the components not related with the opamp and a test structure design cell was defined Figure 3 15 Inside this design cell the bias mirror transistor was inserted and a ground guard ring was implemented The non inverting input the invertin input the output and the bias mirror of the opamp were connected directly to external pads In this way an opamp with the same connections dimensions and positioning of components of that one in the unit cell would be available for testing and characterization 3l Figure 3 15 Unit cell two stage operational amplifier layout 3 7 Unit cell The separated unit cell has 13 connections on ESD pads one independent VDDH six dig
4. UGKo 2T GCGOB UN eS EE REEL 7 1T wm 3i fh m ii t b oe ery ie ees t 1 unm inan nI T Th On A O O Figure 3 26 4 x 4 matrix with dummy designed cells interconnecting the active cells 39 Employing the hierarchical structure of design cells these dummy blocks were created from a copy of the final design cell and were edited to contain only the necessary direct connections for passing through the signals to the next cell as a bridge block Moreover any added design problem on these dummy blocks could be detected more easily with a smaller number of nodes These design cells are listed in Figure 3 27 together with the simulation result of the 4 x 4 pixels dummy chip E ib dummy_0 Column Select 58 E ib dummy matrix 98x98 row UNM E ib dummy 0 Row Select 96 E ib dummy 0 struct FPA to simul ib dummy Column switches with NOR2 E ib dummy jumper UnitCell ib dummy level Shifter E ib dummy PhotoDiode L open sw E ib dummy Pixel PD open E ib dummy test stnct UNM row a b Figure 3 27 Dummy designed cells a and 4 x 4 matrix Spice simulation b 3 14 Future FPA It is worth nothing that because of inadequate planning the future application of this design on a 100 fill factor DWELL FPA could present violations of design rules checking DRC and or open short circuits Consequently the DRC was checked
5. 000 sel ramp stepTABLE mux ramp1 HLstepTABLE mux ramp1_CLK ramp1_UD ramp1_stepTABLE_out ramp1_stepTABLE_STR6 ramp1_RST ramp1_stepTABLE nat See eee eee eee OOO AAA AAA ACNUR ra IAB ramp1_HLstepTABLE_nat ramp1_CLK I Figure 5 16 Block diagram of ramp generator 5948 rampl LO 5949 dounter rampi LO entity work counter STR by2 beh 5950 port map THERE gt HERE 5951 in out 5952 Counter CLK gt COUNTER CLK T 9953 update gt update param T 5954 reset gt SYSRST A 9999 load gt low_level A 5956 counter en gt sel 74 o lt selection on screen 5957 up_down gt ROT1 left 6 5958 STEP gt rampi HLstepTABLE nat rampl stepTABLE out O A 2 z 5959 min val gt min rampl LO E CONSTANT natural s118 5960 initial value gt INI_rampl LO i signal from setup CONSTANT natural s119 5961 max val gt max rampl LO CONSTANT natural s120 5962 5963 Y Mo 5964 5965 5966 l 5967 v v 5968 SSS 1 oo i iigym c 5969 string 3dig gt rampl LO STR3 signal string divided by 2 gt 298 2 149 gt 14 9V 5970 stored value gt rampl LO signal unsigned 16 downto 0 5971 M aoe rampl LOx10 lt rampl LO 10 5973 rampl LO nat lt
6. S Krishna M Hayat J S Tyo U Sakoglu and Raghavan Detector with tunable spectral response U S Patent No 7 217 951 2007 Brian Simolon et al High performance two color one megapixel CMOS ROIC for QWIP detectors Infrared Physics amp Technology 52 pp 391 394 2009 M Mulato et al T wo color amorphous silicon image sensor Journal of Applied Physics 90 p 1589 2001 Eric Beuville Mark Belding Adrienne Costello Randy Hansen and Susan Petronio A High Performance Low noise 128 Channel Readout Integrated Circuit for Instrumentation and X ray Applications IEEE Nuclear Science Symp Conf Rec Vol 1 pp 142 146 2004 http www tannereda com Phillip El Allen Douglas R Holberg CMOS Analog Circuit Design second edition Oxford University Press New York 2002 ISBN 0 19 511644 5 p 134 143 112 18 19 20 27 28 29 30 31 32 33 MicroBlaze Development Kit Spartan 3E 1600E Edition User Guide UG257 V1 1 Dec 5 2007 available at http www xilinx com support documentation boards and kits ug257 pdf http www digilentinc com Products Detail cfm NavPath 2 400 793 amp Prod S3E1600 http www digilentinc com Products Detail cfm NavPath 2 648 613 amp Prod FX2MIB National Instruments LM117 LM317A LM317 3 Terminal Adjustable Regulator datasheet March 1 2010 http www digilentinc com Products Catalog cfm NavPath 2 401
7. 4 12 2 Probe station The Signatone S 251 6 probe station with PSM 1000 microscope 37 shown in Figure 4 21 proved to be a useful tool for quick access measurement and I V curve characterization of individual devices Three new probes were specified and purchased for the characterization of the symmetric transistors Unfortunately care must be taken with the probes because even with pressure control and limitation some damage can occur to the pads and therefore the number of measurements on each point might be 58 limited Figure 4 21 Probe station with integrated video camera to monitor and to computer This was one more justification for the using the wire bonding procedure on the chip carrier and socket PCB even though it was more time consuming and costly and required training and experience 4 12 3 Video camera and software To promote a fast easy way of image documentation of devices and structures analyzed on the probe station a video camera and image acquisition software were priced purchased and installed 38 The control interface video and file manipulation windows are shown in Figure 4 22 This newly implemented resource on the Midinfrared Image Characterization and Application Laboratory MICA lab also allowed the image from the microscope to be viewed on a monitor thus offering a way to view simultaneously the region of interest to follow the procedures and to learn about the measurement and
8. 6606 6607 l 6608 V V COL sel outMUX 6609 AA A ems in RE 6610 string 3dig gt COL sel outMUX STR3 p signal 6611 stored value gt COL sel outMUX signal 6612 6613 10 20 30 40 50 60 70 a b Figure 5 3 Parameter counter block diagram a and instantiation b selection number 0 BENMNENENHI Figure 5 4 Parameter counter selection multiplexer One multiplex version referred to as table mux orange trapezoid shape 1s used to select values that are not direct multiples of one another where an up down counter cannot be used 1 e on clock division Figure 5 6 and step definition of the ramp counter Figure 69 5 16 Others applications of the multiplexer block are the LCD screen labels and variables selection the setup parameter selection purple trapezoid the digital or output signal selection blue trapezoid internal signals test switching and context menu switching explained with details on following sections The great advantage of this structure is that 1t increases its flexibility and that digital signals can be selected along with vectored variables and screen label strings 5 4 Clocks generation The pixel clock Figure 5 5 1s an important signal and its value together with other factors defines the frames per second FPS rate The pixel clock is generated by the division of
9. Figure 4 19 Pinout of ITP ROIC FPA and test structures version 1 4 11 LCD The two line 16 character liquid crystal display LCD module 1s driven by a Toshiba HD44780 controller chip and has well known hardware connections and control commands 33 as illustrated in Figure 4 20 a Figure 4 20 LCD initial screen a and pinout b 57 4 12 Infra structure hardware Several instruments and equipments were required for the measurement testing and characterization of devices circuits and system In addition to the basic bench instruments such as power supplies a soldering station a multimeter a function generator and an oscilloscope specialized instruments and software were used in ITP ROIC operation testing and characterization such as a probe station a wire bonding machine a source measure unit a laser light an energy meter 34 and frame grabber These main resources are discussed below 4 12 1 Oscilloscope Initially a four channel oscilloscope was used 35 but as the number of digital signals increased substantially a 16 channel digital input four channel analog input mixed signal oscilloscope was specified for purchase 36 The main signals for synchronization separated unit cell and FPA control were kept on screen while four digital channels were used with dedicated pins from the FPGA board to visualize any desired internal signal waveform by means of its own FPGA software selection
10. Not all initial desired features could be implemented due the limited time and to the actual limit of program memory on the adopted FPGA board Needed now e Optimization of the software reducing the number of counter muxes to the 110 minimum possible liberating space on hardware of the FPGA for other block s implementation and keeping its operational specifications Design tests and implementation of the following software blocks FLASH memory to store variables and setup values reducing the number of counters memory ADC for image acquisition and DDR SDRAM for acquired processed and stored images As described in Sections 4 11 and 5 5 a VGA controller can be implemented to display not only a graphical user interface to adjust the signals parameter but also to display an individual pixel biasing screen and the aquired image from the ITP ROIC in this way substituting the external frame grabber and making the FPGA system autonomous In a like manner another FPGA board could be programmed to be used as a frame grabber receiveing only video and synchronization signals liberating hardware resources for the test and characterization s main system USB or RS 232 interface for transferring of stored images in a standard image files format 111 hh Y U e A UN ON 9 10 11 12 13 14 15 16 17 References Glauco RC Fiorante Payman Zarkesh Ha Javad Ghasemi
11. and die 8 c 56 Pinout of ITP ROIC FPA and test structures version 1 57 LCD initial screen a and pinout D iine ee Diod ru p usn Va eid 57 Probe station with integrated video camera to monitor and to computer 59 Grabee software for image and video acquiring from video camera on probe v E RN 60 Keithley panel and I V measurement circuit diagram 40 61 NI LabView GUI for Keithley parameters adjust a and its block diagram O RUN NERONI E A A Te ANREDE me Tero nen rare ern 61 Figure 4 25 Laser setup for electro optical response characterization 62 Figure 4 26 Laser optics specifications soricina s 63 Figure 4 27 Laser Optics Setup IMPI ds 63 Figure 4 28 Laser optics setup output oooonnnnnncnncnnnnnnncnnnonononnnnnnonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnos 64 Figure 5 1 Block diagram a and instantiation b of toggle function 66 Figure 5 2 Rotary switch a cam operation b debouncing signals c and event pulse and direction d Dl adonde 67 Figure 5 3 Parameter counter block diagram a and instantiation b 69 XIX Figure 5 4 Parameter counter selection multiplexer sene 69 Figure 5 5 Clock generation and division waveforms sse 70 Figure 5 6 Block diagram of clock generation and division ooocnnn
12. b c Figure 4 5 Pmod push button a slide switch b and rotary switch c 22 b Figure 4 6 Pmod LED a and buffer circuit b 22 One digital input on MIB receives the synchronization signal from the mechanical laser chopper in TTL level and a resistive divider 1s used to reduce the 5 V pulse originated from this signal to the 3 3 V of the FPGA input For the unit cell testing procedure the chopper generates the starting signal for a sequence of pulses synchronized with the laser light 46 4 4 Digital output level shifter A CD4504B 23 has been used for the digital level shifter which converts the 3 3 V of the FPGA board to 15 V on digital control inputs of the FPA such as the SW REF SW INT and SW HOLD In a like manner the level shifter with associated circuitries was used for maximum and minimum output voltage level control for the individual pixel BIAS as illustrated in Figure 4 7 5 VDC Video BIAS a b c Figure 4 7 Digital level shifter circuit a voltage levels control b and designed PCB c 4 5 Electronic switch A high frequency electronic switch 24 controlled by an SW_INT signal opens the circuit to V BIAS to avoid an internal short circuit with V REF on some nonstandard operation tests as illustrated in Figure 4 8 a Another electronic switch controlled by a clamp signal generates an adjustable reference value during the start of line Figure 4 8 b
13. to define the black level of the acquired image which is essential for the correct operation of the low cost AC coupled adopted the frame grabber 47 5 VDC light REF FRAME co PATTERN s not light GRABBER 4066 OR VIDEO 4066 BNC Video BIAS eo F M lt NOT INT a b Figure 4 8 Safety electronic switch for BIAS a and clamp reference value switching b 4 6 DAC A digital to analog converter DAC on the Spartan 3E board was used to generate specific voltage values and ramp waveforms An operational amplifier was used to adapt the DAC voltage range of 0 V to 3 3 V to the necessary voltage range 0 V to 15 V Complete knowledge and domain over the functionality of the DAC with the precise control of the bias voltage value on each pixel at its clock timing was essential for the main ITP ROIC feature Furthermore the ramp generation allowed clock feedthrough analysis on the gate of the transistors and allowed individual voltage definition that permits future on system image processing and also allowed fixed pattern noise FPN compensation and nonuniformity correction NUC on acquired images 48 2 5V OUD 1117 tp I I N10 T4 SPLMOSI QN e DAC_CS_ 1 I u16 LSPLSCK_ 0 VCC DAC CLR 1 2 3V I SPI MISO TNR a b SPI MISO 0 Slave LTC2624 DAC 31 x Don t Care DAC_CS SPI SCK Master Spartan 3E FPGA E 12 bit Uns
14. 12 electronic circuit and interconnections to the FPA necessary for generating of internal bias for selecting of pixels for transferring of input bias multiplexing of output signals and buffering of the video image Several circuit blocks were implemented for these functions and except for one issue that was corrected proved to work appropriately In addition the semiautonomous test and characterization system with its flexible software and hardware developed 1s working as a guideline for new test bench structures of chip projects that are underway to the best of our knowledge Additionally the designed and implemented photodiode based FPA and ROIC together with the FPGA based controller are the first functional video camera designed and built in toto at the University of New Mexico Furthermore the FPGA based test system developed 1s a solid starting point to create an autonomous ROIC controller for fabrication at the commercial level an essential feature for a portable infrared camera Portable image systems could be the better option for preventive skin cancer examinations in rural communities and presidents of these communities often are more likely to be exposed to sun and UV rays than are urban workers In addition new techniques of chip interconnection were developed to obtain access to discrete devices to test structures blocks circuits and dies and consecutively to grant nondestructive flexible quick i
15. 15 Example of flat panel array configuration and TFT interface to the ROIC input b 15 9 Figure 1 9 Typical a unit cell and new ITP ROIC b unit cell 10 Figure 1 10 Typical ROIC multiplexer white with added features gray 11 Figure 2 1 Circuit of ITP ROIC unit cell and peripheral circuit block diagram 17 Figure 2 2 Timing diagram of main signals on ITP ROIC eee 17 Figure 2 3 Electronic circuit of the two stage operational amplifier adopted in the unit E S a ueste dux A E DM VAM D AE Re DUE UE 19 Figure 2 4 Unit cell electronic circuit dIapram da 20 XV Figure 2 5 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Level shifter column bias mirror selector width control and MUX circuit 21 Minimum feature size resolution and adopted values not to scale 27 Draft of DRCs to be considered not to scale occcccncnnnnnoooncconnnnnnnnnnnos 23 Metal 3 to metal 2 a and metal 2 to metal 1 connection b 24 Ground pickup to metal 1 a and VDD pickup to metal 1 b 24 Active area and poly contacts to metal 1 cells ooooooonnnnnnncnnnnnnos 24 setup definition of cells a for semiautomatic matrix creation b 25 Photodiodes discrete
16. He understands our professional needs and personal issues doing his best to help us Many thanks to my co advisor professor Payman Zarkesh Ha for his close guidance throughout this work his visits to the lab sometimes unexpected and always a pleasure were filled with always useful discussions and follow ups I am especially grateful to professor Francisco Javier Ramirez Fernandez for his essential help and support during my graduate studies It also 1s a pleasure to thank professor Keith A Lidke and professor Sang Han for serving as members of my defense committee as well as for their time and interest in my research Thanks also to professor Luke F Lester for his orientation and support I want to thank Elmyra Grelle for receiving me at UNM and guiding me through the formalities of the ECE department I thank my research group members and the Center for High Technology Materials office staff and facilities for precious and timely support I also thank Jim Wagner for the invaluable input he offered for my thesis editing I greatly appreciate my parents love and dedication which shaped my character guiding me throughout my life and into the arena of higher education I also thank to Samuel Ferreira da Silva which even from far away greatly supported me on this journey My warm thanks go to my wife Elaine for her full time work patience and wholehearted friendship and love My special thanks go to my dau
17. Third Terrestrial applications on MWIR and LWIR are very attractive due to the transmission window in the atmosphere 7 1 2 DWELL One possible technology for image acquisition on infrared bands of MWIR and LWIR is the quantum dots in a well DWELL device Although DWELL detector is a motivation for the designed ROIC presented in this work it 1s not the scope here to detail the DWELL development functionality fabrication and characterization However a brief device description and principle of operation are presented 2 A DWELL detector is basically a hybrid of conventional quantum well QW and quantum dot QD detectors In a representative DWELL heterostructure InAs QDs are embedded in InGaAs GaAs multiple QW structures and electrons in the ground state of QD are promoted to a set of bound states within the QW by photoexcitation Altering the QW thickness of the DWELL detector alters the nature of the allowable energy transitions bound to bound bound to quasi bound and bound to continuum thereby altering the DWELL s operating wavelengths These energy transitions enable the detection of photons from MWIR to VLWIR within a single detector Moreover a bias dependent spectral response is also observed in DWELL detectors due to the QCSE The asymmetric geometry of the electronic potential due to the shape of the dot and the different thicknesses of QW above and below the dot results in variation of the local potential
18. 13 Oct 2011 Arlington DC e Ajit V Barve Saumya Sengupta Jun Oh Kim John Montoya Brianna Klein Mohammad Ali Shirazi Marziyeh Zamiri Yagya D Sharma Sourav Adhikary Sebastian E Godoy Woo Yong Jang Glauco R C Fiorante Subhananda Chakrabarti and Sanjay Krishna Barrier selection rules for quantum dots in a well infrared photodetector IEEE Journal of Quantum Electronics Volume 48 Issue 10 Oct 2012 14 1 8 Outline of dissertation This work is organized as follows In Chapter 2 the concept of the proposed individually tunable pixel ROIC ITP ROIC is discussed while in Chapter 3 the detailed circuit designs and implementation techniques are explained The essential and particular infrastructure created for testing and characterization of this design are described in Chapters 4 and 5 detailing the hardware and software respectively In Chapter 6 experimental results are presented and analyzed In Chapter 7 comments are offered and suggestions are made for continuing work 15 Chapter 2 Chip architecture The unit cell shown in Figure 1 9 b was intended to be functional yet simple enough to meet the unit cell area constraint The circuit implementation of the ITP ROIC unit cell 1s shown in Figure 2 1 together with the peripheral circuit block diagram The timing diagram for the dark current response covered chip is shown in Figure 2 2 with Pixel 1 bias in full cycle The CTIA integrator was chosen be
19. 3 g q 0 5 0 3733 Sook toggle east entity work toggle beh 3735 port map THERE gt HERE 3736 in out 3137 input gt east bt signal 3738 reset gt SYSRST 3739 toggle gt high level m 3740 direct gt low level z 3741 3742 M v 37143 3744 EI 3146 v v 3747 0ut imnm 3748 out T or D gt east BI toggled 3749 I 3 I 5 0 o 1 0 ey d j 4 Q EH g b Figure 5 1 Block diagram a and instantiation b of toggle function 66 A versatile device for pulse generation is the rotary switch the principle of which 1s a cam connected to a shaft that is used to operate two switches Figure 5 2 Both switches are closed in the stationary detent position Then depending on which way the shaft is rotated one switch will open before the other In the same way continuing the rotation one switch will close before the other 41 Turning RIGHT 1 gt etent Detent B rotary_q1 rotary_q2 O c d 1 Synchronous pulse rotary ql rotary event rotary qg2 rotary left GND b d Figure 5 2 Rotary switch a cam operation b debouncing signals c and event pulse and direction d 41 Another digital input receives the signal directly from the 3 3 V power supply and controls an implemented
20. 6 12 GMI Be CO Cl LT 103 6 13 Dr Kor 2 ATQ A vec deo un es qus dont 105 6 14 Problema SoIUCIOBAdO cioe eub epo Ee Pede puteo dusk eee pd Pale qutd 107 xili Chapter 7 Conclusions and future WoTk occcccccnnccoooncccnnnnnnnnnnnnnccnnnnnnnononononoconnnnnnnnnnnos 108 Tol Conclusi n ida 108 TZ POT SE OF Kh rate sartaateard E T 108 2 DOSE addon 108 eZee VAN AGC AA E et enateosaens snare 109 JN S MEC In dd ii 110 ROE larch E T LTEM 112 X1V LIST OF FIGURES Figure 1 1 Energy of photons in the visible spectrum 3 oooonnnnnnnnninnnnnnnnnonononinininnn l Figure 1 2 Growth schematic a and bias dependent spectral response at 30K b 3 Figure 1 3 Schematic drawings of three CMOS photodiode structures 9 4 Figure 1 4 Spectral circuit independent Sensitivities A ooooonnnnncccnnnnnnnnnnnnnnnnnnononnnnnnnnos 5 Figure 1 5 Spectral circuit independent sensitivities a and device structure b 10 6 Figure LO EPA hybridized Overa ROIC Tian 7 Figure 1 7 Images taken with the array under white light exposition and sensor bias of 2 6 V a and 2 4 V b respectively The image in b is reversed because of the different current flow direction in the detection system since the two p 1 n sensors have opposite orientations Some bad contacting gate and data lines can be observed 14 8 Figure 1 8 CTIA internal dynamic range hole and electron collection a
21. AND gate on each signal output Figure 5 11 When the power of the device under test DUT is manually turned off after tests are executed the FPGA system which is always on to preserve the programming on RAM memory automatically turns off all signal outputs as a safety measure except for the oscilloscope synchronization output 67 5 2 Parameter up down counter One essential characteristic of this test system is that all parameters can be adjusted online and locally This is crucial to change the waveforms and to allow immediate visual analysis of the cause and effect between the signals and the hardware response For each variable that controls one parameter of a signal a memory was built based on an up down counter Figure 5 3 It 1s reset upon start up or manually in which state the output goes to an initial value that 1s defined by constants on compilation or 1s originated by the setup block as necessary The minimum and maximum values that can be reached are defined by constants in the compiled program but they can be defined by other counters if necessary They receive the up down and clock signals from the rotary switch conditioning block and in this way the value is automatically increased or decreased according to the rotary switch movement These counters work closely with the LCD screen selector Figure 5 8 described in Section 5 6 which enables the up down counting of pulses from the parameter value rotary switch
22. E E EOI a he Gases tana adel ames 105 Figure 6 22 A 2 x 2 matrix of individual unit cells with external column row selectors XX1l LIST OF TABLES Table 1 1 Dark current on the three types of photodiode 9 ooocccccccccnnnnnnommmm gt 5 Table 2 1 Opamp specifications using Spice SIMUlatiODS ooooonnnnnccnnnnnnnnnnnnnnnnnnnononnnnnos 19 Table 5 1 Digital outputs related internal signal names and pulse generated signals Doll m E 65 Table 3 2 VOA timine TOF 640 x 480 pixels M ient stet het Cen DOR ese 87 Fable 6 1 ITP ROI desren naim paramole Sieisen I bells o A bvenp metet ets 90 Table 6 2 Response comparison of different photodiode structures 92 XX111 Chapter 1 Introduction 1 1 Electromagnetic radiation The visible region of the electromagnetic spectrum is defined by the range of wavelength A visible to the human eye from 380 nm to 700 nm 2 The correspondent electromagnetic frequency 1 1 ranges from 790 THz to 430 THz and its energy eV ranges from 1 7 eV to 3 3 eV Figure 1 1 oon y Ir T gt S Or Y in y Je A R PN e led G eN E P4 V m Figure 1 1 Energy of photons in the visible spectrum 3 The infrared IR region of the electromagnetic spectrum presents several subdivision schemes commonly used for the IR region 4 such as from the International Commission on Illumination CIE the ISO 20473 and the astronomy division
23. LCD signals from controller block a 18 and manual selection of internal number Ew signal bar measurement b This block receives two strings of 16 characters that are written on RAM memory of the LCD module 43 which constantly reads its content for display This asynchronous process updates the screen as soon as the value of some parameter changes on the up down counters Adaptations of the original code were made allowing two more lines of 16 bits to be shown on the LCD screen as 0 s and 1 s for verification of numbers and variables inside the program as binary numbers Figure 5 7 b 5 6 LCD screen selector Keeping in mind the development of a simple test system independent of third party software hardware 1 e computer and GUI the onboard LCD receives two lines of strings that are updated with labels or variable values defined on compilation The rotary switch has a push button that alters its function between parameter screen selection and 72 value modification of the desired parameter Figure 5 8 Several parameters can be grouped and adjusted in one screen depending on connected hardware LCD controller STRING to Display eo o r selection number CLK PER Slo 318 south_BT_signal led dks IlI e u u a 8 ROT1_event I ROT1 l ROT left ee gt sel 81 MAIN CONFIGURATION when 61
24. SE eS Ten en eT ene ee en ee er 62 Chapter 9 Test Systern SOM W abe aaa 65 3 Dicital inputs COLONOS ita 65 2 Parameter up down COUIGE ius eere oett pea e eben ea PEE eae e etes nba ped ede 68 5 3 DOAN SN SC E EAE CE AOE A A N AR E 68 5 4 Clocks gcneral ON eraen a i rat ed a aet 70 9 9 Er a A v om Dude 71 5 6 GD gereon Sele OE didas id 72 SWA COMERTE AA de 73 5 8 Pulse eener AOL tibio 74 5 9 a EU O A 75 5 10 Output CO roland odo 75 5 11 SANCTI OSO COn 76 3 12 Frame time calouldtiofbucnuus s S eoa A EORR SB eroe In enne idend TI lOs Pulse Ta AAA Lo o aeuho fads LET 78 5 14 SCA WOTA Tc 78 5 15 PAC FAN CON rito coalici n 79 5 16 DAC DLOPLIQUDIITHIDB ias eru I NAE 82 517 RowO UNM backup Plains 83 xli 5 18 OS x 9s mage Palais 84 5 19 RODA ao 85 5 20 VA CORTO ler citrico 87 Sof B eggs 88 COMA VE 1 AAA E tears E OOO CE In Minerua tentus dLM Eius ted nU 89 6 1 POCO O NS E RT rc 91 6 2 POTOSI Sata 92 6 3 MITO transistors sida didas dos 93 6 4 CO MUTASE LE CLOL rail 94 6 5 Unm ee ysis letersi a in achan ols datums E aan dls dctumeenlnadnc eusdduntboce 94 6 6 A A 9 96 6 7 FPOUA Test SV SLICE cese dene pb pent e Ner REP E P enit Nee ou ea Ob RUE 98 6 8 PCB anda Interconectado 100 6 9 DAC biasand tamp Benetator sie acu Nee eon Ye boa uet ie xS nua aas is reote mend 100 6 10 Sia aiii A E E 102 6 11 is A O once ea cuue Nasa 103
25. STR4 lt c lt high level sel 159 Ei esw c ew c2 ew c ew c4 Figure 5 9 Context menu and switches a circuit under testing b and correlated VHDL code c 5 8 Pulse generator There are 18 pulse generators Table 5 1 based on a counter process controlled by a clock and by a reset start signal the origin of which can be selected by software on a specific screen via a multiplexer Figure 5 10 The size position and high level size of the periodic pulse are defined by their respective parameters also adjusted online Figure 5 10 Block diagram of pulse generation and its parameters SW light pro 74 With these functionalities several signals could be started at the same time to test the unit cell and the relative position between the pulses can be adjusted online as desired to obtain a variable test pattern with immediate waveform response from the hardware for visual analysis of their interaction Two specific counters generate a vertical line and a horizontal line in the video output with adjustable position and size on screen A simple AND gate on these signals generated an adjustable square signal to synchronize an external laser light to a specific pixel or to a region of interest Furthermore this signal was used to define a region of different bias values to enhance the response and to discover specific features of the object in the acquired image 5 9 Setup After a des
26. against a 6H x 3V design cell with dislocated flipped columns and an overlapped power grid Figure 3 28 Attention was taken regarding the metal layers on matching connections and minimum distance rules the joined N Wells areas the minimum distances between the active area and poly layers and to the shared positions of pickup to ground contacts 40 w i A es e Figure 3 28 Dislocated top flipped midle and overlapped columns bottom for 100 fill factor FPA 3 15 Final design The unit cell was designed with 17 transistors with a minimum width length feature size of 2 36 1 5 um um and three poly capacitors Figure 3 29 a to fit in a 30 x 30 um The power grid is distributed by vertical grids Eight horizontal and two vertical lines conect the input output signals Figure 3 29 b The ITP ROIC final layout of the chip is shown in Figure 3 30 41 a b Figure 3 29 Unit cell main layers layout a and signals connections b m BEARNEEENNENMWN SNNSENEE eee AA se E i OMAR NARNIA AO ARONA RANIA AAA AAA AAA A NAS E s E T Figure 3 30 ITP ROIC final chip layout 42 Chapter 4 Test system hardware The actual hardware system Figure 4 1 operates with a minimum of one rotary switch and five push buttons already onboard together with the LCD display on a context menu maximizing its functions and operation but allowing external boards to be adde
27. and Sanjay Krishna Spatio temporal Tunable Pixels for Multi Spectral Infrared Imagers approved for publishing IEEE 56 MWSCAS Aug 2013 http en wikipedia org wiki Visible_ light http en wikipedia org wiki File Colors in eV svg http en wikipedia org wiki Infrared http www ipac caltech edu outreach Edu Regions irregions html Miller Principles of Infrared Technology Van Nostrand Reinhold 1992 and Miller and Friedman Photonic Rules of Thumb 2004 ISBN 9780442012106 S Krishna The infrared retina J Phys D Appl Phys 42 2009 234005 6pp Woo Yong Jang et al Demonstration of Bias Controlled Algorithmic Tuning of Quantum Dots in a Well DWELL MidIR Detectors IEEE Journal of Quantum Electronics Vol 45 No 6 pp 674 683 June 2009 Kartikeya Murari Ralph Etienne Cummings Nitish Thakor and Gert Cauwenberghs Which Photodiode to Use A Comparison of CMOS Compatible Structures IEEE Sens Journal Vol 9 No 7 July 2009 Xiang Cheng Jiantao Bian Chao Chen Wei Chena Research of different structure integrated photodetectors in standard MOS technology Optoelectronic Devices and Integration H Proc of SPIE Vol 6838 683810 2007 Thomas Sprafke and James W Beletic High Performance Infrared Focal Plane Arrays for Space Applications Optics amp Photonics News June 2008 Vol 19 No 6 available at http www ee ucla edu leosla documents James Beletic OPN pdf
28. and concatenated binary number b Figure 5 20 shows the video waveform of another generated pattern together with the pixel clock line sync frame sync and master sync with the clamp signal added at the start of the line sweeping 83 Umm qi i 1 P 3 ij i P Scan Stetus 5 00MS s 7 E ge 5 00 14 50 10k points 2 04 Y 24 0ct 2012 0 D15 D0 07 49 29 MF Timing Resolution 200ns Figure 5 20 Video waveform of 19 x 5 pixel generated pattern 5 18 98 x 98 image pattern To demonstrate the individual bias definition on each pixel a binary image pattern was created with Excel software as a tool for bits concatenation and string creation The desired text was written in a text box and used transparent color as a guide for a manual bits definition Figure 5 21 Then the image was sliced in strings of similar sizes and shapes to reduce the number of constants in the source code Figure 5 22 EE 22 x 15 12 lt gt x 15 I 4 13 x 15 Figure 5 21 Slicing of binary image pattern for concatenation and definition of code 84 12595 U_top std logic vector 15 downto 1256 E top bottom std logic vector 5 downto 1257 E middle std logic vector i5 downto 1258 C 1 std logic vector i15 downto 1111111 I AAAI IIIA o 1259 Cc 2 std logic vector i5 downto 1260 c3 std logic vector 15 downto I I j I I j
29. column selector consists of a 99 output shift register built with 100 D flip flops DFF using the low voltage devices 3 3 V with a minimum transistor width length size of 0 9 0 35 um um Following the design for testability DFT technique the DFF 99 Figure 3 18 does not activate any column but its output 1s driven directly to an external pad as 1s its COL OUT input In this way it was possible to verify the functionality of the column selector to monitor the waveform controlled by 33 the width ctrl pin and to test the output buffer Figure 3 19 shows the waveforms of the column selector in Spice simulation g bar u 8 o B B n g o simul spc 01 11 57 06 17 12 AUT 14 00u 16 00u Seconds Figure 3 19 Waveforms of the column selector in Spice simulation 34 3 9 Column driver The layout of column driver block is shown in Figure 3 20 M10 and M11 are the level shifter input transistors while M6 and MS are the output transistors M4 is the column mirror transistor activated together with M9 and M3 the switch of multiplexer that receives the signal from unit cell output and transfers to out select node MI M2 M7 M8 M12 and M13 constitute the 2 inputs NOR gate for width control on Col sel pulse ect 3 COL Col se QUT Se E y 8B width Ctl bar m Unitcell out B 1 L E res ra to ca ES Figure 3 20 Level shift
30. desired change of internal signals routing to the external pin as well as to easily identify the board connector Figure 5 27 shows the internal signal names Figure 5 28 presents the I O port name on code bridge between signal and pinout and Figure 5 29 illustrates the FPGA pins 186 187 189 11405 11410 11411 11412 11413 11414 IOPin25 IOPin27 IOPin25 IOPin31 connector J4 SW bias ext out SW zero out SW int out SW hold out Figure 5 27 Internal signal connected to in out port on code 1479 1480 1481 1482 1483 1484 1485 1486 1487 10Pin25 IOPin26 IOPin27 IOPin28 10Pin29 IOPin30 IOPin31 IOPin32 out IN out IN out IN out IN std logic std logic std logic std logic std logic std logic std logic std logic connector J4 Figure 5 28 Port defined with the physical connector name on the board IOPin25 IOPin27 IOPin25 OPin31 XE 2149 A16 FIs E11 TT IOGSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD LVCHOS25 LVCHMOS25 LVCHOS25 LVCHOS25 SLEW SLEW SLEW SLEW SLOW SLOW SLOW SLOW Figure 5 29 Board connector name attributed to FPGA pinout 88 DRIVE DRIVE DRIVE DRIVE oo oO Oo LL LI a na a Chapter 6 Results A microphotograph of the die with a total size 5 14 x 5 14 mm is shown in Figure 6 1 together with the identification of the main circuits Table 6 1 summa
31. ee ee ee a ee MMMM b 65S OOOO OOOO OE ST ONO DONACIONES 25 4 175mm imn J inn inen onn a Figure 4 27 Laser optics setup input Figure 4 28 illustrates the cube beam splitter inserted to permit a video camera and respective magnification optics shared from another probe station to visualize the x y z micro positioning of the 7 um diameter beam over the photodiode of the pixel The light energy will be measured with the insertion of the power meter sensor in the beam path 63 immediately in front of the FPA under testing and a second beam splitter facilitates the light power monitoring The same rods cage plates posts and post clamp were designed to hold the FPA under testing on the micrometrical positioning system inch fina Figure 4 28 Laser optics setup output 64 Chapter 5 Test system software The VHDL based software has 26 main digital output signals Table 5 1 with 87 adjustable parameters used for the testing system The 856 digital vector and string type signals were created during the development and any of them could be driven as necessary to the 26 physical signal outputs Due to the nature of VHDL language and the FPGA structure the software blocks easily resemble hardware blocks and are detailed as follows Sync Unit cell UC and FPA Auxiliary Frame FPA grabber shared Pixel clock ROW sel ROW RST EXT SYNC Clamp size COL_ Sub clock ROW sel BAR S
32. functionality of the new ITP ROIC without the direct implementation of the DWELL FPA we have implemented the n n well p sub diodes 9 as photodetectors in this project as illustrated in Figure 3 9 This also allowed us to test and characterize the design at room temperature and to acquire an image at environment illumination level with the use of single lenses 27 Aw hb Oooo 2 55 on 4 noo 7 ooo s E amp ib PhotoDiode L closed sw amp ib_PhotoDiode_L_open_sw noo v ib con M1 M2 auto 7 LARES E ib pickup Bulk to GND via PP 3 5 Da i ib pickup N Well to VDD via NP 2 Minimum safearea O O O Label ooo RULER3 oooO RULER primitwes O O O a c Figure 3 9 Photodiode design layers a cell b and its hierarchical design cells c In this design two access points were inserted to guarantee the connection of the photodiode while a switch design cell allowed two versions of unit cells one with connected photodiodes and another with an open circuit For cross talk reduction one can observe the metal 4 layer covering the area not intended to be photosensitive and one also can observe the substrate ground pickup Several versions of this photodiode were designed for characterization as a copy of the original design keeping dimensions shapes layers connections and the expected response characteristics Figure 3 10 below a illustrates this test structure design b s
33. gt screen upper line label lt Clock div CLK PERIOD Screen bottom line label lt s01 amp amp s02 amp lt amp s03 amp CLK PERIOD STR3 Figure 5 8 Block diagram of LCD screen selector and adjustment of parameters The label of each line although it must be defined on the source program and compiled is easily and directly edited The characters typed inside the double quotation marks are converted inside the main code from a string type to the correspondent binary code which will be sent by the LCD controller block read and correctly interpreted by the LCD board 5 7 Context menu After reaching the limitation of available connections for the desired number of switches and push buttons a context menu was created on the LCD display Figure 5 9 in the way that any number of desired virtual switches could be created using minimal hardware In this case the screen selector signal sel 160 also enables a toggle function to the four context push buttons each selecting an internal connection and the selection 73 label to be displayed context_PB_C1_1 context_PB_C2_1 context_PB_C3_1 context PB C4 1 a 5787 5788 5789 5790 3791 5792 5793 5794 5795 5796 5797 UDC10b clock EN unter_clk4 x sE D a m o b context PB C1 1 select counter en4 Screen text selection context PB C1 1 select context PB C1 1
34. in addition to a standard level shifter the column select contains the control signal width ctrl to avoid cross talk of the bias voltage between two adjacent pixels while the pixel clock selects adjacent columns In addition the column driver contains an analog multiplexer to generate the video signal The schematic of the column level shifter is shown in Figure 2 5 As illustrated the circuit includes one transistor that mirrors the column bias current the multiplexer switch and a 2 input NOR gate which externally controls the width of the column selection pulse The column bias transistors are mirrored on a 10x size transistor that has a bias current of 20 uA defined by an external resistor to GND COL SEL COL_OUTO MUX_OUT f Q 0 0 OUT_CS_B OUT_CS Figure 2 5 Level shifter column bias mirror selector width control and MUX circuit 21 Chapter 3 VLSI Design 3 1 DRC and minimum feature size Tanner EDA tool 16 was chosen for the chip design and for the manufacturing was the double poly four metal layer standard 0 35 um mixed signal 3 3 15 V TSMC high voltage CMOS process 45 presenting a manufacturing grid of 0 025 um internal unit and mouse grid of 0 001 um and contact size of 0 36 x 0 36 um Considering the small number of components using the exact minimum feature grid size of 0 001 um or even 0 01 um could generate difficulties in design to snap shapes together Thus a grid of 0 05 u
35. j 1261 c4 std logic_vector 15 downto wv 1262 C 5 std logic vector 15 downto 1263 C 6 std logic vector i5 downto Il I t t 1264 C 7 std logic vector 15 downto is IN 1265 H top bottom std logic vector i5 downto I I I OQ O O OG OQ OC D OD OO OQ OG Q s Il 1266 T top bottom std logic vector 5 downto Figure 5 22 Constant vector components of binary image pattern The scan word block was used to read each line of the code to the video output which is controlled by the reset signal that 1s connected to line sync signal and by the clock signal which is connected to the pixel clock The desired line code comes from a word multiplexer controlled by a counter the count of which is increased by the line sync signal and is reset by the frame sync signal Figure 5 23 code_words 10 po sean word ONG 700007 1 UDC10b 96 code_word7 9 x code_word6 8 code word98b UNM bias o a D wo si3isi2 code_word5 7 start a code word4 6 gt CK Xox o code_word3 5 238 D one 98x 4 E o B zero 98x 3 clk pixel 4 zebra 98x 2 j FPA98 line bias 1 lt MUX_clk4 1 UP 2 zero 98x Dfit Fsync 4 FPA98_line_bias RS7 0 start fall SYSRST JRST Lsync FPA2 98 word98b FPA2 98 word Line to bias outMUX UDC Figure 5 23 Image pattern scanner for binary bias generation 5 19 ROI biasing To generate not only a fixed image but to demonstrate
36. one can note its devices and respective functions M3 M4 M5 M6 M13 M14 MIS the operational amplifier of CTIA Comp frequency compensation capacitor 19 C4 BIAS ZERO capacitor M7 the integration switch C2 integration capacitor M8 the hold switch C3 HOLD capacitor M1 output buffer M10 the bias switch M2 column input multiplexer switch M9 the reference voltage switch M11 M12 unit cell address selector A_COL_SEL GND UDD OUT A A SEL 6 IBIAS O e B ROM SEL B R M411 S lo qYM DN M 12 M 2 Q le D x a M e D S t B e 5 E gt G G O S G G S e G 5 y j S sh 8 S JAM D SY ASY D Si HOLD Cell_AND M 5 M 6 c l id M U Bias Zero gt O z AOP bias c AQP out U Hold M 1 Ks Na m G G ala wv Le B TO nalan a E G aa e 5 PO2 OL C4 BIASY ZERO 5 57f bO2 a SYM SYM Tot C ae PO M1 C3 HOLD po n4 On ea ua rgo Z a E 5 gt o Y Oel o S S 0 AOP comp po2 I Tm 13 6 6 a ASYM gt i 9 M 14 M 15 M 9 ASYM ASYM N a G qc 4 cL S S z Sa y SH T oo 0 z 0 45 E Oy z PO M1 a A a Z a N co 144 s Z A A es eee J Figure 2 4 Unit cell electronic circuit diagram 2 3 Column driver The low voltage output of the row and column selector must be modified to high voltage to control the unit cells We have used a standard level shifter for the row select 20 However
37. pin was chosen from the numerous generated signals of the FPGA to be connected to the auxiliary input pin of the oscilloscope to synchronize the signals without the effort of locating the desired signal on the hardware and the repositioning of the probe Furthermore using one multiplexer controlled by a specific screen virtually any internal signal could be accessed to synchronize the oscilloscope One specific pulse signal EXT sync also was designed to permit a more practical delay operation similar to the one existing in the oscilloscope 76 5 12 Frame time calculation The test system offers the possibility to adjust the desired number of horizontal active and dead pixels columns of vertical active and dead pixels rows of duration or size of the high level phase on pulses and duration and position of the clamp signal The number of pixels defines the line sync Lsync signal duration and the number of rows defines the duration of the frame sync Fsync in terms of clock pulses A main sync Msync signal generates the synchronization for the start of the frame the writing reading BIAS phase and significantly the integration time phase duration which for value modification is based on row time Any of these parameters if changed alters the duration of the frame time and requires a matching of their values This was achieved by the development of a math block to calculate the necessary number of pulses to match the size of the
38. the integration switch 20 0jus 50 0MS s Aux BP _zero_to_bias 20 0jus 50 0MS s Aux 40 00 10k points 1 86 Y E 10k points 1 86 Y D15 DO 5 00 V Timing Resolution 20 0ns 5 00 D0 Timing Resolution 20 0ns Figure 6 17 Clock feedthrough effect a and slew rate control compensation b An offset compensation on the output signal would be an option but for the actual system it seems that this effect occurs on all pixels and that it is compensated on the final 102 image due to the frame grabber voltage range adjustment 6 11 VGA controller Initial tests were made with a VGA controller block 47 for a 640 x 480 pixel resolution image on an external monitor proving that autonomous monitor controlling could be achieved Figure 6 18 Unfortunately it would be necessary to implement an analog to digital ADC conversion block a dual port RAM memory and a synchronization block to transfer the image from the FPA to the memory and to read the RAM to the VGA control block with independent clock frequencies Due to time limitations this phase of the project was left for later development Figure 6 18 Images from FPGA ROM memory a and processing b 47 6 12 Chip recovery During initial testing of the FPA it was noted that the SW BIAS on each pixel was not being activated by the internal AND gate This problem was detected with the injection of a tri
39. to integer unsigned ramp1_LOx10 from unsigned 17 bits to natural unsigned to natural MEL Lud SS SS SS SSS SS SS SS SSS SSS SS SS SSS SS SS SS SSS SSS SS 5975 rampl LO STR3 dec lt rampl LO STR3 3 E 5976 rampl LO STR3 unit lt rampl LO STR3 1 amp rampl LO STR3 2 a 10 2 gt gt 20 30 40 gt 20 60 J40 7 90 90 100 113 9924 8925 when 70 gt screen upper line label lt Rampl MAN amp rampl STR4 9926 screen bottom line label lt rampl LO STR3 unit amp amp rampl LO STR3 dec amp gt 9927 amp rampl HI STR3 unit amp amp rampl LO STR3 dec amp amp rampl STR4 12 amp PTE rmapl STRA G4 amp w 7 Figure 5 17 Minimum voltage counter instantiation center LCD screen with Ramp 1 parameters top and screen labels values on code bottom 81 5 16 DAC programming A parallel to serial block was used to generate the serial command word for the digital to analog converter Figure 5 18 which consists of a command 4 bits an address 4 bits followed by data value 12 bits and don t care 4 bits The system clock of 50 MHz provides the maximum frequency to write the command word on the DAC and one more bit was added on each of the four concatenated command words to match the desired number of the 100 system clock division which defines the pixel clock frequency of 5
40. with a pixel level tunable bias control is demonstrated The new ROIC is capable of providing a large bias voltage in both polarities on each individual pixel independently These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier CTIA CMOS ROIC architecture The unit cell electronic circuit was designed using 15 transistors and four capacitors and consists of the CTIA integrator a two stage seven transistor operational amplifier one analog memory one address selector one reference recover switch a sample and hold stage an output buffer and an output multiplex switch Several test structures of individual devices and complete circuits were implemented on the test chip to characterize each one and to reconstruct the unit cell with discrete components if necessary Intending to test characterize and control the ITP ROIC an FPGA based hardware and GUI software were developed to generate four analog and 26 digital output signals with 87 adjustable parameters and it contributes for the unit cell characterization setup the FPA ROIC system test and for the development of an autonomous controller for a DWELL based IR portable camera In addition to the hardware chip interconnection techniques were developed to grant nondestructive flexible quick interconnections for definition of new test setups The test chip has been fabricated in TMSC 2P4M 0 35 um high voltage CMOS technology by MOSIS With 250 kHz of pi
41. 0 1 2 54mm straight header male pins 27 for cable connections as illustrated in Figure 4 15 where one also can note the flipped design image for pinout Although this option offered a die connection with a ready professional wire bonding the necessary manual soldering process was found to be more difficult than expected due to the small dimensions of the package In addition in the case of damage to the chip all the material and time invested on this PCB manufacturing would be lost Furthermore in this package we have access only to the main signals of the design and the test structures with internal pads would be useless 53 003 H o B PERS ai OROROORO MM Onn s E po wj A Vm a8 e e ol o 9 o O s xe X uM S o Os O Qs i on Tes 9 anO Xo MO os ORO COLOR RO COI SO DADA OS p RC e LN CI 8 j UI EE O 9 oe AIA Coes O10 0 o GD y y T V 0 ORO macicd OKO os FORORO O 9 b DOO oo E o O yy lm vm 1 1 sr 1 JL FL AL a o 7 1 D 1 1 dd 4 i 15 1 15 sr 1 a TL OL AL 0 1 6 4 MOI 15 o y 3 9 9 22668 e 0000044 OS Figure 4 15 PCB for QFN package pinout a top b and bottom view c 4 10 2 LCC carrier PCB The bare chips were mounted and wire bonded to a 0 4 x 0 4 10 16 mm open cavity leadless chip carrier LCC package of 17 x 17
42. 0 dpo3000 mixed signal http www signatone com products microscopes psm1000 asp http www startech com media products S VID2USB2 Manuals VID2USB2 pdf 113 39 40 41 42 45 44 45 46 47 48 49 50 https en wikipedia org wiki Current E2 80 93voltage characteristic http www keithley com support data asset 878 Ken Chapman Rotary Encoder Interface for Spartan 3E Starter Kit Xilinx Ltd Feb 20 2006 http vhdlguru blogspot com 2010 04 8 bit binary to bcd converter double html A Greensted LCD Driver Module for driving HD44780 Controller June 2007 available at http www repairfaq org filipg LINK F Tech LCD html Vallabh Srikanth Devarapalli Brian Zufelt Tutorial 13 Image Generation ISE 10 1 on the Digilent Spartan 3E board available at http www cosmiac org tutorial_ 13 html https www mosis com vendors view tsmc 035 hv Jan M Rabaey Anantha Chandrakasan Borivoje Nikolic Digital Integrated Circuits A design perspective Prentice Hall NJ 2003 pp 448 449 Tutorial 13 Image Generation ISE 10 1 on the Digilent Spartan 3E board available at http www cosmiac org tutorial 13 html Jan M Rabaey Anantha Chandrakasan Borivoje Nikolic Digital Integrated Circuits A design perspective Prentice Hall NJ 2003 pp 207 210 http www pololu com catalog product 2102 R M Glidden S C Lizotte J S Cable L W Mason C Cao Proceedings of S
43. 00 kHz and its period 1 of 2 us d ramp2 ramp3 ramp4 a me ae ae ae an ae ae e a e e a an ae am e m m a a a a an ae me a ramp1_CLK i scan_word_dac100 Write to DACs s p mie ARIAL SYSCLK DACs CS DAC CS Clk pixel o start SEND BEEN ck scanDAC B cL scan gt ISPLSCK LARA delay 1 clock i E er E E gt start fall SYSRST gt RST send DAC RST scan on status dac A not Msync SYSRST Vchip_lock_pin Figure 5 18 Block diagram of DAC programming function The start pulse coming from the Ramp 1 counter clock activates the scanning of the 100 bit word to the SPI MOSI node command input The one clock delay block allows the Ramp 1 counter to update its output before the scan word block begins reading Inside the scan word block another 100 bit fixed word is read to generate the chip select signal which starts the conversion process on DAC In addition the scan word block controls the system clock to the DAC avoiding pulses and noise generation when no conversion is necessary and generates a status pulse The DAC CLR signal is the active low asynchronous reset input to the DAC 82 5 17 Row0_UNM backup plan As described in Section 3 10 considering the failure of the photodiodes response the first row was designed without photodiodes presenting only the analog memory that could maintain different voltage values o
44. 3 23 Output buffer design a and highlighting b 3 12 Interconnection between blocks After the design of unit cell photodiode test structures FPA level shifters bias mirror and output buffer it was necessary to interconnect the power grid and input output signals to external pads on the ring pad Horizontal and vertical signal buses were designed to distribute these signals between columns and rows as well as to the pads 37 Rete F es a6 i H im MEM A nnl Figure 3 24 Top and bottom interconnection between blocks two images mounted Highlighting of interconnection between blocks helps to identify open short circuits as well as the different signals distribution Figure 3 25 Figure 3 25 Highlighting of interconnection between blocks 38 3 13 FPA simulation Because of the large number of unit cells on the FPA the simulation could take days and could present a similar response on thousands of pixels and it would be difficult to trace this large number of signals and to analyze the process Likewise to build a smaller FPA design with only the unit cells could not detect connection problems on signal distribution lines of the final chip design Consecutively a 4 x 4 matrix of sensors positioned only on the corners of the 98 x 98 matrix was designed for the simulation of the FPA Figure 3 26 keeping the signal distribution blocks and using new dummy designed cells D 39 O38 39 GN 3
45. 6 22 A 2 x 2 matrix of individual unit cells with external column row selectors A ESTA After the wire bonding on the carrier and the elaboration of the interconnection diagram a solution was found for the level shifter problem and the chip responded discontinuing this phase before the VHDL code could be elaborated Nevertheless the 2 x 2 matrix remains useful as intended with each side of the carrier having one unit cell for individual characterization or use Furthermore access to the interconnections of columns and rows offers conditions for specific voltage measurements and analysis which does not happen with the full FPA 106 6 14 Problema solucionado Concentrating analysis efforts on the suspect circuit design the column selector level shifter a discrepancy was observed on the sizes of transistors on the input of the level shifter and on the output of the column selector Figure 6 23 These transistors present 20 um and 0 9 um respectively which represents a ratio of fan out of 22 2 of size and of capacitance In addition the smaller transistor works at low voltage 3 3 V and the larger transistor operates at 15 V presenting a gate source threshold voltage of up to 2 V Figure 6 23 Fan out of the low voltage FF output to the high voltage level shifter input For minimum delay it is recommended 48 that the design ratio between chain transistors should be four The operational column select level
46. A 32 3 8 Row columrmi Selector rnea nea e o on ae ee ne vete v eo eet idad 33 3 9 OUTTA E Ro ad U tuse Sepa Ede uS tate 35 3 10 Row0 UNM aS 19 x 5 MA aaa 35 3 11 COUIED UL DIBIEO Tiesto kdb revere E attested bea vers ENEE de ae saunas 37 3 12 Interconnection between DIOGKS aiii iii 37 3 13 FPA Si AL OD POR OC CONO On eoa Tu dU Med eo esa HERR ORE IDE dan 39 3 14 Fatture Praia 40 3 15 Ding a ei cas ener ee ino Ue nce errr E edis E ene SUE D tere UE 41 Chapter 4 Testsystem hard w are sia lic ate 43 4 1 PROA DO rta scia doo 43 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 10 1 4 10 2 4 10 3 4 11 4 17 4 12 1 4 12 2 4 12 3 4 12 4 4 12 5 Power supply and safety interlock ooooccoccconnnnoonnoooononcnnncnccnnnnnnnos 44 Digital puts OPUS ia 45 Disital output Tey els AIG CL it 47 VS CONICS WILE I dd io 47 PA H 48 Analog output level shifter oocccccccocononnnonononoooononnnnncncnnnnnnnnnonnnnnnnnos 50 v It INSURERS A E RN D P 51 VOA OUDOT aseko aise a ios 51 System Imerconne CHONG ardid 53 OLN package PUB sindicaci n 53 E A 54 baisser ada 55 o A eres 57 Infrastructure Hataw edi S S 58 OSCOS CODE pcs 58 PODS o E nee nee eee eee 58 Video camera dnd SONWALE statistics 59 SOUP COIS AS IES WINNIE aseene eee ii ici 60 E E PP ALEN AEI ASAE A EREE AEE AE 6l X1 A A o nn
47. CD for adjustment of parameters and for internal selection of test circuits via a context menu In addition the main board provides 12 high speed IOs of which four are used as output for the frame grabber synchronization signals and eight are used as extra input for testing Rotary Push Button Switch ROT A K18 requires an internal pull up ROT B G18 requires an internal pull up BTN NORTH V4 ROT Center V16 requires an internal pull down Spartan 3E Development Board e c Li o ct m E ES VERSER i RE d Fi iie 16 Ea z 4 4 il LoS Pa iF pps Tw E a 3 y Y CENE X Te no oo 3SPARTAN 3 ish C UM ah ME TES A Nemes fem a WA Mee E Ln i ww m XCISIGOOE EKIB cine dd 3 Ure 2 4 CGI E l zr TITHIT oo ez MONS RPK RESETICKLPD BTN_WEST D18 BTN_SOUTH K17 BTN_EAST H13 a b c Figure 4 4 Push buttons and rotary switch a main board b and slide switches c 18 45 On the module interface board MIB in use are 22 output control signals two digital inputs and eight inputs for testing push buttons and slide switches comprising 32 IOs External dedicated modules Pmod were used as input for push buttons slide switches and rotary switches as shown in Figure 4 5 In addition all outputs have Pmod buffered LEDs Figure 4 6 which help the visualization of events of low frequency such as the frame signal a
48. Each counter generates internally a three character string for displaying the correlated values on the LCD screen based on a double dabble algorithm 42 which converts the 10 bit binary signal 0 to 1 023 to a 12 bit binary coded decimal BCD consisting of three BCD digits 000 to 999 5 3 Multiplexer One basic and simple structure used extensively on different applications is the multiplexer the output of which is selected by an up down counter The first application and most simple version is contained in one up down counter its output selects a high 68 level to enable one of the parameter counters as illustrated in Figure 5 4 6587 99999 eee 6588 mmm COL sel outMUX COL sel 6589 6590 counter COL sei outMUX entity work counter beh 6591 Jport map THERE gt HERE 3 6592 DAA EA EA AE C AAA 6593 Counter CLK gt COUNTER CLK ra 6594 update gt update param 6595 reset gt SYSRST or eastBTonSETUP manual update O 6596 load gt low_level pr 6597 counter en gt sel 47 lt lt selection on screen 6598 up down gt ROT1 left gt 6599 STEP gt 1 6600 min val gt min COL sel outMUX constants 1 6601 initial value gt INI COL sel outMUX Signal for setupMUX 6602 max val gt max COL sel outMUX constants 64 END l l 6604 xc CAES ME 6605 Tr
49. Figure 4 2 Spartan 3E 1600 board a 18 and FX2 module interface board b 20 4 2 Power supply and safety interlock The main power supply with an adjustable current limit was set to 18 V and supplies several LM317 21 for regulation of 15 V 7 5 V 5 V 3 3 V for which typical application circuit and features are shown in Figure 4 3 Also 5 V was supplied An intermittent beep circuit on the power supply and blinking LEDs were implemented to 44 remember to turn off the power supply when no more tests were necessary Additionally a safety interlock circuit senses the power supply voltage sending a digital signal to the FPGA board as a feedback for the software to turn off the generated signals avoiding control signals on test circuit when the power supply is off tVourt 1 25V t J lapu Ra Features Guaranteed 1 output voltage tolerance LM317A Guaranteed max 0 01 V line regulation LM317A Guaranteed max 0 3 load regulation LM1 17 Guaranteed 1 5A output current Adjustable output down to 1 2V Current limit constant with temperature P Product Enhancement tested 80 dB ripple rejection Output is short circuit protected b Figure 4 3 LM317 typical circuit application a and regulation features b 4 3 Digital inputs outputs The main board has four slide switches five push buttons one rotary switch as illustrated in Figure 4 4 which are used for system reset for selection of screens on L
50. Fsync wait and the Msync wait the relationship between the signals for this process is illustrated in Figure 5 12 Msync HI Row time Msync HI x INTegration Msync_LO mi Lj v m LI z REF VOLTAGE CLAMP 2 Figure 5 12 Timing diagram and relationship of variables for frame time calculation 11 5 13 Pulse train Once the 99 output of the column selector activates an external analog input to the output buffer via the multiplexer a specific number of clock pulses is necessary to reach this column The creative solution was to use the same pulse generator block with its high level phase containing 99 pulses or any number of columns while controlling an AND gate that switches the pixel clock signal to the output With adequate adaptations the number of pulses could be adjusted as a parameter on both column or row pulse train counters and any pixel now can be reached in the matrix for individual verification Figure 5 13 shows the start signal the column row reset signal necessary on start of counting the AND gate output as a status signal and the train of pulses that goes to the column selector clock on FPA Tekfun 5 C sov oe Y 201v D15 DO 06 32 13 Figure 5 13 Timing diagram of a pulse train for selection of Column 99 5 14 Scan word Once the patterns are stored in a vector or string format 1t is necessary to adopt a parallel to se
51. Glauco Rogerio Cugler Fiorante Candidate Electrical and Computer Engineering Department This dissertation 1s approved and it is acceptable in quality and form for publication Approved by the Dissertation Committee Dr Sanjay Krishna Chairperson Dr Payman Zarkesh Ha Dr Francisco Javier Ramirez Fernandez Dr Keith A Lidke Dr Sang Han SPATIO TEMPORAL CIRCUITS FOR IMAGING SENSORS by GLAUCO ROGERIO CUGLER FIORANTE B S Electrical Engineering Universidade Santa Cecilia 1995 M S Electrical Engineering Universidade de Sao Paulo 2004 DISSERTATION Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy Engineering The University of New Mexico Albuquerque New Mexico July 2013 2013 Glauco Rogerio Cugler Fiorante 111 DEDICATION Carmem Barduco Cugler Fiorante in memoriam Joao Batista de Oliveira Fiorante Elaine Cristina Silva Cugler Fiorante and Nathaly Ann Silva Cugler Fiorante who in addition to their long names had in common the sacrifice of moving through life without a husband father and son at their side ACKNOWLEDGMENTS First of all I am very thankful to God It is only because of His love and grace that my knowledge experience and capacity met the opportunity and approval for a successful project I thank my advisor professor Sanjay Krishna for his support guidance and freedom offered during my research
52. PIE 1684 1992 pp 2 39 114
53. S UNITCELL a b Figure 6 2 The 30 x 30 um pixel layout and the test photodiode on pitch of 40 x 40 um a from the layout of the chip b 6 1 Photodiode Figure 6 3 a shows the response of the adopted unit cell photodiode PD structure to procedure defined units pdu of illumination where one can note not only the photocurrent response to the illumination level but the desired variation of photocurrent related with the applied bias 1 E 10 1 E 11 1 E 06 1 E 07 z o 1 E 08 2 i 3 5 1 E 09 9 E 6 9 S E E 3 1 E 12 2 5 5 7 5 Reverse BIAS V a b Figure 6 3 n n well p sub photodiode response a and probing for the guard ring type b 91 Initial comparative measurements of the four types of photodiode test structures are shown in Table 6 2 As expected the covered photodiode shows the smaller response But and unexpected the value of the current was nearly as high as that of the reference structure As expected the photodiode with a guard ring showed a lower response versus the Unit Cell photodiode due to the grounding effect Comparing these values with the more detailed characterization of Figure 6 3 one could conclude that the very high illumination level makes the covered photodiode respond to the high level of scattering The photodiode connected to the PAD showed an extremely high abnormal current value Suspecting pad leakage or light response the se
54. W SEL A TEETE ATL IT nmm a mum de y SW INT id cece gt VDETCOM ROW SELECTOR RS _DIGITAL ANALOG lt s X WIDTH COLUMN SELECTOR CS X CO LINE SYNC WIDTH CTRL PIXEL CLOCK Figure 2 1 Circuit of ITP ROIC unit cell and peripheral circuit block diagram exerco PURA Opps WIDTH_CTRE ARENA ASAS RESET PL o SW INT WRITE FRAME N integration time WRITE FRAME N 1 RD WR X INT READ FRAME N BIAS 1 gt BIAS 2 gt BIAS 3 gt BIAS 4 al eo e s of 9 sr ai PIXEL 1 Output SH PIXEL BIAS V REF SW HOLD IREAD FRAME N 1 PIXEL SELECTION SW BIAS Figure 2 2 Timing diagram of main signals on ITP ROIC 17 Turning on the reference switch SW REF the external reference voltage V REF which is O volts will be transferred to C MEM and reflected over all of the detectors resulting only in the integrated voltage in the opamp output Then the SW HOLD memorizes the value of the integrated voltage on C HOLD to be read in the next frame The timing of one line scan is used as the minimum integration time allowing 1f needed synchronization and visualization of the specific unit cell integration values on these hidden lines on the frame grabber Also the line scan time 1 e number of clock pulses is the step of integration time parameter The limitation of maximum integration time probab
55. W hold ROW PT Lsync FG Table 5 1 Digital outputs related internal signal names and pulse generated signals bold 5 1 Digital inputs conforming It was necessary to use a routine for debouncing the signal from the push buttons slide switches and rotary switches avoiding in this way unintended signals or incorrect counts from the mechanical bouncing of the contact on these devices This function starts to count the clock pulses when the input changes its state and only after a predetermined number of clock pulses and if the input keeps its state the output will respond 65 A toggle function was developed to allow the use of one push button as a selective switch operating similarly to the slide switch The toggle function 1s a D type flip flop with an inverted output feed backed to the data input In this way each pulse on the clock input inverts the output This block has an option to bypass the clock pulse returning the push button to its original functionality Also another input disables the toggle function keeping the last state as a memory if necessary O SS toggle 0 i o 0 q next o qreg D 5 Q 0 0 1 Do o gt o __ 0 0 RQ 1 0 out T or D 8 A GND input Q direct Q i Q i reset a 3 T 3 2 1 o 2 0 n
56. adapter for the LCC socket to fit on it This is necessary once It should be mentioned however that silicon based MOSFETs show a number of operational difficulties conditioned by the very low temperatures required for the readout circuits for these detectors They are related to freeze out of thermally generated charge carriers making the 109 circuits unstable increasing noise and causing signal hysteresis They are described in details by Glidden et al 50 e Power supplies with a shutdown control pin 49 to turn off its output are presented as a better option to manual mechanical switches in which current passing through could generate heat losses noise or oscillations of voltage of the test system e Implementation of a DAC with high speed conversion output for fixed pattern noise FPN correction via BIAS compensation is necessary e An external DAC block with better settling time less than 0 1 us could be defined to offer a higher pixel clock rate to offer a faster individual pixel biasing for the test system and consequently a better FPS rate e An specific PCB containing the electronic circuits analog and digital level shifters input output analog buffers power supplies and current bias generation for interface between the FPGA board and the carrier PCB can offer more stable and reliable interconnections reducing the noise facilitating interconnections for new testing setups 7 2 3 Software
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58. and specificly designed PCB allowed a flexible quick safe practical way to access any test structures inside the chip increasing the number of test structures by chip 6 9 DAC bias and ramp generator The DAC software block was successfully able to create one important feature of the test system the bias voltage generation for each pixel on its related selection and writing time window In addition a triggered pulse with controlled parameters minimum voltage maximum voltage and step size clock division was generated the features of which permit the clock feedthrough characterization via a gate voltage slew rate control Figure 6 15 100 HE gliaht lt dirgv bias gt dq yv zero lt gt W ictri_width_out lt gt EL aux signale O gt gt Wirow rst AA row _clk_pt M icol clk pt Mco rst 2 00ms 500kS s Aux X 20 40 96 10k points 4 00mV D15 DO 29 Jan 2013 Timing Resolution 2 00s 21 06 58 EP Fise Time 126 0jus Low signal amplitude Figure 6 15 Integration switch gate voltage waveform with controlled parameters The programming time of the 4 output DAC initially was established on a minimum of 2 us but unfortunately the settling time of the DAC reached a minimum of 3 us on measurements although 1t could reach as high as 10 us by the datasheet This settling time defines the minimum period for the pixel clock in the actual system 1f using the onboard DAC for biasing and ideally
59. and versatile tool for signal generation and FPA testing and characterization It presents characteristics that facilitate the operation offer flexibility on connection and measurement of all signals and improve the visual analysis of waveforms Its main features are 98 The online autonomous individual adjustment via software of signal parameters Figure 6 13 Phase and size adjustable pulse generation for testing of specific blocks with multiple digital and analog inputs e Synchronized ramp signal generation for analog response and clock feedthrough analysis Repetitive pulse train for access to a specific pixel of the matrix for characterization and testing of related analog circuitries e Differentiated frame sync line sync pixel clock and clamp signals for synchronization of an external frame grabber Generation of a 2D image pattern of individual biased pixels Figure 6 14 defined on code compilation Generation of a biased region of interest based on vertical horizontal and square shapes with adjustable size and position at pixel size resolution Figure 5 25 Figure 6 13 Online individual adjustment of signal parameters 99 CHTM pec E UNM ECE CHTM Figure 6 14 2D image pattern applied to BIAS and acquired from ITP ROIC 6 8 PCB and interconnections The adopted procedure for wire bonding the dies on an open cavity LCC carrier together with the ZIF socket
60. angular waveform in the V ZERO pin with the SW ZERO enabled Independent of SW INT and SW Hold after each pixel 1s selected by the column and row selectors the respective voltage should appear on V BIAS which did not occur Furthermore keeping SW INT and SW Hold on each unit cell should work as a buffer transferring 103 the V ZERO voltage to the output which did not happen Because the column selector was working and the row selector is an exact copy of it it was suspected that the row colum level shifter was defective The level shifter for the column selector is different from the row selector increasing the probability of a defect in that circuit In addition if no row is selected the backup plan of Row0 UNM would not work In an attempt to recover chip functionality at least for one row selection the use of the focused ion beam FIB was planned Figure 6 19 The chip has available two floating internal pads that could be connected to row select and row select bar of Row 97 after cutting the metal connection between the level shifter and unit cells of that row To locate the points to be cut etched filled and connected the design s layout was measured in the same way the SEM image Figure 6 20 Unfortunately the FIB process although able to execute the cutting filling and metal depositing destroyed the silicon structure near the processed points which short circuited the access points to the ground Figure 6 21 sh
61. as a function of the applied bias From these measurements one can observe the multicolor capability of the DWELL detector structure 8 The DWELL 1781 structure was grown by molecular beam epitaxy MBE and fabricated using a standard lithography technique in a class 100 clean room environment The growth conditions of DWELL 1781 and its bias dependent spectral response are shown in Figure 1 2 b GaAs n 2 x 1018 cm 0 2 um AlGaAs 500 a GaAs 30A o a b Figure 1 2 Growth schematic a and bias dependent spectral response at 30K b 4 5 6 7 8 39 1011 12 3 s Y c O a Y _ L 4 o a Un Wavelength um of DWELL 1781 8 1 3 Photodiode To demonstrate the functionality of the new ITP ROIC without the direct implementation of the DWELL FPA a CMOS compatible photodiode structure needed to be chosen for implementation A detailed comparative study of three photodiode structures in standard n well CMOS process can be found in 9 but is summarized as follows ge cm mpm a n well n well p sub p sub p sub a b c Figure 1 3 Schematic drawings of three CMOS photodiode structures 9 Figure 1 3 a shows the most compact structure related to the design rules and the most straightforward structure used to make a photodiode The n p sub or NP Psub is considered the reference design The highly doped n region presents a sma
62. bias voltage and the other terminal is connected to the ROIC input via indium bumps in a hybrid process know as flip chip Figure 1 6 Illumination Detector Array Multiplexer gt output pads Indium A interconnects Silicon ROIC read out array Figure 1 6 FPA hybridized over a ROIC 11 1 5 Motivation There is an increasing demand on next generation infrared imagers to bring enhanced functionality to the pixel Such functionality could include control over the color polarization and dynamic range of the sensor enabling several applications and leading to the development of an infrared retina 7 An infrared retina 1s defined as an IR FPA that works similarly to the human eye to receive different spectral responses colors on different spatial pixels rods and cones but without the limitation of a fixed spectral response per pixel These developments at the sensor level demand advanced spatio temporal circuitry at the pixel level One approach to realize an infrared retina involves the use of spectrally adaptive sensors that are bias tunable by exploiting the quantum confined Stark effect QCSE in the quantum dots in a well DWELL heterostructure 12 Combined with a projection algorithm 8 the QCSE can obtain a continuously tunable detector with overlapping wavelength bands that can be used for target recognition Only one focal plane array FPA could be used to realize multicolor images reducing the prer
63. cause of its high linearity detector bias stability and its capability of applying positive and negative biases to the detector As the column and row selectors receive the reset and clock pulses to activate the output of a specific pixel the internal address selector circuitry represented by the AND gate in Figure 2 1 activates the bias switch SW BIAS that transfers the desired external bias voltage V BIAS to the analog memory capacitor C MEM After the initial reset and on the start of a frame the integration switch SW INT is turned on and therefore the opamp operates as a buffer reflecting the voltage on C MEM to the detector through SW INT The sample and hold switch SW HOLD is kept off once the sweeping selection of unit cells for writing bias on each C MEM in this frame is simultaneously reading the value on the hold capacitor C HOLD from the previous frame At the end of the writing reading process the integration switch 1s opened and the reverse bias detector current charges the C INT proportional to the applied bias and time of integration During the integration time both RS and CS are reset avoiding any SW BIAS to be activated and or avoiding any change in the bias and reducing any noise generated by the clock pixels scanning After the desired integration time every C INT acquires the original bias added with the integration value 16 SW HOLD ep 10 1 BIAS MIRROR COL_OUT RO
64. characterization processes 59 Figure 4 22 Grabee software for image and video acquiring from video camera on probe station 4 12 4 Source measure unit A current voltage characteristic or I V curve current voltage curve is a relationship typically represented as a chart or graph between the electric current through a circuit device or material and the corresponding voltage or potential difference across it 39 It is essential to know the operational specifications of the finger CMOS diodes on internal pads which are designed to protect the chip against electrostatic discharge ESD The intent is to recognize the functionality of the finger CMOS diodes and their influence on input output signals This allows one to determine its leakage current its reverse breakdown voltage its direct threshold voltage and its correlated draw current For this measurement Keithley 236 40 was used as an I V curve device and LabView was used as a software interface to control its parameters via the IEEE 488 interface Figure 4 23 shows the circuit diagram of this measurement procedure and Figure 4 24 shows the parameters adjust screen as well as the block diagram which was adapted to allow the adjustment of output current up to 100 mA 60 WARNING To avoid electric shock toat fixture chassis must be connoctad to a safety earth ground Figure 5 Local Sense Connections Using Model 8006 Fixt Test ure Ele Edt Y
65. d offering up to 16 inputs for optional configurations and or parallel operation of push buttons slide switches and rotary switches Figure 4 1 Actual version of the test and characterization system hardware 4 1 FPGA board Several analog and digital signals are necessary for generation so that the ITP ROIC can be tested For the hardware main control system a MicroBlaze Development Kit Spartan 3S1600E from Xilinx 18 was chosen because of its low cost 19 stand alone characteristic key features for signals generation image acquisition and storage as well as for processing and display Figure 4 2 a It presents 1 600k gate Spartan 3E SOMHz 43 of clock generation 64 Mbyte x 16 bits DDR SDRAM 16 Mbits SPI serial Flash 4 outputs serial peripheral interface based SPI 12 bits digital to analog converter DAC 2 input SPI based 14 bits 1 5 Mega samples per second MSPS analog to digital converter ADC 2 lines x 16 characters liquid crystal display LCD display VGA display port 10 100 Ethernet PHY two 9 pins RS 232 ports PS 2 keyboard 10 switches 8 LEDs 12 digital high speed IO pins among others features This board also has a 100 pin Hirose FX2 connector in which an FX2 module interface board MIB was connected 20 expanding the system with more 32 high speed IO pins Figure 4 16 b LR Ta fy xn mana TE is SPARTAN pis us ger S Attalo dd a wet AN DIGICENT BEYOND THEORY b
66. d in general applications is presented as an advantage in the bias dependent unit Dark current Phot t otodiode type mA cm nt p sub cell n well p sub pt n well p sub Table 1 1 Dark current on the three types of photodiode 9 It is desired for the proof of concept of the proposed ITP ROIC to have not only the photodiode response to the incident light but also a different gain on response in relation to the applied reverse bias This requirement is confirmed by 10 which presents a 5 variation of the responsivity versus the applied reverse bias Figure 1 5 a in an n n well p sub photodiode of 50 x 50 um Figure 1 5 b a device similar to the one adopted in this project Responsivity A W 0 2 4 6 8 10 Reverse Bias V a b Figure 1 5 Spectral circuit independent sensitivities a and device structure b 10 1 4 Focal plane array and readout integrated circuit A focal plane array FPA is an image device consisting of an array of pixels sensitive to electromagnetic radiation 1 e photodiodes and DWELL at the focal plane of a lens most commonly for imaging purposes A readout integrated circuit ROIC 1s a silicon based chip that integrates the photocurrent generated by the sensors during a defined period of time converting this charge in voltage for multiplexing to the output of the chip Generally each sensor of the FPA has one terminal connected to a common point with a defined
67. data lines can be observed 14 One can observe in Figure 1 7 c the spectral response control in the visible spectrum while the bias 1s changed only at the frame level Figure 1 7 a b not at the pixel level in which an RGB pixel could have its color defined only by its bias not by its specific 8 physical chemical constitution The target wavelength depends on the detector used For example the target wavelength for DWELL 1s 3 um to 12 um and for p 1 n 1 p is 0 4 um to 0 75 um Although several commercial ROICs present the option of dual polarity 15 conversely it is a global pixel bias presents a small input dynamic range of up to 3 V and presents greater pixel pitch of 80 um TFT Array split in 2 Gate Driver l Gate Driver pcm ur Figure 1 8 CTIA internal dynamic range hole and electron collection a 15 Example of flat panel array configuration and TFT interface to the ROIC input b 15 Unlike currently available commercial ROICs Figure 1 9 a that apply the same constant bias across all pixels in a limited polarity selection and voltage range in this paper we demonstrate the first readout circuit capable of controlling each pixel voltage bias individually Furthermore the new ROIC is capable of applying a dual polarity and a large bias voltage to the detector devices in smaller pixel pitch We have made it possible by implementing three different but integrated blocks in each unit cel
68. devices and ESD pad test structures on top of the chip Bias transistor and poly resistor of 10 KQ ooooonnnncncccccnnnncnnnonononononncnnnnnnnnnnos 27 Photodiode design layers a cell b and its hierarchical design cells c 28 Figure 3 10 Photodiodes test structures design a highlighting b and microphotograph C REM MM UEM LU IE MEM EE IE ME EM E CLE M 29 Figure 3 11 Active pixels matrix microphotograph a and margin columns rows CONSUMOS Dai io tal 29 Figure 3 12 Layout of input bias transistor a and of output bias transistor b 30 Figure 3 13 Spice code for simulation of VSG x ID CULVE cooooocncccocococcnnnnnncnoconononnnannnnnos 30 Figure 3 14 Simulated source gate voltage versus drain current for the column bias transistors O 31 Figure 3 15 Unit cell two stage operational amplifier layout occccccccnnnnnnnmmm 32 XVI Figure 3 16 Separated unit cell test structure design a microphotograph b and SEM do me E O eke TT ENERO RT NEN 32 Figure 3 17 Spice simulation waveforms for unit cell output top and opamp output DOLO iii 33 Figure 3 18 CS 0 1 2 level shifter 1 2 left and CS 97 98 99 level shifter 97 98 99 MA dad id ia 34 Figure 3 19 Waveforms of the column selector in Spice simulation oooccnnnnnnnnnnnnnns 34 Figure 3 20 Level shifter column bias mirror selector width control and MUX layout Figure 3 21 Matrix 19 x 5
69. e dies on a 68 pins LCC package and to use sockets on specifically designed PCB for the carrier This permitted without the limitation of external pads and packages the design of a great number of internal test structures The wire bonding was executed on a semiautomatic wire bond station 55 illustrated in Figure 4 17 Figure 4 17 Semiautomatic wire bond machine Initially the backplane of the carrier that is attached to the die substrate by a conductive glue is wire bonded to a specific carrier pad Next the ground and VDDH are wire bonded as shown in Figure 4 a Finally the FPA test transistors and test photodiodes are wired as shown in Figure 4 b One can note the numbering on the backplane of the carrier for die tagging Figure 4 a c Figure 4 18 Wire bonded ground and VDD a die 10 b and die 8 c Illustrated in Figure 4 19 are the pinout of ITP ROIC FPA separated unit cell top ESD pad right side top photodiodes right side bottom and bias transistor right side center 56 PhotoD NM j Z e a ao B Row Sel px SW Hold ROW98 BAR of a ER teen ag eo nues ato E d a pu Sue m od yo a a rT ag IN MISS NNI BN i d r Soi 4 am E 7 F3 3 T i e X A J l lg M LLL 4 t E 1 pr
70. e of the FPA being 3 92 x 3 92 mm a circular light beam will be 5 5 mm in diameter with uniform distribution In the same way a 5 x 5 um photodiode of the unit cell requires a circular beam 7 um in diameter A desired beam of 5 5 mm in diameter means a magnification of 6 89 in relation to the 0 8 mm diameter of the laser Choosing the first plano convex lens with a focal distance of 25 4 mm lens 1 in Figure 4 26 and using this magnification the second plano convex lens results in a focal length of 175 mm lens 2 in Figure 4 26 Aiming to use this same optics structure to generate the 7 um and considering that a 7 um focal length lens is difficult to purchase or position a practical and creative option was to use another 175 mm focal length lens in a quick 62 release magnetic mount lens 3 in Figure 4 26 to focus the 5 6 mm diameter collimated beam at 175 mm of distance 5 5mm 0 8 I 175 mm Figure 4 26 Laser optics specifications A 30 mm cage plate structure was used to allow automatic alignment of the beam and to facilitate the alignment verification using hanging targets with a 0 9 mm pinhole Figure 4 27 shows the beam chopper intensity control optics input alignment point and lens tube for focal distance adjust of the 5 5 mm diameter beam 373737373 73 3 3 13 79 ieeeeeeeecc0 eee eee eee ee a ee ee ee ee ee ee a ee ee ee ee gee ee ee ee MMC n oc BEEN 9 959 4 OOOO ee ee
71. e reference recover the sample of the recovered voltage and to the output voltage transferring to the column multiplex input The analog functions memorize a pixel specific voltage bias transfer this voltage bias to the coupled sensor integrate the photocurrent generated by the sensor convert this charge to voltage recover a reference voltage level and hold the processed voltage for external reading The second contribution is the unit cell layout implementation in a 2P4M 0 35 um high voltage CMOS technology which was achieved in a restrictive area of 30 x 30 um Approximately half of this area was defined for use by four essential poly poly2 layers capacitors which should have the larger area and respective capacitance possible A small area had to be defined for the VDD and GND pickup connection Nine NMOS type transistors and six PMOS type transistors of the circuit in a total of 45 terminals were necessary to be designed and interconnected with only two available metal layers to nine internal nodes and 12 external nodes Even the circuit presenting seven nodes shared between pairs of transistors of the same type the restrictive design rules added to the limitation of the number of layers for interconnection had presented a challenge for this design successfully executed after a systematic effort on devices and interconnection positioning The third contribution is the design and implementation of the ROIC itself integrated
72. elopment of this project permits improvements related to the design software and hardware of a continuing work described as follows 7 2 1 Design e The design of a new ITP ROIC version that has improved operational characteristics in the manufacturing process at MOSIS The SW BIAS will assume the function of SW REF as a result of an implemented feature on the row 108 and column selectors This also liberated an area on unit cell layout to improve the voltage swing on output The level shifter on the row selector layout was redesigned and now is similar to the one on the column selector to solve the main problem found on ITP ROIC Version 1 Individual transistors must be designed to reduce the metal 1 layer area that covers most of the actual cell Make two individual transistors one uncovered and one covered with metal 4 for comparison of the light effect Cover the entire chip with metal layers to avoid scattering and collateral light effects as had happened on this version with its exposed areas For this we need to work on metal 3 and metal 4 layers because the DRC requires a dilatation margin on metal 7 2 2 Hardware Testing and characterization of the ITP ROIC at lower temperatures are planned with a gradual reduction of its values to identify the operational range of the CMOS devices and structures at low temperature using the temperature controller on SE IR system which will need to receive a new
73. equisite for different spectral band sensors and the number of 7 connections on the same pixel This requires a wide voltage range bias and the ability to independently control the voltage bias on each pixel the characteristics of which are provided by this novelty proposed ROIC Commercially available ROICs although offering two color or dual band capability for quantum well infrared photodetectors QWIP 13 are based on dual stacked sensors which need at least two contacts to the FPA Our proposed architecture reduces the number of indium bumps by 50 which requires less force during the FPA hybridization process with the ROIC Moreover the global pixel biasing in conventional ROICs does not allow advanced processing at the pixel level Dual polarity for spectral response modification Figure 1 7 also was demonstrated successfully on a p 1 n 1 p amorphous silicon image sensor in a dynamic range of 2 4 V 14 proving the demand for the design proposed in this effort amp wy 7 2 4V Bottom sensor 2 201 Vom 26 Top sensona g gm M me 1 0 gt 2 0 5 o 3 e 0 0 Wavelength nrn Figure 1 7 Images taken with the array under white light exposition and sensor bias of 2 6 V a and 2 4 V b respectively The image in b is reversed because of the different current flow direction in the detection system since the two p i n sensors have opposite orientations Some bad contacting gate and
74. er column bias mirror selector width control and MUX layout 3 10 Row0_UNM as 19 x 5 matrix Considering the low possibility of failure of the photodiode s response the first row was designed with an open switch between the photodetector and the unit cell In this way the individual pixel biasing control still could be demonstrated in a 19H x 5V image Figure 3 21 using only one row with dedicated synchronization signals Figure 3 21 Matrix 19 x 5 pixels built from Row0 UNM To prove the integration process without the internal photodiodes in this first row input nodes in Columns 97 and 98 were connected to pads in a way that external current or photocurrent could be applied Figure 3 22 Finally a comparison between unit cells with and without photodiode response could be performed with this design specification Figure 3 22 Row with photodiodes connected top without photodiode connection bottom and CTIA inverting input connected to pad orange and red 36 3 11 Output buffer The output video amplifier consists of a single stage opamp that was made as a buffer It receives the signal of each column through the switches of the columns multiplexer The output video buffer uses the high voltage VDD 7 5 V and it draws 13 uA current for its bias Figure 3 23 shows the design of the output video buffer and its highlighting for connection verification Figure
75. er connecting the three signals to the DAC output of this board 8 bits grey level 256 levels could be used in an autonomous way to display the acquired image from the FPA which means no computer no frame grabber and no third party software would be necessary to display the image and the FPGA system would be portable DB15 VGA Connector Y DB15 VGA Connector Pin 5 front view Pin 1 in 10 Figure 4 11 DB15 VGA connector and pinout 18 DB15 DES 2700 O H14 VGA RED Green 27010 O H15 VGA_GREEN 2700 w c o O G15 VGA_BLUE Horizontal Sync 82 5 Q O F15 VGA_HSYNC i 82 50 Vertical Sync o F14 VGA_VSYNC 7 GND UG257 06 01 060506 Figure 4 12 Voltage levels for VGA specification 18 E Edit Colors Basic colors EI Ge NISI miss tee n EE E i mmmmmm mmmmmu MA NM JM i BI m a E Cust r 1 EN mmiumm m m m m Figure 4 13 Generated colors with 3 bits word on VGA input 52 4 10 System interconnections Forty dies of ITP ROIC were manufactured and received from MOSIS five of which came wire bonded on a quad flat no lead QFN package of 64 pins at 0 5 mm pitch and 35 of them came on bare dies Figure 4 14 b Figure 4 14 ITP ROIC QFN package a and bare dies b 4 10 1 QFN package PCB The QFN packages were soldered on commercial PCB adapters for SMT devices 26 together with the
76. ew Project Operate Took Window Help gt amp w d 5 uo 13 aootcation Fort v Sov i Al Rights Current Limit 0 01 to 0 1 A 5o 1 Reset Kekhley 236 Tres V1 is particularly important because it resets the U1 and US status words Akemstely these error in iw the Ut and U9 status words ror ebun device di dent 7 3 Setup Star Sweep using front panel controls The user can easily change the type of sweep by replacing this J 5 J vi VE and change the front panel controls to match the new sweep or a JA Figure 4 24 NI LabView GUI for Keithley parameters adjust a and its block diagram b 4 12 5 Laser Intending to characterize the photodiodes and separated unit cell a stable well known intensity and wavelength light must be applied on a specific sensitive area Selected was the Melles Griot 05 LHP 141 Helium Neon Laser which generates a polarized light with a wavelength of 632 8 nm a beam diameter of 0 8 mm and 4 mW Figure 4 25 An electromechanical chopper with adjustable frequency from 4 Hz to 4 000 Hz was used to interfere on the laser path so that the influence of environmental response could be compensated 61 Figure 4 25 Laser setup for electro optical response characterization 4 12 6 Optics Two types of measurement using the laser were considered a uniform light distributed over all of the FPA and a light beam concentrated on the photodiode of the unit cell With the siz
77. ghter Nathaly for her four 4 years old patience lovingness and for showing me how amazing and lovely are the development of a child s mind This work was supported by Fulbright and the CAPES Foundation Ministry of Education of Brazil Cx Postal 365 Brasilia DF 70359 970 Brazil and the National Science Foundation under grant ECCS 0925757 vi SPATIO TEMPORAL CIRCUITS FOR IMAGING SENSORS by GLAUCO ROGERIO CUGLER FIORANTE B S Electrical Engineering Universidade Santa Cecilia 1995 M S Electrical Engineering Universidade de Sao Paulo 2004 Ph D Engineering University of New Mexico 2013 ABSTRACT The first and second generations of infrared detectors developed from the 1950s to the 1990s were dominated by single pixel linear and staring small format containing from 1 Kpixels to 100 Kpixels In the past decade the third generation systems presented a large format 1 Mpixels to 16 Mpixels b higher operating temperature 200 K to 250 K for MWIR and 120 K to150 K for LWIR and c multicolor operation The emphasis demanded for the next generation of devices is the incorporation of an enhanced functionality in the imagers preferably at the pixel level such as color polarization and dynamic range control leading to a dramatic reduction in the size complexity and cost of infrared imaging systems vll In this work a new 96 x 96 pixel 30 um pitch mixed signal readout integrated circuit ROIC
78. hows the highlighted connections with substrate connection rule disabled and c presents its microphotograph The photodiode from the unit cell pink highlight in Figure 3 10 b was connected to an internal pad This same test structure was designed with a cover metal layer green highlight in Figure 3 10 b to permit the analysis of the scattering effect on the unit cell surroundings For cross talk analysis between pixels one cell was designed with a guard ring around the unit cell yellow highlight in Figure 3 10 b Another photodiode structure was connected to an 28 external pad that possesses the ESD protection red highlight in Figure 3 10 b aiming the verification of the ESD diode s influence that could trigger undesired side effects such as a response to light or leakage a b c Figure 3 10 Photodiodes test structures design a highlighting b and microphotograph c A matrix of 98H x 97V pixels utilizing these photodiodes constitutes the FPA The first and last columns together with the last rows were covered with metal layer 4 M4 which resulted in a 96 x 96 active pixel FPA Figure 3 11 In this way the response from lateral scattering on the covered photodiode could be considered to compensate other s pixel s response a b Figure 3 11 Active pixels matrix microphotograph a and margin columns rows covering b 29 3 5 Current mirror Each column of the FPA requires a c
79. igned Don t Care DATA COMMAND Table 1 as ADDRESS COMMAND c3 c2 C1 C0 0 0 0 0 Write to Input Register n 0 0 0 1 Update Power Up DAC Register n 0 0 1 O Write to Input Register n Update Power Up All n 0 0 1 1 Write to and Update Power Up n 0 1 0 0O Power Downn 1 1 1 1 No Operation c SPI Communications Protocol to LTC2624 DAC Figure 4 9 DAC block diagram a analog level adapter b and DAC serial coding c 18 The DAC presents a word depth of 12 bits which means 4 096 levels of 805 664 uV over the 3 3 V end of scale Seeking a match of numbers in the simplest way without losing resolution a counter 0 to 3 000 was defined instead of a counter 0 to 4 095 on a voltage range of 15 V resulting in 5 mV of resolution per step 0 033 This end of counting number 3 000 generates 2 416992 V on DAC output and required a gain of 6 206060 for the operational amplifier On the other hand it was necessary to match the pixel frequency and correlated bias writing frequency with the necessary number of clock pulses to program the serial DAC The serial DAC needs a minimum of 24 clock pulses to write the command the address and the value into one converter So it was decided to 49 use 100 clock pulses to program the four DACs at the maximum frequency of 50 MHz resulting in 2 us of resolution conversion time meaning 500 kHz of pixel clock For 10 000 pixels near 98 x 98 the minimum time for wr
80. igure 6 9 for the FPA reading dirdv 2ero gt aux 2 lt gt diy v 2ero lt gt Wdaux 2 lt gt dirgaux signal gt see Sf ee a ens deem 200s 5 00MS s Aux Y 40 10 96 10k points 1 86 V y D15 DO 8 Feb 2013 Timing Resolution 200ns 19 48 57 th n mn tm Lair wal te Figure 6 9 Integration with 2 biases during sweeping in one row 4 combined images Following adequate signals generation connection and synchronization the ITP ROIC was able to reset bias integrate reference hold and transfer the acquired image to the frame grabber Figure 6 10 shows the main digital signals detaching the analog signals BIAS top the ITP ROIC output middle and the video signal bottom Tek fun sw zro U est Int sw _ hold 33 Lsync Hsvnc row rst fsy Trow clk Ley eol clk px ck nrol rst Lsy _rtliaht LsvFG2 v bias cn eros nc AUX 2 tum Inaux signal gt INES nc Vsync Bii manual Video ae 100v D15 D0O Ue 100v Ub 0 0 aF Timing Resolution 20 0jus hig SO 0kS s Aux X 10k points 1 80 V 2 6 May 2013 17 15 26 20 0ms ui 12 95 Width 5 94ms Figure 6 10 Waveforms of generated digital signals and analog measurements The main individual pixel biasing feature of the ITP ROIC controlled by the FPGA based test system is presented in Figure 6 11 a to f A test image pattern was elaborated and printed presenti
81. ired waveforms configuration and parameter values were reached for a specific characterization the demand for saving these values in a setup option for replication of the experience was noticed In this first version the new values are defined in a parallel multiplexer purple trapezoid shape in Figure 5 11 on the main program and are compiled the development of which required less effort and time than developing a FLASH memory access block to save these parameters 5 10 Output control Seeking more flexibility of operation and increased power of analysis and also to avoid additional hardware for the limited number of IO pins each pulse output could be turned on off or inverted by software in the related parameter screen A multiplexer was implemented for these functions Figure 5 11 and to offer easier access to any internal 75 signals which could be visualized by the 16 channel oscilloscope without changing the position of the probe VH_light_ctrl H test line V test line scan on status dac DAC CS SPI SCK SPI MOSI clk_dacs clk_dac_25 COL_reset_M_Fsync COL_clk_syn ROW reset M Fsync ROW clk syn ctrl width Lsync Fsync Msync and clk2 4 8 and cik8 and clk4 and clk2 and CLK pixel LIGHT 0 off 17on JL INI_light_outMUX 7 A AE light outMUX ROT1 Figure 5 11 Block diagram of output control with setup multiplexer 5 11 SYNC to oscilloscope One output
82. it should be 0 us ctrl width out lt gt EXiaux 2 lt gt Wt sw_hold 3 2v Loi out c Io 2 00jus 500MS s Aux A 20 20 96 10k points 1 86 V LET Timing Resolution 2 00ns TT ED High 4 30 Y 21 38 45 Period 4 160jus Figure 6 16 Settling time of DAC output voltage 4 16 us pixel clock 101 This means a maximum clock frequency of 333 kHz and 30 ms necessary to define the bias on all 10 000 pixels Adding 245 ms of maximum adopted integration time the frame time will be 275 ms resulting in a minimum of 3 63 FPS This value is not so different from the planned 3 78 FPS pixel clock of 2 us showing that the integration time is the main factor that defines the FPS rate Again this is a limitation only for the onboard DAC in defining the individual bias with the high resolution of 5 mV 6 10 Clock feedthrough When testing the separated unit cell an offset was observed in the integration signal Figure 6 17 a likely due to the charge injection via the gate source capacitance which resulted from the high voltage variation that occurs in a short time clock feedthrough Controlling the slew rate of the gate voltage reduced the initial voltage differential but as shown in Figure 6 17 b an integration of this charge still occurs over time More tests are planned with the adoption of a DAC with better features with the characterization of one cell inside the FPA matrix and with an improved design for
83. ital inputs two analog inputs two biases one output and access to photodiode and opamp output circuit nodes Seeking to acquire experience with IC repair fuse for etching and jump for metal deposition test designs were implemented on key lines using the focused ion beam FIB tool The windows on the silicon nitride layer of these structures can be seen in Figure 3 16 c by the scanning electron microscope SEM a b Figure 3 16 Separated unit cell test structure design a microphotograph b and SEM c 32 Figure 3 17 illustrates the Spice simulation of the unit cell working as a buffer with measurements on opamp output and unit cell output for a complete input voltage swing of 15 V to substrate One can note the unit cell minimum output voltage of 4 V and maximum of 15 V but due to the 3 5 V threshold voltage of the integration transistor as the output of the opamp reaches 11 5 V the integration transistor 1s turned off opening the feedback circuit and saturating the opamp output Tanner T Spice 15 16 Users Glauco Documents 0 New Mexico 0 UNM 0 PhD 3 Lab 00 Projects 00 Glauco ibROIC ibROIC8 second chance Simulations Extracted G34 ib_test_struct_AOP_with M7_M1M2 spc 00 26 05 09 29 12 PIN AOP IN pos V PIN AOP OUT V output colum V output colum VSS V 20 00m Seconds Figure 3 17 Spice simulation waveforms for unit cell output top and opamp output bottom 3 8 Row column selector The row and
84. iting all biases is 20 ms Considering the maximum of 245 ms of integration time the frame time is 265 ms resulting in 3 78 FPS minimum sufficient for live video testing 4 7 Analog output level shifter Similar to the DAC output signal conditioning block an analog level shifter circuit was implemented to change the output voltage range from the FPA 5 V to 12 8 V to the input voltage range of the frame grabber 0 3 V to 1 4 V Figure 4 10 illustrates this signal conditioning The start of the FPA output range is subtracted then a gain adjust is applied to match the voltage ranges and finally a start of scale value is added to adjust the black level on the frame grabber Voltage range OUTPUT ZERO 4 ADJUST INPUT ZERO ADJUST Y 1 GAIN ADJUST FPA to frame grabber Figure 4 10 Analog level shifting illustration This interface permitted a basic and quick calibration necessary to achieve a better contrast response on the acquired images at local illumination Using V BIAS 2 5 V for all pixels the lenses are covered to create a dark image and to adjust the zeros on both interface and frame grabber With a white carton positioned at a focal point of 50 approximaly 50 cm the span gain is adjusted for the maximum reflected light from the diffuse incandescent illumination 4 8 Signal buffer TL082 opamp 25 has been used as a buffer to increase the impedance of oscilloscope probe fro
85. l Figure 1 9 b including analog memory capacitor 1 e sample and hold capacitor address selector and reference recover circuitries e FIXED BIAS e SPATIO TEMPORAL BIAS e FIXED POLARITY PER FRAME e BIDIRECTIONAL PER PIXEL e LOW VOLTAGE RANGE BIAS e WIDE VOLTAGE RANGE BIAS Iph Vph J FIXED BIAS REF BIAS a b Figure 1 9 Typical a unit cell and new ITP ROIC b unit cell 1 6 Approach A typical ROIC unit cell consists of a photocurrent to voltage integrator Figure 1 9 a where the same bias value is presented in all pixels of the detector arrays during each frame The bias 1s applied with respect to a detector common DC node generally the backplane of the FPA After the integration time the value is stored in a sample and hold S amp H block keeping this value for external reading during the sweeping of all pixel addresses This is known as integrate then read frame time process In contrast our new approach presents an analog memory for each pixel and an address selector to synchronize the external desired bias to the pixel Figure 1 9 b This memory maintains the bias voltage during the integration time as well as during the S amp H readout processing time which is utilized to write the necessary individual bias for the next integration frame In this way we have different pixel biasing spatial bias inside each frame time 10 temporal bias This required an implemented voltage reference resto
86. licing of binary image pattern for concatenation and definition of code 84 Figure 5 22 Constant vector components of binary image pattern occccccccccnnnnnnnnnnnnnnnnno 85 Figure 5 23 Image pattern scanner for binary bias generatl0N oooccnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 85 Figure 5 24 Positioning and sizing of vertical horizontal and squared ROI windows 86 Figure 5 25 Positioning and sizing of vertical horizontal and squared ROI windows 86 Figure 5 26 VGA control timing 44 occccccccccnnnnnononnononnnnnnnnnnnnnnnnnnnnnnonononnnnnnnnnos 87 Figure 5 27 Internal signal connected to in out port on code sss 88 Figure 5 28 Port defined with the physical connector name on the board 88 Figure 5 29 Board connector name attributed to FPGA pinout sss 88 Figure 6 1 Microphotograph of test chip cccccccccnnncnnnnnnnnononononnnnnnnnnnnnnnnnnnnnnonononnnananons 89 Figure 6 2 The 30 x 30 um pixel layout and the test photodiode on pitch of 40 x 40 um a Trom the layout of the chip A e da el 91 Figure 6 3 n n well p sub photodiode response a and probing for the guard ring type Go E OO PI A e a ene Ceram 91 Figure 6 4 Poly resistor test structure of 10 kQ a and of 320 KQ b 93 Figure 6 5 Current mirror transistor sizing relationship a and measurement b 93 Figure 6 6 Column selector
87. ll depletion region width which leads to low collection efficiency Figure 1 3 b presents the lightly doped n well diffusion to create a pn junction in the p substrate This increases the depletion that combined with the deeper junction presents more efficiency at capturing long wavelength photons Figure 1 3 c adds a p or PP implant covering the n well diffusion called pinned structure that serves to create two pn junctions and two effective depletion regions larger than n well p sub intended to lead to the highest collection efficiency Figure 1 4 a shows the comparison of the spectral circuit independent sensitivities of the three photodiodes measured from a CTIA active pixel sensor APS Comparison of sensitivity noise and SNR averaged over all wavelengths for all photodiodes using data from circuit independent CTIA APS are shown in Figure 1 4 b 3 5 n p n well p p n well p EN n well p EB 5 wewp N N a o a Sensitivity Acm Wem Normalized units 0 5 400 500 600 700 800 900 A nm a b Sensitivity Noise SNR Figure 1 4 Spectral circuit independent sensitivities a and averaged sensitivity noise and SNR b of the three photodiode structures 9 The larger sensitivity of the n well p sub photodiode makes it the best option for testing our proposed new design Furthermore its larger dark current Table 1 1 although not desire
88. ly will occur when some noise leakage current matches a small photocurrent and avoids the capacitor to integrate its charge The actual value is limited in the program and when reached turns off the hold pulse The pixel clock versus the desired FPS 1s related with the integration time In the future the current of the DWELL together with the integration capacitor and voltage range on CTIA define the pixel clock and the FPS 2 1 Operational amplifier Because of the unit cell area constraint a two stage operational amplifier opamp Figure 2 3 with only seven transistors was designed and used to implement the CTIA Table 2 1 shows the opamp specifications extracted from Spice simulations The opamp supply voltage was defined as 7 5 V and its bias current as 1 uA To save space on layout the output bias current mirror transistor was implemented outside the unit cell and the input bias current was generated externally by a resistor on a 10x size mirror transistor 18 Figure 2 3 Electronic circuit of the two stage operational amplifier adopted in the unit cell Dynamic range 7 3 V to 6 7 V Offset 116 uV Power 95 9 uW ft 42 MHz Gain_dB 64 4 f3db 47 kHz Phase margin 13 4 Deg Slew rate rise 84 V us Slew rate fall 132 V us Table 2 1 Opamp specifications using Spice simulations 2 2 Unit cell The detailed electronic circuit diagram of the unit cell is shown in Figure 2 4 where
89. m 10 MQ to 1 TQ It is important to realize that the measurement of 1 V of BIAS over the photodiode of the unit cell can drain 100 nA by the normal 10 MQ of oscilloscope s input impedance As illustrated in Section 6 1 the photodiode generates only 0 1 nA of current at room illumination and in this way the oscilloscope measurement quickly saturates the CTIA integration The same 1 V over 1 TQ of the buffer drew only 1 pA which is a value 100 000 times smaller and is near the dark current of the photodiode This circuit required two separated and uninterrupted connections to the power supplies of 18 V and 5 V to allow measurement of the FPA s operational voltages which range from 0 V to 15 V 4 9 VGA output The Spartan 3E board has a DB15 video graphics array VGA standard output connector Figure 4 11 which receives signals from five output pins of the FPGA Three pins are defined for the red green and blue RGB analog signals and two have horizontal and vertical synchronization function As shown in Figure 4 12 the onboard resistors of 270 2 combined in series with the 75 termination built into the VGA cable ensure that the 3 3 V from the LVCMOS33 I O standard level generates the VGA specified 0 V to 0 7 V range With this configuration eight basic colors can be generated by the 3 bits 51 word Figure 4 13 and used for a simple graphic user interface GUI in an external monitor for parameters configuration Moreov
90. m was selected allowing a better matching of shapes Figure 3 1 Figure 3 1 Minimum feature size resolution and adopted values not to scale With the auto DRC verification disabled due to the excessive computational effort required a draft of the minimum features was necessary Figure 3 2 Values omitted due to confidentiality contract terms As a tool to help with a semiautomatic visual DRC one layer was created and the minimum distance metal 1 to metal 1 layer was drawn Working with the snap tool the design process was facilitated 27 Figure 3 2 Draft of DRCs to be considered not to scale 3 2 Interlayer connections A decision was made to create design cells with all the necessary layers for particular applications to reduce the possibility of omitting some required layer for the connection between layers to reduce the DRC error notifications and its correspondent rework and to take advantage of the hierarchical structure of design that existis in the adopted program The main cells created for interconnection layers e NP or PP to metal 1 using contact e Poly to metal 1 using contact e Metal 1 to metal 2 using via 1 23 e Metal 2 to metal 3 using via 2 e Pickup to VDD or GND e Contact to metal on poly poly2 One can observe the RULER3 layer as the minimum distance between metal 1 objects TTS TTS SSNS a b Figure 3 3 Metal 3 to metal 2 a and metal 2 to metal 1 connection b
91. n each pixel could work as a buffer could sample and hold and could demonstrate the individual bias feature Once the first row possesses 96 active pixels a specific pattern of synchronization signals is generated by the scan_word block to create a matrix of 19 horizontal pixels and 5 vertical pixels 95 total pixels The desired pattern was drawn on Excel software using the conditional formatting feature on each spreadsheet cell for the number 1 facilitating visualization These binary numbers were automatically concatenated Figure 5 19 to be copied to the VHDL source code e Lsync clamp 1 2 3 4 5 6 7 8 9 10 1 CODE WORD BIAS VIDEO CODE_WORDY BIAS VIDEO active pixels 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clamp active pixels 1 2 3 4 5 6 7 8 9 10 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DEN 1111111111 1111111111 1111111111 1111111111 1 1111111111 A A 1111111111101000101000101000100111111111110100010110010110110011111111111010001010101010101001111111111101 010001 010001 010001 010001 001110 010001 011001 010101 010011 010001 b 010001 011011 010101 010101 010001 s8888 o 1111111111101000101000101000100 1111111111101000101100101101100 1111111111101000101010101010100 1111111111101000101001101010100 1111111111100111001000101000100 001010011010101001111111111100111001000101000100 Figure 5 19 Pattern drawing tool a
92. ng several numbers and background bands at different gray levels The acquired image at 250 kHz of pixel clock 10 FPS and 57 04 ms of integration time demonstrates a region of interest defined as a rectangle As it is moved over the white area the enhanced image presents the numbers that were hidden on that respective location Another example of object localization by enhancement of a region of interest using the ITP ROIC is shown in Figure 6 11 g to k The ideal illumination for image acquisition of g contrasts with h where the lightbar barely appears On 1 the square formed by the j and k bars reveals the object with a better contrast Finally an external environment image displayed in a computer monitor was acquired by the ITP ROIC with a bottom BIAS pattern applied as shown in Figure 6 11 1 x _ _ g Figure 6 11 Test image pattern a to f and region of interest enhancement g to k 97 More detailed Figure 6 12 presents two more examples of a region of interest hiding due to its saturation on white level bottom specific features on top of the truck A rectangular area the resolution of which can be defined at pixel level with a different bias is moved to the area of interest reducing the gain and exposing new details of the object Figure 6 12 ROI enhancement examples 6 7 FPGA test system The FPGA based infrastructure has been utilized as a functional
93. nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 71 Figure 5 7 LCD signals from controller block a 18 and manual selection of internal NUIMDEr measurement D nra aM diee se 12 Figure 5 8 Block diagram of LCD screen selector and adjustment of parameters 73 Figure 5 9 Context menu and switches a circuit under testing b and correlated WTAE COG idad dida 74 Figure 5 10 Block diagram of pulse generation and its parameters 74 Figure 5 11 Block diagram of output control with setup multiplexer 76 Figure 5 12 Timing diagram and relationship of variables for frame time calculation 77 Figure 5 13 Timing diagram of a pulse train for selection of Column 99 78 Figure 5 14 State machine diagram a simulation b and waveform c of the Seat VOL CO a ee er eee eee eee 79 Figure 5 15 Ramp generation parameters occccccccnncnnnonononononnnanannnnnnnnnnnnnnnnnnnnnnnononnnnnnnannns 80 Figure 5 16 Block diagram of ramp generator sss 81 Figure 5 17 Minimum voltage counter instantiation center LCD screen 81 Figure 5 18 Block diagram of DAC programming function sse 82 Figure 5 19 Pattern drawing tool a and concatenated binary number b 83 Figure 5 20 Video waveform of 19 x 5 pixel generated pattern ssuuss 84 XX Figure 5 21 S
94. nt to the DAC the slew rate and voltage limits of a digital pulse can be controlled 79 Digital control signal amplitude time Figure 5 15 Ramp generation parameters The digital signal controls the up down input defining the ascendant or descendant ramp As described in Section 4 6 a counter of 0 to 3 000 instead of 4 095 representing a voltage range of 0 V to 15 V results in 5 mV 0 033 of resolution per count step As shown in Figure 5 16 this number is generated by a counter of 0 to 300 in step of two counts and multiplied by 10 Inside the counter the number is divided by two which is an easy software operation For example 298 counts divided by two results in 149 that string will be displayed as 14 9V after the concatenation of 14 9 and V characters The 3 000 counter will have 2 980 counts which multiplied by 5 mV count results in 14 9 V In this way the LCD will directly display the adjusted voltage on minimum maximum and step parameters Figure 5 18 shows the VHDL instantiation code for the minimum voltage counter as well as shows the strings concatenation code for display into the LCD The LCD picture shows the minimum maximum and step parameters of Ramp in volts 80 90 90 90 90 90 90 high_level AB o e 5 Bea lt ale 3lQ0 o 0u Sil0 ojJJ o INl_ramp1_LO o i sas eo TASA lt N 23 o bottom screen to view sel 74
95. nterconnections for definition of new test setups These techniques are based on the use of line distributed design layout the semiautomatic wire bonding process an open cavity chip carrier zero insertion force socket and on a specifically designed connection PCB liberating the IC design from relying on a limited number of external pad connections on the chip and on a package soldering process 13 These milestones pave the way for a new ROIC with individual pixel bias control which can be applied in a portable tunable DWELL FP as described in the following publications and conference presentations e Glauco RC Fiorante Payman Zarkesh Ha Javad Ghasemi and Sanjay Krishna Design and testing of spatio temporal tunable pixels for multi spectral infrared imagers IEEE Transactions on Very Large Scale Integration Systems submitted on Jun 30 2013 e Glauco RC Fiorante Payman Zarkesh Ha Javad Ghasemi and Sanjay Krishna Spatio temporal tunable pixels for multi spectral infrared imagers accepted IEEE 56 MWSCAS 4 7 Aug 2013 Columbus OH e Javad Ghasemi P Zarkesh Ha G R C Fiorante and S Krishna A new CMOS readout circuit approach for multispectral imaging accepted 2013 IEEE Photonics Conference 8 12 Sep 2013 Bellevue WA e JF Xu G R C Fiorante P Zarkesh Ha and S Krishna A readout integrated circuit ROIC with hybrid source sensor array 2011 IEEE Photonics Conference 9
96. online sizing and positioning of a region of interest ROI with different bias for image enhancement and object location specific signals were generated One pulse generator is started reset on the line sync pulse and receives its clock from the pixel clock signal generating a pulse inside the line 85 timing presenting a vertical line on the FPA and consequently on the screen of the frame grabber Another pulse generator is started at the frame sync pulse and its clock comes from the line sync signal generating a horizontal line on the FPA frame grabber Figure 5 24 These signals also can be used for testing the video reception and synchronization without the requirement of passing the ITP ROIC for processing The combination of the vertical test line and horizontal test line generates a squared window signal that is used to define a region of interest for biasing The size and position of this region can be adjusted Figure 5 25 even permitting the selection of just one pixel In this case this signal can control a light over the FPA to measure the response of one pixel without the requirement of optics manipulation or focusing VH light ctrl V test H test up E gt RST gt RST EE LO wait LO wait BR B KIEJ 97 s SYSRST or East BT setup Figure 5 24 Positioning and sizing of vertical horizontal and squared ROI windows Lom Figure 5 25 Positioning and sizing of vertical horizon
97. output 99 and video output in hold with cross talk 94 Figure 6 7 Biasing integration and hold signals on unit cell oooonnnnnnnnnnnnnnnnnn 95 Figure 6 8 Input a bottom voltage range and output swing a top of unit cell 95 Figure 6 9 Integration with 2 biases during sweeping in one row 4 combined images 96 XX1 Figure 6 10 Figure 6 11 Figure 6 12 Figure 6 13 Figure 6 14 Figure 6 15 Figure 6 16 Figure 6 17 Figure 6 18 Figure 6 19 Figure 6 20 Waveforms of generated digital signals and analog measurements 96 Test image pattern a to f and region of interest enhancement g to k 97 ROI enhancement examples it 98 Online individual adjustment of signal parameters oooccccncncnnnnnnnnnnnnnnnnss 99 2D image pattern applied to BIAS and acquired from ITP ROIC 100 Integration switch gate voltage waveform with controlled parameters 101 Settling time of DAC output voltage 4 16 us pixel clock Clock feedthrough effect a and slew rate control compensation b 102 Images from FPGA ROM memory a and processing b 47 103 Focused ion beam FIB equipment a and layout over SEM image b 104 Planned cutting filling locations on design layout a and on SEM image b Figure 6 21 Details of final work with the collateral effects a and overall view of AA
98. ows the etched and filled holes the deposited metal tracks and the collateral destructive effects a b Figure 6 19 Focused ion beam FIB equipment a and layout over SEM image b 104 i xT microscope Control Fle Edit Detectors Scan Beam Patterning Stage Tool Window Heb E Y hix mow aon kr BOY mia is 2 029564 SRN wy Bly PB e a b Figure 6 20 Planned cutting filling locations on design layout a and on SEM image b ao e a b Figure 6 21 Details of final work with the collateral effects a and overall view of processed area b 6 13 2 x 2 matrix With chip recovery using FIB not successfull and with the designed chip unable to demonstrate the spatial feature with different biases on pixels in different positions a backup plan to build a small matrix using separated unit cells was undertaken The 84 pin carrier could accommodate four dies in a 2 x 2 matrix in the same way that the necessary pins for the unit cell operation including the output current mirror could be wire bonded to one side Figure 6 22 shows a wire bonding and carrier interconnection diagram with several biases and the connected control pins of each unit cell A matrix of two columns and two row selection lines has to be provided by the FPGA system 105 2X US tui y Pf NU ee 7 jag y NY ANN e A DORA ae XH A REBE 1 E PIT 7 M Figure
99. parated pad was tested and did not present related significant values for these effects Reviewing the design a problem was found in the photodiode connection triggering an unintended short circuit to ground This problem was not detected by the highlight tool because the substrate connection was disabled On the other hand it was possible to measure the ground resistance of the substrate which was near 800 ohms Table 6 2 Response comparison of different photodiode structures 6 2 Poly resistors The designed poly resistors showed good precision of value definition 1 e 1 5 for the 10 kQ test structure and 0 18 for the 320 kQ resistor as shown in Figure 6 4 This was necessary once an internal digital to analog conversion using an R 2R ladder was planned to assure a better settling time for the output voltage 92 6 3 Mirror transistors As described in Section 3 4 the FF 99 on column selector does not drive current to any internal column but has its column bias transistor and multiplexer switch driven to an external pad Originated from the 10 x 1 sizing of these transistors Figure 6 5 a the column bias current mirror transistor supplies a current of 1 10 of the input adjusted bias current without the requirement of a clock to the column selector Figure 6 5 b shows the externally adjusted bias current of 200 uA middle multimeter to reflect 19 9 WA left multimeter on a 10 kQ current limiter resistor The multimeter
100. pins with a lead pitch 0 050 1 27 mm 28 Figure 4 16 a for use with zero insertion force ZIF sockets 29 on a specifically designed PCB as shown in Figure 4 16 b c On the front side of the socket PCB 0 1 2 54 mm right angle header male pins 30 were mounted permitting cable connections with minimum interference on the front path necessary for illumination access to the 54 chip The back side has straight pins with the same connections as the front side permitting not only cable attachment but the connection of this board on level shifter boards or on signal buffer daughter boards dio 1 T PRA 1 gt Figure 4 16 LCC carrier a specific designed PCB front b and ZIF socket on back c The header pins on both sides of the board can receive jumpers 31 dedicated to ground connection where necessary The interconnection cables were made with pre crimped wires with female terminals twisted with the ground wire to minimize noise generation and terminated on a 0 1 2 54 mm crimp connector housing 32 These resources and features constitute a technique that allows great speed and flexibility for establishing a desired test setup for specific characterization Furthermore the relative low cost of components permitted the building of several setups for the test structures including interconnection of different setups 4 10 3 Wire bonding As explained earlier it was decided to wire bond th
101. pixels built from Row0 UNM en 36 Figure 3 22 Row with photodiodes connected top without photodiode connection bottom and CTIA inverting input connected to pad orange and red 36 Figure 3 23 Output buffer design a and highlighting b cccccccccccncnnnnnnnnnmm 37 Figure 3 24 Top and bottom interconnection between blocks two images mounted 38 Figure 3 25 Highlighting of interconnection between blocks sss 38 Figure 3 26 A 4 x 4 matrix with dummy designed cells interconnecting the active cells err TERR 39 Figure 3 27 Dummy designed cells a and 4 x 4 matrix Spice simulation b 40 Figure 3 28 Dislocated top flipped midle and overlapped columns bottom 4 Figure 3 29 Unit cell main layers layout a and signals connections b 42 XVII Fi9ure 3 30 ITPSROIC tinal chip la YO Ut 42 Figure 4 1 Actual version of the test and characterization system hardware 43 Figure 4 2 Spartan 3E 1600 board a 18 and FX2 module interface board b 20 44 Figure 4 3 LM317 typical circuit application a and regulation features b 45 Figure 4 4 Push buttons and rotary switch a main board b and slide switches c Bice ecm TC 45 Figure 4 5 Pmod push button a slide switch b and rotary switch c 22 46 Fig
102. ration block aiming to subtract the initial pixel biasing from the integrated voltage so that the result is sent to the S amp H stage for external readout As shown in Figure 1 10 the reading of each pixel integrated value is accomplished by a column selector CS and row selector RS which work as unit cell signal multiplexers The reset and clock pulses applied on these shift registers sweep and select one column and one row at a time addressing one specific unit cell in the matrix This typical structure had intensive circuit reuse for the address selector to achieve a compact unit cell COLUMN SELECTOR CS INT HOLD SWITCHES REF SWITCHES O LU Ones ma r EMO OIE 10 E Wy ETE rin 0 213 mic Figure 1 10 Typical ROIC multiplexer white with added features gray 1 7 Contribution of this dissertation The main focus of this dissertation on spatio temporal circuits for imaging sensors is to design implement and test a unit cell an FPA and an ROIC to individually define the pixel bias voltage and to provide a solid basis for the development of a spectral tunable 11 DWELL infrared camera The first contribution is the unit cell electronic circuit design which should be compact simple and reliable to execute the required digital and analog functions The digital function controls a row versus column selective transfer of an external voltage bias to the analog memory the integration process the voltag
103. rial converter to generate each pixel BIAS in the matrix The code of each line 1s sent to this converter by a multiplexer controlled by a line counter with appropriate synchronization signals A state machine Figure 5 14 is initialized by the 78 falling edge of a start signal reading the bits on the code_word signal and presenting this bit on output at each pulse of the input clock Several input words can be scanned to the respective output in parallel so this block can be used to generate the bias the pixel clock the line sync and the frame sync for testing of a 19 x 5 pixel matrix to the frame grabber In addition this same block as detailed later generates the serial code for the DAC together with the chip select signal and clock Iinmmnmnmnnmnnnmnnnn f TII M daidai Jtestbench sync data sysrst Jtestbench sync data sysclk Jtestbench sync data Tsync Jtestbench sync data data p fhestbench_sync_data clk_p Ibench sync data scan on status 0 b Figure 5 14 State machine diagram a simulation b and waveform c of the scan word 5 15 DAC ramp generator To generate a ramp on an analog signal the same up down counter block was used as a variable memory with small adaptations On this block minimum and maximum values the step or number to be added subtracted and the clock division on this counting process can be defined As illustrated in Figure 5 15 working on these parameters to be se
104. right shows the measured source to gate voltage b Figure 6 4 Poly resistor test structure of 10 kQ a and of 320 KQ b Figure 6 5 Current mirror transistor sizing relationship a and measurement b 93 6 4 Column selector The group of multiplexer switches column selector and output buffer proved to work correctly as shown in Figure 6 6 One can observe the cross talk of the full swing width control signal on the output video signal due to parallel wires on design Figure 3 20 and the input floating node of the output buffer amplifier This issue was addressed on the new design by shielding these signals with a ground wire between them and by a VDD shielding layer on top 46 the last of which also shields the circuit against undesired light effects u Zoom Factor DO X oom Position 808 5 et 2 1 E a 2 i f 4 005 5 00MS s Aux 64 pu EPI 18 80 6 10k points 0 00 V IE W19 Mow 2012 11 18 13 Figure 6 6 Column selector output 99 and video output in hold with cross talk 6 5 Unit cell The unit cell in the separated design has proven its functionality as shown on biasing integration and holding waveforms of the Figure 6 7 94 Sync px tst n jJ Wirow rst ses ea laser P EE Wirow clk ot MUDA ESA OI AE d Micol clk_pt EG _ gt Nx dirdcol rst A aE BIASING INTEGRATION my video n mamaaa li aux_signal_ctrl_width MA light
105. rizes the features of the 96 x 96 pixel test prototype chip which has been designed and fabricated via MOSIS 45 in a double poly four metal layer standard 0 35 um mixed signal 3 3 15 V TSMC high voltage CMOS process UC UNITCELL II II PHOTODIODES p ES t ri ananas fa See a000 UC TRANSISTORS o OPAMP ROW SELECTOR P 96 X 96 ACTIVE MATRIX BIAS TRANSISTOR UC PHOTODIODES s BIAS CONTROL p LEVEL SHIFTER n rmm Menem COLUMN SELECTOR a 000000090090 Figure 6 1 Microphotograph of test chip The layout of the unit cell and chip are shown in Figure 6 2 The pixel has 15 transistors and four capacitors designed in a 30 x 30 um area at a pitch of 40 x 40 um to fit the photodiodes Considering 320 um of area not covered by metal layers the fill factor is 20 89 TSMC 0 35 um CMOS Technology 2PAM Low voltage 33V Power section supply High voltage isy section Die size including pads 5 14 x 5 14 mm Total pixels array size 98 x98 Active pixels array size 96 x 96 Pixel pitch 40 x 40 um Pixel size 30 x 30 um Phtotodiode type n n well p sub Fill factor 20 Unit cell transistors 15 Unit cell capacitors 4 C INT 74fF C Bias 55 fF C Hold 57 fF Integration time 0 85 to 245 ms Input voltage swing 10 V Output voltage swing 7 8 V Table 6 1 ITP ROIC design main parameters PHOTODIODE IDIITEEPEHEIUEO CAPACITOR
106. scheme 5 The sensor response division scheme divides the band based on the response of various detectors 6 e Near infrared NIR from 0 7 um to 1 0 um from the approximate end of the response of the human eye to that of the silicon e Shortwave infrared SWIR 1 0 um to 3 um from the cutoff of silicon to that of the MWIR atmospheric window InGaAs covers to about 1 8 jum the less sensitive lead salts cover this region e Midwave infrared MWIR 3 um to 5 um defined by the atmospheric window and covered by Indium antimonide InSb and HgCdTe and partially by lead selenide PbSe e Long wave infrared LWIR 8 um to 12 um or 7 um to 14 um the atmospheric window covered by HgCdTe and microbolometers e Very long wave infrared VLWIR 12 um to approximately 30 um covered by doped silicon e Far infrared FIR more than 25 um MWIR and LWIR bands of the spectrum present high importance for three main reasons First Most objects emit radiation in this wavelength range thus IR sensors are effective in seeing in the dark and in this way are useful for applications in thermography for noninvasive medical imaging and in night vision imaging Second The majority of chemical species have spectral signatures in the IR regime due to fundamental absorption processes associated with vibrational states of the molecules permitting applications such as pollution monitoring gas leakage detection and spectroscopy
107. shifter has a total ratio of 32 09 much bigger than the row selector chain but 1t consists of two inverters at ratios of 5 56 and 5 8 To reduce the difference of operational points of the low voltage and high voltage transistors the low voltage power supply was increased from 3 3 V to 3 5 V and the high voltage power supply was reduced Monitoring the waveforms it was noticed that the SW BIAS begin to work when the high voltage power supply was reduced from 15 V to 9 75 V And consequently the ITP ROIC proved its functionality 107 Chapter 7 Conclusions and future work 7 1 Conclusions A new wide dynamic range high voltage dual polarity individually tunable bias ROIC test chip was successfully designed fabricated and tested The test chip contains a 96 x 96 array of unit cells and controlling logic circuits for readout functionality Based on the TSMC s 0 35 um CMOS process technology the layout of the unit cell was designed to meet the 30 um pitch requirement for the DWELL FPA A flexible test and characterization system with online autonomous individual adjustments via software of signal parameters was developed permitting its use on upcoming similar projects The successful design of the proposed ITP ROIC lays a solid foundation for future applications of infrared FPAs such as the infrared retina classification cameras and remote sensing imagers 7 2 Future work The knowledge and experience acquired during the dev
108. tal and squared ROI windows 86 5 20 VGA controller As described in Section 4 9 the Spartan 3E board uses minimal hardware to connect the FPGA pins to an external monitor which can receive signals defining eight colors on VGA resolution 640 x 480 pixels This is the starting point for displaying an image using only the FPGA hardware resources avoiding the requirement of an external computer frame grabber and proprietary software More importantly the final application of image acquisition requires autonomous operation A VGA controller that generates the pixel clock and the vertical and horizontal synchronization signals 44 was tested and its timing specifications are shown in Table 5 2 and Figure 5 26 Vertical Sync Horizontal Sync symbol Table 5 2 VGA timing for 640 x 480 pixels 44 Figure 5 26 VGA control timing 44 87 5 21 UCF file The user constraint file UCF offers versatility and portability for the VHDL code defining the interconnection between the signals in the source code and hardware pinout of the FPGA This file also defines hardware specifications for the inputs outputs such as the voltage range TTL LVCMOS25 LVCMOS33 the slew rate slow fast and the output drive current 2 4 6 8 12 16 mA The VHDL code can be used with any hardware requiring only changing the interconnection names on the file But it is important to manipulate the names definition to simplify any
109. the sub clock Figure 5 6 which in turn is generated by the division of the system clock 50 MHz The sub clk is used in the SPI DAC to generate one analog BIAS value at each pixel clock In addition multiples of clk pixel were crated to chopper signals on unit cell characterization Tek PreVu po 1 EEE CL p 7 E nw b aa 30 00 96 10k points e 50v D15 Do ee 00v la Timing Resolution 2 00ns Value Mean Min Max Std Dev 22 E 2012 Pulses 8 8 000 8 8 0 000 Ed 03 09 Pulses 4 4 000 4 4 0 000 Figure 5 5 Clock generation and division waveforms 70 Sub_CLK_stepTABLE out sub_CLK_stepTABLE_out_u INI_sub_CLK_stepTABLE R32 wi 4 Cn C j co wo sub CLk stepTABLE mux UDC10 ca C au SIEG el _ SUB_CLK tmm emeret T 2 MHz 0 5 us SETA dkg ini clk DAC inMUXD 1 ini clk DAC inMLX clk dac inMUX ck dac in Figure 5 6 Block diagram of clock generation and division 5 5 LCD controller The two line x 16 character liquid crystal display LCD hardware module receives three control signals command data read write and LCD enable disable a clock and eight bits of data Figure 5 7 a which are sent by the LCD controller block 71 LCD RS 0 Command 1 Data SF D 11 8 i i I LCD RW if LCD_E ramp_stepLIM 230 ns i a i i i 40 ns 10 ns variables 1Ebitz a b Figure 5 7
110. ure 4 6 Pmod LED a and buffer circuit b 22 o ooocccncnnnnnnncnnnnnnnnnnonnnnnm 46 Figure 4 7 Digital level shifter circuit a voltage levels control b and designed PCB E e r eee echo 47 Figure 4 8 Safety electronic switch for BIAS a and clamp reference value switching D hese cesses ea am A A saeco cect cee 48 Figure 4 9 DAC block diagram a analog level adapter b and DAC serial coding c A OS O 49 Figure 4 10 Analog level shifting illustration esses 50 Figure 4 11 DB15 VGA connector and pinout 18 oo ccccccceceeeeeeeeeseeeeeeeeeeeees 52 Figure 4 12 Voltage levels for VGA specification 18 ooccccccccnnnnnnnnnonmmmm 52 Figure 4 13 Generated colors with 3 bits word on VGA input sss 22 Figure 4 14 ITP ROIC QFN package a and bare dies b sssesussssss 53 Figure 4 15 PCB for QFN package pinout a top b and bottom view c 54 XvIll Figure 4 16 Figure 4 17 Figure 4 18 Figure 4 19 Figure 4 20 Figure 4 21 Figure 4 22 Station Figure 4 23 Figure 4 24 LCC carrier a specific designed PCB front b and ZIF socket on back c ositos 55 Semiautomatic wire bond machine ececcccccceececeeecceeeeeeeeeeeeeeeeeeeeeeeeeees 56 Wire bonded ground and VDD a die 10 b
111. urrent source for its biasing and a 10 1 current mirror circuit was adopted to achieve this 17 Figure 3 12 shows the layout of the input bias transistor with 50 um on width size and the output bias transistor with 5 um on width size After the layout design the type and size of the transistors together with the information about the circuit nodes interconnections were extracted using a specific tool on EDA to generate a simulation Spice file Simulation code using Spice Figure 3 13 presents a source gate voltage of 1 95 V for the desired drain current of 200 uA on the input transistor and 20 uA on the output column transistor Figure 3 14 b Figure 3 12 Layout of input bias transistor a and of output bias transistor b sl E 52 P MOS VGS x ID CURVE for current mirror 23 54 lib hv15 1 TT hwa 55 drain gate source bulk model Lengh Width 56 M8 GND GND VDD VDD pch hva 1 1 5e 006 w 5e 005 57 Had 4 125e 011 as 6 5e 011 pd 2 83e 005 ps 5 52e 005 32 2 2 67 33 7 27 67 58 59 M4 GND GND VDD VDD pch hva L 1 5u W 5u AS 13p P5 15 2u 60 61 name node node type value 62 Vdd out pa VOD GND DC ov 63 Vbias ps VDD Gate DC ov 64 ko ig SE Analysing 65 sample time step total simulation time to show 66 tran lus 45ms ET print is M8 iG M8 D M8 iB M8 68 69 dc Vdd out pa 0 4 0 05 Vbias ps 1 1 6 0 1 70 print DC Is mB Is m4 71 e Mil iuiiu hia asc an o
112. xel clock and 57 ms of integration time the acquired image presents 10 FPS The ITP ROIC has a bias voltage range of 5 V and an output voltage swing of 3 9 V The 74 fF integration capacitor presents a charge capacity of 370 fC or 2 31 x 10 electrons at 5 V Vill CONTENTS DEDICATION Dt iV ACKNOWLEDGMENT S is V ABSTRACE aus tascntiia iconos Vil CONTE NES odiar 1X LSTOFHOGURES ostensum aves etd tap aut un Maid este ebat fam ebd enu d Drs epa UE XV LISTO NP dol Saad xxiii Chapter T Inttodueoli eisa ea E RAEE Unsdue EE l 1 1 El ctromniaptetie TagtabtlOTIo s oae TEOT l 122 DWE Eb sitas iii 2 k3 PINOUOC1OG oC 4 1 4 Focal plane array and readout integrated circuit oooooooooooaaacoccccnnnnnnnnnnnnnnnnnos 6 Ls IVI TAU OU PP PAU OT O 1 6 PNP POAC aero ana octave onde ie MS eduu a los eo e a Desde one oe se eivea inso e A Rees Noe Ves 10 1 7 Contribution Of this GISSCrl AMON iia 11 1 8 Other diseno ON aio 15 Chapter 2 Ola AAA oo O A 16 2d Operational Amipld Het aia iia 18 2 2 MTA COM mc 19 2 9 Colada Ve toni 20 Chapter 3 VLSI Dead i 22 ah DRC and minimum feature size eene eene eene eene 22 212 Interidyer COMME CIOS dei 23 3 5 Discrete devices and test structures ined eben een on ane iia 25 3 4 POCO CTO NS RT crc 2 3 9 CCUtECDIDEBITEOT 9e odo stet den Uis seme eto Eo vete dedo iosvee sped Ede dent 30 3 6 Operational amplia ido 31 3 7
113. ymmetric PMOS transistors e One separated pad with ESD protection e A separated unit cell Nwips NP NW SN NP NDD NP PS NW PDD PDD NW INTERNAL PADS ASYMMETRIC P MOS IPS NWIPS IPS LV NW PS PS UNITCELL B E H E IA HEH HEH HB EH HUM HM NONSE NOE ONE OGLnE DEN POLY CAPACITOR ASYMMETRIC N MOS SYMMETRIC N MOS SYMMETRIC P MOS ESD PAD substrate Figure 3 7 Photodiodes discrete devices and ESD pad test structures on top of the chip top symmetric NMOS and PMOS transistors layout detail center and circuit bottom The seven photodiodes test structures present 48 x 98 um and the following layers e NWell Psub e NPlus NWell Psub with silicon nitride layer e NPlus NWell Psub without silicon nitride layer e NDD Psub Ndeep drain to Psubstrate e NPlus Psub low voltage device 26 e NWell PDD NWell Psub e PDD NWell Psub float PN junction for characterization of VDETCOM node with different voltage than the actual 0 V The asymmetric PMOS transistor has its own pad connected to the Nwell layer for electro optical characterization the requirement of which was noted in previous designs The test structures on the right and left sides of the chip are e Two poly resistors e The unit cell opamp e The bias transistor Figure 3 8 e Four types of photodiodes Figure 3 8 Bias transistor and poly resistor of 10 kQ 3 4 Photodiode For the proof of concept and to demonstrate the

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