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Demonstration Setup

1. Signal Name FPGA Pin No Description ce Standard LCD DATA 7 PIN 5 LCD Data 7 3 3V LCD DATA 6 M3 LCD Data 6 3 3V LCD DATA 5 PIN K2 LCD Data 5 3 3V LCD_DATA 4 IPIN LCD Data 4 3 3V LCD DATA 3 PIN K7 LCD Data 3 3 3V 39 Terasic DE2 115 User Manual www terasic com www terasic com NOT RIA LCD DATA 2 PIN L2 LCD Data 2 3 3V LCD DATA 1 PIN L1 LCD Data 1 3 3V LCD DATAIOJ PIN L3 LCD Data 0 3 3V LCD EN PIN L4 LCD Enable 3 3V LCD RW PIN M1 LCD Read Write Select 0 Write 1 Read 3 3V LCD RS PIN M2 LCD Command Data Select 0 Command 1 Data 3 3V LCD ON PIN L5 LCD Power ON OFF 3 3V LCD BLON PIN L6 LCD Back Light ON OFF 3 3V 4 7 High Speed Mezzanine Card The DE2 115 development board contains a HSMC interface to provide a mechanism for extending the peripheral set of a FPGA host board by means of add on cards This can address today s high speed signaling requirement as well as low speed device interface support The HSMC interface support JTAG clock outputs and inputs high speed LVDS and single ended signaling The HSMC connector connects directly to the Cyclone IV E FPGA with 82 pins Signals HSMC_SDA and HSMC SCLK share the same bus with the respected signals IC SDA and I2C_SCL of the WM8 31 audio ship ADV7180 TV decoder chip Table 4 7 shows the maximum power consumption of the daughter card that connects to HSMC p
2. 53 2 12 189 252 et POE nm NETUS 54 55 4 14 Gian Eihemet Bri eb NT TO T OO 56 TY DE 612 NR t 59 4 16 Implementing a TV naas oa Sana AN AN Lan 61 4 17 Usine the USB Interlace no sn mm 6 4 NO Bruni ne mem 62 4 19 Using SRAM SDRAM FLASH EEPROM SD 63 CHAPTERS DE2 I5 SYSTEM BULE Rn aa aan am aa anisa 71 UA 99 NO aa aa asa aa aan 71 gt NOW sn asa 71 23 Using DE2 115 System Builder semat mn Bams aa khas 72 6 EXAMPLES OF ADVANCED DEMONSTRATIONS ooooooooooooooooooooooooooooooo oooooooooooooooooooo 79 6 1 DE2 I15 Factory Con 79 Box CONS AON ee cece ce an en MTM Md 80 USB Paiton nona an ane ear naa 82 OA SB H 84 Karaoke ma E aa lean ala aa 84 Or Card Deo en 88 SD Card Music Play NT aa ke 91 6 5 052 Mouse Demons 95 6 9 IR name ha anna Dena eu RU Meme Rubeo ka 98 6 10 Music Synthesizer
3. 102 6 11 Audio Recording and Playing 105 DE2 115 User Manual www terasic com www terasic com NOTE RIA amp 6 12 Web Server DEMONS AG OM 108 CHAPTER7 e 119 7 1 EPCS Programming via 105 2 119 119 S NG LEITET Tm 120 3 Terasic DE2 115 User Manual www terasic com www terasic com Chapter 1 DE2 115 Package The DE2 115 package contains all components needed to use the DE2 115 board in conjunction with a computer that runs the Microsoft Windows OS 1 1 Package Contents Figure 1 1 shows a photograph of the DE2 115 package Altera DE2 115 Board Altera Complete Design Suite DVD for Windows DE2 115 System CD HARI asean Power DC Adapter 12V 2A B 1 279 USB Programming Cable Two 1 Headers Two Wire Strips black and red Q Six Silicon Footstands 9 Remote Controller nnam mmm Pron Cuv Figure 1 1 The DE2 115 package contents The DE2 115 package includes e The DE2 115 board USB Cable for FPGA programming and control e DE2 115 System CD containing the DE2 115 documentation and supporting materials includin
4. CENA Figure 6 11 Insert SD Card for the SD Card Demonstration Nios II EDS 9 1 ojx nios2 terminal connected to hardware target using JTAG UART on cable nios2 terminal USB Blaster USB 8 1 device 1 instance 8 nios2 terminal Use the IDE stop button or Ctrl C to terminate 2 115 SDCARD Demo Processing sdcard mount success Root Directory Item Count 1 B8 ITEST TXT test txt dump Le es s kkk Test Done Press KEY3 to test again Figure 6 12 Running results of the SD Card demonstration 6 7 SD Card Music Player Many commercial media audio players use a large external storage device such as an SD Card or CF card to store music or video files Such players may also include high quality DAC devices so that good audio quality can be produced The DE2 115 board provides the hardware and software needed for SD Card access and professional audio performance so that it is possible to design advanced multimedia products using the DE2 115 board In this demonstration we show how to implement an SD Card Music Player on the DE2 115 board in which the music files are stored in an SD Card and the board can play the music files via its CD quality audio DAC circuits We use the Nios processor to read the music data stored in the SD Card and use the Wolfson WM8731 audio CODEC to play the music 91 Terasic DE2 115 User Manual www terasic c
5. LEDG3 LEDG3 LEDG4 LEDG4 H21 NA HERU IV LEDR15 LEDR15 E LEDG6 LEDG6 G15 G22 LEDR16 LEDR16 021 LEDG7 LEDG7 LEDR17 LEDR17 Hib F17 LEDG8 LEDG8 Figure 4 9 Connections between the LEDs and Cyclone IV E FPGA A list of the pin names on the Cyclone IV E FPGA that are connected to the slide switches is given in Table 4 1 Similarly the pins used to connect to the push button switches and LEDs are displayed in Table 4 2 and Table 4 3 respectively 34 Terasic DE2 115 User Manual www terasic com www terasic co m NOT RIA Table 4 1 Pin Assignments for Slide Switches Signal Name FPGA Pin No Description Standard SW 0 PIN_AB28 Slide Switch 0 Depending on JP7 SW 1 PIN AC28 Slide Switch 1 Depending on JP7 SW 2 PIN AC27 Slide Switch 2 Depending on JP7 SWI3I PIN AD27 Slide Switch 3 Depending on JP7 SWI4I PIN AB27 Slide Switch 4 Depending on JP7 SW 5 26 Slide Switch 5 Depending on JP7 SWI6 PIN AD26 Slide Switch 6 Depending on JP7 SWIT7I PIN AB26 Slide Switch 7 Depending on JP7 8 PIN 425 Slide Switch 8 Depending on JP7 SW 9 PIN AB25 Slide Switch 9 Depending on JP7 SW 10 PIN AC24 Slide Switch 10 Depending on JP7 SW 11 PIN AB24 Slide Switch 11 Depending on JP7 SW 12 PIN AB23 Slide Switch 12 Depending on JP7 SW 13 24 Slide Switch 13 Depending on JP7 SW 14 PIN AA23 Slide Switch 14 Depending on JP7 SW 15 PIN AA22 Slide Switch 15
6. 16 and PushebUt 19 1 18 3 4 SDRAM SRAM EEPROM Flash Controller and Program mer 19 2 9 4 E 2 OTC IC T 22 23 POER e Mou ELTERN EE mcm 23 na 24 H 25 SNNT C x T DOLEO 26 3 12 Overall Structure of the DE2 115 Control Panel oWooooo cc 27 CHAPTERS USING DE2 I15 BOARD 29 AA Contours the Cyclone PPGUA 29 4 2 Using Push battons and SWILCNGS 32 AU Simo ES Pa en aan 34 2 Usine the Seement Display T 36 1 5 DE2 115 User Manual www terasic com AN OTE RIA a E Bue OT en m 38 4 0 Est the ECT MO ea 39 4 7 High Speed Mezzanine Card inai ala kasa 40 4 Usine the Expansion Header malas 46 4 9 Using 14 pin General Purpose I O 0 8 0 50 e E 51 4 11 Using 24 bit Audio 22 lt bane
7. 17 Seven Segment Digit 7 2 Depending on JP6 HEX7 3 PIN 17 Seven Segment Digit 7 3 Depending on JP6 HEX7 4 17 Seven Segment Digit 7 4 Depending on JP6 HEX7 5 18 Seven Segment Digit 75 Depending on JP6 HEX7 6 PIN 14 Seven Segment Digit 7 6 3 3V 4 5 Clock Circuitry The DE2 115 board includes one oscillator that produces 50 MHz clock signal A clock buffer 15 used to distribute 50 MHz clock signal with low jitter to FPGA The distributing clock signals are connected to the FPGA that are used for clocking the user logic The board also includes two SMA connectors which can be used to connect an external clock source to the board or to drive a clock signal out through the SMA connector In addition all these clock inputs are connected to the phase locked loops PLL clock input pins of the FPGA to allow users to use these clocks as a source clock for the PLL circuit The clock distribution on the DE2 115 board is shown in Figure 4 11 The associated pin assignments for clock inputs to FPGA I O pins are listed in Table 4 5 CLOCK 50 Y2 SMA CLKOUT E AE23 PLL4 CLKOUTp AG14 J15 PI49FCT3803 50MHz CLOCK2 50 OSC CLK15 CLOCK3 50 AG15 RYAN CLK13 14 ae CLK14 J16 Figure 4 11 Block diagram of the clock distribution Table 4 5 Pin Assignments for Clock Inputs Signal Name FPGA Pin No Description Standard CLOCK 50 PIN
8. IO Voltage 25 V Default Prefix Name The Prefix Name is an optional feature that denotes the pin name of the daughter card assigned in your design Users may leave this field empty Project Setting Management The DE2 115 System Builder also provides functions to restore default setting loading a setting and saving users board configuration file shown in Figure 5 7 Users can save the current board configuration information into a cfg file and load it to the DE2 115 System Builder Terasic DE2 115 User Manual www terasic com www terasic com Terasic DE2 115 System Builder 101 System Configuration UNIVERSITY Mad Project Name PROGRAM www terasic com 02 116 DE2 115 FPGA Board CLOCK RS232 LED x27 7 Seqement x 8 Button x 4 Switch x 18 PS2 SDCARD LCD MI SDRAM 128MB vl FLASH 8MB Mv SRAM 2MB M SMA Audio USB Ethernet 1 Ethernet 2 Decoder EJTAG ta eee ues IR Receiver EEPROM 32Kb gt GPIO Header 9 IO Voltage 3 3 V Default 7 Prefix Name DOM Pixel Camera HSMC IO Voltage 25 V Default Prefix Name Full b DIRX Figure 5 7 Project Settings B Project Generation When users press the Generate button the DE2 115 System Builder will generate the corresponding Quartus II files and documents as listed in the Table 5 1 Table 5 1 The files
9. G21 LED Green 7 2 5V LEDG S PIN F17 LED 8 2 5V 4 4 Using the 7 segment Displays The DE2 115 Board has eight 7 segment displays These displays are arranged into two pairs and a group of four behaving the intent of displaying numbers of various sizes As indicated in the schematic in Figure 4 10 the seven segments common anode are connected to pins on Cyclone IV E FPGA Applying a low logic level to a segment will light it up and applying a high logic level turns it off Each segment in a display 15 identified by an index from 0 to 6 with the positions given in Figure 4 10 Table 4 4 shows the assignments of FPGA pins to the 7 segment displays HEXO 0 HEXO 1 TERA 3 ne Cyclone IV HEXO 5 HEXO 6 Figure 4 10 Connections between the 7 segment display HEXO and Cyclone IV E FPGA Table 4 4 Pin Assignments for 7 segment Displays Signal Name FPGA Pin No Description Standard HEXO 0 G18 Seven Segment Digit 010 2 5 HEXO 1 PIN F22 Seven Segment Digit O 1 2 5V HEXO 2 PIN E17 Seven Segment Digit 0 2 2 5V 36 Terasic DE2 115 User Manual wwwW terasic com www terasic com NOS RIA HEXO 3 HEXO 4 HEXO 5 HEXO 6 HEX1 0 HEX1 1 HEX1 2 HEX1 3 HEX1 4 HEX1 5 HEX1 6 2 0 2 1 212 HEX2 3 HEX2 4 HEX2 5 2 6 HEX3 0 HEX3 1 HEX3 2 HEX3 3 HEX3 4 HEX3 5 HEX3 6 410 HEX4 1 HEX4 2 HEX4 3 HEX4 4 HEX4
10. 1 3 3V TD_ DATA 2 PIN D8 TV Decoder Data 2 3 3V TD DATA 3 PIN C7 TV Decoder Data 3 3 3V TD DATA 4 PIN D7 TV Decoder Data 4 3 3V TD DATA 5 PIN D6 TV Decoder Data 5 3 3V TD DATA 6 PIN E7 TV Decoder Data 6 3 3V TD DATA 7 PIN F7 TV Decoder Data 7 3 3V TD HS PIN E5 TV Decoder H SYNC 3 3V TD VS PIN 4 TV Decoder V SYNC 3 3V TD CLK27 PIN B14 TV Decoder Clock Input 3 3V TD RESET PIN G7 TV Decoder Reset 3 3V 2 SCLK 7 I2C Clock 3 3V I2C SDAT PIN A8 2 Data 3 3V 60 www terasic com Terasic DE2 115 User Manual www terasic com NOTE RIA amp 4 16 Implementing a TV Encoder Although the DE2 115 board does not include a TV encoder chip the ADV7123 10 bit high speed triple ADCs can be used to implement a professional quality TV encoder with the digital processing part implemented in the Cyclone IV E FPGA Figure 4 30 shows a block diagram of a TV encoder implemented in this manner FPGA 10 bit VGA DAC O Composite Y U cos V sin gt EB E Clock 8 bit Tring e DSP Block or Y S Video Iming Calculate Composite or RCA Y C U cos V sin S Video or RCA_Pb 8 bit Y gt MEN DSP Block S Video 5 V Tables RCA Pr Figure 4 30 ATV Encoder that uses the Cyclone IV E FPGA and the ADV7123 4 17 Using the USB Interface The DE2 115 board provides both USB host and device interfaces using the Cypress EZ OTG CY7C67200 On The Go OTG
11. download sof and elf files Figure 6 4 illustrates the setup for this demonstration DEP E LI H USB Mouse Monitor HE BB g O U G i i itri it 1 i TY I m IU nnmnnmnmnmmmnmWmmmnmmnm 6 rede Controller IP On Chip Video Frame Buffer Figure 6 4 The setup for the USB paintbrush demonstration 6 4 USB Device Most USB applications and products operate as USB devices rather than USB hosts In this demonstration we show how the DE2 115 board can operate as a USB device that can be connected to a host computer As indicated in the block diagram in Figure 6 5 the Nios II processor is used to communicate with the host computer via host port on the DE2 115 board s Cypress CY7C67200 device After connecting the DE2 115 board to a USB port on the host computer a software program has to be executed on the Nios II processor to initialize the Cypress CY7C67200 chip Once the software program is successfully executed the host computer will identify the new device in its USB device list and asks for the associated driver the device will be identified as a Terasic EZO USB After completion of the driver installation on the host computer the next step is to run a software program on the host computer called USB Controller exe this program communicates with the DE2 115 board Once
12. DE2 115 User Manual World Leading FPGA Based Products and Design Services 7 7 477 E a WEZ ZUM ID LIED DET 1010100101010101010101 0101010 10101010100010101010101010101010010101011101010010101001001010101010100101010101010101010101001011010107107 101010101000101010101010101010100101010111010100101070 10101010100010101010101010101010010101011H010 10101010100010101010101010101010010101011101010010101001001010101010100101070107 1010101010001010101010101010101001010101110101001010100100101010101010010101010101010101010100101 101010101000101010101010101010100101010111010100101010010010101010101001010101010170101070707 Pu E e WWW terasic com Copyright 2003 2013 Terasic Technologies Inc All Rights Reserved CONTENTS R CHAPTER DE2Z IIS PACKAGE ca 4 C 4 L2 IIS Board Assembly manga em sel kalteng 5 gonta aan ama 6 CHAPTER 2 INTRODUCTION OF THE ALTERA DE2 115 804 7 2 Layout and CO MI POMC MS 7 2 2 Block Diagram OF the DB2 115 BOSE Lemas www mal tam jamnya 9 2 Power up the DES ND DOSEG Dana Od Se dO enne 12 CHAPTERS DE2Z 11S CON PROUD PA NGI soorci 14 SN E Seuil Panci 9 s 14 3 2 Controlling LEDs 7 segment Displays and LCD
13. DIS FC DIS SLEEP SEL TWSI INT POL 75 500HM Table 4 20 Default Configuration for Gigabit Ethernet Description Default Value PHY Address in MDIO MDC Mode 10000 for Enet0 10001 for Enet1 Enable Pause Auto negotiation configuration for copper modes Enable Crossover Disable 125MHz clock Hardware Configuration Mode Disable fiber copper interface Energy detect Interface select Interrupt polarity Termination resistance 1 Default Register 4 11 10 to 11 1110 Auto neg advertise all capabilities prefer master 0 Disable 1 Disable 125CLK 1011 1111 RGMII to copper GMII to copper 1 Disable 1 Disable energy detect 0 Select MDC MDIO interface 1 INTn signal is active LOW 0 50 ohm termination for fiber Here only RGMII and MII modes are supported on the board The factory default mode is RGMII Terasic DE2 115 User Manual www terasic com 56 www terasic com ANOTE RYAN There is one jumper for each chip for switching work modes from RGMII to MII See Figure 4 28 You will need to perform a hardware reset after any change for enabling new settings Table 4 21 and Table 4 22 describe the working mode settings for ENETO PHY U8 and ENET1 PHY U9 respectively In addition it is dynamically configurable to support 10Mbps 100Mbps Fast Ethernet or 1000Mbps Gigabit Ethernet operation using standard Cat 5e UTP cabling The associated assignments are listed in Table 4 23 For detailed information o
14. SRAM ADDR 19 SRAM 000 SRAM DQ 1 SRAM DQ 2 SRAM DQ 3 SRAM_DQ 4 SRAM DQ 5 DQ I6 SRAM DQ IS SRAM DQ 9 SRAM DQ 10 SRAM DQ 11 SRAM DQ 12 SRAM DQ 13 SRAM DQ 14 SRAM DQ 15 SRAM OE N SRAM WE N SRAM CE N SRAM LB N SRAM UB N Signal Name DRAM ADDRIOJ DRAM ADDR 1 DRAM ADDR 2 DRAM ADDR 3 DRAM ADDR 4 DRAM ADDR 5 DRAM ADDR 6 DRAM ADDR 7 DRAM ADDRI8I DRAM ADDR 9 DRAM ADDR 10 DRAM ADDR 11 DRAM ADDR 12 DRAM DQ 0 DRAM DQ 1 DRAM DQ 2 Terasic DE2 115 User Manual www terasic com PIN AB11 AC11 9 PIN AB8 8 AF4 4 4 AF6 6 6 AD1 AD2 2 1 AE4 AF3 AG3 AD5 8 AF8 4 PIN ACA Table 4 28 SDRAM Pin Assignments FPGA Pin No PIN R6 PIN V8 PIN U8 PIN P1 PIN V5 PIN W8 PIN W7 PIN AA7 PIN Y5 PIN Y6 PIN R5 5 7 W3 W2 PIN V4 SRAM Address 15 SRAM Address 16 SRAM Address 17 SRAM Address 18 SRAM Address 19 SRAM Data 0 SRAM Data 1 SRAM Datal 2 SRAM Data 3 SRAM Data 4 SRAM Data 5 SRAM Data 6 SRAM Data 7 SRAM Data 8 SRAM Data 9 SRAM Data 10 SRAM Data 11 SRAM Data 12 SRAM Data 13 SRAM Data 14 SRAM Data 15 SRAM Output Enable SRAM Write Enable SRAM Chip Select SRAM Lower Byte St
15. amp PIN F25 PIN C27 PIN E26 PIN G26 PIN H26 PIN K26 PIN L24 PIN M26 PIN R26 PIN T26 PIN U26 PIN L22 PIN N26 PIN P26 PIN R21 PIN R23 PIN T22 PIN F24 PIN D26 PIN F26 PIN G25 PIN H25 PIN K25 LVDS bit or CMOS I O LVDS RX bit 1n or CMOS I O LVDS RX bit 2n or CMOS I O LVDS RX bit 3n or CMOS I O LVDS RX bit 4n or CMOS I O LVDS RX bit 5n or CMOS I O LVDS RX bit 6n or CMOS I O LVDS RX bit 7n or CMOS I O LVDS RX bit 8n or CMOS I O LVDS RX bit 9n or CMOS I O LVDS RX bit 10n or CMOS I O LVDS RX bit 11n or CMOS I O LVDS RX bit 12n or CMOS I O LVDS bit 13n or CMOS I O LVDS RX bit 14n or CMOS I O LVDS RX bit 15n or CMOS I O LVDS RX bit 16n or CMOS I O LVDS RX bit 0 or CMOS I O LVDS RX bit 1 or CMOS I O LVDS RX bit 2 or CMOS I O LVDS RX bit 3 or CMOS I O LVDS RX bit 4 or CMOS I O LVDS RX bit 5 or CMOS I O 43 Terasic DE2 115 User Manual www terasic com Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 www terasic com NO RIA HSMC D P
16. Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 www terasic com YU RIA HSMC TX D N 12 amp HSMC TX D N 13 HSMC TX D N 14 HSMC TX D N 15 HSMC TX D N 16 HSMC TX D HSMC TX D 1 HSMC TX D 2 HSMC TX D 3 HSMC TX D Pjaj HSMC TX D 5 HSMC TX D 6 HSMC TX D HSMC TX D HSMC TX D P 9 HSMC TX D P 10 HSMC TX D P 11 HSMC TX D 12 HSMC TX D P 13 HSMC TX D P 14 HSMC TX D P 15 HSMC TX D P 16 PIN V26 PIN R28 PIN U28 PIN V28 PIN V22 PIN D27 PIN E27 PIN F27 PIN G27 PIN K27 PIN M27 PIN 21 PIN H23 PIN J23 PIN P27 PIN J25 PIN L27 PIN V25 PIN R27 PIN U27 PIN V27 PIN U22 LVDS TX bit 12n or CMOS I O LVDS TX bit 13n or CMOS I O LVDS TX bit 14n or CMOS I O LVDS TX bit 15n or CMOS I O LVDS TX bit 16n or CMOS I O LVDS TX bit 0 or CMOS I O LVDS TX bit 1 or CMOS I O LVDS TX bit 2 or CMOS I O LVDS TX bit 3 or CMOS I O LVDS TX bit 4 or CMOS I O LVDS TX bit 5 or CMOS I O LVDS TX bit 6 or CMOS I O LVDS TX bit 7 or CMOS I O LVDS TX bit 8 or CMOS I O LVDS TX bit 9 or CMOS I O
17. Depending on JP7 SW 16 PIN Y24 Slide Switch 16 Depending on JP7 SW 17 PIN Y23 Slide Switch 17 Depending on JP7 Table 4 2 Pin Assignments for Push buttons Signal Name FPGA Pin No Description Standard 0 23 Push button 0 Depending on JP7 KEY 1 M21 Push button 1 Depending on JP7 KEY 2 PIN 21 Push button 2 Depending on JP7 KEY 3 PIN R24 Push button 3 Depending on JP7 Table 4 3 Pin Assignments for LEDs Signal Name FPGA Pin No Description Standard LEDR 0 PIN G19 LED Red 0 2 5V LEDR 1 PIN F19 LED Red 1 2 5V LEDR 2 PIN_E19 LED Red 2 2 5V LEDR 3 21 LED Red 3 2 5V LEDR 4 18 LED Red 4 2 5V LEDR 5 PIN E18 LED Red 5 2 5V LEDR 6 PIN J19 LED Red 6 2 5V LEDR 7 PIN_H19 LED Red 7 2 5V LEDR 8 PIN_J17 LED Red 8 2 5V LEDR 9 PIN G17 LED Red 9 2 5V LEDR 10 PIN J15 LED Red 10 2 5V LEDR 11 PIN H16 LED Red 11 2 5V LEDR 12 PIN J16 LED Red 12 2 5V LEDR 13 PIN_H17 LED Red 13 2 5V 35 Terasic DE2 115 User Manual www terasic com www terasic com ND RIA amp LEDR 14 PIN F15 LED Red 14 2 5V LEDR 15 PIN G15 LED Red 15 2 5V LEDR 16 PIN G16 LED Red 16 2 5V LEDR 17 PIN H15 LED Red 17 2 5V LEDG O PIN E21 LED Green 0 2 5V LEDG 1 PIN E22 LED Green 1 2 5V LEDGI2 PIN E25 LED Green 2 2 5V LEDG 3 PIN E24 LED Green 3 2 5V LEDG A PIN H21 LED Green 4 2 5V LEDG 5 PIN G20 LED Green 5 2 5V LEDG 6 PIN G22 LED Green 6 2 5V
18. LVDS TX bit 10 or CMOS I O LVDS TX bit 11 or CMOS I O LVDS TX bit 12 or CMOS I O LVDS TX bit 13 or CMOS I O LVDS TX bit 14 or CMOS I O LVDS TX bit 15 or CMOS I O LVDS TX bit 16 or CMOS I O 45 Terasic DE2 115 User Manual www terasic com Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 www terasic com AU S RIA amp 4 8 Using the Expansion Header The DE2 115 Board provides one 40 pin expansion header The header connects directly to 36 pins of the Cyclone IV E FPGA and also provides DC 5 VCC5 DC 3 3V VCC3P3 and two GND pins Figure 4 15 shows the I O distribution of the GPIO connector The maximum power consumption of the daughter card that connects to GPIO port is shown in Table 4 10 GPIO JP5 22 GPIO 0 GPIO 1 AC15 AB21 GPIO 2 GPIO 3 Y17 21 GPlO 4 GPIO B Y16 AD21 GPIO 6 GPIO 7 AE16 AD15 GPIO 8 GPIO 9 AE15 5V GND AC19 GPIO 10 GPIO 11 AF16 AD19 GPIO 12 GPIO 13 AF15 AF24 GPIO 14 GPIO 15 AE21 AF25 GPIO 16 GPIO 17 AC22 22 GPIO 18 c GPIO 19 AF21 AF22
19. the Cyclone E FPGA perform the following steps e Ensure that power is applied to the DE2 115 board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW19 to the RUN position See Figure 4 4 e Connect the supplied USB cable to the USB Blaster port on the DE2 115 board See Figure 2 1 The FPGA can now be programmed by using the Quartus II Programmer to select configuration bit stream file with the sof filename extension USB Blaster Circuit RUN Quartus 4 UART hh Ne EPM 240 JTAG Config Signals OU B JUARTUS II PROG Figure 4 3 The JTAG configuration scheme NM maa nue OS E f PERICOM Nene BB BBEB sati _ APPAR PPT 1 Tok B BE E NM bsd hml SW19 Figure 4 4 The RUN PROG switch SW19 is set in mode 3 2 115 User Manual www terasic com www terasic com NOTE RIA amp B Configuring the EPCS64 in AS Mode Figure 4 5 illustrates the AS configuration setup To download a configuration bit stream into the EPCS64 serial configuration device perform the following steps e Ensure that power is applied to the DE2 115 board e Connect the supplied USB cable to the USB Blaster port on the DE2 115 board See Figure 4 5 e Configure JTAG programming circuit by setting the RUN PROG slide switch SW19 to th
20. 1 Created web server task Prio 4 Web Server starting up Figure 6 35 Web Server Starting Success 117 Terasic DE2 115 User Manual www terasic com www terasic com NOTE RYA 2 115 Nios II Web Server Board Status Control Design Resource LEDG Control 124 51 7 LEDO 7 LED1 FILED www terasic com v LED3 MLED4 MILEDS aO S RYA LEDS MILED7 MLED8 UNIVERSITY Send PROGRAM 7 SEG Control Daughter Board SEG Num 0 4 3 Touch Panel Hex to 7 SEGs above num LCD Control 5Mega Pixel Camera This page is being served from a web server running on a configurable Nios Il LCD Text processor Hello World text to LCD The DE2 series has consistently been at the forefront of educational development above text boards by distinguishing itself with an abundance of interfaces to accommodate DVI Card various applications needs Extending its leadership and success Terasic announces the latest DE2 115 that features the Cyclone IV E device Responding to increased versatile low cost spectrum needs driven by the demand for mobile video voice data access and the hunger for high quality images the new DE2 115 offers an optimal balance of low cost low power and a rich supply of logic memory and DSP capabilities High Speed AD DA m _ Internet 2 RUS Figure 6 36 Served web page for DE2 115 118 124 51 Terasic DE2 115 User Manual
21. 3 Controlling LEDs Choosing the 7 SEG tab leads to the window shown in Figure 3 4 From the window directly use the left right arrows to control the 7 SEG patterns on the DE2 115 board which are updated immediately Note that the dots of the 7 SEGs are not enabled on DE2 115 board lt pg m e gt mm mm mm mm DISCONNECT X Figure 3 4 Controlling 7 SEG display Choosing the LCD tab leads to the window in Figure 3 5 Text can be written to the LCD display by typing it in the LCD box then pressing the Set button 17 Terasic DE2 115 User Manual www terasic com www terasic com h m B T Bal gt pg DISCONNECT Figure 3 5 Controlling the LCD display The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction 15 suspected Thus it can be used for troubleshooting purposes 3 3 Switches and Push buttons Choosing the Switches tab leads to the window in Figure 3 6 The function is designed to monitor the status of slide switches and push buttons in real time and show the status in a graphical user interface It can be used to verify the functionality of the slide switches and
22. 6 amp HSMC D HSMC D HSMC D 9 HSMC RX D P 10 HSMC D P 11 HSMC RX D P 12 HSMC D P 13 HSMC D P 14 HSMC D P 15 HSMC RX D 16 HSMC TX D NJOJ HSMC TX D N 1 HSMC TX D 2 HSMC TX D NI3 HSMC TX D N 4 HSMC TX D NI5 HSMC TX D N 6 HSMC TX D NI7 HSMC TX D 8 HSMC TX D N 9 HSMC TX D N 10 HSMC TX D N t1 PIN L23 PIN M25 PIN R25 PIN T25 PIN U25 PIN L21 PIN N25 PIN P25 PIN P21 PIN R22 PIN 121 PIN D28 PIN E28 PIN F28 PIN G28 PIN K28 PIN M28 PIN K22 PIN H24 PIN J24 PIN P28 PIN J26 PIN L28 LVDS RX bit 6 or CMOS I O LVDS RX bit 7 or CMOS I O LVDS RX bit 8 or CMOS I O LVDS RX bit 9 or CMOS I O LVDS RX bit 10 or CMOS I O LVDS RX bit 11 or CMOS I O LVDS RX bit 12 or CMOS I O LVDS RX bit 13 CMOS I O LVDS RX bit 14 or CMOS I O LVDS RX bit 15 or CMOS I O LVDS RX bit 16 or CMOS I O LVDS TX bit On or CMOS I O LVDS TX bit 1n or CMOS I O LVDS TX bit 2n or CMOS I O LVDS TX bit 3n or CMOS I O LVDS TX bit 4n or CMOS I O LVDS TX bit 5n or CMOS I O LVDS TX bit 6n or CMOS I O LVDS TX bit 7n or CMOS I O LVDS TX bit 8n or CMOS I O LVDS TX bit 9n or CMOS I O LVDS TX bit 10n or CMOS I O LVDS TX bit 11n or CMOS I O 44 Terasic DE2 115 User Manual www terasic com Depending on JP7 Depending on JP7 Depending on JP7
23. Control Panel user interface shown in Figure 3 1 will appear Terasic DE2 115 User Manual www terasic com www terasic com NOTE RIA 5 DE2 115 ControlPanel sof bit stream is loaded automatically as soon as the amp DE2 115 control panel exe is launched 6 In case the connection is disconnected click on CONNECT where sof will be re loaded onto the board 7 Note the Control Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until the USB port is closed 8 Control Panel is now ready for use experience it by setting the ON OFF status for some LEDs and observing the result on the DE2 115 board S LGH Figure 3 1 DE2 115 Control Panel The concept of the DE2 115 Control Panel is illustrated in Figure 3 2 The Control Circuit that performs the control functions 15 implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to issue commands to the control circuit It handles all requests and performs data transfers between the computer and the DE2 115 board 15 Terasic DE2 115 User Manual www terasic com www terasic com 7 SEG Display IR Receiver ri RS 232 VGA HSMC 4 gt PS 2 Mouse USB Device Button lt Sz Car YE
24. DQ 24 5 SDRAM Data 24 3 3V DRAM DQ 25 PIN R7 SDRAM Data 25 3 3V DRAM DQ 26 PIN R1 SDRAM Data 26 3 3V DRAM DQ 27 PIN R2 SDRAM Data 27 3 3V DRAM 00 28 PIN R3 SDRAM Data 28 3 3V DRAM_DQ 29 13 SDRAM Data 29 3 3V DRAM DQ 30 PIN U4 SDRAM Data 30 3 3V DRAM DQ 31 PIN U1 SDRAM Data 31 3 3V DRAM 80 PIN U7 SDRAM Bank Address 0 3 3V DRAM BA 1 R4 SDRAM Bank Address 1 3 3V DRAM U2 SDRAM byte Data Mask 0 3 3V DRAM DQN 1 W4 SDRAM byte Data Mask 1 3 3V DRAM DQN 2 PIN K8 SDRAM byte Data Mask 2 3 3V DRAM 8 SDRAM byte Data Mask 3 3 3V DRAM RAS PIN U6 SDRAM Row Address Strobe 3 3V DRAM CAS N PIN V7 SDRAM Column Address Strobe 3 3V DRAM AA6 SDRAM Clock Enable 3 3V DRAM CLK 5 SDRAM Clock 3 3V DRAM WE_N PIN V6 SDRAM Write Enable 3 3V DRAM CS PIN 14 SDRAM Chip Select 3 3V Table 4 29 Flash Pin Assignments Signal Name FPGA Pin No Description Standard FL ADDR 0 12 FLASH Address 0 3 3V 68 wwwW terasic com Terasic DE2 115 User Manual www terasic com YU RIA FLASH Write Protect Programming Acceleration 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V Standard 3 3V 3 3V IO Standard 3 3V FL ADDR 1 FLASH Address 1 F
25. GPIO 20 GPIO 21 AD22 AG25 GPIO 22 GPIO 23 AD25 AH25 GPIO 24 GPIO 25 AE25 3 3 GND 22 GPIO 26 GPIO 27 AE24 AH22 GPIO 28 GPIO 29 AF26 AE20 GPIO 30 GPIO 31 AG23 AF20 GPIO 32 GPIO 33 AH26 AH23 GPIO 34 GPIO 35 AG26 Figure 4 15 GPIO Pin Arrangement Table 4 10 Power Supply of the Expansion Header Supplied Voltage Current Limit BBV Each pin on the expansion headers is connected to two diodes and a resistor that provides protection against high and low voltages Figure 4 16 shows the protection circuitry for only one of the pin on the header but this circuitry 15 included for all 36 data pins 46 Terasic DE2 115 User Manual www terasic com www terasic com GPIO 600 _ JP5 GPIO 35 0 4 3 Figure 4 16 Connections between the GPIO connector and Cyclone IV E FPGA The voltage level of the I O pins on the expansion headers can be adjusted to 3 3V 2 5V 1 8V 1 5V using JP6 The default value is 3 3V see Figure 4 17 Because the expansion I Os are connected to Bank 4 of the FPGA and the VCCIO voltage VCCIO4 of this bank is controlled by the header JP6 users can use a jumper to select the input voltage VCCIO4 to 3 3V 2 5V 1 8V 1 5V to control the voltage level of the I O pins Table 4 11 lists the jumper settings of t
26. I O Standards JP7 Jumper Settings Supplied Voltage to VCCIO5 amp VCCIO6 IO of HSMC Connector 8 Short Pins 1 and 2 gt 1 PN Short Pins 3 and 4 Short Pins 5 and 6 T Default Short Pins 7 48 3 3 Note Users that connect a daughter the HSMC connector need to pay close attention the standard between DE2 115 HSMC connector pins and daughter card system For example if the O standard of HSMC pins on DE2 115 board is set to 1 8V a daughter card with 3 3V I O standard may not work properly on DE2 115 board due to 1 0 standard mismatch Additionally when LVDS is used as the I O standard of the HSMC connector the LVDS receivers need to assemble a 100 Ohm resistor between two input signals for each pairs as shown in Figure 4 14 Table 4 9 shows all the pin assignments of the HSMC connector 41 Terasic DE2 115 User Manual www terasic com www terasic com NOS RIA Transmitting Device Figure 4 14 LVDS interface HSMC connector and Cyclone IV E FPGA Signal Name HSMC_CLKINO HSMC CLKIN N1 HSMC CLKIN N2 HSMC CLKIN P1 HSMC CLKIN P2 HSMC CLKOUTO Xout HSMC 4 1000 lt HSMC RX D N Input Buffer Table 4 9 Pin Assignments for HSMC connector FPGA Pin No PIN AH15 PIN J28 PIN Y28 PIN J27 PIN Y27 PIN AD28 HSMC CLKOUT N1 PIN G24 HSMC CLKOUT N2PIN V24 HSMC CLKOUT P1 PIN G23 HSMC CLKOUT P2 PI
27. SITETONE functions in the audio chip Finally users can obtain the status of the SD music player from the 16x2 LCD module the 7 segment display and the LEDs The top and bottom row of the LCD module will display the file name of the music that is played on the DE2 115 board and the value of music volume respectively The 7 segment displays will show the elapsed time of the playing music file The LED will indicate the audio signal strength B Demonstration Setup File Locations and Instructions Project directory DE2 115 SD Card Audio Player Bit stream used DE2 115 SD Card Audio Player sof e Nios II Workspace DE2 115 SD Card Audio Player Software e Format your SD Card into FAT16 FAT32 format e Place the wave files to the root directory of the SD Card The provided wave files must have a sample rate of either 96K 48K 44 1K 32K or 8K In addition the wave files must be stereo and 16 bits per channel e Load the bitstream into the FPGA on the DE2 115 board note 1 e Run the Nios II Software under the workspace DE2 115 SD Card Audio PlayerNVsoftware note 1 93 Terasic DE2 115 User Manual www terasic com www terasic NO RIA Connect a headset or speaker to the DE2 115 board and you should be able to hear the music played from the SD Card e Press KEY3 on the DE2 115 board to play the next music file stored in the SD Card e Press KEY2 and KEYI to increase and decrease the output music volume respe
28. System CD Users can copy the whole folder to a host computer without installing the utility Launch the DE2 115 System Builder by executing the DE2_115_SystemBuilder exe on the host computer and the GUI window will appear as shown in Figure 5 2 12 DE2 115 User Manual www terasic com www terasic com Terasic DE2 115 System Builder 101 System Configuration UNIVERSITY Project Name PROGRAM www terasic com DE2 115 DE2 115 FPGA Board CLOCK RS232 LED 27 T Segement x 8 Button x 4 v Switch x 18 PS2 SDCARD LCD SDRAM 128MB FLASH 8MB SRAM 2MB SMA Audio USB Ethernet 1 Ethernet 2 Decoder EJTAG IR Receiver EEPROM 32Kb 4 lt 8888 Tm 4 GPIO Header gt IO Voltage 3 3 V Default HSMC 25V Default Load Setting Locis Save Setting Figure 5 2 DE2 115 System Builder window Input Project Name Input project name as show in Figure 5 3 Project Name Type in an appropriate name here it will automatically be assigned as the name of your top level design entity 73 Terasic DE2 115 User Manual www terasic com www terasic com Terasic DE2 115 System Builder 101 NOTE RYAN UNIVERSITY PROGRAM M www terasic com DE2 115 FPGA Board 1 23 AT 2 222 TT at
29. TD VS To Control the Initial Sequence TCP ANA 99198 Demonstration Setup File Locations and Instructions e Project directory DE2_115_TV e Bit stream used DE2 115 TV sof or DE2 115 TV pof e Connect DVD player s composite video output yellow plug to the Video In RCA jack J12 of the DE2 115 board The DVD player has to be configured to provide NTSC output 60Hz refresh rate 4 3 aspect ratio Non progressive video O O X e Connect VGA output of the DE2 115 board to a VGA monitor both LCD and CRT type of monitors should work e Connect the audio output of the DVD player to the line in port of the DE2 115 board and connect a speaker to the line out port If the audio output jacks from the DVD player are RCA type then an adaptor will be needed to convert to the mini stereo plug supported on the DE2 115 board this 1s the same type of plug supported on most computers e Load the bit stream into FPGA by execute the batch file de2 115 tv bat under DE2 115 TVMdemo batch folder 81 Terasic DE2 115 User Manual www terasic com www terasic com AND RIA e Press KEYO the DE2 115 board to reset the circuit amp Q Note If the HSMC loopback adapter is mounted I2C SCL will be directly routed back to 2 SDA Because audio chip TV decoder chip and HSMC share one I2C bus therefore audio and video chip won t function correctly Figure 6 2 illustrates the setup for
30. The setup for the SD music player demonstration 6 8 PS 2 Mouse Demonstration We offer this simple PS 2 controller coded in Verilog HDL to demonstrate bidirectional communication between PS 2 controller and the device the PS 2 mouse You can treat it as a how to basis and develop your own controller that could accomplish more sophisticated instructions like setting the sampling rate or resolution which need to transfer two data bytes For detailed information about the PS 2 protocol please perform an appropriate search on various educational web sites Here we give a brief introduction B Outline 5 2 protocol use two wires for bidirectional communication one clock line and one data line The PS 2 controller always has total control over the transmission line but the PS 2 device generates clock signal during data transmission 95 Terasic DE2 115 User Manual www terasic com www terasic com NO RIA Data transmit from the device to controller After sending an enabling instruction to the PS 2 mouse at stream mode the device starts to send displacement data out which consists of 33 bits The frame data is cut into three similar slices each of them containing a start bit always zero and eight data bits with LSB first one parity check bit odd check and one stop bit always one PS 2 controller samples the data line at the falling edge of the PS 2 clock signal This could easily be implemented using a s
31. a USB connection 15 established between PC and DE2 115 board it 15 able to control and read 84 Terasic DE2 115 User Manual www terasic com www terasic com YU S RYA the status of specific components by using the USB Controller program such as apply the LED Page to illumine the leds or go it out or select the Button Switch page to monitor the status of the Button amp Switch a Link to Host PC Setup Package Enumeration Information lt Communication gt Peripherals Figure 6 5 Block diagram of the USB device demonstration Demonstration Setup File Locations and Instructions Project directory DE2 115 NIOS DEVICE Bit stream used DE2 115 NIOS DEVICE LED sof Quartus project DE2 115 5 DEVICEHW Nios II Workspace DE2_115_NIOS_DEVICE HW Software PC Software DE2 115 NIOS DEVICE SW Connect the USB Device connector of the DE2 115 board to the host computer using a USB cable Execute DE2 115 NIOS DEVICE demo_batch FPGA_bat test bat A new USB hardware device will be detected Specify the location of the driver as DE2 115 NIOS DEVICE demo_batch PC driver cyusb inf Terasic EZO USB Note If failed to install the driver due to digital signature verification You can reboot press F8 to enter the advanced options and then disable digital signature verification The host computer should report that a Terasic EZO USB is now installed Execute the software located DE2 1
32. automatically loaded from the configuration device into the FPGA every time while power is applied to the board Using the Ouartus II software it is possible to reconfigure the FPGA at any time and it 15 also possible to change the non volatile data that 15 stored in the serial configuration device Both types of programming methods described below 1 programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone IV E FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration information will be lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCS64 serial configuration device It provides non volatile storage of the bit stream 50 that the information 15 retained even when the power supply to the DE2 115 board is turned off When the board s power is turned on the configuration data in the EPCS64 device is automatically loaded into the Cyclone E FPGA JTAG Chain on DE2 115 Board To use JTAG interface for configuring FPGA device the JTAG chain on DE2 115 must form a close loop that allows Quartus II programmer to detect FPGA device Figure 4 1 illustrates the 29 Terasic DE2 115 User Manual www terasic com www terasic com YU S RYAN
33. board or be used as a debug tool while developing RTL code This chapter first presents some basic functions of the Control Panel then describes its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup The Control Panel Software Utility 15 located in the directory DE2 115 tools DE2 115 control panel in the DE2 115 System CD It s free of installation just copy the whole folder to your host computer and launch the control panel by executing the DE2 115 ControlPanel exe Windows 7 64 bit Users If an error message that shows a missing client dll file cannot find jtag client dll while the Control Panel is commencing users should re launch the DE4_ControlPanel exe from the following directory DE2_115_tools DE2_115_control_panel win7_64bits Specific control circuit should be downloaded to your FPGA board before the control panel can request it to perform required tasks The program will call Quartus tools to download the control circuit to the FPGA board through USB Blaster US B 0 connection To activate the Control Panel perform the following steps 1 sure Quartus II 10 0 or later version is installed successfully on your PC 2 Set the RUN PROG switch to the RUN position 3 Connect the supplied USB cable to the USB Blaster port connect the 12V power supply and turn the power switch ON 4 Start the executable DE2_115_ControlPanel exe on the host computer The
34. host peripheral controller The host and device controllers are compliant with the Universal Serial Bus Specification Rev 2 0 supporting data transfer at full speed 12 Mbit s and low speed 1 5 Mbit s Figure 4 31 shows the schematic diagram of the USB circuitry The interface between CY7C67200 and FPGA 15 set to Host Port Interface HPI which can provide DMA access to the CY7C67200 internal memory by FPGA plus a bidirectional mailbox register for supporting high level communication protocols Also the pin assignments for the associated interface are listed in Table 4 25 Detailed information for using the CY7C67200 device is available in its datasheet programming guide both documents can be found on the manufacturer s website or in the DE2_115_datasheets USB folder on the DE2 115 System CD The most challenging part of a USB application is in the design of the software driver needed Two complete examples of USB drivers for both host and device applications can be found in Sections 6 4 and 6 5 These demonstrations provide examples of software drivers for the Nios II processor 61 Terasic DE2 115 User Manual www terasic com www terasic com A DTE RYAN Cyclone IV Signal Name OTG_ADDR 0 OTG_ADDR 1 DATA O DATA 1 OTG_DATA 2 OTG DATAI3I OTG DATA 4 OTG DATA 5 OTG DATA 6 OTG DATAITI OTG DATAI8I OTG DATA 9 OTG DATA 10 OTG DATA 11 OTG DATA 12 OTG DATA 13 OTG DATA 14 OTG DATA 15 O
35. protocol to communicate with the TV Decoder chip Following the power on sequence the TV Decoder chip will be unstable for a time period the Lock Detector 15 responsible for detecting this instability The ITU R 656 Decoder block extracts YcrCb 4 2 2 YUV 4 2 2 video signals from the ITU R 656 data stream sent from the TV Decoder It also generates a data valid control signal indicating the valid period of data output Because the video signal from the TV Decoder 15 interlaced we need to perform de interlacing on the data source We used the SDRAM Frame Buffer and a field selection multiplexer which is controlled by the controller to perform the de interlacing operation Internally the VGA Controller generates data request and odd even selection signals to the SDRAM Frame Buffer and filed selection multiplexer MUX YUVA22 to YUV444 block converts the selected YcrCb 4 2 2 YUV 4 2 2 video data to the YcrCb 4 4 4 YUV 4 4 4 video 80 Terasic DE2 115 User Manual www terasic com www terasic com AND RIA data format Finally the YcrCb_to_RGB block converts the YcrCb data into RGB data output The VGA Controller block generates standard VGA synchronous signals VGA_HS and VGA_VS to enable the display on a VGA monitor FPGA 4 2 2 HD DATA Data Valid Valid Ee 2 SCLK Figure 6 1 Block diagram of the TV box demonstration CC y CZ PPO TD HS
36. push buttons 18 Terasic DE2 115 User Manual www terasic com www terasic com lt 00000000 E ii 41 S10 USB MC Figure 3 6 Monitoring switches and buttons The ability to check the status of push button and slide switch 1s not needed in typical design activities However it provides users a simple mechanism for verifying if the buttons and switches are functioning correctly Thus it can be used for troubleshooting purposes 3 4 SDRAM SRAM EEPROM Flash Controller and Program mer The Control Panel can be used to write read data to from the SDRAM SRAM EEPROM and Flash chips on the DE2 115 board As an example we will describe how the SDRAM may be accessed the same approach is used to access the SRAM EEPROM and Flash Click on the Memory tab and select SDRAM to reach the window in Figure 3 7 Terasic DE2 115 User Manual www terasic com www terasic co m Se har P 00000000 I File Length Be agam 00000 MEO E CAAS cometioaric oiscomeer NM Figure 3 7 Accessing the SDRAM A 16 bit word can be written into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 7 depicts the result of writing the hexadecimal value 06CA into offset address 200 followed by reading the same location The
37. receiver module it is only compatible with the 38KHz carrier Standard with a maximum data rate of about 4kbps for its product information The accompanied remote controller with an encoding chip of uPD6121G 1s very suitable of generating expected infrared signals Figure 4 32 shows the related schematic of the IR receiver and the pin assignments of the associated interface are listed Table 4 26 VCC3P3 U21 am IRDA RXD S RYAN di VCC3P3 gt GND CHASSIS Figure 4 32 Connection between FPGA and IR Table 4 26 IR Pin Assignments FPGA Pin No Description vO Standard Signal Name IRDA_RXD 4 19 Using SRAM SDRAM FLASH EEPROM SD Card SRAM The DE2 115 board has 2MB SRAM memory with 16 bit data width Being featured with a maximum performance frequency of about 125MHz under the condition of standard 3 3V single power supply makes it suitable of dealing with high speed media processing applications that need 15 IR Receiver 3 3V ultra data throughput The related schematic is shown in Figure 4 33 63 Terasic DE2 115 User Manual www terasic com www terasic com 017 19 0 0 15 0 SRAM ADDR 19 0 SRAM DQ 15 0 SRAM CE N SRAM OE N SRAM WE N SRAM UB N SRAM LB N Figure 4 33 Connections between FPGA and SRAM B SDRAM The board features 128MB of SDRAM implemented using two 64MB SDRAM d
38. should set up proper values for the PHY chip 88E1111 The MDIO Module should be included as it 15 used to generate a 2 5MHz MDC clock for the PHY chip from the controller s source clock here a 100MHz clock source is expected to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface The MAC control register interface clock frequency is 100MHz and the desired MDC clock frequency is 2 5MHz so a host clock divisor of 40 should be used 110 Terasic DE2 115 User Manual www terasic com www terasic com Documentation X PCS SGMII Options Core Configuration Options gt FIFO Options Ethernet MAC Options v Enable MAC 10 100 half duplex support v Enable local loopback on MIKGMI RGMII Enable supplemental MAC unicast addresses v include statistics counters Enable 64 bit statistics byte counters include multicast hashtable v Align packet headers to 32 bit boundary _ Enable full duplex flow control Enable VLAN detection Figure 6 29 MAC Options Configuration Once the Triple Speed Ethernet IP configuration has been set and necessary hardware connections have been made as shown in Figure 6 30 click on generate 111 Terasic DE2 115 User Manual www terasic com www terasic com Module Name Description Clock Base End Tags IRQ El usb ISP1362_IF Avalon Memory Mapped Slave al
39. terasic com NOT RIA Interface via 7 1 and 7 2 for Ethernet 0 and Ethernet 1 respectively Table 6 9 shows the project name of web server demonstration for each Ethernet Port and working mode Table 6 9 Demo Directory Paths PHY project directory ENETO ENET1 Interface DE2 115 Web Serven DE2 115 Web Serven RGMI interface pe 115 WEB SERVER RGMII ENETO DE2 115 WEB SERVER RGMII DE2 115 Web Serven DE2 115 Web Serven Mil interface pe 115 WEB SERVER ENETO DE2 115 WEB SERVER B Demonstration Setup File Locations and Instructions The Following steps describe how to setup a Web Server demonstration on the ENETO in RGMII mode Before running the demonstration please copy the demonstration file to your host PC from DE2 115 demonstrations folder on the DE2 115 System CD Demonstration Source Code e Project directory DE2 115 Web Server DE2 115 WEB SERVER RGMII e Bit stream used DE2 115 WEB SERVER sof e Nios II Workspace DE2 115 WEB SERVER RGMII ENETO Software Demonstration Batch File Demo batch file Folder for this demonstration DE2 115 Web ServerN DE2 115 WEB SERVER RGMII ENETO Nlemo batch The demo batch file includes the following files e Batch File DE2 115 WEB SERVER bat DE2 115 WEB SERVER bashrc FPGA Configure File DE2 115 WEB SERVER sof 115 Terasic DE2 115 User Manual www terasic com www terasic com NDS RIA e Nios II Program web_se
40. terasic com www terasic com DEMOO1 ee VGA HS E VGA VS VGA CLK KEY 1 DEMOO2 o E SOUND1 VGA B CODE SOUND2 CODE E Ec SOUND1 CODE SOUND2 5 2 4 KEY2 SOUND1OFF gt _CODE SOUND2 SWI9 SWIO SWI2 1 Figure 6 23 Block diagram of the Music Synthesizer design Demonstration Setup File Locations and Instructions e Project directory DE2 115 Synthesizer e Bit stream used DE2 115 Synthesizer sof or DE2 115 Synthesizer pof e Connect a PS 2 Keyboard to the DE2 115 board e Connect VGA output of the DE2 115 board to a VGA monitor both LCD and CRT type of monitors should work e Connect the lineout of the DE2 115 board to a speaker Load the bit stream into FPGA by executing DE2 115 Synthesizerdemo batchDE2 115 Synthesizer bat file e Make sure all the switches SW 9 0 are set to 0 Down Position Press on the DE2 115 board to start the music demo e Press KEYO on the DE2 115 board to reset the circuit ote If the HSMC loopback adapter is mounted 2 5 will be directly routed back to I2C SDA Because audio chip TV decoder chip and HSMC share bus therefore audio and video chip won t function correctly 103 Terasic DE2 115 User Manual www terasic com www terasic com NOTES RYA Table 6 5 and Table 6 6 illustrate the usage of the slide sw
41. the audio chip The audio chip is programmed through I2C protocol which is implemented in C code The I2C pins from audio chip are connected to SOPC System Interconnect Fabric through PIO controllers In this example the audio chip is configured in Master Mode The audio interface is configured as I2S and 16 bit mode 18 432MHz clock generated by the PLL 1s connected to the XTI MCLK pin of the audio chip through the AUDIO Controller 106 Terasic DE2 115 User Manual www terasic com www terasic com Store Audio Data Nios II Program LED KEY SWII2C ouqe J 0 LCD Clock to SDRAM 4 C TT Figure 6 26 Block diagram of the audio recorder and player B Demonstration Setup File Locations and Instructions e Hardware Project directory DE2 115 AUDIO e Bit stream used DE2 115 AUDIO sof e Software Project directory DE2 115 AUDIO software e Connect an Audio Source to the LINE IN port of the DE2 115 board e Connect a Microphone to MIC IN port on the DE2 115 board e Connect a speaker or headset to LINE OUT port on the DE2 115 board e Load the bit stream into FPGA note 1 e Load the Software Execution File into FPGA note 71 e Configure audio with the Slide switches e Press KEY3 on the DE2 115 board to start stop audio recoding note 72 Press KEY2 on the DE2 115 board to start stop audio p
42. to Section 3 1 Figure 3 15 depicts the structure of the Control Panel Each input output device is controlled by the Nios Processor instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link The Nios interprets the commands sent from the PC and performs the corresponding actions 27 DE2 115 User Manual www terasic com www terasic com FPGA SOPC JTAG Blaster Hardware peuuodsaju lt gt HSMC VGA CNN z LED Button Switch SDCard SDRAM lt gt Flash SRAM Figure 3 15 The block diagram of the DE2 115 control panel Terasic DE2 115 User Manual www terasic com www terasic com 4 Using the DE2 115 Board This chapter gives instructions for using the DE2 115 board and describes each of its peripherals 4 1 Configuring the Cyclone IV E FPGA The procedure for downloading a circuit from a host computer to the DE2 115 board is described in the tutorial Quartus II Introduction This tutorial 1s found in DE2 115 tutorials folder on the DE2 115 System CD The user is encouraged to read the tutorial first and treat the information below as a short reference The DE2 115 board contains a serial configuration device that stores configuration data for the Cyclone IV E FPGA This configuration data is
43. various educational website for example search for VGA signal timing Figure 4 22 illustrates the basic timing reguirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization hsync input of the monitor which signifies the end of one row of data and the start of the next The data RGB output to the monitor must be off driven to 0 for time period called the back porch b after the hsync pulse occurs which is followed by the display interval c During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of the vertical synchronization vsync 15 the similar as shown in Figure 4 22 except that vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 4 14 and Table 4 15 show different resolutions and durations of time periods a b c and d for both horizontal and vertical timing 51 Terasic DE2 115 User Manual www terasic com www terasic com NOTE RIA Detailed information for using the ADV7123 video DAC is available in its datasheet which be found on the manufacturer s website or in the DE2 115 datasheets VIDEO D
44. 15 NIOS DEVICE demo USB Control exe on the host computer Then experiment with the program o LCD 7SEG Control Setting LCD and 7SEG o LED Control Light or unlight LEDs 85 Terasic DE2 115 User Manual www terasic com www terasic NOE RIA Button Switch Control display the status of button and switches o Hot plug Reconnect Figure 6 6 illustrates the setup for this demonstration ILLI EI ERIT am um um II m REI LET feel E E m Peripheral Driver LCD 7SEG LED BUTTON SW Figure 6 6 Setup for the USB device demonstration 6 5 Karaoke Machine This demonstration uses the microphone in line in and line out ports on the DE2 115 board to create a Karaoke Machine application The Wolfson WM8731 audio CODEC is configured in the master mode with which the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 6 7 the 2 interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set in this manner and 86 Terasic DE2 115 User Manual www terasic com www terasic com AND 8 RIA the data input from the line in port is then mixed with the microphone in port and the result is sent to the line out port For this demo
45. 4 5 Seven Segment Digit 4 6 Seven Segment Digit 5 0 Seven Segment Digit 5 1 Seven Segment Digit 5 2 Seven Segment Digit 5 3 Seven Segment Digit 5 4 Seven Segment Digit 5 5 Seven Segment Digit 5 6 Seven Segment Digit 6 0 Seven Segment Digit 6 1 Seven Segment Digit 6 2 Seven Segment Digit 6 3 Seven Segment Digit 6 4 Seven Segment Digit 6 5 37 2 115 User Manual www terasic com Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 Depending on JP6 wwwW terasic com ND RIA amp HEX6 6 17 Seven Segment Digit 6 6 Depending on JP6 HEX7 0 AD17 Seven Segment Digit 70 Depending on JP6 HEX7 1 17 Seven Segment Digit 71 Depending on JP6 HEX7 2
46. 5 4 6 510 5 1 5 2 5 3 5 4 5 5 5 6 HEX6 0 HEX6 1 HEX6 2 HEX6 3 HEX6 4 HEX6 5 PIN L26 PIN L25 PIN J22 PIN H22 PIN M24 PIN Y22 PIN W21 PIN W22 PIN W25 PIN U23 PIN U24 PIN AA25 PIN AA26 PIN Y25 PIN W26 PIN Y26 PIN W27 PIN W28 PIN V21 PIN U21 PIN AB20 21 AD24 AF23 19 19 19 21 21 19 19 18 AD18 18 18 19 AG19 18 18 17 16 16 17 15 15 Seven Segment Digit 0 3 Seven Segment Digit O 4 Seven Segment Digit 0 5 Seven Segment Digit O 6 Seven Segment Digit 1 0 Seven Segment Digit 1 1 Seven Segment Digit 1 2 Seven Segment Digit 1 3 Seven Segment Digit 1 4 Seven Segment Digit 1 5 Seven Segment Digit 1 6 Seven Segment Digit 2 0 Seven Segment Digit 2 1 Seven Segment Digit 2 2 Seven Segment Digit 2 3 Seven Segment Digit 2 4 Seven Segment Digit 2 5 Seven Segment Digit 2 6 Seven Segment Digit 3 0 Seven Segment Digit 3 1 Seven Segment Digit 3 2 Seven Segment Digit 3 3 Seven Segment Digit 3 4 Seven Segment Digit 3 5 Seven Segment Digit 3 6 Seven Segment Digit 4 0 Seven Segment Digit 4 1 Seven Segment Digit 4 2 Seven Segment Digit 4 3 Seven Segment Digit 4 4 Seven Segment Digit
47. 5 board bottom view The DE2 115 board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the DE2 115 board e Altera Cyclone 4CE115 FPGA device e Altera Serial Configuration device EPCS64 e USB Blaster on board for programming both JTAG and Active Serial AS programming modes are supported 2MB SRAM e Two 64MB SDRAM 8MB Flash memory e SD Card socket e 4 Push buttons e 18 Slide switches e 18 Red user LEDs e 9 Green user LEDs e 50MHz oscillator for clock sources 24 bit CD quality audio CODEC with line in line out and microphone in jacks e VGA DAC 8 bit high speed triple DACs with VGA out connector TV Decoder NTSC PAL SECAM and TV in connector e 2 Gigabit Ethernet PHY with RJ45 connectors e USB Host Slave Controller with USB type A and type connectors e RS 222 transceiver and 9 pin connector Terasic DE2 115 User Manual www terasic com www terasic com NOTE RIA PS 2 mouse keyboard connector IR Receiver e 2SMA connectors for external clock input output e 40 Expansion Header with diode protection e High Speed Mezzanine Card HSMC connector 16x2 LCD module amp In addition to these hardware features the DE2 115 board has software support for standard I O interfaces and a control panel facility for accessing various compon
48. 5_SD_CARD Software Demonstration Batch File Demo Batch File Folder DE2 115 SD CARD Memo batch The demo batch file includes the following files e Batch File DE2 115 SD Card bat DE2 115 SD CARD bashrc FPGA Configure File DE2 115 SD CARD sof e Nios II Program DE2 115 SD CARD elf Demonstration Setup e Make sure Quartus II and Nios II are installed on your PC e Power the DE2 115 board e Connect USB Blaster to the DE2 115 board and install USB Blaster driver if necessary e Execute the demo batch file DE2 115 SD Card bat under the batch file folder DE2 115 SD CARDNdemo batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e Copy test files to the root directory of the SD Card e Insert the SD Card into the SD Card socket of DE2 115 as shown in Figure 6 11 e Press KEY3 of the DE2 115 board to start reading SD e The program will display SD Card information as shown in Figure 6 12 90 Terasic DE2 115 User Manual www terasic com www terasic com EN 8 az E 15 NES 0 EN a maona E Dm 55 d Fus 1 w g i np 55 css EE i M oe amp 55885 Ta 3 22 B 5 50 e 8 88 B5 i 60 0660 0660 PPP
49. 8 3 65 XGA 70Hz 1024x768 6 29 768 3 75 XGA 85Hz 1024x768 3 36 768 1 95 1280x1024 60Hz 1280x1024 3 38 1024 1 108 Table 4 16 Pin Assignments for ADV7123 Signal Name FPGA Pin No Description Standard VGA_R 0 12 VGA Red 0 3 3V VGA R 1 PIN E11 VGA Red 1 3 3V VGA R 2 PIN D10 VGA Red 2 3 3V 12 VGA Red 3 3 3V 4 10 VGA Red 4 3 3V VGA R 5 PIN J12 VGA Red 5 3 3V VGA R 6 PIN H8 VGA Red 6 3 3V VGA 7 PIN H10 VGA Red 7 3 3V VGA G O0 PIN G8 VGA Green 0 3 3V VGA G 1 PIN G11 VGA Green 1 3 3V VGA_G 2 PIN_F8 VGA Green 2 3 3V VGA_G 3 PIN_H12 VGA Green 3 3 3V VGA_G 4 8 4 3 3V VGA G 5 PIN B8 VGA Green 5 3 3V VGA G 6 PIN F10 VGA Green 6 3 3V VGA PIN C9 VGA Green 7 3 3V VGA_B 0 PIN_B10 VGA Blue 0 3 3V VGA 1 PIN_A10 VGA Blue 1 3 3V VGA_B 2 11 VGA Blue 2 3 3V 811 VGA Blue 3 3 3V VGA 4 PIN A11 Blue 4 3 3V VGA B 5 PIN C12 VGA Blue 5 3 3V VGA 6 PIN D11 Blue 6 3 3V VGA 7 PIN D12 VGA Blue 7 3 3V VGA_CLK PIN_A12 VGA Clock 3 3V VGA_BLANK_N PIN_F11 VGA BLANK 3 3V VGA_HS PIN 13 VGA H_SYNC 3 3V VGA_VS PIN C13 VGAV SYNC 3 3V VGA SYNC N PIN C10 VGA SYNC 3 3V 4 11 Using the 24 bit Audio CODEC The DE2 115 board provides high quality 24 bit audio via the Wolfson WM8731 audio CODEC Terasic DE2 115 User Manual www terasic com 53 www terasi
50. AC folder on the DE2 115 System CD The pin assignments between the Cyclone IV E FPGA and the ADV7123 are listed in Table 4 16 An example of code that drives a display is described in Sections 6 2 and 6 3 amp Q Note The RGB data bus on DE2 115 board is 8 bit instead of 10 bit on DE2 DE2 70 board Back porch b Front porch d Display interval HSYNC sync a Figure 4 22 VGA horizontal timing specification Table 4 14 VGA Horizontal Timing Specification VGA mode Horizontal Timing Spec Configuration Resolution HxV a us b us c us d us Pixel clock MHz VGA 60Hz 640x480 3 8 1 9 25 4 0 6 25 VGA 85Hz 640x480 1 6 2 2 17 8 1 6 36 SVGA 60Hz 800x600 3 2 2 2 20 1 40 SVGA 75Hz 800x600 1 6 3 2 16 2 0 3 49 SVGA 85Hz 800x600 1 1 2 7 14 2 0 6 56 XGA 60Hz 1024x768 2 1 2 5 15 8 0 4 65 XGA 70Hz 1024x768 1 8 1 9 13 7 0 3 75 XGA 85Hz 1024x768 1 0 2 2 10 8 0 5 95 1280x1024 60Hz 1280x1024 1 0 2 3 11 9 0 4 108 Table 4 15 Vertical Timing Specification VGA mode Vertical Timing Spec Configuration Resolution HxV a lines b lines c lines d lines Pixel clock MHz VGA 60Hz 640x480 2 33 480 10 25 VGA 85Hz 640x480 3 25 480 1 36 52 Terasic DE2 115 User Manual www terasic com www terasic com AN OTE n YAN amp SVGA 60Hz 800x600 4 23 600 1 40 SVGA 75Hz 800x600 3 21 600 1 49 SVGA 85Hz 800x600 3 27 600 1 56 XGA 60Hz 1024x768 6 29 76
51. D x27 Button x 4 PS2 SDRAM 128MB SRAM 2MB Audio Ethernet 1 TV Decoder IR Receiver RS232 7 Segementx 8 Switch x 18 SDCARD LCD FLASH 8MB SMA USB Ethernet 2 EJTAG EEPROM 32Kb GPIO Header IO Voltage 3 3 V Default Prefix Name 5M Pixel Camera Figure 5 5 GPIO Expansion Group assigned in your design Users may leave this field empty B HSMC Expansion Users can connect HSMC interfaced daughter cards onto HSMC located on the DE2 115 board shown in Figure 5 6 Select the daughter card you wish to add to your design under the appropriate HSMC connector where the daughter card 15 connected to The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and IO standard Terasic DE2 115 User Manual www terasic com 76 www terasic com Terasic DE2 115 System Builder Y 101 ATERA UNIVERSITY PR Www tTerasic com OGRAM DE2 115 FPGA Board Figure 5 6 HSMC Expansion Group System Configuration Project Name 052 115 CLOCK LED x2 Button x 4 PS2 VGA SDRAM 128MB SRAM 2MB Audio Ethernet 1 Decoder IR Receiver GPIO Header RS232 Seqement x 8 Switch x 18 SDCARD LCD FLASH 8MB SMA USB Ethernet 2 EJTAG 32Kb IO Voltage 3 V Default Prefix Name 05 BM Pixel Camera HSMC
52. E2 115 User Manual www terasic com VCC3P3 JP 1 EX IO 6 EX IO 5 EX IO 4 JA DERYA Cyclone IV EX_IO 3 EX IO 2 3800000 EX IO 1 EX IO 0 LAN O VCC3P3 Figure 4 20 Connections between FPGA 14 pin general purpose I O Table 4 13 Pin Assignments for General Purpose I Os FPGA Pin No Description VO Standard PIN_J10 Extended 3 3V PIN_J14 Extended IO 1 3 3V PIN_H13 Extended 10 2 3 3V 50 www terasic com NOTE RIA amp EX IO 3 PIN H14 Extended IO 3 IO 4 14 Extended IO 4 3 3V EX IO 5 PIN E10 Extended IO 5 3 3V EX IO 6 PIN D9 Extended 1 6 3 3V 4 10 Using VGA The DE2 115 board includes 15 pin D SUB connector for VGA output The synchronization signals are provided directly from the Cyclone IV E FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC only the higher 8 bits are used is used to produce the analog data signals red green and blue It could support the SXGA standard 1280 1024 with a bandwidth of 100MHz Figure 4 21 gives the associated schematic J13 07 VGA_R 7 0 VGA 6 7 0 T VGA_B 7 0 A S RYAN VGA DAC VGA ADv7123 Ma ycioner VGA SYNC VGA BLANK N VGA VS VGA HS Figure 4 21 Connections between FPGA and VGA The timing specification for VGA synchronization and RGB red green blue data can be found on
53. E2 115 User Manual www terasic com www terasic com IMPORTANT NOTICE FOR REFERENCE DESIGNS Texas Instruments Incorporated reference designs are solely intended to assist designers Buyers who are developing systems that incorporate semiconductor products also referred to herein as components Buyer understands and agrees that Buyer remains responsible for using its independent analysis evaluation and judgment in designing Buyer s systems and products reference designs have been created using standard laboratory conditions and engineering practices has not conducted any testing other than that specifically described in the published documentation for a particular reference design may make corrections enhancements improvements and other changes to its reference designs Buyers are authorized to use reference designs with the component s identified in each particular reference design and to modify the reference design in the development of their end products HOWEVER NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY THIRD PARTY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information publis
54. ENETO TX 0 ENETO TX DATA 1 ENETO TX DATA 2 ENETO TX DATA 3 ENETO TX EN ENETO TX ER ENET1 GTX CLK ENET1 INT N ENET1 LINK100 ENET1 MDC ENET1 MDIO ENET1 RST N ENET1 RX CLK ENET1 RX COL ENET1 RX CRS ENET1 DATAIOJ Terasic DE2 115 User Manual www terasic com PHY Working Mode RGMII Mode Mil Mode Table 4 23 Pin Assignments for Fast Ethernet FPGA Pin No 17 21 14 20 21 19 15 15 D15 16 016 017 15 17 D18 17 18 D19 19 19 18 18 23 024 023 025 022 15 22 PIN 020 23 Description GMII Transmit Clock 1 Interrupt open drain output 1 Parallel LED output of 100BASE TX link 1 Management data clock reference 1 Management data 1 Hardware reset signal 1 GMII and MII receive clock 1 GMII and MII collision 1 GMII and MII carrier sense 1 GMII and MII receive data 0 1 GMII and MII receive data 1 1 GMII and MII receive data 2 1 GMII and MII receive data 3 1 GMII and MII receive data valid 1 GMII and MII receive error 1 MII transmit clock 1 MII transmit data 0 1 MII transmit data 1 1 MII transmit data 2 1 MII transmit data 3 1 GMII and MII transmit enable 1 GMII and MII transmit error 1 GMII Transmi
55. L ADDR 2 Y13 FLASH Address 2 FL ADDR 3 14 FLASH Address 3 FL ADDR 4 Y12 FLASH Address 4 FL ADDR 5 AA13 FLASH Address 5 FL ADDR 6 AA12 FLASH Address 6 FL ADDR 7 AB13 FLASH Address 7 FL ADDR 8 AB12 FLASH Address 8 FL ADDR 9 10 FLASH Address 9 FL ADDR 10 PIN AE9 FLASH Address 10 FL ADDR 11 PIN AF9 FLASH Address 11 FL ADDR 12 PIN AA10 FLASH Address 12 FL ADDR 13 PIN AD8 FLASH Address 13 FL ADDR 14 PIN AC8 FLASH Address 14 FL ADDR 15 PIN Y10 FLASH Address 15 FL ADDR 16 PIN AA8 FLASH Address 16 FL ADDR 17 PIN AH12 FLASH Address 17 FL ADDR 18 PIN AC12 FLASH Address 18 FL ADDR 19 PIN AD12 FLASH Address 19 FL ADDR 20 PIN AE10 FLASH Address 20 FL ADDR 21 PIN AD10 FLASH Address 21 FL ADDR 22 PIN AD11 FLASH Address 22 FL DQ O PIN 8 FLASH Data 0 FL DQ 1 PIN AF10 FLASH Data 1 FL DQ 2 PIN AG10 FLASH Data 2 FL DQ 3 PIN AH10 FLASH Data 3 FL DQ 4 PIN AF11 FLASH Data 4 FL DQ 5 PIN AG11 FLASH Data 5 FL DQ 6 PIN AH11 FLASH Data 6 FL PIN AF12 FLASH Data 7 FL CE N PIN AG7 FLASH Chip Enable FL OE N PIN AG8 FLASH Output Enable FL RST N PIN AE11 FLASH Reset FL RY PIN Y1 FLASH Ready Busy output FL WE N PIN AC10 FLASH Write Enable FL WP N PIN AE12 Table 4 30 EEPROM Pin Assignments Signal Name FPGA Pin No Description EEP 2 SCLK PIN D14 EEPROM clock EEP 2 SDAT PIN E14 EEPROM data Table 4 31 SD Card Socket Pin Assignments Signal N
56. MHz mii rx cik mii rx en mii rx col mii rx crs Mi IX err mii 43 Figure 6 31 PHY connected to the via Figure 6 32 shows the connections for programmable 10 100 1000Mbps Ethernet operation via 112 Terasic DE2 115 User Manual www terasic com www terasic com 2 5 25 125 2 rgmii tx tb Wie eet 4 Not Used _ _ eth_mode 10 10 100 1000 Ethernet MAC Optional tie to logic 0 if not used 3 set 1000 2 5 25 125 2 rgmii rx cik ee rom rx cel Figure 6 32 PHY connected to the MAC via RGMII After the SOPC hardware project has been built develop the SOPC software project whose basic architecture is shown in Figure 6 33 The top block contains the Nios II processor and the necessary hardware to be implemented into the DE2 115 host board The software device drivers contain the necessary device drivers needed for the Ethernet and other hardware components to work The HAL API block provides the interface for the software device drivers while the Micro C OS II provides communication services to NicheStack and Web Server The NicheStack TCP IP Stack software block provides networking services to the application block where it contains the tasks for Web Server 113 Terasic DE2 115 User Manual www terasic com www tera
57. N V23 HSMC 0 HSMC D 1 HSMC 0 21 HSMC D 3 Terasic DE2 115 User Manual www terasic com PIN AE26 PIN AE28 27 27 Description Dedicated clock input LVDS RX or CMOS input or differential clock input LVDS RX or CMOS input or differential clock input LVDS RX or CMOS input or differential clock input LVDS RX or CMOS input or differential clock input Dedicated clock output LVDS TX or CMOS 0 or differential clock output LVDS TX or CMOS I O or differential clock output LVDS TX or CMOS I O or differential clock output LVDS TX or CMOS I O or differential clock output LVDS TX or CMOS I O LVDS RX or CMOS I O LVDS TX or CMOS I O LVDS RX or CMOS I O 42 Standard Depending on JP6 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 Depending on JP7 www terasic com YU RIA HSMC RX D 01 HSMC RX D N 1 HSMC RX D NJ2 HSMC RX D N 3 HSMC RX D 41 HSMC D NI5 HSMC RX D N 6 HSMC RX D HSMC RX D 8 HSMC RX D N 9 HSMC RX D N 10 HSMC RX D N t1 HSMC RX D N 12 HSMC RX D N 13 HSMC RX D N 14 HSMC RX D N 15 HSMC RX D N 16 HSMC D HSMC D 1 HSMC RX D 2 HSMC RX D PT 3 HSMC D HSMC D 5
58. Pm UM k I T re 3 f5 ika as 13 um 29 m Ken 1 Ni TU o malam aimi 1 E he f m if C Neg 3 3 USB Blaster i i Switch SD Card SDRAM EEPROM gt Flash SRAM Figure 3 2 The DE2 115 Control Panel concept The DE2 115 Control Panel can be used to light up LEDs change the values displayed on 7 segment and LCD displays monitor buttons switches status read write the SDRAM SRAM EEPROM and Flash Memory monitor the status of an USB device communicate with the PS 2 mouse output VGA color pattern to VGA monitor verify functionality of HSMC connector I Os communicate with PC via RS 232 interface and read SD Card specification information The feature of reading writing a word or an entire file from to the Flash Memory allows the user to develop multimedia applications Flash Audio Player Flash Picture Viewer without worrying about how to build a Memory Programmer 3 2 Controlling the LEDs 7 segment Displays and LCD Display A simple function of the Control Panel is to allow setting the values displayed on LEDs 7 segment displays and the LCD character display Choosing the LED tab leads to the window in Figure 3 3 Here you can directly turn the LEDs on or off individually or by clicking Light All or Unlight All Terasic DE2 115 User Manual www terasic com www terasic com gt SDCard Figure 3
59. Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be written in the Length box If the entire file is to be loaded then a checkmark may be placed the File Length box instead of giving the number of bytes 3 To initiate the writing process click on the Write a File to Memory button 4 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Control Panel also supports loading files with a hex extension Files with a hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values For example a file containing the line 0123456789 ABCDEF Defines eight 8 bit values 01 23 45 67 89 AB CD These values will be loaded consecutively into the memory 20 Terasic DE2 115 User Manual www terasic com www terasic co m NOTE RIA The Sequential Read function is used to read the contents the SDRAM and fill them into file as follows amp 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM to be copied which involves all 128 Mbytes then place a checkmark in the Entire Memory box 3 Press Load Mem
60. TG CS N OTG RD N OTG WR N OTG RST N OTG INT Figure 4 31 Table 4 25 USB CY7C67200 Pin Assignments CY67200 OTG DATA jo o OTG ADDR 0 AiO 016 65 N zz 016 WR N um OTG RD N 016 016 RST N MAXII 12MHz EPM240 Connections between FPGA and USB CY7C67200 FPGA Pin No Description PIN H7 CY7C67200 Address 0 PIN C3 CY7C67200 Address 1 PIN J6 CY7C67200 Data 0 PIN K4 CY7C67200 Data 1 PIN J5 CY7C67200 Data 2 PIN K3 CY7C67200 Data 3 PIN J4 CY7C67200 Data 4 PIN J3 CY7C67200 Data 5 PIN J7 CY7C67200 Data 6 PIN H6 CY7C67200 Data 7 PIN H3 CY7C67200 Data 8 PIN H4 CY7C67200 Data 9 PIN G1 CY7C67200 Data 10 PIN G2 CY7C67200 Data 11 PIN G3 CY7C67200 Data 12 PIN F1 CY7C67200 Data 13 PIN F3 CY7C67200 Data 14 PIN G4 CY7C67200 Data 15 PIN A3 CY7C67200 Chip Select PIN B3 CY7C67200 Read PIN A4 CY7C67200 Write PIN C5 CY7C67200 Reset PIN D5 CY7C67200 Interrupt 4 18 Using IR DE2 115 provides an infrared remote control receiver Module model IRM V538N7 TR1 62 Terasic DE2 115 User Manual www terasic com USB A TYPE A Host USB B TYPE r 9 Device I O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com YU S RIA amp whose datasheet is offered in the DE2 115 datasheetsNMR Receiver folder on DE2 115 system CD Note that for this all in one
61. Y2 50 MHz clock input 3 3V CLOCK2 50 PIN AG14 50 MHz clock input 3 3V CLOCKS 50 PIN AG15 50 MHz clock input Depending on JP6 SMA CLKOUT PIN AE23 External SMA clock output Depending on JP6 SMA CLKIN PIN AH14 External SMA clock input 3 3V 38 wwwW terasic com Terasic DE2 115 User Manual www terasic com NOTE RIA 4 6 Using the LCD Module The LCD module has built in fonts and can be used to display text by sending appropriate commands to the display controller called HD44780 Detailed information for using the display is available in its datasheet which can be found on the manufacturer s website and from the DE2 115 datasheetsNLCD folder on the DE2 115 System CD A schematic diagram of the LCD module showing connections to the Cyclone IV E FPGA is given in Figure 4 12 The associated pin assignments appear in Table 4 6 JA DTE RA Cyclone IV 16 L5 L1 12 K7 K1 K2 M3 M5 L4 M2 M1 0 391 0 eV1Vd 401 vVLVG SV1Vd a97 991 4N1VG 091 N3 SH w 0 2 Figure 4 12 Connections between the LCD module Cyclone IV E FPGA 1 Note the current LCD modules used DE2 115 boards do not have backlight Therefore the LCD_BLON signal should not be used in users design projects Table 4 6 Pin Assignments for LCD Module
62. ame FPGA Pin No Description SD CLK PIN AE13 SD Clock 69 Terasic DE2 115 User Manual www terasic com www terasic com D CMD D DATIOJ D DAT 1 D DAT 2 D DAT 3 _ 14 _ SDDatj 0 PIN 4 50 Write Protect 70 Terasic DE2 115 User Manual www terasic com www terasic com DE2 115 System Builder This chapter describes how users can create a custom design project on the DE2 115 board by using DE2 115 Software Tool DE2 115 System Builder 5 1 Introduction The DE2 115 System Builder is a Windows based software utility designed to assist users to create Quartus II project for the DE2 115 board within minutes The generated Quartus II project files include Quartus II Project File qpf Quartus II Setting File qsf e Top Level Design File v e Synopsis Design Constraints file sdc e Pin Assignment Document htm By providing the above files DE2 115 System Builder prevents occurrence of situations that are prone to errors when users manually edit the top level design file or place pin assignments The common mistakes that users encounter are the following 1 Board damaged for wrong pin bank voltage assignments 2 Board malfunction caused by wrong device connections or missing pin counts for connected ends 3 Performance degeneration because of improper pin assignments 5 2 General Design Flow This section will introduce the gen
63. and the function prototype is defined in the header file lt io h gt The SD Card block implements SD 4 bit mode protocol for communication with SD Cards The FAT File System block implements reading function for FAT16 and FAT 32 file system Long filename is supported By calling the public FAT functions users can browse files under the root directory of the SD Card Furthermore users can open a specified file and read the contents of the file The main block implements main control of this demonstration When the program is executed it detects whether an SD Card 15 inserted If an SD Card 15 found it will check whether the SD Card is formatted as FAT file system If so it searches all files in the root directory of the FAT file system and displays their names in the nios2 terminal If a text file named test txt is found it will dump the file contents If it successfully recognizes the FAT file system it will turn on the green LED On the other hand it will turn on the red LED if it fails to parse the FAT file system or if there is no SD Card found in the SD Card socket of the DE2 115 board If users press KEY3 of the DE2 115 board the program will perform above process again 89 Terasic DE2 115 User Manual www terasic com www terasic com Figure 6 10 Software Stack the SD Card Demonstration Demonstration Source Code e Project directory DE2_115_SD_CARD e Bit stream used DE2 115 SD CARD sof e Nios Workspace DE2_11
64. artus II project should set to LVDS_E_3R GPIO JP5 GPIO TX E W Single ended TX NO M Single ended GPIO TX P1 M ME Mi Single ended I O GPIO TX M M Single ended Single ended EN Single ended 5v M MI M GND GPIO TX P2 M M MM Single ended TX N2 ME M Single ended GPIO TX P3 M M Single ended GPIO TX N3 ME MP Single ended GPIO TX H MP Single ended I O E Single ended GPIO TX 5 M M Single ended I O GPIO TX 5 M M Single ended I O 33V GND TX M Single ended I O GPIO TX 6 H Single ended I O GPIO TX ME Single ended GPIO TX 7 M Single ended Single ended Single ended 1 Figure 4 18 Pin defined when using LVDS interface on GPIO FPGA pins 48 Terasic DE2 115 User Manual www terasic com www terasic com AY RIA The factory default setting on Rs resistor will be 47 ohm and Rp resistor will not be assembled for single ended I O standard application For LVDS transmitter application please assemble 120 and 170 ohm resistor on Rs and Rp position respectively Finally Table 4 12 shows all the pin assignments of the GPIO connector GPIO F P GA Resistor Network i E Emulated LVDS Transmitter LVDS Rece
65. ay be subject to additional restrictions Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards that anticipate dangerous failures monitor failures and their consequences lessen the likelihood of dangerous failures and take appropriate remedial actions Buyer will fully indemnify and its representatives against any damages arising out of the use of any components Buyer s safety critical applications In some cases components be promoted specifically to facilitate safety related applications With such components Tl s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No components are authorized for use in FDA Class or similar life critical medical equipment unless authorized officers of the parties have executed an agreement specifically governing such use Only those components that has specifically designated as military grade or enhanced plastic are designed and intended for use military aer
66. c com NO RIA Encoder Decoder This chip supports microphone in line in and line out ports with sample rate adjustable from 8 kHz to 96 kHz The WM8731 is controlled via serial I2C bus interface which is connected to pins on the Cyclone E FPGA A schematic diagram of the audio circuitry is shown in Figure 4 23 and the FPGA pin assignments are listed in Table 4 17 Detailed information for using the WM8 31 codec is available in its datasheet which can be found on the manufacturer s website or in the DE2 115 datasheetsMudio CODEC folder on the DE2 115 System CD amp U5 WM8731 AUD AUR XTI MCLK Mic In 4 AUD BCLK BCLK AUD_DACDAT AND Line In AUD_DACLRCK J2 IV DACLRCK ADCDAT Line Out AUD ADCLRCK J3 ADCLRCK Figure 4 23 Connections between FPGA and Audio CODEC Table 4 17 Audio CODEC Pin Assignments Signal Name FPGA Pin No Description Standard AUD ADCLRCK PIN C2 Audio CODEC ADC LR Clock 3 3V AUD_ADCDAT 02 Audio CODEC ADC Data 3 3V AUD_DACLRCK PIN_E3 Audio CODEC DAC LR Clock 3 3V AUD_DACDAT PIN D1 Audio CODEC DAC Data 3 3V AUD XCK PIN E1 Audio CODEC Chip Clock 3 3V AUD BCLK PIN F2 Audio CODEC Bit Stream Clock 3 3V l2C SCLK PIN B7 2 Clock 3 3V 2 SDAT PIN A8 20 Data 3 3V Q Note If the HSMC loopback adapter is mounted 2 SCL will be directly routed back to 2 SDA Because audio chi
67. cators e 18 slide switches and 4 push buttons switches e 18 red and 9 green LEDs e Eight 7 segment displays Other features e Infrared remote control receiver module e TV decoder NTSC PAL SECAM and TV in connector Power e Desktop DC input e Switching and step down regulators LM3150MH 2 3 Power up the DE2 115 Board The DE2 115 board comes with a preloaded configuration bit stream to demonstrate some features of the board This bit stream also allows users to see quickly if the board is working properly To power up the board perform the following steps 1 Connect the provided USB cable from the host computer to the USB Blaster connector on the DE2 115 board For communication between the host and the DE2 115 board it is necessary to install the Altera USB Blaster driver software If this driver is not already installed on the host computer it can be installed as explained in the tutorial Getting Started with Altera s DE2 115 Board tut_initialDE2 115 pdf This tutorial is available in the directory DE2 115 tutorials on the DE2 115 System CD 2 Turn off the power by pressing the red ON OFF switch before connecting the 12V adapter to the DE2 115 board 3 Connect a monitor to the port on the DE2 115 board 4 Connect your headset to the line out audio port the DE2 115 board Terasic DE2 115 User Manual www terasic com www terasic com NOTE RIA 5 Turn RUN PROG switch SW19 on the left ed
68. chain on DE2 115 board Shorting pinl and pin2 on JP3 can disable the JTAG signals on HSMC connector that will form a close JTAG loop chain on DE2 115 board See Figure 4 2 Thus only the on board FPGA device Cyclone IV E will be detected by Quartus II programmer If users want to include another FPGA device or interface containing FPGA device in the chain via HSMC connector short pin2 and pin3 on JP3 to enable the JTAG signal ports on the HSMC connector USB Embedded Blaster Connector USB Controller EPM240 npe c0 Ti LN Y JP3 25 Ban Tok 4 Figure 4 2 JTAG chain configuration header The sections below describe the steps used to perform both JTAG and AS programming For both methods the DE2 115 board is connected to a host computer via a USB cable Using this connection the board will be identified by the host computer as an Altera USB Blaster device The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial Getting Started with Altera s DE2 115 Board tut_initialDE2 115 pdf This tutorial is available on DE2 115 System CD 30 Terasic DE2 115 User Manual www terasic com www terasic co m NOTES RYAN B Configuring the FPGA JTAG Mode Figure 4 3 illustrates the JTAG configuration setup To download a configuration bit stream into
69. ctively e Users can also use the remote control to play pause the music select the last next music file to play and control volume The detailed information about each function of remote controller is shown in Table 6 1 Table 6 1 Detailed information of the button on the remote controller Button Name Function Description PLAY Play music or pause music CHANNEL Select last next music file to play VOLUME Turn up down volume MUTE Mute un mute Q Note Figure 7 Execute the batch file DE2 115 SD Card Audio Player demo batch VDE2 115 SD Card Audio Player bat to download both hardware and software bit stream 2 If the capacity of your SD Memory Card 15 more than or equal SGB please make sure it has the performance more than or equal to Class 4 3 If the HSMC loopback adapter is mounted 2 SCL will be directly routed back to 2 SDA Because audio chip TV decoder chip and HSMC share one I2C bus therefore audio and video chip won t function correctly Figure 6 15 illustrates the setup for this demonstration 94 Terasic DE2 115 User Manual www terasic com www terasic com Speaker Remote Controller B M 8 M seen 50 foe eee eee eee aaa ae 6000 with music files wav AAR RAR AAAS AAA Py ry gt 0008 Audio CODEC SD Card Controller Driver On Chip Audio PCM Buffer Nios II Figure 6 15
70. de Lead Code Custom Code Figure 6 21 State shift diagram of State Machine 100 Terasic DE2 115 User Manual www terasic com www terasic NOTE RIA We apply the receiver to many applications such as integrating to SD Card Demo you can also develop other related interesting applications with it Demonstration Setup File Locations and Instructions e Project directory DE2_115_IR e Bit stream used DE2 115 IR sof e Load the bit stream into the FPGA by executing DE2_115_IR demo_batch DE2_115_IR bat file e Point the IR receiver with the remote controller and press any button Table 6 4 shows how the received code and key data display on eight 7 segment displays Table 6 4 Detailed information of the indicators Indicator Name Description Inversed low byte of Key Code HEX1 Inversed high byte of Key Code HEX2 Low byte of Key Code Figure 6 22 illustrates the setup for this demonstration Remote Controller 3 PEREON YAN 5 CES 5 7 zi WE X Y 4 AS i 3 G E eT lt c d kd aM 2 4 2 8 pem T 14 lt i A 05 19 t m m m 3 3 3 4 lt HA Fc o o o o UR LR LR LR LR LR f Custom Code Key Code IR Receiver Figur
71. detailed information about the blocks in Figure 2 3 FPGA device e Cyclone IV EP4CE115F29 device e 114 480 LEs 432 memory blocks e 3 888 Kbits embedded memory e 4PLLs FPGA configuration e JTAG and AS mode configuration e EPCS64 serial configuration device e On board USB Blaster circuitry Memory devices e 128MB 32Mx32bit SDRAM e 2MB 1Mx16 SRAM Terasic DE2 115 User Manual www terasic com www terasic com ND RIA e 8MB 4Mx16 Flash with 8 bit mode e 32Kb EEPROM amp SD Card socket e Provides SPI and 4 bit SD mode for SD Card access Connectors e Two Ethernet 10 100 1000 Mbps ports e High Speed Mezzanine Card HSMC e Configurable I O standards voltage levels 3 3 2 5 1 8 1 5V e USB type A and B Provide host and device controllers compliant with USB 2 0 Support data transfer at full speed and low speed o PC driver available 40 pin expansion port o Configurable I O standards voltage levels 3 3 2 5 1 8 1 5V VGA out connector VGA DAC high speed triple DACs e DB9 serial connector for RS 232 port with flow control e 5 2 mouse keyboard Clock e Three 50MHz oscillator clock inputs SMA connectors external clock input output Audio e 24 bit encoder decoder CODEC e Line in line out and microphone in jacks Terasic DE2 115 User Manual www terasic com www terasic com NOTE RIA amp Display 16x2 LCD module Switches and indi
72. e 6 22 The Setup of the IR receiver demonstration 101 Terasic DE2 115 User Manual www terasic com www terasic com NOTE RIA 6 10 Music Synthesizer Demonstration This demonstration shows how to implement a Multi tone Electronic Keyboard using DE2 115 board with a PS 2 Keyboard and a speaker PS 2 Keyboard 15 used as the piano keyboard for input The Cyclone E FPGA on the DE2 115 board serves as the Music Synthesizer SOC to generate music and tones The VGA connected to the DE2 115 board is used to show which key is pressed during the playing of the music Figure 6 23 shows the block diagram of the design of the Music Synthesizer There are four major blocks in the circuit DEMO SOUND PS2 KEYBOARD STAFF and TONE_GENERATOR The DEMO_SOUND block stores a demo sound for users to play 52 KEYBOARD handles the users input from PS 2 keyboard The STAFF block draws the corresponding keyboard diagram on VGA monitor when key s are pressed The TONE_GENERATOR is the core of music synthesizer SOC Users can switch the music source either from 52 KEYBOAD or the DEMO SOUND block using SW9 To repeat the demo sound users can press KEY The TONE GENERATOR has two tones 1 String 2 Brass which is controlled by SWO The audio codec used on the DE2 115 board has two channels which can be turned ON OFF using SW1 and SW2 Figure 6 24 illustrates the setup for this demonstration 102 Terasic DE2 115 User Manual www
73. e PROG position e The EPCS64 chip can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS64 device to be loaded into the FPGA chip USB Blaster Circuit RUN Quartus ll AS Mode Auto Power on amp Programmer MAX II Config Config a EPM 240 TARTU 7 QUARTUS II PROG yclon EPCS64 Figure 4 5 The AS configuration scheme 4 2 Using Push buttons and Switches The DE2 115 board provides four push button switches as shown in Figure 4 6 Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 4 7 The four outputs called KEYO KEY2 and KEY3 of the Schmitt Trigger devices are connected directly to the Cyclone IV E FPGA Each push button switch provides a high logic level when it is not pressed and provides a low logic level when depressed Since the push button switches are debounced they are appropriate for using as clock or reset inputs in a circuit 22 DE2 115 User Manual www terasic com www terasic co m There are also 18 slide switches the DE2 115 board See Figure 4 8 These switches are debounced and are assumed for use as level sensitive data
74. ents Also the software 15 provided for supporting a number of demonstrations that illustrate the advanced capabilities of the DE2 115 board In order to use the DE2 115 board the user has to be familiar with the Quartus II software The necessary knowledge can be acquired by reading the tutorials Getting Started with Altera s DE2 115 Board tut initialDE2 115 pdf and Quartus II Introduction which exists in three versions based on the design entry method used namely Verilog VHDL or schematic entry These tutorials are provided in the directory DE2 115 tutorials on the DE2 115 System CD that accompanies the DE2 115 kit and can also be found on Terasic s DE2 115 web pages 2 2 Block Diagram of the DE2 115 Board Figure 2 3 gives the block diagram of the DE2 115 board To provide maximum flexibility for the user all connections are made through the Cyclone IV E FPGA device Thus the user can configure the FPGA to implement any system design Terasic DE2 115 User Manual www terasic com www terasic com LINE TV VGA OUT fi DECODER ff OUTPUT Boo USB USB USB M BLASTER DEVICE HOST V LS LCD module X13 tm SDRAM X57 SRAM X41 Flash X37 SDRAM1 SDRAMO SRAM 7 Seg X56 9 CLKOUT 1 CLOCK X3 OSC Push buttons X4 LED X27 Adjustable Voltage Signal Figure 2 3 Block Diagram of DE2 115 Following is more
75. eral design flow to build a project for the DE2 115 board via the DE2 115 System Builder The general design flow is illustrated in Figure 5 1 Users should launch DE2 115 System Builder and create a new project according to their design requirements When users complete the settings the DE2 115 System Builder will generate two 71 Terasic DE2 115 User Manual www terasic com www terasic com NOTES RIA major files which include top level design file v and Quartus II setting file qsf amp The top level design file contains top level verilog HDL wrapper for users to add their own design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and I O standard for each user defined I O pin Finally Quartus II programmer must be used to download SOF file to DE2 115 board using JTAG interface Launch Launch Quartus and DE2 115 System Builder Open Project Create New DE2 115 System Builder Add User Design Logic Project Generate Quartus II Project and Document Compile to generate Configure FPGA Figure 5 1 general design flow of building a design 5 3 Using DE2 115 System Builder This section provides the detailed procedures on how the DE2 115 System Builder is used B Install and launch the DE2 115 System Builder The DE2 115 System Builder 15 located in the directory DE2_115_tools DE2_115_system_builder on the DE2 115
76. evices Each device consists of separate 16 bit data lines connected to the FPGA and shared control and address lines These chips use the 3 3V LVCMOS signaling standard Connections between FPGA and SDRAM are shown in Figure 4 34 DRAM DQ 15 0 DRAM DRAM 0011 DRAM Other Control Signals DRAM CKE DRAM CLK DRAM WE N DRAM CAS SDRAM 0 DRAM RAS N gt DRAM CS S RYA e DRAM BA 1 0 DRAM ADDR 12 0 013 32 16 DQ 31 16 DRAM DOM2 DRAM DQM3 Figure 4 34 Connections between FPGA and SDRAM 64 Terasic DE2 115 User Manual www terasic com www terasic com NOE RIA amp B FLASH The board 15 assembled with 8MB of flash memory using an 8 bit data bus The device uses 3 3V CMOS signaling standard Because of its non volatile property it 15 usually used for storing software binaries images sounds or other media Connections between FPGA and Flash are shown in Figure 4 35 FL ADDR 22 1 FL DQ 7 0 FL ADDRIOJ FL WE N FL RST FL FL FL CE FL OE N BYTE Mode U18 A 21 0 DQI7 0 DQ15 A 1 WE RESET WP ACC RY BY CE OE BYTE FLASH Figure 4 35 Connections between FPGA and Flash B EEPROM The board has 32Kb EEPROM With the benefit of I2C bus users could use it as residence of user data like version information MAC address or other description substance Figure 4 36 gives the schema
77. g the User Manual the Control Panel System Builder and Altera Monitor Program utility reference designs and demonstrations device datasheets tutorials and a set of laboratory exercises e CD ROMs containing Altera s Quartus II Web Edition and the Nios II Embedded Design Suit Evaluation Edition software Terasic DE2 115 User Manual www terasic com www terasic com AND RIA amp e Bag of six rubber silicon covers for the DE2 115 board stands bag also contains some extender pins which can be used to facilitate easier probing with testing equipment of the board s I O expansion headers Clear plastic cover for the board 12V DC desktop power supply e Remote controller 1 2 The DE2 115 Board Assembly To assemble the included stands for the DE2 115 board e Assemble a rubber silicon cover as shown in Figure 1 2 for each of the six copper stands on the DE2 115 board e The clear plastic cover provides extra protection and is mounted over the top of the board by using additional stands and screws Figure 1 2 The feet for the DE2 115 board Terasic DE2 115 User Manual www terasic com www terasic com AU S RIA amp 1 3 Getting Help Here 1s information of how to get help if you encounter any problem e Terasic Technologies e Tel 886 3 575 0880 e Email support terasic com e Altera Corporation e Email university altera com Terasic DE2 115 User Manual www terasic com ww
78. ge of the DE2 115 board to RUN position the PROG position is used only for the AS Mode programming amp 6 Recycle the power by turning the red power switch on the DE2 115 board OFF and ON again At this point you should observe the following All user LEDs are flashing All 7 segment displays are cycling through the numbers 0 to The LCD display shows Welcome to the Altera DE2 115 e The monitor displays the image shown in Figure 2 4 Set the slide switch SW17 to the DOWN position you should hear a 1 kHz sound careful of the very loud volume for avoiding any discomfort e Set the slide switch SW17 to the UP position and connect the output of an audio player to the line in connector on the DE2 115 board on your speaker or headset you should hear the music played from the audio player MP3 PC iPod or the like e You can also connect a microphone to the microphone in connector on the DE2 115 board your voice will be mixed with the music playing on the audio player Figure 2 4 The default VGA output pattern Terasic DE2 115 User Manual www terasic com www terasic com DE2 115 Control Panel The DE2 115 board comes with a Control Panel facility that allows users to access various components on the board from a host computer The host computer communicates with the board through a USB connection The facility can be used to verify the functionality of components on the
79. generated by DE2 115 System Builder Top level verilog HDL file for Quartus II Project name gt qpf Quartus Project File Project name gt sdc Synopsis Design Constraints file for Quartus Il Project name gt htm Pin Assignment Document Users can use Quartus II software to add custom logic into the project and compile the project to generate the SRAM Object File sof RT Project name gt qsf Quartus ll Setting File 78 Terasic DE2 115 User Manual www terasic com www terasic com 6 Examples Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DE2 115 board These circuits provide demonstrations of the major features on the board such as its audio and video capabilities USB and Ethernet connectivity For each demonstration the Cyclone IV E FPGA or EPCS64 serial EEPROM configuration file 1s provided as well as the full source code in Verilog HDL of the associated files can be found the DE2 115 demonstrations folder on the DE2 115 System CD For each demonstrations described in the following sections the name of the project directory for its files is given which are subdirectories of the DE2 115 demonstrations folder B Installing the Demonstrations To install the demonstrations on your computer Copy the directory DE2 115 demonstrations into a local directory of your choice It is important to ensure that the path to yo
80. he JP6 The pin outs of the JP6 appear in Figure 4 17 Ors INSTRUMENTS i Ve JEU Eamptu use tools Simple wi E i d d Figure 4 17 GPIO supply voltage setting header 47 Terasic DE2 115 User Manual www terasic com www terasic com AU S RIA amp Table 4 11 Voltage Level Setting of the Expansion Headers Using JP6 JP6 Jumper Settings Supplied Voltage VCCIO4 IO Voltage of Expansion Headers JP5 Short Pins 1 and 2 41 5V 1 5V Short Pins 3 and 4 1 8V 1 8 Short Pins 5 and 6 2 5V 2 5V Short Pins 7 and 8 3 3V 3 3V Default Note Users who want to use daughter on GPIO connector need to pay close attention to the O standard between DE2 115 GPIO connector pins and daughter card system For example if the YO standard of GPIO pins on DE2 115 board is set to 1 8V a daughter card with 3 3V O standard not work properly on the DE2 115 board due to I O standard mismatch Figure 4 18 depicts the pin definition on the expansion connector for using these I Os as LVDS transmitters Due to the reason that the column I Os of the FPGA the expansion pins connecting with can only support emulated LVDS transmitters two single ended output buffers and external resistors must be used as shown in Figure 4 19 The associated I O standard of these differential FPGA I O pins on Qu
81. hed by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from under the patents or other intellectual property of TI REFERENCE DESIGNS ARE PROVIDED AS IS TI MAKES NO WARRANTIES OR REPRESENTATIONS WITH REGARD TO THE REFERENCE DESIGNS OR USE OF THE REFERENCE DESIGNS EXPRESS IMPLIED OR STATUTORY INCLUDING ACCURACY OR COMPLETENESS TI DISCLAIMS ANY WARRANTY OF TITLE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE QUIET ENJOYMENT QUIET POSSESSION AND NON INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO TI REFERENCE DESIGNS OR USE THEREOF TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY BUYERS AGAINST ANY THIRD PARTY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON A COMBINATION OF COMPONENTS PROVIDED IN A TI REFERENCE DESIGN IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL SPECIAL INCIDENTAL CONSEQUENTIAL OR INDIRECT DAMAGES HOWEVER CAUSED ON ANY THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING IN ANY WAY OUT OF TI REFERENCE DESIGNS OR BUYER S USE OF TI REFERENCE DESIGNS TI reserves the right to make corrections enhancements improvements and other changes to its semiconduct
82. hift register of 33 bits but be cautious with the clock domain crossing problem Data transmit from the controller to device Whenever the controller wants to transmit data to device it first pulls the clock line low for more than one clock cycle to inhibit the current transmit process or to indicate the start of a new transmit process which usually be called as inhibit state After that 1t pulls low the data line then release the clock line and this 15 called the request state The rising edge on the clock line formed by the release action can also be used to indicate the sample time point as for a start bit The device will detect this succession and generates a clock sequence in less than 105 time The transmit data consists of 12bits one start bit as explained before eight data bits one parity check bit odd check one stop bit always one and one acknowledge bit always zero After sending out the parity check bit the controller should release the data line and the device will detect any state change on the data line in the next clock cycle If there s no change on the data line for one clock cycle the device will pull low the data line again as an acknowledgement which means that the data is correctly received After the power on cycle of the PS 2 mouse it enters into stream mode automatically and disable data transmit unless an enabling instruction is received Figure 6 16 shows the waveform while communication happening
83. hoosing the tab leads to the window in Figure 3 12 2 Plug a D sub cable to VGA connector of the DE2 115 board and LCD CRT monitor 24 Terasic DE2 115 User Manual www terasic com www terasic com NOTE RIAN 3 The LCD CRT monitor will display the same color pattern on the control panel window 4 Click the drop down menu shown in Figure 3 12 where you can output the selected color individually Memory il Figure 3 12 Controlling VGA display 3 10 HSMC Select the HSMC tab to reach the window shown in Figure 3 13 This function is designed to verify the functionality of the signals located on the HSMC connector Before running the HSMC loopback verification test follow the instruction noted under the Loopback Installation section and click on Verify Please note to turn off the DE2 115 board before the HSMC loopback adapter is installed to prevent any damage to the board The HSMC loopback adapter is not provided in the kit package but can be purchased through the website below http www terasic com tw cgi bin page archive pl Language English amp CategoryNo 78 amp No 495 25 Terasic DE2 115 User Manual www terasic com www terasic com 4 mA c i 9 EU GZ 7 RS232 Please make sure the HSMC loopback adapter has connected to the HSMC co Memory ll VGA Otherwise p
84. i TT Jeleleizisigia Save Setting System Configuration CLOCK LED x 27 Button x 4 PS2 128 SRAM 2MB v Audio Ethernet 1 Tv Decoder IR Receiver GPIO Header RS232 T Segement x 8 Switch x 18 SDCARD LED FLASH 8MB SMA USB Ethernet 2 EJTAG EEPROM 32 IO Voltage 3 3 V Defaut Prefix None HSMC IO Voltage 25 V Default Prefi Name None Figure 5 3 The DE2 115 Board Type and Project Name B System Configuration Under System Configuration users are given the flexibility of enabling their choice of included components on the DE2 115 as shown in Figure 5 4 Each component of the DE2 115 is listed where users can enable or disable a component according to their design by simply marking a check or removing the check in the field provided If the component 15 enabled the DE2 115 System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standard Terasic DE2 115 User Manual www terasic com 74 www terasic com Terasic DE2 115 System Builder 101 NOTE RYAN UNIVERSITY PROGRAM M www terasic com DE2 115 FPGA Board i vs 5 LGA r isaanaea ae ee eRe ee Izizigizimimim Rig IRI IR Save Setting Figure 5 4 System Configuration Group B GPIO Expansion Users can connec
85. inputs to a circuit Each switch 15 connected directly to a pin the Cyclone E FPGA When the switch is in the DOWN position closest to the edge of the board it provides a low logic level to the FPGA and when the switch 15 VCC3P3 KEY3 E 1 74 245 M21 IV M23 Figure 4 6 Connections between the push button and Cyclone IV E FPGA oe depressed oe released Before Pebomana FTIT EBENEN Schmitt Trigger Debounced Figure 4 7 Switch debouncing in the UP position it provides a high logic level Terasic DE2 115 User Manual www terasic com 23 www terasic com ANB S YAN ANB S YAN 2528 2628 22 AD27 27 SW17 SW16 SW15 51 14 SW3 SW2 SWI 0 Figure 4 8 Connections between the slide switches and Cyclone IV E FPGA 4 3 Using LEDs There are 27 user controllable LEDs on the DE2 115 board Eighteen red LEDs are situated above the 18 Slide switches and eight green LEDs are found above the push button switches the 9th green LED 15 in the middle of the 7 segment displays Each LED 15 driven directly by a pin on the Cyclone E FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off Figure 4 9 shows the connections between LEDs and Cyclone IV E FPGA LEDRO LEDRO G19 5 LEDGO LEDGO LEDR1 LEDR1 E21 F19 LEDG1 LEDG1 LEDR2 LEDR2 E22 E19 LEDG2 LEDG2 LEDR3 LEDR3 25
86. ion PS 2 Mouse fj PERIOOM ai F NR A 4 8 bnnc 3 15111 1 7 i Y axis X axis Middle Right Left Displacement Displacement Click Click Click Figure 6 17 The setup of the PS 2 Mouse demonstration 6 9 IR Receiver Demonstration In this demonstration the key related information that the user has pressed on the remote controller Figure 6 18 Table 6 3 will be displayed on the DE2 115 board Users only need to point the remote controller to the IR receiver on DE2 115 board and press the key After the signal being decoded and processed through FPGA the related information will be displayed on the 7 segment displays in hexadecimal format which contains Custom Code Key Code and Inversed Key Code The Custom Code and Key Code are used to identify a remote controller and key on the remote controller respectively Next we will introduce how this information being decoded and then displayed in this demo When a key on the remote controller is pressed the remote controller will emit a standard frame shown in Figure 6 19 The beginning of the frame is the lead code represents the start bit and then is the key related information and the last 1 bit end code represents the end of the frame 98 Terasic DE2 115 User Manual www terasic co
87. itches push button switches 8 PS 2 Keyboard e Slide Switches and Push buttons switches Table 6 5 Usage of the slide switches and push buttons switches KEYs Signal Name 0 Reset Circuit KEY 1 Repeat the Demo Music QFFDEMOON PS2KEYBOARD gt Channel 1 ON OFF 7 Chamel20N OFF 00 PS 2 Keyboard Table 6 6 Usage of the PS 2 Keyboard Keys Signal Name Description 104 Terasic DE2 115 User Manual www terasic com www terasic VGA LCD CRT Monitor Line Out Speaker Keyboard Input Keyboard Algorithms for Audio Processing Synthesizer Figure 6 24 The Setup of the Music Synthesizer Demonstration 6 11 Audio Recording and Playing This demonstration shows how to implement an audio recorder and player using the DE2 115 board with the built in Audio CODEC chip This demonstration is developed based on SOPC Builder and Nios II IDE Figure 6 25 shows the man machine interface of this demonstration Two push buttons and six slide switches are used for users to configure this audio system SWO is used to specify recording source to be Line in MIC In SWI is used to enable disable MIC Boost when the recording source is MIC In SW2 15 used to enable disable Zero Cross Detection for audio playing SW3 SW4 SW5 are used to specify recording sample rate as 96K 48K 44 1K 32K or 8K The 16x2 LCD is used to indicate the Recording Playing statu
88. iver Figure 4 19 Using Emulated LVDS GPIO Table 4 12 Pin Assignments for Expansion Headers Signal Name FPGA Pin No Description Standard GPIO 0 PIN AB22 GPIO Connection DATA 0 Depending on JP6 GPIO 1 PIN AC15 GPIO Connection DATA 1 Depending on JP6 GPIO 2 PIN 21 GPIO Connection DATA 2 Depending on JP6 GPIO 3 PIN Y17 GPIO Connection DATA 3 Depending on JP6 GPIO 4 PIN AC 1 GPIO Connection DATA 4 Depending on JP6 GPIO 5 PIN Y16 GPIO Connection DATA 5 Depending on JP6 GPIO 6 PIN AD21 GPIO Connection DATA 6 Depending on JP6 GPIO 7 PIN 16 GPIO Connection DATA 7 Depending on JP6 GPIO 8 PIN AD15 GPIO Connection DATA 8 Depending on JP6 GPIO 9 PIN AE15 GPIO Connection DATA 9 Depending on JP6 GPIO 10 PIN AC19 GPIO Connection DATA 10 Depending on JP6 GPIO 11 PIN AF16 GPIO Connection DATA 11 Depending on JP6 GPIO 12 PIN AD19 GPIO Connection DATA 12 Depending on JP6 GPIO 13 PIN AF15 GPIO Connection DATA 13 Depending on JP6 GPIO 14 PIN AF24 GPIO Connection DATA 14 Depending on JP6 GPIO 15 PIN AE21 GPIO Connection DATA 15 Depending on JP6 GPIO 16 PIN AF25 GPIO Connection DATA 16 Depending on JP6 GPIO 17 PIN AC22 GPIO Connection DATA 17 Depending on JP6 GPIO 18 PIN AE22 GPIO Connection DATA 18 Depending on JP6 GPIO 19 PIN AF21 GPIO Connection DATA 19 Depending on JP6 GPIO 20 PIN AF22 GPIO Connection DATA 20 De
89. k of this demonstration SD 4 Bit Mode block implements the SD 4 Bit mode protocol for reading raw data from the SD Card The FAT block implements FAT16 FAT32 file system for reading wave files that is stored in the SD Card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for extracting audio data from wave files The I2C block implements I2C protocol for configuring audio chip The SEG7 block implements displaying function to display elapsed playing time The Audio block implements audio FIFO checking function and audio signal sending receiving function The IR block acts as a control interface of the music player system 92 Terasic DE2 115 User Manual www terasic com www terasic com Figure 6 14 Software Stack of the SD music player demonstration The audio chip should be configured before sending audio signal to the audio chip The main program uses I2C protocol to configure the audio chip working in master mode the audio output interface working in 125 16 bits per channel and with sampling rate according to the wave file contents In audio playing loop the main program reads 512 byte audio data from the SD Card and then writes the data to DAC FIFO in the Audio Controller Before writing the data to the FIFO the program will verify if the FIFO is full The design also mixes the audio signal from the microphone in and line in for the Karaoke style effects by enabling the BYPASS and
90. laying note 3 Q Note 1 Execute DE2 115 AUDIOldemo batchlaudio bat will download sof and elf files 2 Recording process will stop if audio buffer is full 3 Playing process will stop if audio data is played completely 4 If the HSMC loopback adapter is mounted the 2 SCL will be directly routed back to 2 SDA Because audio chip TV decoder chip and HSMC share one 2 bus therefore audio and video chip wont function correctly 107 Terasic DE2 115 User Manual www terasic com www terasic com YU RIA Table 6 7 Slide switches usage for audio source and signal processing setting Slide Switches 0 DOWN Position 1 UP Position SWO Audio is from MIC Audio is from LINE IN SW1 Disable MIC Boost Enable MIC Boost SW2 Disable Zero cross Detection Enable Zero cross Detection Table 6 8 Slide switch setting for sample rate switching for audio recorder and player SW5 SW4 SWS3 0 DOWN 0 DOWN 0 DOWN Sample Rate 1 UP 1 UP 1 UP 0 0 0 96K 0 0 1 48K 0 1 0 44 1K 0 1 1 32K 1 0 0 8K Unlisted combination 96K 6 12 Web Server Demonstration This design example shows server using the sockets interface of the NicheStack TCP IP Stack Nios II Edition MicroC OS II to serve web content from the DE2 115 board The server can process basic requests to serve HTML JPEG GIF PNG JS CSS SWE ICO files from the Altera read only zip file system Additionally it allows u
91. lease follow the steps below REEN DISCONNECT X NG Figure 3 13 HSMC loopback verification test performed under Control Panel 3 11 IR Receiver From the control panel we can test the IR receiver on the DE2 115 by sending scan code from a remote controller Figure 3 14 depicts the IR receiver window when the IR tab is pressed When the scan code is received the information will be displayed on the IR Receiver window represented in hexadecimal Also the pressed button on the remote controller will be indicated on the graphic of remote controller on the IR receiver window Note that there exists several encoding form among different brands of remote controllers Only the remote controller comes with the kit is confirmed to be compatible with this software 26 Terasic 2 115 User Manual www terasic com WWW COTY sss E M LII tA em Scan Code Heximal BUTTON 77525 gt SDCard Figure 3 14 Testing the IR receiver using remote controller 3 12 Overall Structure of the DE2 115 Control Panel The DE2 115 Control Panel is based on a Nios SOPC system instantiated in the Cyclone E FPGA with software running on the on chip memory The software part is implemented in C code the hardware part is implemented in Verilog HDL code with SOPC builder The source code is not available on the DE2_115 System CD To run the Control Panel users should make the configuration according
92. m www terasic com POWER 800 o 09 CHANNEL 090 00 0 MENU RETURN 2 6 PLAY ADJUST Figure 6 18 Remote controller Table 6 3 Key code information for each Key on remote controller Key Code Key Code Key Code Key Code Code Inv Key Code bits Figure 6 19 The transmitting frame of the IR remote controller Terasic DE2 115 User Manual www terasic com www terasic en aa anu NOTE RYA amp After the IR receiver on DE2 115 board receives this frame it will directly transmit that to FPGA In this demo the IP of IR receiver controller is implemented in the FPGA As Figure 6 20 shows it includes Code Detector State Machine and Shift Register First the IR receiver demodulates the signal inputs to Code Detector block The Code Detector block will check the Lead Code and feedback the examination result to State Machine block The State Machine block will change the state from IDLE to GUIDANCE once the Lead code 15 detected Once the Code Detector has detected the Custom Code status the current state will change from GUIDANCE to DATAREAD state At this state the Code Detector will save the Custom Code and Key Inv Key Code and output to Shift Register then displays it on 7 segment displays Figure 6 21 shows the state shift diagram of State Machine block Note that the input clock should be 50MHz IR Signal d Figure 6 20 The IR Receiver controller IDLE End Co
93. mmms8mESESEN 7 Clock Data Frequency Generator Figure 6 8 The setup for the Karaoke Machine 6 6 SD Card Demonstration Many applications use a large external storage device such as an SD Card or CF card to store data The DE2 115 board provides the hardware and software needed for SD Card access In this demonstration we will show how to browse files stored in the root directory of an SD Card and how to read the file contents of a specific file The SD Card is required to be formatted as FAT File System in advance Long file name is supported in this demonstration Figure 6 9 shows the hardware system block diagram of this demonstration The system requires a 5 clock provided by the board PLL generates a 100MHz clock for the Nios II processor and other controllers Four PIO pins are connected to the SD Card socket SD 4 bit Mode is used to access the SD Card hardware The SD 4 bit protocol and FAT File System function are all implemented by Nios II software The software is stored in the on chip memory 88 Terasic DE2 115 User Manual www terasic com www terasic com 50 2 50 Socket POUUODJAJU uigjes S Figure 6 9 Block Diagram of the SD Card Demonstration Figure 6 10 shows the software stack of this demonstration The Nios block provides basic IO functions to access hardware directly The functions are provided from Nios system
94. n how to use the 88 1111 refers to its datasheet and application notes which are available on the manufacturer s website ENETO U8 ENETO TX DATA 3 0 TXD 3 0 lt ENETO GTX GTX CLK TX_CLK _ VCC2P5 TX ER DATA 3 0 ENETO LED TX RXD 3 0 LED_TX ENETO_RX_CLK RX_CLK LED_RX ENETO_RX_DV ENETO RX ER ENETO LINK 1000 ENETO RX CRS ENETO LINK 100 ENETO_RX_COL COL LED LINK10 ENETO MDIO MDIO MDC MDC ENETO_INT_N JP1 INT n 3 ENETO RST N MODE RESET n 2 i RGMII MODE XTAL1 88E1111 JP1 WU Designed 5 Manufactured t PAKAR welt ff B B Figure 4 28 Working mode setup header for Ethernet PHY 57 2 115 User Manual www terasic com www terasic com NOT RIA Table 4 21 Jumper Settings for Working Mode ENETO US JP1 Jumper Settings Short Pins 1 and 2 Short Pins 2 and 3 ENETO PHY Working Mode RGMII Mode MII Mode Table 4 22 Jumper Settings for Working Mode of ENET1 U9 JP2 Jumper Settings Short Pins 1 and 2 Short Pins 2 and 3 Signal Name ENETO GTX CLK ENETO INT N ENETO LINK100 ENETO MDC ENETO MDIO ENETO RST N ENETO RX CLK ENETO RX COL ENETO RX CRS ENETO DATAIOJ ENETO RX DATA 1 ENETO RX DATA 2 ENETO DATA 3 ENETO RX DV ENETO RX ER ENETO TX CLK
95. n the DE2 115 board simultaneously by plugging an extension PS 2 Y Cable See Figure 4 26 Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational websites The pin assignments for the associated interface are shown in Table 4 19 Note If users connect only PS 2 equipment the PS 2 interface between FPGA I O should be PS2 CLK and 062 DAT 52 CLK PS2 CLK2 PS2 0412 PS2 DAT F5 H5 Figure 4 25 Connection between FPGA and PS 2 55 Terasic DE2 115 User Manual www terasic com www terasic com Signal PS2 52 PS2 CLK2 PS2 DAT2 Figure 4 26 Y Cable use for both Keyboard and Mouse Table 4 19 PS 2 Pin Assignments FPGA Pin No Description Standard PIN G6 PS 2 Clock 3 3V PIN H5 PS 2 Data 3 3V PIN G5 PS 2 Clock reserved for second PS 2 device 3 3V PIN F5 PS 2 Data reserved for second PS 2 device 3 3V 4 14 Gigabit Ethernet Transceiver The DE2 115 board provides Ethernet support via two Marvell 88E1111 Ethernet PHY chips The 88E1111 chip with integrated 10 100 1000 Mbps Gigabit Ethernet transceiver support GMII MII RGMII TBI MAC interfaces Table 4 20 describes the default settings for both chips Figure 4 27 shows the connection setup between the Gigabit Ethernet PHY and FPGA Configuration PHYADDR 4 0 ENA_PAUSE ANEG 3 0 ENA XC DIS 125 HWCFG 3 0
96. nstration the sample rate is set to 48kHz Pressing the pushbutton KEYO reconfigures the gain of the audio CODEC via bus cycling within ten predefined gain values volume levels provided by the device E Line In Push Button Bien 3 Figure 6 7 Block diagram of the Karaoke Machine demonstration Demonstration Setup File Locations and Instructions e Project directory DE2_115_i2sound e Bit stream used DE2 115 12sound sof or DE2 115 i2sound pof e Connect a microphone to the microphone in port pink color on the DE2 115 board e Connect the audio output of a music player such as an player or computer to the line in port blue color on the DE2 115 board e Connect headset speaker to the line out port green color on the DE2 115 board e Load the bit stream into FPGA by execute the batch file DE2 115 i2sound under the DE2 115 12soundldemo batch folder e You should be able to hear a mixture of the microphone sound and the sound from the music player e Press KEYO to adjust the volume it cycles between volume levels to 9 Q Note If the HSMC loopback adapter is mounted I2C SCL will be directly routed back to 2 SDA Because audio chip TV decoder chip and HSMC share one I2C bus therefore audio and video chip won t function correctly Figure 6 3 illustrates the setup for this demonstration 87 Terasic DE2 115 User Manual www terasic com www terasic com mummmmum
97. of the RS 232 serial communication interface on the DE2 115 The setup 15 established by connecting a RS 232 9 pin male to female cable from the PC to the RS 232 port where the Control Panel communicates to the terminal emulator software on the PC or vice versa Alternatively a RS 232 loopback cable can also be used if you do not wish to use the PC to verify the test The Receive terminal window on the Control Panel monitors the serial communication status Follow the steps below to initiate the RS 232 communication 1 Choosing the RS 232 tab leads to the window in Figure 3 11 23 Terasic DE2 115 User Manual www terasic com www terasic com NOTE RIA 2 Plug in RS 232 9 male to female cable from PC to RS 232 port RS 232 loopback cable directly to RS 232 port amp 3 The RS 232 settings are provided below in case a connection from the PC 15 used e Baud Rate 115200 e Parity Check Bit None e Data Bits 8 e Stop Bits 1 e Flow Control CTS RTS ON 4 begin the communication enter specific letters followed by clicking Send During the communication process observe the status of the Receive terminal window to verify its operation Figure 3 11 RS 232 Serial Communication 3 9 DE2 115 Control Panel provides VGA pattern function that allows users to output color pattern to LCD CRT monitor using the DE2 115 board Follow the steps below to generate the pattern function 1 C
98. om www terasic com NOTE RIAN Figure 6 13 shows the hardware block diagram of this demonstration The system requires 50 clock provided from the board PLL generates a 100MHz clock for Nios II processor and the other controllers except for the audio controller The audio chip is controlled by the Audio Controller which is a user defined SOPC component This audio controller needs an input clock of 18 432 MHz In this design the clock is provided by the PLL block The audio controller requires the audio chip working in master mode so the serial bit BCK and the left right channel clock LRCK are provided by the audio chip The 7 segment display is controlled by the 5 Controller which also is a user defined SOPC component Two PIO pins are connected to the I2C bus The I2C protocol is implemented by software Four PIO pins are connected to the SD Card socket The IR receiver is controlled by the IR Controller which also is a user defined SOPC component SD 4 Bit Mode 15 used to access the SD Card and is implemented by software All of the other SOPC components in the block diagram are SOPC Builder built in components 100MHz Phase 65deg SDRAM Chip Audio Socket MIC In Line In l LCD Line Out Module _50MHz 7 SEG Display SD Card Socket Bus LED Button IR Receiver Figure 6 13 Block diagram of the SD music player demonstration Figure 6 14 shows the software stac
99. on two lines 96 Terasic DE2 115 User Manual www terasic com www terasic com AU S RIA Inhibit 4st 2nd gth 10 11 CLK e 9 0690 DATA Ine 8 7 55 555500 Start bit BitO Bit7 Parity bit Stop Line bit control bit Receiving data 1 st 2nd 1 0 1 1 th CLK CLK ecce Start bit BitO Bit7 Parity bit Stop bit Figure 6 16 Waveforms on two lines while communication taking place B Demonstration Setup File Locations and Instructions e Project directory DE2 115 PS2 DEMO e Bit stream used DE2 115 PS2 DEMO sof e Load the bit stream into FPGA by executing DE2 115 52 DEMOdemo batch 5DE2 115 PS2 DEMO bat e Plug in the PS 2 mouse e Press KEY 0 for enabling data transfer e Press KEY 1 to clear the display data cache You should see digital changes on 7 segment display when the PS 2 mouse moves and the LEDG 2 0 will blink respectively when the left button right button or middle button is pressed Table 6 2 gives the detailed information Table 6 2 Detailed information of the indicators Indicator Name Description LEDG 0 Left button press indicator LEDG 1 Right button press indicator 97 DE2 115 User Manual www terasic com www terasic com NOTE RIN Figure 6 17 illustrates the setup of this demonstrat
100. or is able to keep track of the movement and record it in a frame buffer memory The VGA Controller will overlap the data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display Cypress USB gt Ko t lt gt ege Host Port SIE1 VGA Controller Altera System Interconnect Fabrit Frame Buffer Figure 6 3 Block diagram of the USB paintbrush demonstration Demonstration Setup File Locations and Instructions Project directory DE2 115 NIOS HOST MOUSE VGA Bit stream used DE2 115 NIOS HOST MOUSE VGA sof Nios II Workspace DE2 115 NIOS HOST MOUSE VGAWNSoftware e Connect a USB Mouse to the USB Host Connector type A of the DE2 115 board e Connect the VGA output of the DE2 115 board to VGA monitor both LCD and CRT type of monitors should work e Load the bit stream into FPGA note e Run the Nios and choose DE2 115 NIOS HOST MOUSE VGAWNSoftware as the workspace Click on the Run button note e You should now be able to observe blue background with an Altera logo on the VGA display e Move the USB mouse and observe the corresponding movements of the cursor on the screen e eft click mouse to draw white dots lines and right click the mouse to erase white dots lines on the screen 83 Terasic DE2 115 User Manual www terasic com www terasic com NOS RIN Note execute DE2_115_NIOS_HOST_MOUSE_VGA demo_batch nios_host_mouse_vga bat will
101. or products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques for components are used to the extent deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using Tl components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards Reproduction of significant portions of information in TI data books data sheets or reference designs is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Tl is not responsible or liable for such altered documentation Information of third parties m
102. ort Table 4 7 Power Supply of the HSMC Supplied Voltage Max Current Limit 12V 1A 3 3V 1 5A 1 Note the current levels indicated in Table 4 7 based 50 resource consumption If the HSMC interface is utilized with design resources exceeding 50 please notify our support support terasic com 2 the HSMC loopback adapter is mounted the 12C_SCL will be directly routed back to 12C_SDA Because audio chip TV decoder chip HSMC share 2 bus therefore audio and video chip wont function correctly The voltage level of the I O pins on the HSMC connector can be adjusted to 3 3V 2 5V 1 8V or 1 5V using JP7 The default setting 1s 2 5V see Figure 4 13 Because the HSMC I Os are connected to Bank 5 amp 6 of the FPGA and the VCCIO voltage 5 amp VCCIO6 of these banks are controlled by the header JP7 users can use a jumper to select the input voltage of amp VCCIOO to 3 3V 2 5V and 1 5V to control the voltage level of the I O pins Table 4 8 lists the jumper settings of the JP7 40 Terasic DE2 115 User Manual www terasic com www terasic com latata Dp m 23 amp 1 Cyclone 1v A s 5 ELLE 1 ured by Terasic U PERICOM B B lt 8h Figure 4 13 HSMC VCCIO supply voltage setting header Table 4 8 Jumper Settings for different
103. ory Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner Users can use the similar way to access the SRAM EEPROM and Flash Please note that users need to erase the Flash before writing data to it 3 5 USB Monitoring The Control Panel provides users a USB monitoring tool which monitors the status of the USB devices connected to the USB port on the DE2 115 board By plugging in a USB device to the USB host port of the board the device type is displayed on the control window Figure 3 8 shows a USB mouse plugged into the host USB port Cyrene Th p ne 7777 Y Figure 3 8 USB Mouse Monitoring Tool 21 Terasic DE2 115 User Manual www terasic com www terasic com NOS RIA 3 6 PS 2 Device amp The Control Panel provides users a PS 2 monitoring tool which monitors the real time status of a PS 2 mouse connected to DE2 115 board The movement of the mouse and the status of the three buttons will be shown in the graphical and text interface The mouse movement is translated as a position x y with range from 0 0 1023 767 This function can be used to verify the functionality of the PS 2 connection Follow the steps below to exercise the PS 2 Mouse Monitoring tool 1 Choosing the PS 2 tab leads to the window in Figure 3 9 2 Plug a PS 2 mo
104. ospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of components that have not been so designated is solely at Buyer s risk and Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products will not be responsible for any failure to meet ISO TS16949 Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2015 Texas Instruments Incorporated
105. p TV decoder chip and HSMC share one I2C bus therefore audio and video chip won t function correctly 4 12 RS 232 Serial Port DE2 115 board uses the ZT3232 transceiver chip and a 9 DB9 connector for RS 232 communications For detailed information on how to use the transceiver please refer to the datasheet which is available on the manufacturer s website or in the DE2 115 datasheetMRS 2352 folder on the DE2 115 System CD Figure 4 24 shows the related schematics and Table 4 18 lists the Cyclone IV E FPGA pin assignments 54 Terasic DE2 115 User Manual www terasic com www terasic com UART 12 612 gt INDERA pa UARTRTS UART TXD 11 e G9 IV E UART CTS 10 gt G14 ZT3232LEEY Figure 4 24 Connections between FPGA ZT3232 RS 232 chip Table 4 18 RS 232 Pin Assignments FPGA Pin No Description Standard PIN_G12 UART Receiver 33V UART TXD PIN G9 UART Transmitter 3 3V UART CTS PIN G14 Clear to Send 3 3V UART_RTS PIN_J13 UART Request to Send 3 3V 4 13 PS 2 Serial Port The DE2 115 board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 4 25 shows the schematic of the PS 2 circuit In addition users can use the PS 2 keyboard and mouse o
106. pending on JP6 GPIO 21 PIN AD22 GPIO Connection DATA 21 Depending on JP6 Terasic DE2 115 User Manual www terasic com www terasic com YU S RIA amp GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 PIN AG25 GPIO Connection DATA 22 Depending on JP6 PIN AD25 GPIO Connection DATA 23 Depending on JP6 PIN AH25 GPIO Connection DATA 24 Depending on JP6 PIN AE25 GPIO Connection DATA 25 Depending on JP6 PIN AG22 GPIO Connection DATA 26 Depending on JP6 PIN AE24 GPIO Connection DATA 27 Depending on JP6 PIN AH22 GPIO Connection DATA 28 Depending on JP6 PIN AF26 GPIO Connection DATA 29 Depending on JP6 PIN AE20 GPIO Connection DATA 30 Depending on JP6 PIN AG23 GPIO Connection DATA 31 Depending on JP6 PIN AF20 GPIO Connection DATA 32 Depending on JP6 PIN AH26 GPIO Connection DATA 33 Depending on JP6 PIN AH23 GPIO Connection DATA 34 Depending on JP6 PIN AG26 GPIO Connection DATA 35 Depending on JP6 4 9 Using 14 pin General Purpose Connector The DE2 115 Board provides 14 pin expansion header The header connects directly to 7 pins of the Cyclone IV E FPGA and also provides DC 43 3V VCC3P3 and six GND pins as shown in Figure 4 20 The voltage level of the I O pins on the 14 pin expansion header is 3 3V Finally Table 4 13 shows the pin assignments for I O connections Signal Name EX IO 0 EX IO 1 EX 10 2 Terasic D
107. robe SRAM Higher Byte Strobe Description SDRAM Address 0 SDRAM Address 1 SDRAM Address 2 SDRAM Address 3 SDRAM Address 4 SDRAM Address 5 SDRAM Address 6 SDRAM Address 7 SDRAM Address 8 SDRAM Address 9 SDRAM Address 10 SDRAM Address 11 SDRAM Address 12 SDRAM Data 0 SDRAM Data 1 SDRAM Data 2 67 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V I O Standard 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V www terasic com NOT RIA DRAM DQ 3 PIN W1 SDRAM Data 3 3 3V DRAM DOQ 4 PIN V3 SDRAM Data 4 3 3V DRAM DQ 5 PIN V2 SDRAM Data 5 3 3V DRAM DQ 6 PIN V1 SDRAM Data 6 3 3V DRAM DQ 7 PIN U3 SDRAM Data 7 3 3V DRAM PIN Y3 SDRAM Data 8 3 3V DRAM DQ 9 PIN Y4 SDRAM Data 9 3 3V DRAM DQ 10 PIN AB1 SDRAM Data 10 3 3V DRAM DQ 11 PIN AA3 SDRAM 11 3 3V DRAM DQ 12 PIN AB2 SDRAM Data 12 3 3V DRAM DQ 13 PIN AC1 SDRAM Data 13 3 3V DRAM 14 PIN AB3 SDRAM Data 14 3 3V DRAM DQ 15 PIN AC2 SDRAM Data 15 3 3V DRAM DQ 16 PIN M8 SDRAM Data 16 3 3V DRAM DQ 17 PIN L8 SDRAM Data 17 3 3V DRAM DQ 18 PIN P2 SDRAM Data 18 3 3V DRAM DQ 19 PIN N3 SDRAM Data 19 3 3V DRAM DQ 20 4 SDRAM Data 20 3 3V DRAM DQ 21 4 SDRAM Data 21 3 3V DRAM DQ 22 PIN M7 SDRAM Data 22 3 3V DRAM DQ 23 PIN L7 SDRAM Data 23 3 3V DRAM
108. rver elf amp Demo batch file folder for writing web site content zip file into flash DE2 115 Web Server WEB SERVER FLASH The demo batch file includes the following files Batch File WEB SERVER FLASH bat WEB SERVER FLASH bashrc FPGA Configure File WEB SERVER FLASH sof Demonstration Setup e Make sure the PHY device is working on mode Short pin 1 and pin 2 of JP1 e PlugaCAT 5e cable into the Ethernet port 74 on the DE2 115 board Make sure the Ethernet cable is connected to router and the DHCP function 1s supported Power on DE2 115 board e Execute the demo batch file WEB SERVER FLASH bat to write web site content into flash on DE2 115 board e Execute the demo batch file DE2 115 WEB SERVER bat for downloading sof and elf file for this demonstration e See Figure 6 35 when the message Web Server Starting up is shown on nios2 terminal The LCD on DE2 115 board will show the valid IP address It may take a while to get IP address from Gateway Once the LCD on DE2 115 board shows the valid IP address got from Gateway then launch your web browser e Input the IP into your browser IP is shown on the LCD display e You will see the brand new DE2 115 webpage on your computer e Onthe web page you could access the DE2 115 board s peripherals from the left sidebar or link to external pages from the right sidebar Try check some LEDs on the left sidebar and then press send will light up the
109. s The 7 SEG is used to display Recording Playing duration with time unit in 1 100 second The LED 15 used to indicate the audio signal strength Table 6 7 and Table 6 8 summarize the usage of Slide switches for configuring the audio recorder and player 105 Terasic DE2 115 User Manual www terasic com www terasic com Bd 23 Lu E i F 1343 i di 1 1222 22 7 ee vi Du Bs zr 11551 CycioneE IV 3 r Na PERK Record Play Status Record Play Duration fig 9 og 12212010 Designer rufactareat by Tera SIN PLE SE m E UU Signal Strength TA AA AAA RR RU RR TU j Sample rate Play Record Audio Source MIC Boost Zero Cross Detect Figure 6 25 Man Machine Interface of Audio Recorder and Player Figure 6 26 shows the block diagram of the Audio Recorder and Player design There are hardware and software parts in the block diagram The software part stores the Nios program in SRAM The software part is built by Nios II IDE in C programming language The hardware part is built by SOPC Builder under Quartus II The hardware part includes all the other blocks The AUDIO Controller is a user defined SOPC component It is designed to send audio data to the audio chip or receive audio data from
110. sers to control various board components from the web page As Part of the Nios II EDS NicheStack TCP IP Network Stack is a complete networking software suite designed to provide an optimal solution for network related applications accompany Nios II Using this demo we assume that you already have a basic knowledge of TCP IP protocols The following describes the related SOPC system The SOPC system used in this demo contains Nios II processor On Chip memory JTAG UART timer Triple Speed Ethernet Scatter Gather DMA controller and other peripherals etc In the configuration page of the Altera Triple Speed Ethernet Controller users can either set the MAC interface as MII or RGMII as shown in Figure 6 27 and Figure 6 28 respectively 108 Terasic DE2 115 User Manual www terasic com www terasic com Parameter Settings 10 100 1000 Ethernet 10 100 0 Ethe met gt 10008ASE X SGMII PCS Figure 6 27 Mll interface MAC Configuration 109 Terasic DE2 115 User Manual www terasic com Core Configuration MAC Options FIFO Options PCS SGMII Options X Core variation 10 100 1000Mb Ethernet MAC 10 100 1000Mb Ethernet interface v Use internal FIFO Number of ports L 1000BASE X SGMII PCS Use transceiver block LVDS VC Figure 6 28 RGMII interface MAC Configuration In the MAC Options tab See Figure 6 29 users
111. sic com Figure 6 33 Nios Il Program Software Architecture Finally the detail descriptions for Software flow chart of the Web Server program are listed in below Firstly the Web Server program initiates the MAC and net device then calls the get_mac_addr function to set the MAC addresses for the PHY Secondly it initiates the auto negotiation process to check the link between PHY and gateway device If the link exists the PHY and gateway devices will broadcast their transmission parameters speed and duplex mode After the auto negotiation process has finished it will establish the link Thirdly the Web Server program will prepare the transmitting and receiving path for the link If the path 15 created successfully it will call the get_ip_addr function to set up the IP address for the network interface After the IP address 15 successfully distributed the NicheStack TCP IP Stack will start to run for Web Server application Figure 6 34 describes this demo setup and connections on DE2 115 The Nios II processor is running NicheStack on the MicroC OS II RTOS Q your gateway should support DHCP because it uses DHCP protocol to request a valid IP from the Gateway or else you would need to reconfigure the system library to use static IP assignment Furthermore the web server demonstration uses the or interface to access the TCP IP You can switch the MAC 114 Terasic DE2 115 User Manual www terasic com www
112. specified LEDs on board You also could send text to the LCD or set the value for 7 segment displays on DE2 115 board Figure 6 36 gives a snapshot of the web server page e perform the demonstrations of other mode or Ethernet port please refer to Table 4 21 Table 4 22 for mode setting and running the associate project on the DE2 115 demonstrations DE2 115 Web Server folder in the DE2 115 System CD 116 Terasic DE2 115 User Manual www terasic com www terasic com 10 100 1000Mbps 10 100 1000Mbps CAT 5e Cable CAT 5e Cable Figure 6 34 System Principle Diagram EM Altera Nios I EDS 12 1 gee PHY Marvell 88E1111 found at PHY address 6x14 of MAC GrouplBl FHY 6 0 Automatically mapped to tse_mac_device PHY H H Restart Nuto Megotiation checking PHY link 1 Auto Megotiation PASSED PHY 8 8 Restart fluto Megyotiation checking PHY link PHY H H1 Auto Negotiation PASSED PHY 8 81 Checking link PHY 6 81 Link established PHY H H1 Speed 166 Duplex Full CMD_CONFIG 6x61 6600668 MAC post initialization CMD_COMFIG 8x65088263 tse_sqdma_read_init descriptor chain desc lt i depth created mctezt init called IP address of eti 192 168 21 171 Created Inet main task Prio 27 Created clock tick task Prio 3 Acquired IP address via DHCP client for interface eti IP address 192 168 21 213 Subnet Mask 255 255 255 868 Gateway 172 168 21
113. t Clock 2 Interrupt open drain output 2 Parallel LED output of 100BASE TX link 2 Management data clock reference 2 Management data 2 Hardware reset signal 2 GMII and MII receive clock 2 GMII and MII collision 2 GMII and MII carrier sense 2 GMII and MII receive data 0 2 58 Standard 2 5 2 5 3 3V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 3 3V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V www terasic com AN OTE RIA ENET1_RX_DATA 1 21 GMII and receive data 1 2 2 5V ENET1 DATAR PIN A23 GMII and receive data 2 2 2 5V ENET1 DATA 3 021 GMII and receive data 3 2 2 5V ENET1 DV A22 GMII and MII receive data valid 2 2 5V ENET1 24 GMII receive error 2 2 5 22 transmit clock 2 2 5 TX 0 C25 MII transmit data 0 2 2 5V ENET1 TX DATA 1 PIN A26 MII transmit data 1 2 2 5 ENET1 TX DATA 2 826 Mil transmit data 2 2 2 5V ENET1 TX DATA 3 C26 MII transmit data 3 2 2 5V ENET1 TX EN PIN B25 GMII and MII transmit enable 2 2 5 25 GMII and transmit error 2 2 5V ENETCLK 25 PIN A14 Ethernet clock source 3 3V 4 15 TV Decoder The DE2 115 board is equipped with an Analog Device ADV7180 TV decoder chip The ADV7180 is an integrated video decoder that automa
114. t GPIO expansion card onto GPIO header located on the DE2 115 board as shown in Figure 5 5 Select the appropriate daughter card you wish to include in your design from the drop down menu The system builder will automatically generate the associated pin assignments including the pin name pin location pin direction and IO standard If a customized daughter board is used users can select GPIO Default followed by changing the pin name pin direction and IO standard according to the specification of the customized daughter board Terasic DE2 115 User Manual www terasic com 75 System Configuration Project Name DE2 115 CLOCK LED x 27 Button x 4 PS2 VGA SDRAM 128MB SRAM 2MB Audio Ethernet 1 TV Decoder IR Receiver GPIO Header RS282 7 Segementx 8 Switch x 18 SDCARD LCD FLASH 8MB SMA USB Ethernet 2 EJTAG EEPROM 82Kb IO Voltage 3 8 V Default Prefix Name None HSMC IO Voltage 2 5 V Default Prefix Name None www terasic com The Prefix is an optional feature which denotes the prefix pin name of the daughter Terasic DE2 115 System Builder 101 ter UNIVERSITY PROGRAM wtrerasic com DE2 115 FPGA Board gigi Ds M HSMC IO Voltage 2 5 V Default Prefix Name None System Configuration Project Name DE2 1 15 CLOCK LE
115. this demonstration Line Out VGA LCD CRT Speaker Line In Video In CVBS Output gt HE mnm TT 4 ITU R 656 YUV 422 Decoder De Interlace Figure 6 2 setup for the TV box demonstration 6 3 USB Paintbrush USB port is widely used in many multimedia products The DE2 115 board provides a complete USB solution for both host and device applications In this demonstration we implement a Paintbrush application by using a USB mouse as the input device This demonstration uses the device port of the Cypress CY7C67200 chip and the Nios II processor to implement a USB mouse movement detector We also implemented a video frame buffer with a 82 Terasic DE2 115 User Manual www terasic com www terasic com AND RIA amp controller to perform the real time image storage and display Figure 6 3 shows the block diagram of the circuit which allows the user to draw lines on the display screen using the USB mouse The Controller block 15 integrated into the Altera Avalon bus so that it can be controlled by the Nios II processor Once the program runs the Nios II processor is started as it will detect the existence of the USB mouse connected to DE2 115 board When the mouse moves the Nios II process
116. tic view of the EEPROM The configured access address EEPROM is OxA0 for writing for reading VCC3P3 2 SCLK I2C 5041 24 324 Figure 4 36 Connections between FPGA and EEPROM 65 Terasic DE2 115 User Manual www terasic com www terasic com YU S RYA B SD Card Many applications use a large external storage device such as SD Card or CF card for storing data The DE2 115 board provides the hardware needed for SD Card access Users can implement custom controllers to access the SD Card in SPI mode and SD Card 4 bit or I bit mode Figure 4 37 shows the related signals Finally Table 4 27 Table 4 30 lists all the associated pins for interfacing FPGA respectively VCC3P3 E isowml lilii LIT E NOTE RYA kdes SD_CLK Cyclone IV EE 22 sopa SD WP N Figure 4 37 Connections between FPGA and SD Card Socket Table 4 27 SRAM Pin Assignments SRAM Address 0 RAM 5 PIN_AE6 SRAMAddess5 39 0 2 SRAM_ADDRI7 5 SRAM Address 7 RAM ADDR S PIN SRAM Address 8 3 3V SRAM 7 SRAM Address 9 SRAM ADDR 10 PIN 22 Address 10 SRAM ADDR M SRAMAddress 11 39 3 3V 3 3 66 Terasic DE2 115 User Manual www terasic com www terasic NOT RIA SRAM ADDR 15 SRAM ADDR 16 SRAM ADDR 17 SRAM ADDR 18
117. tically detects and converts a standard analog baseband television signals NTSC PAL and SECAM into 4 2 2 component video data compatible with the 8 bit ITU R BT 656 interface standard The ADV7180 is compatible with a broad range of video devices including DVD players tape based sources broadcast sources and security surveillance cameras The registers in the TV decoder be programmed by a serial I2C bus which is connected to the Cyclone IV E FPGA as indicated in Figure 4 29 Note that the I2C address W R of the TV decoder 06 is 0 40 0 41 The pin assignments are listed in Table 4 24 Detailed information of the ADV7180 is available on the manufacturer s website or in the DE2 115 datasheetsNTV Decoder folder on the DE2 115 System CD 59 Terasic DE2 115 User Manual www terasic com www terasic com ADV7180 TD DATA T 0 TD VS J12 E RCA JACK 50 IV TD CLK27 TD RESET N I2C SCLK 2 SDAT OSC 28MHz Y1 Figure 4 29 Connections between FPGA and TV Decoder Q Note If the HSMC loopback adapter is mounted the I2C SCL will be directly routed back to 2 SDA Because audio chip TV decoder chip and HSMC share one I2C bus therefore audio and video chip won t function correctly Table 4 24 TV Decoder Pin Assignments Signal Name FPGA Pin No Description Standard TD DATA 0 8 TV Decoder Data 0 3 3V TD DATA 1 A7 TV Decoder
118. tpll Oxi34424dB 0 44244 a ee de Avalon Memory Mapped Slave 0413442400 0 124424 7 gt Avalon Memory Mapped Slave sys r08000000 IxOffffiff KETAR tse mac riple Speed Ethernet transmit Avalon Streaming Sink sys receive Avalon Streaming Source sys control Avalon Memory Mapped Slave sys 013442000 0x134423ff El sgdma tx Scatter Gather Controller csr Avalon Memory Mapped Slave sys 2 0213442400 44243 gt descriptor read Memory Mapped Master descriptor_write Memory Mapped Master m_read Avalon Memory Mapped Master out Avalon Streaming Source El sgdma rx Scatter Gather Controller Avalon Memory Mapped Slave altpll sys 13442440 0x1344247f gt descriptor read Memory Mapped Master descriptor write Avalon Memory Mapped Master m_write Avalon Memory Mapped Master in Avalon Streaming Sink descriptor On Chip Memory RAM or ROM 81 Avalon Memory Mapped Slave altpll sys 02123440000 0x13440ffFf Figure 6 30 SOPC Builder Figure 6 31 shows the connections for programmable 10 100Mbps Ethernet operation via MII 2 5 25MHz mii tx eed 2 bm 7 O kt eth_mode 10 E Ur OMS eh set 100 10 100 1000 Small MAC Tie to GND 2 5 25
119. udio out jack e Place slide switch SW17 in the DOWN position to hear a kHz humming sound from the audio out port Alternatively if slide switch SW17 is in the UP position and optionally connects the microphone in port with a microphone and or connects the line in port with an audio player s output you will hear the sound from the microphone or audio player or mixed sound from both The Verilog HDL source code for this demonstration is provided in the DE2 115 Default folder which also includes the necessary files for the corresponding Quartus II project The top level Verilog HDL file called DE2 115 Default v can be used as a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone IV E FPGA 6 2 TV Box Demonstration This demonstration plays video and audio input from a DVD player using the VGA output audio CODEC and one TV decoder U6 on the DE2 115 board Figure 6 1 shows the block diagram of the design There are two major blocks in the circuit called DC AV Config and TV to VGA The TV to block consists of the ITU R 656 Decoder SDRAM Frame Buffer YUV422 to YUV444 YcrCb to RGB and VGA Controller The figure also shows the TV Decoder AD 7160 and the VGA DAC ADV7123 chips used As soon as the bit stream is downloaded into the FPGA the register values of the Decoder chip are used to configure the TV decoder via the I2C_AV_Config block which uses the I2C
120. ur local directory contains no spaces otherwise the Nios II software will not work Note Quartus II v9 1 SP2 is required for all DE2 115 demonstrations to support Cyclone IV E device Quartus II v10 0 can be installed from the Altera Complete Design Suite DVD provided 6 1 DE2 115 Factory Configuration The DE2 115 board is shipped from the factory with a default configuration bit stream that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below B Demonstration Setup File Locations and Instructions e Project directory DE2 115 Default e Bit stream used DE2 115 Default sof or DE2 115 Default pof Power on the DE2 115 board with the USB cable connected to the USB Blaster port If 79 Terasic DE2 115 User Manual www terasic com www terasic com ND RIA necessary that is if the default factory configuration of the DE2 115 board 15 not currently stored in EPCS64 device download the bit stream to the board by using either JTAG or AS programming e You should now be able to observe that the 7 segment displays are displaying a sequence of characters and the red and green LEDs are flashing Also Welcome to the Altera DE2 115 15 shown on the LCD display e Optionally connect a VGA display to the VGA D SUB connector When connected the VGA display should show a color picture e Optionally connect a powered speaker to the stereo a
121. use to the PS 2 port on the DE2 115 board 3 Press the Start button to start the PS 2 mouse monitoring process and the button caption 1s changed from Start to Stop In the monitoring process the status of the PS 2 mouse is updated and shown in the Control Panel s GUI window in real time Press Stop to terminate the monitoring process 5 lt TA 2255 LR son r1 Figure 3 9 PS 2 Mouse Monitoring Tool 22 Terasic DE2 115 User Manual www terasic com www terasic com NOTE RIA 3 7 SD Card amp The function 15 designed to read the identification and specification information of the SD Card The 4 bit SD MODE 15 used to access the SD Card This function can be used to verify the functionality of the SD Card Interface Follow the steps below to exercise the SD Card 1 Choosing the SD Card tab leads to the window in Figure 3 10 2 Insert an SD Card to the DE2 115 board and then press the Read button to read the SD Card The SD Card s identification specification and file format information will be displayed in the control window je AM Jang T vm ply pity PP ee Ud hg 4 aigu Figure 3 10 Reading the SD Card Identification and Specification 3 8 RS 232 Communication The Control Panel allows users to verify the operation
122. w terasic com 2 Introduction of the Alfera DE2 115 Board This chapter presents the features and design characteristics of the DE2 115 board 2 1 Layout and Components A photograph of the DE2 115 board is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the location of the connectors and key components 12V DC Power Supply Connector Power ON OFF Switch Altera USB Blaster Controller chipset USB Host Slave Controller Altera EPCS64 Configuration Device LCD 16x2 Module 7 segment Displays Programming Mode Switch Audio TV Decoder CODEC NTSC PAL Oscillator USB USB Blaster Port Device USB Mic Line Line Host In In Out lon J Ir LJ ee 18 Red LEDs 18 Slide Switches Video In 64MB SDRAM x2 VGA Out 28MHz Ethemet Ethernet 10 100 1000 10 100 1000M RS 232 Port 0 Port 1 Port 2 4Push button 8MB SRAM FLASH 8 Green LEDs Figure 2 1 The DE2 115 board top view Terasic DE2 115 User Manual www terasic com PS 2 Port VGA 24 bit DAC Gigabit Ethernet PHY Expansion Header J15 with Protection Diodes HSMC Connector Altera 60 nm Cyclone FPGA with 115K LEs 50MHz Oscillator SMA Ext Clock Out SMA Ext Clock In IR Receiver www terasic com EEPROM SD Card Socket H t 1 Figure 2 2 The DE2 11
123. www terasic com www terasic com 7 Appendix 7 1 EPCS Programming via nios 2 flash programmer Before programming the EPCS nios 2 flash programmer users must add an EPCS patch file nios flash override txt into the Nios II EDS folder The patch file is available in the folder DE2_115_demonstrations EPCS_Patch of DE2 115 System CD Please copy this file to the folder QuartusInstalledFolder nios2eds bin e g C altera 11 1 nios2eds bin If the patch file is not included into the Nios II EDS folder an error will occur as shown in the Figure 7 1 Using cable USB Blaster TII TEM device 1 instance Ha TT II 1 3 Fh E EPCS layout data looking for section 182156 1 Unable Co use EPLS device Leaying target processor paused Figure 7 1 EPCS Message 7 2 Revision History Version Change Log V1 0 Initial Version Preliminary V1 01 VGA Vertical Timing table correction SDRAM Table reference modification V1 02 Modify Table4 15 Header info V1 03 Modify section 6 3 demo description V1 04 Added EPCS information V2 0 Replace USB Chip from ISP1362 to CY67200 V2 1 Modify Table 4 9 change pin description of HSMC_CLKIN_N HSMC CLKIN P HSMC CLKOUT N and HSMC CLKOUT P 119 Terasic DE2 115 User Manual www terasic com www terasic com YU S RYA 7 3 Copyright Statement Copyright 2012 Terasic Technologies rights reserved 120 Terasic D

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