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SuperHTM Family E10A-USB Multi-core Emulator

1. M Bus amp Branch CPUT Acquisition v Read v Write IV relative addressing M Branch v Software IV Data access Instruction Fetch When trace buffer full Trace continue Realtime trace Won realtime trace mode Start porter EG Display Type Iv DMAC E Cancel Figure 2 1 Acquisition Dialog Box Internal Trace Function Rev 1 00 Nov 26 2007 Page 25 of 48 2eENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 For the internal trace using Channel 1 or Channel 2 of I Trace mode enables acquisition of 512 step trace information on a different bus When only Channel 1 is used 1024 step trace information can be acquired The internal trace functions are common resources for CPUO or CPUI and can be set by the High performance Embedded Workshop installed in either of the CPUs For Channel 1 and Channel 2 it is possible to select a bus that acquires trace information among the items shown in table 2 11 Table 2 11 Information on Acquiring the Internal Trace Item Acquisition Information Note M Bus amp Branch CPUO Acquires the data and branch information on the M bus for CPUO e Data access read write e PC relative access e Branch information e Software trace I Bus CPUO Acquires the data on the I bus for CPU
2. 1 00 Nov 26 2007 Page 4 of 48 REJ10J1767 0100 RENESAS Section 1 Connecting the Emulator with the User System SH7265 input SH7265 Signal t Note Signal Outi SH7205 Pin No N C N C N C TRSTK 4 ASEMD GND N C N C N C UCON GND gt AUDAT Output AUDCK Output N C N C AUDAT Output ASEBRKAK4 Input ASEBRK 2 Output Output User reset AUDAT Output N C N C X TDO Output AUDAT Output UVCC_AUD Output N C N C AUDSYNG Output UVCC Output N C p TCK Input N C N C EI N C TMS N C N C N C TDI Input H20 N C 1 Input to or output from the user system 2 The symbol means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 When the user system interface cable is connected to this pin and the ASEMD pin is set to 0 do not connect to GND but to the ASEMD pin directly 5 The GND bus lead at the center of the H UDI port connector must be grounded Unit mm H UDI port connector top view Figure 1 3 Pin Assignments of the H UDI Port Connector 38 Pins Rev 1 00 Nov 26 2007 Page 5 of 48 RENESAS REJ10J1767 0100 Section 1 Connecting the Emulator with the User System 1 5 1 5 1 Recommended Circuit between the H UDI Port Connector and the MCU
3. 150 cm Mass 50 6 g Soft E10A USB Multi core 1 HS0005KCUO4SR ware emulator setup program C e 7 SuperH Family E10A HSO005KCUO4HJ USB Multi core Emulator User s Manual HSOOO5KCUO04HE Supplementary Information on Using the HS7265KCUO1HJ SH7265 and SH7205 HS7265KCUO1HE and Test program manual HS0005TMO4HJ and for HSOOO5KCU01H and HS0005TMO4HE HS0005KCUO4H Provided on the CD R Note Additional document for the MCUs supported by the emulator is included Check the target MCU and refer to its additional document Rev 1 00 Nov 26 2007 Page 1 of 48 3 NE SAS REJ10J1767 0100 Section 1 Connecting the Emulator with the User System 1 2 Connecting the Emulator with the User System To connect the E10A USB Multi core emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user system interface cable When designing the user system refer to the recommended circuit between the H UDI port connector and the MCU In addition read the E10A USB Multi core emulator user s manual and hardware manual for the related device Table 1 2 shows the type number of the emulator the corresponding connector type and the use of AUD function Table 1 2 Type Number AUD Function and Connector Type Type Number Connector AUD Function HS0005KCUO4H 14 pin connector Not Available HS0005KCUO4H 38 pin connector Available The H UDI port conne
4. Event Condition Rev 1 00 Nov 26 2007 Page 17 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 7 Types of Event Condition Event Condition Type Description Address bus condition Address Sets a condition when the address bus data access value or the program counter value before or after execution of instructions is matched Data bus condition Data Sets a condition when the data bus value is matched Byte word or longword can be specified as the access data size Bus state condition Bus State There are two bus state condition settings Bus state condition Sets a condition when the data bus value is matched Read Write condition Sets a condition when the read write condition is matched Count Sets a condition when the specified other conditions are satisfied for the specified counts CPU core condition CPU Core Select Sets a condition when the CPU core CPUO and CPU1 or the internal DMA bus internal DMA write bus and internal DMA read bus is accessed Reset point A reset point is set when the count and the sequential condition are specified Action Selects the operation when a condition such as a break a trace halt condition or a trace acquisition condition is matched For a break the CPU core in which a break will occur is selected Using the Combination action Sequential or PtoP dialog box
5. Recommended Circuit 14 Pin Type Figure 1 4 shows a recommended circuit for connection between the H UDI port connectors 14 pins and the MCU when the emulator is in use Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 The ASEMD pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMD 0 2 When the emulator is not used ASEMD 1 Figure 1 4 shows an example of circuits that allow the ASEMD pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the ASEMD pin is changed by switches etc ground pin 9 Do not connect this pin to the ASEMD pin When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MCU must be as short as possible Do not connect the signal lines to other components on the board Since the H UDI and the AUD of the MCU operate with the PVcc supply only the PVcc to the UVCC pin The resistance value shown in figure 1 4 is for reference The TRST pin must be at the low level for a certain period when the power is supplied whether the H UDI is used or not For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MCU Rev 1 00 Nov 26 2007 Page 6 of 48 REJ10J1767 0100 7tENESAS Section
6. SH7265 and SH7205 2 During user program execution the change of settings or the measurement items for the CPU cannot be displayed b Measurement item Items are measured by setting channels in the Performance Analysis dialog box A maximum of eight conditions four conditions for each of CPUO and CPUI can be specified at the same time Rev 1 00 Nov 26 2007 Page 44 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 20 Measurement Item Selected Name Option Disabled None Elapsed time AC The number of execution cycles I is set as the measurement item Branch instruction counts BT Number of execution instructions l Number of execution 32bit instructions 132 Exception interrupt counts EA Interrupt counts INT Data cache miss counts DC Instruction cache miss counts IC All area access counts ARN All area instruction access counts ARIN All area data access counts ARND Cacheable area access counts CDN data access Cacheable area instruction access counts CIN Non cacheable area data access counts NCN URAM area access counts UN URAM area instruction access counts UIN URAM area data access counts UDN Internal I O area data access counts IODN All area access cycle ARC All area instruction access cycle ARIC All area data access cycle ARDC All area access stall ARS All area
7. clock P 15 bus clock Bo The program will be suspended for 1 757 when the peripheral clock P is 33MHz the bus clock P is 66MHz Displaying a trace If a trace is displayed during execution of the program execution will be suspended to acquire the trace information The number of clocks to be suspended during execution of the program is the maximum is around 20480 peripheral clock 4096 bus clock B The program will be suspended for 676 524 when the peripheral clock P is 33 3MHz the bus clock Bd is 66 6MHz Branch trace If breaks occur immediately after executing non delayed branch and TRAPA instructions and generating a branch due to exception or interrupt a trace for one branch will not be acquired immediately before such breaks However this does not affect on generation of breaks caused by a BREAKPOINT and a break before executing instructions of Event Condition Writing memory immediately before generating a break If an instruction is executed to write memory immediately before generating a break trace acquisition may not be performed Rev 1 00 Nov 26 2007 Page 32 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 AUD Trace Functions This function is operational when the AUD pin of the device is connected to the emulator The AUD trace functions are common resources for CPUO or CPUI and can be set by the High performance Embedded Workshop insta
8. of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications You should use the products described herein withi
9. the instruction and data caches to 0 after loading of the program has been completed If memory is read from or written to the disabled cache area cache is not searched for but the external area is accessed Note The CPU side which loaded the program operates the above instructions after completing the load however the other which did not load the program will not perform the above operations even the cache is available When the updating for the cache is needed perform Rev 1 00 Nov 26 2007 Page ldof48 0000000000000 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 the program load in both of CPUO side and CPUI side or flash the cache by operating the control register for the cache in the CPU which did not the load the program 9 Multiplexing the AUD Pins The AUD pins are multiplexed as shown in table 2 5 Table 2 5 Multiplexed Functions MCU Function 1 Function 2 SH7265 PJ5 VIDATA0 DACK3 DACT3 AUDCK SH7205 PJ6 VIDATA1 TEND3 AUDSYNC PJ7 VIDATA2 TIOC1A AUDATAO PJ8 VIDATA3 TIOC1B AUDATA1 PJ9 VIDATA4 SSCK1 AUDATA2 PJ10 VIDATA5 SSI1 AUDATAS Note Function 1 can be used when the AUD pins of the device are not connected to the emulator The AUD pins are multiplexed with other pins When the AUD function is used by the emulator AUD pins are used regardless of the settings of the pin function controller PFC 10 Using WDT The WDTO or WDT1
10. the memory window of one High performance Embedded Workshop the contents of the memory window for the other High performance Embedded Workshop are not updated automatically To force updating in such cases execute a refresh from the memory window or issue the command REFRESH 2AD on the command line The same applies to other windows which display the contents of memory that is forcible updating is required on the side where the change was not made 3 Software break Do not set the software break to the same address from the High performance Embedded Workshop for the CPUO side and the one for the CPU1 side Do not set the software break at the address of an instruction which will be executed by both CPUO and CPU1 4 Event Condition Event conditions can be set from the High performance Embedded Workshops for both CPUO and CPU1 When an Event Condition is modified or added from one High performance Embedded Workshop the Event window in the other High performance Embedded Workshop is not updated automatically To force updating in such cases issue the command REFRESH_2AD on the command line Operations on one High performance Embedded Workshop should not proceed while the Event condition dialog box on the other the High performance Embedded Workshop is open Close the Event condition dialog box before proceeding with operations on the other the High performance Embedded Workshop When DMA is selected as the bus co
11. 1 Connecting the Emulator with the User System PVcc l O power supply All pulled up at 4 7 kQ PVcc PVcc PVcc PVcc PVcc PVcc H UDI port connector 14 pin type SH7265 SH7205 ASEBRKAK ASEBRK TMS TDI Reset signal User system Figure 1 4 Recommended Circuit for Connection between the H UDI Port Connector and MCU when the Emulator is in Use 14 Pin Type Rev 1 00 Nov 26 2007 Page 7 of 48 RENESAS REJ10J1767 0100 Section 1 Connecting the Emulator with the User System 1 55 2 Recommended Circuit 38 Pin Type Figure 1 5 shows a recommended circuit for connection between the H UDI and AUD port connectors 38 pins and the MCU when the emulator is in use Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 10 11 The ASEMD pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMD 0 2 When the emulator is not used ASEMD 1 Figure 1 5 shows an example of circuits that allow the ASEMD pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the ASEMD pin is changed by switches etc ground pin 3 Do not connect this pin to the ASEMD pin When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MCU must be as short as possible Do no
12. 10A USB Multi 38 pin V4 user system interface cable 2 5767004 2 38 2 ge EZ Area to be kept free of other components Target system H UDI port connector Figure 1 1 Restriction on Component Mounting 1 4 Pin Assignments of the H UDI Port Connector Figures 1 2 and 1 3 show the pin assignments of the 14 pin and 38 pin H UDI port connectors respectively Note Note that the pin number assignments of the H UDI port connector shown on the following pages differ from those of the connector manufacturer Rev 1 00 Nov 26 2007 Page 3 of 48 RENESAS REJ10J1767 0100 Section 1 Connecting the Emulator with the User System Signal Hd d put TCK Input TRST Input TDO Output ASEBRKAK Input ASEBRK 2 Output TMS Input TDI Input RES Output N C GND 11 Output 10 12 13 GND mm 14 GND Output Notes 1 Input to or output from the user system 2 The symbol means that the signal is active low SH7265 SH7205 Pin No J19 K20 J20 L20 User reset 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 When the user system interface cable is connected to this pin and the ASEMD pin is set to 0 do not connect to GND but to the ASEMD pin directly Pin 1 mark 1 mark a H UDI port connector top view H UDI port connector top view Figure 1 2 Pin Assignments of the H UDI Port Connector 14 Pins Rev
13. 2713 2999 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Technology Korea Co Ltd Kukje Center Bldg 18th Fl 191 2 ka Hangang ro Yongsan ku Seoul 140 702 Korea Tel 82 2 796 3115 Fax 82 2 796 2145 Renesas Technology Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jalan Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 603 7955 9390 Fax 603 7955 9510 Colophon 6 0 SuperH Family E10A USB Multi core Emulator Additional Document for User s Manual Supplementary Information on Using the SH7265 and SH7205 2 NEC S AS RenesasTechnology Corp 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan
14. CPU core condition as CPUO Set I Trace as Ch5 to Ch4 PtoP in the Combination action Sequential or PtoP dialog box When point to point and trace acquisition condition are set simultaneously they are ANDed Rev 1 00 Nov 26 2007 Page 30 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 Notes on Internal Trace Acquiring internal trace To acquire the internal trace both of CPUO and CPUI must be in the execution states after the trace acquisition condition has been set If execution of one of CPUs is stopped acquisition of the internal trace is halted Timestamp The timestamp is the clock counts of Bd 48 bit counter Table 2 17 shows the timing for acquiring the timestamp Table 2 16 Timing for the Timestamp Acquisition Item Acquisition Information Counter Value Stored in the Trace Memory F bus fetch Counter value when a fetch has been completed M bus data access Counter value when data access read or write has been completed Branch Counter value when the next bus cycle has been completed after a branch I bus Fetch Counter value when a fetch has been completed Data access Counter value when data access has been completed Point to point The trace start condition is satisfied when the specified instruction has been fetched Accordingly if the trace start condition has been set for the overrun fetched instruction an instruction tha
15. I Trace mode Set the following in the Event Condition 1 or Event Condition 2 dialog box Address condition Set Address and H FFF80000 Bus state condition Set M Bus and Write CPU core condition Set CPUO Action condition Disable Acquire Break and set Acquire Trace for Stop Example of acquiring only write access M bus to H FFF80000 in CPUO by the user program trace acquisition condition Select M Bus amp Branch CPUO from Channel 1 and enable Write and Data access on Acquisition Set the following in the Event Condition 1 or Event Condition 2 dialog box Address condition Set Address and H FFF80000 Bus state condition Set M Bus and Write CPU core condition Set CPUO Action condition Disable Acquire Break and set Acquire Trace for Condition Rev 1 00 Nov 26 2007 Page 29 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 For the trace acquisition condition the condition to be acquired by Event Condition should be acquired by I Trace mode e Example of acquiring a trace for the period while the user program executed in CPUO passes H 1000 through H 2000 point to point Set the condition to be acquired on I Trace mode Set the address condition as H 1000 in the Event Condition 5 dialog box and the CPU core condition as CPUO Set the address condition as H 2000 in the Event Condition 4 dialog box and the
16. O e Data access read write e Instruction fetch F Bus CPUO Acquires the data on the F bus for CPUO e Instruction fetch M Bus amp Branch CPU1 Acquires the data and branch information on the M bus for CPU1 e Data access read write e PC relative access e Branch information e Software trace I Bus CPU1 Acquires the data on the I bus for CPU1 e Data access read write e Instruction fetch F Bus CPU1 Acquires the data on the F bus for CPU1 e Instruction fetch Rev 1 00 Nov 26 2007 Page 26 of 48 REJ10J1767 0100 34 NE SAS Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 11 Information on Acquiring the Internal Trace cont Item Acquisition Information Note DMAC Acquires the access of the internal DMA bus Selected only for e Internal DMA write bus access Channel 1 e Internal DMA read bus access None Selects no acquisition information this itemis only Selected only for set when 1024 step trace information is acquired in Channel 2 Channel 1 Note It is not possible to select the same items for Channel 1 and Channel 2 Acquired information can be selected from the Acquisition item for the bus information specified for Channel 1 or Channel 2 Table 2 12 Acquired Information Item Description M bus I bus F bus Read Selects acquisition of the read Enabled Enabled Disabled cycle on
17. REJ10J1767 0100 Everywhere you imagine g 2 E N ESAS SuperH Family E10A USB Multi core Emulator Additional Document for User s Manual Supplementary Information on Using the SH7265 and SH7205 Renesas Microcomputer Development Environment System SuperH Family E10A USB Multi core for SH7265 HS7265KCU04HE Rev 1 00 R Technol Revision Date Nov 26 2007 E his id Rev 1 00 Nov 26 2007 Page ii of vi REJ10J1767 0100 7tENESAS Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology de
18. box Displays the contents including the DMAC operation among the acquired trace information Rev 1 00 Nov 26 2007 Page 33 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 To set the AUD trace acquisition mode click the Trace window with the right mouse button and select Setting from the pop up menu to display the Acquisition dialog box The AUD trace acquisition mode can be set in the AUD model or AUD mode2 group box in the Trace mode page of the Acquisition dialog box Acquisition Trace mode AUD Trace CPU 0 AUD Trace CPL 1 Trace type C FTrace AUD function I irace mode Channel 1 1 li amp Branch CPU 0 Gl 714999799742 Instruction Fetch When trace BUTTER Tul AUD mode AUD model Realtime trace C Mon realtime trace AUD mode2 Trace continue C Trace stop AUD trace display range Start pointer D 255 End pointer po Display Type IV CPU DMAC Figure 2 2 Trace mode Page Rev 1 00 Nov 26 2007 Page 34 of 48 REJ10J1767 0100 RENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 When the AUD trace function is used select the AUD function radio button in the Trace type group box of the Trace mode page Select the AUD Trace CPUO and AUD Trace CPU1 pages for tracing execution of CPUO and CPUI resp
19. cified by using Event Condition 7 8 The Ch1 2 3 and Ch7 8 list boxes of the Combination action Sequential or PtoP dialog box can be used Table 2 19 Measurement Period Classification Item Description Selection in Performance For CPUO performance measurement the period from the the Ch1 2 3 Ch2 to Ch1 satisfaction of the condition set in Event Condition 2 start list box PtoP for CPUO condition to the satisfaction of the condition set in Event Condition 1 end condition is set as the performance measurement period Performance For CPUO performance measurement the period from the Ch1 to Ch2 satisfaction of the condition set in Event Condition 1 start PtoP for CPUO condition to the satisfaction of the condition set in Event Condition 2 end condition is set as the performance measurement period Other than The period from the start of execution of the user program to the above occurrence of a break is measured Selection in Performance For CPU1 performance measurement the period from the the Ch7 8 Ch8 to Ch7 satisfaction of the condition set in Event Condition 8 start list box PtoP for CPU1 condition to the satisfaction of the condition set in Event Condition 7 end condition is set as the performance measurement period Performance For CPU1 performance measurement the period from the Ch7 to Ch8 satisfaction of the condition set in Event Condition 7 start PtoP for CPU1 condition to the satisfaction of t
20. ck boxes in the Trace Settings group box Each channel will become valid iv Specify the bus cycle memory range bus type and bus type to be set for each channel Rev 1 00 Nov 26 2007 Page 37 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 Acquisition Trace mode AUD Trace CPU 0 AUD Trace CPU m Trace Settings Branch trace C v Window trace v Channel Software trace v Channel B Branch racc Vy Scaune Hart JI Ghee F SUubroUTIA Iv Acquire e Window Trace Channel Read Write C Read C Write Read Write Start address Ho End address Ho Bus state M Bus m r Channel B Read Write C Read C 6 Read Write Start address Ho End address Ho Bus state M Bus Figure 2 4 Setting Window Trace in the AUD Trace CPU0 Page Note When M Bus or DMAC is selected the following bus cycles will be traced e M Bus A bus cycle generated by the CPU is acquired A bus cycle is also acquired when the cache has been hit e DMAC A bus cycle generated by the DMA is acquired Rev 1 00 Nov 26 2007 Page 38 of 48 REJ10J1767 0100 RENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 c Software Trace Function Note This function is supported with SHC C compiler manufactured by Renesas Technology Corp including OEM and bundle products V7 0 or later A software t
21. cription Acquisition Trace continue This function overwrites the oldest trace information to store mode when the latest trace information the on chip Trace stop After the trace buffer becomes full the trace information is no trace buffer longer acquired The user program is continuously executed becomes full 9 q prog y Break Breaks the user program The contents to be displayed in the Trace window can be selected from table 2 15 according to the Display Type item The Display Type item can be set separately by the High performance Embedded Workshop for CPUO and CPUI Table 2 14 Contents to be Displayed in the Trace Window Type Description CPUO check box Displays the contents including the CPUO operation among the acquired trace information CPU1 check box Displays the contents including the CPU1 operation among the acquired trace information DMAC check box Displays the contents including the DMAC operation among the acquired trace information After selecting Channel 1 or Channel 2 of I Trace mode select the content to be acquired from Acquisition Typical examples are described below note that items disabled for Acquisition are not acquired e Example of acquiring only 1024 step branch information executed in CPUO Select M Bus amp Branch CPUO from Channel 1 and enable Branch on Acquisition Select None from Channel 2 e Example of acquiring only 1024 step r
22. ctor has the 14 pin and 38 pin types as described below Use them according to the purpose of the usage 1 14 pin type without AUD interface The H UDI function is supported The AUD function is not available 2 38 pin type with AUD interface This connector supports AUD tracing through which a large amount of trace information can be acquired in realtime It also supports window tracing i e acquisition of the addresses and data involved in access to a specified area of memory Rev 1 00 Nov 26 2007 Page 2 of 48 REJ10J1767 0100 7tENESAS Section 1 Connecting the Emulator with the User System 1 3 Installing the H UDI Port Connector on the User System Table 1 3 shows the recommended H UDI port connectors for the emulator Table 1 3 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 14 pin connector 7614 6002 Sumitomo 3M Limited 14 pin straight type 38 pin connector 2 5767004 2 Tyco Electronics AMP K K 38 pin Mictor type Note If you are using the 14 pin H UDI connector do not mount any other component within 3 mm of the user system connector and wiring runs to the MCU When designing the layout for the 38 pin connector on the user board reduce cross talk noise etc by keeping other signal lines out of the region where the H UDI port connector is situated As is shown in figure 1 1 an upper limit 5 mm applies to the heights of components mounted around the user system connector E
23. e manual change the I O register definition file according to the description in the hardware manual The I O register definition file can be customized depending on its format However the emulator does not support the bit field function Verify In the IO window the verify function of the input value is disabled 13 Illegal Instructions Do not execute illegal instructions with STEP type commands Rev 1 00 Nov 26 2007 Page 16 of 48 REJ10J1767 0100 RENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 14 Reset Input During execution of the user program the emulator may not operate correctly if a contention occurs between the following operations for the emulator and the reset input to the target device Setting an Event Condition Setting an internal trace Displaying the content acquired by an internal trace Reading or writing of a memory Note that those operations should not contend with the reset input to the target device 2 2 Specific Functions for the Emulator when Using the SH7265 and SH7205 2 2 1 Event Condition Functions The emulator is used to set event conditions for the following three functions e Break of the user program e Internal trace e Start or end of performance measurement The Event Condition functions are common resources for CPUO or CPU1 and can be set by the High performance Embedded Workshop installed in either of the CPUs Table 2 7 lists the types of
24. ead or write access M bus in CPUO by a user program Select M Bus amp Branch CPUO from Channel 1 and enable Read Write and Data access on Acquisition Select None from Channel 2 e Example of acquiring only 1024 step read access by DMA Rev 1 00 Nov 26 2007 Page 28 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 Select DMAC from Channel 1 and enable Read on Acquisition Select None from Channel 2 Using Event Condition restricts the condition the following three items are set as the internal trace conditions Table 2 15 Trace Conditions of the Internal Trace Item Acquisition Information Trace halt Acquires the internal trace until the Event Condition is satisfied The trace content is displayed in the Trace window after a trace has been halted No break occurs in the user program Trace acquisition Acquires only the data access where the Event Condition is satisfied Point to point Traces the period from the satisfaction of Event Condition 4 to the satisfaction of Event Condition 5 To restrict trace acquisition to access for only a specific address or specific function of a program an Event Condition can be used Typical examples are described below Example of halting a trace with a write access M bus to H FFF80000 in CPUO by the user program as a condition trace halt Set the condition to be acquired on
25. ectively a Branch Trace Function The branch source and destination addresses and their source lines are displayed Setting Method i Select the AUD Trace CPUO page or the AUD Trace CPU1 page ii Branch trace can be acquired by selecting the Branch trace check box in the Trace Settings group box The branch type can be selected in the Branch trace group box Rev 1 00 Nov 26 2007 Page 35 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 Acquisition Trace mode AUD Trace CPU AUD Trace CPUs Trace Settings v Branch trace Window trace Software trace Branch Trace v Acquire normal branch instruction trace v Acquire subroutine branch instruction trace v Acquire exception branch instruction trace Figure 2 3 Setting Branch Trace in the AUD Trace CPU0 Page Rev 1 00 Nov 26 2007 Page 36 of 48 REJ10J1767 0100 RENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 b Window Trace Function Memory access in the specified range can be acquired by trace Two memory ranges can be specified for channels A and B The read write or read write cycle can be selected as the bus cycle for trace acquisition Setting Method i Select the AUD Trace CPUO page or the AUD Trace CPU1 page ii Select the Window trace check box in the Trace Settings group box iii Select the Channel A and Channel B che
26. et in the dialog box X Cannot be set in the dialog box 2 For the CPU Select item 0 1 and DMA Setting a condition is enabled when CPUO CPU1 and internal DMA bus are accessed 0 and 1 Setting a condition is enabled when CPUO and CPU1 are accessed Rev 1 00 Nov 26 2007 Page 19 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 3 For the Action item B Setting a break is enabled T1 Setting the trace halt and acquisition conditions are enabled for the internal trace T2 Setting the trace halt is enabled for the internal trace T3 Setting the trace halt and point to point is enabled for the internal trace P1 Setting a performance measurement start or end condition is enabled for CPUO P2 Setting a performance measurement start or end condition is enabled for CPU1 4 The Event Condition 11 dialog box is used to specify the count of Event Condition 1 and becomes a reset point when the sequential condition is specified Rev 1 00 Nov 26 2007 Page 20 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 Sequential Setting Using the Combination action Sequential or PtoP dialog box specifies the sequential condition and the start or end of performance measurement Table 2 9 Conditions to Be Set Classification Item Description Ch1 2 3 list box Sets the sequential condition and the start or end of pe
27. for the MCU where a break has occurred does not operate during break 11 Loading Sessions Information in JT AG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be 5 00 MHz Rev 1 00 Nov 26 2007 Page 15 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 12 IO Window Display and modification There are two registers to be separately used for write and read operations Table 2 6 Register with Different Access Size Register Name Usage Register WTCSRO W Write Watchdog timer control status register WTCSR1 W Write Watchdog timer control status register WTCNTO W Write Watchdog timer counter WTCNT1 W Write Watchdog timer counter WTCSRO R Read Watchdog timer control status register WTCSR1 R Read Watchdog timer control status register WTCNTO R Read Watchdog timer counter WTCNT1 R Read Watchdog timer counter WRCSRO W Write Watchdog reset control status register WRCSR1 W Write Watchdog reset control status register WRCSRO R Read Watchdog reset control status register WRCSR1 R Read Watchdog reset control status register Customization of the I O register definition file After the I O register definition file SH2A_D1 i0 is created the MCU s specifications may be changed If each I O register in the I O register definition file differs from addresses described in the hardwar
28. have no liability for damages arising out of such detachment This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries Rev 1 00 Nov 26 2007 Page iii of vi RENESAS REJ10J1767 0100 Rev 1 00 Nov 26 2007 Page iv of vi REJ10J1767 0100 RENESAS Contents Section 1 Connecting the Emulator with the User System 1 1 1 Components of the 1 1 2 Connecting the Emulator with the User System 0 esee 2 1 3 Installing the H UDI Port Connector on the User System seeeeeeeee 3 1 4 Pin Assignments of the H UDI Port Connector eeseeeeeeeeeereneen eene 3 1 5 Recommended Circuit between the H UDI Port Connector and the MCU 6 1 5 1 Recommended Circuit 14 Pin Type eese 6 1 5 2 Recommended Circuit 38 Pin Type sese 8 Section 2 Software Specifications when Using the SH7265 and SH7205 11 2 1 Differences between the MCU and the Emulator oo eee eee 11 2 2 Specific Functions for the Emulato
29. he condition set in Event Condition 8 end condition is set as the performance measurement period Other than The period from the start of execution of the user program to the above occurrence of a break is measured Rev 1 00 Nov 26 2007 Page 42 of 48 REJ10J1767 0100 34 NE SAS Section 2 Software Specifications when Using the SH7265 and SH7205 Performance Analysis Condition GPUs Channel 1 Elapsed time e Channel 2 Disabled e Channel 3 Disabled Channel 4 Disabled e Channel 1 Disabled e Channel 2 Disabled e Channel 3 Disabled e Channel 4 Disabled M Figure 2 5 Performance Analysis Dialog Box For measurement tolerance e The measured value includes tolerance e Tolerance will be generated before or after a break Notes 1 When Performance Ch2 to Chl PtoP for CPUO or Performance Ch1 to Ch2 PtoP for CPUO is selected to execute the user program specify conditions set in Event Condition 2 and Event Condition 1 and one or more items for performance measurement Similarly when Performance Ch8 to Ch7 PtoP for CPUO or Performance Ch7 to Ch8 PtoP for CPUO is selected to execute the user program specify conditions set in Event Condition 8 and Event Condition 7 and one or more items for performance measurement Rev 1 00 Nov 26 2007 Page 43 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the
30. hort break Cache access is enabled The stopping time of the user program is long because the user program temporarily breaks Note Accessing memory to cache control registers 1 and 2 is fixed as a short break during execution of the user program The method for accessing memory during execution of the user program is specified by using the Configuration dialog box Table 2 3 Stopping Time by Memory Access Reference Method Condition Stopping Time H UDI read write Reading of one longword for the internal RAM Reading Maximum three bus clocks Writing of one longword for the internal RAM Writing Maximum two bus clocks Short break CPU clock 66MHz JTAG clock 5MHz Reading or writing of one longword for the external area About 20ms 7 Memory Access to the External Flash Memory Area The emulator can download the load module to the external flash memory area for details refer to section 6 22 Download Function to the Flash Memory Area in the SuperH Family E10A USB Multi core Emulator User s Manual Other memory write operations are enabled for the RAM area Therefore an operation such as memory write or BREAKPOINT should be set only for the RAM area 34 NE SAS Rev 1 00 Nov 26 2007 Page 13 of 48 REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 8 Operation while Cache is Enabled When cache is enabled the emu
31. instruction access stall ARIS All area data access stall ARDS Note Selected names are displayed for CONDITION in the Performance Analysis window Options are parameters for lt mode gt of the PERFORMANCE_SET command Note In the non realtime trace mode of the AUD trace normal counting cannot be performed because the generation state of the stall or the execution cycle is changed 2eENESAS Rev 1 00 Nov 26 2007 Page 45 of 48 REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 2 Displaying the measured result The measured result is displayed in the Performance Analysis window or the PERFORMANCE ANALYSIS command with hexadecimal 32 bits Note Ifa performance counter overflows as a result of measurement will be displayed 3 Initializing the measured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE ANALYSIS command Rev 1 00 Nov 26 2007 Page 46 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 2 3 Notes on SH7265 and SH7205 E10A USB Multi core Emulator Table 2 21 Notes No Function Name Note 1 The external flash memory When using the emulator to program the external flash memory break execution by both CPUs beforehand 2 Memory window Even when the contents of memory are modified in
32. lator operates as shown in table 2 4 Table 2 4 Operation while Cache is Enabled Function Operation Notes Memory write Searches for whether or not the address to be written hits the instruction and operand caches e When the address hits the corresponding position of the data array is changed by the data to be written and single write is performed to the external area e When the address does not hit the cache contents are not changed and single write is performed to the external area The contents of the address array are not changed before or after writing of memory Memory read Searches for whether or not the address to be read hits the operand cache e When the address hits the corresponding position of the data array is read e When the address does not hit single write is performed to the external area The instruction cache is not searched for The contents of the address array are not changed before or after reading of memory BREAKPOINT Clears the V and LRU bits of all entries in the instruction cache to 0 if a BREAKPOINT is set or canceled Clears the V and LRU bits of all entries in the instruction cache to 0 if a break occurs when a BREAKPOINT has been set Use the Event Condition if you do not wish to change the contents of the instruction cache Program load Writes the contents of the data cache to the external memory and clears the V and LRU bits of entries in
33. lled in either of the CPUs Table 2 17 shows the AUD trace acquisition mode that can be set in each trace function Table 2 17 AUD Trace Acquisition Mode Type Mode Description Continuous Realtime trace trace occurs When the next branch occurs while the trace information is being output all the information may not be output The user program can be executed in realtime but some trace information will be lost Non realtime trace When the next branch occurs while the trace information is being output the CPU stops operations until the information is output The user program is not executed in realtime Trace buffer Trace continue full This function overwrites the oldest trace information to store the latest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed The contents to be displayed in the Trace window can be selected from table 2 18 according to the item of Display Type The item of Display Type can be set separately by the High performance Embedded Workshop for CPUO and Table 2 18 Contents to be Displayed in the Trace Window Type Description CPUO check box Displays the contents including the CPUO operation among the acquired trace information CPU1 check box Displays the contents including the CPU1 operation among the acquired trace information DMAC check
34. n of the user program is started It also applies when the value is changed by the REGISTER_SET command 2 The emulator uses the H UDI do not access the H UDI Rev 1 00 Nov 26 2007 Page 11 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 3 Low Power States The single processor state can be cleared with either the STOP button or a break after satisfaction of the conditions of the Event Condition function and a break will then occur The dual sleep state can be cleared with either the STOP button or a break after satisfaction of the conditions of the Event Condition function and a break will then occur When Sleep is selected for Standby Mode in the Configuration dialog box the software standby and deep standby states become the dual sleep state Accordingly the state can be cleared with either the STOP button or a break after satisfaction of the conditions of the Event Condition function and a break will then occur When Standby is selected for Standby Mode in the Configuration dialog box the software standby and deep standby states transit to their respective standby states as does the MCU The memory must not be accessed or modified in the software standby state The memory must not be accessed or modified in the deep standby state When the emulator is in use the state is in pseudo deep standby The operation of registers whose val
35. n the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall
36. ndition specify either Read or Write as the Read and Write conditions i e do not specify both Read and Write at the same time 5 Trace The traces for both CPUO and CPU1 are being displayed at the same time by selecting the buttons for both CPUs in the Display type group box of the Acquisition dialog box do not select supplementation of branch trace information Rev 1 00 Nov 26 2007 Page 47 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 21 Notes cont No Function Name Note 6 Performance Performance settings can be made from the High performance Embedded Workshop for both CPUO and CPU1 When performance settings are updated by one High performance Embedded Workshop the performance window on the other High performance Embedded Workshop will not be updated automatically To update the window issue the command REFRESH 2AD on the command line 7 Memory access If a break has been generated for one CPU at a time when during execution of execution of the other CPU should be temporarily suspended the user program by a short break for memory access execution of the CPU may continue despite generation of the short break To force updating in such cases issue the command REFRESH_2AD on the command line Rev 1 00 Nov 26 2007 Page 48 of 48 REJ10J1767 0100 RENESAS SuperH Family E10A USB Multi core Emulator Additional Document for U
37. of which intervals are satisfied closely is set no sequential condition will be satisfied e For the same core set the Event conditions which are satisfied closely by the program counter with intervals of two or more instructions e For the same core after the data access condition has been matched set the Event condition by the program counter with intervals of 17 or more instructions If the settings of the Event condition or the sequential conditions are changed during execution of the program execution will be suspended The number of clocks to be suspended during execution of the program is 102 bus clocks B If the bus clock Bo is 66 6 MHz the program will be suspended for 1 53 us If the settings of Event conditions or the sequential conditions are changed during execution of the program the emulator temporarily disables all Event conditions to change the settings During this period no Event condition will be satisfied If the break condition before executing an instruction is set to the instruction followed by DIVU and DIVS the factor for halting a break will be incorrect under the following Rev 1 00 Nov 26 2007 Page 23 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 condition If a break occurs during execution of the above DIVU and DIVS instructions the break condition before executing an instruction which has been set to the next instruction may be dis
38. ons when Using the SH7265 and SH7205 If the start condition is satisfied after the end condition has been satisfied by the point to point of the internal trace trace acquisition will be restarted When a sequential break is satisfied the CPU core in which a break will occur is CPUO or CPU1 specified by the Ch1 condition Usage Example of Sequential Break Extension Setting A tutorial program provided for the product is used as an example For the tutorial program refer to section 6 Tutorial in the SuperH Family EIOA USB Multi core Emulator User s Manual Notes 1 If the Event condition is set for the slot in the delayed branch instruction by the program counter after execution of the instruction the condition is satisfied before executing the instruction in the branch destination when a break has been set it occurs before executing the instruction in the branch destination Do not set the Event condition for the SLEEP instruction by the program counter after execution of the instruction When the Event condition is set for the 32 bit instruction by the program counter set that condition in the upper 16 bits of the instruction If the power on reset and the Event condition are matched simultaneously no condition will be satisfied Do not set the Event condition for the DIVU or DIVS instruction and the instruction followed by DIVU and DIVS by the program counter after execution of the instruction If a condition
39. played as the factor for halting a break 10 If the break conditions before and after executing instructions are set to the same address the factor for halting a break will be incorrectly displayed The factor for halting a break due to the break condition after executing an instruction will be displayed even if a break is halted by the break condition before executing an instruction 11 Do not set the break condition after executing instructions and BREAKPOINT software break to the same address 12 When the emulator is being connected the user break controller UBC function is not available 2 2 2 Trace Functions The emulator supports the trace functions listed in table 2 10 Table 2 10 Trace Functions Function Internal Trace AUD Trace Branch trace Supported Supported Memory access trace Supported Supported Software trace Supported Supported Rev 1 00 Nov 26 2007 Page 24 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 Internal Trace Function When I Trace is selected for Trace type on the Trace Mode page of the Acquisition dialog box the internal trace can be used Acquisition Trace mode Trace type Trace C AUD function FTrace mode Channel 1 M Bus Branch GPUO Acquisition v Read v Write v PG relative addressing v Branch v Software v Data access Instruction Fetch r Channel 2
40. r when Using the SH7265 and SH7205 17 2 2 1 Event Condition Functions essent een eene nre rennen 17 2 2 2 Trace PHBCLIOUS er Pee 24 2 2 3 Note on Using the JTAG H UDI Clock 40 2 2 4 Notes on Setting the Breakpoint Dialog Box see 40 2 2 5 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION SET Command eee 40 2 2 6 Performance Measurement Function sese 41 2 3 Notes on SH7265 and SH7205 E10A USB Multi core 47 Rev 1 00 Nov 26 2007 Page v of vi RENESAS REJ10J1767 0100 Rev 1 00 Nov 26 2007 Page vi of vi REJ10J1767 0100 RENESAS Section 1 Connecting the Emulator with the User System Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator The E10A USB Multi core emulator supports the SH7265 and SH7205 Table 1 1 lists the components of the emulator Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks Hard Emulator box 1 HS0005KCUOA4H ware Depth 68 0 mm Width 101 0 mm Height 22 0 mm Mass 73 0 g GIOAGe Muti 2 User system interface 1 14 pin type cable X Length 20 cm Mass 13 0 g User system interface 1 38 pin type cable Bus Length 20 cm Mass 13 0 g USB cable 1 Length
41. race can be used by describing the Trace x function x is a variable name which is compiled and linked on the C source lines For details refer to the SHC manual When the load module is downloaded on the emulator and is executed while a software trace function is valid the PC value that has executed the Trace x function the general register value for x and the source lines are displayed Setting Method i Select the AUD Trace CPUO page or the AUD Trace CPU1 page ii Select the Software trace check box in the Trace Settings group box Notes on AUD Trace 1 When the trace display is performed during user program execution the mnemonics operands or source is not displayed 2 The AUD trace function outputs the differences between newly output branch source addresses and previously output branch source addresses The window trace function outputs the differences between newly output addresses and previously output addresses If the previous branch source address is the same as the upper 16 bits the lower 16 bits are output If it matches the upper 24 bits the lower 8 bits are output If it matches the upper 28 bits the lower 4 bits are output The emulator regenerates the 32 bit address from these differences and displays it in the Trace window If the emulator cannot display the 32 bit address it displays the difference from the previously displayed 32 bit address 3 If the 32 bit address cannot be displayed
42. rformance measurement using Event Conditions 1 to 3 and 11 Don t care Sets no sequential condition or the start or end of performance measurement Break Ch3 2 1 Breaks when a condition is satisfied in the order of Event Condition 3 2 1 Break Ch3 2 1 Breaks when a condition is satisfied in the order of Reset point Event Condition 3 2 1 Enables the reset point of Event Condition 11 Break Ch2 1 Breaks when a condition is satisfied in the order of Event Condition 2 1 Break Ch2 1 Breaks when a condition is satisfied in the order of Reset point Event Condition 2 1 Enables the reset point I Trace stop Ch3 2 1 Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 3 2 1 I Trace stop Ch3 2 1 Reset point Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 3 2 1 Enables the reset point Trace stop Ch2 1 Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 2 1 I Trace stop Ch2 1 Reset point Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 2 1 Enables the reset point Performance Ch2 to Ch1 PtoP for CPUO Sets the performance measurement period for CPUO during the time from the satisfaction of the condition set in Event Condition 2 start condition to
43. rformance measurement period for CPU1 during the time from the satisfaction of the condition set in Event Condition 8 start condition to the satisfaction of the condition set in Event Condition 7 end condition Performance Ch7 to Ch8 PtoP for CPU1 Sets the performance measurement period for CPU1 during the time from the satisfaction of the condition set in Event Condition 7 start condition to the satisfaction of the condition set in Event Condition 8 end condition Notes 1 After the sequential condition and the count specification condition of Event Condition 1 have been set break and trace acquisition will be halted if the sequential condition is satisfied for the specified count 2 Ifa reset point is satisfied the satisfaction of the condition set in Event Condition will be disabled For example if the condition is satisfied in the order of Event Condition 3 2 reset point 1 the break or trace acquisition will not be halted If the condition is satisfied in the order of Event Condition 3 2 reset point 3 2 1 the break and trace acquisition will be halted 3 If the start condition is satisfied after the end condition has been satisfied by measuring performance performance measurement will be restarted For the measurement result after a break the measurement results during performance measurement are added Rev 1 00 Nov 26 2007 Page 22 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specificati
44. scribed herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products With the exception
45. ser s Manual Supplementary Information on Using the SH7265 and SH7205 Publication Date Rev 1 00 November 26 2007 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2007 Renesas Technology Corp All rights reserved Printed in Japan Renesas Technology Corp Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan 2CENESAS RENESAS SALES OFFICES http www renesas com Refer to http www renesas com en network for the latest and detailed information Renesas Technology America Inc 450 Holger Way San Jose CA 95134 1368 U S A Tel lt 1 gt 408 382 7500 Fax lt 1 gt 408 382 7501 Renesas Technology Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel lt 44 gt 1628 585 100 Fax lt 44 gt 1628 585 900 Renesas Technology Shanghai Co Ltd Unit 204 205 AZIACenter No 1233 Lujiazui Ring Rd Pudong District Shanghai China 200120 Tel 86 21 5877 1818 Fax 86 21 6887 7898 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2
46. ses An area other than CS and the internal RAM An instruction in which Break Condition 2 is satisfied A slot instruction of a delayed branch instruction During step operation specifying BREAKPOINTs and Event Condition breaks are disabled When execution resumes from the address where a BREAKPOINT is specified and a break occurs before Event Condition execution single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed When a BREAKPOINT is set to the slot instruction of a delayed branch instruction the PC value becomes an illegal value Accordingly do not set a BREAKPOINT to the slot instruction of a delayed branch instruction If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area a mark will be displayed in the BP area of the address on the Source or Disassembly window by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the event condition the mark disappears 2 2 5 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION SET Command When Go to cursor Step In Step Over or Step Out is selected in CPUO the settings of Event Condition 3 are disabled When Go to cursor Step In Step Over or Step Out is selected in CPUI the settings of Event Condition 5 are disabled When an E
47. t connect the signal lines to other components on the board The AUD signals AUDCK AUDATA3 to AUDATAO and AUDSYNC operate in high speed Isometric connection is needed if possible Do not separate connection nor connect other signal lines adjacently Since the H UDI and the AUD of the MCU operate with the PVcc supply only the PVcc to the UVCC pin The resistance value shown in figure 1 5 is for reference For the AUDCK pin guard the pattern between the H UDI port connector and the MCU at GND level The TRST pin must be at the low level for a certain period when the power is supplied whether the H UDI is used or not The GND bus lead at the center of the H UDI port connector must be grounded For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MCU Rev 1 00 Nov 26 2007 Page 8 of 48 REJ10J1767 0100 7tENESAS Section 1 Connecting the Emulator with the User System power supply All pulled up at 4 7kQ or more PVcc PVcc PVcc H UDI port connector 38 pin type SH7265 SH7205 AUDCK AUDSYNC TL LLLLLL AUDSYNG AUDSYNG AUDATA1 Pp TT ave TT AUDATA3 AUDATAO AUDATAO AUDATA1 AUDATA2 AUDATA3 TCK TMS TRST TDI a TDO ASEBRK RES ASEMD UVCC_AUD Reset signal UCON GND 1 2 4 7 10 13 16 18 20 22 23 25 27 29 31 33 34 35 36 37 38 User system Figure 1 5 Recommended Circuit for Connec
48. t is not executed although it has been fetched at a branch or transition to an interrupt tracing is started during overrun fetching of the instruction However when overrun fetching is achieved a branch is completed tracing is automatically suspended If the start and end conditions are satisfied closely trace information will not be acquired correctly The execution cycle of the instruction fetched before the start condition is satisfied may be traced When the I bus is acquired do not specify point to point Memory access may not be acquired by the internal trace if it occurs at several instructions immediately before satisfaction of the point to point end condition Halting a trace Do not set the trace halt condition for the sleep instruction and the branch instruction that the delay slot becomes the sleep instruction Rev 1 00 Nov 26 2007 Page 31 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 Trace acquisition condition When I Bus M Bus amp Branch is selected and the trace acquisition condition is set for the M bus and I bus with Event Condition set the M bus condition and the I bus condition for Event Condition 1 and Event Condition 2 respectively If the settings of I Trace mode are changed during execution of the program execution will be suspended The number of clocks to be suspended during execution of the program is the maximum is around 51 peripheral
49. the M bus or I bus Write Selects acquisition of the write Enabled Enabled Disabled cycle on the M bus or I bus PC relative addressing Selects acquisition of the PC Enabled Disabled Disabled relative access Branch Selects acquisition of branch Enabled Disabled Disabled information Software Selects acquisition of the software Enabled Disabled Disabled trace Data access Selects acquisition of the data Enabled Enabled Disabled access read or write on the M bus or I bus Instruction Fetch Acquires instruction fetch from the Disabled Enabled Enabled external area Note This function is supported with the SHC C compiler manufactured by Renesas Technology Corp V7 0 or later A software trace can be used by describing the Trace x function x is a variable name which is compiled and linked on the C source lines For details refer to the SHC manual When the load module is downloaded on the emulator and executed while a software trace function is valid the PC value that has executed the Trace x function the general register value for x and the source lines are displayed Rev 1 00 Nov 26 2007 Page 27 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 When the on chip trace buffer becomes full the operation is selected through When trace buffer full from the following modes Table 2 13 Operation Mode when the On Chip Trace Buffer Becomes Full Type Mode Des
50. the satisfaction of the condition set in Event Condition 1 end condition Rev 1 00 Nov 26 2007 Page 21 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 9 Conditions to Be Set cont Classification Item Description Ch1 2 3 listbox Performance Ch1 to Sets the performance measurement period for cont Ch2 PtoP for CPUO CPUO during the time from the satisfaction of the condition set in Event Condition 1 start condition to the satisfaction of the condition set in Event Condition 2 end condition Ch4 5 list box Sets the point to point of the internal trace the start or end condition of trace acquisition using Event Conditions 4 and 5 Don t care Sets no start or end condition of trace acquisition I Trace Ch5 to Ch4 Sets the acquisition period during the time from the PtoP satisfaction of the condition set in Event Condition 5 start condition to the satisfaction of the condition set in Event Condition 4 end condition I Trace Ch5 to Ch4 PtoP power on reset Sets the acquisition period during the time from the satisfaction of the condition set in Event Condition 5 start condition to the satisfaction of the condition set in Event Condition 4 end condition or the power on reset Ch7 8 list box Sets the start or end of performance measurement using Event Conditions 7 and 8 Performance Ch8 to Ch7 PtoP for CPU1 Sets the pe
51. the source line is not displayed 4 If acompletion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 5 Setthe AUD clock AUDCK frequency to 50 MHz or lower If the frequency is higher than 50 MEZ the emulator will not operate normally The AUD clock can be set in the Configuration dialog box 6 If breaks occur immediately after executing non delayed branch and TRAPA instructions and generating a branch due to exception or interrupt a trace for one branch will not be acquired immediately before such breaks However this does not affect on generation of breaks caused by a BREAKPOINT and a break before executing instructions of Event Condition Rev 1 00 Nov 26 2007 Page 39 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 2 2 3 Note on Using the JTAG H UDI Clock TCK 1 Set the JTAG clock TCK frequency to lower than the frequency of the peripheral module clock The initial value of the JTAG clock TCK is 5 00 MHz A value to be set for the JTAG clock TCK is initialized after executing Reset CPU or Reset Go Thus the TCK value will be 5 00 MHz 2 2 4 Notes on Setting the Breakpoint Dialog Box 1 When an odd address is set the next lowest even address is used A BREAKPOINT is accomplished by replacing instructions of the specified address It cannot be set to the following addres
52. tion between the H UDI Port Connector and MCU when the Emulator is in Use 38 Pin Type Rev 1 00 Nov 26 2007 Page 9 of 48 RENESAS REJ10J1767 0100 Section 1 Connecting the Emulator with the User System Rev 1 00 Nov 26 2007 Page 10 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 Section 2 Software Specifications when Using the SH7265 and SH7205 2 1 Differences between the MCU and the Emulator 1 When the emulator system is initiated it initializes the general registers and part of the control registers as shown in table 2 1 The initial values of the MCU are undefined When the emulator is initiated from the workspace a value to be entered is saved in a session Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP Value of the SP in the power on reset vector table PC Value of the PC in the power on reset vector table SR GBR H 00000000 VBR H 00000000 TBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 FPSCR H 00040001 FPUL H 00000000 FPRO 15 H 00000000 Note If the MCU does not incorporate the floating point unit FPU these registers are not displayed Note When a value of the interrupt mask bit in the SR register is changed in the Registers window it is actually reflected in that register immediately before executio
53. ues are held or updated is the same as in the deep standby state of the MCU However the power is not shut down only the clock is halted Do not stop the clock input to the H UDI module by using the module standby function 4 Reset Signals The MCU reset signals are only valid in the emulation state while both of CPUs are being executed If one of CPUs is in a break state reset signals are not sent to the MCU Note Do not break the user program when the RES or WAIT signal is being low A TIMEOUT error will occur If the WAIT signal is fixed to low during break a TIMEOUT error will occur at memory access 5 Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer 6 Memory Access during User Program Execution During execution of the user program memory is accessed by the following two methods as shown in table 2 2 each method offers advantages and disadvantages Rev 1 00 Nov 26 2007 Page 12 of 48 REJ10J1767 0100 134 NE SAS Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 2 Memory Access during User Program Execution Method Advantage Disadvantage H UDI read write The stopping time of the user program is short because memory is accessed by the dedicated bus master Cache access is disabled Actual memory is always accessed by the H UDI read or write S
54. vent Condition is satisfied emulation may stop after two or more instructions have been executed Rev 1 00 Nov 26 2007 Page 40 of 48 REJ10J1767 0100 7tENESAS Section 2 Software Specifications when Using the SH7265 and SH7205 2 2 6 Performance Measurement Function The emulator supports the performance measurement function 1 Setting the performance measurement conditions To set the performance measurement conditions use the Performance Analysis dialog box and the PERFORMANCE SET command When any line in the Performance Analysis window is clicked with the right mouse button a popup menu is displayed and the Performance Analysis dialog box can be displayed by selecting Setting The performance measurement functions are common resources for CPUO or CPUI and can be set by the High performance Embedded Workshop installed in either of the CPUs Setting channels of the CPUO group box measures performance of CPUO Similarly setting channels of the CPU1 group box measures performance of CPUI Note For the command line syntax refer to the online help Rev 1 00 Nov 26 2007 Page 41 of 48 RENESAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 a Specifying the measurement start end conditions For CPUO performance measurement the measurement start end conditions are specified by using Event Condition 1 2 For CPU1 performance measurement the measurement start end conditions are spe
55. which is opened by selecting Combination action Sequential or PtoP from the pop up menu on the Event Condition sheet specifies the sequential condition and the start or end of performance measurement Table 2 8 lists the combinations of conditions that can be set under Ch1 to Ch11 and the software trace Rev 1 00 Nov 26 2007 Page 18 of 48 3q NE SAS REJ10J1767 0100 Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 8 Dialog Boxes for Setting Event Conditions Function Address Bus Data Bus Bus State Count CPU Core Condition Condition Condition Condition Condition Dialog Box Address Data Bus Status Count CPU Select Action Event Ch1 O O O O O O Condition 1 40 41 and P DMA Event Ch2 O O O X O O Condition 2 40 41 and P DMA Event Ch3 O X X X O O Condition 3 0 and 1 B and T2 Event Ch4 O X X X O O Condition 4 0 and 1 B and T3 Event Ch5 O X X X O Condition 5 0 and 1 B and T3 Event Ch6 O X X X O O Condition 6 0 and 1 B and T2 Event Ch7 O X X X O O Condition 7 0 and 1 B T2 and P Event Ch8 O X X X O O Condition 8 0 and 1 B T2 and P Event Ch9 O X X X O O Condition 9 0 and 1 B and T2 Event Ch10 O X X X O O Condition 10 0 and 1 B and T2 Event Ch11 O X X X O O Condition 11 reset point 0 and 1 B and T2 Notes 1 O Can be s

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