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DSP56311 Users Manual - Freescale Semiconductor

1. I_SCIRD EQU I_SCIRDE EQU I_SCITD EQU I_SCIIL EQU I_SCITM EQU Data Full I_HRDF EQU T_VEC 60 I_HTDE EQU T_VEC 62 THG EQU I_VEC 64 EFCOP Interrupts I_FDIBE EQU T_VEC 68 I_FDOBF EQU I_VEC S6A _VEC S2E _VEC 30 _VEC 32 _VEC 34 _VEC 36 _VEC 38 _VEC S 3A _VEC 40 _VEC 42 _VEC S44 _VEC S 46 _VEC 48 _VEC S4A _VEC 50 _VEC 52 _VEC 54 _VEC 56 _VEC 58 _VEC SFF Freescale Semiconductor Interrupt Equates Exception Status Exception Status Exception Status Exception Status TIMER 2 overflow ESSIO Receive Data ESSIO Receive Data With ESSIO Receive last slot ESSIO Transmit data ESSIO Transmit Data With ESSIO Transmit last slot ESSI1 Receive Data ESSI1 Receive Data With ESSI1 Receive last slot ESSI1 Transmit data ESSI1 Transmit Data With ESSI1 Transmit last slot SCI Receive Data SCI Receive Data With SCI Transmit Data SC dle Line SCI Timer Host Receive Host Transmit Data Exception Status Default Host Command EFCOP EFCOP Output Empty Buffer nput Empty Buffer Full last address of interrupt vector space DSP56311 User s Manual Rev 2 A 21 Bootstrap Program DSP56311 User s Manual Rev 2 A 22 Frees
2. B 8 Interrupt pel ai Interrupt Source Starting Address Range VBA 00 3 Hardware RESET VBA 02 3 Stack Error VBA 04 3 Illegal Instruction VBA 06 3 Debug Request Interrupt VBA 08 3 Trap VBA 0A 3 Non Maskable Interrupt NMI VBA 0C 3 Reserved VBA 0E 3 Reserved VBA 10 0 2 IRQA VBA 12 0 2 IRQB VBA 14 0 2 IRQC VBA 16 0 2 IRQD VBA 18 0 2 DMA Channel O VBA 1A 0 2 DMA Channel 1 VBA 1C 0 2 DMA Channel 2 VBA 1E 0 2 DMA Channel 3 VBA 20 0 2 DMA Channel 4 VBA 22 0 2 DMA Channel 5 VBA 24 0 2 Timer 0 Compare VBA 26 0 2 Timer O Overflow VBA 28 0 2 Timer 1 Compare VBA 2A 0 2 Timer 1 Overflow VBA 2C 0 2 Timer 2 Compare VBA 2E 0 2 Timer 2 Overflow VBA 30 0 2 ESSIO Receive Data VBA 32 0 2 ESSIO Receive Data With Exception Status VBA 34 0 2 ESSIO Receive Last Slot VBA 36 0 2 ESSIO Transmit Data VBA 38 0 2 ESSIO Transmit Data With Exception Status VBA 3A 0 2 ESSIO Transmit Last Slot VBA 3C 0 2 Reserved VBA 3E 0 2 Reserved VBA 40 0 2 ESSI1 Receive Data DSP56311 User s Manual Rev 2 Freescale Semiconductor Table B 4 Interrupt Sources Continued Interrupt Sources and Priorities Interrupt Broa od Interrupt Source Starting Address Range VBA 42 0 2 ESSI1 Receive Data With Exception Status VBA 44 0 2 ESSI1 Receive Last Slot VBA 46 0 2 ESSI1 Transmit Data VBA
3. Reserved bit read as 0 write to 0 for future compatibility Figure 6 15 Interface Control Register ICR Table 6 15 Interface Control Register ICR Bit Definitions Bit Number Bit Name Reset Value Description 7 INIT 0 Initialize The host processor uses INIT to force initialization of the HIO8 hardware During initialization the HI08 transmit and receive control bits are configured Use of the INIT bit to initialize the HIO8 hardware depends on the software design of the interface The type of initialization when the INIT bit is set depends on the state of TREQ and RREQ The INIT command which is local to the HI08 configures the HI08 into the desired data transfer mode When the host sets the INIT bit the HIO8 hardware executes the INIT command The interface hardware clears the INIT bit after the command executes TREQ RREQ After INIT Execution Transfer Direction 0 0 INIT 0 None 0 INIT 0 DSP to host RXDF 0 HTDE 1 INIT 0 Host to DSP TXDE 1 HRDF 0 INIT 0 Host to from DSP RXDF 0 HTDE 1 TXDE 1 HRDF 0 Reserved Write to 0 for future compatibility HLEND Host Little Endian If the HLEND bit is cleared the host can access the HI08 in Big Endian byte order If set the host can access the HIO8 in Little Endian byte order If the HLEND bit is cleared the RXH TXH register is lo
4. DMAO IPL DMA1 IPL DMA2 IPL DMA3 IPL DMA4 IPL DMAS IPL 11 10 9 8 7 6 E 4 5 4 3 2 0 E EN TRQA IPL IRQA mode IRQB IPL IRQB mode TRQC IPL IRQC mode TRQD IPL TRQD mode Figure 4 3 Interrupt Priority Register Core IPRC X FFFFFF DSP56311 User s Manual Rev 2 4 14 Freescale Semiconductor Configuring Interrupts 23 22 21 20 19 18 17 16 15 14 13 12 reserved 11 10 9 8 7 6 5 4 3 2 1 0 gt Tom Toro Sct sco s11 sto soL soLo HPL HPLo HI08 IPL ESSIO IPL ESSI1 IPL SCI IPL TRIPLE TIMER IPL reserved es Reserved bit read as zero write with zero for future compatibility Figure 4 4 Interrupt Priority Register Peripherals IPRP X FFFFFE The DSP56311 has a four level interrupt priority structure Each interrupt has two interrupt priority level bits IPL 1 0 that determine its interrupt priority level Level 0 is the lowest priority Level 3 is the highest level priority and is non maskable Table 4 4 defines the IPL bits Table 4 4 Interrupt Priority Level Bits IPL bits Interrupts Enabled Interrupts Masked Interrupt Priority Level xxL1 xxL0O 0 0 No 0 0 1 Yes 0 1 1 0 Yes O 1 2 1 1 Yes 0 1 2 3 The IPRC also selects the trigger mode of the external interrupts IRQA IRQD If the value of the IxL2 bit is 0 the interrupt mod
5. Transmitter Clock Mode Source O Internal clock for Transmitter 1 External clock from SCLK Clock Out Divider 0 Divide clock by 16 before feed to SCLK 1 Feed clock to directly to SCLK SCI Clock Prescaler O 1 1 8 15 14 13 12 10 9 8 7 ie W Clock Control Register SCCR Address X FFFF9B Read Write Reset 000000 Reserved Program as O Figure B 19 SCI Clock Control Registers SCCR DSP56311 User s Manual Rev 2 Freescale Semiconductor B 30 Programming Sheets Application Date Programmer Sheet 1 of 3 IMers Prescaler Clock Source Internal CLK 2 TIOO TIO1 TIO2 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PS1 PSO 0 Prescaler Preload Value PL 20 0 Timer Prescaler Load Register TPLR X FFFF83 Read Write Reset 000000 Reserved Program as 0 Figure B 20 Timer Prescaler Load Register TPLR DSP56311 User s Manual Rev 2 Freescale Semiconductor B 31 Programming Reference B 32 Application Date Programmer Sheet 2 of 3 Inverter Bit 8 Ti l Je rs O 0 to 1 transitions on TIO input increment the counter or high pulse width measured or high pulse output on TIO 1 1 to 0 transitions on TIO input increment the counter or low pulse width measured or low pulse output on TIO Timer Reload Mode Bit 9 0 Timer operates as a free running counter 1 Timer is reloaded when
6. Last update February 20 1999 A 8 DSP56311 User s Manual Rev 2 Freescale Semiconductor Internal I O Equates 7 eK KKK KKK KKK KKK KKK KEK KR KKK KEK KKK KK KEK KK KKK KE KK KKK KEK KKK KKK KKK KKK KKK KKK KKK KEK KKK KKK EKEK page 132 55 0 0 0 opt mex ioequ ident 1 0 Register Addresses M_HDDR EQU SFFFFC9 Host port GPIO direction Register M_HDR EQU SFFFFC8 Host port GPIO data Register M_PCRC EQU SFFFFBF Port C Control Register M_PRRC EQU SFFFFBE Port C Direction Register M_PDRC EQU SFFFFBD Port C GPIO Data Register M_PCRD EQU SFFFFAF Port D Control register M_PRRD EQU SFFFFAE Port D Direction Data Register M_PDRD EQU SFFFFAD Port D GPIO Data Register M_PCRE EQU SFFFFOF Port E Control register M_PRRE EQU SFFFF9E Port E Direction Register M_PDRE EQU SFFFF9D Port E Data Register M_OGDB EQU SFFFFFC ONCE GDB Register EQUATES for Host Interface Register Addresses M_HCR EQU SFFFFC2 Host Control Register M_HSR EQU SFFFFC3 Host Status Register M_HPCR EQU SFFFFC4 Host Polarity Control Register M_HBAR EQU SFFFFC5 Host Base Address Register M_HRX EQU SFFFFC6 Host Receive Register M_HTX EQU SFFFFC7 Host Transmit Register gt HCR bits definition M_HRIE EQU SO Host Receive interrupts Enable M_HTIE EQU 1
7. Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 01 0 1 80K 24K 24K None 64K 0000 0000 5FFF 0000 5FFF 13FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 15 Memory Switch On MSW 01 Cache Off 16 Bit Mode Freescale Semiconductor DSP56311 User s Manual Rev 2 3 23 Memory Configuration Program X Data Y Data SFERE PERES External I O Internal I O FFCO External FF80 FF80 Internal I O FFFF 1800 External External C000 C000 Internal 6000 6000 Program RAM Internal Y data RAM 24K Internal X data RAM 24K 0000 0000 0000 Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 01 1 1 79K 24K 24K Enabled 64K 0400 17FF 0000 5FFF 0000 5FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 16 Memory Switch On MSW 01 Cache On 16 Bit Mode DSP56311 User s Manual Rev 2 3 24 Freescale Semiconductor Program FFFF FFFF FF80 C000 8000 Internal Program RAM 64K 0000 0000 X
8. DSP56311 User s Manual Rev 2 6 32 Freescale Semiconductor Enhanced Synchronous Serial Interface ESSI 7 The ESSI provides a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator There are two independent and identical ESSIs in the DSP56311 ESSIO and ESSI1 For simplicity a single generic ESSI is described here The ESSI block diagram is shown in Figure 7 1 This interface is synchronous because all serial transfers are synchronized to one clock SRD SCO SC1 SC2 SCK Interrupts Clock Frame Sync Generators and Control Logic Figure 7 1 ESSI Block Diagram This synchronous interface should not be confused with the asynchronous channels mode of the ESSI in which separate clocks are used for the receiver and transmitter In that mode the ESSI is still a synchronous device because all transfers are synchronized to these clocks Pin notations for the generic ESSI refer to the analogous pin of ESSIO PCx and ESSI1 PDx DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 1 Enhanced Synchronous Serial Interface ESSI Additional synchronization signals delineate the word frames The Normal mode of operation transfers data at a periodic rate one word per period The Network m
9. TIO pin INV 1 TOF Overflow Interrupt if TCIE 1 First toggle M N clock periods Second and later toggles 2 2 clock periods Figure 9 8 Toggle Mode TRM 0 DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 9 Triple Timer Module 9 3 1 4 Timer Event Counter Mode 3 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 0 1 1 3 Event Counter Timer Input External In Mode 3 the timer counts external events and issues an interrupt if interrupt enable bits are set when the timer counts a preset number of events The timer clock signal can be taken from either the TIO input signal or the prescaler clock output If an external clock is used it must be internally synchronized to the internal clock and its frequency must be less than the DSP56311 internal operating frequency divided by 4 The value of the TCSR INV bit determines whether low to high 0 to 1 transitions or high to low 1 to 0 transitions increment the counter If the INV bit is set high to low transitions increment the counter If the INV bit is cleared low to high transitions increment the counter When the counter matches the value contained in the TCPR TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set If the TCSR TRM bit is set the counter is loaded with the value of the TLR when the next timer clock is received
10. The MD MA bits reflect the corresponding value of the mode input that is MODD MODA respectively Freescale Semiconductor DSP56311 User s Manual Rev 2 4 13 Core Configuration 4 4 Configuring Interrupts DSP56311 interrupt handling like that for all DSP56300 family members is optimized for DSP applications Refer to the sections describing interrupts in Chapter 2 Core Architecture Overview in the DSP56300 Family Manual Two registers are used to configure the interrupt characteristics E Interrupt Priority Register Core IPRC Programmed to configure the priority levels for the core DMA interrupts and the external interrupt lines as well as the interrupt line trigger modes E Interrupt Priority Register Peripherals IPRP Programmed to configure the priority levels for the interrupts used with the on chip peripheral devices The interrupt table resides in the 256 locations of program memory to which the PCU vector base address VBA register points These locations store the starting instructions of the interrupt handler for each specified interrupt The memory is programmed by the bootstrap program at startup 4 4 1 Interrupt Priority Registers IPRC and IPRP There are two interrupt priority registers in the DSP56311 The IPRC Figure 4 3 is dedicated to DSP56300 core interrupt sources and IPRP Figure 4 3 is dedicated to DSP56311 peripheral interrupt sources 21 2 19 18 17 16 23 22 0 15 14 13 12
11. Data X Read Datacut Data Out HRD Read Cycle In dual strobe mode separate HRD and HWR signals specify the access as a read or write access respectively Figure 6 14 Dual Strobe Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor 6 19 Host Interface HI08 6 6 7 Host Transmit HTX Register The HTX register is used in DSP to host data transfers The DSP56311 views it as a 24 bit write only register Its address is X FFFFC7 Writing to the HTX register clears the host transfer data empty bit HSR HTDE on the DSP side The contents of the HTX register are transferred as 24 bit data to the Receive Data Registers RXH RXM RXL when both HSR HTDE and receive data full ISR RXDF on the host side bits are cleared This transfer operation sets the ISR RXDF and HSR HTDE bits The DSP56311 can set the HCR HTIE bit to cause a host transmit data interrupt when HSR HTDE is set To prevent the previous data from being overwritten the DSP56311 should never write to the HTX when HSR HTDE is cleared Note When data is written to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If you read any of the status bits within the next two cycles the bit does not reflect its current status For details see Section 6 4 1 Software Polling on page 6 6 6 6 8 Host Receive HRX Register The HRX register is used in host to DSP data transfers The DSP5
12. 000000 18 14 13 12 11 Ki KIKI KK KIL KY Ki TAN ee EFCOP Decimation Channel Count Register FDCH Y FFFFB8 Read Write Reset 000000 k Reserved Program as 0 Figure B 28 EFCOP FACR FDBA FCBA and FDCH Registers Freescale Semiconductor DSP56311 User s Manual Rev 2 Programming Reference DSP56311 User s Manual Rev 2 B 40 Freescale Semiconductor Index A adder 1 7 Address Arithmetic Logic Unit Address ALU 1 7 Address Attribute Priority Disable APD bit 4 12 Address Attribute Registers AAR 4 20 4 25 Bus Access Type BAT 4 27 Bus Address Attribute Polarity BAAP 4 26 Bus Address to Compare BAC 4 25 Bus Number of Address Bits to Compare BNC 4 25 Bus Packing Enable BPAC 4 26 Bus Program Memory Enable BPEN 4 26 Bus X Data Memory Enable BXEN 4 26 Bus Y Data Memory Enable BYEN 4 26 programming sheet B 19 Address Generation Unit AGU 1 7 Address Mode Wakeup 8 3 Address Trace Enable ATE bit 4 11 Address Trace mode 1 6 addressing modes 1 8 Alignment Control ALC bit 7 14 Arithmetic Saturation Mode SM bit 4 6 Asynchronous Bus Arbitration Enable ABE bit 4 12 asynchronous data transfer 8 2 Asynchronous mode 7 9 8 2 8 13 8 15 8 16 Asynchronous Multidrop mode 8 15 barrel shifter 1 6 bit oriented instructions 5 1 BCHG 5 1 BCLR 5 1 BRCLR 5 1 BRSET 5 1 BSCLR 5 1 BSET 5 1 BSSET 5 1 BTST 5 1 JCLR 5 1 JSCLR 5 1 JSET 5 1 JSSET 5 1 bootstrap 3 1 3 3 4 4 code
13. 9 2 3 Timer Exceptions Each timer can generate two different exceptions E Timer Overflow highest priority Occurs when the timer counter reaches the overflow value This exception sets the TOF bit TOF is cleared when a value of one is written to it or when the timer overflow exception is serviced Timer Compare lowest priority Occurs when the timer counter reaches the value given in the Timer Compare Register TCPR for all modes except measurement modes In measurement modes 4 6 a compare exception occurs when the appropriate transition occurs on the TIO signal The Compare exception sets the TCF bit TCF is cleared when a value of one is written to it or when the timer compare interrupt is serviced To configure a timer exception perform the following steps The example at the right of each step shows the register settings for configuring a Timer 0 compare interrupt The order of the steps is optional except that the timer should not be enabled step 2e until all other exception configuration is complete 1 9 4 Configure the interrupt service routine ISR a b Load vector base address register VBA b23 8 Define I_VEC to be equal to the VBA value if that is nonzero If it is defined I_VEC must be defined for the assembler before the interrupt equate file is included Load the exception vector table entry two word fast interrupt or jump branch to subroutine long interrupt p TIMOC Configure the
14. External Interrupt Request B After reset this input becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing If the processor is in the WAIT standby state and IRQB is asserted the processor exits the WAIT state 2 8 DSP56311 User s Manual Rev 2 Freescale Semiconductor Table 2 9 Interrupt and Mode Control Continued HI08 Signal Name Type State During Reset Signal Description MODC Input Input Schmitt trigger Mode Select C MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the Input RESET signal is deasserted External Interrupt Request C After reset this input becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing If the processor is in the WAIT standby state and IRQC is asserted the processor exits the WAIT state MODD Input Input Input Schmitt trigger Mode Select D MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is deasserted External Interrupt Request D After reset this input becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing If the processor is in the WAIT standby state and IRQD is asserted the p
15. Output Buffer FDOR Figure 10 1 EFCOP Block Diagram 10 2 1 PMB Interface The PMB interface block contains control and status registers buffers the internal bus from the PMB decodes and generates addresses and controls the handshake signals required for DMA and interrupt operations The block generates interrupt and DMA trigger signals for data transfers The interface registers accessible to the DSP56300 core through the PMB are summarized in Table 10 1 Table 10 1 EFCOP Registers Accessible Through the PMB Register Name Description Filter Data Input Register FDIR A 4 word deep 24 bit wide FIFO used for DSP to EFCOP data transfers Data from the FDIR is transferred to the FDM for filter processing Filter Data Output Register FDOR A 24 bit wide register used for EFCOP to DSP data transfers Data is transferred to FDOR after processing of all filter taps is completed for a specific set of input samples Filter K Constant Input Register FKIR A 24 bit register for DSP to EFCOP constant transfers Filter Count FONT Register A 24 bit register that specifies the number of filter taps The count stored in the FCNT register is used by the EFCOP address generation logic to generate correct addressing to the FDM and FCM EFCOP Control Status Register FCSR A 24 bit read write register used by the DSP56300 core to program the EFCOP and to examine the
16. 0 0 cece cece eee e eens 10 35 Filter Data Input Register FDIR 2 0 0 eect nee eee 10 35 Filter Data Output Register FDOR 0 0 0 een nee eens 10 35 Filter K Constant Input Register FKIR 0 0 ee eee een eee 10 36 Filter Count FCNT Register 0 0 cence nee e ene 10 36 EFCOP Control Status Register FCSR 0 0 0 cee eens 10 37 EFCOP ALU Control Register FACR 20 0 0 ccc eee eens 10 40 EFCOP Data Base Address FDBA 0 00 ccc eee e enn ene 10 41 EFCOP Coefficient Base Address FCBA 0 0 00 ccc eee eens 10 41 Decimation Channel Count Register FDCH 0 00 cece eens 10 42 EPC OP Interrupt Vectors fag ave a eh Geen ae ag ed eee E eel I bd 10 43 DSP56311 User s Manual Rev 2 Freescale Semiconductor A A l A 2 A 3 B 1 B 2 B 3 Contents Bootstrap Program Bootstrap COJE sat A area tate oh ea DEE Natale a be Rate BOA A 1 Internal I O Equates 0 cece ene n nnn n E A eas A 8 Interrupt Equates 24 cy 20h cc oot heh cole te cece eels fled d ea Mee Bae Bi Mel gl A 20 Programming Reference Internal VO Memory Map is lit cis olan diel eed ta BW ghee BA ENS bes B 2 Interrupt Sources and Priorities 2 0 cence nen n eee nee B 8 Programming SEE cuasi rr Banged woe eel B 12 DSP56311 User s Manual Rev 2 Freescale Semiconductor xi Contents DSP56311 User s Manual Rev 2 xii Freescale Semiconductor DSP56311 Overview 1 This manual descri
17. 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Fe a ee ae Pe E EE 50 E 0 0 E E Host Transmit Data Register HTX X FFFFC7 Write Only Reset empty Figure B 10 Host Transmit Data Register DSP56311 User s Manual Rev 2 B 21 Freescale Semiconductor Programming Reference Application Date Programmer Sheet 2 of 5 Be Base Address Register HBAR X FFFFC5 Read Write Reset 80 Host Request Open Drain Host GPIO Port Enable HROD HREN HEW 0 GPIO Pins Disable 1 GPIO Pin Enable 0 1 1 1 Host Address Line 8 Enable 0 1 0 5HA8 GPIO 1 5HA8 HA8 1 1 Host Address Line 9 Enable 0 Strobe Active Low 1 Strobe Active High 0 MAIT ORIO EHAR EHAS Host Address Strobe Polarity Host Chip Select Enable 0 Strobe Active Low 1 Strobe Active High 0 gt HCS HAIO GPIO 1 HCS HA10 HC8 if HMUX 0 Host Multiplexed Bus 1 gt HCS HA10 HC10 if HMUX 1 0 Nonmultiplexed 1 Multiplexed Host Dual Data Strobe Host Request Enable 0 Singles Stroke 1 Dual Stoke 0 gt HREQ HACK GPIO 1 gt HREQ HREQ if HDRQ 0 Host Chip Select Polarity 0 HCS Active Low Host Acknowledge Enable HTRQ amp HRRQ Enable 0 HACK GPIO 1 HCS Active High If HDRQ 8 HREN 1 HACK HACK Host Request Priority HRP 0 HREQ Active Low Host Enable 0 HI08 Disable HREQ Active High Pins GPIO 4 0 HTRQ HRR Q Active Low 1 HTRQ HRRO Active High 1 gt HI08
18. Contents 1 1 1 1 2 1 3 1 4 1 5 1 6 1 6 1 1 6 1 1 1 6 1 2 1 6 2 1 6 3 1 6 4 1 6 5 1 6 6 1 6 7 1 7 1 8 1 9 1 9 1 1 9 2 1 9 3 1 9 4 1 9 5 1 9 6 2 1 2 2 23 2 4 2 5 2 5 1 2 5 2 2 5 3 2 6 2 7 2 8 2 9 2 10 2 11 DSP56311 Overview Manual Organiza Odesa wears e paa a io wR EEE E ara Manual Conventions oso galera a E iat eben a a a A eae Manual Revision History for Revision 2 0 0 cece cee eee eee PES A ri DSP56300 Core Functional Blocks orasini rerni ai aa a a aa Data ALU ia A Bons ETA OLER ERTA E ETR R Data ALU Registers 0 0 ee ccc E A eee a a Ea Multiplier Accumulator MAC 0 0 0 cee tent e een eens Address Generation Unit AGU 0 i eria eee ene n eens Program Control Unit PCU renren eee n cence E ie PLL and Clock Oscillator oia ai oe mae tes A antes aed cate ius al A JTAG TAP and OnCE Module reete aaa ae aoa ea hee a Bae EA a ae Internal Memory sia ii aarin RR ns Cua clave cand asen External Memory Expansion 0 0 cece ccc cece een ene ae Internal BUSES A ae Sen A aw eA a Da ide Peripheral it A Oe PANE a Metis e la bude Bala lad hae bs GPIO Functionality iii beac bh ew E ebb OE eb ee een eed ee des FOS rica iaa POWeb aula ia ds dr ad dike owe geet External Memory Expansion Port Port A 0 0 cee ccc eee teenies External Address Bus tia o a Arteta aes External Data BUS 22 5 20 ia a a a a e es External B s Control A dt Ai Interrupt
19. Each peripheral has its own set of flags which can be polled to determine when data is ready to be transferred For example the ESSI control registers provide bits that tell the core when data is ready to be transferred to or from the peripheral The core polls these bits to determine when to interact with the peripheral Similar flags exist for each peripheral Example 5 1 shows software polling programmed in an application using the HI08 Example 5 1 Software Polling jclr 1 x M_HSR loop if HSR 1 HTDE 0 movey TBUFF_PTR x1 move data to x1 In this example the core waits until the Host Status Register HSR Host Transmit Data Empty HTDE flag is set When the flag is set the core moves data from Y memory to the X1 register 5 4 2 Interrupts Interrupts are more efficient than polling but interrupts also require additional register initialization Polling requires the core to remain busy checking a flag in a specified control register and therefore does not allow the core to execute other code at the same time For interrupts you can initialize the interrupt so it is triggered off one of the same flags that can also be polled Then the core does not have to continuously check a flag Once the interrupt is initialized and the flag is set the core is notified to execute a data transfer Until the flag is set the core can remain busy executing other sections of code When an interrupt occurs the core execution flo
20. Reflect the base address where the host side registers are mapped into the bus address space Freescale Semiconductor DSP56311 User s Manual Rev 2 6 15 Host Interface HI08 HAD 0 7 HAS HA 8 10 S l Chip select oO Base DSP Peripheral Address 8 Data Bus Register Figure 6 11 Self Chip Select Logic 6 6 6 Host Port Control Register HPCR The HPCR is a read write control register that controls the HIOS operating mode HPCR bit initialization values are discussed in Section 6 6 9 DSP Side Registers After Reset on page 6 20 Hardware and software reset clear the HPCR bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HAP HRP HCSP HDDS HMUX HASP HDSP HROD HEN HAEN HREN HCSEN HA9EN HAB8EN HGEN Reserved bit read as 0 write to O for future compatibility Figure 6 12 Host Port Control Register HPCR X FFFFC4 To assure proper operation of the DSP56311 the HPCR bits HAP HRP HCSP HDDS HMUX HASP HDSP HROD HAEN and HREN should be changed only if HEN is cleared Similarly the HPCR bits HAP HRP HCSP HDDS HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN and HA8EN should not be set when HEN is set nor at the time HEN is set Table 6 12 Host Port Control Register HPCR Bit Definitions Bit Number Bit Name Reset Value Description 15 HAP 0 Host Acknowledge Polarity If HAP is cleared the host acknowledge
21. SSI Transmit Slot Mask Register B M_SSTSB EQU SFFFF SSI Transmit Slot Bits Mask B TS16 TS31 SSI Receive Slot Mask Register A M_SSRSA EQU SFFFF SSI Receive Slot Bits Mask A RSO RS15 SSI Receive Slot Mask Register B M_SSRSB EQU SFFFF SSI Receive Slot Bits Mask B RS16 RS31 Register Addresses M_IPRC EQU SFFFFFF z M_IPRP EQU SFFFFFE A nterrupt Priority Register Core nterrupt Priority Register Peripheral Interrupt Priority Register Core IPRC M_IAL EQU 7 IROA Mode Mask M_IALO EQU 0 IRQA Mode Interrupt Priority Level low M_TAL1 EQU 1 IRQA Mode Interrupt Priority Level high M_TAL2 EQU 2 IRQA Mode Trigger Mode M_IBL EQU 38 IROB Mode Mask M_IBLO EQU 3 IRQB Mode Interrupt Priority Level low M_IBL1 EQU 4 IROB Mode Interrupt Priority Level high M_IBL2 EQU 5 IROB Mode Trigger Mode M_ICL EQU 1C0 IROC Mode Mask M_ICLO EQU 6 IROC Mode Interrupt Priority Level low M_ICL1 EQU 7 IROC Mode Interrupt Priority Level high M_ICL2 EQU 8 IRQC Mode Trigger Mode M_IDL EQU SEO0O IROD Mode Mask M_IDLO EQU 9 IRQD Mode Interrupt Priority Level low M_IDL1 EQU 10 IROD Mode Interrupt Priority Level high M_IDL2 EQU ET IROD Mode Trigger Mode M_DOL EQU 3000 DMAO Interrupt priority Level Mask M_DOLO EQU 12 DMAO Interrupt Pri
22. 000000 Internal X data oo0000 RAM 40K __ so00000 RAM 40K Internal Y data Reserved Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 11 1 0 47K 40K 40K Enabled 16M 0400 BFFF 0000 9FFF 0000 9FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller 3 18 Figure 3 10 Memory Switch On MSW 11 Cache On 24 Bit Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor Memory Maps Program X Data Y Data SEREF FETE External 1 O Internal I O FFCO FF80 FF80 Internal I O FFFF External External External C000 C000 8000 Internal Program RAM 32K Internal X data RAM 48K Internal Y data RAM 48K 0000 0000 0000 Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 0 any 0 1 32K 48K 48K None 64K value 0000 3FFF 0000 BFFF 0000 BFFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 11 Memory Switch Off Cache Off 16 Bit Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor 3
23. Date Programmer Sheet 2 of 3 Clock Polarity clk edge data amp Frame Sync clocked out in 0 out on rising in on falling 1 in on rising out on falling Frame Sync Polarity 0 high level positive 1 low level negative Frame Sync Relative Timing WL Frame Sync only 0 with first data bit 1 1 clock cycle earlier than first data bit Frame Sync Length TX RX Word Word Bit Word Bit Bit Bit Shift Direction 0 MSB First 1 LSB First Clock Source Direction O External Clock 1 Internal Clock Serial Control Direction Bits see Table 8 2 Pin SCDx 0 Input SCDx 1 Output Sco Rx Clk Flag 0 SC1 Rx Frame Sync Flag 1 SC2 Tx Frame Sync Tx Rx Frame Sync Output Flag x If SYN 1 and SCD1 1 OFx SCx Pin 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 AE AAA Peale A ar i ESSI Control Register B CRBx Reset 000000 ESSIO X FFFFB6 Read Write ESSI1 X FFFFA6 Read Write Figure B 16 ESSI Control Register B CRB DSP56311 User s Manual Rev 2 Freescale Semiconductor B 27 Programming Reference B 28 Application Date Programmer SSI Transmit Slot Mask 0 IgnoreTime Slot 1 Active Time Slot ESSI Transmit Slot Mask A TSMA 0 1 ESSIO X FFFFB4 Read Write Reset FFFF ESSI1 X FFFFA4 Read Write SSI Transmit Slot Mask 0 IgnoreTime Slot 1 ActiveTime Slot ESSI Transmit Slot Mask B TSMB 0
24. E Multichannel Mode E Decimation 10 3 3 2 1 Coefficient Update Option The Coefficient Update option is only available in Real operating mode If the user sets the FUPD bit the EFCOP updates the coefficients and clears the FUPD bit When used with adaptive mode this only sets the initial update since the mode sets the FUPD bit dynamically during normal operation to update the coefficients 10 3 3 2 2 Adaptive Mode Option Adaptive mode is only available in Real operating mode It provides a way to update the coefficients based on filter input x n using the following equation h 0 h i K n x n i where h i is the ith coefficient at time n The coefficients are updated when FSCR FUPD is set The EFCOP checks to see if a value has been written to the FKIR If no value is written the EFCOP halts processing until a value is written to the FKIR When a value is written to the FKIR the EFCOP updates all the coefficients based on the above equation using the value in the DSP56311 Reference Manual Rev 2 10 10 Freescale Semiconductor EFCOP Operation FKIR for K n The EFCOP automatically clears FSCR FUPD when the coefficient update is complete If the coefficients are to be updated after every input sample Adaptive mode is enabled by setting the FCSR FADP In Adaptive mode the EFCOP automatically sets the FUDP bit after each input sample is processed This allows for continuous processing using interrupts that incl
25. HCSEN 1 Host chip select input enabled HA9EN 0 address 9 enable bit has no meaning in non multiplexed bus HA8EN 0 address 8 enable bit has no meaning non multiplexed bus HGEN 0 Host GPIO pins are disabled bra lt HIO8CONT HC11HOSTLD movep 0000001000011000 x M_HPCR Configure the following conditions DSP56311 User s Manual Rev 2 Freescale Semiconductor A 5 Bootstrap Program I8051HOSTLD bra movep HIO8CONT A 6 bset jclr movep jclr movep move do lt HIO8CONT HRP HCSP HD HS HMUX HASP HDSP spare HAEN HREN HCSEN HA9EN HA8EN HGEN DT O O O GOG OF 30001110000011110 x M_HPCR HEN x M_HPCR HRDF xX M_HSR x M_HRX a0 RFHRDF x M_HSR x M_HRX r0 0 al a0 HIO8LOOP Non mea HOS Negative host acknowledge Negative host request Negatice chip select input Single strobe bus R W and DS multiplexed bus address strobe polarity has no ning in non multiplexed bus Negative data strobes polarity t request is active when enabled This bit should be set to 0 for future compatability whe HEN Hos Hos Hos m ea mea Hos the Mul HOS n the HPCR register is modified should be cleared t acknowledge is disabled t requests are enabled t chip select input enabled address 9 enable bit has no ning in non multiplexed bus address 8 enable bit
26. Synchronous operation is not supported above 100 MHz when using TA the OMR TAS bit must be set to synchronize the TA signal with the internal clock 10 BE 0 Cache Burst Mode Enable Enables disables Burst mode in the memory expansion port during an instruction cache miss If the bit is cleared Burst mode is disabled and only one program word is fetched from the external memory when an instruction cache miss condition is detected If the bit is set Burst mode is enabled and up to four program words are fetched from the external memory when an instruction cache miss is detected DSP56311 User s Manual Rev 2 Freescale Semiconductor Central Processor Unit CPU Registers Table 4 3 Operating Mode Register OMR Bit Definitions Continued Bit Number Bit Name Reset Value Description 9 8 CDP 1 0 11 Core DMA Priority Specify the priority of core and DMA accesses to the external bus 00 Determined by comparing status register CP 1 0 to the active DMA channel priority 01 DMA accesses have higher priority than core accesses 10 DMA accesses have the same priority as the core accesses 11 DMA accesses have lower priority than the core accesses MS Memory Switch Mode Allows some internal data memory X Y or both to become part of the chip internal Program RAM Notes 1 To ensure proper operation place six NOP instructions after the instruction that chang
27. TRNE Transmitter Empty This flag bit is set when both the transmit shift register and transmit data register STX are empty indicating that there is no data in the transmitter When TRNE is set data written to one of the three STX locations or to the transmit data address register STXA is transferred to the transmit shift register and is the first data transmitted TRNE is cleared when a write into STX or STXA clears TDRE or when an idle preamble or break is transmitted When set TRNE indicates that the transmitter is empty therefore the data written to STX or STXA is transmitted next That is there is no word in the transmit shift register being transmitted This procedure is useful when initiating the transfer of a message that is a string of characters 8 16 DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 6 3 SCI Clock Control Register SCCR SCI Programming Model The SCCR is a read write register that controls the selection of clock modes and baud rates for the transmit and receive sections of the SCI interface The SCCR is cleared by a hardware RESET signal 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TCM RCM SCP COD CD11 CD10 CD9 CD8 6 5 4 3 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CDO Reserved Read as 0 Write to 0 for future compatibility Figure 8 4
28. select source of clock signal 7 21 Serial Clock SCK ESSI 7 3 Serial Control 0 SC00 and SC10 7 3 Serial Control 1 SC01 and SC11 7 4 Serial Control 2 SC02 and SC12 7 5 Serial Input Flag IFO 7 4 Serial Output Flag 0 OFO bit 7 4 Serial Output Flags OFO OF1 7 17 Serial Receive Data SRD 7 3 Serial Transmit Data STD 7 2 SPI protocol 7 2 Synchronous mode 7 3 7 4 7 10 7 12 Synchronous Serial Interface Status Register SSISR 7 12 7 26 bit definitions 7 27 Receive Data Register Full RDF 7 27 Receiver Frame Sync Flag RFS 7 27 Receiver Overrun Error Flag ROE 7 27 Serial Input Flag 0 IFO 7 28 Serial Input Flag 1 IF1 7 28 Transmit Data Register Empty TDE 7 27 Transmit Frame Sync Flag TFS 7 27 Transmitter Underrun Error Flag TUE 7 27 Synchronous Asynchronous SYN bit 7 10 Time Slot Register TSR 7 8 7 31 Transmit Data Registers TXO TX2 7 12 7 31 Transmit Enable TE 7 17 Transmit Shift Registers 7 28 Transmit Slot Mask Register TSM programming sheet B 28 Transmit Slot Mask Registers TSMA and TSMB 7 12 7 31 TX clock 7 10 variable prescaler 7 15 word length frame sync 7 11 word length frame sync timing 7 11 EOM byte 4 10 equalization 10 1 Index ESSI 2 2 ESSIO Interrupt Priority Level SOL bits 4 15 ESSI1 Interrupt Priority Level S1L bits 4 15 expansion memory 3 1 Extended Mode Register EMR 4 5 Arithmetic Saturation Mode SM 4 6 Cache Enable CE 4 6 Core Priorit
29. 1 Stop 11 bit Asynchronous 1 Start 8 Data 1 Even Parity 1 Stop WDS2 WDS1 WDSO TX SSFTD 0 Data Type 1 Address Byte 0 Data Byte e Modes 1 3 and 7 are reserved DO LSB D7 MSB e Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 Figure 8 2 SCI Data Word Formats SSFTD 0 2 8 6 1 SCI Control Register SCR The SCR is a read write register that controls the serial interface operation DSP56311 User s Manual Rev 2 8 10 Freescale Semiconductor SCI Programming Model 23 22 21 20 19 18 17 16 REIE 15 14 13 12 11 10 9 8 SCKP STIR TMIE TIE RIE ILIE TE RE 7 6 5 4 3 2 1 0 WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDSO Reserved bit read as 0 write to O for future compatibility Figure 8 3 SCI Control Register SCR Table 8 2 SCI Control Register SCR Bit Definitions Bit Bit Reset Number Name Value Deseription 23 17 0 Reserved Write to 0 for future compatibility 16 REIE 0 Receive with Exception Interrupt Enable Enables disables the SCI receive data with exception interrupt If REIE is cleared the receive data with exception interrupt is disabled If both REIE and RDRF are set and PE FE and OR are not all cleared the SCI requests an SCI receive data with exception interrupt from the interrupt controller Either a hardware RESET signal or a software RESET instruction clears REIE
30. 11 7 0 Reserved and unused They read as 0 write with O for future compatibility 6 FISL 0 Filter Input Scale When set this read write control bit directs the EFCOP ALU to scale the IIR feedback terms but not the IIR input When cleared the EFCOP ALU scales both the IIR feedback terms and the IIR input The scaling value in both cases is determined by the FSCL 1 0 bits 5 FSA 0 Filter Sixteen bit Arithmetic FSA Mode When set this read write control bit enables FSA mode In this mode the rounding of the arithmetic operation is performed on Bit 31 of the 56 accumulator instead of the usual bit 23 of the 56 bit accumulator The scaling of the EFCOP data ALU is affected accordingly 4 FSM 0 Filter Saturation Mode When set this read write control bit selects automatic saturation on 48 bits for the results going to the accumulator A special circuit inside the EFCOP MAC unit then saturates those results The purpose of this bit is to provide arithmetic saturation mode for algorithms that do not recognize or cannot take advantage of the extension accumulator 3 2 FRM 1 0 0 Filter Rounding Mode These read write control bits select the type of rounding performed by the EFCOP data ALU during arithmetic operation e FRM 00 Convergent rounding e FRM 01 Two s complement rounding e FRM 10 Truncation no rounding FRM 11 Reserved for future expansion These bits affect operation of the EFCOP data ALU 10 40
31. 15 SCKP 0 SCI Clock Polarity Controls the clock polarity sourced or received on the clock signal SCLK eliminating the need for an external inverter When SCKP is cleared the clock polarity is positive when SCKP is set the clock polarity is negative In Synchronous mode positive polarity means that the clock is normally positive and transitions negative during valid data Negative polarity means that the clock is normally negative and transitions positive during valid data In Asynchronous mode positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid Negative polarity means that the falling edge of the clock occurs during the center of the period that data is valid Either a hardware RESET signal or a software RESET instruction clears SCKP 14 STIR 0 Timer Interrupt Rate Controls a divide by 32 in the SCI Timer interrupt generator When STIR is cleared the divide by 32 is inserted in the chain When STIR is set the divide by 32 is bypassed thereby increasing timer resolution by a factor of 32 Either a hardware RESET signal or a software RESET instruction clears this bit To ensure proper operation of the timer STIR must not be changed during timer operation that is if TMIE 1 13 TMIE 0 Timer Interrupt Enable Enables disables the SCI timer interrupt If TMIE is set timer interrupt requests are sent to the interrupt controller at the rate set by the SCI clock regi
32. 24 bit fractional data 7 14 after reset 7 6 Asynchronous mode 7 3 7 4 7 10 7 19 audio enhancements 7 2 byte format 7 11 clock generator 7 10 7 16 Clock Sources 7 3 codec 7 11 control and time slot registers 7 6 control direction of SC2 I O signal 7 21 Control Register A CRA Alignment Control ALC 7 14 Frame Rate Divider Control DC 7 15 Prescale Modulus Select PM 7 15 Prescaler Range PSR 7 15 programming sheet B 26 Select SCK SSC1 7 13 Word Length Control WL 7 14 Control Register B CRB Clock Polarity CKP 7 20 Clock Source Directions SCKD 7 21 Frame Sync Length FSL 7 21 Frame Sync Polarity FSP 7 20 Frame Sync Relative Timing FSR 7 21 Mode Select MOD 7 20 programming sheet B 27 Receive Enable RE 7 19 Receive Exception Interrupt Enable REIE 7 18 Receive Interrupt Enable RIE 7 18 Receive Last Slot Interrupt Enable 7 18 Serial Control Direction 0 SCDO 7 22 Serial Control Direction 1 SCD1 7 22 Serial Control Direction 2 SCD2 7 21 Serial Output Flag 0 OFO 7 22 Serial Output Flag 1 OF1 7 22 Shift Direction SHFD 7 21 Synchronous Asynchronous SYN 7 20 Transmit 0 Enable TEO 7 19 Transmit 1 Enable TE1 7 19 Transmit 2 Enable TE2 7 20 Transmit Exception Interrupt Enable TEIE 7 18 Transmit Interrupt Enable TIE 7 18 Transmit Last Slot Interrupt Enable TLIE 7 18 control registers 7 12 data and control signals 7 2 DMA 7 6 exception configuration 7 8 exceptions 7 7 r
33. 4009 eos 1 GOW epoW A40MION ouAS Wed led a9uo pa 19 sue S eyep pue nooo sidn119 u 31ON y s6e 4 pue 1sanbay Yad JO 1dn118 u 1anladay y Y pue isanbay YW JO dn113 U SL L Y ONAS ewe SLIYM dV4 GYD g 19181694 101 U09 ISS yOOID elas 0 GOW apo jewson Figure 7 8 CRB MOD Bit Operation DSP56311 User s Manual Rev 2 7 25 Freescale Semiconductor Enhanced Synchronous Serial Interface ESSI Frame SYNC E AS FSLO 0 FSL1 0 Frame SYNC FSLO 0 FSL1 1 Slot 0 Wait Slot 0 Figure 7 9 Normal Mode External Frame Sync 8 Bit 1 Word in Frame Frame SYNC E TEN FSLO 0 FSL1 0 Frame SYNC A A A FSLO 0 FSL1 1 Daia OK SLOT 0 A SLOT 1 o SLOT 0 pa SLOT 1 Figure 7 10 Network Mode External Frame Sync 8 Bit 2 Words in Frame 7 5 3 ESSI Status Register SSISR The SSISR is a read only status register by which the DSP reads the ESSI status and serial input flags 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RDF TDE ROE TUE RFS TFS IF1 IFO Reserved bit read as 0 write to 0 0 for future compatibility ESSIO X FFFFB7 ESSI1 X FFFFA7 Figure 7 11 ESSI Status Register SSISR DSP56311 User s Manual Rev 2 7 26 Freescale Semiconductor ESSI Programming Model Table 7 5 ESSI Status Register SSISR Bit Definitions Bit Number
34. 48 0 2 ESSI1 Transmit Data With Exception Status VBA 4A 0 2 ESSI1 Transmit Last Slot VBA 4C 0 2 Reserved VBA 4E 0 2 Reserved VBA 50 0 2 SCI Receive Data VBA 52 0 2 SCI Receive Data With Exception Status VBA 54 0 2 SCI Transmit Data VBA 56 0 2 SCI Idle Line VBA 58 0 2 SCI Timer VBA 5A 0 2 Reserved VBA 5C 0 2 Reserved VBA 5E 0 2 Reserved VBA 60 0 2 Host Receive Data Full VBA 62 0 2 Host Transmit Data Empty VBA 64 0 2 Host Command Default VBA 66 0 2 Reserved VBA 68 0 2 EFCOP Data Input Buffer Empty VBA 6A 0 2 EFCOP Data Output Buffer Full VBA 6C 0 2 Reserved VBA 6E 0 2 Reserved VBA FE 0 2 Reserved Freescale Semiconductor DSP56311 User s Manual Rev 2 B 9 Programming Reference Table B 5 Interrupt Source Priorities Within an IPL Priority Interrupt Source Level 3 Nonmaskable Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Non Maskable Interrupt Levels 0 1 2 Maskable Highest TRQA External Interrupt IRQB External Interrupt IRQC External Interrupt IRQD External Interrupt DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt Host Command Interrupt Host Transmit Data Empty Host Receive Data Full ESSIO RX Data with Excepti
35. DSP56311 Reference Manual Rev 2 Freescale Semiconductor EFCOP Programming Model Table 10 8 EFCOP ALU Control Register FACR Bits Continued Bit Reset E Number Bit Name Value Description 1 0 FSCL 1 0 0 Filter Scaling FSCL These read write control bits select the scaling factor of the FMAC result e FSCL 00 Scaling factor 1 no shift e FSCL 01 Scaling factor 8 3 bit arithmetic left shift e FSCL 10 Scaling factor 16 4 bit arithmetic left shift e FSCL 11 Reserved for future expansion To ensure proper operation never change the FSCL bits unless the EFCOP is in the individual reset state that is FEN 0 10 4 7 EFCOP Data Base Address FDBA The FDBA is a 16 bit read write counter register used as an address pointer to the EFCOP FDM bank FDBA points to the location to write the next data sample The FDBA points to a modulo delay buffer of size M defined by the filter length M FCNT 11 0 1 The address range of this modulo delay buffer is defined by lower and upper address boundaries The lower address boundary is the FDBA value with 0 in the k LSBs where 2 gt M 2 2 it therefore must be a multiple of 2K The upper boundary is equal to the lower boundary plus M 1 Since M 2 once M has been chosen that is FCNT has been assigned a sequential series of data memory blocks each of length 2k will be created where multiple circular buffers for multicha
36. E Data arithmetic logic unit Data ALU Fully pipelined 24 x 24 bit parallel multiplier accumulator MAC 56 bit parallel barrel shifter fast shift and normalization bit stream generation and parsing Conditional ALU instructions 24 bit or 16 bit arithmetic support under software control E Program control unit PCU Position Independent Code PIC support Addressing modes optimized for DSP applications including immediate offsets Instruction cache controller Internal memory expandable hardware stack Nested hardware DO loops Fast auto return interrupts DSP56311 User s Manual Rev 2 Freescale Semiconductor 1 5 DSP56311 Overview E Direct memory access DMA Six DMA channels supporting internal and external accesses One two and three dimensional transfers including circular buffering End of block transfer interrupts Triggering from interrupt lines and all peripherals E Phase lock loop PLL Allows change of low power Divide Factor DF without loss of lock Output clock with skew elimination E Hardware debugging support On chip emulation OnCE module Joint Test Action Group JTAG Test Access Port TAP Address Trace mode reflects internal program RAM accesses at the external port E Reduced power dissipation Very low power CMOS design Wait and stop low power standby modes Fully static design specified to operate down to 0 H
37. FF0000 00C000 Internal Reserved 004000 Internal Y data o00000 RAM 16K External a Internal Reserved Internal X data RAM 16K Bit Settings Memory Configuration ms MSW ce sc ProgramRAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 00 0 0 96K 16K 16K None 16M 0000 0000 3FFF 0000 3FFF 17FFF e Lowest 10K of X data RAM and 410K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 3 Memory Switch On MSW 00 Cache Off 24 Bit Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor 3 11 Memory Configuration Program FFFFFF FFFFFF FFFF80 FFFOOO Internal Reserved FFOOCO FF0000 Bootstrap ROM FF0000 External 018000 Internal 00C000 Program RAM 95K 004000 000400 000000 000000 X Data Internal I O Internal Reserved External Internal Reserved Internal X data RAM 16K FFFFFF FFFFCO FFFF80 FFFOOO FF0000 004000 000000 Y Data External I O Internal I O External Internal Reserved External 00C000 Internal Reserved Internal Y data RAM 16K Bit Settings Memory Configuration MSW 7 6 Addressable MS 1 0 CE SC Program RAM X Data RAM Y Data RAM Cache Memory Size 1 00 1 0 95K 16K 16K Enabled 16M
38. Filter Channels FCHL 10 42 Filter Decimation FDCM 10 42 Direct Memory Access DMA 6 5 6 8 DSP56311 User s Manual Rev 2 Index 2 Freescale Semiconductor EFCOP 10 2 EFCOP restrictions 10 5 Request Source bits 4 27 transfers and host bus 6 8 triggered by timer 9 21 Direction DIR bit 9 25 Division Factor DF bits 4 20 DMA Address Mode DAM bit 4 32 DMA Channel Enable DE bit 4 27 DMA Channel Priority DPR bit 4 29 DMA Continuous Mode Enable DCON bit 4 30 DMA Control Registers DCR53 DCRO programming sheet B 20 DMA Control Registers DCRs 4 27 bit definitions 4 27 DMA Address Mode DAM 4 32 DMA Channel Enable DE 4 27 DMA Channel Priority DPR 4 29 DMA Continuous Mode Enable DCON 4 30 DMA Destination Space DDS 4 32 DMA Interrupt Enable DIE 4 28 DMA Request Source DRS 4 31 DMA Source Space DSS 4 32 DMA Three Dimensional Mode D3D 4 31 DMA Transfer Mode DTM 4 28 DMA Destination Space DDS bit 4 32 DMA Interrupt Enable DIE bit 4 28 DMA Request Source DRS bit 4 31 DMA Source Space DSS bit 4 32 DMA Three Dimensional Mode D3D bit 4 31 DMA Transfer Mode DTM bit 4 28 DO FOREVER FV Flag bit 4 7 DO loop 1 8 Do Loop Flag LF bit 4 7 Double Data Strobe 2 2 Double Host Request HDRQ bit 6 8 6 23 Double Precision Multiply Mode DM bit 4 7 DRAM Control Register DCR 4 20 4 22 Bit Definitions 4 23 Bus Column In Page Wait State BCW 4 24 Bus DRAM Page Size BPS 4 24 Bus Mastership Ena
39. HACK signal is configured as an active low input The HIO8 drives the contents of the IVR onto the host bus when the HACK signal is low If the HAP bit is set the HACK signal is configured as an active high input The HIO8 outputs the contents of the IVR when the HACK signal is high 14 HRP 0 Host Request Polarity Controls the polarity of the host request signals In single host request mode that is when HDRQ is cleared in the ICR if HRP is cleared and host requests are enabled that is if HREN is set and HEN is set then the HREQ signal is an active low output If HRP is set and host requests are enabled the HREQ signal is an active high output In the double host request mode that is when HDRQ is set in the ICR if HRP is cleared and host requests are enabled that is if HREN is set and HEN is set then the HTRQ and HRRQ signals are active low outputs If HRP is set and host requests are enabled the HTRQ and HRRQ signals are active high outputs DSP56311 User s Manual Rev 2 6 16 Freescale Semiconductor DSP Core Programming Model Table 6 12 Host Port Control Register HPCR Bit Definitions Continued Bit Number Bit Name Reset Value Description 13 HCSP 0 Host Chip Select Polarity If the HCSP bit is cleared the host chip select HCS signal is configured as an active low input and the HI08 is selected when the HCS signal is low If the HCSP signal is set HCS is confi
40. Host Transmit Interrupt Enable M_HCIE EQU 2 Host Command Interrupt Enable M_HF2 EQU 3 Host Flag 2 M_HF3 EQU 4 Host Flag 3 E HSR bits definition M_HRDF EQU S0 Host Receive Data Full M_HTDE EQU s1 Host Receive Data Empty M_HCP EQU 2 Host Command Pending DSP56311 User s Manual Rev 2 Freescale Semiconductor A 9 Bootstrap Program M_HFO EQU 3 Host Flag 0 M_HF1 EQU 4 Host Flag 1 HPCR bits definition Zo _HGEN EQU SO Host Port GPIO Enable M_HA8EN EQU 1 Host Address 8 Enable M_HA9EN EQU 2 Host Address 9 Enable M_HCSEN EQU 3 Host Chip Select Enable M_HREN EQU 4 Host Request Enable M_HAEN EQU S5 Host Acknowledge Enable M_HEN EQU 6 Host Enable M_HOD EQU 8 Host Request Open Drain mode M_HDSP EQU 9 Host Data Strobe Polarity M_HASP EQU SA Host Address Strobe Polarity M_HMUX EQU SB Host Multiplexed bus select M_HD_HS EQU sc Host Double Single Strobe select M_HCSP EQU SD Host Chip Select Polarity M_HRP EQU SE Host Request Polarity M_HAP EQU SF Host Acknowledge Polarity EQUATES for Serial Communications Interface SCI Register Addresses M_STXH EQU SFFFF97 SCI Transmit Data Register high M_STXM EQU SFFFF96 SCI Transmit Data Register middle M_STXL EQU
41. MOVEP instruction to the flag to be cleared and 0 to the other flag 20 TOF 0 Timer Overflow Flag Indicates that a counter overflow has occurred This bit is cleared by writing a one to the TOF bit Writing a zero to TOF has no effect The bit is also cleared when the timer overflow interrupt is serviced The TOF bit is cleared by a hardware RESET signal a software RESET instruction the STOP instruction or by clearing the TCSR TE bit to disable the timer 19 16 0 Reserved Write to zero for future compatibility 15 PCE 0 Prescaler Clock Enable Selects the prescaler clock as the timer source clock When PCE is cleared the timer uses either an internal CLK 2 signal or an external TIO signal as its source clock When PCE is set the prescaler output is the timer source clock for the counter regardless of the timer operating mode To ensure proper operation the PCE bit is changed only when the timer is disabled The PS 1 0 bits of the TPLR determine which source clock is used for the prescaler A timer can be clocked by a prescaler clock that is derived from the TIO of another timer 14 0 Reserved Write to zero for future compatibility DSP56311 User s Manual Rev 2 9 24 Freescale Semiconductor Triple Timer Module Programming Model Table 9 3 Timer Control Status Register TCSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 13 DO 0 Data Ou
42. Memory Space FFFF80 FFFOOO Internal Reserved FF0000 External 000800 Internal X Data RAM 2 K default 000000 Figure 5 1 Memory Mapping of Peripherals Control Registers 5 3 Reading Status Registers Each peripheral has a read only status register that indicate the state of the peripheral at a given time The HIO8 ESSI and SCI have dedicated status registers The triple timer has status bits embedded within a control status register Changes in the status bits can generate interrupt conditions For example the HIO8 has a host status register with two host flag bits that can be encoded by the host to generate an interrupt in the DSP 5 4 Data Transfer Methods Peripheral I O on the DSP56311 can be accomplished in three ways E Polling E Interrupts E DMA DSP56311 User s Manual Rev 2 5 2 Freescale Semiconductor Data Transfer Methods 5 4 1 Polling Polling is the easiest method for data transfers When polling is chosen the DSP56311 core continuously checks a specified register flag waiting for an event to happen One example would be setting an overflow flag in one of the Timers Once the event occurs the DSP56311 is free to continue with its next task However while it is waiting for the event to occur the DSP56311 core is not executing any other code Polling is the easiest transfer method since it does not require register initialization but it is also the least efficient use of the DSP core
43. Register 0 cette eee nee 4 33 JTAG Boundary Scan Register BSR 0 0 eet eee e eens 4 33 Programming the Peripherals Peripheral Initialization Steps 2 2 eee een e teen teen ees 5 1 Mapping the Control Registers 2 0 eee eee nent n eee ene 5 1 Reading Status Registers cs cee ec pesii ii ne cee ee ene bee ened ee eee reese 5 2 Data Transfer Methods sourno Torere pe keene he pag ge esa nee ae Pang Sar ages eae 5 2 PONS cata o tao ea Is ee IS Gente 5 3 AMES it a Peasy i 5 3 DSP56311 User s Manual Rev 2 Freescale Semiconductor 5 4 3 5 4 4 5 5 5 5 1 5 5 2 5 5 3 5 5 4 5 5 5 6 1 6 1 1 6 1 2 6 2 6 3 6 4 6 4 1 6 4 2 6 4 3 6 4 4 6 4 5 6 5 6 6 6 6 1 6 6 2 6 6 3 6 6 4 6 6 5 6 6 6 6 6 7 6 6 8 6 6 9 6 7 6 7 1 6 7 2 6 7 3 6 7 4 6 7 5 6 7 6 6 7 7 6 8 7 1 1 2 7 2 1 7 2 2 7 2 3 7 2 4 Contents DMA vitecscfte toh g risa pt atte Me tard oe RW gua oe a iS ye 5 4 Advantages and Disadvantages 0 0 cece een ene nee e ees 5 5 General Purpose Input Output GPIO 0 cee eee nee 5 6 Port B Signals and Registers 0 eee cette ene ene e eens 5 6 Port C Signals and Registers 2 ec cee ene ay aa i 5 7 Port D Signals and Registers 1 0 eee cee ence nee eens 5 7 Port E Signals and Registers 2 0 0 cece cece eee e nee eens 5 7 Triple Timer Signals and Registers 0 0 een eee nee ees 5 8 Host Interface HI08 Features o er tds cotta O kid 6
44. SDFFFFF active low Pee Pee be bee ee DSP T OUREGTIS TERS pore ee Fe Peay FREE Ne Pee Tee DSP56311 User s Manual Rev 2 Freescale Semiconductor A 3 Bootstrap Program M_SSR EQU SFFFF93 SCI Status Register M_STXL EQU SFFFF95 SCI Transmit Data Register low M_SRXL EQU SFFFF98 SCI Receive Data Register low M_SCCR EQU SFFFF9B SCI Clock Control Register M_SCR EQU SFFFF9C SCI Control Register M_PCRE EQU SFFFFOF Port E Control register M_AAR1 EQU SFFFFF8 Address Attribute Register 1 M_HPCR EQU SFFFFC4 Host Polarity Control Register M_HSR EQU SFFFFC3 Host Status Register M_HRX EQU SFFFFC6 Host Receive Register HRDF EQU SO Host Receive Data Full HFO EQU 3 Host Flag 0 HEN EQU 6 Host Enable ORG PL Sf 0000 PL S 0000 bootstrap code starts at Sff0000 START clr a 0 r5 clear a and init R5 with 0 jclr 3 omr OMROXXX If MD MC MB MA 0xxx go to OMROXXX jclr 2 omr EPRSCILD If MD MC MB MA 10xx go load from EPROM SCI jclr 1 omr OMR1IS0 IF MD MC MB MA 110x go to look for ISA HC11 jclr 0 omr I8051HOSTLD If MD MC MB MA 1110 go load from 8051 Host If MD MC MB MA 1111 go load from MC68302 Host This routine loads a program through the 1 3 bytes Define the program length 2 3 bytes Define the address to which 3 3n bytes while n is any integer numbe at the
45. TCPR TCF Compare Interrupt if TCIE 1 Figure 9 3 Timer Mode TRM 1 Mode 0 internal clock no timer output TRM 0 N write preload first event last event M write compare TE Clock CLK 2 or prescale CLK TLR AU A y E O AD UD E een ios TCF Compare Interrupt if TCIE 1 TOF Overflow Interrupt if TCIE 1 Figure 9 4 Timer Mode TRM 0 DSP56311 User s Manual Rev 2 9 6 Freescale Semiconductor Operating Modes 9 3 1 2 Timer Pulse Mode 1 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 0 0 1 1 Timer Pulse Timer Output Internal In Mode 1 the timer generates an external pulse on its TIO signal when the timer count reaches a pre set value The TIO signal is loaded with the value of the TCSR INV bit When the counter matches the TCPR value TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set The polarity of the TIO signal is inverted for one timer clock period If TCSR TRM is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If TCSR TRM is cleared the counter continues to increment on each timer clock This process repeats until TCSR TE is cleared disabling the timer The TLR value in the TCPR sets the delay between starting the timer and generating the output pulse To generate successive output pulses with a delay of X clock cycl
46. The 24K higher locations 6000 BFFF of the internal Y memory are switched to internal program memory and therefore the highest internal Y memory location is 5FFF The Y memory space at the switched locations 6000 BFFF becomes reserved and should not be accessed The lowest external Y memory location is C000 MSW 1 0 10 The 8K higher locations 8000 BFFF of the internal Y memory are switched to internal program memory and therefore the highest internal Y memory location is 7FFF The Y memory space at the switched locations 8000 BFFF becomes reserved and should not be accessed The lowest external Y memory location is CO00 MSW 1 0 11 The 4K higher locations A000 BFFF of the internal Y memory are switched to internal program memory and therefore the highest internal Y memory location is 9FFF The Y memory space at the switched locations A000 BFFF becomes reserved and should not be accessed The lowest external Y memory location is C000 The 10K lowest locations 0 27FF of the internal Y memory are shared memory which is accessible both to the core and the EFCOP The EFCOP connects to the shared memory in place of the DMA bus Therefore DMA cannot access the shared memory and simultaneous accesses by the core and EFCOP to the same memory bank of 256 locations of the shared memory are not permitted It is your responsibility to prevent such simultaneous accesses DSP56311 User
47. a Figure 10 3 EFCOP Memory Organization 10 2 3 Filter Multiplier and Accumulator FMAC The FMAC machine can perform a 24 bit x 24 bit multiplication with accumulation in a 56 bit accumulator The FMAC operates a pipeline the multiplication is performed in one clock cycle and the accumulation occurs in the following clock cycle Throughput is one MAC result per clock cycle The two MAC operands are read from the FDM and from the FCM The full 56 bit width of the accumulator is used for intermediate results during the filter calculations For operations with saturation mode disabled the final result is rounded according to the selected rounding mode and limited to the most positive number 7FFFFF if overflow occurred or most negative number 800000 if underflow occurred after processing of all filter taps is completed In saturation mode the result is limited to the most positive number 7FFFFF if overflow occurred or the most negative number 800000 if underflow occurred after each MAC operation The 24 bit result from the FMAC is stored in the EFCOP output buffer FDOR Operating in sixteen bit arithmetic mode the FMAC performs a 16 bit x 16 bit multiplication with accumulation into a 40 bit accumulator As with 24 bit operations if saturation mode is disabled the result is rounded according to the selected rounding mode and limited to the most positive number 7FFF if overflow occurred or the most
48. compatibility 11 8 FDCM 3 0 Filter Decimation These read write control bits select the decimation function There are 16 decimation factor options from 1 to 16 To ensure proper operation never change the FDCM bits unless the EFCOP is in the individual reset state FEN 0 7 6 Reserved and unused They read as 0 write with O for future compatibility 5 0 FCHL 5 0 Filter Channels These read write control bits determine the number of filter channels to process simultaneously from 1 to 64 in multichannel mode The number represented by the FCHL bits is one less than the number of channels to be processed that is if FCHL O then 1 channel is processed if FCHL 1 then 2 channels are processed and so on To ensure proper operation never change the FCHL bits unless the EFCOP is in the individual reset state FEN 0 10 42 DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 4 10 EFCOP Interrupt Vectors Table 10 10 shows the EFCOP interrupt vectors and Table 10 11 shows the DMA request EFCOP Programming Model sources Table 10 10 EFCOP Interrupt Vectors Interrupt aa Interrupt Interrupt Address Interrupt Vector Priority Enable Conditions VBA 68 Data input buffer empty Highest FDIIE FDIBE 1 VBA 6A Data output buffer full Lowest FDOIE FDOBF 1 Table 10 11 EFCOP DMA Request Sources Requesting Device Number R
49. jset 11 y M_FCSR Wait until FDOIE is cleared do 40 endd nop endd nop nop stop_label nop jmp stop_label e KKK KEK KKK KKK KK KEK KKK KKK KKK KKK KEK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK RAR at kdo Interrupt handler for EFCOP output movep y M_FDOR x r0 Get F n from FDOR Store in destination memory space PARA KEK Calculate Ke KKKKKKKKK move x r1 a Retrieve desired value R n move x r0 y0 sub y0 a calculate E n R n F n move MU2 yO move a yl mpy y0 yl a calculate Ke mu 2 E n KKK KEK KEK KKK KKK KKK KEK KKK ARK ARA movepal y M_FKIR store Ke in FKIR DSP56311 Reference Manual Rev 2 10 30 Freescale Semiconductor E EFCOP Operation dec b jne cont nop belr 11 y M_FCSR Disable output interrupt cont TEL nop nop nop e KKK KEK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KA KAR RRA KARA KA KK RAR at e KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK at ORG y FCBA_ADDRS de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 de 000000 DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 31 Enhanced Filter Coprocessor ORG x SRC_ADDRS NCLUDE input asm Refere
50. pr PDRD i bit is reflected as a value on the output signal line Either a hardware RESET signal or a software RESET instruction clears all PDRC and PDRD bits 23 22 20 19 17 16 15 14 13 12 11 10 8 7 5 4 3 2 1 0 PDRx5 PDRx4 PDRx3 PDRx2 PDRx1 PDRx0 Note For bits 5 0 the value represents the level that is written to or read from the associated signal line if it is enabled as a GPIO signal by the respective port control register PCRC or PCRD bits For ESSIO the GPIO signals are PC 5 0 For ESSI1 the GPIO signals are PD 5 0 The corresponding data bits for Port C GPIOs are PDRC 5 0 The corresponding data bits for Port D GPIOs are PDRD 5 0 Reserved Read as zero Write with zero for future compatibility Figure 7 20 Port Data Registers PDRC X FFFFBD PDRD X FFFFAD Freescale Semiconductor DSP56311 User s Manual Rev 2 7 35 Enhanced Synchronous Serial Interface ESSI DSP56311 User s Manual Rev 2 7 36 Freescale Semiconductor Serial Communication Interface SCI 8 The SCI provides a full duplex port for serial communication with other DSPs microprocessors or peripherals such as modems The SCI interfaces without additional logic to peripherals that use TTL level signals With a small amount of additional logic the SCI can connect to peripheral interfaces that have non TTL level signals such as RS
51. s Manual Rev 2 Freescale Semiconductor Dynamic Memory Configuration Switching 3 3 3 Internal Y I O Space The second part of the on chip peripheral registers occupies 16 locations FFFF80 FFFF8F of the Y data memory This area is the internal Y I O space and it can be accessed by MOVE MOVEP instructions and by bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET The contents of the internal Y I O memory space are listed in Appendix A 3 3 4 External Y I O Space Off chip peripheral registers should be mapped into the top 112 locations FFFF90 FFFFFF to take advantage of the move peripheral data MOVEP instruction and the bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET This area is the external Y I O space 3 4 Dynamic Memory Configuration Switching When the internal memory configuration is altered by remapping RAM modules from X and Y data memories into program memory space and vice versa data contents of the switched RAM modules are preserved Any sequence that complies with the switch condition is valid For example if the program flow executes in the address range that is not affected by the switch the switch condition can be met very easily A switch can be accomplished just by changing the OMR MS MSW bits in the regular program flow assuming no accesses to the affected address ranges of the data
52. the SCI receiver recognizes only the overrun error Freescale Semiconductor DSP56311 User s Manual Rev 2 8 15 Serial Communication Interface SCI Table 8 4 SCI Status Register SSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 4 OR 0 Overrun Error Flag Set when a byte is ready to be transferred from the receive shift register to the receive data register SRX that is already full RDRF 1 The receive shift register data is not transferred to the SRX The OR flag indicates that character s in the received data stream may have been lost The only valid data is located in the SRX OR is cleared when the SCI status register is read followed by a read of SRX The OR bit clears the FE and PE bits that is overrun error has higher priority than FE or PE A hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction clears OR IDLE Idle Line Flag Set when 10 or 11 consecutive ones are received IDLE is cleared by a start bit detection The IDLE status bit represents the status of the receive line The transition of IDLE from 0 to 1 can cause an IDLE interrupt ILIE RDRF Receive Data Register Full Set when a valid character is transferred to the SCI receive data register from the SCI receive shift register regardless of the error bits condition RDRF is cleared when the SCI receive data register is re
53. the TSM register is reset to FFFFFFFF enabling all 32 slots for data transmission DSP56311 User s Manual Rev 2 7 32 Freescale Semiconductor ESSI Programming Model 7 5 10 Receive Slot Mask Registers RSMA RSMB Both receive slot mask registers are read write registers In Network mode the receiver s use these registers to determine which action to take in the current time slot Depending on the setting of the bits the receiver s either tri state the receiver s data signal s or receive a data word and generate a receiver full condition 23 22 21 20 19 18 17 16 15 14 13 12 RS15 RS14 RS13 RS12 11 10 9 8 7 6 5 4 3 2 1 0 RS11 RS10 RS9 RS8 RS7 RS6 RS5 RS4 RS3 RS2 RS1 RSO Reserved bit read as 0 write to O O for future compatibility ESSIO X FFFFB2 ESSI1 X FFFFA2 Figure 7 16 ESSI Receive Slot Mask Register A RSMA 23 22 21 20 19 18 17 16 15 14 13 12 RS31 RS30 RS29 RS28 11 10 9 8 7 6 5 4 3 2 1 0 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16 Reserved Read as zero Write with zero for future compatibility ESSIO X FFFFB1 ESSI1 X FFFFA1 Figure 7 17 ESSI Receive Slot Mask Register B RSMB RSMA and RSMB as in Figure 7 12 and Figure 7 13 can be seen as one 32 bit register RSM Bit nin RSM RSn is an enable disable control bit for time slot n
54. 0 RIE 11 0 0 ILIE 10 0 0 TE 9 0 0 NN RE 8 0 0 NN WOMS 7 0 0 RWU 6 0 0 WAKE 5 0 0 SBK 4 0 0 SSFTD 3 0 0 WDS 2 0 2 0 0 0 SSR R8 7 0 0 0 0 FE 6 0 0 0 0 PE 5 0 0 0 0 OR 4 0 0 0 0 IDLE 3 0 0 0 0 RDRF 2 0 0 0 0 TDRE 1 1 1 1 1 TRNE 0 1 1 1 1 TCM 15 0 0 RCM 14 0 0 SCCR SCP 13 0 0 COD 12 0 0 CD 11 0 11 0 0 0 T SRX SRX 23 0 23 16 15 8 7 0 STX STX 23 0 23 0 NN E SRSH SRS 8 0 8 0 e STSH STS 8 0 8 0 z E 7 SRSH SCI receive shift register STSH SCI transmit shift register HW Hardware reset is caused by asserting the external RESET signal SW Software reset is caused by executing the RESET instruction IR Individual reset is caused by clearing PCRE bits 0 2 configured for GPIO ST Stop reset is caused by executing the STOP instruction 1 The bit is set during this reset 0 The bit is cleared during this reset The bit is not changed during this reset DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 5 Serial Communication Interface SCI 8 4 SCI Initialization The SCI is initialized as follows 1 Ensure that the SCI is in its individual reset state PCRE 0 Use a hardware RESET signal or software RESET instruction 2 Program the SCI control registers 3 Configure at least one SCI signal as an SCI signal If interrupts are to be used the signals must be selected and global interrupts must be enabled an
55. 0400 BFFF 0000 3FFF 0000 3FFF EFCOP but not by the DMA controller e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the Figure 3 4 Memory Switch On MSW 00 Cache On 24 Bit Mode DSP56311 User s Manual Rev 2 3 12 Freescale Semiconductor Memory Maps Program X Data Y Data FFFFFF FFFFFF FFFFFF External I O Internal O SFFFFCO FFFF80 FFFF80 _ Internal I O FFFOOO FFFooo External Internal Reserved Internal Internal Reserved Reserved FFOOCO FF0000 Bootstrap ROM FF0000 FF0000 018000 External 01 4000 Reserved 00C000 00C000 Internal Internal Internal Reserved Reserved Program RAM 006000 006000 80K Internal X data 000000 oo0000 RAM 24K Internal Y data 000000 RAM 24K Bit Settings Memory Configuration MS MSW pro CE SC ProgramRAM XDataRAM Y Data RAM Cache Addressable Memory Size 1 01 0 0 80K 24K 24K None 16M 0000 0000 5FFF 0000 5FFF 13FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 5 Memory Switch On MSW 01 Cache Off 24 Bit Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor 3 13 3 14 Memory Configuration Program X Data Y Data SEFFFFF FFFFFF External 1
56. 1 ESSIO X FFFFB3 Read Write Reset FFFF ESSI1 X FFFFA3 Read Write 23 16 15 14 13 12 11 SSI Receive Slot Mask 0 IgnoreTime Slot ESSI Receive Slot Mask A RSMA 0 1 ESSIO X FFFFB2 Read Write Reset FFFF ESSI1 X FFFFA2 Read Write SSI Receive Slot Mask 0 Ignore Time Slot 1 Active Time Slot ESSI Receive Slot Mask B RSMB 0 1 ESSIO X FFFFB1 Read Write Reset FFFF ESSI1 X FFFFA1 Read Write Sheet 3 of 3 3 2 Reserved Program as 0 Figure B 17 ESSI Transmit and Receive Slot Mask Registers TSM RSM DSP56311 User s Manual Rev 2 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 1 of 2 Transmitter Enable Word Select Bits 0 Transmitter Disable 0 0 0 8 bit Synchronous Data Shift Register Mode 1 Transmitter Enable 0 0 1 Reserved 0 1 0 10 bit Asynchronous 1 Start 8 Data 1 Stop Reserved 11 bit Asynchronous 1 Start 8 Data Even Parity 1 Stop 11 bit Asynchronous 1 Start 8 Data Odd Parity 1 Stop 11 bit Multidrop 1 Start 8 Data Data Type 1 Stop Reserved Idle Line Interrupt Enable 011 O Idle Line Interrupt Disabled 100 1 Idle Line Interrupt Enabled 101 110 111 Receive Interrupt Enable 0 Receive Interrupt Disabled 1 Idle Line Interrupt Enabled Receiver Wakeup Enable SCI Shift Direction Transmit Interrupt Enable 0 receiver has awakened O LSB First 0 Transmit Interrupts Disabled 1 Wakeup functio
57. 1 DSP Core Int rface 2 2 gece tien A we ee Se chee rea O A 6 1 Host Processor Interface cai a pina a kaii 6 1 Host Port Signals yes ia yor gaa Ayan vey bea oe etn wah ee ee Ae EE A 6 3 DU te aet arte caren pa E Aen aa ean ay aaa a Bean edt pacha a A a e hove 6 4 Operativa cies mele a O A A RA 6 5 Software Poll sse tae tar rei rie 6 6 Core Interrupts and Host Commands 0 cece eee eee ees 6 6 Core DMA ACCESS 54 sich A a SPE OPN been an abe ee ease 6 8 Host Request 32 22 ee eh ei ede A So Mahe ge de RA ANAL i cta 6 8 Endian Modest ead lb beg A a de AA eG hoes 6 9 Boot up Using the HIO8 Host Port 0 0 eee cece ences 6 11 DSP Core Programming Model 0 0 0 0 eee cee ee eee ene nes 6 11 Host Control Register HCR 0 0 0 a a a a E ara nen e a 6 12 Host Status Register HSR o oooooocoocoocooococo 6 13 Host Data Direction Register HDDR oooocoocccccncooco 6 14 Host Data Register HDR J yas a a REA BEA idas needa 6 15 Host Base Address Register HBAR 1 0 0 0 000 ccc cece teen nee 6 15 Host Port Control Register HPCR 0 cence eens 6 16 Host Transmit HTX Register 0 cence teen ne i 6 20 Host Receive HRX Register 1 cence ene E ees 6 20 DSP Side Registers After Reset 0 0 0 cece eere 6 20 Host Programmer Models onres it bowel ae hn be ea ae bes oe 6 21 Interface Control Register ICR 0 0 eee nen ence eas 6 22 Command Vector Register CVR 20 0 ccc ce
58. 10 FIR Filter Type Processing Options 0 0 0 10 10 Coefficient Update Option 0 0 eee eee eee 10 10 Adaptive Mode Option o oooococcccocoo cece eee nets 10 10 Multichannel Mode Option 0 0 0c cece ccc een ene 10 11 Decimation Option peeta a eae seas a ee ane gels Ges E 10 11 UR Filter Py pe is ovis eae fie ag See eh WOE oe Boe YEE a eee eee as 10 11 EFCOP Data Transfer Examples 2 0 0 0 eee eee ene eens 10 12 EFCOP Operation Examples 2 0 0 0 cece eee ene ene E 10 14 Real PIR Filter omic a dad e 10 14 DMA Input DMA Output 2 0 2 ccc eee nee 10 14 DMA Input Polling Output 2 0 0 cece eee ee 10 19 DMA Input Interrupt Output 0 0 ccc eee 10 21 Real FIR Filter With Decimation by M 0 0 cee eee eee 10 24 Adaptive FIR Filt r aiii a phate fades eee dae bel ee 10 25 Implementation Using Polling 0 0 cece eee eee 10 26 Implementation Using DMA Input and Interrupt Output 0 10 27 Updating an PIR Filter oc es 10 27 Verification for Filter Examples 00 0 c cece cee eens 10 32 Input Sequence input asm 0 0 eee ee ee nee 10 32 Filter Coefficients coefs asm orainne a ee een een eens 10 33 Output Sequence for Examples 10 1 10 2 and 10 3 00000 10 33 Desired Signal for Example 10 4 0 0 0 2 eee cece eee 10 34 Output Sequence for Example 10 4 00 0 cece ec eee 10 34 EFCOP Programming Model
59. 10K of Y data RAM are shared memory that can be accessed by the core and Figure 3 13 Memory Switch On MSW 00 Cache Off 16 Bit Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor 3 21 Memory Configuration Program X Data Y Data FFFF FFFF Internal I O FFCO FF80 __Internal I O FFFF External 1 O External FF80 1800 External External C000 C000 Reserved Reserved Internal PEY ott AM 4000 g4000 ___ 0400 Internal X data Internal Y data 0000 0000 RAM 16K oo00 RAM 16K Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 00 1 1 95K 16K 16K Enabled 64K 0400 17FF 0000 3FFF 0000 3FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 14 Memory Switch On MSW 00 Cache On 16 Bit Mode DSP56311 User s Manual Rev 2 3 22 Freescale Semiconductor FFFF 1400 0000 Program External Internal Program RAM 80K FFFF FF80 C000 6000 0000 X Data Internal I O External Reserved Internal X data RAM 24K Memory Maps Y Data External I O Internal I O FFFF FFCO FF80 External C000 Internal Y data RAM 24K 6000 0000
60. 11 10 9 8 7 6 5 4 3 2 1 0 MF11 MF10 MF9 MF8 MF7 MF6 MF5 MF4 MF3 MF2 MP1 MFO Figure 4 5 PLL Control Register PCTL Table 4 7 defines the DSP56311 PCTL bits Changing the following bits may cause the PLL to lose lock and re lock according to the new value PD 3 0 PEN XTLR and MF Table 4 7 PLL Control Register PCTL Bit Definitions Bit Number Bit Name Reset Value Description 23 20 PD 3 0 0 Predivider Factor Define the predivision factor PDF to be applied to the PLL input frequency The PD 3 0 bits are cleared during DSP56311 hardware reset which corresponds to a PDF of one COD Clock Output Disable Controls the output buffer of the clock at the CLKOUT pin When COD is set the CLKOUT output is pulled high When COD is cleared the CLKOUT pin provides a 50 percent duty cycle clock Freescale Semiconductor DSP56311 User s Manual Rev 2 4 19 Core Configuration Table 4 7 PLL Control Register PCTL Bit Definitions Continued Bit Number Bit Name Reset Value Description 18 PEN Set to PINIT PLL Enable input value Enables PLL operation 17 PSTP 0 PLL Stop State Controls PLL and on chip crystal oscillator behavior during the stop processing state 16 XTLD 0 XTAL Disable Controls the on chip crystal oscillator XTAL output The XTLD bit is cleared during DSP56311 hardware reset so the XTAL output signal is active permitt
61. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CP 1 0 RM SM CE SA FV LF DM Sc S 1 0 111 0 s LJEJU N zlv Reset 1 1po o o o o ofo o o o o o 1 1Jo o o o o o j o Oo Reserved bit Read as zero write to zero for future compatibility Figure 4 1 Status Register SR DSP56311 User s Manual Rev 2 Freescale Semiconductor 4 5 Core Configuration Table 4 2 Status Register Bit Definitions Bit Number Bit Name Reset Value Description 23 22 CP 1 0 11 Core Priority Under control of the CDP 1 0 bits in the OMR the CP bits specify the priority of core accesses to external memory These bits are compared against the priority bits of the active DMA channel If the core priority is greater than the DMA priority the DMA waits for a free time slot on the external bus If the core priority is less than the DMA priority the core waits for a free time slot on the external bus If the core priority equals the DMA priority the core and DMA access the external bus in a round robin pattern for example P X Y DMA P X Y DMA OMR Priority CDP 1 0 Core Priority Priority oae SR CP 1 0 Dynamic 0 Determined 00 00 Lowest by DCRn 1 DPR 1 0 00 01 2 for active 00 10 3 DMA 00 11 Highest channel Static core lt DMA 01 XX core DMA 10 XX core gt DMA 11 XX 21 RM Rounding Mode Selects the type of round
62. 2 Freescale Semiconductor 3 9 Memory Configuration Program FFFFFF FFFFFF FFFF80 FFFOOO Internal Reserved FFOOCO rFo000 Bootstrap ROM FF0000 External 00C000 008000 Internal Program RAM 31K 000000 000000 000400 X Data Internal Reserved External Internal X data RAM 48K FFFFFF Internal O FFFFCO FFFF80 FFFOOO FF0000 000000 Y Data External 1 O Internal I O External Internal Reserved External 00C000 Internal Y data RAM 48K Bit Settings Memory Configuration ms MSW cE sc ProgramRAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 0 any 1 0 31K 48K 48K Enabled 16M value 0400 7FFF 0000 BFFF 0000 BFFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 2 Memory Switch Off Cache On 24 Bit Mode DSP56311 User s Manual Rev 2 3 10 Freescale Semiconductor Program FFFFFF FFFFFF FFFF80 FFFOOO Internal Reserved FFOOCO FF0000 FF0000 External 018000 00C000 Internal Program RAM 96 K 004000 000000 000000 Memory Maps X Data Y Data SFFFFFF External I O Internal I O FFFFCO Internal I O External FFFF80 External FFF000 Internal Reserved Internal Reserved
63. 2 or prescale CLK TLR N I Counter TCR 0 N N 1 De M M 1 TCPR M TCF Compare Interrupt if TCIE 1 TOF Overflow Interrupt if TOIE 1 float TIO pin INV 0 float high TIO pin INV 1 TIO can connect to the RESET pin internal hardware preserves the TIO value and direction for an additional 2 5 clocks to ensure a reset of valid length low Figure 9 19 Watchdog Toggle Mode 9 3 4 3 Reserved Modes Modes 8 11 12 13 14 and 15 are reserved DSP56311 User s Manual Rev 2 9 20 Freescale Semiconductor Triple Timer Module Programming Model 9 3 5 Special Cases The following special cases apply during wait and stop state E Timer behavior during wait Timer clocks are active during the execution of the wait instruction and timer activity is undisturbed If a timer interrupt is generated the DSP56311 leaves the wait state and services the interrupt E Timer behavior during stop During execution of the stop instruction the timer clocks are disabled timer activity stops and the TIO signals are disconnected Any external changes that happen to the TIO signals are ignored when the DSP56311 is in stop state To ensure correct operation disable the timers before the DSP56311 is placed in stop state 9 3 6 DMA Trigger Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered by a timer event The timer issues a DMA trigger on every event in
64. 232 RS 422 and so on This interface uses three dedicated signals transmit data receive data and SCI serial clock It supports industry standard asynchronous bit rates and protocols as well as high speed synchronous data transmission SCI asynchronous protocols include a multidrop mode for master slave operation with wake up on idle line and wake up on address bit capability This mode allows the DSP56311 to share a single serial line efficiently with other peripherals The SCI consists of separate transmit and receive sections that can operate asynchronously with respect to each other A programmable baud rate generator supplies the transmit and receive clocks An enable vector and an interrupt vector are included so that the baud rate generator can function as a general purpose timer when the SCI is not using it or when the interrupt timing is the same as that used by the SCI 8 1 Operating Modes The operating modes for the DSP56311 SCI are as follows E 8 bit synchronous shift register mode 10 bit asynchronous 1 start 8 data 1 stop E 11 bit asynchronous 1 start 8 data 1 even parity 1 stop E 11 bit asynchronous 1 start 8 data 1 odd parity 1 stop E 11 bit multidrop asynchronous 1 start 8 data 1 data type 1 stop This mode is used for master slave operation with wake up on idle line and wake up on address bit capability It allows the DSP56311 to share a single serial line efficiently with other peripherals Thes
65. 4 3 HF 3 2 0 Host Flags 2 3 General purpose flags for DSP to host communication The DSP core can set or clear HF 3 2 The values of HF 3 2 are reflected in the interface status register ISR that is if they are modified by the DSP software the host processor can read the modified values by reading the ISR These two general purpose flags can be used individually or as encoded pairs in a simple DSP to host communication protocol implemented in both the DSP and the host processor software The bit value is indeterminate after an individual reset DSP56311 User s Manual Rev 2 6 12 Freescale Semiconductor DSP Core Programming Model Table 6 8 Host Control Register HCR Bit Definitions Bit Number Bit Name Reset Value Description 2 HCIE 0 Host Command Interrupt Enable Generates a host command interrupt request if the host command pending HCP status bit in the HSR is set If HCIE is cleared HCP interrupts are disabled The interrupt address is determined by the host command vector register CVR NOTE If more than one interrupt request source is asserted and enabled for example HRDF is set HCP is set HRIE is set and HCIE is set the HI08 generates interrupt requests according to priorities shown here The bit value is indeterminate after an individual reset Priority Interrupt Source Highest Host Command HCP 1 Transmit Data HTDE 1 Lowest Recei
66. 5 4 3 2 1 0 k X Peps pcoa Pcos Pcoa Pcp1 PcDo 0 0 Port D Control Register PCRD X FFFFAF Read Write Reset 000000 PDCn 1 gt Port Pin is Output PDCn 0 gt Port Pin is Input 2376 5 4 3 2 1 0 3 Pros PRD4 PRDS PRD2 PRD1 PRDO Port D Direction Register PRRD X FFFFAE Read Write Reset 000000 if port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n 23 76 5 4 3 2 1 0 X Pops PDD4 Pops PDD2 PDD1 PDD Port D GPIO Data Register PDRD X FFFFAD Read Write Reset 000000 Reserved Program as 0 Figure B 25 Port D Registers PCRD PRRD PDRD DSP56311 User s Manual Rev 2 B 36 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 4 of 4 GPIO Port E SCI PCn 1 Port Pin configured as ESSI PCn 0 Port Pin configured as GPIO 2376 5 4 3 2 1 0 lx X Pee Pce Pceo 0 olo o Port E Control Register PCRE X FFFF9F Read Write Reset 000000 PDCn 1 gt Port Pin is Output PDCn 0 gt Port Pin is Input 2376 5 4 3 2 1 0 k xe x Jerez PRE PREO a a TT Port E Direction Register PRRE X FFFF9E Read Write Reset 000000 if port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n 236 5 4 3 2
67. 6 26 Transmitter Ready TRDY 6 26 interrupt routines 6 7 Interrupt Vector Register IVR 6 21 6 27 programming sheet B 25 interrupt based techniques 6 21 masking interrupts 6 7 MOVEP instruction 6 12 multiplexed bus mode 6 3 6 15 6 18 non multiplexed bus mode 6 3 6 18 pipeline 6 5 polling techniques 6 21 6 27 programming model DSP side 6 11 host side 6 21 quick reference 6 29 Receive Byte Registers RXH RHM RHL 6 6 Receive Byte Registers RXH RXM RXL 6 5 6 27 register banks 6 4 request service from host 6 8 resets hardware and software 6 3 6 12 single strobe mode 6 19 software polling 6 6 software reset 6 28 STOP command 6 22 STOP instruction 6 28 Stop mode 6 22 timing requirements 6 6 Transmit Byte Registers 6 5 Transmit Byte Registers TXH TXM TXL 6 28 Transmit Data Registers TXH TXM TXL 6 5 Transmit Registers TXH TXM TXL 6 6 vector registers 6 21 Host Litle Endian HLEND bit 6 23 Host Multiplexed Bus HMUX bit 6 17 Host Port Control Register HPCR 6 3 6 12 6 16 6 20 6 21 6 29 6 30 Host Acknowledge Enable HAEN 6 18 Host Acknowledge Polarity HAP 6 16 Host Address Line 8 Enable HA8EN 6 18 Host Address Line 9 Enable HA9EN 6 18 7 19 Host Address Strobe Polarity HASP 6 17 Host Chip Select Enable HCSEN 6 18 Host Chip Select Polarity HCSP 6 17 Host Data Strobe Polarity HDSP 6 17 Host Dual Data Strobe HDDS 6 17 Host Enable HEN 6 17 Host GPIO Port Enable HGEN 6 18 Host Multip
68. 8 7 mode 4 3 program 4 4 A 1 program options invoking 4 4 ROM 1 6 Boundary Scan Register BSR 4 33 Burst Mode Enable BE bit 4 12 bus address 2 2 data 2 2 external address 2 5 external data 2 5 internal 1 10 multiplexed 2 2 non multiplexed 2 2 Bus Access Type BAT bits 4 27 Bus Address Attribute Polarity BAAP bit 4 26 Bus Address to Compare BAC bits 4 25 Bus Area 0 Wait State Control BAOW bits 4 22 Bus Area 1 Wait State Control BA1W bits 4 22 Bus Area 2 Wait State Control BA2W bits 4 22 Bus Area 3 Wait State Control BA3W bits 4 21 Bus Column In Page Wait State BCW bits 4 24 Bus Control Register BCR 4 20 bit definitions 4 21 Bus Area 0 Wait State Control BAOW 4 22 Bus Area 1 Wait State Control BA1W 4 22 Bus Area 2 Wait State Control BA2W 4 22 Bus Area 3 Wait State Control BA3W 4 21 Bus Default Area Wait State Control BDFW 4 21 Bus Request Hold BRH 4 21 Bus State BBS bit 4 21 programming sheet B 17 Bus Default Area Wait State Control BDFW bits 4 21 Bus DRAM Page Size BPS bits 4 24 Bus Interface Unit BIU Address Attribute Registers AAR 4 20 Bus Control Register BCR 4 20 DRAM Control Register DCR 4 20 Bus Mastership Enable BME bit 4 24 Bus Number of Address Bits to Compare BNC bits 4 25 Bus Packing Enable BPAC bit 4 26 DSP56311 User s Manual Rev 2 Freescale Semiconductor Index 1 Index Bus Page Logic Enable BPLE bit 4 24 Bus Program Memory Enable BPEN bit 4 26 B
69. DSP core can access all eight registers but the external host cannot The following data registers are 24 bit registers used for high speed data transfers by the DSP core E Host data receive register HRX on page 6 20 E Host data transmit register HTX on page 6 20 The DSP side control registers are 16 bit registers that control HI08 functionality Host control register HCR on page 6 12 Host status register HSR on page 6 13 Host GPIO data direction register HDDR on page 6 14 Host GPIO data register HDR on page 6 15 Host base address register HBAR on page 6 15 E Host port control register HPCR on page 6 16 Both hardware and software resets disable the HIO8 After a reset the HIOS signals are configured as GPIO and disconnected from the DSP56300 core that is the signals are left floating 6 6 1 Host Control Register HCR This read write register controls the HIO8 interrupt operation Initialization values for HCR bits are presented in Section 6 6 9 DSP Side Registers After Reset on page 6 20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HF3 HF2 HCIE HTIE HRIE Reserved bit read as 0 write to O for future compatibility Figure 6 6 Host Control Register HCR X FFFFC2 Table 6 8 Host Control Register HCR Bit Definitions Bit Number Bit Name Reset Value Description 15 5 0 Reserved Write to O for future compatibility
70. Direction SCKD 7 21 Frame Sync Length FSL 7 21 Frame Sync Polarity FSP 7 20 Frame Sync Relative Timing FSR 7 21 Mode Select MOD 7 20 programming sheet B 27 Receive Enable RE 7 19 Receive Exception Interrupt Enable REIE 7 18 Receive Interrupt Enable RIE 7 18 Receive Last Slot Interrupt Enable RLIE 7 18 Serial Control Direction 0 SCDO 7 22 Serial Control Direction 1 SCD1 7 22 Serial Control Direction 2 SCD2 7 21 Serial Output Flag 0 OFO 7 22 Serial Output Flag 1 OF1 7 22 Shift Directions SHFD 7 21 Synchronous Asynchronous SYN 7 20 Transmit 0 Enable TEO 7 19 Transmit 1 Enable TE1 7 19 Transmit 2 Enable TE2 7 20 Transmit Exception Interrupt Enable TEIE 7 18 Transmit Interrupt Enable TIE 7 18 Transmit Last Slot Interrupt Enable TLIE 7 18 Core Priority CP bits 4 6 Core DMA Priority CDP bits 4 13 cross correlation filtering 10 1 crystal frequency 8 6 Crystal Range XTLR bit 4 20 D data and control host processor registers 6 12 Data Arithmetic Logic Unit Data ALU 1 6 1 7 Data Input DI bit 9 25 data memory expansion 1 10 Data Output DO bit 9 25 data strobe 6 3 data transfer methods 5 2 data coefficient transfer contention bit 10 2 DE signal 2 19 Debug Event signal DE signal 2 19 Debug mode entering 2 19 external indication 2 19 warning 3 8 Debug support 1 6 decimation 10 4 10 35 10 42 example sequence of even real numbers 10 24 Decimation Channel Count Register FDCH 10 42
71. Enable Host Acknowledge Priority 0 HACK Active Low 1 HACK Active High 14 11 es HcsP HDDS HMUX HASP HDSP HROD ll HAEN HREN HCSEN HA9EN HASEN HGEN Host Port Control Register HPCR X FFFFC4 Read Write Reset 00 Reserved Program as 0 Figure B 11 Host Base Address and Host Port Control Registers DSP56311 User s Manual Rev 2 B 22 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 3 of 5 Host Receive Interrupt Enable 0 Disable 1 Enable if HRDF 1 Host Transmit Interrupt Enable 0 Disable 1 Enable if HTDE 1 Host Command Interrupt Enable 0 Disable 1 Enable if HCP 1 Host Control Register HCR X FFFFC2 Read Write Reset 0 Reserved Program as 0 Figure B 12 Host Control Register DSP56311 User s Manual Rev 2 Freescale Semiconductor B 23 Programming Reference Application Date Programmer O ST Host Side Receive Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 Host DSP 1 DSP gt Host Sheet 4 of 5 Transmit Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 DSP gt Host 1 Host gt DSP HDRQ HREQ HTRQ HACK HRRQ 0 HREQ HACK 1 HTRQ HRRQ Host Flags Write Only Host Little Endian Initialize Write Only 0 No Action 1 Initialize DMA 7 6 5 4 3 2 1 0 aa HF1 HFO HDRQ TREQ RREQ 0 Interrupt Control
72. Enabled 64K 0400 BFFF 0000 9FFF 0000 9FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 20 Memory Switch On MSW 11 Cache On 16 Bit Mode DSP56311 User s Manual Rev 2 3 28 Freescale Semiconductor Core Configuration 4 This chapter presents DSP56300 core configuration details specific to the DSP56311 These configuration details include the following E Operating modes E Bootstrap program E Central Processor registers Status register SR Operating mode register OMR E Interrupt Priority Registers IPRC and IPRP E PLL control PCTL register E Bus Interface Unit registers Bus Control Register BCR DRAM Control Register DCR Address Attribute Registers AAR 3 0 DMA Control Registers 5 0 DCR 5 0 Device identification register IDR JTAG identification register JTAG boundary scan register BSR For information on specific registers or modules in the DSP56300 core refer to the DSP56300 Family Manual 4 1 Operating Modes The DSP56311 begins operation by leaving the Reset state and going into one of eight operating modes As the DSP56311 exits the Reset state it loads the values of MODA MODB MODC and MODD into bits MA MB MC and MD of the OMR These bit settings determine the chip s operating mode which in turn determine
73. Enhanced Synchronous Serial Interface 0 ESSIO Continued Signal Name Type State During Reset 2 Signal Description Scot PC1 Input Output Input or Output Ignored input Serial Control 1 Functions in either Synchronous or Asynchronous mode For Asynchronous mode this signal is the receiver frame sync I O For Synchronous mode this signal is either Transmitter 2 output or Serial I O Flag 1 Port C 1 The default configuration following reset is GPIO For PC1 signal direction is controlled through PRRC This signal is configured as SCO1 or PC1 through PCRC This input is 5 V tolerant SC02 PC2 Input Output Input or Output Ignored input Serial Control Signal 2 The frame sync for both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode When configured as an output this signal is the internally generated frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter and the receiver in synchronous operation Port C 2 The default configuration following reset is GPIO For PC2 signal direction is controlled through PRRC This signal is configured as SC02 or PC2 through PCRC This input is 5 V tolerant SCKO PC3 Input Output Input or Output Ignored input Serial Clock Provides the serial bit rate clock for the ESSI interface for both the transmitter and receiver
74. Figure 6 9 Host Data Register HDR X FFFFC8 Table 6 10 HDR and HDDR Functionality HDDR HDR Dxx DRxx 1 1 GPIO Signal Non GPIO Signal 0 Read only bit The value read is the binary value of Read only bit Does not contain significant data the signal The corresponding signal is configured as an input 1 Read write bit The value written is the value read Read write bit The value written is the value read The corresponding signal is configured as an output and is driven with the data written to Dxx 1 Defined by the selected configuration 6 6 5 Host Base Address Register HBAR In multiplexed bus modes HBAR selects the base address where the host side registers are mapped into the host bus address space The address from the host bus is compared with the base address as programmed in the Base Address Register An internal chip select is generated if a match is found Figure 6 11 shows how the chip select logic uses HBAR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA10 BAY BA8 BA7 BA6 BAS BA4 BA3 Reserved bit read as 0 write to O for future compatibility Figure 6 10 Host Base Address Register HBAR X FFFFC5 Table 6 11 Host Base Address Register HBAR Bit Definitions Bit Number Bit Name Reset Value Description 15 8 0 Reserved Write to 0 for future compatibility 7 0 BA 10 3 80 Base Address
75. Freescale Semiconductor 10 17 Enhanced Filter Coprocessor movex0 x r0 clear FDM memory area DMA channel 1 initialization output from EFCOP movep M_FDOR x M_DSR1 DMA source address points to the EFCOP FDIR movep DST_ADDRS x M_DDR1 Init DMA destination address movep DST_COUNT x M_DCO1 Init DMA count movep S8EB2C1 x M_DCR1 Start DMA 1 with FDOBF request EFCOP initialization movep FIR_LEN 1 y M_FCNT FIR length movep FDBA_ADDRS y M_FDBA FIR input samples Start Address movep FCBA_ADDRS y M_FCBA FIR Coeff Start Address movep FCON y M_FCSR Enable EFCOP DMA channel 0 initialization input to EFCOP movep SRC_ADDRS x M_DSRO DMA source address points to the DATA bank movep M_FDIR x M_DDRO Init DMA destination address movep SRC_COUNT x M_DCOO Init DMA count to line mode movep 1 x M_DORO DMA offset reg is 1 movep S940AA04 x M_DCRO Init DMA control reg to line mode FDIBE request nop nop KKK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KEKE mn jclr 0 x M_DSTR jclr 1 x M_DSTR nop nop stop_label nop jmp stop_label org xX SRC_ADDRS NCLUDE input asm org y FCBA_ADDRS NCLUDE coefs asm DSP56311 Reference Manu
76. HS 0 Single strobe bus R W and DS HMUX 0 Non multiplexed bus HASP 0 address strobe polarity has no meaning in non multiplexed bus HDSP 0 Negative data strobes polarity HROD 0 Host request is active when enabled Spare 0 This bit should be set to 0 for future compatability HEN 0 When the HPCR register is modified R HEN should be cleared HAEN 1 Host acknowledge is enabled HREN 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 0 address 9 enable bit has no meaning in non multiplexed bus HABEN 0 address 8 enable bit has no meaning in non multiplexed bus HGEN 0 Host GPIO pins are disabled bra lt HIO8CONT OMR11IS0O jset 0 omr HC11HOSTLD If MD MC MB MA 1101 go load from HC11 Host If MD MC MB MA 1100 go load from ISA HOST ISAHOSTLD movep 0101000000011000 x M_HPCR Configure the following conditions HAP 0 Negative host acknowledge HRP 1 Positive host request HCSP 0 Negative chip select input HD HS 1 Dual strobes bus RD and WR HMUX 0 Non multiplexed bus HASP 0 address strobe polarity has no meaning in non multiplexed bus HDSP 0 Negative data strobes polarity HROD 0 Host request is active when enabled Spare 0 This bit should be set to 0 for future compatability HEN 0 When the HPCR register is modified s HEN should be cleared HAEN 0 Host acknowledge is disabled HREN 1 Host requests are enabled
77. I O Memory Map Continued X Data Memory Peripheral 16 Bit Address 24 Bit Address Register Name FFD7 FFFFD7 Reserved FFD6 FFFFD6 Reserved FFD5 FFFFD5 Reserved FFD4 FFFFD4 Reserved FFD3 FFFFD3 Reserved FFD2 FFFFD2 Reserved FFD1 FFFFD1 Reserved FFDO FFFFDO Reserved FFCF FFFFCF Reserved FFCE FFFFCE Reserved FFCD FFFFCD Reserved FFCC FFFFCC Reserved FFCB FFFFCB Reserved FFCA FFFFCA Reserved Port B FFC9 FFFFC9 Host Port GPIO Data Register HDR FFC8 FFFFC8 Host Port GPIO Direction Register HDDR HI08 FFC7 FFFFC7 Host Transmit Register HTX FFC6 FFFFC6 Host Receive Register HRX FFC5 FFFFC5 Host Base Address Register HBAR FFC4 SFFFFC4 Host Port Control Register HPCR FFC3 FFFFC3 Host Status Register HSR FFC2 FFFFC2 Host Control Register HCR FFC1 FFFFC1 Reserved FFCO FFFFCO Reserved Port C FFBF FFFFBF Port C Control Register PCRC FFBE FFFFBE Port C Direction Register PRRC FFBD FFFFBD Port C GPIO Data Register PDRC DSP56311 User s Manual Rev 2 B 4 Freescale Semiconductor Internal I O Memory Map Table B 2 Internal I O Memory Map Continued X Data Memory Peripheral 16 Bit Address 24 Bit Address Register Name ESSI 0 FFBC FFFFBC ESSI 0 Trans
78. If the XYS bit is set the stack extension is mapped to the Y memory space 15 ATE 0 Address Trace Enable This bit is valid if the operating frequency is 100 MHz or less When the conditions are valid and the bit is set the Address Trace Enable ATE bit enables Address Trace mode The Address Trace mode is a debugging tool that reflects internal memory accesses on the external address bus DSP56311 User s Manual Rev 2 Freescale Semiconductor 4 11 Core Configuration Table 4 3 Operating Mode Register OMR Bit Definitions Continued Bit Number Bit Name Reset Value Description 14 APD 0 Address Attribute Priority Disable Disables the priority assigned to the Address Attribute signals AA 0 3 When APD 0 default setting the four Address Attribute signals each have a certain priority AA3 has the highest priority AAO has the lowest priority Therefore only one AA signal can be active at one time This allows continuous partitioning of external memory however certain functions such as using the AA signals as additional address lines require the use of additional interface hardware When APD is set the priority mechanism is disabled allowing more than one AA signal to be active simultaneously Therefore the AA signals can be used as additional address lines without the need for additional interface hardware For details on the Address Attribute Registers see Section 4 6 3 Address Attribu
79. M_XTLD EQU 16 XTAL Disable Bit M_PSTP EQU 17 STOP Processing State Bit M_PEN EQU 18 PLL Enable Bit M_PCOD EQU 19 PLL Clock Output Disable Bit M_PD EQU F00000 PreDivider Factor Bits Mask PD0 PD3 M_BCR M_DCR M_AARO M_AAR1 M_AAR2 M_AAR3 M_IDR M_BAOW M_BA1W M_BA2W M_BA3W M_BDFW M_BBS M_BLH M_BRH M_BCW M_BRW M_BPS M_BPL M_BM Register Addresses Of BIU EQU EQU EQU EQU EQU EQU EQU SFFFFFB Bus Control Register SFFFFFA DRAM Control Register SFFFFF9 Address Attribute Register 0 SFFFFF8 Address Attribute Register 1 SFFFFF7 Address Attribute Register 2 SFFFFF6 Address Attribute Register 3 SFFFFF5 ID Register Bus Control Register S1F Area 0 Wait Control Mask BAOQWO BAOW4 S3E0 Area 1 Wait Control Mask BA1W0 BA14 s1C00 Area 2 Wait Control Mask BA2W0 BA2W2 SE000 Area 3 Wait Control Mask BA3W0 BA3W3 S1F0000 Default Area Wait Control Mask BDFWO BDFW4 21 Bus State 22 Bus Lock Hold 23 Bus Request Hold EQU DRAM T M_BR M_BSTR M_BRF M_BRP M_BAT M_BAAP M_BP M_BX A 18 EN EN Control Register 3 i c 300 11 7 12 A 13 14 7F8000 23 3 Ww In Page Wait States Bits Mask BCWO BCW1 Out Of Page Wait States Bits Mask BRWO BRW1 DRAM Page Size B
80. Memory Switch On MSW 10 Cache On 16 Bit Mode DSP56311 User s Manual Rev 2 3 26 Freescale Semiconductor Program FFFF External C000 Internal Program RAM 48K 0000 X Data Internal I O External FFFF FF80 C000 A000 Internal X data RAM 40K 0000 Memory Maps Y Data SERE External 1 O FFCO Internal I O FF80 External C000 A000 Internal Y data RAM 40K 0000 Bit Settings Memory Configuration ms MSW ce sc ProgramRAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 11 0 1 48K 40K 40K None 64K 0000 BFFF 0000 9FFF 0000 9FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 19 Memory Switch On MSW 11 Cache Off 16 Bit Mode Freescale Semiconductor DSP56311 User s Manual Rev 2 3 27 Memory Configuration Program X Data Y Data PEPEE PEELE External I O Internal I O FFCO External FF80 FF80 Internal I O FFFF External External C000 C000 C000 Reserved Reserved A000 A000 Internal Program RAM Internal Y data RAM 40K Internal X data M 40K 0000 0000 0000 Bit Settings Memory Configuration ms MSW ce sc ProgramRAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 11 1 1 47K 40K 40K
81. Name Value Description 18 17 DPR 1 0 OMR CDP 1 0 CP 1 0 Core Priority cont 00 00 0 lowest 00 01 1 00 10 2 00 11 3 highest 01 XX DMA accesses have higher priority than core accesses 10 XX DMA accesses have the same priority as core accesses 11 XX DMA accesses have lower priority than core accesses E if DMA priority gt core priority for example if CDP 01 or CDP 00 and DPR gt CP the DMA performs the external bus access first and the core waits for the DMA channel to complete the current transfer E if DMA priority core priority for example if CDP 10 or CDP 00 and DPR CP the core performs all its external accesses first and then the DMA channel performs its access E if DMA priority lt core priority for example if CDP 11 or CDP 00 and DPR lt CP the core performs its external accesses and the DMA waits for a free slot in which the core does not require the external bus E in Dynamic Priority mode CDP 00 the DMA channel can be halted before executing both the source and destination accesses if the core has higher priority If another higher priority DMA channel requests access the halted channel finishes its previous access with a new higher priority before the new requesting DMA channel is serviced 16 DCON O DMA Continuous Mode Enable Enables disables DMA Continuous mode When DCON is set the channel enters the Continuous Transfer mode and cannot be interrupted during a transfer by
82. O For Synchronous mode this signal is either Transmitter 2 output or Serial I O Flag 1 PD1 Input or Output Port D 1 The default configuration following reset is GPIO For PD1 signal direction is controlled through PRRD This signal is configured as SC11 or PD1 through PCRD This input is 5 V tolerant sc12 Input Output Ignored input Serial Control Signal 2 The frame sync for both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode When configured as an output this signal is the internally generated frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter and the receiver in synchronous operation Port D 2 PD2 Input or Output The default configuration following reset is GPIO For PD2 signal direction is controlled through PRRD This signal is configured as SC12 or PD2 through PCRD This input is 5 V tolerant Freescale Semiconductor DSP56311 User s Manual Rev 2 2 15 Signals Connections Table 2 12 Enhanced Synchronous Serial Interface 1 ESSI1 Continued Signal State During i Name Type Reset 2 Signal Description SCK1 Input Output Ignored input Serial Clock Provides the serial bit rate clock for the ESSI interface for both the transmitter and receiver in Synchronous modes or the transmitter only in Asynchronous modes Although an external serial clock
83. RB TE2 CRB OF1 CRA SSC1 CRB FSL 1 0 CRB FSR y Sync Mode TX Word CRB SCD2 Clock CRA DC4 0 Internal TX Frame Sync Transmit Control Logic Sync TX RX F S Async TX F S Frame Sync Figure 7 4 ESSI Frame Sync Generator Functional Block Diagram DSP56311 User s Manual Rev 2 7 16 Freescale Semiconductor ESSI Programming Model 7 5 2 ESSI Control Register B CRB CRB is one of two read write control registers that direct the operation of the ESSI see Figure 7 5 The CRB bit definitions are presented in Table 7 4 CRB controls the ESSI multifunction signals SC 2 0 which can be used as clock inputs or outputs frame synchronization signals transmit data signals or serial I O flag signals 23 22 21 20 19 18 17 16 15 14 13 12 REIE TEIE RLIE TLIE RIE TIE RE TEO TE1 TE2 MOD SYN 11 10 9 8 7 6 5 4 3 2 1 0 CKP FSP FSR FSL1 FSLO SHFD SCKD SCD2 SCD1 SCDO OF1 OFO ESSIO X FFFFB6 ESSI1 X FFFFA6 Figure 7 5 ESSI Control Register B CRB The CRB contains the serial output flag control bits and the direction control bits for the serial control signals Also in the CRB are interrupt enable bits for the receiver and the transmitter Bit settings of the CRB determines how many transmitters are enabled 0 1 2 or 3 The CRB settings also determine the ESSI operating mode Either a hardware RESET signal or a software RESET instruction clears a
84. Register ICR Host Address 0 Read Write Reset 00 Host Vector Contains Host Command Interrupt Address 2 Host Command Handshakes Executing Host Command Interrupts 7 6 5 4 83 2 1 0 Contains the host command interrupt address Command Vector Register CVR Host Address 1 Read Write Reset 32 Reserved Program as 0 Figure B 13 Interrupt Control and Command Vector Registers DSP56311 User s Manual Rev 2 B 24 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 5 of 5 HOST Host Side 7 6 5 4 3 2 1 0 Contains the interrupt vector or number Interrupt Vector Register IVR Host Address 3 Read Write Reset 0F Host Transmit Data usually loaded by program 0 7 Transmit Low Byte Transmit Middle Byte Transmit High Byte Not Used Transmit Byte Registers Host Addresses 7 6 5 4 Write Only Reset 00 Figure B 14 Interrupt Vector and Host Transmit Data Registers DSP56311 User s Manual Rev 2 Freescale Semiconductor B 25 Programming Reference Application Date Programmer Sheet 1 of 3 Select SC1 as Tx 0 drive enable 0 SC1 functions as serial I O flag 1 functions as driver enable of Tx 0 external buffer Word Length Control WLO Number of bits word 8 12 16 24 32 data in first 24 bits 32 data in last 24 bits Reserved R 22220000 220000 20000 Reserved Alignment Control 0 16 bit d
85. SFFFF95 SCI Transmit Data Register low M_SRXH EQU SFFFF9IA SCI Receive Data Register high M_SRXM EQU SFFFF99 SCI Receive Data Register middle M_SRXL EQU SFFFF98 SCI Receive Data Register low M_STXA EQU SFFFF94 SCI Transmit Address Register M_SCR EQU SFFFF9IC SCI Control Register M_SSR EQU SFFFF93 SCI Status Register M_SCCR EQU SFFFF9B SCI Clock Control Register SCI Control Register Bit Flags M_WDS EQU 7 Word Select Mask WDSO WDS3 M_WDSO EQU 0 Word Select 0 M_WDS1 EQU 1 Word Select 1 M_WDS2 EQU 2 Word Select 2 M_SSFTD EQU 3 SCI Shift Direction M_SBK EQU 4 Send Break M_WAKE EQU 5 Wakeup Mode Select M_RWU EQU 6 Receiver Wakeup Enable M_WOMS EQU 7 Wired OR Mode Select M_SCRE EQU 8 SCI Receiver Enable M_SCTE EQU 9 SCI Transmitter Enable M_ILIE EQU 10 Idle Line Interrupt Enable M_SCRIE EQU 11 SCI Receive Interrupt Enable DSP56311 User s Manual Rev 2 A 10 Freescale Semiconductor M_SCTIE EQU M_TMIE EQU M_TIR EQU M_SCKP EQU M_RETE EQU SCI Status Register 12 13 14 15 16 lt J OAU e wnn he OC SCI Clock Control Register Register Addresses Of SSIO BC M_TRNE EQU M_TDRE EQU M_RDRF EQU M_IDLE EQU M_OR EQU M_PE EQU M_FE EQU M_R8 EQU M_CD EQU M_COD EQU M_SCP EQU M_RCM EQU M_TCM EQU M_TX00 EQU M_TX01 EQU M_TX02 EQU M_TSRO EQU M_RXO EQU M_S
86. Semiconductor 9 23 Triple Timer Module 9 4 4 Timer Control Status Register TCSR The TCSR is a read write register controlling the timer and reflecting its status 23 22 21 20 19 18 17 16 15 14 13 12 TCF TOF PCE DO DI 11 10 9 8 7 6 5 4 3 2 1 0 DIR TRM INV TC3 TC2 TC1 TCO TCIE TOIE TE Reserved Read as 0 Write to 0 for future compatibility Figure 9 23 Timer Control Status Register TCSR Table 9 3 Timer Control Status Register TCSR Bit Definitions Bit Number Bit Name Reset Value Description 23 22 0 Reserved Write to zero for future compatibility 21 TCF 0 Timer Compare Flag Indicate that the event count is complete In timer PWM and watchdog modes the TCF bit is set after M N 1 events are counted M is the value in the compare register and N is the TLR value In measurement modes the TCF bit is set when the measurement completes Writing a one to the TCF bit clears it A zero written to the TCF bit has no effect The bit is also cleared when the timer compare interrupt is serviced The TCF bit is cleared by a hardware RESET signal a software RESET instruction the STOP instruction or by clearing the TCSR TE bit to disable the timer Note The TOF and TCF bits are cleared by a 1 written to the specific bit To ensure that only the target bit is cleared do not use the BSET command The proper way to clear these bits is to write 1 using a
87. TCPR TCR page B 33 GPIO Figure B 23 Host Data Direction and Host Data Registers HDDR HDR page B 34 Figure B 24 Port C Registers PCRC PRRC PDRC page B 35 Figure B 25 Port D Registers PCRD PRRD PDRD page B 36 Figure B 26 Port E Registers PCRE PRRE PDRE page B 37 Figure B 27 EFCOP Counter and Control Status Registers FCNT and FCSR page B 38 SRAN Figure B 28 EFCOP FACR FDBA FCBA and FDCH Registers page B 39 B 1 Internal I O Memory Map Table B 2 Internal l O Memory Map X Data Memory Peripheral 16 Bit Address 24 Bit Address Register Name IPR FFFF FFFFFF Interrupt Priority Register Core IPRC FFFE FFFFFE Interrupt Priority Register Peripheral IPRP PLL FFFD FFFFFD PLL Control Register PCTL OnCE FFFC FFFFFC OnCE GDB Register OGDB BIU FFFB FFFFFB Bus Control Register BCR FFFA FFFFFA DRAM Control Register DCR FFF9 FFFFF9 Address Attribute Register O AARO FFF8 FFFFF8 Address Attribute Register 1 AAR1 FFF7 FFFFF7 Address Attribute Register 2 AAR2 FFF6 FFFFF6 Address Attribute Register 3 AAR3 FFF5 FFFFF5 ID Register IDR DSP56311 User s Manual Rev 2 B 2 Freescale Semiconductor Internal I O Memory Map Table B 2 Internal I O Memory Map Continued X Data Memory Peripheral 16 Bit Address 24
88. The boot program concatenates every 3 bytes read from the SCI into a 24 bit wide DSP56311 word B 1 0 1 1 FF0000 Reserved C 1 1 0 0 FF0000 HI08 bootstrap in ISA DSP563xx mode The HI08 is configured to interface with an ISA bus or with the memory expansion port of a master DSP563xx processor through the HI08 The HI08 pin configuration is optimized for connection to the ISA bus or memory expansion port of a master DSP based on the DSP56300 core D 1 1 0 1 FF0000 HI08 bootstrap in HC11 nonmultiplexed mode The bootstrap program sets the host interface to interface with the Motorola HC11 microcontroller through the HI08 The HI08 pin configuration is optimized for connection to the Motorola HC11 nonmultiplexed bus E 1 1 1 0 FF0000 HI08 bootstrap in 8051 multiplexed bus mode The bootstrap program sets the host interface to interface with the Intel 8051 bus through the HI08 The program stored in this location after testing MODA MODB MODC and MODD bootstraps through HI08 The HIO8 pin configuration is optimized for connection to the Intel 8051 multiplexed bus F 1 1 1 1 FF0000 HI08 bootstrap in MC68302 bus mode The bootstrap program sets the host interface to interface with the Motorola MC68302 or MC68360 bus through the HI08 The HIO8 pin configuration is optimized for connection to a Motorola MC68302 or MC68360 bus DSP56311 User s Manual Rev 2 Freescale Semiconductor 4 3
89. VBA 24 0 2 TIMER 0 compare VBA 26 0 2 TIMER 0 overflow VBA 28 0 2 TIMER 1 compare VBA 2A 0 2 TIMER 1 overflow VBA 2C 0 2 TIMER 2 compare VBA 2E 0 2 TIMER 2 overflow VBA 30 0 2 ESSIO receive data VBA 32 0 2 ESSIO receive data with exception status VBA 34 0 2 ESSIO receive last slot VBA 36 0 2 ESSIO transmit data VBA 38 0 2 ESSIO transmit data with exception status VBA 3A 0 2 ESSIO transmit last slot VBA 3C 0 2 Reserved VBA 3E 0 2 Reserved 4 16 DSP56311 User s Manual Rev 2 Freescale Semiconductor Configuring Interrupts Table 4 5 Interrupt Sources Continued Interrupt priority Level Starting Address Range Interrupt Source VBA 40 0 2 ESSI1 receive data VBA 42 0 2 ESSI1 receive data with exception status VBA 44 0 2 ESSI1 receive last slot VBA 46 0 2 ESSI1 transmit data VBA 48 0 2 ESSI1 transmit data with exception status VBA 4A 0 2 ESSI1 transmit last slot VBA 4C 0 2 Reserved VBA 4E 0 2 Reserved VBA 50 0 2 SCI receive data VBA 52 0 2 SCI receive data with exception status VBA 54 0 2 SCI transmit data VBA 56 0 2 SCI idle line VBA 58 0 2 SCI timer VBA 5A 0 2 Reserved VBA 5C 0 2 Reserved VBA 5E 0 2 Reserved VBA 60 0 2 Host receive data full VBA 62 0 2 Host transmit data empty VBA 64 0 2 Host command default VBA 66 0 2 Reserved VBA 68 0 2 EFCOP Data Input Buffer Empty VBA 6A 0 2 EFCOP Data Output Buffer F
90. a 1 to O edge on TIO loads the counter and a 0 to 1 edge on TIO stops the counter and loads TCR with the count Figure 9 12 Pulse Width Measurement Mode TRM 0 9 3 2 2 Measurement Input Period Mode 5 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 1 0 1 5 Input period Measurement Input Internal In Mode 5 the timer counts the period between the reception of signal edges of the same polarity across the TIO signal The value of the INV bit determines whether the period is measured between consecutive low to high 0 to 1 transitions of TIO or between consecutive high to low 1 to 0 transitions of TIO If INV is set high to low signal transitions are selected If INV is cleared low to high signal transitions are selected After the first appropriate transition occurs on the TIO input signal the counter is loaded with the TLR value On the next signal transition of the same polarity that occurs on TIO TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set The contents of the counter load into the TCR The TCR then contains the value of the time that elapsed between the two signal transitions on the TIO signal After the second signal transition if the TCSR TRM bit is set the TCSR TE bit is set to clear the counter and enable the timer The counter is repeatedly loaded and incremented until the timer is disabled If the TCSR TRM bit i
91. a software RESET instruction clears all PRRE bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRRE2 PRRE1 PRREO Note For bits 2 0 a O configures PEn as a GPI and a 1 configures PEn as a GPO For the SCI the GPIO signals are PE 2 0 The corresponding direction bits for Port E GPIOs are PRRE 2 0 Reserved Read as zero Write with zero for future compatibility Figure 8 9 Port E Direction Register PRRE X FFFF9E 8 7 3 Port E Data Register PDRE Bits 2 0 of the read write 24 bit PDRE writes data to or reads data from the associated SCI signal lines when configured as GPIO signals If a port signal PE 1 is configured as an input GPT the corresponding PDRE i bit reflects the value present on the input signal line If a port signal PE 1 is configured as an output GPO a value written to the corresponding PDRET i bit is reflected as a value on the output signal line Either a hardware RESET signal or a software RESET instruction clears all PDR bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PDRE2 PDRE1 PDREO Note For bits 2 0 the value represents the level that is written to or read from the associated signal line if enabled as a GPIO signal by the PCRE bits For SCI the GPIO signals are PE 2 0 The corresponding data bits are PDRE 2 0 Reserved Read a
92. all modes of operation To ensure that all DMA triggers are serviced provide for the preceding DMA trigger to be serviced before the DMA channel receives the next trigger 9 4 Triple Timer Module Programming Model The timer programming model in Figure 9 20 shows the structure of the timer registers 9 4 1 Prescaler Counter The prescaler counter is a 21 bit counter that decrements on the rising edge of the prescaler input clock The counter is enabled when at least one of the three timers is enabled that is one or more of the timer enable bits are set and is using the prescaler output as its source that is one or more of the PCE bits are set DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 21 Triple Timer Module 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Poe o o om Ben nw 7 6 5 4 3 2 1 0 i CORE te as Reserved bit Read as 0 Write with O for future compatibility Timer Prescaler Load Register TPLR TPLR FFFF83 Timer Prescaler Count Register TPCR TPLR FFFF82 Timer Control Status Register TCSR TCSRO FFFF8F TCSR1 FFFF8B TCSR2 FFFF87 Timer Load Register TLR TLRO FFFF8E TLR1 FFFF8A TLR2 FFFF86 Timer Compare Register TCPR TCPRO FFFF8D TCPR1 FFFF89 TCPR2 FFFF85 Timer Count Register TCR TCRO FFFF8C TCR1 FFFF88 TCR2 FFFF84 Figure 9 20 Timer Module Programming Model 9 4 2 Timer Prescaler Load Register TPLR The TPLR is a
93. and Mode Control oooocococccco cee eee eens PHOS 000 See ied eas br rar is Enhanced Synchronous Serial Interface O 0 cece een ee Enhanced Synchronous Serial Interface 1 ooo ooooooconcococoooorr SCE ect yeaah oS eye mae eee ama anne ai Mike a ee a ads ATMO ES te a dada queda de dl bere tre ll bbs DSP56311 User s Manual Rev 2 Freescale Semiconductor Contents 2 12 3 3 1 3 1 1 3 1 2 3 1 3 3 1 4 3 2 3 2 1 3 2 2 3 2 3 3 3 3 3 1 3 3 2 3 3 3 3 3 4 3 4 3 5 3 6 4 1 4 2 4 3 4 3 1 4 3 2 4 4 4 4 1 4 4 2 4 4 3 4 5 4 6 4 6 1 4 6 2 4 6 3 4 7 4 8 4 9 4 10 5 1 5 2 5 3 5 4 5 4 1 5 4 2 vi JTAG and OnCE Interface cc eee ec eee eee eee eens 2 19 Memory Configuration Program Memory Space iii a e ao ed dedi abu ae own 3 1 Internal Program Memory nis minnie iia AA a e ene n en ene 3 2 Memory Switch Modes Program Memory 0 00 cece eee e tenes 3 2 Instruction Cache x ita tt a egos eee ok wai ee eked Pee Ae ea esa 3 3 Program Bootstrap ROM ed eea cece cece een nent ene nee 3 3 X Data Memory Space cia e estes A Geostand dens asda aoe 3 3 Internal X Data Memory o 3 4 Memory Switch Modes X Data Memory 0 cece eee eee eens 3 4 Int rnal X VO Space ii dare eee ag ee eae eee ee 3 5 Y Data Memory Space omiso an senna reyes Sb Majeh pi a 3 5 Internal Y Data Memory cionado a dd ai 3 5 Memory Switch Modes Y Data Memory 0 ce
94. and the count is resumed If the TCSR TRM bit is cleared the counter continues to increment on each timer clock This process repeats until the timer is disabled Mode 3 internal clock TRM 1 N write preload first event M write compare 4 TE if clock source is from TIO pin Clock LN TIO lt CPUCLK 4 TIO pin or prescale CLK TLR SON lt RDP N X _ N 1 X M XN TCPR lt M interrupts every TCF Compare Interrupt if TCIE 1 ee _ periods NOTE If INV 1 counter is clocked on 1 to 0 clock transitions instead of 0 to 1 transitions Figure 9 9 Event Counter Mode TRM 1 DSP56311 User s Manual Rev 2 9 10 Freescale Semiconductor Operating Modes Mode ds TEM 0 if clock source is from TIO pin N write preload first event TIO lt CPUCLK 4 M write compare y TE 4 Clock P TIO pin or prescale CLK TLR Counter TCR TCPR TCF Compare Interrupt if TCIE 1 ol o N TOF Overflow Interrupt if TCIE 1 a NOTE If INV 1 counter is clocked on 1 to 0 clock transitions instead of 0 to 1 transitions Figure 9 10 Event Counter Mode TRM 0 9 3 2 Signal Measurement Modes The following signal measurement and pulse width modulation modes are provided E Measurement input width Mode 4 E Measurement input period Mode 5 E Measurement capture Mode 6 E Pulse width modulation PWM m
95. both cleared then the SCI clock is divided by 16 before being output to the SCLK signal Thus the SCLK output is a 1 X clock e If COD is set and SCLK is an output the SCI clock is fed directly out to the SCLK signal Thus the SCLK output is a 16 X baud clock 11 0 CD 1 1 0 Clock Divider Specifies the divide ratio of the prescale divider in the SCI clock generator A divide ratio from 1 to 4096 CD 1 1 0 000 to FFF can be selected Freescale Semiconductor DSP56311 User s Manual Rev 2 8 17 Serial Communication Interface SCI The SCI clock determines the data transmission baud rate and can also establish a periodic interrupt that can act as an event timer or be used in any other timing function Bits CD11 CDO SCP and SCR STIR work together to determine the time base If SCR TMIE 1 when the periodic time out occurs the SCI timer interrupt is recognized and pending The SCI timer interrupt is automatically cleared when the interrupt is serviced This interrupt occurs every time the periodic timer times out Figure 8 5 shows the block diagram of the internal clock generation circuitry with the formula to compute the bit rate when the internal clock is used Poore Divide 12 bit Counter CD 11 0 Prescaler Divide by 1o0r8 Internal Clock Divide SCI Core Logic by 16 Uses Divide by 16 for Asynchronous Uses Divide by 2 for STIR Synchronous If Asynchronous
96. can be viewed as three types of registers E Control SCI Control Register SCR in Figure 8 3 SCI Clock Control Register SCCR in Figure 8 4 E Status SCI Status Register SSR in Figure 8 3 E Data transfer 8 8 SCI Receive Data Registers SRX in Figure 8 7 SCI Transmit Data Registers STX in Figure 8 7 DSP56311 User s Manual Rev 2 Freescale Semiconductor SCI Programming Model SCI Transmit Data Address Register STXA in Figure 8 7 The SCI includes the GPIO functions described in Section 8 7 GPIO Signals and Registers on page 8 22 The next subsections describe the registers and their bits Mode 0 8 bit Synchronous Data Shift Register Mode WDS2 WDS1 WDSO TA D7 D5 D4 D3 D D SSFTD 1 One Byte From Shift Register gt p30 ate Hh eeu 10 bit Asynchronous 1 Start 8 Data 1 Stop WDS2 WDS1 WDSO TX SSFTD 1 TX SSFTD 1 Data Type b Z Roe e Modes 1 3 and 7 are reserved y DO LSB D7 MSB Data is transmitted and received LSB first if SSFTD 0 or MSB first if SSFTD 1 Figure 8 1 SCI Data Word Formats SSFTD 1 1 DSP56311 User s Manual Rev 2 8 9 Freescale Semiconductor Serial Communication Interface SCI Mode 0 Eg 8 bit Synchronous Data Shift Register Mode WDS2 WDS1 WDSO wo epele eee e One Byte From Shift Register gt ojij 0s 1 10 bit Asynchronous 1 Start 8 Data
97. control the GPIO functionality of the SCI pins Port E control register PCRE Port E direction register PRRE and Port E data register PDRE 8 7 1 Port E Control Register PCRE The read write PCRE controls the functionality of SCI GPIO signals Each of the PCRE 2 0 bits controls the functionality of the corresponding port signal When a PCRE i bit is set the corresponding port signal is configured as an SCI signal When a PC i bit is cleared the corresponding port signal is configured as a GPIO signal A hardware RESET signal or a software RESET instruction clears all PCRE bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PE2 PE1 PEO SCLK TXD RXD Note For bits 2 0 a O selects PEn as the signal and a 1 selects the specified SCI signal Reserved Read as zero Write to zero for future compatibility Figure 8 8 Port E Control Register PCRE X FFFF9F DSP56311 User s Manual Rev 2 8 22 Freescale Semiconductor GPIO Signals and Registers 8 7 2 Port E Direction Register PRRE The read write PRRE controls the direction of SCI GPIO signals When port signal 1 is configured as GPIO PRRE i controls the port signal direction When PRRE i is set the GPIO port signal i is configured as output When PRRE i is cleared the GPIO port signal 1 is configured as input A hardware RESET signal or
98. data signal 2 TOD Transmitter O drive enable if SSC1 1 amp SCD1 1 RD Receive data FO Flag 0 F1 Flag1ifSSC1 0 U Unused can be used as GPIO signal X Indeterminate When configured as an output SC1 functions as a serial Output Flag as the transmitter 0 drive enabled signal or as the receive frame sync signal output If SC1 is used as serial Output Flag 1 its value is determined by the value of the serial Output Flag 1 OF1 bit in the CRB When configured as an input this signal can receive frame sync signals from an external source or it acts as a serial input flag As a serial input flag SCl controls status bit IF1 in the SSISR When SC1 is configured as a transmit data signal it is always an output signal regardless of the SCD1 bit value As an output it is fully synchronized with the other ESSI transmit data signals STD and SCO SC1 can be programmed as a GPIO signal P1 when the ESSI SC1 function is not in use 7 2 6 Serial Control Signal SC2 ESSI0 SC02 ESSI1 SC12 SC2 is a frame sync I O signal for both the transmitter and receiver in Synchronous mode and for the transmitter only in Asynchronous mode The direction of this signal is determined by the SCD2 bit in the CRB When configured as an output this signal outputs the internally generated frame sync signal When configured as an input this signal receives an external frame sync signal for the transmitter in Asynchronous mode and for both t
99. disabled 21 19 DTM 2 0 0 DMA Transfer Mode Specify the operating modes of the DMA channel as follows DE DTM 2 0 Trigger Cleared Transfer Mode After 000 request Yes Block Transfer DE enabled and DMA request initiated The transfer is complete when the counter decrements to zero and the DMA controller reloads the counter with the original value 001 request Yes Word Transfer A word by word block transfer length set by the counter that is DE enabled The transfer is complete when the counter decrements to zero and the DMA controller reloads the counter with the original value 010 request Yes Line Transfer A line by line block transfer length set by the counter that is DE enabled The transfer is complete when the counter decrements to zero and the DMA controller reloads the counter with the original value 011 DE Yes Block Transfer The DE initiated transfer is complete when the counter decrements to zero and the DMA controller reloads the counter with the original value 100 request No Block Transfer The transfer is enabled by DE and initiated by the first DMA request The transfer is completed when the counter decrements to zero and reloads itself with the original value The DE bit is not cleared at the end of the block so the DMA channel waits for a new request Note The DMA End of Block Transfer Interrupt cannot be used in this mode 101 request No Word Transfer The t
100. eight MSBs of the destination LA LC SP SSL SSH EP SZ VBA and SC If the source is either the SR or OMAR then the eight MSBs of the destination are also cleared If the destination is either the SR or OMR then the eight MSBs of the destination are left unchanged To change the value of one of the eight MSBs of the SR or OMR clear SC SC also affects the contents of the Loop Counter Register If SC is cleared normal operation then a loop count value of zero causes the loop body to be skipped and a loop count value of F FFFFF causes the loop to execute the maximum number of 224 1 times If the SC bit is set a loop count value of zero causes the loop to execute 21 times and a loop count value of F FFFFF causes the loop to execute 2 6 1 times Note Due to pipelining a change in the SC bit takes effect only after three instruction cycles Insert three NOP instructions after the instruction that changes the value of this bit to ensure proper operation 12 0 Reserved Write to 0 for future compatibility 11 10 S 1 0 0 Scaling Mode Specify the scaling to be performed in the Data ALU shifter limiter and the rounding position in the Data ALU MAC unit The Shifter limiter Scaling mode affects data read from the A or B accumulator registers out to the X data bus XDB and Y data bus YDB Different scaling modes can be used with the same program code to allow dynamic scaling One application of dynamic scaling is to fac
101. enable the timer Clearing TCSR TE disables the timer E The value to which the timer is to count is loaded into the TCPR This is true for all modes except the measurement modes modes 4 through 6 E The counter is loaded with the TLR value on the first clock E Ifthe counter overflows TCSR TOF is set and if TCSR TOIE is set an overflow interrupt is generated E You can read the counter contents at any time from the Timer Count Register TCR 9 3 1 1 Timer GPIO Mode 0 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 0 0 0 0 GPIO Timer GPIO Internal In Mode 0 the timer generates an internal interrupt when a counter value is reached if the timer compare interrupt is enabled see Figure 9 3 and Figure 9 4 When the counter equals the TCPR value TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is Freescale Semiconductor DSP56311 User s Manual Rev 2 9 5 Triple Timer Module set If the TCSR TRM bit is set the counter is reloaded with the TLR value at the next timer clock and the count is resumed If TCSR TRM is cleared the counter continues to increment on each timer clock signal This process repeats until the timer is disabled Mode 0 internal clock no timer output TRM 1 N write preload first event last event M write compare TE Clock CLK 2 or prescale CLK TLR Counter TCR
102. exception interrupt ESSIO RX data interrupt ESSIO receive last slot interrupt ESSIO TX data with exception interrupt ESSIO transmit last slot interrupt ESSIO TX data interrupt ESSI1 RX data with exception interrupt ESSI1 RX data interrupt ESSI1 receive last slot interrupt ESSI1 TX data with exception interrupt ESSI1 transmit last slot interrupt ESSI1 TX data interrupt SCI receive data with exception interrupt 4 18 DSP56311 User s Manual Rev 2 Freescale Semiconductor PLL Control Register PCTL Table 4 6 Interrupt Source Priorities Within an IPL Continued Priority Interrupt Source SCI receive data SCI transmit data SCI idle line SCI timer TIMERO overflow interrupt TIMERO compare interrupt TIMER1 overflow interrupt TIMER1 compare interrupt TIMER2 overflow interrupt TIMER2 compare interrupt EFCOP Data Input Buffer Empty Lowest EFCOP Data Output Buffer Full 4 5 PLL Control Register PCTL The bootstrap program must initialize the system Phase Lock Loop PLL circuit by configuring the PLL Control Register PCTL The PCTL is an X I O mapped read write register that directs the on chip PLL operation See Figure 4 5 23 22 21 20 19 18 17 16 15 14 13 12 PD3 PD2 PD1 PDO COD PEN PSTP XTLD XTLR DF2 DF1 DFO
103. for each idle state no matter how long the idle state lasts TE Transmitter Enable When TE is set the transmitter is enabled When TE is cleared the transmitter completes transmission of data in the SCI transmit data shift register and then the serial output is forced high that is idle Data present in the SCI transmit data register STX is not transmitted STX can be written and TDRE cleared but the data is not transferred into the shift register TE does not inhibit TDRE or transmit interrupts Either a hardware RESET signal or a software RESET instruction clears TE Setting TE causes the transmitter to send a preamble of 10 or 11 consecutive ones depending on WDS giving you a convenient way to ensure that the line goes idle before a new message starts To force this separation of messages by the minimum idle line time we recommend the following sequence 1 Write the last byte of the first message to STX 2 Wait for TDRE to go high indicating the last byte has been transferred to the transmit shift register 3 Clear TE and set TE to queue an idle line preamble to follow immediately the transmission of the last character of the message including the stop bit 4 Write the first byte of the second message to STX If the first byte of the second message is not transferred to STX prior to the finish of the preamble transmission the transmit data line remains idle until STX is finally written DSP5631
104. has no ning in non multiplexed bus t GPIO pins are disabled following conditions Negative host acknowledge Negative host request Negative chip select input Dual strobes bus RD and WR tiplexed bus Positive address strobe polarity Negative data strobes polarity t request is active when enabled This bit should be set to 0 for future compatability whe HEN n the HPCR register is modified should be cleared t acknowledge is disabled t requests are enabled t chip select input enabled Enable address 9 input Enable address 8 input Configure HAP 0 HRP 0 HCSP 0 HD HS 1 HMUX 1 HASP 1 HDSP 0 HROD 0 spare 0 HEN O HAEN 0 HREN 1 HCSEN 1 HA9EN HA8EN HGEN 0 t GPIO pins are disabled Enable the HI08 to operate as host interface set HEN 1 wait for the program length to be written wait for the program starting address to be written set a loop with the downloaded length DSP56311 User s Manual Rev 2 Freescale Semiconductor Bootstrap Code HIO8LL jset HRDF x M_HSR HIO8NW If new word was loaded then jump to read that word ear HFO x M_HSR HIO8LL If HFO 0 then continue with the downloading enddo Must terminate the do loop bra lt HI08LOOP HIO8NW movep x M_HRX p r0 Move the new word into its destination location in the program RAM nop pipeline delay HIO8LOOP bra lt F
105. host processor to read or write DSP registers X Y or program memory locations force interrupt handlers for example ESSI SCI IRQA IRQB interrupt routines and perform control or debugging operations Note When the DSP enters Stop mode the HI08 signals are electrically disconnected internally thus disabling the HIOS until the core leaves stop mode While the HIOS configuration remains unchanged in Stop mode the core cannot be restarted via the HIOS interface Do not issue a STOP command to the DSP via the HIO8 unless you provide some other mechanism to exit stop mode Table 6 14 Host Side Register Map Host Address Big Endian HLEND 0 Little Endian HLEND 1 Register Name 0 ICR ICR Interface Control 1 CVR CVR Command Vector 2 ISR ISR Interface Status 3 IVR IVR Interrupt Vector 4 00000000 00000000 Unused 5 RXH TXH RXL TXL 6 RXM TXM RXM TXM Saal acl 7 RXL TXL RXH TXH 6 7 1 Interface Control Register ICR The ICR is an 8 bit read write control register by which the host processor controls the HIOS interrupts and flags The DSP core cannot access the ICR The ICR is a read write register which allows the use of bit manipulation instructions on control register bits Hardware and software reset clear the ICR bits DSP56311 User s Manual Rev 2 6 22 Freescale Semiconductor Host Programmer Model 5 4 3 2 1 0 INIT HLEND HF1 HFO HDRQ TREQ RREQ
106. individual and stop resets 6 7 3 Interface Status Register ISR The host processor uses the ISR an 8 bit read only status register to interrogate the HIOS status and flags The DSP core cannot address the ISR 7 6 5 4 3 2 1 0 HREQ HF3 HF2 TRDY TXDE RXDF Reserved bit read as 0 write to O for future compatibility Figure 6 17 Interface Status Register ISR DSP56311 User s Manual Rev 2 Freescale Semiconductor 6 25 Host Interface HI08 Table 6 17 Interface Status Register ISR Bit Definitions Bit Number Bit Name Reset Value Description 7 HREQ O Hardware and Software reset 1 Individual reset and TREQ is set 1 Stop reset and TREQ is set Host Request If HDRQ is set the HREQ bit indicates the status of the external transmit and receive request output signals HTRQ and HRRQ If HDRQ is cleared HREQ indicates the status of the external host request output signal HREQ The HREQ bit is set from either or both of two conditions the receive byte registers are full or the transmit byte registers are empty These conditions are indicated by status bits ISR RXDF indicates that the receive byte registers are full and ISR TXDE indicates that the transmit byte registers are empty If the interrupt source is enabled by the associated request enable bit in the ICR HREQ is set if one or more of the two enabled inte
107. instructions and moves are performed accordingly For details on Sixteen Bit Arithmetic mode consult the DSP56300 Family Manual 4 6 DSP56311 User s Manual Rev 2 Freescale Semiconductor Central Processor Unit CPU Registers Table 4 2 Status Register Bit Definitions Continued Bit Number Bit Name Reset Value Description 16 FV 0 DO FOREVER Flag Set when a DO FOREVER loop executes The FV flag like the LF flag is restored from the stack when a DO FOREVER loop terminates Stacking and restoring the FV flag when initiating and exiting a DO FOREVER loop respectively allow program loops to be nested When returning from the long interrupt with an RTI instruction the system stack is pulled and the value of the FV bit is restored 15 LF Do Loop Flag When a program loop is in progress enables the detection of the end of the loop The LF is restored from stack when a program loop terminates Stacking and restoring the LF when initiating and exiting a program loop respectively allow program loops to be nested When returning from the long interrupt with an RTI instruction the System Stack is pulled and the LF bit value is restored 14 DM Double Precision Multiply Mode Enables four multiply MAC operations to implement a double precision algorithm that multiplies two 48 bit operands with a 96 bit result Clearing the DM bit disables the mode Note The Double Pr
108. interrupt trigger a Enable and prioritize overall peripheral interrupt functionality IPRP TOL 1 0 Enable a specific peripheral interrupt TCSRO TCIE Unmask interrupts at the global level SR I 1 0 Configure a peripheral interrupt generating function TCSRO TC 7 4 Enable peripheral and associated signals TCSRO TE DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 3 Operating Modes Operating Modes Each timer has operating modes that meet a variety of system requirements as follows E Timer GPIO mode 0 Internal timer interrupt generated by the internal clock Pulse mode 1 External timer pulse generated by the internal clock Toggle mode 2 Output timing signal toggled by the internal clock Event counter mode 3 Internal timer interrupt generated by an external clock E Measurement Input width mode 4 Input pulse width measurement Input period mode 5 Input signal period measurement Capture mode 6 Capture external signal E PWM mode 7 Pulse width modulation E Watchdog Pulse mode 9 Output pulse internal clock Toggle mode 10 Output toggle internal clock Note 9 3 1 Triple Timer Modes To ensure proper operation the TCSR TC 3 0 bits should be changed only when the timer is disabled that is when TCSR TE is cleared For all triple timer modes the following points are true E The TCSR TE bit is set to clear the counter and
109. is lost Therefore you must connect an external pull up resistor to these pins In this case BME 0 the DSP DRAM controller assumes a page fault each time the mastership is lost A DRAM refresh requires a bus mastership If the BME bit is set the RAS and CAS pins are always driven from the DSP Therefore DRAM refresh can be performed even if the DSP is not the bus master 11 BPLE 0 Bus Page Logic Enable Enables disables the in page identifying logic When BPLE is set it enables the page logic the page size is defined by BPS 1 0 bits Each in page identification causes the DRAM controller to drive only the column address and the associated CAS signal When BPLE is cleared the page logic is disabled and the DRAM controller always accesses the external DRAM in out of page accesses for example row address with RAS assertion and then column address with CAS assertion This mode is useful for low power dissipation Only one in page identifying logic exists Therefore during switches from one DRAM external bank to another DRAM bank the DRAM external banks are defined by the access type bits in the AARs different external banks are accessed through different AA RAS pins a page fault occurs 10 0 Reserved Write to zero for future compatibility 9 8 BPS 1 0 0 Bus DRAM Page Size Defines the size of the external DRAM page and thus the number of the column address bits The internal page mechanism works according to these bits
110. it checks the MODD MODC MODB and MODA pins and sets the corresponding mode bits in the Operating Mode Register OMR If the mode bits are write to 0010 or 1010 respectively the DSP loads the program RAM from the SCI Appendix A Bootstrap Program shows the complete bootstrap code This program performs the following steps 1 Configures the SCI 2 Loads the program size 3 Loads the location where the program begins loading in program memory 4 Loads the program First the SCI Control Register is set to 000302 which enables the transmitter and receiver and configures the SCI for 10 bits asynchronous with one start bit 8 data bits one stop bit and no parity Next the SCI Clock Control Register is set to 00C000 which configures the SCI to use external receive and transmit clocks from the SCLK pin input This external clock must be 16 times the desired serial data rate The next step is to receive the program size and then the starting address to load the program These two numbers are three bytes each loaded least significant byte first Each byte is echoed DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 7 Serial Communication Interface SCI back as it is received After both numbers are loaded the program size is in AO and the starting address is in Al The program is then loaded one byte at a time least significant byte first After the program is loaded the operating mode is set to zero the CCR is cleare
111. its external address space The DSP side registers appear to the DSP core as six 24 bit registers mapped into internal I O X memory space and therefore accessible via standard DSP56300 instructions and addressing modes DSP Side Registers Control Registers Data Registers HCR Host Control Register HSR Host Status Register HPCR Host Port Control Register HTX Host Transmit Register HRX Host Receive Register HDDR Host Data Direction Register HBAR Host Base Address Register HDR Host Data Register Core DMA Data Bus DSP Peripheral Data Bus ae 24 24 24 24 24 24 24 24 24 24 HCR HSR HDDR HDR HBAR HPCR HTX HRX DSP Side A k oN 1 US an a A E 4 1 o 1 I l 1 2 1 y l Address l 24 24 poi E TN 1 Comparator 2ra i l 3 ALU Se 1 ye i E 1 1 34 Host y Latch RXH RXM RXL TXH o a Side l I 8 8 8 8 HOST Bus Host Side Registers Control Registers Data Registers ISR Interface Status Register ICR Interface Control Register CVR Command Vector Register IVR Interrupt Vector Register RXH Receive Register High RXM Receive Register Middle RXL Receive Register Low TXH Transmit Register High TXM Transmit Register Middle TXL Transmit Register Low Figure 6 1 HI08 Block Diagram DSP56311 User s Manual Rev 2 6 4 Freescale Semiconductor Operation In GPIO mode two additional registers HDDR and HDR are related to the HIO8 peripheral The separate receive a
112. move FDBA_ADDRS r0 FDM memory area move 0 x0 rep DST_COUNT movex0 x r0 clear FDM memory area move DST_ADDRS r0 Destination address EFCOP initialization DSP56311 Reference Manual Rev 2 10 22 Freescale Semiconductor a EFCOP Operation movep FIR_LEN 1 y M_FCNT FIR length movep FDBA_ADDRS y M_FDBA FIR input samples Start Address movep FCBA_ADDRS y M_FCBA FIR Coeff Start Address movep FCON y M_FCSR Enable EFCOP DMA channel 0 initialization input to EFCOP movep SRC_ADDRS x M_DSRO DMA source address points to the DATA bank movep M_FDIR x M_DDRO Init DMA destination address movep SRC_COUNT x M_DCOO Init DMA count to line mode movep 1 x M_DORO DMA offset reg is 1 movep S940A04 x M_DCRO Init DMA control reg to line mode FDIBE request nop nop KKK KEK KKK KKK KKK KEK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KEK KKK KKK KKK KKK KARA at waitl jset 11 y M_FCSR Wait until FDOIE is cleared do 40 endd nop endd nop nop stop_label nop jmp stop_label KKK KEK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KEKEK at kdo Interrupt handler for EFCOP output movep y M_FDOR x r0 Get y k from FDOR Store in destination memory space nop dec b jne cont nop belr 11 y M_FCSR Disable outpu
113. r2 address of external EPROM aarl configured for SRAM types of access read number of words and starting address Get the 8 LSB from ext P mem Shift 8 bit data into Al _ LOOPY i move al r0 starting address for load move al rl Save it in rl a0 holds the number of words do a0 _LOOP10 read program words do 3 _LOOP11 Each instruction has 3 bytes movem p r2 a2 Get the 8 LSB from ext P mem asr 8 a a Shift 8 bit data into A1 _LOOP11 Go get another byte movem al p r0 Store 24 bit result in P mem nop pipeline delay _LOOP10 and go get another 24 bit word Boot from EPROM done FINISH This is the exit handler that returns execution to normal expanded mode and jumps to the RESET vector andi 0 ccr jmp r1 Clear CCR as if RESET to 0 Then go to starting Prog addr The following modes are reserved some of which are used for internal testing Can be implemented in future OMROXXX jclr 2 omr RESERVED jclr 1 omr RESERVE jclr 0 omr RESERVE O O bra lt end A 2 Internal I O Equates MD MC MB MA 00xx is reserved MD MC MB MA 010x is reserved MD MC MB MA 0110 is reserved MD MC MB MA 0111 is reserved E K K E K K K K K E K K K K k K K K K K K K k K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K gt E EQUATES for DSP56311 I O registers and ports
114. shift register and word length divider The internal clock is output on the SCK signal When SCKD is cleared the external clock source is selected The internal clock generator is disconnected from the SCK signal and an external clock source may drive this signal SCD2 Serial Control Direction 2 Controls the direction of the SC2 I O signal When SCD2 is set SC2 is an output when SCD2 is cleared SC2 is an input Note Programming the ESSI to use an internal frame sync that is SCD2 1 in CRB causes the SC2 and SC1 signals to be programmed as outputs However if the corresponding multiplexed pins are programmed by the Port Control Register PCR to be GPIOs the GPIO Port Direction Register PRR chooses their direction The ESSI uses an external frame sync if GPIO is selected To assure correct operation either program the GPIO pins as outputs or configure the pins in the PCR as ESSI signals The default selection for these signals after reset is GPIO This note applies to both ESSIO and ESSI1 Freescale Semiconductor DSP56311 User s Manual Rev 2 7 21 Enhanced Synchronous Serial Interface ESSI Table 7 4 ESSI Control Register B CRB Bit Definitions Continued Bit Number Bit Name Reset Value Description 3 SCD1 0 Serial Control Direction 1 In Synchronous mode SYN 1 when transmitter 2 is disabled TE2 0 or in Asynchronous mode SYN 0 SCD1 controls the dire
115. shifted in and transferred to the ESSI receive data register RE must be set in both Normal and On Demand modes for the ESSI to receive data In Network mode clearing RE and setting it again disables the receiver after reception of the current data word The receiver remains disabled until the beginning of the next data frame Note The setting of the RE bit does not affect the generation of a frame sync 16 TEO 0 Transmit 0 Enable Enables the transfer of data from TXO to Transmit Shift Register 0 TEO is functional when the ESSI is in either synchronous or Asynchronous mode When TEO is set and a frame sync is detected the transmitter O is enabled for that frame When TEO is cleared transmitter 0 is disabled after the transmission of data currently in the ESSI transmit shift register The STD output is tri stated and any data present in TXO is not transmitted In other words data can be written to TXO with TEO cleared the TDE bit is cleared but data is not transferred to the transmit shift register O The transmit enable sequence in On Demand mode can be the same as in Normal mode or TEO can be left enabled Note Transmitter 0 is the only transmitter that can operate in Asynchronous mode SYN 0 The setting of the TEO bit does not affect the generation of frame sync or output flags 15 TE1 0 Transmit 1 Enable Enables the transfer of data from TX1 to Transmit Shift Register 1 TE1 is functional only when the ESSI is i
116. term for any pin on the chip 2 Ground is an acceptable low voltage level See the appropriate data sheet for the range of acceptable low voltage levels typically a TTL logic low 3 Voc is an acceptable high voltage level See the appropriate data sheet for the range of acceptable high voltage levels typically a TTL logic high E Pins or signals that are asserted low made active when pulled to ground are indicated like this In text they have an overbar for example RESET is asserted low Incode examples they have a tilde in front of their names In Example 1 1 line 3 refers to the SSO signal shown as SS0 E Sets of signals are indicated by the first and last signals in the set for instance HAD 0 7 E Input Output indicates a bidirectional signal Input or Output indicates a signal that is exclusively one or the other E Code examples are displayed in a monospaced font as shown in Example 1 1 Example 1 1 Sample Code Listing BFSET 0007 X PCC Configure line 1 MISOO MOSIO SCKO for SPI master line 2 SSO as PC3 for GPIO line 3 E Hexadecimal values are indicated with a preceding the value as follows FFFFFF is the X memory address for the core interrupt priority register E The word reset is used in four different contexts in this manual the reset signal written as RESET the reset instruction written as RESET the reset operating state writt
117. to Compare Bits 11 8 BNC 3 0 number of bits from BAC bits that are Combinations BNC 3 0 1111 1110 1101 are 1 Enable internal packing unpacking logic Bus Y Data Memory Enable Bit 5 0 Disable AA pin and logic during external Y data space accesses 1 Enable AA pin and logic during external Y data space accesses Bus X Data Memory Enable Bit 4 0 Disable AA pin and logic during external X data space accesses 1 Enable AA pin and logic during external X data space accesses Bus Program Memory Enable Bit 3 0 Disable AA pin and logic during external program space accesses 1 Enable AA pin and logic during external program space accesses Bus Address Attribute Polarity Bit 2 0 AA signal is active low 1 AA signal is active high Bus Access Type Bits 1 0 BAT 1 0 Encoding 00 Reserved 01 SRAM access 10 Reserved 11 Reserved 2507 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BACO BNC3 BNC2 BNC1 BNCO IR BYEN BXEN BPEN BAAP BAT1 BATO Address Attribute Registers 3 AAR3 Address Attribute Registers 2 AAR2 Address Attribute Registers 1 AAR1 Address Attribute Registers 0 AARO Reset 000000 X FFFFF6 Read Write X FFFFF7 Read Write X FFFFF8 Read Write X FFFFF9 Read Write k Reserved Program as 0 Figure B 8 Address Attribute
118. to begin output SRC_COUNT equ 006003 DMAO count 7 4 word transfers DST_COUNT equ 8 number of outputs generated FDBA_ADDRS equ 0 Input samples Start Address x 0 FCBA_ADDRS equ O Coeff Start Address y 0 KKK KKK KKK KKK KKK KEK KK KKK KKK RARA KKK KKK KKK KKK KKK KEK RRA RR RR AAA KAR RR at DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 19 EE a a Enhanced Filter Coprocessor Main program OO Se ee K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K K O OOOO 29 ORG p Start move 0 b move 0 a move HDST_COUNT b0 counter for output interrupt move FDBA_ADDRS r0 FDM memory area move 0 x0 rep DST_COUNT movex0 x r0 clear FDM memory area move DST_ADDRS r0 Destination address EFCOP initialization movep FIR_LEN 1 y M_FCNT FIR length movep FDBA_ADDRS y M_FDBA FIR input samples Start Address movep FCBA_ADDRS y M_FCBA FIR Coeff Start Address movep FCON y M_FCSR Enable EFCOP DMA channel 0 initialization input to EFCOP movep SRC_ADDRS x M_DSRO DMA source address points to the DATA bank movep M_FDIR x M_DDRO Init DMA destination address movep SRC_COUNT x M_DCOO Init DMA count to line mode movep 1 x M_DORO DMA offset reg is 1 movep S940AA04 x M_DCRO Init DMA control reg to line mode FDIBE request nop nop 7
119. transfer DSP56311 Reference Manual Rev 2 Freescale Semiconductor EFCOP Operation The filter coefficients are stored in reverse order as Figure 10 6 shows Output Data Stream F 0 Coefficient F 1 Memory F 2 Bank F 3 FCM F 4 _F S Figure 10 6 Real FIR Filter Data Stream Example 10 1 Real FIR Filter Using DMA Input DMA Output INCLUDE ioequ asm KKK KKK KKK KKK KKK KEK KKK KEK KKK KKK KKK KEK KKK KK KKK KKK KKK KKK KKK KEK KKK A KAR at equates AOA HARRI I IIIA RII AIR A RK AIR KI HR KRE RI AERA TK ISIE A RIAA RH IEA REA RK Ie Start equs00100 Main program starting address FCON equ 001 EFCOP FSCR register contents enable the EFCOP FIR_LEN equ 20 EFCOP FIR length SRC_ADDRS equ 3040 DMA source address point to DATA bank DST_ADDRS equ 3000 address at which to begin output SRC_COUNT equ 006003 DMAO count 7 4 word transfers DST_COUNT equ 8 number of outputs generated FDBA_ADDRS equ 0 Input samples Start Address x 0 FCBA_ADDRS equ 0 Coeff Start Address y 0 e KKK KEK KKK KKK KKK KEK KKK KEK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKKKKEEEK at Main program e KKK KEK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK RARA ARA RARA AAA at ORG p Start move FDBA_ADDRS r0 FDM memory area move 0 x0 rep DST_COUNT DSP56311 Reference Manual Rev 2
120. using either standard polled or interrupt programming techniques Separate double buffered transmit and receive data registers allow the DSP and host processor to transfer data efficiently at high speed Memory mapping allows you to program DSP core communication with the HIOS registers using standard instructions and addressing modes DSP56311 User s Manual Rev 2 1 12 Freescale Semiconductor Peripherals 1 9 3 ESSI The DSP56311 provides two independent and identical ESSIs Each ESST has a full duplex serial port for communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals that implement the Freescale SPI The ESSI consists of independent transmitter and receiver sections and a common ESSI clock generator ESSI capabilities include the following E Independent asynchronous or shared synchronous transmit and receive sections with separate or shared internal external clocks and frame syncs Normal mode operation using frame sync Network mode operation with as many as 32 time slots Programmable word length 8 12 or 16 bits Program options for frame synchronization and clock generation One receiver and three transmitters per ESSI 1 9 4 SCI The SCI provides a full duplex port for serial communication with other DSPs microprocessors or peripherals such as modems The SCI interfaces without additional logic to peripherals that use TTL level sig
121. wait states for each in page access DSP56311 User s Manual Rev 2 4 24 Freescale Semiconductor Bus Interface Unit BIU Registers 4 6 3 Address Attribute Registers AAR 0 3 The Address Attribute Registers AAR 0 3 are read write registers that control the activity of the AA0 RASO AA3 RAS3 pins The associated AAn RASn pin is asserted if the address defined by the BAC bits in the associated AAR matches the exact number of external address bits defined by the BNC bits and the external address space X data Y data or program is enabled by the AAR Figure 4 8 shows an AAR register Table 4 10 lists the bit definitions Note The DSP56311 does not support address multiplexing 23 22 21 20 19 18 17 16 15 14 13 12 BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BACO 11 10 9 8 7 6 5 4 3 2 1 0 BNC3 BNC2 BNC1 BNCO BPAC BYEN BXEN BPEN BAAP BAT1 BATO Reserved bit Read as zero write to zero for future compatibility Figure 4 8 Address Attribute Registers AAR O 3 X FFFFF9 SFFFFF6 Table 4 10 Address Attribute Registers AAR O 3 Bit Definitions Bit Reset oo Number Bit Name Value Description 23 12 BAC 11 0 0 Bus Address to Compare Read write control bits that define the upper 12 bits of the 24 bit address with which to compare the external address to determine whether to assert the correspon
122. 0 Internal O SFFFFCO FFFFFF FFFF80 FFFF80 Internal I O Reserved Internal Internal FFOOCO Reserved Reserved FF0000 Bootstrap ROMI se Eo 900 FF0000 sitea External External External 014000 Reserved 00C000 00C000 Internal Internal Program RAM 006000 Reserved 006000 Reserved 79K 000400 Internal X data Internal Y data goooooo Reserved 000000 RAM24K go00000 RAM 24K Bit Settings Memory Configuration ms MSW ce sc Program RAM XData RAM YDataRAM Cache Addressable 1 0 Memory Size 1 01 1 0 79K 24K 24K Enabled 16M 0400 0000 5FFF 0000 5FFF 13FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 6 Memory Switch On MSW 01 Cache On 24 Bit Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor Memory Maps Program X Data Y Data FFFFFF FFFFFF FFFFFF External I O Internal O SFFFFCO FFFF80 FFFF80 Internal I O Internal FFF000 FFFO00 __Exteral Reserved Internal Internal FFOOCO Reserved Reserved FF0000 Bootstrap ROM FF0000 FF0000 Seo External External External 010000 Reserved 00C000 00C000 Internal 008000 008000 Program RAM Internal X data Internal Y data 64K RAM 32K RAM 32K 000000 000000 000000 Bit Settings Memory Configuration ms MSW ce s
123. 0 6 32 32 DSP56311 User s Manual Rev 2 6 28 Freescale Semiconductor Programming Model Quick Reference Table 6 18 Host Side Registers After Reset Continued Reset Type Register Register Name Data HW Sw Individual Reset STOP Reset Reset ISR HREQ 0 0 1 if TREQ is set 1 if TREQ is set 0 otherwise 0 otherwise HF3 HF2 0 0 TRDY 1 1 1 1 TXDE 1 1 1 1 RXDF 0 0 0 0 IVR IV 0 7 OF 0F E RX RXH RXM RXL empty empty empty empty TX TXH TXM TXL empty empty empty empty Note A long dash denotes that the bit value is not affected by the specified reset 6 8 Programming Model Quick Reference Table 6 19 summarizes the HI08 programming model Table 6 19 HI08 Programming Model DSP Side Bit Reset Type Register f e Bit HW Indivi No Bit Name Value Function SW dual STOP HCR 0 HRIE Receive Interrupt 0 HRRA interrupt disabled 0 Enable 1 HRRQ interrupt enabled 1 HTIE Transmit 0 HTRQ interrupt disabled 0 mE Interrupt Enable 1 HTRQ interrupt enabled 2 HCIE Host Command 0 HCP interrupt disabled 0 Interrupt Enable 1 HCP interrupt enabled 3 HF2 Host Flag 2 0 4 HF3 Host Flag 3 0 HPCR 0 HGEN Host GPIO 0 GPIO signal disconnected 0 Enable 1 GPIO signals active 1 HA8EN Host Address 0 HA8 A1 GPIO 0 Line 8 Enable 1 HA8 A1 HA8 2 HA9EN Host Address 0 HA9 A2 GP
124. 1 0 k x amp Poe PDE Poeo 0 0 0 0 0 Port E GPIO Data Register PDRE X FFFF9D Read Write Reset 000000 Reserved Program as 0 Figure B 26 Port E Registers PCRE PRRE PDRE DSP56311 User s Manual Rev 2 Freescale Semiconductor B 37 Programming Reference Application Date Programmer Sheet 1 of 2 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 is A 5 o A 0 0 0 0 0 h 0 Filter Count Value Filter Count Register FCNT Y FFFFB3 Read Write Reset 000000 Filter Enable Bit 0 0 EFCOP Disabled FilterData Input Interrupt Enable Bit 10 1 EFCOP Enabled Read write control bit 0 Interrupt disabled Filter Type Bit 1 1 Interrupt enabled Ha Ee FilterData Output Interrupt Enable Bit 11 y Read write control bit Adaptive Mode Enable Bit 2 0 Adaptive Mode Disabled O Interrupt disabled 1 Adaptive Mode Enabled 1 Interrupt enabled Update Mode Enable Bit 3 Read only status bit 0 Update Mode Disabled 0 No FMAC underflow overflow sia sae Mode ei 1 FMAC underflow overflow occurred Filter Operating ModeBits 5 4 00 Real 10 Alt Complex FilterContention Bit 13 01 Complex 11 Magnitude Read only status bit 0 No dual access occurred py eo a 1 Core and EFCOP tried to access E Miichannol the same bank in FDM or FCM FilterSaturation Bit 12 f y Initialization Bit 7 Filter Data Input Buffer Empty Bit 14 0 Preprocess initialization Read on
125. 1 User s Manual Rev 2 Freescale Semiconductor SCI Programming Model Table 8 2 SCI Control Register SCR Bit Definitions Continued Bit Number Bit Name Reset Value Description 8 RE 0 Receiver Enable When RE is set the receiver is enabled When RE is cleared the receiver is disabled and data transfer from the receive shift register to the receive data register SRX is inhibited If RE is cleared while a character is being received the reception of the character completes before the receiver is disabled RE does not inhibit RDRF or receive interrupts Either a hardware RESET signal or a software RESET instruction clears RE WOMS Wired OR Mode Select When WOMS is set the SCI TXD driver is programmed to function as an open drain output and can be wired together with other TXD signals in an appropriate bus configuration such as a master slave multidrop configuration An external pullup resistor is required on the bus When WOMS is cleared the TXD signal uses an active internal pullup Either a hardware RESET signal or a software RESET instruction clears WOMS RWU Receiver Wakeup Enable When RWU is set and the SCI is in Asynchronous mode the wakeup function is enabled that is the SCI is asleep and can be awakened by the event defined by the WAKE bit In Sleep state all interrupts and all receive flags except IDLE are disabled When the receiver wakes up RWU is cleared by the wak
126. 12 11 10 9 8 7 6 5 4 3 2 1 0 PRx5 PRx4 PRx3 PRx2 PRx1 PRx0 Note For bits 5 0 a O configures PRxn as a GPI and a 1 configures PRxn as a GPO For ESSIO the GPIO signals are PC 5 0 For ESSI1 the GPIO signals are PD 5 0 The corresponding direction bits for Port C GPIOs are PRC 5 0 The corresponding direction bits for Port D GPIOs are PRD 5 0 Reserved Read as zero Write with zero for future compatibility Figure 7 19 Port Direction Registers PRRC X FFFFBE PRRD X FFFFAE DSP56311 User s Manual Rev 2 7 34 Freescale Semiconductor GPIO Signals and Registers Table 7 6 summarizes the ESSI port signal configurations Table 7 6 ESSI Port Signal Configurations PCRC PCADIi PRRC PRADIi Port Signal i Function 1 Xx ESSIO ESSI1 0 0 Port C Port D GPI 0 1 Port C Port D GPO X The signal setting is irrelevant to the Port Signal i function 7 6 3 Port Data Registers PDRC and PDRD Bits 5 0 of the read write PDRs write data to or read data from the associated ESSI GPIO signal lines if they are configured as GPIO signals If a port signal PC 1 or PD i is configured as an input GPI the corresponding PDRC i pr PDRD i bit reflects the value present on the input signal line If a port signal PC i or PD 1 is configured as an output GPO a value written to the corresponding PDRC i
127. 13 in the OMR When this bit is set BG and BB are synchronized internally See BG for additional information BB requires an external pull up resistor CAS Output Tri stated Column Address Strobe When the DSP is the bus master CAS is an active low output used by DRAM to strobe the column address Otherwise if the Bus Mastership Enable BME bit in the DRAM control register is cleared the signal is tri stated Note DRAM access is not supported above 100 MHz DSP56311 User s Manual Rev 2 Freescale Semiconductor 2 7 Signals Connections Table 2 8 External Bus Control Signals Continued Signal Name Type State During Reset Stop or Wait Signal Description BCLK Output Tri stated Bus Clock When the DSP is the bus master BCLK is active when the OMR ATE is set When BCLK is active and synchronized to CLKOUT by the internal PLL BCLK precedes CLKOUT by one fourth of a clock cycle Note At operating frequencies above 100 MHz this signal produces a low amplitude waveform that is not usable externally by other devices BCLK Output Tri stated Bus Clock Not When the DSP is the bus master BCLK is the inverse of the BCLK signal Otherwise the signal is tri stated Note At operating frequencies above 100 MHz this signal produces a low amplitude waveform that is not usable externally by other devices 2 6 Interrupt and Mode Control The
128. 19 Memory Configuration Program X Data Y Data SEREF SERRE External I O Internal I O FFCO FF80 FF80 Internal I O External External External C000 C000 Internal Program RAM 0000 Internal X data RAM 48K Internal Y data RAM 48K 0000 Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 0 any 1 1 31K 48K 48K Enabled 64K value 0400 7FFF 0000 BFFF 0000 BFFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 12 Memory Switch Off Cache On 16 Bit Mode DSP56311 User s Manual Rev 2 3 20 Freescale Semiconductor Program FFFF FFFF External FF80 1800 C000 Internal Program RAM 96K 4000 0000 0000 X Data Internal I O Reserved Internal X data RAM 16K Memory Maps Y Data External 1 O Internal I O FFFF FFCO FF80 C000 Reserved Internal Y data RAM 16K 4000 0000 Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 00 0 1 96K 16K 16K None 64K 0000 17FF 0000 3FFF 0000 3FFF the EFCOP but not by the DMA controller e Lowest 10K of X data RAM and
129. 2 3 9 3 3 9 3 4 9 3 4 1 9 3 4 2 9 3 4 3 9 3 5 9 3 6 9 4 9 4 1 9 4 2 9 4 3 9 4 4 9 4 5 9 4 6 9 4 7 10 10 1 10 2 Contents SCI Programming Model excita hg cel ake sandals Oye hb ead wh ded ead ea nd ee Pear 8 8 SCI Control Register SCR r ssc tka dae a R das 8 10 SCI Status Register SSR Jueni eka eee Ro ok eS ew Oh 8 15 SCI Clock Control Register SCCR 0 0 0 0 eee eens 8 17 SCI Data Registers iria bae di by a Dares ltda 8 19 SCLReceive Register SRX eiii in en 8 20 SCI Transmit Register STX o ooooooooocooooocoo e nee ence eens 8 21 GPIO Sisnals and REe18ters ici a e ory ea Bea ee eA ee 8 22 Port E Control Register PCRE 20 0 0 cece cence ene e en ees 8 22 Port E Direction Register PRRE 0 00 0 eect ees 8 23 Port E Data Register PDRE 0 ccc eee eae 8 23 Triple Timer Module OVERVIEW oti oS A Was Wie eas GL Aas eG Nae tro hare aaa ae ee Raa 9 1 Triple Timer Module Block Diagram 2 0 0 ee een eens 9 1 Individual Timer Block Diagram 20 0 cece ene nent tenes 9 2 Operation iA s gertsin fabs bre ed deb dation di st 9 3 Timer After Reset orita A Gees baie Pee CA a hae ate tea baa a bes 9 3 Timer Initialization a A a a e EA 9 3 Timer Exeption se it E ta ii a pate bh it ie ias 9 4 Operating Modes oi A A hes 9 5 Triple Timer Modest OE EE e 9 5 Timer GPO Mode U rs ai a a e a bee eee SA ee 9 5 Timer Pulse Mode cote A Web dea AE davies whch d
130. 2 banks with 1024 locations each You can make additional program memory available using the memory switch modes 3 1 2 Memory Switch Modes Program Memory Memory switch mode allows reallocation of portions of X and Y data RAM as program RAM OMR 7 is the memory switch MS bit that controls this function as follows 3 2 E When the MS bit is cleared program memory consists of the default 32K x 24 bit memory space described in the previous section In this default mode the lowest external program memory location is 8000 When the MS bit is set a portion of the higher locations of the internal X and Y data memory are switched to internal program memory The memory switch configuration MSW 1 0 bits also called M1 and MO in the OMR select one of the following options MSW 1 0 00 The 32K higher locations 4000 BFFF of the internal X data memory and the 32K higher locations 6000 BFFF of the internal Y data memory are switched to internal program memory In such a case the on chip program memory occupies the lowest 96K locations 0 17FFF in the program memory space The instruction cache if enabled occupies the lowest 1K program words locations 0 3FF The lowest external program memory location in this mode is 18000 MSW 1 0 01 The 24K higher locations 6000 BFFF of the internal X data memory and the 24K higher locations 6000 BFFF of the internal Y data memory are switched
131. 4 3 Frame Syne Selection sota a td wes 7 10 7 4 4 Frame Sync Signal Format 0 0 0 eee eee eens 7 10 7 4 5 Frame Sync Length for Multiple Devices 0 0 0 cece ccc ee eee 7 10 7 4 6 Word Length Frame Sync and Data Word Timing 0 0 0 0 ce eee eee ee 7 11 74 7 Frame Sync Polarity crisi ia td eds 7 11 7 4 8 Byte Format LSB MSB for the Transmitter 2 0 0 ccc eee 7 11 7 4 9 Pla gs a A O A load 7 12 7 5 ESSI Programming Model 20 0 eect EEA NEEE EE NER 7 12 7 5 1 ESSI Control Register A CRA 2 0 0 ccc eee nent ees 7 13 7 5 2 ESSI Control Register B CRB 0 ccc eee e ene n en E 7 17 7 5 3 ESSI Status Register SSISR escasas erenc een eee e een eens 7 26 7 5 4 ESSTRecely Shift Register unica a da eed eed wee 7 28 7 5 5 ESSI Receive Data Register RX o oooo ooocoococoncoo eens 7 28 7 5 6 ESSI Transmit Shift R gisterSs oorau i enneds renine rit itor eens 7 28 7 5 7 ESSI Transmit Data Registers TX 20 0 0 eee eens 7 31 7 5 8 ESSI Time Slot Register TSR 0 ccc cence eben nee 7 31 7 5 9 Transmit Slot Mask Registers TSMA TSMB oooccccocccccncr eee eens 7 31 7 5 10 Receive Slot Mask Registers RSMA RSMB 00 7 33 7 6 GPIO Signals and Re isters xiii Pie aa als a aoe bl AG beets 7 34 7 6 1 Port Control Registers PCRC and PORD o oococccccccc eee 7 34 7 6 2 Port Direction Registers PRRC and PRRD ooooococcoccccoccc a 7 34 7 6 3 Port Data Reg
132. 5 Index SCI Interrupt Priority Level SCL 4 15 Timer Interrupt Priority Level TOL 4 15 Interrupt Priority Register Peripherals IPR P programming sheet B 15 interrupt routines Host Interface HIO8 6 7 Interrupt Service Routine ISR 7 8 9 4 interrupt trigger event 7 9 Interrupt Vector Register IVR 6 21 programming sheet B 25 Inverter INV bit 9 25 9 27 IRQD IRQA Priority and Mode IDL IAL bits 4 14 J Joint Test Action Group JTAG 1 9 BSR 4 33 interface 2 19 Test Acces Port TAP 1 6 L Limit L bit 4 9 Loop Address register LA 1 8 Loop Counter register LC 1 8 M M68HC11 SCI interface 8 14 manual conventions 1 2 mapping control registers 5 1 MC68000 family 6 27 MC68681 DUART 8 14 memory allocation switching 3 2 configuration 3 7 dynamic switching 3 7 expansion 3 1 external expansion port 1 10 maps 3 8 on chip 1 9 shared 10 2 Memory Expansion Port 1 6 memory map internal I O B 2 memory maps 3 8 3 9 3 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 3 18 3 19 3 20 3 21 3 22 3 23 3 24 3 25 3 26 3 27 3 28 Memory Switch mode 3 2 X data Memory 3 4 Y data Memory 3 6 Memory Switch Mode MS bit 4 13 mobile switching center 10 1 MODD MODC MODB and MODA 8 7 mode control 2 8 Mode Register MR 4 5 DSP56311 User s Manual Rev 2 Freescale Semiconductor Index 9 Index Do Loop Flag LF 4 7 Double Precision Multiply Mode DM 4 7 Interrupt Mask I 4 9 Scaling S
133. 6311 User s Manual Rev 2 Freescale Semiconductor Program X Data FFFFFF FFFFFF FFFFFF Internal O FFFFCO FFFF80 FFFF80 FFFOOO FFFOOO Internal Reserved Internal Reserved FFOOCO FF0000 Bootstrap ROM FF0000 FF0000 External 018000 Reserved 00C000 00C000 00A000 Internal Program RAM 48K 000000 000000 External Internal X data RAM 40K 00C000 00A000 000000 Y Data External 1 O Internal I O Internal Reserved External Internal Y data RAM 40K Memory Maps Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 11 0 0 48K 40K 40K None 16M 0000 BFFF 0000 9FFF 0000 9FFF the EFCOP but not by the DMA controller e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and Figure 3 9 Memory Switch On MSW 11 Cache Off 24 Bit Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor Memory Configuration Program X Data Y Data FFFFFF FFFFFF FFFFFF External 1 0 Internal O SFFFFCO FFFF80 FFFF80 Internal I O S So Internal Reserved Internal Internal Reserved Reserved FFOOCO FF0000 Bootstrap ROM FF0000 FF0000 External External External 018000 00C000 00C000 00C000 Internal 00A000 00A000 Program RAM 47K 000400
134. 6311 views it as a 24 bit read only register Its address is X FFFFC6 It is loaded with 24 bit data from the transmit data registers TXH TXM TXL on the host side when both the transmit data register empty ISR TXDE on the host side and host receive data full HSR HRDF on the DSP side are cleared The transfer operation sets both ISR TXDE and HSR HRDF When the HSR HRDF is set the HRX register contains valid data The DSP56311 can set the HCR HRIE to cause a host receive data interrupt when HSR HRDF is set When the DSP56311 reads the HRX register the HSR HRDF bit is cleared Note The DSP56311 should never try to read the HRX register if the HSR HRDF bit is already cleared 6 6 9 DSP Side Registers After Reset Table 6 13 shows the results of the four reset types on the bits in each of the HIO8 registers accessible to the DSP56311 The hardware reset HW is caused by the RESET signal The software reset SW is caused by execution of the RESET instruction The individual reset IR occurs when HPCR HEN is cleared The stop reset ST occurs when the STOP instruction executes DSP56311 User s Manual Rev 2 6 20 Freescale Semiconductor Table 6 13 DSP Side Registers After Reset Host Programmer Model Reset Type Register Register Name Data HW sw IR ST Reset Reset Reset Reset HCR All bits 0 0 HPCR All bits 0 0 HSR HF 1 0 0 0 HCP 0 0 0 0 HTD
135. 8 Bit MSB LSB 8 bit Data AE 0 0 0 WL1 WLO MSB LSB Least Significant 12 bit Data Zero Fill LSB 16 bit Data LSB 24 bit Data NOTES b Transmit Registers Data is received MSB first if SHED 0 4 bit fractional format ALC 0 32 bit mode is not shown Figure 7 13 ESSI Data Path Programming Model SHFD 1 DSP56311 User s Manual Rev 2 7 30 Freescale Semiconductor ESSI Programming Model 7 5 7 ESSI Transmit Data Registers TX 2 0 ESSI0 TX20 TX10 TX00 ESSI1 TX21 TX11 TX01 TX2 TX1 and TXO are 24 bit write only registers Data written into these registers automatically transfers to the transmit shift registers See Figure 7 12 and Figure 7 13 The data transmitted 8 12 16 or 24 bits is aligned according to the value of the ALC bit When the ALC bit is cleared the MSB is Bit 23 When ALC is set the MSB is Bit 15 If the transmit data register empty interrupt has been enabled the DSP is interrupted whenever a transmit data register becomes empty Note When data is written to a peripheral device there is a two cycle pipeline delay while any status bits affected by this operation are updated If any of those status bits are read during the two cycle delay the status bit may not reflect the current status 7 5 8 ESSI Time Slot Register TSR TSR is effectively a write only null data register that prevents data transmission in the current transmit time slot For timing purposes TSR is a write only register tha
136. 80 Frame Sync Length Mask FSLO FSL1 M_FSLO EQU 7 Frame Sync Length 0 M_FSL1 EQU 8 Frame Sync Length 1 M_FSR EQU 9 Frame Sync Relative Timing M_FSP EQU 10 Frame Sync Polarity M_CKP EQU Clock Polarity M_SYN EQU 12 Sync Async Control M_MOD EQU 13 SSI Mode Select M_SSTE EQU 1C000 SSI Transmit enable Mask M_SSTE2 EQU 14 SSI Transmit 2 Enable M_SSTE1 EQU 15 SSI Transmit 1 Enable M_SSTEO EQU 16 SSI Transmit 0 Enable M_SSRE EQU 17 SSI Receive Enable M_SSTIE EQU 18 SSI Transmit Interrupt Enable M_SSRIE EQU 19 SSI Receive Interrupt Enable M_STLIE EQU 20 SSI Transmit Last Slot Interrupt Enable M_SRLIE EQU 21 SSI Receive Last Slot Interrupt Enable M_STEIE EQU 22 SSI Transmit Error Interrupt Enable M_SREIE EQU 23 SSI Receive Error Interrupt Enable SSI Status Register Bit Flags M_IF EQU 3 Serial Input Flag Mask M_IFO EQU 0 Serial Input Flag 0 M_IF1 EQU 1 Serial Input Flag 1 M_TFS EQU 2 Transmit Frame Sync Flag M_RFS EQU 3 Receive Frame Sync Flag M_TUE EQU 4 Transmitter Underrun Error FLag M_ROE EQU 5 Receiver Overrun Error Flag M_TDE EQU 6 Transmit Data Register Empty DSP56311 User s Manual Rev 2 A 12 Freescale Semiconductor Internal I O Equates M_RDF EQU 7 Receive Data Register Full SSI Transmit Slot Mask Register A M_SSTSA EQU SFFFF SSI Transmit Slot Bits Mask A TSO TS15
137. A Host side i y Y Low Byte p gt cc bb aa e High Byte read write last Host bus address 5 6 7 lost Soe XX cc bb aa internal register Figure 6 4 HI08 Read and Write Operations in Little Endian Mode The host can transfer one byte at a time so a 24 bit datum would be transferred using three store or load byte operations ensuring that the data byte at host bus address 7 is written last since this causes the transfer of the data to the DSP side HRX However the host bus controller may be sophisticated enough that the host can transfer all bytes in a single operation instruction For example in the PowerPC MPC860 processor the General Purpose Controller Module GPCM in the memory controller can be programmed so that the host can execute a single read load word LDW or write store word STW instruction to the HIO08 port and cause four byte transfers to occur on the host bus The 32 bit datum transfer shown in Figure 6 4 has byte data xx written to HIO8 address 4 byte aa to address 5 byte bb to address 6 and byte cc to address 7 this assumes the 24 bit datum is contained in the lower 24 bits of the host s 32 bit data register as shown A similar operation occurs when the HIOS is initialized in Big Endian mode by clearing the Host Little Endian bit ICR 5 HLEND Big Endian mode is depicted in Figure 6 5 HTX HRX Register 23 0 aa bb cc DSP side A Host
138. A10 is configured as a GPIO signal according to the value of the HDDR and HDR HA9EN Host Address Line 9 Enable If HA9EN is set and the HIO8 is in multiplexed bus mode then HA9 HA2 is host address line 9 HA9 If this bit is cleared and the HIO8 is in multiplexed bus mode then HA9 HA2 is configured as a GPIO signal according to the value of the HDDR and HDR NOTE HAQEN is ignored when the HI08 is not in the multiplexed bus mode that is when HMUX is cleared HA8EN Host Address Line 8 Enable If HA8EN is set and the HIO8 is in multiplexed bus mode then HA8 A1 is host address line 8 HA8 If this bit is cleared and the HIO8 is in multiplexed bus mode then HA8 HA1 is a GPIO signal according to the value of the HDDR and HDR NOTE HA8EN is ignored when the HIO8 is not in the multiplexed bus mode that is when HMUX is cleared HGEN Host GPIO Port Enable Enables disables signals configured as GPIO If this bit is cleared signals configured as GPIO are disconnected outputs are high impedance inputs are electrically disconnected Signals configured as HI08 are not affected by the value of HGEN 6 18 DSP56311 User s Manual Rev 2 Freescale Semiconductor DSP Core Programming Model HDS In a single strobe mode a DS data strobe signal qualifies the access while a R W Read Write signal specifies the direction of the access Figure 6 13 Single Strobe Mode HWR Write Cycle
139. BA register 10 41 Filter Coefficient Memory FCM bank 10 2 Filter Coefficient Memory FCM bank 10 2 Filter Control Status Register FCSR 10 37 Filter 10 37 Filter Adaptive Mode FADP 10 39 Filter Contention FCONT 10 37 Filter Data Input Buffer Empty FDIBE 10 37 Filter Data Input Interrupt Enable FDITE 10 38 Filter Data Output Interrupt Enable FDOIE 10 38 Filter Enable FEN 10 39 Filter Multichannel Mode FMLC 10 38 Filter Operation Mode FOM 10 39 DSP56311 User s Manual Rev 2 Freescale Semiconductor Index 3 Index Filter Processing State Initialization Mode FPRC 10 38 Filter Saturation FSAT 10 37 Filter Shared Coefficients Mode FSCO 10 38 Filter Type FLT 10 39 Filter Update FUPD 10 39 Filter Count Register FCNT 10 36 Filter Data Base Address FDBA register 10 41 Filter Data Input Register FDIR 10 35 Filter Data Memory FDM 10 2 10 4 Filter Data Memory FDM bank 10 2 Filter Data Output Register FDOR 10 35 Filter K Constant Input Register FKIR 10 36 Filter Multiplier Accumulator FMAC 10 2 Filter Multiplier and Accumulator FMAC 10 5 FIR 10 1 HR 10 1 initialization 10 1 input data buffer 10 2 interrupt vector table 10 35 memory bank base address pointers 10 2 memory banks 10 4 memory organization 10 4 Peripheral Module Bus PMB 10 3 programming model 10 35 Saturation mode 10 5 Sixteen bit Arithmetic mode 10 5 Enhanced Synchronous Serial Interface ESSI 1 13 2 15 2 16 7 1
140. Bi Interrupt Interrupt Scaling Mode Scaling Mode Sixteen_Bi DO Sixteen Bi Ins Ari thmetic truction Cache E Mask Bit 0 Mask Bit 1 Bit 0 Bit 1 t Compatibility Double Precision Multiply Loop Flag DO Forever Flag t Arithmetic Enable Saturation Rounding Mode bit 0 of priority bits in bit 1 of priority bits in OMR SR SR mask for CORE DMA priority bits in OMR Operating Mode A Operating Mode B Operating Mode C Operating Mode D External Bus Disable bit in OMR Delay Memory Switch bit in OMR bit 0 of priority bits in OMR bit 1 of priority bits in OMR Burst Enable Stop TA Synchro nize Select Bus Release Timing Address Tracing Enable bit in OMR Stack Exte Extended s Extended s nsion space select bit in OMR tack UNderflow flag in OMR tack OVerflow flag in OMR Extended WRaP flag in OMR Stack Exte nsion Enable bit in OMR DSP56311 User s Manual Rev 2 Freescale Semiconductor A 19 Bootstrap Program A 3 Interrupt Equates KKK KKK KKK KKK KKK KEKE KKK KKK KEK KKK KKK KK KKK KEKE KK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK AAA EQUATES for 56311 interrupts Last update February 20 1999 eK KKK KKK KKK KKK KKK KEK KKK KK KEK KKK KK KEK KKK KK KEK KKK KK KEK KKK KKK KKK KKK KKK KKK KKK KEK KKK AAA page 132 55 0 0 0 opt mex intequ ident 1 0 if DEF I_VEC leave us
141. Bit Address Register Name DMA FFF4 FFFFF4 DMA Status Register DSTR FFF3 FFFFF3 DMA Offset Register 0 DORO FFF2 FFFFF2 DMA Offset Register 1 DOR1 FFF1 FFFFF1 DMA Offset Register 2 DOR2 FFFO FFFFFO DMA Offset Register 3 DOR3 DMAO FFEF FFFFEF DMA Source Address Register DSRO FFEE FFFFEE DMA Destination Address Register DDRO FFED FFFFED DMA Counter DCOO FFEC FFFFEC DMA Control Register DCRO DMA1 FFEB FFFFEB DMA Source Address Register DSR1 FFEA FFFFEA DMA Destination Address Register DDR1 FFE9 FFFFE9 DMA Counter DCO1 FFE8 FFFFE8 DMA Control Register DCR1 DMA2 FFE7 FFFFE7 DMA Source Address Register DSR2 FFE6 FFFFE6 DMA Destination Address Register DDR2 FFE5 FFFFE5 DMA Counter DCO2 FFE4 FFFFE4 DMA Control Register DCR2 DMA3 FFE3 FFFFE3 DMA Source Address Register DSR3 FFE2 FFFFE2 DMA Destination Address Register DDR3 FFE1 FFFFE1 DMA Counter DCO3 FFEO FFFFEO DMA Control Register DCR3 DMA4 FFDF FFFFDF DMA Source Address Register DSR4 FFDE FFFFDE DMA Destination Address Register DDR4 FFDD FFFFDD DMA Counter DCO4 FFDC FFFFDC DMA Control Register DCR4 DMA5 FFDB FFFFDB DMA Source Address Register DSR5 FFDA FFFFDA DMA Destination Address Register DDR5 FFD9 FFFFD9 DMA Counter DCO5 FFD8 FFFFD8 DMA Control Register DCR5 Freescale Semiconductor DSP56311 User s Manual Rev 2 B 3 Programming Reference Table B 2 Internal
142. Bit Name Reset Value Description 23 8 0 Reserved Write to 0 for future compatibility 7 RDF 0 Receive Data Register Full Set when the contents of the receive shift register transfer to the receive data register RDF is cleared when the DSP reads the receive data register If RIE and RDF are set a DSP receive data interrupt request is issued TDE 0 Transmit Data Register Empty Set when the contents of the transmit data register of every enabled transmitter are transferred to the transmit shift register It is also set fora TSR disabled time slot period in Network mode as if data were being transmitted after the TSR has been written When TDE is set TDE data is written to all the TX registers of the enabled transmitters or to the TSR The TDE bit is cleared when the DSP writes to all the transmit data registers of the enabled transmitters or when the DSP writes to the TSR to disable transmission of the next time slot If the TIE bit is set a DSP transmit data interrupt request is issued when TDE is set ROE 0 Receiver Overrun Error Flag Set when the serial receive shift register is filled and ready to transfer to the receive data register RX but RX is already full that is the RDF bit is set If the REIE bit is set a DSP receiver overrun error interrupt request is issued when the ROE bit is set The programmer clears ROE by reading the SSISR with the ROE bit set and then reading the RX TUE 0 Transmitter
143. CO and SC1 signals are fully synchronized to the clock if they are programmed as transmit data signals 7 2 1 Serial Transmit Data Signal STD The STD signal transmits data from the serial transmit shift register STD is an output when data is transmitted from the TXO shift register With an internally generated bit clock the STD signal becomes a high impedance output signal for a full clock period after the last data bit is transmitted if another data word does not follow immediately If sequential data words are DSP56311 User s Manual Rev 2 7 2 Freescale Semiconductor ESSI Data and Control Signals transmitted the STD signal does not assume a high impedance state The STD signal can be programmed as a GPIO signal P5 when the ESSI STD function is not in use 7 2 2 Serial Receive Data Signal SRD SRD receives serial data and transfers the data to the receive shift register SRD can be programmed as a GPIO signal P4 when the SRD function is not in use 7 2 3 Serial Clock SCK SCK is a bidirectional signal providing the serial bit rate clock for the ESSI interface The signal is a clock input or output used by all the enabled transmitters and receivers in Synchronous modes or by all the enabled transmitters in Asynchronous modes See Table 7 1 for details SCK can be programmed as a GPIO signal P3 when not used as the ESSI clock Table 7 1 ESSI Clock Sources RX Clock SYN SCKD SCDO RX Clock Source
144. Chapter Chapter 8 Instruction Cache and Chapter Chapter 11 Operating Modes and Memory Spaces DSS1 DSSO DMA Source Memory Space 0 0 X Memory Space 0 1 Y Memory Space 1 0 P Memory Space 1 1 Reserved Note The lowest 4 K of X data RAM and 4 K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller 4 8 Device Identification Register IDR The IDR is a read only factory programmed register that identifies DSP56300 family members It specifies the derivative number and revision number of the device This information is used in testing or by software Figure 4 10 shows the contents of the IDR Revision numbers are assigned as follows 0 is revision 0 1 is revision A and so on 23 16 15 12 11 0 Reserved Revision Number Derivative Number 00 0 317 Figure 4 10 Identification Register Configuration Revision A 4 32 DSP56311 User s Manual Rev 2 Freescale Semiconductor JTAG Identification ID Register 4 9 JTAG Identification ID Register The JTAG ID register is a 32 bit read only factory programmed register that distinguishes the component on a board according to the IEEE 1149 1 standard Figure 4 11 shows the JTAG ID register configuration Version information corresponds to the revision number 0 for revision 0 1 for revision A etc 31 28 27 22 21 12 11 1 0 Version Informati
145. Core Configuration 4 2 Bootstrap Program The bootstrap program is factory programmed in an internal 192 word by 24 bit bootstrap ROM located in program memory space at locations FFOOO0O FFOOBF The bootstrap program can load any program RAM segment from an external byte wide EPROM the SCI or the host port The bootstrap program code is listed in Appendix A Upon exiting the Reset state the DSP56311 samples the MOD A D signal lines and loads their values into OMR MA MD The mode input signals MOD A D and the resulting MA MB MC and MD bits determine which bootstrap mode the DSP56311 enters see Table 4 1 Note To stop the bootstrap in any HI08 bootstrap mode set the Host Flag 0 HFO The loaded user program begins executing from the specified starting address You can invoke the bootstrap program options except modes 0 and 8 at any time by setting the MA MB MC and MD bits in the OMR and jumping to the bootstrap program entry point FF0000 Software can directly set the mode selection bits in the OMR Bootstrap modes 0 and 8 are the normal DSP56311 functioning modes Bootstrap modes 9 A and C F select different specific bootstrap loading source devices In these modes the bootstrap program expects the following data sequence when downloading the user program through an external port 1 Three bytes that specify the number of 24 bit program words to be loaded 2 Three bytes that specify the 24 bit start address w
146. DSP56311 USER S MANUAL DSP56311UM Rev 2 December 2005 Sey 2 freescale semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations not listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GMBH Technical Information Center Schatzbogen 7 81829 Munchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Order Number DSP56311UM Rev 2 12 2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no
147. DTD EQU S3F Channel Transfer Done Status MASK M_DTDO EQU 0 DMA Channel Transfer Done Status 0 M_DTD1 EQU 1 DMA Channel Transfer Done Status 1 M_DTD2 EQU 2 DMA Channel Transfer Done Status 2 M_DTD3 EQU 3 DMA Channel Transfer Done Status 3 M_DTD4 EQU 4 DMA Channel Transfer Done Status 4 M_DTD5 EQU 5 DMA Channel Transfer Done Status 5 M_DACT EQU 8 DMA Active State M_DCH EQU SEOO DMA Active Channel Mask DCHO DCH2 M_DCHO EQU 9 DMA Active Channel 0 M_DCH1 EQU 10 DMA Active Channel 1 M_DCH2 EQU 11 DMA Active Channel 2 EQUATES for Enhanced Filter Coprocessor EFCOP M_FDIR EQU SFFFFBO EFCOP Data Input Register M_FDOR EQU SFFFFB1 EFCOP Data Output Register M_FKIR EQU SFFFFB2 EFCOP K Constant Register M_FCNT EQU SFFFFB3 EFCOP Filter Counter M_FCSR EQU SFFFFB4 EFCOP Control Status Register M_FACR EQU SFFFFB5 EFCOP ALU Control Register M_FDBA EQU SFFFFB6 EFCOP Data Base Address M_FCBA EQU SFFFFB7 EFCOP Coefficient Base Address M_FDCH EQU SFFFFB8 EFCOP Decimation Channel Register EQUATES for Phase Locked Loop PLL Register Addresses Of PLL M_PCTL EQU SFFFFFD PLL Control Register PLL Control Register Freescale Semiconductor DSP56311 User s Manual Rev 2 Bootstrap Program M_MF EQU SFFF Multiplication Factor Bits Mask MFO MF11 M_DF EQU 7000 Division Factor Bits Mask DFO DF2 M_XTLR EQU 15 XTAL Range select bit
148. Data Internal I O External Internal X data RAM 32K Memory Maps Y Data External 1 O Internal I O FFFF FFCO FF80 External C000 8000 Internal Y data 0000 RAM 32K Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 10 0 1 64K 32K 32K None 64K 0000 FFFF 0000 7FFF 0000 7FFF the EFCOP but not by the DMA controller e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and Figure 3 17 Memory Switch On MSW 10 Cache Off 16 Bit Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor 3 25 Memory Configuration Program X Data Y Data FFFF SEREF External I O Internal I O FFCO FF80 FF80 Internal I O FFFF External External C000 C000 A000 A000 Internal Program RAM 79K 0400 Internal X data Internal Y data 0000 0000 PRAM 24K 0000 PAM 24K Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 10 1 1 79K 24K 24K Enabled 64K 0400 FFFF 0000 9FFF 0000 9FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 18
149. Divide by 1 or 16 If Synchronous Divide By 2 Timer Interrupt STMINT Fcore bps 64 x 7 SCP 1 x CD 1 where SCP 00r1 CD 000 to FFF SCKP Op SCKP 1p SCLK Figure 8 5 SCI Baud Rate Generator As noted in Section 8 6 1 the SCI can be configured to operate in a single Synchronous mode or one of five Asynchronous modes Synchronous mode requires that the TX and RX clocks use the same source but that source may be the internal SCI clock if the SCI is configured as a master device or an external clock if the SCI is configured as a slave device Asynchronous modes may use clocks from the same source internal or external or different sources for the TX clock and the RX clock For synchronous operation the SCI uses a clock that is equal to the two times the desired bit rate designated as the 2 x clock for both internal and external clock sources It must use the same source for both the TX and RX clock The internal clock is used if the SCI is the master device DSP56311 User s Manual Rev 2 8 18 Freescale Semiconductor SCI Programming Model and the external clock is used if the SCI is the slave device as noted above The clock is gated and limited to a maximum frequency equal to one eighth of the DSP core operating frequency that is 12 5 MHz for a DSP core frequency of 100 MHz For asynchronous operation the SCI can use the internal and external clocks in any combination as the source cloc
150. E 1 A DMA request is always generated when the FDOBF bit is set but a DMA transfer takes place only if a DMA channel is activated and triggered by this event A read from the FDOR clears the FDOBF bit 14 FDIBE 0 Filter Data Input Buffer Empty When set this read only status bit indicates that the FDIR is empty and the DSP can write data to the FDIR The FDIBE bit is set when all four FDIR locations are empty For proper operation write data to the FDIR only if FDIBE is set After the EFCOP is enabled by setting FEN FDIBE is set indicating that the FDIR is empty When FDIBE is set the EFCOP generates an FDIR empty interrupt request to the DSP56300 core if enabled that is FDIIE 1 A DMA request is always generated when the FDIBE bit is set but a DMA transfer takes place only if a DMA channel is activated and triggered by this event A write to the FDIR clears the FDIBE bit 13 FCONT 0 Filter Contention When set this read only status bit indicates an attempt by both the DSP56300 core and the EFCOP to access the same 1024 word bank in either the shared FDM or FCM A dual access could result in faulty data output in the FDOR Once set the FCONT bit is a sticky bit that can only be cleared by a hardware RESET signal a software RESET instruction or an individual reset 12 FSAT 0 Filter Saturation When set this read only status bit indicates that an overflow or underflow occurred in the MAC result Wh
151. E 1 1 1 1 HRDF 0 0 0 0 HBAR BA 10 3 80 80 NN HDDR DR 15 0 0 0 HDR D 15 0 HRX HRX 23 0 empty empty empty empty HTX HTX 23 0 empty empty empty empty Note A long dash denotes that the bit value is not affected by the specified reset 6 7 Host Programmer Model The HIOS provides a simple high speed interface to a host processor To the host bus the HIOS appears to be eight byte wide registers Separate transmit and receive data paths are double buffered to allow the DSP core and host processor to transfer data efficiently at high speed The host can access the HIO8 asynchronously using polling techniques or interrupt based techniques The HIOS appears to the host processor as a memory mapped peripheral occupying eight bytes in the host processor address space See Table 6 14 The eight HI08 registers include the following E A control register ICR on page 6 22 E A status register ISR on page 6 25 E Three data registers RXH TXH RXM TXM and RXL TXL on page 6 27 E Two vector registers CVR and IVR on page 6 24 and page 6 27 To transfer data between itself and the HIO8 the host processor bus performs the following steps 1 Asserts the HIOS address and strobes to select the register to be read or written Chip select in non multiplexed mode the address strobe in multiplexed mode 2 Selects the direction of the data transfer If it is writing the host processor places the data
152. Edge 0 1 1 0 1 1 DMA4 IPL D4LO Enabled 0 Trigger 0 Level 1 Neg Edge DMA3 IPL D3LO Enabled 0 0 1 Trigger Level DMA2 IPL Meo Edge D2L0 Enabled 0 No 1 0 1 Trigger DMA1 IPL Level D1LO Enabled Neg Edge DMAO IPL DOLO Enabled 0 1 0 1 CAMERON CO SERA y CO N Y SN 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 76 5 4 3 2 1 aaa Priority Register AS ra o Reset 000000 Figure B 3 Interrupt Priority Register Core IPRC DSP56311 User s Manual Rev 2 B 14 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 1 of 2 Interrupt Priority Triple Timer IPL TOL1 TOLO Enabled 0 No 0 1 Yes 1 0 Yes 1 1 Yes ESSI1 IPL S1L0 Enabled No SCI IPL e SCLO Enabled Yes 0 No Yes Yes 0 Yes 1 Yes ESSIO IPL SOLO Enabled 0 No Yes 0 Yes 1 Yes Host IPL HPLO Enabled 0 No Yes 0 Yes 1 Yes 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 XKXIXIXIXIXIXXIXIXIX IXIX XI XI TOL TOLA SCL1 SCLO S1LA S1LO SOLA SOLO HPL1 HPLO 0j 0 0 0 0 0 0 0 0 0 0 0 0 0 Inte
153. F2F SBE8B32 SBAD8D3 B99999 SBAD8D3 SBE8B32 10 3 6 4 5 Output Sequence for Example 10 4 000000 Sf44c4c See54b3 Se7cd6b Sdaed26 10 34 DSP56311 Reference Manual Rev 2 Freescale Semiconductor EFCOP Programming Model cc1071 Sc7dbic Scdfe45 10 4 EFCOP Programming Model This section documents the registers for configuring and operating the EFCOP The EFCOP registers available to the DSP programmer are listed in Table 10 5 The following paragraphs describe these registers in detail Table 10 5 EFCOP Registers and Base Addresses Address EFCOP Register Name Y FFFFBO Filter data input register FDIR Y FFFFB1 Filter data output register FDOR Y FFFFB2 Filter K constant register FKIR Y FFFFB3 Filter count register FCNT Y FFFFB4 Filter control status register FCSR Y FFFFB5 Filter ALU control register FACR Y FFFFB6 Filter data buffer base address FDBA Y FFFFB7 Filter coefficient base address FCBA Y FFFFB8 Filter decimation channel register FDCH Note The EFCOP registers are mapped onto Y data memory space 10 4 1 Filter Data Input Register FDIR The FDIR is a 4 word deep 24 bit wide FIFO for DSP to EFCOP data transfers Up to four data samples can be written into the FDIR at the same address Data from the FDIR is transferred to the FDM for filter processing For proper operation write data to the FDIR only if the FDIBE status bit is set indic
154. FDIBE bit 10 37 DSP56311 User s Manual Rev 2 Freescale Semiconductor Index 5 Index Filter Data Input Interrupt Enable FDITE bit 10 38 Filter Data Input Register FDIR 10 35 Filter Data Memory FDM bank 10 2 Filter Data Memory FDM bank 10 2 Filter Data Output Buffer Full FDOBF bit 10 37 Filter Data Output Interrupt Enable FDOIE bit 10 38 Filter Data Output Register FDOR 10 35 Filter Decimation FDCM bits 10 42 Filter Enable FEN bit 10 39 Filter Input Scale FISL bit 10 40 Filter K Constant Input Register FKIR 10 36 Filter Multichannel Mode FMLC bit 10 38 Filter Multiplier Accumulator FMAC 10 2 Filter Operation Mode FOM bits 10 39 Filter Processing State Initialization Mode FPRC bit 10 38 Filter Rounding Mode FRM bit 10 40 Filter Saturation FSAT bit 10 37 Filter Saturation Mode FSM bit 10 40 Filter Scaling FSCL bits 10 41 Filter Shared Coefficients Mode FSCO bit 10 38 Filter Type FLT bit 10 39 Filter Update FUPD bit 10 39 Finite Impulse Response FIR filter 10 1 10 14 10 17 10 24 10 25 10 26 10 27 frame rate divider 7 9 Frame Rate Divider Control DC bits 7 15 frame sync generator 7 16 length 7 10 selection 7 10 signal 7 7 7 9 7 17 Frame Sync Length FSL bits 7 21 Frame Sync Polarity FSP bit 7 20 Frame Sync Relative Timing FSR bit 7 21 Framing Error Flag FE bit 8 15 functional groups 2 2 G general purpose flags for host DSP communication 6 6 General Purpose In
155. HREQ HTRQ HTRQ PB14 HTRA HACK HACK HACK HRRQ HRRQ PB15 HRRQ The HI08 port can operate in multiplexed or non multiplexed mode In multiplexed mode HPCR 1 1 HMUX 1 the lower eight address signals multiplex with the eight data lines In non multiplexed mode HPCR 11 HMUX 0 the HIO8 requires a chip select signal and three address lines to select one of the eight registers accessible to the host Eight lines are used for data The HI08 port can also be programmed to use a single or dual read write data strobe and single or double host request Software and hardware resets clear all DSP side control registers and configure the HIOS as GPIO To select GPIO functions clear HPCR bits 6 through 1 to select other HIO8 functions set those same bits If the HIO8 is in GPIO mode the HDDR configures each corresponding signal in the HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is set For details see Section 6 6 3 Host Data Direction Register HDDR on page 6 14 and Section 6 6 4 Host Data Register HDR on page 6 15 Freescale Semiconductor DSP56311 User s Manual Rev 2 6 3 Host Interface HI08 6 3 Overview The HIOS is partitioned into two register banks as Figure 6 1 shows The host side register bank 1s accessible only to the host and the DSP side register bank is accessible only to the DSP core For the host the HIO8 appears as eight byte wide locations mapped in
156. HRW Input Ignored Input Host Read Write When the HI08 is programmed to interface with a single data strobe host bus and the HI function is selected this signal is the Host Read Write input HRD HRD Input Host Read Data When the HI08 is programmed to interface with a double data strobe host bus and the HI function is selected this signal is the Host Read Data strobe HRD Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HRD after reset Port B 11 When the HI08 is configured as GPIO through the HPCR this PB11 Input or signal is individually programmed through the HDDR Output 2 10 DSP56311 User s Manual Rev 2 Freescale Semiconductor HI08 Table 2 10 Host Interface Continued Signal Name Type State During Reset 1 2 Signal Description HDS HDS HWR HWR PB12 Input Input Input or Output Ignored Input Host Data Strobe When the HI08 is programmed to interface with a single data strobe host bus and the HI function is selected this signal is the Host Data Strobe HDS Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HDS following reset Host Write Data When the HI08 is programmed to interface with a double data strobe host bus and the HI function is selected this signal is the Host Write Data Strobe HWR Schmitt trigger input The polarity of the data strob
157. HX n Figure 10 5 IIR Filter Type Processing The IIR filter type only operates in Real mode Thus the FCSR FOM bits are ignored when the IIR filter type is in use Real mode performs IIR type filtering with real data One sample the real input is written to the FDIR and the EFCOP processes the data Then one sample the real output is read from the FDOR The default operation is single channel but the user can also select the Multi channel Mode option Multichannel mode for IIR filter type works exactly the same as it does for FIR filter type as explained in Section 10 3 3 2 3 Multichannel Mode Option on page 10 11 The Coefficient Update Adaptive mode and Decimation options are not available with the IR filter type 10 3 5 EFCOP Data Transfer Examples This section describes how to transfer data to and from the EFCOP using an FIR filter configuration Here we provide background information to help you understand the examples in Section 10 3 6 EFCOP Operation Examples on page 10 14 The examples employ the following notations E Dn Data sample at time n E H n Filter coefficient at time n DSP56311 Reference Manual Rev 2 10 12 Freescale Semiconductor EFCOP Operation E F n Output result at time n E filter_count Number of coefficient values in the coefficient memory bank FCM it is equal to the initial value written to the FCNT register plus 1 E Compute Perform all calculations to determin
158. IDLE 8 16 Overrun Error Flag OR 8 16 Parity Error PE 8 15 DSP56311 User s Manual Rev 2 Index 12 Freescale Semiconductor Receive Data Register Full RDRF 8 16 Received Bit 8 R8 8 15 Transmit Data Register Empty TDRE 8 16 Transmitter Empty TRNE 8 16 SCI Transmit Data Address Register STXA 8 9 SCI Transmit Data Register STX 8 8 select wakeup on idle line mode 8 13 Serial Clock SCLK 8 4 8 19 state after reset 8 5 Synchronous mode 8 2 transmission priority preamble break and data 8 7 transmit and receive shift registers 8 2 Transmit Data TXD 8 4 Transmit Data Register STX or STXA 8 19 Transmit Data Register STX 8 21 Wired OR mode 8 3 Serial Control 0 SC00 and SC10 signals 7 3 Serial Control 1 SC01 and SC11 signals 7 4 Serial Control 2 SC02 and SC12 signals 7 5 Serial Control Direction 0 SCDO bit 7 22 Serial Control Direction 1 SCD1 bit 7 22 Serial Control Direction 2 SCD2 bit 7 21 Serial Input Flag 0 IFO bit 7 4 7 28 Serial Input Flag 1 IF1 bit 7 28 Serial Output Flag OFO OF1 bits 7 17 Serial Output Flag 0 OFO bit 7 4 7 22 Serial Output Flag 1 OF1 bit 7 22 Serial Receive Data SRD signal 7 3 Serial Transmit Data STD signal 7 2 setting timer operating mode 9 3 shared memory 10 2 Shift Direction SHFD bit 7 21 signals 2 1 functional grouping 2 2 Single Data Strobe 2 2 Sixteen Bit Arithmetic Mode SA bit 4 6 Sixteen Bit Compatibility SC mode bit 4 8 Sixteen bit Compatibil
159. INISH EPRSCILD B MA 1001 go load from EPROM B MA 1011 reserved default to SCI This is the routine that loads from the SCI MD MC MB MA 1010 external SCI clock SCILD movep 0302 X M_SCR movep C000 X M_SCCR movep 7 X M_PCRE do 6 _LOOP6 jclr 2 X M_SSR movep X M_SRXL A2 jclr 1 X M_SSR movep A2 X M_STXL asr 8 a a _LOOP6 move al r0 move al rl do a0 _LOOP7 do 3 _LOOP8 jclr 2 X M_SSR movep X M_SRXL A2 jclr 1 X M_SSR movep a2 X M_STXL asr 8 a a _LOOP8 movem al p r0 nop _LOOP7 Configure SCI Control Reg Configure SCI Clock Control Reg Configure SCLK TXD and RXD get 3 bytes for number of program words and 3 bytes for the starting address Wait for RI Put 8 bits DRF to go high in A2 Wait for TDRE to go high echo the received byte starting address for load Save starting address Receive program words Wait for RI Put 8 bits Wait for TI DRF to go high in A2 DRE to go high echo the received byte Store 24 bit result in P mem pipeline delay Boot from SCI done This is the routine that loads from external EPROM MD MC MB MA 1001 Freescale Semiconductor DSP56311 User s Manual Rev 2 A 7 Bootstrap Program EPROMLD move BOOT r2 movep AARV X M_AAR1 do 6 _LOOP9 movem p r2 a2 asr 8 a a
160. IO 0 Line 9 Enable 1 HA9 A2 HA9 3 HCSEN Host Chip Select 0 HCS A10 GPIO 0 Enable 1 HCS A10 HCS Freescale Semiconductor DSP56311 User s Manual Rev 2 Host Interface HI08 Table 6 19 HIO8 Programming Model DSP Side Continued Bit Reset Type Register nen Bit A HW Indivi No Bit Name Value Function SW dual STOP HPCR 4 HREN Host Request HDRQ 0 0 cont Enable HDRQ 1 0 HREQ HTRQ GPIO HREQ HTRQ 1 HACK HRRQ GPIO HREQ HTRQ HREQ HREQ HTRQ HACK HRRQ HTRQ HRRQ 5 HAEN Host HDRQ 0 0 Acknowledge HDRQ 1 Enable 0 HACK HRRQ GPIO HREQ HTRQ 1 HACK HRRQ GPIO HACK HRRQ HACK HREQ HTRQ HACK HRRQ HTRQ HRRQ 6 HEN Host Enable 0 Host Port GPIO 0 1 Host Port Active 7 Reserved 0 Reserved 0 8 HROD Host Request 0 HREQ HTRQ HRRQ driven 0 Open Drain 1 HREQ HTRQ HRRQ open drain 9 HDSP Host Data Strobe 0 HDS HRD HWR active low 0 Polarity 1 HDS HRD HWR active high 10 HASP Host Address 0 HAS active low 0 Strobe Polarity 1 HAS active high 11 HMUX Host Multiplexed 0 Separate address and data lines 0 Bus 1 Multiplexed address data 12 HDDS Host Dual Data 0 Single Data Strobe HDS 0 Strobe 1 Double Data Strobe HWR HRD 13 HCSP Host Chip Select 0 HCS active low 0 Polarity 1 HCS active high 14 HRP Host Req
161. IO Interrupt Priority Level Mask M_SOLO EQU 2 SSIO Interrupt Priority Level low M_SOL1 EQU 3 SSIO Interrupt Priority Level high M_S1L EQU 30 SS nterrupt Priority Level Mask M_S1L0 EQU 4 SS nterrupt Priority Level low M_S1L1 EQU 5 SS nterrupt Priority Level high M_SCL EQU Sco SC nterrupt Priority Level Mask M_SCLO EQU 6 SE nterrupt Priority Level low M_SCL1 EQU 7 7 SE nterrupt Priority Level high M_TOL EQU 300 TIMER Interrupt Priority Level Mask M_TOLO EQU 8 TIMER Interrupt Priority Level low M_TOL1 EQU 9 TIMER Interrupt Priority Level high M_EPL EQU C00 EFCOP Interrupt Priority Level Mask M_EPLO EQU 10 EFCOP Interrupt Priority Level low M_EPL1 EQU EL EFCOP Interrupt Priority Level high T EQUATES for TIMER E Register Addresses Of TIMERO M_TCSRO EQU SFFFFSF TIMERO Control Status Register M_TLRO EQU SFFFF8E TIMERO Load Reg M_TCPRO EQU SFFFF8D TIMERO Compare Register M_TCRO EQU SFFFF8C TIMERO Count Register Register Addresses Of TIMER M_TCSR1 EQU SFFFF8B TIMER1 Control Status Register M_TLR1 EQU SFFFF8A TIMER1 Load Reg M_TCPR1 EQU SFFFF89 TIMER1 Compare Register M_TCR1 EQU SFFFF88 TIMER1 Count Register 7 Register Addresses Of TIMER2 DSP56311 User s Manual Rev 2 A 14 Freescale Semiconductor M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ M_ SFFFF87 SFFFF86 SFFFF85 SFFFF84 SFFFF83 SFFFF82 TIMER2 TIMI TIME
162. IR Filter DMA Input Interrupt Output INCLUDE ioequ asm e KKK KEK KKK KEK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KK AAA an equates KKK KEK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KK AAA RR af Startequ 00100 main program starting address FCON equ 801 EFCOP FSCR register contents DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 21 Enhanced Filter Coprocessor enable output interrupt enable the EFCOP FIR_LEN equ 20 EFCOP FIR length SRC_ADDRS equ 3040 DMA source address point to DATA bank DST_ADDRS equ 3000 address at which to begin output SRC_COUNT equ 006003 DMAO count 7 4 word transfers DST_COUNT equ 8 number of outputs generated FDBA_ADDRS equ 0 Input samples Start Address x 0 FCBA_ADDRS equ 0 Coeff Start Address y 0 RIK ARK LEEK REI EKER EE IKE EKER E ELEN RA RICA RIERA KLAR IEK ERE EERE org P 0 jmpStart ORG p 6a jsr gt kdo nop nop s RERE TL ERK REAR SAK RAR ARIS ARS ARR ER EE RERNE RERA KERR OEE KEE E KEE EA main program ekxkkxkxkxkxkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk k at ORG p Start interrupt initialization bset 10 x M_IPRP bset 11 x M_IPRP enable EFCOP interrupts in IPRP belr 8 SR A belr 9 SR enable interrupts in SR move 0 b move 0 a move DST_COUNT b0O counter for output interrupt
163. If the TCSR TRM bit is cleared the counter continues to increment on each subsequent timer clock This process repeats until the timer is disabled that is TCSR TE is cleared If the counter overflows a pulse is output on the TIO signal with a pulse width equal to the timer clock period If the INV bit is set the pulse polarity is high logical 1 If INV is cleared the pulse polarity is low logical 0 The counter reloads when the TLR is written with a new value while the TCSR TE bit is set In Mode 9 internal logic preserves the TIO value and direction for an additional 2 5 internal clock cycles after the hardware RESET signal is asserted This convention ensures that a valid RESET signal is generated when the TIO signal resets the DSP56311 Mode 9 internal clock TRM 0 Software does not reset watchdog timer watchdog times out N write preload first event TRM 1 is not useful for watchdog function M write compare TE cick A A CLK 2 or prescale CLK TLR N Counter TCR 0 4 N Net gt lt MS Mei TCPR M TCF Compare Interrupt if TCIE 1 TOF Overflow Interrupt if TOIE 1 float pulse width TIO pin INV 0 low timer IL clock period float_ high TIO pin INV 1 TIO can connect to the RESET pin internal hardware preserves the TIO value and direction for an additional 2 5 clocks to ensure a reset of valid length Figure 9 18 Watchd
164. Inputs Power Name Description Vocp PLL Power Vcc dedicated for PLL use The voltage should be well regulated and the input should be provided with an extremely low impedance path to the Vcc power rail VecaL Quiet Core Low Power An isolated power for the DSP56300 core processing logic This input must be isolated externally from all other chip power inputs The user must provide adequate external decoupling capacitors VeccoH Quiet External High Power A quiet power source for I O lines This input must be tied externally to all other chip power inputs except Veco The user must provide adequate decoupling capacitors Voca Address Bus Power An isolated power for sections of the address bus I O drivers This input must be tied externally to all other chip power inputs except Voca The user must provide adequate external decoupling capacitors Veco Data Bus Power An isolated power for sections of the data bus I O drivers This input must be tied externally to all other chip power inputs except Voca The user must provide adequate external decoupling capacitors Vece Bus Control Power An isolated power for the bus control I O drivers This input must be tied externally to all other chip power inputs except Voco The user must provide adequate external decoupling capacitors Vech Host Power An isolated power for the HI08 I O drivers This input must be tied externally to a
165. MA access 6 5 host request 6 5 interrupts 6 5 pros and cons of polling 6 6 software polling 6 5 hardware reset 6 20 6 28 HI08 to DSP core interface 6 1 HI08 to host interface 6 1 Host Base Address Register HBAR 6 12 6 15 6 31 programming sheet B 22 host command 6 7 6 22 Host Control Register HCR 6 12 6 29 Host Command Interrupt Enable HCIE 6 13 Host Flags 2 3 HF 6 12 Host Receive Interrupt Enable HRIE 6 13 Host Transmit Interrupt Enable HTIE 6 13 programming sheet B 23 Index Host Data Direction Register HDDR 6 3 6 12 6 14 programming sheet B 34 Host Data Direction Register HDRR 6 31 Host Data Register HDR 6 12 6 15 6 31 programming sheet B 34 host interrupt request pins IRQx 6 8 Host Port Control Register HPCR 6 3 6 12 6 16 6 20 6 21 6 29 6 30 Host Acknowledge Enable HAEN 6 18 Host Acknowledge Polarity HAP 6 16 Host Address Line 8 Enable HA8EN 6 18 Host Address Line 9 Enable HA9EN 6 18 7 19 Host Address Strobe Polarity HASP 6 17 Host Chip Select Enable HCSEN 6 18 Host Chip Select Polarity HCSP 6 17 Host Data Strobe Polarity HDSP 6 17 Host Dual Data Strobe HDDS 6 17 Host Enable HEN 6 17 Host GPIO Port Enable HGEN 6 18 Host Multiplexed Bus HMUX 6 17 Host Request Enable HREN 6 18 Host Request Open Drain HROD 6 17 Host Request Polarity HRP 6 16 programming sheet B 4 B 22 host processor registers 6 12 Host Receive HRX register 6 5 6 20 6 31 Host Receive Data R
166. MA block has the following features Six DMA channels supporting internal and external accesses One two and three dimensional transfers including circular buffering End of block transfer interrupts Triggering from interrupt lines and all peripherals 1 9 Peripherals In addition to the core features the DSP56311 provides the following peripherals E As many as 34 user configurable GPIO signals HI08 to external hosts Dual ESSI SCI Triple timer module Memory switch mode Four external interrupt mode control lines 1 9 1 GPIO Functionality The GPIO port consists of up to 34 programmable signals also used by the peripherals H1I08 ESSI SCI and timer There are no dedicated GPIO signals After a reset the signals are automatically configured as GPIO Three memory mapped registers per peripheral control GPIO functionality Programming techniques for these registers to control GPIO functionality are detailed in Chapter 5 Programming the Peripherals 1 9 2 HI08 The HIOS is a byte wide full duplex double buffered parallel port that can connect directly to the data bus of a host processor The HI08 supports a variety of buses and provides connection with a number of industry standard DSPs microcomputers and microprocessors without requiring any additional logic The DSP core treats the HIOS as a memory mapped peripheral occupying eight 24 bit words in data memory space The DSP can use the HIOS as a memory mapped peripheral
167. Mode 4 8 Sixteen Bit Compatibility SC mode 4 8 Mode Select MOD bit 7 20 move MOVE MOVEP instructions 5 1 MOVEP instruction 6 12 Multidrop mode 8 2 multiplexed bus 2 2 multiplexed bus mode 6 3 6 15 6 18 Multiplication Factor MF bits 4 20 Multiplier Accumulator MAC 1 6 1 7 N Negative N bit 4 9 Network mode 7 7 non multiplexed bus 2 2 non multiplexed bus mode 6 3 O off chip memory 1 6 3 1 OnCE JTAG 2 2 On Chip Emulation OnCE Interface Debug Event signal DE signal 2 19 On Chip Emulation OnCE module 1 6 1 9 interface 2 19 on chip memory 1 6 1 9 On Demand mode 7 9 7 14 Operating 4 1 operating frequency 1 6 operating mode 4 1 4 2 Host Interface HIO8 6 16 Operating Mode Register OMR 1 8 4 10 Address Attribute Priority Disable APD 4 12 Address Trace Enable ATE 4 11 Asynchronous Bus Arbitration Enable ABE 4 12 Bus Release Timing BRT 4 12 Cache Burst Mode Enable BE 4 12 Chip Operating Mode MD MA 4 13 COM byte 4 10 Core DMA Priority CDP 4 13 EOM byte 4 10 External Bus Disable EBD 4 13 Memory Switch Mode MS 4 13 programming sheet B 13 SCS byte 4 10 Stack Extension Enable SEN 4 11 Stack Extension Overflow Flag EOV 4 11 Stack Extension Underflow Flag EUN 4 11 Stack Extension Wrap Flag WRP 4 11 Stack Extension XY Select X YS 4 11 Stop Delay Mode SD 4 13 TA Synchronize Select TAS 4 12 Overflow V bit 4 10 Overrun Error Flag OR bit 8 16 P Parity Error
168. O signal Three registers control the GPIO functionality of Port D Port D control register PCRD Port D direction register PRRD and Port D data register PDRD Chapter 7 Enhanced Synchronous Serial Interface ESSI discusses these registers DSP56311 Port D GPIO dM SsC1 0 2 PD 0 2 Enhanced Synchronous lt gt _SCK1 PD3 Serial Interface Port 1 ESSI1 SRD 1 PD4 3 STD1 PD5 Figure 5 4 Port D Signals 5 5 4 Port E Signals and Registers Each of the three Port E signals not used as an SCI signal can be configured as a GPIO signal Three registers control the GPIO functionality of Port E Port E control register PCRE Port E DSP56311 User s Manual Rev 2 Freescale Semiconductor 5 7 Programming the Peripherals direction register PRRE and Port E data register PDRE Chapter 8 Serial Communication Interface SCT discusses these registers DSP56311 Port E GPIO RXD PEO Serial TXD PFI Communications Interface SCI Port SCLK PE2 Figure 5 5 Port E Signals 5 5 5 Triple Timer Signals and Registers Each of the three triple timer interface signals TIO 0 2 not used as a timer signal can be configured as a GPIO signal Each signal is controlled by the appropriate timer control status register TCSR 0 2 Chapter 9 Triple Timer Module discusses these registers DSP56311 Timer GPIO TIOO TIOO Timers TIO1 TIO1 TIO2 TIO2 Figure 5 6 Triple Timer Signals DSP56311 User s Manual Re
169. OP is in the individual reset state that is FEN 0 FEN Filter Enable This read write control bit enables the operation of the EFCOP When FEN is cleared operation is disabled and the EFCOP is in the individual reset state In the individual reset state the EFCOP is inactive internal logic and status bits assume the same state as that produced by a hardware RESET signal or a software RESET instruction the contents of the FCNT FDBA and FCBA registers are preserved and the control bits in FCSR and FACR remain unchanged Freescale Semiconductor DSP56311 Reference Manual Rev 2 10 39 Enhanced Filter Coprocessor 10 4 6 EFCOP ALU Control Register FACR The FACR is a read write register by which the DSP56300 core controls the main operation modes of the EFCOP ALU 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 FISL FSA FSM FRM1 FRMO FSCL1 FSCLO Reserved bit read as 0 write with 0 for future compatibility Reserved for internal use read as 0 write with O for proper use Table 10 8 EFCOP ALU Control Register FACR Bits Bit Reset Number Bit Name Value Description 23 16 0 Reserved They read as 0 write with O for future compatibility 15 12 0 Reserved for internal use Written as O for proper operation
170. Out TX Clock Source TX Clock Out Asynchronous 0 0 0 EXT SCO EXT SCK 0 0 1 INT SCO EXT SCK 0 1 0 EXT SCO INT SCK 0 1 1 INT SCO INT SCK Synchronous 1 0 0 1 EXT SCK EXT SCK 1 1 0 1 INT SCK INT SCK Note Although an external serial clock can be independent of and asynchronous to the DSP system clock the external ESSI clock frequency must not exceed EFcore 3 and each ESSI phase must exceed the minimum of 1 5 CLKOUT cycles The internally sourced ESSI clock frequency must not exceed F 5 4 7 2 4 Serial Control Signal SCO ESSIO0 SC00 ESSI1 SC10 To determine the function of the SCo signal select either Synchronous or Asynchronous mode according to Table 7 2 In Asynchronous mode this signal is used for the receive clock I O In Synchronous mode this signal is the transmitter data out signal for transmit shift register TX1 or for serial flag I O A typical application of serial flag I O would be multiple device selection for addressing in codec systems If SCo is configured as a serial flag signal or receive clock signal its direction is determined by the Serial Control Direction 0 SCDO bit in ESSI Control Register B CRB When configured as an output SCO functions as the serial Output Flag O OFO or as a receive shift register clock DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 3 Enhanced Synchronous Serial Interface ESSI output If SCo is used as
171. PE bit 8 15 Peripheral I O Expansion Bus 1 10 Peripheral Module Bus PMB 10 3 peripherals programming bit oriented instructions 5 1 data transfer methods 5 2 guidelines 5 1 individual reset state 5 1 initialization steps 5 1 interrupts 5 2 mapping control registers 5 1 move MOVE MOVEP instructions 5 1 polling 5 2 reading status registers 5 2 Phase Lock Loop PLL 2 4 PINIT 4 20 PLL 1 9 PLL Control PCTL register 4 19 Clock Output Disable COD 4 19 Crystal Range XTLR 4 20 Division Factor DF 4 20 PLL Enable PEN 4 20 PLL Multiplication Factor MF 4 20 PLL Stop State PSTP 4 20 Predivider Factor PD 4 19 programming sheet B 16 XTAL Disable XTLD 4 20 PLL Enable PEN bit 4 20 PLL Stop State PSTP bit 4 20 pointers EFCOP memory bank base address 10 2 polling 5 2 Port A 2 5 4 20 Port B 2 2 HIOS 5 6 programming sheet B 34 Port C 2 2 2 15 2 16 control registers 7 34 ESSIO 5 7 Port C Control Register PCRC 7 34 programming sheet B 35 Port C Data Register PDRC 7 35 programming sheet B 35 Port C Direction Register PRRC 7 34 programming sheet B 35 Port D 2 2 control registers 7 34 ESSI1 5 7 Port D Control Register PCRD 7 34 programming sheet B 36 DSP56311 User s Manual Rev 2 Index 10 Freescale Semiconductor Port D Data Register PDRD 7 35 programming sheet B 36 Port D Direction Register PRRD 7 34 programming sheet B 36 Port E 2 17 5 7 Port E Control Register PCRE 8 22 programming s
172. R The IVR is an 8 bit read write register that typically contains the interrupt vector number used with MC68000 family processor vectored interrupts Only the host processor can read and write this register The contents of the IVR are placed on the host data bus H 7 0 when both the HREQ and HACK signals are asserted The contents of this register are initialized to 0F by a hardware or software reset This value corresponds to the uninitialized interrupt vector in the MC68000 family 7 6 5 4 3 2 1 0 IV7 IV6 IV5 IV4 IV3 IV2 IV1 IVO Figure 6 18 Interrupt Vector Register IVR 6 7 5 Receive Data Registers RXH RXM RXL The host processor views the receive byte registers as three 8 bit read only registers the receive high register RXH the receive middle register RXM and the receive low register RXL They receive data from the high middle and low bytes respectively of the HTX register and are selected by the external host address inputs HA 2 0 during a host processor read operation The memory address of the receive byte registers are set by ICR HLEND If ICR HLEND is set the RXH is located at address 7 RXM at 6 and RXL at 5 If ICR HLEND is cleared the RXH is located at address 5 RXM at 6 and RXL at 7 When data is transferred from the HTX register to the receive byte register at host address 7 the ISR Receive Data Register Full RXDF bit is set The host processor can progra
173. R2 TIMI TIMI Internal I O Equates Control Status Register ER2 Load Reg ER2 Count ER Prescal TIMI Compare Register Register ler Load Register ER Prescal Timer Control Status Register Bit Flags Timer Prescaler Register 13 15 20 21 EQU 600000 21 22 Bits 4 5 6 a Timer Enable Timer Overflow Interrupt Enable Timer Compare Interrupt Enable Timer Con Inverter Bit Timer Res Direction Data Input Data Output ler Count Register trol Mask TCO TC3 tart Mode Bit Prescaled Clock Enable Timer Overflow Flag Timer Compare Flag Bit Flags Prescaler Source Mask Timer Control Timer Control Timer Control Timer Control Register Addresses Of DMA SFFFFF4 SFFFFF3 SFFFFF2 SFFFFFL SFFFFFO DMA DMA DMA DMA DMA Register Addresses Of DMAO TCSR2 EQU TLR2 EQU TCPR2 EQU TCR2 EQU TPLR EQU TPCR EQU TE EQU TOILE EQU TCIE EQU TC EQU INV EQU TRM EQU _ DIR EQU DI EQU DO EQU PCE EQU TOF EQU TCF EQU PS PSO EQU PS1 EQU Timer Control TCO EQU TC1 EQU TC2 EQU TC3 EQU _DSTR EQU DORO EQU _DOR1 EQU _DOR2 EQU _DOR3 EQU _DSRO EQU SFFFFEF Freescale Semiconductor EQUATES for Direct Memory Access DMA WN RO Status Register Offset Register Offset Register Offset Register Offset Regis
174. RAKE ALK RETE R REK IKE EEE AIEEE KER RE REKER TORE ER EEEE TEREE RE EERE REK TERR do DST_COUNT endd nop jclr 15 y M_FCSR movep y M_FDOR x r0 endd nop nop stop_label DSP56311 Reference Manual Rev 2 10 20 Freescale Semiconductor EFCOP Operation nop jmp stop_label org xX SRC_ADDRS NCLUDE input asm org y FCBA_ADDRS INCLUDE coefs asm 10 3 6 1 3 DMA Input Interrupt Output The different stages of DMA input and interrupt output are as follows 1 Setup e Set the filter count register FCNT to the length of the filter coefficients 1 that is N 1 e Set the Data and Coefficient Base Address pointers FDBA FCBA e Set the operation mode FCSR 5 4 FOM 00 e Set Initialization mode FCSR 7 FPRC 0 e Set Filter Data Output Interrupt Enable FSCR 11 FDOIE 1 e Set DMA register with DMA input as per channel 0 in Section 10 3 6 1 1 2 Initialization e Enable interrupts in the Interrupt Priority Register IPRP 10 11 EOL 11 e Enable interrupts in the Status Register SR 8 9 00 e Enable EFCOP FCSR 0 FEN 1 e Enable the DMA input channel DCRO 23 DE 1 3 Processing e Whenever the Input Data Buffer FDIR is empty that is FDIBE 1 the EFCOP triggers DMA which loads the next input into the FDIR e Compute F n the result is stored in FDOR The core is interrupted when FDOBF is set and stores the data in memory Example 10 3 Real F
175. RESET Non Multiplexed Bus H 0 7 HAO HA1 HA2 HCS HCS Single DS HRW HDS HDS Single HR HREQ HREQ HACK HACK SCO 0 2 SCKO SRDO STDO SC1 0 2 SCK1 SRD1 STD1 RXD TXD SCLK TIOO TIO1 TIO2 TCK TDI TDO TMS TRST DE After Reset Multiplexed Bus HAD O 7 HAS HAS HA8 HA9 HA10 Double DS HRD HRD HWR HWR Double HR HTRQ HTRQ HRRQ HRRQ Port C GPIO PC o 2 PC3 PC4 PC5 Port D GPIO PD O 2 PD3 PD4 PD5 Port E GPIO PEO PE1 PE2 Timer GPIO TIOO TIO1 TIO2 Port B GPIO PB 0 7 PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15 The HIO8 port supports a non multiplexed or a multiplexed bus single or double Data Strobe DS and single or double Host Request HR configurations Since each of these modes is configured independently any combination of these modes is possible These HI08 signals can also be configured alternately as GPIO signals PB O 15 Signals with dual designations for example HAS HAS have configurable polarity 2 The ESSIO ESSI1 and SCI signals are multiplexed ESSIO with the Port C GPIO signals PC 0 5 ESSI1 with Port D GPIO signals PD 0 5 and SCI with Port E GPIO signals PE O 2 3 TIO O 2 can be configured as GPIO signals 4 These signals are not supported above 100 MHz 2 2 Figure 2 1 Signals Identified by Functional Group DSP56311 User s Manual Rev 2 Freescale Semiconductor 2 1 Power Power Table 2 2 Power
176. Receive Data Register High Read Only SCI Receive Data Register Middle Read Only SCI Receive Data Register Low Read Only SCI Receive Data Shift Register Note SRX is the same register decoded at three different addresses a Receive Data Register SCI Transmit Data Register High Write Only SCI Transmit Data Register Middle Write Only SCI Transmit Data Register Low Write Only y SCI Transmit Data Shift Register 23 16 15 8 7 T 0 E TXA SCI Transmit Data Address Register Write Only Note Bytes are masked on the fly STX is the same register decoded at four different addresses b Transmit Data Register Figure 8 7 SCI Programming Model Data Registers 8 6 4 1 SCI Receive Register SRX Data bits received on the RXD signal are shifted into the SCI receive shift register When a complete word is received the data portion of the word is transferred to the byte wide SRX This process converts serial data to parallel data and provides double buffering Double buffering promotes flexibility and increased throughput since the programmer can save and process the previous word while the current word is being received The SRX can be read at three locations as SRXL SRXM and SRXH When SRXL is read the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on the data bus are read as zeros Similarly when SRXM is read the contents of SRX are placed into the middle byte of the
177. Register PCRE FF9E SFFFF9E Port E Direction Register PRRE FF9D FFFF9D Port E GPIO Data Register PDRE DSP56311 User s Manual Rev 2 Freescale Semiconductor B 5 Programming Reference Table B 2 Internal I O Memory Map Continued X Data Memory Peripheral 16 Bit Address 24 Bit Address Register Name SCI FF9C FFFF9C SCI Control Register SCR FF9B FFFF9B SCI Clock Control Register SCCR FF9A FFFF9A SCI Receive Data Register High SRXH FF99 FFFF99 SCI Receive Data Register Middle SRXM FF98 FFFF98 SCI Receive Data Register Low SRXL FF97 FFFF97 SCI Transmit Data Register High STXH FF96 FFFF96 SCI Transmit Data Register Middle STXM FF95 FFFF95 SCI Transmit Data Register Low STXL FF94 FFFF94 SCI Transmit Address Register STXA FF93 FFFF93 SCI Status Register SSR FF92 FFFF92 Reserved FF91 FFFF91 Reserved FF90 FFFF90 Reserved Triple Timer FF8F FFFF8F Timer O Control Status Register TCSRO FF8E FFFF8E Timer O Load Register TLRO FF8D FFFF8D Timer 0 Compare Register TCPRO FF8C FFFF8C Timer O Count Register TCRO FF8B FFFF8B Timer 1 Control Status Register TCSR1 FF8A FFFF8A Timer 1 Load Register TLR1 FF89 FFFF89 Timer 1 Compare Register TCPR1 FF88 FFFF88 Timer 1 Count Register TCR1 FF87 FFFF87 Timer 2 Control Status Register TCSR2 FF86 FFFF86 Timer 2 Load
178. Register TLR2 FF85 FFFF85 Timer 2 Compare Register TCPR2 FF84 FFFF84 Timer 2 Count Register TCR2 FF83 FFFF83 Timer Prescaler Load Register TPLR FF82 FFFF82 Timer Prescaler Count Register TPCR FF81 FFFF81 Reserved FF80 FFFF80 Reserved DSP56311 User s Manual Rev 2 B 6 Freescale Semiconductor Internal I O Memory Map Table B 3 Internal I O Memory Map Y Data Memory Peripheral rian 24 Bit Address Register Name FFBF FFFFBF Reserved FFBE FFFFBE Reserved FFBD FFFFBD Reserved FFBC FFFFBC Reserved FFBB FFFFBB Reserved FFBA FFFFBA Reserved FFB9 FFFFB9 Reserved Enhanced Filter FFB8 FFFFB8 EFCOP Decimation Channel FDCH Register Coprocessor EFCOP FFB7 FFFFB7 EFCOP Coefficient Base Address FCBA FFB6 FFFFB6 EFCOP Data Base Address FDBA FFB5 FFFFB5 EFCOP ALU Control Register FACR FFB4 FFFFB4 EFCOP Control Status Register FCSR FFB3 FFFFB3 EFCOP Filter Count FCNT Register FFB2 FFFFB2 EFCOP K Constant Register FKIR FFB1 FFFFB1 EFCOP Data Output Register FDOR FFBO FFFFBO EFCOP Data Input Register FDIR SFFAF SFFFFAF Reserved FF80 FFFF80 Freescale Semiconductor DSP56311 User s Manual Rev 2 B 7 Programming Reference B 2 Interrupt Sources and Priorities Table B 4 Interrupt Sources
179. Registers AAR 3 0 DSP56311 User s Manual Rev 2 Freescale Semiconductor B 19 Programming Reference Application DMA Channel Enable Bit 23 0 Disables channel operation 1 Enables channel operation DMA Interrupt Enable Bit 22 0 Disables DMA Interrupt 1 Enables DMA interrupt DMA Transfer Mode Bits 21 19 DTM 2 0 Triggered By DE Cleared Transfer Mode 000 request yes block transfer 001 request yes word transfer request yes line transfer DE yes block transfer request no block transfer request no word transfer reserved reserved DMA Channel Priority Bits 18 17 DPR 1 0 Channel Priority 00 Priority level 0 lowest 01 Priority level 1 10 Priority level 2 11 Priority level 3 highest DMA Continuous Mode Enable Bit 16 0 Disables continuous mode 1 Enables continuous mode DMA Request Source Bits 15 11 DRS 4 0 Requesting Device 00000 00011 External IRQA IRQB IRQC IRQD 00100 01001 Transfer done from channel 0 1 2 3 4 5 01010 01011 ESSIO Receive Transmit Data 01100 01101 ESSI1 Receive Transmit Data 01110 01111 SCI Receive Transmit Data 10000 10010 TimerO Timer1 Timer2 10011 Host Receive Data Full 10100 Host Transmit Data Empty 10101 11111 Reserved Date Programmer Sheet 1 of 1 Three Dimensional Mode Bit 10 0 Three Dimensiona
180. Rev 2 2 13 Signals Connections Table 2 11 Enhanced Synchronous Serial Interface 0 ESSIO Continued Signal State During F daba Name Type Reset 2 Signal Description Notes 1 Inthe Stop state the signal maintains the last state as follows e Ifthe last state is input the signal is an ignored input e Ifthe last state is output these lines are tri stated 2 The Wait processing state does not affect the signal state DSP56311 User s Manual Rev 2 Freescale Semiconductor Enhanced Synchronous Serial Interface 1 2 9 Enhanced Synchronous Serial Interface 1 Table 2 12 Enhanced Synchronous Serial Interface 1 ESSI1 Signal State During j Peer Name Type Reset 2 Signal Description SC10 Input or Output Ignored input Serial Control 0 Functions in either Synchronous or Asynchronous mode For Asynchronous mode this signal is the receive clock I O Schmitt trigger input For Synchronous mode this signal is either for Transmitter 1 output or Serial I O Flag 0 PDO Port D 0 The default configuration following reset is GPIO For PDO signal direction is controlled through the Port D Direction Register PRRD This signal is configured as SC10 or PDO through the Port D Control Register PCRD This input is 5 V tolerant SC11 Input Output Ignored input Serial Control 1 Functions in either Synchronous or Asynchronous mode For Asynchronous mode this signal is the receiver frame sync I
181. Rev 2 2 6 Freescale Semiconductor External Memory Expansion Port Port A Table 2 8 External Bus Control Signals Continued Signal Name Type State During Reset Stop or Wait Signal Description Output Reset Output deasserted State during Stop Wait depends on BCR BRH bit setting BRH 0 Output deasserted e BRH 1 Maintains last state that is if asserted remains asserted Bus Request Asserted when the DSP requests bus mastership BR is deasserted when the DSP no longer needs the bus BR is asserted or deasserted independently of whether the DSP56311 is a bus master or a bus slave Bus parking allows BR to be deasserted even though the DSP56311 is the bus master See the description of bus parking in the BB signal description The Bus Request Hold BRH bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus BR is typically sent to an external bus arbitrator that controls the priority parking and tenure of each master on the same external bus BR is affected only by DSP requests for the external bus never for the internal bus During hardware reset BR is deasserted and the arbitration is reset to the bus slave state Input Ignored Input Bus Grant Asserted by an external bus arbitration circuit when the DSP56311 becomes the next bus master When BG is asserted the DSP56311 must wait until BB is deasserted before
182. SCI Clock Control Register SCCR Table 8 5 SCI Clock Control Register SCCR Bit Definitions Bit Number Bit Name Reset Value Description 23 16 0 Reserved Write to O for future compatibility 15 TCM 0 Transmit Clock Source Selects whether an internal or external clock is used for the transmitter If TCM is cleared the internal clock is used If TCM is set the external clock from the SCLK signal is used 14 RCM Receive Clock Mode Source Selects whether an internal or external clock is used for the receiver If RCM is cleared the internal clock is used If RCM is set the external clock from the SCLK signal is used TCM RCM TX Clock RX Clock SCLK Mode 0 Internal Internal Output Synchronous asynchronous 0 Internal External Input Asynchronous only 1 External Internal Input Asynchronous only O oO 1 External External Input Synchronous asynchronous 13 SCP Clock Prescaler Selects a divide by 1 SCP is cleared or divide by 8 SCP is set prescaler for the clock divider The output of the prescaler is further divided by 2 to form the SCI clock 12 COD Clock Out Divider The clock output divider is controlled by COD and the SCI mode If the SCI mode is synchronous the output divider is fixed at divide by 2 If the SCI mode is asynchronous either e If COD is cleared and SCLK is an output that is TCM and RCM are
183. SISRO EQU M_CRBO EQU M_CRAO EQU M_TSMAO EQU M_TSMBO EQU M_RSMAO EQU M_RSMBO EQU M_TX10 EQU M_TX11 EQU M_TX12 EQU M_TSR1 EQU M_RX1 EQU M_SSISR1 EQU M_CRB1 EQU M_CRA1 EQU SFFF 12 13 14 15 SFFFF SFFFF B B SFFFF SFFFF SFFFF SFFFF SFFFF SFFFF SFFFF SFFFF SFFFF SFFFF BA B9 B8 B7 B6 B5 B4 B3 B2 B1 SFFFFAC SFFFFAI SFFFFAA SFFFFA9 SFFFFAS SFFFFA7 SFFFFA6 SFFFFA5 Freescale Semiconductor B Register Addresses Of SSI1 SCI Transmit Interrupt Enable Timer Interrupt Enable Timer Interrupt Rate SCI Clock Polarity SCI Error Interrupt Enable REIE Bit Flags Transmitter Empty Transmit Data Register Empty Receive Data Register Full Idle Line Flag Overrun Error Flag Parity Error Framing Error Flag Received Bit 8 R8 Address Clock Divider Mask CDO CD11 Clock Out Divider Clock Prescaler Receive Clock Mode Source Bit Transmit Clock Source Bit Internal I O Equates SSIO Transmit Data Register 0 SSIO Transmit Data Register 1 SSIO Transmit Data Register 2 SSIO Time Slot Register SSIO Receive Data Register SSIO Status Register SSIO Control Register B SSIO Control Register A SSIO Transmit Slot Mask Register A SSIO Transmit Slot Mask Register B SSIO Receive Slot Mask Register A SSIO Receive Slot Mask Register B SSI1 Transmit Data Register 0
184. SP56311 User s Manual Rev 2 1 10 Freescale Semiconductor Internal Buses E Y memory data bus for carrying Y data throughout the core E Program address bus for carrying program memory addresses throughout the core E X memory address bus for carrying X memory addresses throughout the core E Y memory address bus for carrying Y memory addresses throughout the core The block diagram in Figure 1 1 illustrates these buses among other components All internal buses on the DSP56300 family members are 24 bit buses The program data bus is also a 24 bit bus Ss Enhanced Filter ESSI Co Interface processor Memory Expansion Area Program RAM 32K x 24 or Program X Data RAM RAM 1K x 24 and aun x 24and gek x 24 Instruction Y Data RAM 48K x 24 Cache a 1024x 24 Peripheral Expansion Area Address Generation External 18 Address External Bus 13 Interface and I Cache Control Control Internal Data 24 Sitch al A l eaa oo Data af CUT coe TT Clock E Gen 1 Program 14 Program Data ALU TAG erator leo 1 i Decode T i Address 24x 24 56 56 bit MAC A ree ae ere Two 56 bit Accumulators DE 56 bit Barrel Shifter MODA IRQA MODB IRQB MODC IRQC MODD IRQD Figure 1 1 DSP56311 Block Diagram See Section 1 6 6 Internal Memory on page 1 9 for memory size details PINIT NMI Note DSP56311 User s Manual Rev 2 Freescale Semiconductor 1 11 DSP56311 Overview 1 8 DMA The D
185. SSI1 Transmit Data Register 1 SSI1 Transmit Data Register 2 SSI1 Time Slot Register SSI1 Receive Data Register SSI1 Status Register SSI1 Control Register B SSI1 Control Register A DSP56311 User s Manual Rev 2 Bootstrap Program M_TSMA1 EQU SFFFFA4 SSI1 Transmit Slot Mask Register A M_TSMB1 EQU SFFFFA3 SSI1 Transmit Slot Mask Register B M_RSMA1 EQU SFFFFA2 SSIl Receive Slot Mask Register A M_RSMB1 EQU SFFFFAL SSIl Receive Slot Mask Register B SSI Control Register A Bit Flags M_PM EQU SFF Prescale Modulus Select Mask PM0O PM7 M_PSR EQU Prescaler Range M_DC EQU S1F000 Frame Rate Divider Control Mask DC0O DC7 M_ALC EQU 18 Alignment Control ALC M_WL EQU 380000 Word Length Control Mask WLO WL7 M_SSC1 EQU 22 Select SC1 as TR 0 drive enable SSC1 E SSI Control Register B Bit Flags M_OF EQU 3 Serial Output Flag Mask M_OFO EQU 0 Serial Output Flag 0 M_OF1 EQU 1 Serial Output Flag 1 M_SCD EQU sic Serial Control Direction Mask M_SCDO EQU 2 Serial Control 0 Direction M_SCD1 EQU 3 Serial Control 1 Direction M_SCD2 EQU 4 Serial Control 2 Direction M_SCKD EQU 5 Clock Source Direction M_SHFD EQU 6 Shift Direction M_FSL EQU 1
186. Underrun Error Flag TUE is set when at least one of the enabled serial transmit shift registers is empty that is there is no new data to be transmitted and a transmit time slot occurs When a transmit underrun error occurs the previous data which is still present in the TX registers not written is retransmitted In Normal mode there is only one transmit time slot per frame In Network mode there can be up to 32 transmit time slots per frame If the TEIE bit is set a DSP transmit underrun error interrupt request is issued when the TUE bit is set The programmer can also clear TUE by first reading the SSISR with the TUE bit set then writing to all the enabled transmit data registers or to the TSR RFS 0 Receive Frame Sync Flag When set the RFS bit indicates that a receive frame sync occurred during the reception of a word in the serial receive data register In other words the data word is from the first time slot in the frame When the RFS bit is cleared and a word is received it indicates only in Network mode that the frame sync did not occur during reception of that word RFS is valid only if the receiver is enabled that is if the RE bit is set In Normal mode RFS is always read as 1 when data is read because there is only one time slot per frame the frame sync time slot TFS 0 Transmit Frame Sync Flag When set TFS indicates that a transmit frame sync occurred in the current time slot TFS is set at the start of the
187. WL 2 1 MOD SYN FSL 1 0 FSR FSP CKP and SHFD 7 4 1 Normal Network On Demand Mode Selection To select either Normal mode or Network mode clear or set CRB MOD In Normal mode the ESSI sends or receives one data word per frame per enabled receiver or transmitter In Network mode 2 to 32 time slots per frame can be selected During each frame O to 32 data words are received or transmitted from each enabled receiver or transmitter In either case the transfers are periodic The Normal mode typically transfers data to or from a single device Network mode is typically used in time division multiplexed networks of CODECs or DSPs with multiple words per frame Network mode has a submode called On Demand mode Set the CRB MOD for Network mode and set the frame rate divider to 0 DC 00000 to select On Demand mode This submode does not generate a periodic frame sync A frame sync pulse is generated only when data is available to transmit The frame sync signal indicates the first time slot in the frame On Demand mode requires that the transmit frame sync be internal output and the receive frame sync be external input For simplex operation Synchronous mode could be used however for full duplex operation Asynchronous mode must be used You can enable data transmission that is data driven by writing data into each TX Although the ESSI is double buffered only one word can be written to each TX even if the transmit shift regist
188. WO BA3W2 BA3W1 BA3WO0 BA2W2 11 10 9 8 7 6 5 4 3 2 1 0 BA2W1 BA2W0 BA1W4 BA1W3 BA1W2 BA1W1 BA1WO BAOW4 BAOW3 BAOW2 BAOW1 BAOWO Reserved bit Read as zero write to zero for future compatibility Figure 4 6 Bus Control Register BCR Table 4 8 Bus Control Register BCR Bit Definitions Bit Number Bit Name Reset Value Description 23 BRH 0 Bus Request Hold Asserts the BR signal even if no external access is needed When BRH is set the BR signal is always asserted If BRH is cleared the BR is asserted only if an external access is attempted or pending 22 0 Reserved Write to 0 for future compatibility 21 BBS 0 Bus State This read only bit is set when the DSP is the bus master and is cleared otherwise 20 16 BDFW 4 0 11111 Bus Default Area Wait State Control 31 wait Defines the number of wait states one through 31 inserted into each external states access to an area that is not defined by any of the AAR registers The access type for this area is SRAM only These bits should not be programmed as zero since SRAM memory access requires at least one wait state When four through seven wait states are selected one additional wait state is inserted at the end of the access When selecting eight or more wait states two additional wait states are inserted at the end of the access These trailing wait states increase t
189. a receive frame sync edge leading edge if CRB FSP is cleared trailing edge if FSP is set only when the previous frame is completed If the frame sync is asserted before the frame is completed or before the last bit of the frame is received in the case of a bit frame sync or a word length frame sync with CRB FSR set the current frame sync is not recognized and the receiver is internally disabled until the next frame sync Frames do not have to be adjacent that is a new frame sync does not have to follow the previous frame immediately Gaps of arbitrary periods can occur between frames All the enabled transmitters are tri stated during these gaps 7 4 8 Byte Format LSB MSB for the Transmitter Some devices such as CODECs require a MSB first data format Other devices such as those that use the AES EBU digital audio format require the LSB first To be compatible with all formats the shift registers in the ESSI are bidirectional You select either MSB or LSB by programming CRB SHFD E If CRB SHFD is cleared data is shifted into the receive shift register MSB first and shifted out of the transmit shift register MSB first E If CRB SHEFD is set data is shifted into the receive shift register LSB first and shifted out of the transmit shift register LSB first DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 11 Enhanced Synchronous Serial Interface ESSI 7 4 9 Flags Two ESSI signals SC 1 0 are availab
190. able 10 3 DMA Channel 0 Register Initialization Register Setting Description DCRO bit values are as follows DMA Control Register 0 DIE 0 Disables end of transfer interrupt DTM 2 Chooses line transfer triggered by request DE auto clear on end of transfer DPR 2 Priority 2 DCON 0 Disables continuous mode DRS 15 Chooses DMA to trigger on EFCOP input buffer empty D3D 0 Chooses non 3D mode DAM 20 Sets the following DMA Address Mode source address 2D counter mode B offset DORO destination address no update no offset DDS 1 Destination in Y memory space because the EFCOP is in Y memory DSS 0 Source in X memory space DORO 1 DMA Offset Register 0 DCOO0 006003 DMA Counter Register 0 Gives transfer of 7 4 28 items input sequence length DSRO Address of source data DMA Source Address Register 0 DDRO FFFFBO DMA Destination Address Register for Channel O DMA output Channel 1 is used with a configuration similar to that of the DMA input channel except for a 1D transfer The DMA output control registers are initialized as shown in Table 10 4 Table 10 4 DMA Channel 1 Register Initialization Register Setting Description DCR1 bit values are as follows DMA Control Register 1 DIE 0 Disables end of transfer interrupt DTM 1 Chooses word transfer triggered by request DE auto clear on end of tran
191. access for the area defined by the BAC 11 0 BYEN BXEN and BPEN bits The encoding of BAT 1 0 is E 00 Reserved E 01 SRAM access E 10 DRAM access E 11 Reserved When the external access type is defined as a DRAM access BAT 1 0 10 AA RAS acts as a Row Address Strobe RAS signal Otherwise it acts as an Address Attribute signal External accesses to the default area always execute as if BAT 1 0 01 that is SRAM access If Port A is used for external accesses the BAT bits in the AAR3 0 registers must be initialized to the SRAM access type that is BAT 01 or to the DRAM access type that is BAT 10 To ensure proper operation of Port A this initialization must occur even for an AAR register that is not used during any Port A access Note At reset the BAT bits are initialized to 00 4 7 DMA Control Registers 5 0 DCR 5 0 The DMA Control Registers DCR 5 0 are read write registers that control the DMA operation for each of their respective channels All DCR bits are cleared during processor reset 23 22 21 20 19 18 17 16 15 14 13 12 DE DIE DTM2 DTM1 DTMO DPR1 DPRO DCON DRS4 DRS3 DRS2 DRS1 11 10 9 8 7 6 5 4 3 2 1 0 DRSO D3D DAM5 DAM4 DAM3 DAM2 DAM1 DAMO DDS1 DDSO DSS1 DSSO Figure 4 9 DMA Control Register DCR Table 4 11 DMA Control Register DCR Bit Definitions Bit Reset Pee Number Bit Nam
192. ace HI08 The choice of which protocol to use is based on such system constraints as the amount of data to be transferred the timing requirements for the transfer and the availability of such resources as processing bandwidth and DMA channels All of these constraints are discussed in the following sections The transfers described here occur asynchronously between the host and the DSP each transferring data at its own pace However use of the appropriate handshaking protocol allows data transfers to occur at optimum rates 6 4 1 Software Polling Software polling is the simplest data transfer method to use but it demands the greatest amount of the core s processing power Status bits are provided for the host or the DSP core to test and determine if the data registers are empty or full However the DSP core cannot be involved in other processing activities while it is polling these status bits On the DSP side for transfers from the DSP to the host host reads the DSP core must determine the state of Host Transmit Data register HTX In transfers from the host to the DSP host writes the DSP side should determine the state of the Host Receive Data Register HRX Thus two bits are provided to the core for polling E the Host Transmit Data Empty HTDE bit in the Host Status register HSR 1 HTDE E the Host Receive Data Full HRDF bit in the Host Status register HSR 0 HRDF A similar mechanism is available on the host side to d
193. activated in a round robin fashion that is channel 0 is activated to transfer one word followed by channel 1 then channel 2 and so on E if channels have different priorities the highest priority channel executes DMA transfers and continues for its pending DMA transfers E fa lower priority channel is executing DMA transfers when a higher priority channel receives a transfer request the lower priority channel finishes the current word transfer and arbitration starts again E if some channels with the same priority are active in a round robin fashion and a new higher priority channel receives a transfer request the higher priority channel is granted transfer access after the current word transfer is complete After the higher priority channel transfers are complete the round robin transfers continue The order of transfers in the round robin mode may change but the algorithm remains the same E The DPR bits also determine the DMA priority relative to the core priority for external bus access Arbitration uses the current active DMA priority the core priority defined by the SR bits CP 1 0 and the core DMA priority defined by the OMR bits CDP 1 0 Priority of core accesses to external memory is as follows Freescale Semiconductor DSP56311 User s Manual Rev 2 4 29 Core Configuration Table 4 11 DMA Control Register DCR Bit Definitions Continued Bit A Reset Pare Number Bit
194. ad TDRE Transmit Data Register Empty Set when the SCI transmit data register is empty When TDRE is set new data can be written to one of the SCI transmit data registers STX or the transmit data address register STXA TDRE is cleared when the SCI transmit data register is written Either a hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction sets TDRE In Synchronous mode when the internal SCI clock is in use there is a delay of up to 5 5 serial clock cycles between the time that STX is written until TDRE is set indicating the data has been transferred from the STX to the transmit shift register There is a delay of 2 to 4 serial clock cycles between writing STX and loading the transmit shift register in addition TDRE is set in the middle of transmitting the second bit When using an external serial transmit clock if the clock stops the SCI transmitter stops TDRE is not set until the middle of the second bit transmitted after the external clock starts Gating the external clock off after the first bit has been transmitted delays TDRE indefinitely In Asynchronous mode the TDRE flag is not set immediately after a word is transferred from the STX or STXA to the transmit shift register nor when the word first begins to be shifted out TDRE is set 2 cycles of the 16 x clock after the start bit that is 2 16 x clock cycles into the transmission time of the first data bit
195. address matches the DSP reads and processes the message and then suspends reception until the next address The Idle Line Wakeup mode wakes up the SCI to read a message before the first character arrives 8 1 3 4 Address Mode Wakeup The purpose and basic operational procedure for Address Mode Wakeup is the same as for Idle Line Wakeup The difference is that Address Mode Wakeup re enables the SCI when the ninth bit in a character is set to one if cleared this bit marks a character as data if set an address As a result an idle line is not needed which eliminates the dead time between messages 8 2 I O Signals Each of the three SCI signals RXD TXD and SCLK can be configured as either a GPIO signal or as a specific SCI signal Each signal is independent of the others For example if only the TXD signal is needed the RXD and SCLK signals can be programmed for GPIO However at least one of the three signals must be selected as an SCI signal to release the SCI from reset To enable SCI interrupts program the SCI control registers before any of the SCI signals are programmed as SCI functions In this case only one transmit interrupt can be generated because the Transmit Data Register is empty The timer and timer interrupt operate regardless of how the SCI pins are configured either as SCI or GPIO DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 3 Serial Communication Interface SCI 8 2 1 Receive Data RXD This i
196. after a frame sync signal either internally or externally generated only when the receive enable RE bit is set Data is transmitted after a frame sync signal either internally or externally generated only when the transmitter enable TE 2 0 bit is set 7 3 3 Exceptions The ESSI can generate six different exceptions They are discussed in the following paragraphs ordered from the highest to the lowest exception priority Note ESSI receive data with exception status Occurs when the receive exception interrupt is enabled the receive data register is full and a receiver overrun error has occurred This exception sets the ROE bit The ROE bit is cleared when you first read the SSISR and then read the Receive Data Register RX ESSI receive data Occurs when the receive interrupt is enabled the receive data register is full and no receive error conditions exist A read of RX clears the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead ESSI receive last slot interrupt Occurs when the ESSI is in Network mode and the last slot of the frame has ended This interrupt is generated regardless of the receive mask register setting The receive last slot interrupt can signal that the receive mask slot register can be reset the DMA channels can be reconfigured and data memory pointers can be reassigned Using the receive last slot interrupt guarantees that the previous frame is s
197. ag 2 HF2 bit 6 26 Host Flag 3 HF3 bit 6 26 Host Flags 0 1 HF bits 6 14 Host Flags 2 3 HF bits 6 12 Host GPIO Port Enable HGEN bit 6 18 Host Interface 2 2 Host Interface HIO8 2 9 2 11 2 12 6 1 chip select logic 6 16 Command Vector Register CVR 6 7 6 21 Host Command HC 6 25 Host Vector HV 6 25 programming sheet B 24 configuring host request mode 6 8 control operating mode 6 16 core communication with HI08 registers 6 11 core interrupts host command 6 7 DSP56311 User s Manual Rev 2 Index 6 Freescale Semiconductor receive data register full 6 7 transmit data empty 6 7 data registers 6 21 data strobe 6 3 Direct Memory Access DMA 6 8 DMA transfers and host bus 6 8 double buffered mechanism 6 5 DSP core 6 5 programming model 6 11 DSP core interrupts 6 6 DSP interrupt routines 6 22 DSP side control registers 6 12 data registers 6 12 registers after reset 6 20 DSP to host data word 6 2 handshaking protocols 6 2 interrupts 6 2 mapping 6 2 transfer modes 6 2 transfers 6 5 6 20 dual host request enabled 6 9 dual strobe mode 6 19 enabling host requests 6 8 external host address inputs 6 28 external host programmer s model 6 21 four kinds of reset 6 28 four reset types 6 20 general purpose flags for host DSP communication 6 6 GPIO configuration options 6 14 GPIO functions 6 3 HACK signal 6 18 HACK HRRQ handshake flags 6 22 handshaking mechanisms 6 5 handshaking protocols 6 5 choosing 6 6 Core D
198. ained by the timer compare register and the new event occurs In this mode the counter is also reloaded whenever the TLR is written with a new value while TCSR TE is set In all modes if TCSR TRM is cleared TRM 0 the counter operates as a free running counter Timer Compare Register TCPR The TCPR is a 24 bit read write register that contains the value to be compared to the counter value These two values are compared every timer clock after TCSR TE is set When the values match the timer compare flag bit is set and an interrupt is generated if interrupts are enabled that is the timer compare interrupt enable bit in the TCSR is set The TCPR is ignored in measurement modes 9 28 DSP56311 User s Manual Rev 2 Freescale Semiconductor Triple Timer Module Programming Model 9 4 7 Timer Count Register TCR The TCR is a 24 bit read only register In timer and watchdog modes the contents of the counter can be read at any time from the TCR register In measurement modes the TCR is loaded with the current value of the counter on the appropriate edge of the input signal and its value can be read to determine the width period or delay of the leading edge of the input signal When the timer is in measurement mode the TIO signal is used for the input signal DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 29 Triple Timer Module DSP56311 User s Manual Rev 2 9 30 Freescale Semiconductor Enhanced Fi
199. al Rev 2 10 18 Freescale Semiconductor EFCOP Operation 10 3 6 1 2 DMA Input Polling Output The different stages of input polling are as follows 1 Setup e Set the filter count register FCNT to the length of the filter coefficients 1 that is N 1 e Set the data and coefficient base address pointers FDBA FCBA e Set the operation mode FCSR 5 4 FOM 00 1 e Set the initialization mode FCSR 7 FPRC 0 e Set DMA registers DMA input as per channel 0 in Section 10 3 6 1 1 2 Initialization Enable EFCOP FCSR 0 FEN 1 e Enable DMA input channel DCRO 23 DE 1 3 Processing e Whenever the Input Data Buffer FDIR is empty that is FDIBE 1 the EFCOP triggers DMA input to transfer up to four new data words to FDM via FDIR e Compute F n the result is stored in FDOR e The core keeps polling the FCSR FDOBF bit and stores the data in memory Example 10 2 Real FIR Filtering using DMA input Polling output INCLUDE ioequ asm eR KKK KK KKK KKK KKK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KEKE KKK KKK KKK KKK KKK KEKKK at equates ARERAEIIRERERE ERE RL RE BAEK BE LORE BEL ROK BRIE RS RK AE KC KR BRR EK I RA Startequ 00100 main program starting address FCON equ 001 EFCOP FSCR register contents enable the EFCOP FIR_LEN equ 20 EFCOP FIR length SRC_ADDRS equ 3040 DMA source address point to DATA bank DST_ADDRS equ 3000 address at which
200. amming models see the chapter on debugging support in the DSP56300 Family Manual Table 2 15 OnCE JTAG Interface State Type During Signal Description Reset Signal Name TCK Input Input Test Clock A test clock input signal to synchronize the JTAG test logic TDI Input Input Test Data Input A test data serial input signal used for test instructions and data TDI is sampled on the rising edge of TCK and has an internal pull up resistor TDO Output Tri stated Test Data Output A test data serial output signal for test instructions and data TDO is tri statable and is actively driven in the shift IR and shift DR controller states TDO changes on the falling edge of TCK TMS Input Input Test Mode Select Sequences the test controller s state machine TMS is sampled on the rising edge of TCK and has an internal pull up resistor TRST Input Input Test Reset Initializes the test controller asynchronously TRST has an internal pull up resistor TRST must be asserted after power up DE Input Input Debug Event As an input provides a means of entering debug mode from an Output external command controller As an output provides a means of acknowledging that the chip has entered debug mode Asserted as an input DE causes the DSP56300 core to finish executing the current instruction save the instruction pipeline information enter debug mode and wait for commands from the debug serial input line This sig
201. ansmit last slot interrupt service time should not exceed N 1 ESSI bits service time where N is the number of bits in a slot ESSI transmit data Occurs when the transmit interrupt is enabled at least one of the enabled transmit data registers is empty and no transmitter error conditions exist Write to all the enabled TX registers or to the TSR to clear this interrupt This error free interrupt uses a fast interrupt service routine for minimum overhead if no more than two transmitters are used To configure an ESSI exception perform the following steps 1 7 8 Configure the interrupt service routine ISR Load vector base address register VBA b23 8 Define I_VEC to be equal to the VBA value if that is nonzero If it is defined I_VEC must be defined for the assembler before the interrupt equate file is included c Load the exception vector table entry two word fast interrupt or jump branch to subroutine long interrupt p I_SIOTD Configure interrupt trigger preload transmit data a Enable and prioritize overall peripheral interrupt functionality IPRP SOL1 0 b Write data to all enabled transmit registers TX00 c Enable a peripheral interrupt generating function CRB TEO d Enable a specific peripheral interrupt CRBO TIE e Enable peripheral and associated signals PCRC PC 5 0 f Unmask interrupts at the global level SR 11 0 The example material to the right of the steps shows register sett
202. any other DMA channel of equal priority DMA transfers in the continuous mode of operation can be interrupted if a DMA channel of higher priority is enabled after the continuous mode transfer starts If the priority of the DMA transfer in continuous mode that is DCON 1 is higher than the core priority CDP 01 or CDP 00 and DPR gt CP and if the DMA requires an external access the DMA gets the external bus and the core is not able to use the external bus in the next cycle after the DMA access even if the DMA does not need the bus in this cycle However if a refresh cycle from the DRAM controller is requested the refresh cycle interrupts the DMA transfer When DCON is cleared the priority algorithm operates as for the DPR bits DSP56311 User s Manual Rev 2 4 30 Freescale Semiconductor DMA Control Registers 5 0 DCR 5 0 Table 4 11 DMA Control Register DCR Bit Definitions Continued Bit A Reset soui Number Bit Name Value Description 15 11 DRS 4 0 0 DMA Request Source Encodes the source of DMA requests that trigger the DMA transfers The DMA request sources may be external devices requesting service through the IRQA IRQB IRQC and IRQD pins triggering by transfers done from a DMA channel or transfers from the internal peripherals All the request sources behave as edge triggered synchron
203. ar HRDF using the initialize function 6 6 3 Host Data Direction Register HDDR The HDDR controls the direction of the data flow for each of the HI08 signals configured as GPIO Even when the HIOS functions as the host interface its unused signals can be configured as GPIO signals For information on the HI08 GPIO configuration options see Section 6 2 Host Port Signals on page 6 3 If Bit DRxx is set the corresponding HI08 signal is configured as an output signal If Bit DRxx is cleared the corresponding HI08 signal is configured as an input signal Hardware and software reset clear the HDDR bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR15 DR14 DR13 DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DRO 6 14 Figure 6 8 Host Data Direction Register HDDR X FFFFC8 DSP56311 User s Manual Rev 2 Freescale Semiconductor DSP Core Programming Model 6 6 4 Host Data Register HDR The HDR register holds the data value of the corresponding bits of the HI08 signals configured as GPIO signals The functionality of Dxx depends on the corresponding HDDR bit that is DRxx The host processor can not access the Host Data Register HDR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO
204. ared no address comparison is performed BXEN Bus X Data Memory Enable A read write control bit that enables disables the AA pin and logic during external X data space accesses When set BXEN enables the comparison of the external address to the BAC bits during external X data space accesses If BXEN is cleared no address comparison is performed BPEN Bus Program Memory Enable A read write control bit that enables disables the AA RAS pin and logic during external program space accesses When set BPEN enables the comparison of the external address to the BAC bits during external program space accesses If BPEN is cleared no address comparison is performed BAAP Bus Address Attribute Polarity A read write Bus Address Attribute Polarity BAAP control bit that defines whether the AA RAS signal is active low or active high When BAAP is cleared the AA RAS signal is active low useful for enabling memory modules or for DRAM Row Address Strobe If BAAP is set the appropriate AA RAS signal is active high useful as an additional address bit 4 26 DSP56311 User s Manual Rev 2 Freescale Semiconductor DMA Control Registers 5 0 DCR 5 0 Table 4 10 Address Attribute Registers AAR O 3 Bit Definitions Bit Number Bit Name Reset Value Description 1 0 BAT 1 0 0 Bus Access Type Read write bits that define the type of external memory DRAM or SRAM to
205. arity SCKP 8 11 SCI Receive Interrupt Enable RIE 8 12 SCI Shift Direction SSFTD 8 14 SCI Transmit Interrupt Enable TIE 8 12 Send Break SBK 8 14 Timer Interrupt Enable TMIE 8 11 Timer Interrupt Rate STIR 8 11 Transmitter Enable TE 8 12 Wakeup Mode Select WAKE 8 13 Wired OR Mode Select WOMS 8 13 Word Select WDS 8 14 SCI Interrupt Priority Level SCL bits 4 15 SCI pins RXD TXD SCLK 8 3 SCI Receive Data Register SRX 8 8 8 20 SCI Receive Interrupt Enable RIE bit 8 12 SCI Serial Clock signal SCLK 8 4 SCI Shift Direction SSFTD 8 14 SCI Status Register SSR 8 8 8 15 bit definitions 8 15 Framing Error Flag FE 8 15 Idle Line Flag IDLE 8 16 Overrun Error Flag OR 8 16 Parity Error PE 8 15 Receive Data Register Full RDRF 8 16 Received Bit 8 R8 8 15 Transmit Data Register Empty TDRE 8 16 Transmitter Empty TRNE 8 16 SCI Transmit Data Address Register STXA 8 9 SCI Transmit Data Register STX or STXA 8 19 SCI Transmit Data Register STX 8 8 8 21 SCI Transmit Interrupt Enable TIE bit 8 12 SCLK 8 2 8 6 SCS byte 4 10 Select SCK SSC1 bit 7 13 Send Break SBK bit 8 14 Serial Clock SCK 7 3 Serial Clock SCLK SCI 8 2 Serial Communications Interface SCI 1 13 2 17 Address Mode Wakeup 8 3 Asynchronous mode 8 2 bootstrap loading 8 7 crystal frequency 8 6 data registers 8 19 Data Word Formats 8 9 enable wakeup function 8 13 enable disable SCI receive data with exception interrupt 8 11 exc
206. as follows e If the last state is input the signal is an ignored input e If the last state is output these lines have weak keepers that maintain the last output state even if the drivers are tri stated 2 The Wait processing state does not affect the signal state 2 8 Enhanced Synchronous Serial Interface 0 There are two synchronous serial interfaces ESSIO and ESSI1 that provide a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals which implement the Motorola serial peripheral interface SPI Table 2 11 Enhanced Synchronous Serial Interface O ESSIO Signal State During o Reset 2 Signal Description Name Type SC00 Input or Output Ignored input Serial Control 0 Functions in either Synchronous or Asynchronous mode For Asynchronous mode this signal is the receive clock I O Schmitt trigger input For Synchronous mode this signal is either for Transmitter 1 output or Serial I O Flag 0 PCO Port C 0 The default configuration following reset is GPIO For PCO signal direction is controlled through the Port C Direction Register PRRC This signal is configured as SCOO or PCO through the Port C Control Register PCRC This input is 5 V tolerant DSP56311 User s Manual Rev 2 2 12 Freescale Semiconductor Table 2 11 Enhanced Synchronous Serial Interface 0
207. ata left aligned to bit 23 1 16 bit data left aligned to bit 15 Frame Rate Divider Control DC4 0 00 1F 1 to 32 Divide ratio for Normal mode of time slots for Network The combination of PSR 1 and PM 7 0 00 is forbidden Prescaler Range Prescale Modulus Select 0 divide by 8 PM 7 0 00 FF divide by 1 to 256 1 divide by 1 23 22 Gi 20 19 20 19 18 u 16 15 14 13 12 11 10 9 8 7 ssc1 wL2 wit wLo acc DC4 pcs ocz oc1 obco Psa amp amp PM7 0 00 ESSI Control Register A CRAx ESSIO X FFFFB5 Read Write Reset 000000 ESSI1 X FFFFA5 Read Write Reserved Program as 0 Figure B 15 ESSI Control Register A CRA DSP56311 User s Manual Rev 2 B 26 Freescale Semiconductor Application Receive Exception Interrupt Enable 0 Disable 1 Enable Transmit Exception Interrupt Enable 0 Disable 1 Enable Receive Last Slot Interrupt Enable 0 Disable 1 Enable Transmit Last Slot Interrupt Enable 0 Disable 1 Enable Receive Interrupt Enable 0 Disable 1 Enable Transmit Interrupt Enable 0 Disable 1 Enable Receiver Enable 0 Disable 1 Enable Transmit 0 Enable 0 Disable 1 Enable Transmit 1 Enable SYN 1 only 0 Disable 1 Enable Transmit 2 Enable SYN 1 only 0 Disable 1 Enable Mode Select 0 Normal 1 Network Sync Async Control Tx amp Rx transfer together or not 0 Asynchronous 1 Synchronous Programming Sheets
208. ates The EFCOP supports up to 10K taps and 10K coefficients in any combination of number and length of filters for example eight filters of length 512 or 16 filters of length 256 It performs either 24 bit or 16 bit precision arithmetic with full support for saturation arithmetic A cost effective and power efficient coprocessor the EFCOP accelerates filtering tasks such as echo cancellation or correlation concurrently with software running on the DSP core DSP56311 User s Manual Rev 2 1 14 Freescale Semiconductor Signals Connections 2 The DSP56311 input and output signals are organized into functional groups as shown in Table 2 1 Figure 2 1 diagrams the DSP56311 signals by functional group The remainder of this chapter describes the signal pins in each functional group Table 2 1 DSP56311 Functional Signal Groupings Functional Group Number of Signals Power Vcc 20 Ground GND 66 Clock gt PLL 3 Address bus 18 Data bus Port A 24 Bus control 13 Interrupt and mode control 5 Host interface H108 Port B 16 Enhanced synchronous serial interface ESSI Ports C and D 12 Serial communication interface SCI Port E 3 Timer 3 OnCE JTAG Port 6 Note 1 PortA signals define the external memory interface port including the external address bus data bus and control signals 2 Port B signals are the HIO8 port signals multiplexed with the GPIO signals 3 Por
209. ating that the FIFO is empty A write to the FDIR clears the FDIBE bit Data transfers can be triggered by an interrupt request for core transfers or a DMA request for DMA transfers The FDIR is accessible for writes by the DSP56300 core and the DMA controller 10 4 2 Filter Data Output Register FDOR The FDOR is a 24 bit read only register for EFCOP to DSP data transfers The result of the filter processing is transferred from the FMAC to the FDOR For proper operation read data from the FDOR only if the FDOBF status bit is set indicating that the FDOR contains data A read from the FDOR clears the FDOBF bit Data transfers can be triggered by an interrupt request for core transfers or a DMA request DMA transfers The FDOR is accessible for reads by the DSP56300 core and the DMA controller DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 35 Enhanced Filter Coprocessor 10 4 3 Filter K Constant Input Register FKIR The Filter K Constant Input Register FKIR is a 24 bit write only register for DSP to EFCOP data transfers in adaptive mode where the value stored in FKIR represents the weight update multiplier FKIR is accessible only to the DSP core for reads or writes When adaptive mode is enabled the EFCOP immediately starts the coefficient update if a K Constant value is written to FKIR If no value is written to FKIR for the current data sample the EFCOP halts processing until the K Constant is written to FKIR Aft
210. atio of one DC 00000 provides continuous periodic data word transfers A bit length frame sync must be used in this case you select it by setting the FSL 1 0 bits in the CRA to 01 Figure 7 4 shows the ESSI frame sync generator functional block diagram 11 PSR Prescaler Range Controls a fixed divide by eight prescaler in series with the variable prescaler This bit extends the range of the prescaler when a slower bit clock is needed When PSR is set the fixed prescaler is bypassed When PSR is cleared the fixed divide by eight prescaler is operational as in Figure 7 3 This definition is reversed from that of the SSI in other DSP56000 family members The maximum allowed internally generated bit clock frequency is the internal DSP56311 clock frequency divided by 4 the minimum possible internally generated bit clock frequency is the DSP56311 internal clock frequency divided by 4096 Note The combination PSR 1 and PM 7 0 00 dividing Foore by 2 can cause synchronization problems and thus should not be used 10 8 Reserved Write to 0 for future compatibility 7 0 PM 7 0 Prescale Modulus Select Specify the divide ratio of the prescale divider in the ESSI clock generator A divide ratio from 1 to 256 PM 0 to FF can be selected The bit clock output is available at the transmit clock signal SCK and or the receive clock SCO signal of the DSP The bit clock output is also available internal
211. atus bit 4 word deep input data buffer for maximum performance EFCOP shared and core shared 12 K word filter data memory bank and 12 K word filter coefficient memory bank Two memory bank base address pointers one for data memory shared with X memory and one for coefficient memory shared with Y memory I O data transfers via core or DMA with minimal core intervention Core concurrent operation with minimal core intervention 10 2 Architecture Overview As Figure 10 1 shows the EFCOP comprises these main functional blocks 10 2 Peripheral module bus PMB interface including Data input buffer Constant input buffer Output buffer Filter counter Filter data memory FDM bank Filter coefficient memory FCM bank Filter multiplier accumulator FMAC machine Address generator Control logic DSP56311 Reference Manual Rev 2 Freescale Semiconductor Architecture Overview DMA BUS iia GDB BUS Interface Y Memory Shared 4 Word FDIR Data Input Buffer FONT RAM Control Filter Count a Logic a FCBA 1 FCM I Be eat ee Coeff Base Ad I I l FDM l FDBA COEFFICIENT X Memor Shared k l r Data Base Ad mo Memory Bank I RAM UA I 24 bit Memory Bank Address Ea ae J 24 bit l Generator i L I sl FMA FKIR E Filter Constant p 24x24 gt 56 bit gt Rounding amp Limiting
212. aya tae haya ch RE Na EA ie heed Raat Bea As 10 2 DSP56311 User s Manual Rev 2 ix Freescale Semiconductor Contents 10 2 1 10 2 2 10 2 3 10 3 10 3 1 10 3 2 10 3 2 1 10 3 2 2 10 3 3 10 3 3 1 10 3 3 1 1 10 3 3 1 2 10 3 3 1 3 10 3 3 1 4 10 3 3 2 10 3 3 2 1 10 3 3 2 2 10 3 3 2 3 10 3 3 2 4 10 3 4 10 3 5 10 3 6 10 3 6 1 10 3 6 1 1 10 3 6 1 2 10 3 6 1 3 10 3 6 2 10 3 6 3 10 3 6 3 1 10 3 6 3 2 10 3 6 3 3 10 3 6 4 10 3 6 4 1 10 3 6 4 2 10 3 6 4 3 10 3 6 4 4 10 3 6 4 5 10 4 10 4 1 10 4 2 10 4 3 10 4 4 10 4 5 10 4 6 10 4 7 10 4 8 10 4 9 10 4 10 PMB Inte rt ace 2 aiostar torioa e ana de Mgtlie aye dit mda Aye dada s 10 3 EFCOP Memory Banks circa lew tase Bove native e eae tens BAe ee weak 10 4 Filter Multiplier and Accumulator FMAC 0 0 eee ene 10 5 BPCOP Op r tiois s sranna nmr a ae ea ee gene wal hee Sie eas wala es 10 6 EFCOP Operation Summary 0 0 ccc cece cece eens 10 7 EECOP Initialization dps dod eget tinged east Sinan A A ote Ge Auge espa td cues 10 7 PIR Initialization cocino ES eee ee eee ed eo ee ada tes 10 7 HR Initialization di di di tati wet 10 7 BIR Filter Type ri ole ee avo A ee Soa A ear E 10 8 FIR Operating Modestas notere sot die A AAE AAE E O digiend EAER 10 8 Real Mode 9 3 0 nb Pee in ba a e Pt he e o Gees 10 8 Complex Mode cf cscs an dn dt lg 10 9 Alternating Complex Mode 0 0 cece cece eee 10 9 Masnitide Mode ccc ies eh ditty bie 10
213. be 16 32 or 40 bits and always originate from data ALU registers The results of all data ALU operations are stored in an accumulator Data ALU operations are performed in two clock cycles in a pipeline so that a new instruction can be initiated in every clock cycle yielding an effective execution rate of one instruction per clock cycle The destination of every arithmetic operation can be a source operand for the immediately following operation without penalty 1 6 1 2 Multiplier Accumulator MAC The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands For arithmetic instructions the unit accepts as many as three input operands and outputs one 56 bit result of the following form extension most significant product least significant product EXT MSP LSP The multiplier executes 24 bit x 24 bit parallel fractional multiplies between twos complement signed unsigned or mixed operands The 48 bit product is right justified and added to the 56 bit contents of either the A or B accumulator A 56 bit result can be stored as a 24 bit operand The LSP is either truncated or rounded into the MSP Rounding is performed if specified 1 6 2 Address Generation Unit AGU The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers that generate the addresses It implements four types of ari
214. bes the DSP56311 24 bit digital signal processor DSP its memory operating modes and peripheral modules The DSP56311 is an implementation of the DSP56300 core with a unique configuration of internal memory cache and peripherals Use this manual in conjunction with the DSP56300 Family Manual DSP56300FM which describes the CPU core programming models and instruction set The DSP56311 Technical Data DSP56311 referred to as the data sheet provides DSP56311 electrical specifications timing pinout and packaging descriptions You can obtain these documents and the Freescale DSP development tools through a local Freescale Semiconductor Sales Office or authorized distributor To receive the latest information on this DSP access the Freescale web site at the address listed on the back cover of this manual 1 1 Manual Organization This manual contains the following sections and appendices E Chapter 1 DSP56311 Overview Features list and block diagram related documentation organization of this manual and the notational conventions used E Chapter 2 Signals Connections DSP56311 signals and their functional groupings E Chapter 3 Memory Configuration DSP56311 memory spaces RAM configuration memory configuration bit settings memory configurations and memory maps E Chapter 4 Core Configuration Registers for configuring the DSP56300 core when programming the DSP56311 in particular the interrupt vector locations and the o
215. bit 7 18 Receive Frame Sync Flag RFS 7 27 Receive Interrupt Enable RIE bit 7 18 Receive Last Slot Interrupt Enable RLIE bit 7 18 Receive Request Enable RREQ bit 6 24 Receive Shift Register 7 28 Receive Slot Mask Registers RSMA and RSMB 7 12 7 33 Receive with Exception Interrupt Enable REIE bit 8 11 Received Bit 8 R8 bit 8 15 Receiver Enable RE bit 8 13 Receiver Overrun Error Flag ROE 7 27 Receiver Wakeup Enable RWU bit 8 13 register banks 6 4 RESET 2 8 reset bus signals 2 5 2 6 clock signals 2 4 interrupt signals 2 8 JTAG signals 2 19 mode control 2 8 OnCE signals 2 19 PLL signals 2 4 resets hardware and software 6 3 ROM bootstrap 1 6 3 1 3 3 Rounding Mode RM bit 4 6 RX clock 7 10 RXH RXM RXL registers 6 27 S saturation status bit 10 2 Scaling S bit 4 9 Scaling S Mode bits 4 8 SCI 2 2 2 17 SCI Clock Control Register SCCR 8 8 8 17 bit definitions 8 17 Clock Divider CD 8 17 Clock Out Divider COD 8 17 Clock Prescaler SCP 8 17 programming sheet B 30 Receive Clock Mode Source RCM 8 17 Transmit Clock Source TCM 8 17 SCI Clock Polarity SCKP bit 8 11 SCI Control Register SCR 8 8 8 10 bit definitions 8 11 DSP56311 User s Manual Rev 2 Freescale Semiconductor Index 11 Index Idle Line Interrupt Enable ILIE 8 12 programming sheet B 29 Receive with Exception Interrupt Enable REIE 8 11 Receiver Enable RE 8 13 Receiver Wakeup Enable RWU 8 13 SCI Clock Pol
216. ble BME 4 24 Bus Page Logic Enable BPLE 4 24 Bus Refresh Enable BREN 4 23 Bus Refresh Prescaler BRP 4 23 Bus Refresh Rate BRF 4 23 Bus Row Out of Page Wait States BRW 4 24 Bus Software Triggered Reset BSTR 4 23 programming sheet B 18 DS 2 2 DSP core programming model 6 11 DSP56300 core 1 1 Family Manual 1 1 1 5 6 8 Index DSP56311 Technical Data 1 1 DSP to host data word 6 2 handshaking protocols 6 2 interrupts 6 2 mapping 6 2 transfer modes 6 2 transfers 6 5 6 20 dynamic memory configuration switching 3 7 E echo cancellation 10 1 EFCOP ALU Control Register FACR programming sheet B 39 EFCOP Coefficient Base Address FCBA register programming sheet B 39 EFCOP Control Status Register FCSR programming sheet B 38 EFCOP Counter FCNT programming sheet B 38 EFCOP Data Base Address FDBA register programming sheet B 39 EFCOP Decimation Channel FDCH Count Register programming sheet B 39 Enhanced Filter Coprocessor EFCOP 1 2 1 14 10 1 control and status registers 10 3 core transfers 10 2 Decimation Channel Count Register FDCH 10 42 Decimation Channel Counter Register FDCH 10 42 Filter Channels FCHL 10 42 Filter Decimation FDCM 10 42 DMA restrictions 10 4 DMA transfers 10 2 features 10 1 Filter ALU Control Register FACR 10 40 Filter Input Scale FISL 10 40 Filter Rounding Mode FRM 10 40 Filter Saturation Mode FSM 10 40 Filter Scaling FSCL 10 41 Filter Coefficient Base Address FC
217. ble TOIE 9 27 Timer Reload Mode TRM 9 25 Timer Count Register TCR 9 29 Timer Load Registers TLR 9 28 Timer Prescaler Count Register TPCR 9 23 Prescaler Counter Value PC 9 23 Timer Prescaler Load Register TPLR 9 22 bit definitions 9 23 Prescaler Preload Value PL 9 23 Prescaler Source PS 9 23 Timer Compare Flag TCF bit 9 24 Timer Compare Interrupt Enable TCIE bit 9 27 Timer Compare Register TCPR 9 4 9 28 Timer Control TC bits 9 26 Timer Control Status Register TCSR 9 3 9 24 bit definitions 9 24 Data Input DI 9 25 Data Output DO 9 25 Direction DIR 9 25 Inverter INV 9 25 9 27 Prescaler Clock Enable PCE 9 24 programming sheet B 32 Timer Compare Flag TCF 9 24 Timer Compare Interrupt Enable TCIE 9 27 Timer Control TC 9 26 Timer Enable TE 9 27 Timer Overflow Flag TOF 9 24 Timer Overflow Interrupt Enable TOIE 9 27 Timer Reload Mode TRM 9 25 Timer Count Register TCR 9 29 Timer Enable TE bit 9 27 Timer Interrupt Enable TMIE bit 8 11 Timer Interrupt Priority Level TOL bits 4 15 Timer Interrupt Rate STIR bit 8 11 Timer Load Registers TLR 9 4 9 28 programming sheet B 33 Timer module architecture 9 1 timer block diagram 9 2 Timer Overflow Flag TOF bit 9 24 Timer Overflow Interrupt Enable TOIE bit 9 27 Timer Prescaler Count Register TPCR 9 23 bit definitions 9 23 Prescaler Counter Value PC 9 23 Timer Prescaler Load Register TPLR 9 4 9 22 bit definitions 9 23 Prescale
218. bus and when SRXH is read the contents of SRX are placed into the high byte with the remaining bits are read as Os This way of mapping SRX efficiently packs three bytes into one 24 bit word by ORing three data bytes read from the three addresses The SCR WDSO WDS1 and WDS2 control bits define the length and format of the serial word The SCR receive clock mode RCM defines the clock source DSP56311 User s Manual Rev 2 8 20 Freescale Semiconductor SCI Programming Model In Asynchronous mode the start bit the eight data bits the address data indicator bit or the parity bit and the stop bit are received respectively Data bits are sent LSB first if SSFTD is cleared and MSB first if SSFTD is set In Synchronous mode a gated clock provides synchronization In either Synchronous or Asynchronous mode when a complete word is clocked in the contents of the shift register can be transferred to the SRX and the flags RDRF FE PE and OR are changed appropriately Because the operation of the receive shift register is transparent to the DSP the contents of this register are not directly accessible to the programmer 8 6 4 2 SCI Transmit Register STX The transmit data register is a one byte wide register mapped into four addresses as STXL STXM STXH and STXA In Asynchronous mode when data is to be transmitted STXL STXM and STXH are used When STXL is written the low byte on the data bus is transferred to the STX When STXM is w
219. c Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 1 10 0 0 64K 32K 32K None 16M 0000 FFFF 0000 7FFF 0000 7FFF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the EFCOP but not by the DMA controller Figure 3 7 Memory Switch On MSW 10 Cache Off 24 Bit Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor 3 15 Memory Configuration Program X Data Y Data FFFFFF FFFFFF SFFFFFF External I O Internal O SFFFFCO FFFF80 FFFFSO Internal I O SFFFODO SEFFODO Internal Reserved Internal Internal Reserved Reserved FFOOCO FF0000 Bootstrap ROMI FF0000 FF0000 External External External 00C000 801000 00C000 00C000 Internal Reserved Program RAM 008000 008000 63K 000400 Internal X data Internal Y data sooo000 L_Reserved 000000 L_RAM32K_ go00000 __RAM 32K Bit Settings Memory Configuration MS MSW cE sc Program RAM X Data RAM YDataRAM Cache Addressable 1 0 Memory Size 10 1 0 63K 32K 32K Enabled 16M 0400 FFFF 0000 7FFF 0000 7FFF EF e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the COP but not by the DMA controller 3 16 Figure 3 8 Memory Switch On MSW 10 Cache On 24 Bit Mode DSP5
220. cale Semiconductor Programming Reference This reference for programmers includes a table showing the addresses of all DSP memory mapped peripherals an exception priority table and programming sheets for the major programmable DSP registers The programming sheets are grouped in the following order central processor Phase Lock Loop PLL Host Interface HI08 Enhanced Synchronous Serial Interface ESSI Serial Communication Interface SCI Timer and GPIO Each sheet provides room to write in the value of each bit and the hexadecimal value for each register You can photocopy these sheets and reuse them for each application development project For details on the instruction set of the DSP56300 family of DSPs see the DSP56300 Family Manual E Table B 2 Internal I O Memory Map X Data Memory on page B 2 lists the memory addresses of all internal peripherals E Table B 4 Interrupt Sources on page B 8 lists the interrupt starting addresses and sources E Table B 5 Interrupt Source Priorities Within an IPL on page B 10 lists the priorities of specific interrupts within interrupt priority levels E The programming sheets appear in this manual as figures listed in Table B 1 they show the major programmable registers on the DSP56311 Table B 1 Guide to Programming Sheets Module Programming Sheet Page Central Figure B 1 Status Register SR page B 12 PIQePeeor Figure B 2 Operat
221. can be independent of and asynchronous to the DSP system clock it must exceed the minimum clock cycle time of 6 T that is the system clock frequency must be at least three times the external ESSI clock frequency The ESSI needs at least three DSP phases inside each half of the serial clock PD3 Input or Output Port D3 The default configuration following reset is GPIO For PD3 signal direction is controlled through PRRD This signal is configured as SCK1 or PD3 through PCRD This input is 5 V tolerant SRD1 Input Ignored input Serial Receive Data Receives serial data and transfers the data to the ESSI receive shift register SADO is an input when data is being received PD4 Input or Output Port D 4 The default configuration following reset is GPIO For PD4 signal direction is controlled through PRRD This signal is configured as SRD1 or PD4 through PCRD This input is 5 V tolerant STD1 Output Ignored input Serial Transmit Data Transmits data from the serial transmit shift register STD1 is an output when data is being transmitted PD5 Input or Output Port C 5 The default configuration following reset is GPIO For PD5 signal direction is controlled through PRRD This signal is configured as STD1 or PD5 through PCRD This input is 5 V tolerant Notes 1 Inthe Stop state the signal maintains the last state as follows 2 16 e Ifthe last state is input the signal is an ignored input e Ifthe last state is output these lines are tri s
222. cated at address 5 the RXM TXM register at 6 and the RXL TXL register at 7 If the HLEND bit is set the RXH TXH register is located at address 7 the RXM TXM register at 6 and the RXL TXL register at 5 HF1 Host Flag 1 A general purpose flag for host to DSP communication The host processor can set or clear HF1 and the DSP56311 can not change it HF1 is reflected in the HSR on the DSP side of the HI08 HFO Host Flag 0 A general purpose flag for host to DSP communication The host processor can set or clear HFO and the DSP56311 cannot change it HFO is reflected in the HSR on the DSP side of the HI08 HDRQ Double Host Request If cleared the HDRQ bit configures HREQ HTRQ and HACK HRRQ as HREQ and HACK respectively If HDRQ is set HREQ HTRQ is configured as HTRQ and HACK HRRQ is configured as HRRQ Freescale Semiconductor DSP56311 User s Manual Rev 2 6 23 Host Interface HI08 Table 6 15 Interface Control Register ICR Bit Definitions Continued Bit Number Bit Name Reset Value Description 1 TREQ 0 Transmit Request Enable Enables host requests via the host request HREQ or HTRQ signal when the transmit data register empty TXDE status bit in the ISR is set If TREQ is cleared TXDE interrupts are disabled If TREQ and TXDE are set the host request signal is asserted TREQ and RREQ modes HDRQ 0 TREQ RREQ HREQ Signal 0 0 No in
223. ccess time 4 6 2 DRAM Control Register DCR The DRAM controller is an efficient interface to dynamic RAM devices in both random read write cycles and Fast Access mode Page mode An on chip DRAM controller controls the page hit circuit the address multiplexing row address and column address the control signal generation CAS and RAS and the refresh access generation CAS before RAS for a variety of DRAM module sizes and access times The on chip DRAM controller configuration is determined by the DRAM Control Register DCR The DRAM Control Register DCR is a 24 bit read write register that controls and configures the external DRAM accesses The DCR bits are shown in Figure 4 7 DSP56311 User s Manual Rev 2 4 22 Freescale Semiconductor Bus Interface Unit BIU Registers Note To prevent improper device operation you must guarantee that all the DCR bits except BSTR are not changed during a DRAM access 23 22 21 20 19 18 17 16 15 14 13 12 BRP BRF7 BRF6 BRF5 BRF4 BRF3 BRF2 BRF1 BRFO BSTR BREN BME 11 10 9 8 7 6 5 4 3 2 1 0 BPLE BPS1 BPSO BRW1 BRWO BCW1 BCWO Reserved bit Read as zero write to zero for future compatibility Figure 4 7 DRAM Control Register DCR Table 4 9 DRAM Control Register DCR Bit Definitions Bit 4 Reset a Number Bit Name Value Description 23 BRP 0 Bus Refresh Prescaler Controls a p
224. ce eee e eens 6 24 Interface Status Register ISR 1 0 0 0 cee eenenneneeas 6 25 Interrupt Vector Register IVR 0 a E E cece teen e beeen a 6 27 Receive Data Registers RXH RXM RXL 0 0 een eens 6 27 Transmit Data Registers TXH TXM TXL 0 0 0 ce eens 6 28 Host Side Registers After Reset nsise rieo A a p a E A A 6 28 Programming Model Quick Reference 0 0 0 0 cece eee 6 29 Enhanced Synchronous Serial Interface ESSI ESSI Enhancements 22 03 3450 eet bebe A a a edo ees 7 2 ESSI Data and Control Signals 1 0 ec ene ene e eens 7 2 Serial Transmit Data Signal STD 0 n eens 7 2 Serial Receive Data Signal SRD 0 0 0 ccc cette nee nee 7 3 Serial Clock SCE o Dio io be ies 7 3 serial Control Strena COn ad A a tng a 7 3 DSP56311 User s Manual Rev 2 vii Freescale Semiconductor Contents 7 2 5 Serial Control Siena Clonar do gid tii dd ok won le 7 4 7 2 6 Serial Control Signal SEL ati ii wh wale Tee da 7 5 7 3 Operations rA en ase o A E E ee A hon Ee E 7 6 7 3 1 ESST After Resets hve gas br hyn a a id a agains 7 6 7 3 2 Tiitiali zaioen Deedes i E ad e a a a e 7 6 7 3 3 EXCODUODS ves A A A Gu stacha o ER ane 7 7 7 4 Operating Modes Normal Network and On Demand 0 0 00 e eee eee eee 7 9 7 4 1 Normal Network On Demand Mode Selection 0 0 c eee cece ee eee 7 9 7 4 2 Synchronous Asynchronous Operating Modes 0 0 00 ce eee cece eee 7 10 7
225. ce nurnure 3 6 Internal Y VO Space somos aria el Redeye Boxee Rohe gt Neat AR 3 7 External Y V OSpace s recane naaca a ne erari ah el a ead las 3 7 Dynamic Memory Configuration Switching 0 0 0 0 eee ccc eee 3 7 Sixteen Bit Compatibility Mode Configuration 0 0 0 0 cece cee eee ee 3 8 Memory Maps ud ey eroding Be te tes ag See Ne ee ED ek 3 8 Core Configuration Operating Modes i ieoa oot oeiy E A tay DO A Bare Te eee Saas BA 4 1 Bootstrap Progra ri iio ts ews Sed laa Bae ee at eee la 4 4 Central Processor Unit CPU Registers 0 0 anneuenn nnana 4 4 Stat s Register Rosi pate A Peeping A tesa Masaka anaes aa ds 4 4 Operating Mode Register OMR 0 cece rr 4 10 Configuring Interrupts a io Meigen wea RR age eee eS 4 14 Interrupt Priority Registers IPRC and IPRP 0 0 cece eee eee 4 14 Interrupt Table Memory Map 20 0 cece cece A ene n eae 4 15 Processing Interrupt Source Priorities Within an IPL 2 2 eee eee 4 17 PELE Control Register POCTE siian id da di Gage eh Mes 4 19 Bus Interface Unit BIU Registers 0 0 0 cent neneas 4 20 Bus Control Registers mnre erro pe ts E ta oia EAA EA 4 20 DRAM Control Register DCR 0 0 nuanean nerea 4 22 Address Attribute Registers AAR 0 3 0 cece ene 4 25 DMA Control Registers 5 0 DCR 5 O 2 0 nane 4 27 Device Identification Register IDR 0 0 0 cc eee een eens 4 32 JTAG Identification ID
226. chine starts computing once the FDM bank contains N input samples for an N tap filter When this bit is set the EFCOP starts processing with no state initialization The EFCOP machine starts computing as soon as the first data sample is available in the input buffer To ensure proper operation never change the FPRC bit unless the EFCOP is in individual reset state that is FEN 0 6 FMLC 0 Filter Multichannel FMLC Mode This read write control bit enables multichannel mode allowing the EFCOP to process several filters defined by FCHL 5 0 bits in FDCH register concurrently by sequentially entering a different sample to each filter If FMLC is cleared multichannel mode is disabled and the EFCOP operates in single filter mode To ensure proper operation never change the FMLC bit unless the EFCOP is in individual reset state that is FEN 0 DSP56311 Reference Manual Rev 2 10 38 Freescale Semiconductor EFCOP Programming Model Table 10 7 FCSR Bits Continued Bit Number Bit Name Reset Value Description 5 4 FOM 1 0 Filter Operation Mode This pair of read write control bits defines one of four operation modes if the FIR filter is selected that is FLT is cleared e FOM 00 Mode 0 Real FIR filter e FOM 01 Mode 1 Full complex FIR filter e FOM 10 Mode 2 Complex FIR filter with alternate real and imaginary outputs e FOM 11 Mode 3 Magnitude To en
227. chitecture operation and programming model 10 1 Features E Fully programmable real complex filter machine with 24 bit resolution E FIR filter options Four modes of operation with optimized performance e Mode 0 FIR machine with real taps e Mode 1 FIR machine with complex taps e Mode 2 Complex FIR machine generating pure real imaginary outputs alternately e Mode 3 Magnitude calculate the square of each input sample 4 bit decimation factor in FIR filters providing up to 1 16 decimation ratio Easy to use adaptive mode supporting true or delayed LMS type algorithms K constant input register for coefficient updates in adaptive mode E IIR filter options Direct form 1 DFI and direct form 2 DFI configurations Three optional output scaling factors 1 8 or 16 DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 1 Enhanced Filter Coprocessor Multichannel mode to process multiple equal length filter channels up to 64 simultaneously with minimal core intervention Optional input scaling for both FIR and IIR filters Two filter initialization modes No initialization Data initialization Sixteen bit arithmetic mode support Three rounding options available No rounding Convergent rounding Two s complement rounding Arithmetic saturation mode support for bit exact applications Sticky saturation status bit indication Sticky data coefficient transfer contention st
228. clocking and can interrupt the DSP after a specified number of events clocks or signal an external device after counting internal events E Connection to the external world through one bidirectional signal When this signal is configured as an input the timer functions as an external event counter or measures external pulse width signal period When the signal is used as an output the timer functions as either a timer a watchdog or a pulse width modulator 1 9 6 EFCOP The EFCOP interfaces with the DSP core via the peripheral module bus It is a general purpose fully programmable coprocessor that performs filtering tasks concurrently with the DSP core with minimum core overhead The DSP core and the EFCOP can share data via an 8K word shared data memory DMA channels shuttle input and output data between the DSP core and the EFCOP The EFCOP supports a variety of filter modes some of which are optimized for cellular base station applications Real finite impulse response FIR with real taps Complex FIR with complex taps Complex FIR generating pure real or pure imaginary outputs alternately A 4 bit decimation factor in FIR filters thus providing a decimation ratio up to 16 Direct form 1 DFD infinite impulse response IIR filter Direct form 2 DFID IIR filter Four scaling factors 1 4 8 16 for IIR output Adaptive FIR filter with true least mean square LMS coefficient updates Adaptive FIR filter with delayed LMS coefficient upd
229. contained by the TCR In PWM mode 7 the counter is reloaded each time counter overflow occurs In measurement 4 5 modes if the TRM and the TCSR TE bits are set the counter is preloaded with the TLR value on each appropriate edge of the input signal If the TRM bit is cleared the counter operates as a free running counter and is incremented on each incoming event 8 INV 0 Inverter Affects the polarity definition of the incoming signal on the TIO signal when TIO is programmed as input It also affects the polarity of the output pulse generated on the TIO signal when TIO is programmed as output See Table 9 4 Inverter INV Bit Operation on page 9 27 The INV bit does not affect the polarity of the prescaler source when the TIO is input to the prescaler Note The INV bit affects both the timer and GPIO modes of operation To ensure correct operation change this bit only when one or both of the following conditions is true the timer is disabled the TCSR TE bit is cleared The timer is in GPIO mode DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 25 Triple Timer Module Table 9 3 Timer Control Status Register TCSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 7 4 TC 3 0 0 Timer Control Control the source of the timer clock the behavior of the TIO signal and th
230. cted The IFO bit is updated with this data when the data in the receive shift register transfers into the receive data register IFO is enabled only when SCO is an input flag and the Synchronous mode is selected that is when SCO is programmed as ESSI in the port control register PCR the SYN bit is set and the TE1 and SCDO bits are cleared If it is not enabled the IFO bit is cleared 7 5 4 ESSI Receive Shift Register The 24 bit Receive Shift Register see Figure 7 12 and Figure 7 13 receives incoming data from the serial receive data signal The selected internal external bit clock shifts data in when the associated frame sync I O is asserted Data is received MSB first if SHFD is cleared and LSB first if SHFD is set Data transfers to the ESSI Receive Data Register RX after 8 12 16 24 or 32 serial clock cycles are counted depending on the word length control bits in the CRA 7 5 5 ESSI Receive Data Register RX The Receive Data Register RX is a 24 bit read only register that accepts data from the receive shift register as it becomes full according to Figure 7 12 and Figure 7 13 The data read is aligned according to the value of the ALC bit When the ALC bit is cleared the MSB is bit 23 and the least significant byte is unused When the ALC bit is set the MSB is bit 15 and the most significant byte is unused Unused bits are read as 0 If the associated interrupt is enabled the DSP is interrupted whene
231. ction of the SC1 I O signal When SCD1 is set SC1 is an output when SCD1 is cleared SC1 is an input When TE2 is set the value of SCD1 is ignored and the SC1 signal is always an output SCDO Serial Control Direction 0 In Synchronous mode SYN 1 when transmitter 1 is disabled TE1 0 or in Asynchronous mode SYN 0 SCDO controls the direction of the SCO I O signal When SCDO is set SCO is an output when SCDO is cleared SCO is an input When TE1 is set the value of SCDO is ignored and the SCO signal is always an output OF1 Serial Output Flag 1 In Synchronous mode SYN 1 when transmitter 2 is disabled TE2 0 the SC1 signal is configured as ESSI flag 1 When SCD1 is set SC1 is an output Data present in bit OF1 is written to SC1 at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode OFO Serial Output Flag 0 In Synchronous mode SYN 1 when transmitter 1 is disabled TE1 0 the SCO signal is configured as ESSI flag 0 When SCDO is set the SCO signal is an output Data present in Bit OFO is written to SCO at the beginning of the frame in Normal mode or at the beginning of the next time slot in Network mode DSP56311 User s Manual Rev 2 7 22 Freescale Semiconductor ESSI Programming Model Word Length FSL1 0 FSLO 0 Serial Clock RX TX Frame A EN RX TX Serial Data NOTE Frame sync occurs while data is
232. d 1 Mapped to Y memory Stack Extension Underflow Flag Bit 17 Core DMA Priority Bits 9 8 0 No stack underflow CPD 1 0 1 Stack underflow Description 00 Compare SR CP to active DMA channel Stack Extension Overflow Flag Bit 18 riorit 0 No stack overflow Paca 1 Stack overflow DMA has higher priority than core Stack Extension Wrap Flag Bit 19 DMA has same 0 No stack extension wrap priority as core 1 Stack extension wrap sticky bit DMA has lower priority than core Stack Extension Enable Bit 20 0 Stack extension disabled Cache Burst Mode Enable Bit 10 1 Stack extension enabled 0 Burst Mode disabled 1 Burst Mode enabled Memory Switch Configuration Bits 22 21 Refer to the memory maps in Chapter 3 for TA Synchronize Select Bit 11 details 0 Not synchronized 1 Synchronized Bus Release Timing Bit 12 0 Fast Bus Release mode 1 Slow Bus Release mode EN E Operating Mode Register Reserved Program as 0 Reset 00030X X latched from levels on Mode pins Figure B 2 Operating Mode Register OMR DSP56311 User s Manual Rev 2 Freescale Semiconductor B 13 Programming Reference Application Date Programmer Sheet 1 of 2 Interrupt Priority EM ASTER IRQD Mode D5L0 Enabled 0 Trigger IDL1 IDLO Enabled Level 0 0 0 Neg
233. d and the DSP begins execution with the first instruction loaded 8 5 Exceptions The SCI can cause five different exceptions in the DSP discussed here from the highest to the lowest priority 1 SCI receive data with exception status occurs when the receive data register is full with a receiver error parity framing or overrun error To clear the pending interrupt read the SCI status register then read SRX Use a long interrupt service routine to handle the error condition This interrupt is enabled by SCR 16 REIE SCI receive data occurs when the receive data register is full Read SRX to clear the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead This interrupt is enabled by SCR 11 RIE SCI transmit data occurs when the transmit data register is empty Write STX to clear the pending interrupt This error free interrupt can use a fast interrupt service routine for minimum overhead This interrupt is enabled by SCR 12 TIE SCI idle line occurs when the receive line enters the idle state 10 or 11 bits of ones This interrupt is latched and then automatically reset when the interrupt is accepted This interrupt is enabled by SCR 10 ILIB SCI timer occurs when the baud rate counter reaches zero This interrupt is automatically reset when the interrupt is accepted This interrupt is enabled by SCR 13 TMIE 8 6 SCI Programming Model The SCI programming model
234. d unmasked before the SCI can operate The order does not matter any one of these three requirements for interrupts can enable the SCI but the interrupts should be unmasked last that is I 1 0 bits in the Status Register SR should be changed last Synchronous applications usually require exact frequencies so the crystal frequency must be chosen carefully An alternative to selecting the system clock to accommodate the SCI requirements is to provide an external clock to the SCI When the SCI is configured in Synchronous mode internal clock and all the SCI pins are simultaneously enabled an extra pulse of one DSP clock length is provided on the SCLK pin There are two workarounds for this issue E Enable an SCI pin other than SCLK E In the next instruction enable the remaining SCI pins including the SCLK pin Following is an example of one way to initialize the SCI 1 Ensure that the SCI is in its individual reset state PCRE 0 2 Configure the control registers SCR SCCR according to the operating mode but do not enable transmitter TE 0 or receiver RE 0 Note It is now possible to set the interrupts enable bits that are used during the operation No interrupt occurs yet 3 Enable the SCI by setting the PCRE bits according to which signals are used during operation 4 If transmit interrupt is not used write data to the transmitter Note If transmitter interrupt enable is set an interrupt is issued and t
235. data is transferred when the data strobe is low If HDSP is set the data strobe signals are configured as active high inputs and data is transferred when the data strobe is high The data strobe signals are either HDS by itself or both HRD and HWR together HROD Host Request Open Drain Controls the output drive of the host request signals In the single host request mode that is when HDRQ is cleared in ICR if HROD is cleared and host requests are enabled that is if HREN is set and HEN is set in the host port control register HPCR then the HREQ signal is always driven by the HIO8 If HROD is set and host requests are enabled the HREQ signal is an open drain output In the double host request mode that is wen HDRQ is set in the ICR if HROD is cleared and host requests are enabled that is if HREN is set and HEN is set in the HPCR then the HTRQ and HRRQ signals are always driven If HROD is set and host requests are enabled the HTRQ and HRRQ signals are open drain outputs Reserved Write to O for future compatibility HEN Host Enable If HEN is set the HIO8 operates as the host interface If HEN is cleared the HIO8 is not active and all the HI08 signals are configured as GPIO signals according to the value of the HDDR and HDR Freescale Semiconductor DSP56311 User s Manual Rev 2 Host Interface HI08 Table 6 12 Host Port Control Register HPCR Bit Definitions Continued B
236. delay M N clock TCF Compare Interrupt if TCIE 1 periods NOTE If INV 1 a 1 to 0 edge on TIO loads TCR with count and stops the counter Figure 9 15 Capture Measurement Mode TRM 0 DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 15 Triple Timer Module 9 3 3 Pulse Width Modulation Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 1 1 1 7 Pulse width modulation PWM Output Internal In Mode 7 the timer generates periodic pulses of a preset width When the counter equals the value in the TCPR the TIO output signal is toggled and TCSR TCF is set The contents of the counter are placed into the TCR If the TCSR TCIE bit is set a compare interrupt is generated The counter continues to increment on each timer clock If counter overflow occurs the TIO output signal is toggled TCSR TOF is set and an overflow interrupt is generated if the TCSR TOIE bit is set If the TCSR TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count resumes If the TCSR TRM bit is cleared the counter continues to increment on each timer clock This process repeats until the timer is disabled When the TCSR TE bit is set and the counter starts the TIO signal assumes the value of INV On each subsequent toggle of the TIO signal the polarity of the TIO signal is reversed For example if the INV bit is set the TIO s
237. ding AA RAS signal This is also true of 16 bit compatibility mode The BNC 3 0 bits define the number of address bits to compare 11 8 BNC 3 0 0 Bus Number of Address Bits to Compare Specify the number of bits from the BAC bits that are compared to the external address The BAC bits are always compared with the Most Significant Portion of the external address for example if BNC 3 0 0011 then the BAC 11 9 bits are compared to the 3 MSBs of the external address If no bits are specified that is BNC 3 0 0000 the AA signal is activated for the entire 16 M word space identified by the space enable bits BPEN BXEN BYEN but only when the address is external to the internal memory map The combinations BNC 3 0 1111 1110 1101 are reserved DSP56311 User s Manual Rev 2 Freescale Semiconductor 4 25 Core Configuration Table 4 10 Address Attribute Registers AAR O 3 Bit Definitions Bit Number Bit Name Reset Value Description 7 BPAC 0 Bus Packing Enable Enables disables the internal packing unpacking logic When BPAC is set packing is enabled In this mode each DMA external access initiates three external accesses to an 8 bit wide external memory the addresses for these accesses are DAB then DAB 1 and then DAB 2 Packing to a 24 bit word or unpacking from a 24 bit word to three 8 bit words is done automatically by the expansion port control hardware The exte
238. ductor Operating Modes 9 3 2 3 Measurement Capture Mode 6 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 1 1 0 6 Capture Measurement Input Internal In Mode 6 the timer counts the number of clocks that elapse between when the timer starts and when an external signal is received At the first appropriate transition of the external clock detected on the TIO signal TCSR TCF is set and if the TCSR TCIE bit is set a compare interrupt is generated The counter halts The contents of the counter are loaded into the TCR The value of the TCR represents the delay between the setting of the TCSR TE bit and the detection of the first clock edge signal on the TIO signal The value of the INV bit determines whether a high to low 1 to 0 or low to high 0 to 1 transition of the external clock signals the end of the timing period If the INV bit is set a high to low transition signals the end of the timing period If INV is cleared a low to high transition signals the end of the timing period Mode 6 internal clock TRM 1 N write preload event M write compare TE Clock CLK 2 or prescale CLK TLR Pa N Counter stops Counter 0 x N N 1 M N counting overflow may occur before capture TOF 1 TCR M TIO pin delay being measured Interrupt Service reads TCR
239. e Timer mode of operation Section 9 3 Operating Modes on page 9 5 describes the timer operating modes in detail To ensure proper operation the TC 3 0 bits should be changed only when the timer is disabled that is when the TCSR TE bit is cleared Note If the clock is external the counter is incremented by the transitions on the TIO signal The external clock is internally synchronized to the internal clock and its frequency should be lower than the internal operating frequency divided by 4 that is CLK 4 Bit Settings Mode Characteristics Tce3 TC2 Tc1 Too Mode hoor TIO Clock Number Function 0 0 0 0 0 Timer and GPIO Internal GPIO 1 0 0 0 1 1 Timer pulse Outpu Internal t 0 0 1 0 2 Timer toggle Outpu Internal t 0 0 1 1 3 Event counter Input Externa 0 1 0 0 4 Input width Input Internal measurement 0 1 0 1 5 Input period Input Internal measurement 0 1 1 0 6 Capture Input Internal event 0 1 1 1 7 Pulse width Outpu a Internal modulation t 1 0 0 0 8 Reserved OR 1 0 0 1 9 Watchdog Outpu nternal pulse t 1 0 1 0 10 Watchdog Outpu Internal Toggle t 1 0 1 1 11 Reserved 1 1 0 0 12 Reserved NN 1 1 0 1 13 Reserved 1 1 1 0 14 Reserved 1 1 1 1 15 Reserved e eS Note The GPIO function is enabled only if all of the TC 3 0 bits are O 3 0 Reserved Write to zero for future compatibility 9 26 DSP56311 User s Manual Rev 2 Freescale Semiconductor Triple Ti
240. e DSP or obtained from external sources If clocks are internally generated the ESSI clock generator derives bit clock and frame sync signals from the DSP internal system clock The ESSI clock generator consists of a selectable fixed prescaler with a programmable prescaler for bit rate clock generation and a programmable frame rate divider with a word length divider for frame rate sync signal generation 7 4 3 Frame Sync Selection The transmitter and receiver can operate independently The transmitter can have either a bit long or word long frame sync signal format and the receiver can have the same or another format The selection is made by programming the CRB FSL 1 0 FSR and FSP bits 7 4 4 Frame Sync Signal Format CRB FSL1 controls the frame sync signal format E If CRB FSL1 is cleared the receive frame sync is asserted during the entire data transfer period This frame sync length is compatible with Freescale codecs serial peripherals that conform to the Freescale SPI serial A D and D A converters shift registers and telecommunication pulse code modulation serial I O E If CRB FSL 1 is set the receive frame sync pulses active for one bit clock immediately before the data transfer period This frame sync length is compatible with Intel and National Semiconductor Corporation components codecs and telecommunication pulse code modulation serial I O 7 4 5 Frame Sync Length for Multiple Devices Mixing frame sync lengths is use
241. e TLR value on the first timer clock received following the next valid transition on the TIO input signal and the count resumes If TCSR TRM is cleared the counter continues to increment on each timer clock This process repeats until the timer is disabled Mode 4 internal clock TRM 1 first event N write preload 4 M write compare TE Clock A K J CLK 2 or prescale CLK TLR a ON P 4 Se Counter gt 0 lt NO OX Nelo M Next 0 to 1 edge on TIO loads counter and process repeats TCR TIO pin 7 width being measured 5 Interrupt Service TCF Compare Interrupt if TCIE 1 C pi e vo periods NOTE If INV 1 a 1 to 0 edge on TIO loads the counter and a 0 to 1 edge on TIO stops the counter and loads TCR with the count Figure 9 11 Pulse Width Measurement Mode TRM 1 DSP56311 User s Manual Rev 2 9 12 Freescale Semiconductor Operating Modes Mode 4 internal clock TRM 1 first event N write preload M write compare TE ce ITALIA LR CLK 2 or prescale CLK TLR N A Ss Counter O X lt N Ss N t M o ___ Next 0 to 1 edge TCR y o 2 ale EN l count and process TIO pin _ width being measured a Ree ean TOPS 1 A Interrupt Service TCF Compare Interrupt if TCIE 1 Ke fel reads TOR for accumulated width of M N clock periods NOTE If INV 1
242. e Value Description 23 DE 0 DMA Channel Enable Enables the channel operation Setting DE either triggers a single block DMA transfer in the DMA transfer mode that uses DE as a trigger or enables a single block single line or single word DMA transfer in the transfer modes that use a requesting device as a trigger DE is cleared by the end of DMA transfer in some of the transfer modes defined by the DTM bits If software explicitly clears DE during a DMA operation the channel operation stops only after the current DMA transfer completes that is the current word is stored into the destination Freescale Semiconductor DSP56311 User s Manual Rev 2 4 27 Core Configuration Table 4 11 DMA Control Register DCR Bit Definitions Continued Bit A Reset o Number Bit Name Value Description 22 DIE O DMA Interrupt Enable Generates a DMA interrupt at the end of a DMA block transfer after the counter is loaded with its preloaded value A DMA interrupt is also generated when software explicitly clears DE during a DMA operation Once asserted a DMA interrupt request can be cleared only by the service of a DMA interrupt routine To ensure that a new interrupt request is not generated clear DIE while the DMA interrupt is serviced and before a new DMA request is generated at the end of a DMA block transfer that is at the beginning of the DMA channel interrupt service routine When DIE is cleared the DMA interrupt is
243. e XTAL unconnected 2 4 PLL Table 2 5 Phase Lock Loop Signals State During Signal Name Type Signal Description Reset PCAP Input Input PLL Capacitor Connects an off chip capacitor to the PLL filter Connect one capacitor terminal to PCAP and the other terminal to Vcocp If the PLL is not used PCAP is tied to Voc GND or left floating CLKOUT Output Chip driven Clock Output Provides an output clock synchronized to the internal core clock phase If the PLL is enabled and both the multiplication and division factors equal one then CLKOUT is also synchronized to EXTAL If the PLL is disabled the CLKOUT frequency is half the frequency of EXTAL Note At operating frequencies above 100 MHz this signal produces a low amplitude waveform that is not usable externally by other devices Above 100 MHz you use the asynchronous bus arbitration option that is enabled by the Asynchronous Bus Arbitration Enable ABE bit in the Operating Mode Register OMR When set the DSP enters the Asynchronous Arbitration mode which eliminates the BB and BG setup and hold time requirements with respect to CLKOUT DSP56311 User s Manual Rev 2 2 4 Freescale Semiconductor External Memory Expansion Port Port A Table 2 5 Phase Lock Loop Signals Continued Signal Name Type State During Reset Signal Description PINIT zZ Input Input Input PLL In
244. e down Scale up Reserved Sixteen Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO Forever Flag Sixteen Bit Arithmetic Instruction Cache Enable Arithmetic Saturation Rounding Mode Core Priority Core Priority 0 lowest 1 2 3 highest NR ERP 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 Extended Mode Register EMR Mode Register MR Condition Code Register CCR Status Register SR Read Write Reset C00300 Reserved Program as 0 Figure B 1 Status Register SR DSP56311 User s Manual Rev 2 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 2 of 2 Asynchronous Bus Arbitration Enable Bit 13 z C e n t ra P roce SS O r 0 Synchronization disabled Chip Operating Mode Bits 3 0 Refer to the operating modes 1 Synchronization enabled table in Chapter 4 Address Attribute Priority Disable Bit 14 External Bus Disable Bit 4 0 Priority mechanism enabled 0 Enables external bus 1 Priority mechanism disabled 1 Disables external bus Address Trace Enable Bit 15 Stop Delay Mode Bit 6 0 Address Trace mode disabled 0 Delay is 128K clock cycles 1 Address Trace mode enabled 1 Delay is 16 clock cycless valid for 100 MHz or less only Memory Switch Mode Bit 7 Stack Extension X Y Select Bit 16 0 Memory switching disabled 0 Mapped to X memory 1 Memory switching enable
245. e is level triggered If the value is 1 the interrupt mode is negative edge triggered 4 4 2 Interrupt Table Memory Map Each interrupt is allocated two instructions in the interrupt table resulting in 128 table entries for interrupt handling Table 4 5 shows the table entry address for each interrupt source The DSP56311 initialization program loads the table entry for each interrupt serviced with two interrupt servicing instructions In the DSP56311 only some of the 128 vector addresses are used for specific interrupt sources The remaining interrupt vectors are reserved and can be used for DSP56311 User s Manual Rev 2 Freescale Semiconductor 4 15 Core Configuration host NMI IPL 3 or for host command interrupt IPL 2 Unused interrupt vector locations can be used for program or data storage Table 4 5 Interrupt Sources Interrupt priority Level Starting Address Range Interrupt Source VBA 00 3 Hardware RESET VBA 02 3 Stack error VBA 04 3 Illegal instruction VBA 06 3 Debug request interrupt VBA 08 3 Trap VBA 0A 3 Nonmaskable interrupt NMI VBA 0C 3 Reserved VBA 0E 3 Reserved VBA 10 0 2 IRQA VBA 12 0 2 IRQB VBA 14 0 2 IRQC VBA 16 0 2 IRQD VBA 18 0 2 DMA channel 0 VBA 1A 0 2 DMA channel 1 VBA 1C 0 2 DMA channel 2 VBA 1E 0 2 DMA channel 3 VBA 20 0 2 DMA channel 4 VBA 22 0 2 DMA channel 5
246. e is programmable but is configured as active low HWR following reset Port B 12 When the HI08 is configured as GPIO through the HPCR this signal is individually programmed through the HDDR HCS HA10 PB13 Input Input Input or Output Ignored Input Host Chip Select When the HI08 is programmed to interface with a non multiplexed host bus and the HI function is selected this signal is the Host Chip Select HCS input The polarity of the chip select is programmable but is configured active low HCS after reset Host Address 10 When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected this signal is line 10 of the Host Address bus Port B 13 When the HI08 is configured as GPIO through the HPCR this signal is individually programmed through the HDDR HREQ HREQ HTRQ HTRQ PB14 Output Output Input or Output Ignored Input Host Request When the HI08 is programmed to interface with a single host request host bus and the HI function is selected this signal is the Host Request HREQ output The polarity of the host request is programmable but is configured as active low HREQ following reset The host request can be programmed as a driven or open drain output Transmit Host Request When the HI08 is programmed to interface with a double host request host bus and the HI function is selected this signal is the Transmit Host Re
247. e modes are selected by the SCR WD 2 0 bits Synchronous data mode is essentially a high speed shift register for I O expansion and stream mode channel interfaces A gated transmit and receive clock compatible with the Intel 8051 serial interface mode O synchronizes data Asynchronous modes are compatible with most UART type serial devices Standard RS 232 communication links are supported by these modes Multidrop Asynchronous mode is DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 1 Serial Communication Interface SCI compatible with the MC68681 DUART the M68HC11 SCI interface and the Intel 8051 serial interface 8 1 1 Synchronous Mode Synchronous mode SCR WD2 0 000 Shift Register mode handles serial to parallel and parallel to serial conversions In Synchronous mode the clock is always common to the transmit and receive shift registers As a controller synchronous master the DSP puts out a clock on the SCLK pin To select master mode choose the internal transmit and receive clocks set TCM and RCM 0 As a peripheral synchronous slave the DSP accepts an input clock from the SCLK pin To select the slave mode choose the external transmit and receive clocks TCM and RCM 1 Since there is no frame signal if a clock is missed because of noise or any other reason the receiver loses synchronization with the data without any error signal being generated You can detect an error of this type with an error detecting p
248. e one filter output F n for a specific set of input data samples To transfer data to from the EFCOP input output registers the Filter Data Input Register FDIR and the Filter Data Output Register FDOR are triggered by three different methods E Direct Memory Access DMA E Interrupts E Polling Two FCSR bits FDIBE and FDOBF indicate the status of the FDIR and the FDOR respectively All three data transfer methods use these two FCSR bits as their control mechanism If FDIBE is set the input buffer is empty if FDOBF is set the output buffer is full Because these bits come into full operation only when the EFCOP is enabled FCSR FEN is set the polling DMA or interrupt methods can be initialized either before or after the EFCOP is enabled No service request is issued until the EFCOP is enabled since FDIBE and FDOBF are cleared while the EFCOP is in the Individual Reset state The most straightforward EFCOP data transfer method uses the core processor to poll the status flags monitoring for input output service requests The disadvantage of this approach is that it demands large amounts of if not all of the core s processing time The interrupt and DMA methods are more efficient in their use of the core processor Interrupts intervene on the core processor infrequently to service input output data DMA can operate concurrently with the processor core and demands only minimal core resource for setup DMA transfers are recommended
249. e set to their reset state The contents of CRA and CRB are not affected The ESSI individual reset allows a program to reset each interface separately from the other internal peripherals During ESSI individual reset internal DMA accesses to the data registers of the ESSI are not valid and data read there are undefined To ensure proper operation of the ESSI use an ESSI individual reset when you change the ESSI control registers except for bits TEIE REIE TLIE RLIE TIE RIE TE2 TE1 TEO and RE Here is an example of how to initialize the ESSI 1 Put the ESSI in its individual reset state by clearing the PCR bits 2 Configure the control registers CRA CRB to set the operating mode Disable the transmitters and receiver by clearing the TE 2 0 and RE bits Set the interrupt enable bits for the operating mode chosen Enable the ESSI by setting the PCR bits to activate the input output signals to be used Write initial data to the transmitters that are in use during operation This step is needed even if DMA services the transmitters 5 Enable the transmitters and receiver to be used DSP56311 User s Manual Rev 2 7 6 Freescale Semiconductor Operation Now the ESSI can be serviced by polling interrupts or DMA Once the ESSI is enabled Step 3 operation starts as follows 1 For internally generated clock and frame sync these signals start activity immediately after the ESSI is enabled The ESSI receives data
250. eared the word length frame sync occurs together with the first bit of the data word of the first slot When FSR is set the word length frame sync occurs one serial clock cycle earlier that is simultaneously with the last bit of the previous data word FSL 1 0 Frame Sync Length Selects the length of frame sync to be generated or recognized as in Figure 7 6 on page 23 Figure 7 9 on page 26 and Figure 7 10 Network Mode External Frame Sync 8 Bit 2 Words in Frame on page 7 26 Frame Sync Length FSL1 FSLO RX TX 0 0 word word 0 1 word bit 1 0 bit bit 1 1 bit word SHFD Shift Direction Determines the shift direction of the transmit or receive shift register If SHFD is set data is shifted in and out with the LSB first If SHFD is cleared data is shifted in and out with the MSB first as in Figure 7 12 ESS Data Path Programming Model SHFD 0 on page 7 29 and Figure 7 13 on page 30 SCKD Clock Source Direction Selects the source of the clock signal that clocks the transmit shift register in Asynchronous mode and both the transmit and receive shift registers in Synchronous mode If SCKD is set and the ESSI is in Synchronous mode the internal clock is the source of the clock signal used for all the transmit shift registers and the receive shift register If SCKD is set and the ESSI is in Asynchronous mode the internal clock source becomes the bit clock for the transmit
251. eceive last slot interrupt 7 7 transmit data 7 8 transmit data with exception status 7 7 transmit last slot interrupt 7 7 flags 7 12 frame rate divider 7 9 frame sync generator 7 16 length 7 10 polarity 7 11 selection 7 10 signal 7 7 7 9 7 17 word length 7 11 initialization 7 6 initialization example 7 6 internally generated clock and frame sync 7 7 interrupt 7 7 Interrupt Service Routine ISR 7 8 interrupt trigger event 7 9 interrupts 7 7 multiple serial device selection 7 4 network enhancements 7 2 Network mode 7 2 7 7 7 9 7 19 7 20 Normal mode 7 2 7 9 7 19 On Demand mode 7 9 7 14 7 19 operating mode 7 6 7 9 7 20 polling 7 7 Port Control Register PCR 7 6 7 34 Port Control Register C PCRC 7 34 Port Control Register D PCRD 7 34 Port Data Register PDR 7 35 Port Data Register C PDRC 7 35 Port Data Register D PDRD 7 35 DSP56311 User s Manual Rev 2 Index 4 Freescale Semiconductor Port Direction Register PRR 7 34 Port Direction Register C PRRC 7 34 Port Direction Register D PRRD 7 34 prescale divider 7 15 programming model 7 12 receive data interrupt request 7 27 Receive Data Register RX 7 12 7 28 Receive Shift Register 7 28 receive shift register clock output 7 4 Receive Slot Mask Register RSM programming sheet B 28 Receive Slot Mask Registers RSMA and RSMB 7 12 7 33 reset 7 6 RX clock 7 10 RX frame sync 7 10 RX frame sync pulses active 7 10
252. ecision Multiply mode is supported to maintain object code compatibility with devices in the DSP56000 family For a more efficient way of executing double precision multiply refer to the chapter on the Data Arithmetic Logic Unit in the DSP56300 Family Manual In Double Precision Multiply mode the behavior of the four specific operations listed in the double precision algorithm is modified Therefore do not use these operations with those specific register combinations in Double Precision Multiply mode for any purpose other than the double precision multiply algorithm All other Data ALU operations or the four listed operations but with other register combinations can be used The double precision multiply algorithm uses the YO Register at all stages Therefore do not change YO when running the double precision multiply algorithm If the Data ALU must be used in an interrupt service routine YO should be saved with other Data ALU registers to be used and restored before the interrupt routine terminates Freescale Semiconductor DSP56311 User s Manual Rev 2 4 7 Core Configuration Table 4 2 Status Register Bit Definitions Continued Bit Number Bit Name Reset Value Description 13 sc 0 Sixteen Bit Compatibility Mode Affects addressing functionality enabling full compatibility with object code written for the DSP56000 family When SC is set MOVE operations to from any of the following PCU registers clear the
253. ed in other processing activities while it is polling receive and transmit ready bits Interrupts require more code but the core can process other routines while waiting for data I O An interrupt is generated when data is ready to be transferred to or from the peripheral device DMA requires even less core intervention and the setup code is minimal but the DMA channels must be available Note Do not use interrupt requests and DMA requests simultaneously DSP56311 User s Manual Rev 2 Freescale Semiconductor 5 5 Programming the Peripherals 5 5 General Purpose Input Output GPIO The DSP56311 provides 34 bidirectional signals that can be configured as GPIO signals or as peripheral dedicated signals No dedicated GPIO signals are provided All of these signals are GPIO by default after reset The control register settings of the DSP56311 peripherals determine whether these signals function as GPIO or as peripheral dedicated signals This section describes how signals can be used as GPIO Chapter 2 Signals Connections details the special uses of the 34 bidirectional signals These signals fall into five groups and are controlled separately or as a group E Port B 16 GPIO signals shared with the HIOS signals E Port C six GPIO signals shared with the ESSIO signals E Port D six GPIO signals shared with the ESSI1 signals E Port E three GPIO signals shared with the SCI signals E Timers three GPIO signals shared with the triple
254. ed to the MSB bit 23 For applications that use 16 bit fractional data shorter data words are left aligned to bit 15 The ALC bit supports shorter data words If ALC is set received words are left aligned to bit 15 in the receive shift register Transmitted words must be left aligned to bit 15 in the transmit shift register If the ALC bit is cleared received words are left aligned to bit 23 in the receive shift register Transmitted words must be left aligned to bit 23 in the transmit shift register Note Ifthe ALC bit is set only 8 12 or 16 bit words are used The use of 24 or 32 bit words leads to unpredictable results 17 Reserved Write to 0 for future compatibility DSP56311 User s Manual Rev 2 Freescale Semiconductor ESSI Programming Model Table 7 3 ESSI Control Register A CRA Bit Definitions Continued Bit Number Bit Name Reset Value Description 16 12 DC 4 0 0 Frame Rate Divider Control Control the divide ratio for the programmable frame rate dividers that generate the frame clocks In Network mode this ratio is the number of words per frame minus one In Normal mode this ratio determines the word transfer rate The divide ratio ranges from 1 to 32 DC 00000 to 11111 for Normal mode and 2 to 32 DC 00001 to 11111 for Network mode A divide ratio of one DC 00000 in Network mode is a special case known as On Demand mode In Normal mode a divide r
255. ee options can be used individually or together Decimation cannot be used with the adaptive and multichannel mode options 10 3 3 1 2 Complex Mode Complex mode performs FIR type filtering with complex data based on the following equations N 1 Re F n Y Re H i Re D n 1 Im H 1 Im D n 1 i 0 N 1 Im F n Y Re H Im D n i Im H i Re D n i i 0 where A n is the coefficients D n is the input data and F n is the output data at time n Two samples the real part then the imaginary part of the input are written to the FDIR The EFCOP processes the data and then two samples the real and then the imaginary part of the output are read from the FDOR Complex mode is selected by setting the FCSR FOM bits to 01 In Complex mode the number written to the FCNT register should be twice the number of filter coefficients Also the coefficients are stored in the FCM with the real part of the coefficient in the memory location preceding the memory location holding the imaginary part of the coefficient Complex mode can be used with the decimation option 10 3 3 1 3 Alternating Complex Mode Alternating Complex mode performs FIR type filtering with complex data providing alternating real and complex results based on the following equations N 1 Re F n ReH Re D n i Im H i Im D n i i 0 N 1 Im F n 4 Y ReH Im D n i Im H i Re D n i i 0 where H n is the coefficients D n is the inp
256. egister HRX 6 20 Host Receive Request HRRQ 6 8 host request line 6 3 host request pins 6 9 host side Command Vector Register CVR 6 24 Interface Control Register ICR 6 22 Interface Status Register ISR 6 25 Interface Vector Register IVR 6 27 Receive Byte Registers RXH RXM RXL 6 27 Transmit Byte Registers TXH TXM TXL 6 28 host side registers after reset 6 28 Host Status Register HSR 6 12 6 13 6 30 Host Command Pending HCP 6 14 Host Flags 0 1 HF 6 14 Host Receive Data Full HRDF 6 14 Host Transmit Data Empty HTDE 6 14 Host Transmit HTX register 6 6 6 20 6 27 6 31 Host Transmit Data Register HTDR programming sheet B 21 B 25 host side register map 6 22 host to DSP data transfers 6 5 6 20 data word 6 1 handshaking protocols 6 1 instructions 6 1 mapping 6 1 HREQ HTRQ handshake flags 6 22 DSP56311 User s Manual Rev 2 Freescale Semiconductor Index 7 Index instructions and addressing modes 6 4 Interface Control Register ICR 6 21 6 22 Double Host Request HDRQ 6 8 6 23 Host Flag 0 HFO 6 23 Host Flag 1 HF1 6 23 Host Little Endian HLEND 6 23 Initialize INIT 6 23 Receive Request Enable RREQ 6 24 Transmit Request Enable TREQ 6 24 Interface Status Register ISR 6 21 6 25 Host Flag 2 HF2 6 26 Host Flag 3 HF3 6 26 Host Request HREQ 6 26 Receive Data Full RDF 6 6 Receive Data Register Full RXDF 6 27 Transmit Data Empty TDE 6 6 Transmit Data Register Empty TXDE
257. empty TXDE bit is set The host processor can program the ICR TREQ bit to assert the external HREQ HTRQ signal when ISR TXDE is set This informs the host processor that the transmit byte registers are empty Writing to the data register at host address 7 clears the ISR TXDE bit The contents of the transmit byte registers are transferred as 24 bit data to the HRX register when both ISR TXDE and HSR HRDF are cleared This transfer operation sets HSR TXDE and HSR HRDF The external host should never write to the TXH TXM TXL registers if the ISR TXDE bit is cleared Note When data is written to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If you read any of those status bits within the next two cycles the bit will not reflect its current status For details see Section 6 4 1 Software Polling on page 6 6 6 7 7 Host Side Registers After Reset Table 6 18 shows the result of the four kinds of reset on bits in each of the HIOS registers seen by the host processor To cause a hardware reset assert the RESET signal To cause a software reset execute the RESET instruction To reset the HEN bit individually clear the HPCR HEN bit To cause a stop reset execute the STOP instruction Table 6 18 Host Side Registers After Reset Reset Type Register Register Name Data HW Sw Individual Reset STOP Reset Reset ICR All bits 0 0 CVR HC 0 0 0 0 HV
258. en SYN is set the ESSI is in Synchronous mode and the transmit and receive sections use common clock and frame sync signals Only in Synchronous mode can more than one transmitter be enabled 11 CKP 0 Clock Polarity Controls which bit clock edge data and frame sync are clocked out and latched in If CKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the receive bit clock If CKP is set the data and the frame sync are clocked out on the falling edge of the transmit bit clock and latched in on the rising edge of the receive bit clock 10 FSP 0 Frame Sync Polarity Determines the polarity of the receive and transmit frame sync signals When FSP is cleared the frame sync signal polarity is positive that is the frame start is indicated by the frame sync signal going high When FSP is set the frame sync signal polarity is negative that is the frame start is indicated by the frame sync signal going low DSP56311 User s Manual Rev 2 7 20 Freescale Semiconductor ESSI Programming Model Table 7 4 ESSI Control Register B CRB Bit Definitions Continued Bit Number Bit Name Reset Value Description 9 FSR 0 Frame Sync Relative Timing Determines the relative timing of the receive and transmit frame sync signal in reference to the serial data lines for word length frame sync only When FSR is cl
259. en an overflow occurs the FSAT bit is set and the result is saturated to the most positive number that is 7FFFFF When an underflow occurs the FSAT bit is set and the result is saturated to the most negative number that is 800000 FSAT is a sticky status bit that is set by hardware and can be cleared only by a hardware RESET signal a software RESET instruction or an individual reset Freescale Semiconductor DSP56311 Reference Manual Rev 2 10 37 Enhanced Filter Coprocessor Table 10 7 FCSR Bits Continued Bit A Reset in Number Bit Name Value Description 11 FDOIE 0 Filter Data Output Interrupt Enable This read write control bit enables the filter data output interrupt If FDOIE is cleared the filter data output interrupt is disabled and the FDOBF status bit should be polled to determine whether the FDOR is full If both FDOIE and FDOBF are set the EFCOP requests a data output buffer full interrupt service from the DSP56300 core ADMA transfer is enabled if a DMA channel is activated and triggered by this event For proper operation enable the interrupt service routine and the corresponding interrupt for core processing or enable the DMA transfer and configure the proper trigger for the selected channel Never enable both simultaneously 10 FDIIE 0 Filter Data Input Interrupt Enable This read write control bit enables the data input buffer empty interrupt If FDIIE is cleared the data input buffe
260. en as Reset the reset function written as reset DSP56311 User s Manual Rev 2 Freescale Semiconductor 1 3 DSP56311 Overview 1 3 Manual Revision History for Revision 2 Significant differences between Revision 1 and Revision 2 are listed in Table 1 2 Table 1 2 Change History Revision 1 to Revision 2 Change Revision 1 Revision 2 9 Page Number Page Number Modified signal definitions Updated the number of GND signals in Table 2 1 Page 2 1 Page 2 1 Modified signal definitions Updated Figure 2 1 Added notes regarding operation Page 2 2 Page 2 2 above and below 100 MHz Modified signal definitions Updated Table 2 3 for ground signals Page 2 4 Page 2 4 Modified signal definitions Updated Table 2 5 for PLL signals Page 2 6 Page 2 5 Modified signal definitions Updated AA RAS TA BR BB BCLK BCLK and CAS signal information in Table 2 8 Page 2 7 to 2 9 Page 2 6 to 2 8 Modified signal definitions In Table 2 10 changed the title of the third column to State During Reset Added a new note 1 and changed the old note 1 to note 2 Changed the State During Reset of all signals to Ignored input Changed the signal description for PB14 Pages 2 11 to 2 14 Pages 2 10 to 2 12 Modified signal definitions In Table 2 11 to Table 2 14 deleted the Stop column Page 2 15 to Page 2 13 to Changed the title of the third column to State During Reset Added a new no
261. en consecutive messages The idle string cannot occur within a valid message because each word frame there contains a start bit that is 0 When WAKE is set the wakeup on address bit mode is selected In the wakeup on address bit mode the SCI receiver is re enabled when the last eighth or ninth data bit received in a character frame is 1 The ninth data bit is the address bit R8 in the 11 bit multidrop mode the eighth data bit is the address bit in the 10 bit asynchronous and 11 bit asynchronous with parity modes Thus the received character is an address that has to be processed by all sleeping processors that is each processor has to compare the received character with its own address and decide whether to receive or ignore all following characters DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 13 Serial Communication Interface SCI Table 8 2 SCI Control Register SCR Bit Definitions Continued Bit Number Bit Reset Name Value Description 4 SBK 0 Send Break A break is an all zero word frame a start bit 0 characters of all zeros including any parity and a stop bit O that is ten or eleven zeros depending on the mode selected If SBK is set and then cleared the transmitter finishes transmitting the current frame sends 10 or 11 Os and reverts to idle or sending data If SBK remains set the transmitter continually sends whole frames of Os 10 or 11 bits with no stop bit At
262. enerator which performs low power division and clock pulse generation These features allow you to E Change the low power divide factor without losing the lock E Output a clock with skew elimination The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input a feature that offers two immediate benefits E A lower frequency clock input reduces the overall electromagnetic interference generated by a system E The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system 1 6 5 JTAG TAP and OnCE Module In the DSP56300 core is a dedicated user accessible TAP that is fully compatible with the JEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Problems with testing high density circuit boards led to the development of this standard under the sponsorship of the Test Technology Committee of IEEE and the JTAG The DSP56300 core implementation supports circuit board test strategies based on this standard The test logic includes a TAP with four dedicated signals a 16 state controller and three test data registers A boundary scan register links all device signals into a single shift register The test logic implemented utilizing static logic design is independent of the device system logic For details on the JTAG port consult the DSP56300 Family Manual The OnCE module interacts with the DSP56300 core and its p
263. eptions 8 8 Idle Line 8 8 Receive Data 8 8 Receive Data with Exception Status 8 8 Timer 8 8 Transmit Data 8 8 GPIO 5 7 GPIO functionality 8 22 I O signals 8 3 Idle Line Wakeup mode 8 3 individual reset state PCR 0 8 6 initialization 8 6 Inter processor messages 8 2 interrupts 8 6 Multidrop mode 8 2 operating mode 8 1 Asynchronous 8 1 Synchronous 8 1 programming model 8 8 data registers 8 20 Receive Data RXD 8 4 recover synchronization 8 2 reset 8 4 SCI Clock Control Register SCCR 8 6 8 7 8 8 8 17 bit definitions 8 17 Clock Divider CD 8 17 Clock Out Divider COD 8 17 Clock Prescaler SCP 8 17 programming sheet B 30 Receive Clock Mode Source RCM 8 17 Transmit Clock Source TCM 8 17 SCI Control Register SCR 8 6 8 7 8 8 8 10 bit defintions 8 11 Idle Line Interrupt Enable ILIE 8 12 programming sheet B 29 Receive with Exception Interrupt Enable REIE 8 11 Receiver Enable RE 8 13 Receiver Wakeup Enable RWU 8 13 SCI Clock Polarity SCKP 8 11 SCI Receive Interrupt Enable RIE 8 12 SCI Shift Direction SSFTD 8 14 SCI Transmit Interrupt Enable TIE 8 12 Send Break SBK 8 14 Timer Interrupt Enable TMIE 8 11 Timer Interrupt Rate STIR 8 11 Transmitter Enable TE 8 12 Wakeup Mode Select WAKE 8 13 Wired OR Mode Select WOMS 8 13 Word Select WDS 8 14 SCI Receive Data Register SRX 8 8 8 20 SCI Status Register SSR 8 8 8 15 bit definitions 8 15 Framing Error Flag FE 8 15 Idle Line Flag
264. equest Conditions Peripheral Reaves MDRQ EFCOP input buffer empty FDIBE 1 MDRQ11 EFCOP output buffer full FDOBF 1 MDRQ12 Freescale Semiconductor DSP56311 Reference Manual Rev 2 10 43 Enhanced Filter Coprocessor DSP56311 Reference Manual Rev 2 10 44 Freescale Semiconductor Bootstrap Program A This appendix lists the bootstrap program and equates for the DSP56311 Freescale posts updates to the bootstrap program on the Worldwide Web at the web site listed on the back cover of this manual A 1 Bootstrap Code BOOTSTRAP CODE FOR DSP56311 C Copyright 1999 Motorola Inc Revised March 18 1999 Bootstrap through the Host Interface External EPROM or SCI This is the Bootstrap program contained in the DSP56311 192 word Boot ROM This program can load any program RAM segment from an external EPROM from the Host Interface or from the SCI serial interface If MD MC MB MA x000 then the Boot ROM is bypassed and the DSP56311 starts fetching instructions beginning with address C00000 MD 0 or 008000 MD 1 assuming that an external memory of SRAM type is used The accesses are performed using 31 wait states with no address attributes selected default area AAA A Operation modes MD MC MB MA 0001 0111 are reserved If MD MC MB MA 1001 then it loads a program RAM segment from consecutive byte wide P memory locations star
265. equest the command interrupt and the seven Host Vector bits CVR 6 0 HV 6 0 to select the interrupt address to be used When the DSP core recognizes the host command interrupt the address of the interrupt taken is 2xHV For host command interrupts the interrupt acknowledge from the DSP56311 program controller clears the pending interrupt condition DSP56311 User s Manual Rev 2 Freescale Semiconductor 6 7 Host Interface HI08 Note When the DSP enters Stop mode the HI08 pins are electrically disconnected internally thus disabling the HIOS until the core leaves Stop mode Do not issue a STOP command via the HIO8 unless some other mechanism for exiting this mode is provided 6 4 3 Core DMA Access The DSP56300 family Direct Memory Access DMA controller permits transfers between internal or external memory and I O without any core intervention A DMA channel can be set up to transfer data to from the HTX and HRX data registers freeing the core to use its processing power on functions other than polling or interrupt routines for the HI08 DMA may well be the best method to use for data transfers but it requires that one of the six DMA channels be available for use Two HIO8 DMA sources are possible as Table 6 4 shows Refer to the DSP56300 Family Manual to learn about DMA accesses Table 6 4 DMA Request Sources Requesting Device DCRx 15 11 DRS 4 0 Host Receive Data Full HRDF 1 10011 Host Transm
266. er A hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction clears R8 FE Framing Error Flag In Asynchronous mode FE is set when no stop bit is detected in the data string received FE and RDRE are set simultaneously when the received word is transferred to the SRX However the FE flag inhibits further transfer of data into the SRX until it is cleared FE is cleared when the SCI status register is read followed by a read of the SRX A hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction clears FE In 8 bit Synchronous mode FE is always cleared If the byte received causes both framing and overrun errors the SCI receiver recognizes only the overrun error PE Parity Error In 11 bit Asynchronous modes PE is set when an incorrect parity bit is detected in the received character PE and RDRF are set simultaneously when the received word is transferred to the SRX If PE is set further data transfer into the SRX is not inhibited PE is cleared when the SCI status register is read followed by a read of SRX A hardware RESET signal a software RESET instruction an SCI individual reset or a STOP instruction also clears PE In 10 bit Asynchronous mode 11 bit multidrop mode and 8 bit Synchronous mode the PE bit is always cleared since there is no parity bit in these modes If the byte received causes both parity and overrun errors
267. er TCSRO FFFF8F Read Write Reset 000000 TCSR1 FFFF8B Read Write TCSR2 FFFF87 Read Write Reserved Program as 0 Figure B 21 Timer Control Status Register TCSR DSP56311 User s Manual Rev 2 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 3 of 3 Timers 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 O Timer Reload Value Timer Load Register TLR 0 2 TLRO X FFFF8E Write Only Reset xxxxxx value indeterminate after reset TLR1 X FFFF8A Write Only TLR2 X FFFF86 Write Only 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Value Compared to Counter Value Timer Compare Register TCPR 0 2 TCPRO X FFFF8D Read Write Reset xxxxxx value is indeterminate after reset TCPR1 X FFFF89 Read Write TCPR2 X FFFF85 Read Write 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 Timer Count Value Timer Count Register TCR 0 2 TCRO X FFFF8C Read Only Reset 000000 TCR1 X FFFF88 Read Only TCR2 X FFFF84 Read Only Figure B 22 Timer Load Compare and Count Registers TLR TCPR TCR DSP56311 User s Manual Rev 2 Freescale Semiconductor B 33 Programming Reference Application Date Programmer Sheet 1 of 4 GPIO Port B HIO8 DRx 1 gt HIx is Output DRx 0 gt HIx is Input 14 1 11 1 15 3 12 o 9 8 7 6 5 4 3 2 1 0 i i a ii Fi i a i a i Host Data Direction Register HDDR X FFFFC8 W
268. er definition as is else I_VEC EQU 0 endif I_RESET EQU _VEC 00 Hardware RESET I_STACK EQU _VEC 02 Stack Error I_ILL EQU _VEC S 04 Illegal Instruction I_DBG EQU _VEC S 06 Debug Request I_ TRAP EQU _VEC S08 Trap I_NMI EQU _VEC S0A Non Maskable Interrupt I_IRQA EQU _VEC 10 IRQA I_IRQB EQU _VEC 12 IROB I_TRQC EQU _VEC 14 IROC I_IRQD EQU _VEC 16 IROD DMA Interrupts T_DMAO EQU _VEC 18 DMA Channel 0 I_DMA1 EQU _VEC 1A DMA Channel 1 I_DMA2 EQU _VEC 1C DMA Channel 2 I_DMA3 EQU _VEC S1E DMA Channel 3 I_DMA4 EQU _VEC 20 DMA Channel 4 T_DMA5 EQU _VEC 22 DMA Channel 5 I_TIMOC EQU _VEC 24 TIMER O compare I_TIMOOF EQU _VEC 26 TIMER 0 overflow I_TIM1C EQU _VEC 28 TIMER compare I_TIM1OF EQU _VEC S2A TIMER overflow I_TIM2C EQU _VEC 2C TIMER 2 compare DSP56311 User s Manual Rev 2 A 20 Freescale Semiconductor I_TIM20F I_STORD EQU I_SIORDE EQU I_SIORLS I_SIOTD EQU EQU I_SIOTDE EQU I_SIOTLS EQU I_SI1RD EQU I_SI1RDE EQU I_SI1RLS EQU I_SI1TD EQU T_SI1TDE I_SI1TLS EQU EQU
269. er is disabled Disable the prescaler counter by clearing TCSR TE of each of three timers PS1 PSO Prescaler Clock Source 0 0 Internal CLK 2 0 TIOO 1 0 TIO1 1 1 TIO2 20 0 PL 20 0 Prescaler Preload Value Contains the prescaler preload value which is loaded into the prescaler counter when the counter value reaches 0 or the counter switches state from disabled to enabled If PL 20 0 N then the prescaler counts N 1 source clock cycles before generating a prescaler clock pulse Therefore the prescaler divide factor preload value 1 9 4 3 Timer Prescaler Count Register TPCR The TPCR is a read only register that reflects the current value in the prescaler counter 23 22 21 20 19 18 17 16 15 14 13 12 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 11 10 9 8 7 6 5 4 3 2 1 0 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO Reserved bit read as 0 write to O for future compatibility Figure 9 22 Timer Prescaler Count Register TPCR Table 9 2 Timer Prescaler Count Register TPCR Bit Definitions Bit Number Bit Name Reset Value Description 23 21 0 Reserved Write to zero for future compatibility 200 PC 20 0 0 Prescaler Counter Value Contain the current value of the prescaler counter DSP56311 User s Manual Rev 2 Freescale
270. er is empty The receive and transmit interrupts function normally using TDE and RDF however transmit underruns are impossible for On Demand transmission and are disabled This mode is useful for interfacing with codecs requiring a continuous clock Note When the ESSI transmits data in On Demand mode that is MOD 1 in the CRB and DC 4 0 00000 in the CRA with WL 2 0 100 the transmission does not work properly To ensure correct operation do not use On Demand mode with the WL 2 0 100 32 bit word length mode DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 9 Enhanced Synchronous Serial Interface ESSI 7 4 2 Synchronous Asynchronous Operating Modes The transmit and receive sections of the ESSI interface are synchronous or asynchronous The transmitter and receiver use common clock and synchronization signals in Synchronous mode they use separate clock and sync signals in Asynchronous mode The CRB SYN bit selects synchronous or asynchronous operation When the SYN bit is cleared the ESSI TX and RX clocks and frame sync sources are independent If the SYN bit is set the ESSI TX and RX clocks and frame sync are driven by the same source either external or internal Since the ESSI operates either synchronously or asynchronously separate receive and transmit interrupts are provided Transmitter 1 and transmitter 2 operate only in Synchronous mode Data clock and frame sync signals are generated internally by th
271. er of coefficient values is the number of locations used in the FCM For a real FIR filter the number of coefficient values is identical to the number of filter taps For a complex FIR filter the number of coefficient values is twice the number of filter taps DSP56311 Reference Manual Rev 2 10 36 Freescale Semiconductor EFCOP Programming Model 10 4 5 EFCOP Control Status Register FCSR The FCSR is a read write register by which the DSP56300 core controls the main operation modes of the EFCOP and monitors the EFCOP status 23 22 21 19 18 17 16 15 14 13 12 FDOBF FDIBE FCONT FSAT 11 10 9 7 6 5 4 3 2 1 0 FDOIE FDIIE FSCO FPRC FMLC FOM1 FOMO FUPD FADP FLT FEN Reserved bit read as 0 write with O for future compatibility Table 10 7 FCSR Bits Bit a Reset Number Bit Name Value Description 23 16 0 These bits are reserved and unused They read as 0 write with O for future compatibility 15 FDOBF 0 Filter Data Output Buffer Full When set this read only status bit indicates that the FDOR is full and the DSP can read data from the FDOR The FDOBF bit is set when a result from FMAC is transferred to the FDOR For proper operation read data from the FDOR only if the FDOBF status bit is set When FDOBF is set the EFCOP generates an FDOBF interrupt request to the DSP56300 core if that interrupt is enabled that is FDOI
272. er priority than normal receive data interrupts If the receiver overrun error ROE bit is set signaling that an exception has occurred and the REIE bit is set the ESSI requests an SSI receive data with exception interrupt from the interrupt controller 18 TIE 0 Transmit Interrupt Enable Enables disables a DSP transmit interrupt the interrupt is generated when both the TIE and the TDE bits in the ESSI status register are set When TIE is cleared the transmit interrupt is disabled The transmit interrupt is documented in Section 7 3 3 When data is written to the data registers of the enabled transmitters or to the TSR it clears TDE and also clears the interrupt Transmit interrupts with exception conditions have higher priority than normal transmit data interrupts If the transmitter underrun error TUE bit is set signaling that an exception has occurred and the TEIE bit is set the ESSI requests an SSI transmit data with exception interrupt from the interrupt controller DSP56311 User s Manual Rev 2 7 18 Freescale Semiconductor ESSI Programming Model Table 7 4 ESSI Control Register B CRB Bit Definitions Continued Bit Number Bit Name Reset Value Description 17 RE 0 Receive Enable Enables disables the receive portion of the ESSI When RE is cleared the receiver is disabled data transfer into RX is inhibited If data is being received while this bit is cleared the remainder of the word is
273. er the weight update multiplier is written to FKIR the EFCOP transfers it to the FMAC unit and starts updating the filter coefficients according to the following equation New_coefficients Old_coefficients FKIR Input_buffer 10 4 4 Filter Count FCNT Register The FCNT register is a read write register that selects the filter length number of filter taps Always write the initial count into the FCNT register before you enable the EFCOP that is before you set FEN The number stored in FCNT is used to generate the correct addressing for the FDM and for the FCM Note To ensure correct operation never change the contents of the FCNT register unless the EFCOP is in the individual reset state that is FEN 0 In the individual reset state that is FEN 0 the EFCOP module is inactive but the contents of the FCNT register are preserved 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FCNT11 FCNT10 FCNT9 FCNTB FCNT7 FCNT6 FCNT5 FCNT4 FCNT3 FCNT2 FCNT1 FCNTO Reserved bit read as 0 write with O for future compatibility Table 10 6 Filter Count FCNT Register Bits Bit Abbr Description 23 12 These bits are reserved and unused They read as 0 write with O for future compatibility 11 0 FCNT Filter Count The actual value written to the FCNT register must be the number of coefficient values minus one The numb
274. eripherals nonintrusively so that you can examine registers memory or internal peripherals This facilitates hardware and software development on the DSP56300 core processor OnCE module functions are provided through the JTAG TAP signals For details on the OnCE module consult the DSP36300 Family Manual 1 6 6 Internal Memory The memory space of the DSP56300 core is partitioned into program X data and Y data memory space The data memory space is divided into X and Y data memory in order to work with the two address ALUs and to feed two operands simultaneously to the data ALU Memory space includes internal RAM and ROM and can be expanded off chip under software control There is an on chip 192 x 24 bit bootstrap ROM For details on internal memory see Chapter 3 DSP56311 User s Manual Rev 2 Freescale Semiconductor 1 9 DSP56311 Overview Memory Configuration Program RAM instruction cache X data RAM and Y data RAM size are programmable as Table 1 2 shows Table 1 1 DSP56311 Switch Memory Configuration ee ar acid X Data RAM Size Y Data RAM Size san sie aes MSW1 MSWO 32 K x 24 bit 0 48 K x 24 bit 48 K x 24 bit disabled disabled 0 1 0 1 31 K x 24 bit 1024 x 24 bit 48 K x 24 bit 48 K x 24 bit enabled disabled 0 1 0 1 96 K x 24 bit 0 16 K x 24 bit 16 K x 24 bit disabled enabled 0 0 95 K x 24 bit 1024 x 24 bit 16 K x 24 bit 16 K x 24 bit enabled enabled 0 0 80 K x 24 bi
275. ers are transferred to the HRX register TXDE is cleared when the transmit register TXL or TXH according to HLEND bit is written by the host processor The host processor can set TXDE using the initialize function TXDE can assert the external HTRQ signal if the TREQ bit is set Regardless of whether the TXDE interrupt is enabled TXDE indicates whether the TX registers are full and data can be latched in so that polling techniques may be used by the host processor Hardware software individual and stop resets all set TXDE 6 26 DSP56311 User s Manual Rev 2 Freescale Semiconductor Host Programmer Model Table 6 17 Interface Status Register ISR Bit Definitions Continued Bit Number Bit Name Reset Value Description 0 RXDF 0 Receive Data Register Full Indicates that the receive byte registers RXH RXM RXL contain data from the DSP56311 to be read by the host processor RXDF is set when the HTX is transferred to the receive byte registers RXDF is cleared when the host processor reads the receive data register RXL or RXH according to HLEND bit The host processor can clear RXDF using the initialize function RXDF can assert the external HREQ signal if the RREQ bit is set Regardless of whether the RXDF interrupt is enabled RXDF indicates whether the RX registers are full and data can be latched out so that the host processor can use polling techniques 6 7 4 Interrupt Vector Register IV
276. erviced with the previous setting and the new frame is serviced with the new setting without synchronization problems The maximum time it takes to service a receive last slot interrupt should not exceed N 1 ESSI bits service time where N is the number of bits the ESSI can transmit per time slot ESSI transmit data with exception status Occurs when the transmit exception interrupt is enabled at least one transmit data register of the enabled transmitters is empty and a transmitter underrun error has occurred This exception sets the SSISR TUE bit The TUE bit is cleared when you first read the SSISR and then write to all the transmit data registers of the enabled transmitters or when you write to TSR to clear the pending interrupt ESSI transmit last slot interrupt Occurs when the ESSI is in Network mode at the start of the last slot of the frame This DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 7 Enhanced Synchronous Serial Interface ESSI Note exception occurs regardless of the transmit mask register setting The transmit last slot interrupt can signal that the transmit mask slot register can be reset the DMA channels can be reconfigured and data memory pointers can be reassigned Using the Transmit Last Slot interrupt guarantees that the previous frame is serviced with the previous frame settings and the new frame is serviced with the new frame settings without synchronization problems The maximum tr
277. es between signals set the TLR value to X 2 and set the TCSR TRM bit This process repeats until the timer is disabled Mode 1 internal clock TRM 1 first event N write preload M write compare TE Clock CLK 2 or prescale CLK TLR Counter TCR TCPR TCF Compare Interrupt if TCIE 1 TIO pin INV 0 pulse width timer clock TIO pin INV 1 peros Figure 9 5 Pulse Mode TRM 1 DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 7 Triple Timer Module Mode 1 internal clock TRM 0 N write preload M write compare first event TE Clock CLK 2 or prescale CLK TLR NY f l NN Sorel ee we x A A Nei AM D M 1 aK 1 n x TCPR lt M Fa TCF Compare Interrupt if TCIE 1 A He pin INV 0 pulse width J timer clock iod TIO pin INV 1 pa TOF Overflow Interrupt if TCIE 1 Se Figure 9 6 Pulse Mode TRM 0 9 3 1 3 Timer Toggle Mode 2 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 0 1 0 2 Toggle Timer Output Internal In Mode 2 the timer periodically toggles the polarity of the TIO signal When the timer is enabled the TIO signal is loaded with the value of the TCSR INV bit When the counter value matches the value in the TCPR the polarity of the TIO output signal is inverted TCSR TCF is set and a compa
278. es the MS bit 2 To ensure proper operation do not set the MS bit while the Instruction Cache is enabled CE bit is set in SR SD Stop Delay Mode Determines the length of the delay invoked when the core exits the Stop state The STOP instruction suspends core processing indefinitely until a defined event occurs to restart it If SD is cleared a 128K clock cycle delay is invoked before a STOP instruction cycle continues However if SD is set the delay before the instruction cycle continues is 16 clock cycles The long delay allows a clock stabilization period for the internal clock to begin oscillating and to stabilize When a stable external clock is used the shorter delay allows faster start up of the DSP56300 core Reserved Write to zero for future compatibility EBD External Bus Disable Disables the external bus controller to reduce power consumption when external memories are not used When EBD is set the external bus controller is disabled and external memory cannot be accessed When EBD is cleared the external bus controller is enabled and external access can be performed Hardware reset clears the EBD bit 3 0 MD MA Chip Operating Mode Indicate the operating mode of the DSP56300 core On hardware reset these bits are loaded from the external mode select pins MODD MODC MODB and MODA respectively After the DSP56300 core leaves the Reset state MD MA can be changed under program control
279. etermine the state of the Transmit Registers TXH TXM TXL and Receive Registers RXH RHM RHL Two bits are provided to the host for polling E the Transmit Data Empty TXDE bit in the Interface Status Register ISR 1 TXDE E the Receive Data Full RXDF bit in the Interface Status Register ISR 0 RXDF The HIOS also offers four general purpose flags for communication between the host and the DSP The DSP side uses the HSR Host Flag bits HCR 4 3 HF 3 2 to pass application specific information to the host The status of HF3 HF2 is reflected in the host side ISR Host Flag bits ISR 4 3 HF 3 2 Similarly the host side can use the ICR Host Flag bits ICR 4 3 HF 1 0 to pass application specific information to the DSP The status of HF 1 0 is reflected in the DSP side HSR Host Flag bits HSR 4 3 HF 1 0 6 4 2 Core Interrupts and Host Commands The HIOS can request interrupt service from the DSP56311 core The DSP56311 core interrupts are internal and do not require the use of an external interrupt signal When the appropriate interrupt enable bit in the HCR is set an interrupt condition caused by the host interface sets the appropriate bit in the HSR generating an interrupt request to the DSP56311 interrupt controller see Figure 6 2 The DSP56311 acknowledges interrupts by jumping to the appropriate interrupt service routine The following DSP core interrupts are possible from the HIO8 peripheral DSP56311 User s Man
280. eup hardware You can also clear the RWU bit to wake up the receiver You can use RWU to ignore messages that are for other devices on a multidrop serial network Wakeup on idle line i e WAKE is cleared or wakeup on address bit i e WAKE is set must be chosen When WAKE is cleared and RWU is set the receiver does not respond to data on the data line until an idle line is detected When WAKE is set and RWU is set the receiver does not respond to data on the data line until a data frame with Bit 9 set is detected When the receiver wakes up the RWU bit is cleared and the first frame of data is received If interrupts are enabled the CPU is interrupted and the interrupt routine reads the message header to determine whether the message is intended for this DSP If the message is for this DSP the message is received and RWU is set to wait for the next message If the message is not for this DSP the DSP immediately sets RWU Setting RWU causes the DSP to ignore the remainder of the message and wait for the next message Either a hardware RESET signal or a software RESET instruction clears RWU RWU is ignored in Synchronous mode WAKE Wakeup Mode Select When WAKE is cleared the wakeup on Idle Line mode is selected In the wakeup on idle line mode the SCI receiver is re enabled by an idle string of at least 10 or 11 depending on WDS mode consecutive ones The transmitter s software must provide this idle string betwe
281. ev 2 10 28 Freescale Semiconductor move move move 0 b 0 a DST_COUNT bO FDM memory initialization move move rep move FDBA_ADDRS r0 0 x0 FIR_LEN x0 x r0 address register initialization move move rep move DST_ADDRS r0 DES_ADDRS r1 EFCOP initialization movep movep movep movep DMA movep movep movep movep movep FIR_LEN 1 y M_FCNT FDBA_ADDRS y M_FDBA FCBA_ADDRS y M_FCBA FCON y M_FCSR channel 0 initialization FSRC_ADDRS x M_DSRO M_FDIR x M_DDRO SRC_COUNT x M_DCOO HS1 x M_DORO S94AA04 x M_DCRO r f f EFCOP Operation counter for output interrupt FDM memory area clear FDM memory area kk Destination address Desired signal address Set reference pointer correctly FIR length FIR input samples Start Address FIR Coeff Start Address Enable EFCOP input to EFCOP DMA source address points to the DATA bank Init DMA destination address Init DMA count to line mode DMA offset reg is 1 Init DMA control reg to line mode FDIBE request DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 29 Enhanced Filter Coprocessor nop nop e KKK KEK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KARA RRA RRA KARA an waitl
282. express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Free
283. ficient address pointer always starts at the lower boundary and ends at the upper address boundary Therefore a FCBA read always gives the value of the lower address boundary DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 41 Enhanced Filter Coprocessor 10 4 9 Decimation Channel Count Register FDCH The FDCH is a read write register that sets the number of channels used in multichannel mode FCHL and sets the decimation ratio in FIR filter mode FDCH must be written before the FEN enables the EFCOP FDCH should be changed only when the EFCOP is in individual reset state FEN 0 otherwise improper operation may result The number stored in FCHL is used by the EFCOP address generation logic to generate the correct address for the FDM bank and for the FCM bank in multichannel mode When the EFCOP enable bit FEN is cleared the EFCOP is in individual reset state In this state the EFCOP is inactive and the contents of FDCH register are preserved 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FDCM3 FDCM2 FDCM1 FDCMO FCHL5 FCHL4 FCHL3 FCHL2 FCHL1 FCHLO Reserved bit read as 0 write with O for future compatibility Table 10 9 Decimation Channel Count Register FDCH Bits Bit Number Bit Name Reset Value Description 23 12 0 These bits are reserved and unused They read as 0 write with O for future
284. first time slot in the frame and cleared during all other time slots If the transmitter is enabled data written to a transmit data register during the time slot when TFS is set is transmitted in Network mode during the second time slot in the frame TFS is useful in Network mode to identify the start of a frame TFS is valid only if at least one transmitter is enabled that is when TEO TE1 or TE2 is set In Normal mode TFS is always read as 1 when data is being transmitted because there is only one time slot per frame the frame sync time slot DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 27 Enhanced Synchronous Serial Interface ESSI Table 7 5 ESSI Status Register SSISR Bit Definitions Continued Bit Number Bit Name Reset Value Description 1 IF 1 0 Serial Input Flag 1 The ESSI latches any data on the SC1 signal during reception of the first received bit after the frame sync is detected IF1 is updated with this data when the data in the receive shift register transfers into the receive data register IF1 is enabled only when SC1 is an input flag and Synchronous mode is selected that is when SC1 is programmed as ESSI in the port control register PCR the SYN bit is set and the TE2 and SCD1 bits are cleared If it is not enabled IF1 is cleared 0 IFO 0 Serial Input Flag 0 The ESSI latches any data on the SCO signal during reception of the first received bit after the frame sync is dete
285. forms only two basic types of processing FIR filter type and IIR filter type processing Various sub options are available with each filter type as described in the following sections 10 3 2 EFCOP Initialization Before the first sample is processed the EFCOP filter must be initialized that is the input samples for times before n 0 assuming that time starts at 0 must be loaded into the FDM The method by which this is done depends on the Filter Type selected 10 3 2 1 FIR Initialization The number of samples needed to initialize the filter is the number of filter coefficients minus one To select Initialization mode clear the FCSR FPRC bit If FCSR FPRC is set initialization is disabled and the EFCOP assumes that the core wrote the initial input values to the FDM before the EFCOP was enabled Thus the first value written to FDIR is the first sample to be filtered If FCSR FPRC is clear initialization mode is enabled and the EFCOP initializes the FDM by receiving the number of coefficients minus one samples through the FDIR After samples are loaded the next value written to the FDIR is the first sample to be filtered 10 3 2 2 IIR Initialization Initialization is always disabled with the IIR filter type and the FCSR FPRC bit is ignored Thus the DSP56300 core must write the initial input values before the EFCOP is enabled The first value written to FDIR is always the first sample to be filtered DSP56311 Reference Manua
286. ful in configuring systems in which data is received from one type of device for example codec and transmitted to a different type of device CRB FSLO controls whether RX and TX have the same frame sync length E If CRB FSLO is cleared both RX and TX have the same frame sync length DSP56311 User s Manual Rev 2 7 10 Freescale Semiconductor Operating Modes Normal Network and On Demand E If CRB FSLO is set RX and TX have different frame sync lengths CRB FSLO is ignored when CRB S YN is set 7 4 6 Word Length Frame Sync and Data Word Timing The CRB FSR bit controls the relative timing of the word length frame sync relative to the data word timing E When CRB FSR is cleared the word length frame sync is generated or expected with the first bit of the data word E When CRB FSR is set the word length frame sync is generated or expected with the last bit of the previous word CRB FSR is ignored when a bit length frame sync is selected 7 4 7 Frame Sync Polarity The CRB FSP bit controls the polarity of the frame sync E When CRB FSP is cleared the polarity of the frame sync is positive that is the frame sync signal is asserted high The ESSI synchronizes on the leading edge of the frame sync signal E When CRB FSP is set the polarity of the frame sync is negative that is the frame sync is asserted low The ESSI synchronizes on the trailing edge of the frame sync signal The ESSI receiver looks for
287. future compatibility Freescale Semiconductor DSP56311 User s Manual Rev 2 6 13 Host Interface HI08 Table 6 9 Host Status Register HSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 4 3 HF 1 0 0 Host Flags 0 1 General purpose flags for host to DSP communication These bits reflect the status of host flags HF 1 0 in the ICR on the host side These two general purpose flags can be used individually or as encoded pairs ina simple host to DSP communication protocol implemented in both the DSP and the host processor software HCP Host Command Pending Reflects the status of the CVR HC bit When set it indicates that a host command interrupt is pending HIO8 hardware clears HC and HCP when the DSP core services the interrupt request If the host clears HC HCP is also cleared HTDE Host Transmit Data Empty Indicates that the host transmit data register HTX is empty and can be written by the DSP core HTDE is set when the HTX register is transferred to the RXH RXM RXL registers The host processor can also set HTDE using the initialize function HTDE is cleared when the DSP core writes to HTX HRDF Host Receive Data Full Indicates that the host receive data register HRX contains data from the host processor HRDF is set when data is transferred from the TXH TXM TXL registers to the HRX register The host processor can also cle
288. g ROE 7 27 Serial Input Flag 0 IFO 7 28 Serial Input Flag 1 1F1 7 28 Transmit Data Register Empty TDE 7 27 Transmit Frame Sync Flag TFS 7 27 Transmitter Underrun Error Flag TUE 7 27 Synchronous Asynchronous SYN bit 7 20 T TA Synchronize Select TAS bit 4 12 Test Access Port TAP 1 6 1 9 Time Slot Register TSR 7 31 timer 2 18 after Reset 9 3 enabling 9 4 exception 9 4 Compare 9 4 Overflow 9 4 GPIO 5 8 DSP56311 User s Manual Rev 2 Freescale Semiconductor Index 13 Index initialization 9 3 operating modes 9 5 Capture mode 6 9 5 9 11 9 15 Event Counter mode 3 9 5 9 10 GPIO mode 0 9 5 Input Period mode 5 9 5 9 11 9 13 Input Width mode 4 9 5 9 11 9 12 overview 9 5 Pulse mode 1 9 5 9 7 Pulse Width Modulation PWM mode 7 9 5 9 11 9 16 reserved 9 20 setting 9 3 signal measurement modes 9 11 Toggle mode 2 9 5 9 8 watchdog modes 9 18 Watchdog Pulse mode 9 9 5 9 18 Watchdog Toggle mode 10 9 5 9 18 prescaler counter 9 21 programming model 9 21 special cases 9 21 timer compare interrupts 9 27 Timer Compare Register TCPR 9 28 Timer Control Status Register TCSR 9 24 Data Input DI 9 25 Data Output DO 9 25 Direction DIR 9 25 Inverter INV 9 25 9 27 Prescaler Clock Enable PCE 9 24 Timer Compare Flag TCF 9 24 Timer Compare Interrupt Enable TCIE 9 27 Timer Control TC 9 26 Timer Enable TE 9 27 Timer Overflow Flag TOF 9 24 Timer Overflow Interrupt Ena
289. gnal R n that is E n gt 0 A R n EMO Adaptive Elm ai FIR Filter gt Filter Update A Figure 10 8 Adaptive FIR Filter The adaptive FIR filter typically comprises four stages which are performed for each input sample at time n E Stage 1 The FIR filter output value is calculated for the EFCOP FIR session according to this equation N 1 F n YA DD i i 0 where H i are the filter coefficients at time n D n is the input signal and F n is the filter output at time n This stage requires N MAC operations calculated by the EFCOP FMAC unit E Stage 2 The core calculates the error signal E n in software according to the following equation E n R n F n where R n is the desired signal at time n This stage requires a single arithmetic operation E Stage 3 The core calculates the weight multiplier Ke n in software according to the following equation Ke n K E n DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 25 Enhanced Filter Coprocessor where K is the convergence factor of the algorithm After calculating the weight multiplier Kg the core must write it into the FKIR E Stage 4 The coefficients are updated by the EFCOP update session H 10 H i Ke D n 1 where H i are the adaptive filter coefficients at time n 1 Ke n is the weight multiplier at time n and D n is the input signal This stage starts
290. gured as an active high input and the HIO8 is selected when the HCS signal is high 12 HDDS Host Dual Data Strobe If the HDDS bit is cleared the HIO8 operates in single strobe bus mode In this mode the bus has a single data strobe signal for both reads and writes If the HDDS bit is set the HIO8 operates in dual strobe bus mode In this mode the bus has two separate data strobes one for data reads the other for data writes See Figure 6 13 on page 19 and Figure 6 14 on page 19 for details on dual and single strobe modes 11 HMUX Host Multiplexed Bus If HMUX is set the HIO8 operates in multiplex mode latching the lower portion of a multiplexed address data bus In this mode the internal address line values of the host registers are taken from the internal latch If HMUX is cleared it indicates that the HI08 is connected to a non multiplexed type of bus The values of the address lines are then taken from the HI08 dedicated address signals 10 HASP Host Address Strobe Polarity If HASP is cleared the host address strobe HAS signal is an active low input and the address on the host address data bus is sampled when the HAS signal is low If HASP is set HAS is an active high address strobe input and the address on the host address or data bus is sampled when the HAS signal is high HDSP Host Data Strobe Polarity If HDSP is cleared the data strobe signals are configured as active low inputs and
291. he data hold time and the memory release time and do not increase the memory access time 15 13 BA3W 2 0 111 Bus Area 3 Wait State Control 7 wait states Defines the number of wait states 1 7 inserted in each external SRAM access to Area 3 DRAM accesses are not affected by these bits Area 3 is the area defined by AARS Note Do not program the value of these bits as zero since SRAM memory access requires at least one wait state When four through seven wait states are selected one additional wait state is inserted at the end of the access This trailing wait state increases the data hold time and the memory release time and does not increase the memory access time Freescale Se DSP56311 User s Manual Rev 2 miconductor 4 21 Core Configuration Table 4 8 Bus Control Register BCR Bit Definitions Continued Bit Bit Name Reset Value Description Number 12 10 BA2W 2 0 111 Bus Area 2 Wait State Control 7 wait states Defines the number of wait states 1 7 inserted into each external SRAM access to Area 2 DRAM accesses are not affected by these bits Area 2 is the area defined by AAR2 Note Do not program the value of these bits as zero since SRAM memory access requires at least one wait state When four through seven wait states are selected one additional wait state is inserted at the end of the access This trailing wait state increases the data hold time and t
292. he interrupt handler should write data into the transmitter The DMA channel services the SCI transmit request if it is programmed to service the SCI transmitter 5 Enable transmitters TE 1 and receiver RE 1 according to use DSP56311 User s Manual Rev 2 8 6 Freescale Semiconductor SCI Initialization Operation starts as follows E For an internally generated clock the SCLK signal starts operation immediately after the SCI is enabled Step 3 above for Asynchronous modes In Synchronous mode the SCLK signal is active only while transmitting that is a gated clock E Data is received only when the receiver is enabled RE 1 and after the occurrence of the SCI receive sequence on the RXD signal as defined by the operating mode that is idle line sequence E Data is transmitted only after the transmitter is enabled TE 1 and after the initialization sequence has been transmitted depending on the operating mode 8 4 1 Preamble Break and Data Transmission Priority Two or three transmission commands can be set simultaneously E A preamble TE is set E A break SBK is set or is cleared E An indication that there is data for transmission TDRE is cleared After the current character transmission if two or more of these commands are set the transmitter executes them in the following order preamble break data 8 4 2 Bootstrap Loading Through the SCI Boot Mode 2 or RA When the DSP comes out of reset
293. he memory release time and does not increase the memory access time 9 5 BA1W 4 0 11111 Bus Area 1 Wait State Control 31 wait Defines the number of wait states 1 31 inserted into each external SRAM access states to Area 1 DRAM accesses are not affected by these bits Area 1 is the area defined by AAR1 Note Do not program the value of these bits as zero since SRAM memory access requires at least one wait state When four through seven wait states are selected one additional wait state is inserted at the end of the access When selecting eight or more wait states two additional wait states are inserted at the end of the access These trailing wait states increase the data hold time and the memory release time and do not increase the memory access time 40 BAOW 4 0 11111 Bus Area 0 Wait State Control 31 wait Defines the number of wait states 1 31 inserted in each external SRAM access states to Area 0 DRAM accesses are not affected by these bits Area 0 is the area defined by AARO Note Do not program the value of these bits as zero since SRAM memory access requires at least one wait state When selecting four through seven wait states one additional wait state is inserted at the end of the access When selecting eight or more wait states two additional wait states are inserted atthe end of the access These trailing wait states increase the data hold time and the memory release time and do not increase the memory a
294. he transmitter and receiver when in Synchronous mode SC2 can be programmed as a GPIO signal P2 when the ESSI SC2 function is not in use DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 5 Enhanced Synchronous Serial Interface ESSI 7 3 Operation This section discusses ESSI basics reset state initialization and exceptions 7 3 1 ESSI After Reset A hardware RESET signal or software reset instruction clears the port control register and the port direction control register thus configuring all the ESSI signals as GPIO The ESSI is in the reset state while all ESSI signals are programmed as GPIO it is active only if at least one of the ESSI I O signals is programmed as an ESSI signal 7 3 2 Initialization To initialize the ESSI do the following 1 Send a reset hardware RESET signal software reset instruction ESSI individual reset or stop instruction reset Program the ESSI control and time slot registers Write data to all the enabled transmitters Configure at least one signal as ESSI signal oP oN If an external frame sync is used from the moment the ESSI is activated at least five 5 serial clocks are needed before the first external frame sync is supplied Otherwise improper operation may result When the PC 5 0 bits in the GPIO Port Control Register PCR are cleared during program execution the ESSI stops serial activity and enters the individual reset state All status bits of the interface ar
295. heet B 37 Port E Data Register PDRE 8 23 programming sheet B 37 Port E Direction Register PRRE 8 23 programming sheet B 37 position independent code PIC 1 8 power low 1 6 management 1 6 standby modes 1 6 Predivider Factor PD bits 4 19 prescale divider for ESSI 7 15 Prescale Modulus Select PM bits 7 15 Prescaler Clock Enable PCE bit 9 24 prescaler counter 9 21 Prescaler Counter Value PC bits 9 23 Prescaler Preload Value PL bits 9 23 Prescaler Range PSR bit 7 15 Prescaler Source PS bits 9 23 Program Address Bus PAB 1 11 Program Address Generator PAG 1 8 Program Control Unit PCU 1 8 Program Counter register PC 1 8 Program Data Bus PDB 1 10 Program Decode Controller PDC 1 8 program memory 1 6 3 1 3 2 program memory expansion 1 10 bus 1 10 Program ROM bootstrap 3 1 programming model DSP core 6 11 EFCOP 10 35 ESSI 7 12 HIOS 6 11 DSP side 6 11 host side 6 21 HIOS quick reference 6 29 peripherals 5 1 SCI 8 8 timer 9 21 programming sheets list B 1 R RAM program 3 1 reading status registers 5 2 Receive Byte Registers RXH RXM RXL 6 5 6 27 Index Receive Clock Mode Source RCM 8 17 Receive Data RXD signal 8 4 Receive Data Full RDF bit 6 6 Receive Data Register RX 7 28 Receive Data Register Full RDF bit 7 27 Receive Data Register Full RDRF bit 8 16 Receive Data Register Full RXDF bit 6 27 Receive Enable RE bit 7 19 Receive Exception Interrupt Enable REIE
296. here the user program loads in the DSP56311 program memory 3 The user program three bytes for each 24 bit program word Note The three bytes for each data sequence are loaded least significant byte first When the bootstrap program finishes loading the specified number of words it jumps to the specified starting address and executes the loaded program 4 3 Central Processor Unit CPU Registers There are two CPU registers that must be configured to initialize operation The Status Register SR selects various arithmetic processing protocols and contains several status reporting flag bits The Operating Mode Register OMR configures several system operating modes and characteristics 4 3 1 Status Register SR The Status Register SR Figure 4 1 is a 24 bit register that indicates the current system state of the processor and the results of previous arithmetic computations The SR is pushed onto the system stack when program looping is initialized or a JSR is performed including long interrupts The SR consists of the following three special purpose 8 bit control registers DSP56311 User s Manual Rev 2 4 4 Freescale Semiconductor Central Processor Unit CPU Registers E Extended Mode Register EMR SR 23 16 and Mode Register MR SR 15 8 These special purpose registers define the current system state of the processor The bits in both registers are affected by hardware reset exception processing ENDDO end curren
297. hrough PCRE This input is 5 V tolerant Notes 1 Inthe Stop state the signal maintains the last state as follows 2 e Ifthe last state is input the signal is an ignored input e Ifthe last state is output these lines are tri stated The Wait processing state does not affect the signal state Freescale Semiconductor DSP56311 User s Manual Rev 2 Signals Connections 2 11 Timers Three identical and independent timers are implemented in the DSP56311 Each timer can use internal or external clocking and can either interrupt the DSP56311 after a specified number of events clocks or signal an external device after counting a specific number of internal events Table 2 14 Triple Timer Signals Signal Name State During Signal Description Type Reset 2 TIOO Input or Output Ignored input Timer 0 Schmitt Trigger Input Output As an external event counter or in Measurement mode TIOO is input In Watchdog Timer or Pulse Modulation mode TIOO is output The default mode after reset is GPIO input This can be changed to output or configured as a Timer Input Output through the Timer 0 Control Status Register TCSRO This input is 5 V tolerant TIO1 Input or Output Ignored input Timer 1 Schmitt Trigger Input Output As an external event counter or in Measurement mode TIO1 is input In Watchdog Timer or Pulse Modulation mode TIO1 is output The default mode after reset is GPIO input This can be changed to ou
298. ie VA tase ad 9 7 Timer Toggle Mode 2 a cco04 ee ina a heme Gane egy beled deve ged ened A a ves 9 8 Timer Event Counter Mode 3 rss 0 e tear eee EE AE 9 10 Signal Measurement Modes ionerne eii enira a cece eee eee ene aa 9 11 Measurement Input Width Mode 4 0 ccc eee eens 9 12 Measurement Input Period Mode 5 0 cece eee e eens 9 13 Measurement Capture Mode 6 0 0 ete teen e eens 9 15 Pulse Width Modulation a a a e a a E n ene eens 9 16 Watchdog Modes cuco o OP eds OED A a es Sete 9 18 Watchdog Pulse Mode 9 o ooooooccoccooccoo tne n ene e ee neee 9 19 Watchdog Toggle Mode 10 0 2 eee eee e nee aee 9 20 Reserved Mod n rolean eaaa ths ate tied Bute nals adeno dowel edna sauna eae 9 20 Special Cases ici eee es Dee ele A a ees pay Yee ede 9 21 DMA Tres a a ita 9 21 Triple Timer Module Programming Model o oocococoocococococo aeee 9 21 Prescaler Counter ica ra il Bure 9 21 Timer Prescaler Load Register TPLR 0 eee een eens 9 22 Timer Prescaler Count Register TPCR 00 ccc cece n ene nee 9 23 Timer Control Status Register TCSR 0 0 cence nee 9 24 Timer Load Register TLR creperen cece cence teen ene EE 9 28 Timer Compare Register TCPR 0 0 cee ent tne e nea 9 28 Timer Count Register TCR 0 6 6c ence ence ne eas 9 29 Enhanced Filter Coprocessor ECU a A SOS bu Sai beet eee Se bon A Had wee ee 10 1 Architecture Overview dui
299. ignal generates the following signal 1010 If the INV bit is cleared the TIO signal generates the following signal 0101 The value of the TLR determines the output period FFFFFF TLR 1 The timer counter increments the initial TLR value and toggles the TIO signal when the counter value exceeds FFFFFF The duty cycle of the TIO signal is determined by the value in the TCPR When the value in the TLR increments to a value equal to the value in the TCPR the TIO signal is toggled The duty cycle is equal to SFFFFFF TCPR divided by FFFFFF TLR 1 For a 50 percent duty cycle the value of TCPR is equal to SFFFFFF TLR 1 2 Note The value in TCPR must be greater than the value in TLR DSP56311 User s Manual Rev 2 9 16 Freescale Semiconductor Operating Modes Period FFFFFF TLR 1 Duty cycle SF FFFFF TCPR Ensure that TCPR gt TLR for correct functionalit Mode 7 internal clock TRM 1 4 N write preload first event M write compare y TE gt A Y E CLK 2 or prescale CLK TLR Nee i Counter TCR 0 N 0 N N 1 TCPR gt M if TCIE 1 TCF Compare Interrupt TCF Overflow Interrupt if TDIE 1 TIO pin INV 0 TIO pin INV 1 Pulse width gt ane Period Figure 9 16 Pulse Width Modulation Toggle Mode TRM 1 DSP56311 User s Manual Rev 2 F
300. ilitate block floating point arithmetic The scaling mode also affects the MAC rounding position to maintain proper rounding when different portions of the accumulator registers are read out to the XDB and YDB Scaling mode bits are cleared at the start of a long Interrupt Service Routine and during a hardware reset Scaling Mode 0 0 No scaling 23 S A46 XOR A45 OR B46 XOR B45 OR S previous 0 1 Scale down 24 S A47 XOR A46 OR B47 XOR B46 OR S previous 1 0 Scale up 22 S A45 XOR A44 OR B45 XOR B44 OR S previous 1 1 Reserved S undefined S1 so Rounding Bit SEquation DSP56311 User s Manual Rev 2 4 8 Freescale Semiconductor Central Processor Unit CPU Registers Table 4 2 Status Register Bit Definitions Continued Bit Number Bit Name Reset Value Description 9 8 I 1 0 11 Interrupt Mask Reflect the current Interrupt Priority Level IPL of the processor and indicate the IPL needed for an interrupt source to interrupt the processor The current IPL of the processor can be changed under software control The interrupt mask bits are set during hardware reset but not during software reset Exceptions Priority 11 10 Permitted Exceptions Masked Lowest o IPL O 1 2 3 None _ IPL1 2 3 IPLO IPL 2 3 IPL O 1 Highest lojo alo IPL3 IPL 0 1 2 Scaling Set when a res
301. immediately after K n is written in the FKIR if Adaptive mode is enabled 10 3 6 3 1 Implementation Using Polling Figure 10 9 shows a flowchart for an adaptive FIR filter that uses polling to transfer data Set FONT N 1 Set FDBA FCBA Calculate K Enable EFCOP ADP Real FIR Mode Write K to FKIR Write next x n Set FUPD 1 opt Automatically Done in ADP Mode Block No Done Yes End Figure 10 9 Adaptive FIR Filter Using Polling DSP56311 Reference Manual Rev 2 10 26 Freescale Semiconductor EFCOP Operation 10 3 6 3 2 Implementation Using DMA Input and Interrupt Output Figure 10 10 shows a flowchart for an adaptive FIR filter that uses DMA and an interrupt to transfer data Output Buffer Full Interrupt Set DMA Int for input on FDIBE Set FCNT L 1 Set FDBA FCBA Enable EFCOP ADP Real FIR Mode Calculate K Write K to FKIR opt Set FUPD 1 Automatically Done in ADP Mode Figure 10 10 Adaptive FIR Filter Using DMA Input and Interrupt Output 10 3 6 3 3 Updating an FIR Filter The following example shows an FIR adaptive filter that is updated using the LMS algorithm Example 10 4 FIR Adaptive Filter Update Using the LMS Algorithm TITLE ADAPTIVE NCLUDE ioequ asm eR KKK KKK KKK KKK KKK KKK KKK KEK KKK KKK KKK KEK KKK KEK KKK KKK KEK KKK KEK KKK KKK KKK KKK KKK KKK KKK KK KKK KKEKEK e
302. in MS mode but the maximum addressing ranges are limited to FFFF and all data and program code are 16 bits wide 3 6 Memory Maps The following figures illustrate each of the memory space and RAM configurations defined by the settings of the MS and MSW 1 0 CE and SC bits The figures show the configuration and describe the bit settings memory sizes and memory locations DSP56311 User s Manual Rev 2 3 8 Freescale Semiconductor Program FFFFFF FFFFFF FFFF80 Internal Reserved FFOOCO FFO000 Bootstrap ROM FF0000 External 00C000 008000 Internal Program RAM 32K 000000 000000 Default X Data SFFEOOO Internal Reserved External Internal X data RAM 48K FFFFFF Internal O FFFFCO FFFF80 FFF000 FF0000 000000 Y Data External 1 O Internal I O Internal Reserved External 00C000 Internal Y data RAM 48K Memory Maps value 0000 7FFF 0000 BFFF 0000 BFFF Bit Settings Memory Configuration ms MSW ce sc Program RAM XDataRAM YDataRAM Cache Addressable 1 0 Memory Size 0 any 0 0 32K 48K 48K None 16M the EFCOP but not by the DMA controller e Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and Figure 3 1 Memory Switch Off Cache Off 24 Bit Mode Default DSP56311 User s Manual Rev
303. in Synchronous modes or the transmitter only in Asynchronous modes Although an external serial clock can be independent of and asynchronous to the DSP system clock it must exceed the minimum clock cycle time of 6 T that is the system clock frequency must be at least three times the external ESSI clock frequency The ESSI needs at least three DSP phases inside each half of the serial clock Port C 3 The default configuration following reset is GPIO For PC3 signal direction is controlled through PRRC This signal is configured as SCKO or PC3 through PCRC This input is 5 V tolerant SRDO PC4 Input Input or Output Ignored input Serial Receive Data Receives serial data and transfers the data to the ESSI receive shift register SRDO is an input when data is being received Port C 4 The default configuration following reset is GPIO For PC4 signal direction is controlled through PRRC This signal is configured as SRDO or PC4 through PCRC This input is 5 V tolerant STDO PC5 Output Input or Output Ignored input Serial Transmit Data Transmits data from the serial transmit shift register STDO is an output when data is being transmitted PortC 5 The default configuration following reset is GPIO For PC5 signal direction is controlled through PRRC This signal is configured as STDO or PC5 through PCRC This input is 5 V tolerant Freescale Semiconductor DSP56311 User s Manual
304. ing SRAM memory access type with 31 wait states and no address attributes selected 9 1 0 0 1 FF0000 Bootstrap from byte wide memory The bootstrap program loads instructions through Port A from external byte wide memory starting at P D00000 The SRAM memory access type is selected by the values in address attribute register 1 AAR1 Thirty one wait states are inserted between each memory access Address D00000 is reflected as address 00000 on Port A signals A 0 17 The boot program concatenates every 3 bytes read from the external memory into a 24 bit wide DSP56311 word DSP56311 User s Manual Rev 2 4 2 Freescale Semiconductor Operating Modes Table 4 1 DSP56311 Operating Modes Continued Reset Mode MODD MODC MODB MODA Vector Description A 1 0 1 0 FF0000 Bootstrap through SCI Instructions are loaded through the SCI The bootstrap program sets the SCI to operate in 10 bit asynchronous mode with 1 start bit 8 data bits 1 stop bit and no parity Data is received in this order start bit 8 data bits LSB first and one stop bit Data is aligned in the SCI receive data register with the LSB of the least significant byte of the received data appearing at Bit 0 The user must provide an external clock source with a frequency at least 16 times the transmission data rate Each byte received by the SCI is echoed back through the SCI transmitter to the external transmitter
305. ing Mode Register OMR page B 13 IPR Figure B 3 Interrupt Priority Register Core IPRC page B 14 Figure B 4 Interrupt Priority Register Peripherals IPRP page B 15 PLL Figure B 5 Phase Lock Loop Control Register PCTL page B 16 BIU Figure B 6 Bus Control Register BCR page B 17 Figure B 7 DRAM Control Register DCR page B 18 Figure B 8 Address Attribute Registers AAR 3 0 page B 19 DMA Figure B 9 DMA Control Registers 5 0 DCR 5 0 page B 20 DSP56311 User s Manual Rev 2 Freescale Semiconductor B 1 Programming Reference Table B 1 Guide to Programming Sheets Continued HI08 Figure B 10 Host Transmit Data Register page B 21 Figure B 11 Host Base Address and Host Port Control Registers page B 22 Figure B 12 Host Control Register page B 23 Figure B 13 Interrupt Control and Command Vector Registers page B 24 Figure B 14 Interrupt Vector and Host Transmit Data Registers page B 25 ESSI Figure B 15 ESSI Control Register A CRA page B 26 Figure B 16 ESSI Control Register B CRB page B 27 Figure B 17 ESSI Transmit and Receive Slot Mask Registers TSM RSM page B 28 SCI Figure B 18 SCI Control Register SCR page B 29 Figure B 19 SCI Clock Control Registers SCCR page B 30 Timers Figure B 20 Timer Prescaler Load Register TPLR page B 31 Figure B 21 Timer Control Status Register TCSR page B 32 Figure B 22 Timer Load Compare and Count Registers TLR
306. ing normal operation of the crystal oscillator 15 XTLR 0 Crystal Range Controls the on chip crystal oscillator transconductance The XTLR bit is cleared 0 during hardware reset in the DSP56303 14 12 DF 2 0 0 Division Factor Define the DF of the low power divider These bits specify the DF as a power of two in the range from 20 to 27 11 0 MF 11 0 0 PLL Multiplication Factor Define the multiplication factor that is applied to the PLL input frequency The MF bits are cleared during DSP56311 hardware reset and thus correspond to an MF of one 4 6 Bus Interface Unit BIU Registers The three Bus Interface Unit BIU registers configure the external memory expansion port Port A They include the following E Bus Control Register BCR E DRAM Control Register DCR E Address Attribute Registers AAR 3 0 To use Port A correctly configure these registers as part of the bootstrap process The following subsections describe these registers 4 6 1 Bus Control Register The Bus Control Register BCR depicted in Figure 4 6 is a read write register that controls the external bus activity and Bus Interface Unit BIU operation All BCR bits except bit 21 BBS are read write bits The BCR bits are defined in Table 4 8 DSP56311 User s Manual Rev 2 4 20 Freescale Semiconductor Bus Interface Unit BIU Registers 23 22 21 20 19 18 17 16 15 14 13 12 BRH BBS BDFW4 BDFW3 BDFW2 BDFW1 BDF
307. ing performed by the Data ALU during arithmetic operations If RM is cleared convergent rounding is selected If RM is set two s complement rounding is selected 20 SM Arithmetic Saturation Mode Selects automatic saturation on 48 bits for the results going to the accumulator This saturation is performed by a special circuit inside the MAC unit The purpose of this bit is to provide an Arithmetic Saturation mode for algorithms that do not recognize or cannot take advantage of the extension accumulator 19 CE Cache Enable Enables disables the instruction cache controller If CE is set the cache is enabled and instructions are cached into and fetched from the internal Program RAM If CE is cleared the cache is disabled and the DSP56300 core fetches instructions from external or internal program memory according to the memory space table of the specific DSP56300 core based device Note To ensure proper operation do not clear Cache Enable mode while Burst mode is enabled OMR BE is set 18 Reserved Write to zero for future compatibility 17 SA Sixteen Bit Arithmetic Mode Affects data width functionality enabling the Sixteen bit Arithmetic mode of operation When SA is set the core uses 16 bit operations instead of 24 bit operations In this mode 16 bit data is right aligned in the 24 bit memory locations registers and 24 bit register portions Shifting limiting rounding arithmetic
308. ingle clock cycle per instruction engine code compatible with Freescale s popular DSP56000 core family a barrel shifter 24 bit addressing instruction cache and DMA controller The DSP56311 offers 150 million instructions per second MIPS performance 300 MIPS using the EFCOP in filtering applications using an internal 150 MHz clock with 3 3 V core and input output I O power All DSP56300 core family members contain the DSP56300 core and additional modules The modules are chosen from a library of standard predesigned elements such as memories and peripherals New modules can be added to the library to meet customer specifications A standard interface between the DSP56300 core and the internal memory and peripherals supports a wide variety of memory and peripheral configurations In particular the DSP56311 includes a JTAG port integrated with the Freescale OnCE module The DSP56311 with its large internal memory arrary of 128 K words and its EFCOP is well suited for high end multichannel telecommunication applications such as multi line voice data fax processing video conferencing and general digital signal processing 1 5 DSP56300 Core Core features are fully described in the DSP56300 Family Manual This manual in contrast documents pinout memory and peripheral features Core features are as follows E 150 MIPS 300 MIPS using the EFCOP in filtering applications with a 150 MHz clock at 1 8 V E Highly parallel instruction set
309. ings for configuring an ESSIO transmit interrupt using transmitter O The order of the steps is optional except that the interrupt trigger configuration must not be completed until the ISR configuration is complete Since step 2c may cause an immediate transmit without generating an interrupt perform the transmit data preload in step 2b before step 2c to ensure that valid data is sent in the first transmission DSP56311 User s Manual Rev 2 Freescale Semiconductor Operating Modes Normal Network and On Demand After the first transmit subsequent transmit values are typically loaded into TXnn by the ISR one value per register per interrupt Therefore if N items are to be sent from a particular TXnn the ISR needs to load the transmit register N 1 times Steps 2c and 2d can be performed in step 2a as a single instruction If an interrupt trigger event occurs before all interrupt trigger configuration steps are performed the event is ignored and not queued If interrupts derived from the core or other peripherals need to be enabled at the same time as ESSI interrupts step 2f should be performed last 7 4 Operating Modes Normal Network and On Demand The ESSI has three basic operating modes and several data and operation formats These modes are programmed via the ESSI control registers The data and operation formats available to the ESSI are selected when you set or clear control bits in the CRA and CRB These control bits are
310. interrupt and mode control signals select the chip s operating mode as it comes out of hardware reset After RESET is deasserted these inputs are hardware interrupt request lines Table 2 9 Interrupt and Mode Control Signal Name Type State During Reset Signal Description RESET Input Input Schmitt trigger Reset When asserted places the chip in the Reset state and resets the internal phase generator The Schmitt trigger input allows a slowly rising input such as a capacitor charging to reset the chip reliably When the RESET signal is deasserted the initial chip operating mode is latched from the MODA MODB MODC and MODD inputs The RESET signal must be asserted after power up MODA Input Input Input Schmitt trigger Mode Select A MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is deasserted External Interrupt Request A After reset this input becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing If the processor is in the STOP or WAIT standby state and IRQA is asserted the processor exits the STOP or WAIT state MODB D w Input Input Input Schmitt trigger Mode Select B MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is deasserted
311. ion The Stack Control Status SCS byte is referenced implicitly by some instructions such as DO JSR and RTI or directly by the MOVEC instruction During processor reset the chip operating mode bits MD MC MB and MA are loaded from the external mode select pins MODD MODC MODB and MODA respectively Table 4 3 defines the DSP56311 OMR bits DSP56311 User s Manual Rev 2 4 10 Freescale Semiconductor Central Processor Unit CPU Registers Table 4 3 Operating Mode Register OMR Bit Definitions Bit Number Bit Name Reset Value Description 23 0 Reserved Write to 0 for future compatibility 22 21 MSW 1 0 0 Memory Switch Mode Bits 1 0 When enabled by the MS bit 7 the two bits configure the internal memory sizes for Program X data and Y data memory See Chapter 3 for details Notes 1 To ensure proper operation place six NOP instructions after the instruction changing the MS bit 2 To ensure proper operation do not change the MS bit while the Instruction Cache is enabled SR CE bit is set 20 SEN 0 Stack Extension Enable Enables disables the stack extension in data memory If the SEN bit is set the extension is enabled Hardware reset clears this bit so the default out of reset is a disabled stack extension 19 WRP 0 Stack Extension Wrap Flag Set when copying from the on chip hardware stack System Stack Register file to the stack extension memory begins You can use this flag during
312. ion operation This bit is also set if a borrow is generated in a subtraction operation otherwise this bit is cleared The carry or borrow is generated from Bit 55 of the result The C bit is also affected by bit manipulation rotate and shift instructions 4 3 2 Operating Mode Register OMR The OMR is a read write register divided into three byte sized units The lowest two bytes EOM and COM control the chip s operating mode The high byte SCS controls and monitors the stack extension The OMR control bits are shown in Figure 4 2 Stack Control Status SCS Extended Operating Mode EOM Chip Operating Mode COM 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSW 1 0 SEN WRP EOV EUN xYS ATE APD ABE BRT TAS BE corr1 o MS SD EBD MD MC MB MA Reset o o o o o o o o o o o o o o i l l iflo o o o After reset these bits reflect the corresponding value of the mode input that is MODD MODC MODB or MODA respectively Reserved bit Read as zero write to zero for future compatibility Figure 4 2 Operating Mode Register OMR The Enhanced Operating Mode EOM and Chip Operating Mode COM bytes are affected only by processor reset and by instructions directly referencing the OMR that is ANDI ORI and other instructions such as MOVEC that specify OMR as a destinat
313. isters PDRC and PDRD o ooccccoccccccc eee 7 35 8 Serial Communication Interface SCI 8 1 Operating Modes e ato A A AAA A Bees 8 1 8 1 1 Synchronous Mode eviten ta 8 2 8 1 2 Asynchronous Mode ooo 8 2 8 1 3 Multidrop Mode rs aa 8 2 8 1 3 1 Transmitting Data and Address Characters 20 0 cece cece eee eee 8 3 8 1 3 2 Wited OR Mode octal ddd dh ehh ohare lt ten a Benet 8 3 8 1 3 3 Idle Lane Wakeup st tata eae Vay ba Tea vier hag ae ae a 8 3 8 1 3 4 Address Mode Wakeup oii erent 0 0c a cece ene teen teen ene 8 3 8 2 WO Sonal fst it bs Medan ke tikes ok lal shld edad tad E lad 8 3 8 2 1 Rec rve Data RADY A a e Tod ea ae a a he Wael be ae eae EAS a 8 4 8 2 2 Transmit Data TXDI ati a ao need Winey ethno Se ape a hen Sate eases Blac aad talla GOONS 8 4 8 2 3 SCI Serial Clock SCLK coito a OP eee SP ae Sea eee SE OEE 8 4 8 3 SCLAtter Reset fend Ai sini eds Soe es di A tt da Ba hed he 8 4 8 4 SGI Initialization s pt et oes Week eed he A ee hb 8 6 8 4 1 Preamble Break and Data Transmission Priority 0 0 0 000 cc cece eee eee 8 7 8 4 2 Bootstrap Loading Through the SCI Boot Mode 2 or RA 0 0 c cece eee ee o 8 7 8 5 EXcepuions ita A Saa 8 8 DSP56311 User s Manual Rev 2 viii Freescale Semiconductor 8 6 8 6 1 8 6 2 8 6 3 8 6 4 8 6 4 1 8 6 4 2 8 7 8 7 1 8 7 2 8 7 3 9 1 9 1 1 9 1 2 9 2 9 2 1 9 2 2 9 2 3 9 3 9 3 1 9 3 1 1 9 3 1 2 9 3 1 3 9 3 1 4 9 3 2 9 3 2 1 9 3 2 2 9 3
314. it Data Empty HTDE 1 10100 Note DMA transfers do not access the host bus The host must determine when data is available in the host side data registers using an appropriate polling mechanism 6 4 4 Host Requests A set of signal lines allow the HI08 to request service from the host The request signal lines normally connect to the host interrupt request pins IRQx and indicate to the host when the DSP HIOS port requires service The HIOS can be configured to use either a single Host Request HREQ line for both receive and transmit requests or two signal lines a Host Transmit Request HTRQ and a Host Receive Request HRRQ for each type of transfer Host requests are enabled on both the DSP side and host side On the DSP side the HPCR Host Request Enable bit HPCR 4 HREN is set to enable host requests On the host side clearing the ICR Double Host Request bit ICR 2 HDRQ configures the HIOS to use a single request line HREQ Setting the ICR 2 HDRQ bit enables both transmit and request lines to be used Further the host uses the ICR Receive Request Enable bit ICR 0 RREQ and the ICR Transmit Request Enable bit ICR 1 TREQ to enable receive and transmit requests DSP56311 User s Manual Rev 2 6 8 Freescale Semiconductor Operation respectively When host requests are enabled the host request pins operate as shown in Figure 6 3 Status 7 oF 2 ISR Host Request Signals Host Request As
315. it Number Bit Name Reset Value Description 5 HAEN 0 Host Acknowledge Enable Controls the HACK signal In the single host request mode HDRQ is cleared in the ICR if HAEN and HREN are both set HACK HRRQ is configured as the host acknowledge HACK input If HAEN or HREN is cleared HACK HRRA is configured as a GPIO signal according to the value of the HDDR and HDR In the double host request mode HDRQ is set in the ICR HAEN is ignored HREN Host Request Enable Controls the host request signals If HREN is set and the HIO8 is in the single host request mode that is if HDRQ is cleared in the host interface control register ICR then HREQ HTRQ is configured as the host request HREQ output If HREN is cleared HREQ HTRQ and HACK HRRQ are configured as GPIO signals according to the value of the HDDR and HDR If HREN is set in the double host request mode that is if HDRQ is set in the ICR HREQ HTRQ is configured as the host transmit request HTRQ output and HACK HRRAQ as the host receive request HRRQ output If HREN is cleared HREQ HTRQ and HACK HRRQ are configured as GPIO signals according to the value of the HDDR and HDR HCSEN Host Chip Select Enable If the HCSEN bit is set HCS HA10 is a host chip select HCS in the non multiplexed bus mode that is wnen HMUX is cleared and host address line 10 HA10 in the multiplexed bus mode that is when HMUX is set If this bit is cleared HCS H
316. ith the 12 K lowest locations 0 2FFF of the on chip internal X memory E Filter Coefficient Memory FCM This 24 bit wide memory bank is mapped as Y memory and stores filter coefficients for EFCOP filter processing The FCM is written via the DSP56300 core and the EFCOP address generation logic generates its addressing The filter coefficients are read sequentially from the FCM into the MAC The FCM is accessible for writes only by the core The FCM is shared with the 12 K lowest locations 0 2FFF of the on chip internal Y memory Note The filter coefficients H n are stored in reverse order where H N 1 is stored at the lowest address of the FCM register as shown in Figure 10 2 Data Coefficient Memory Memory Bank Bank FDM FCM Figure 10 2 Storage of Filter Coefficients DSP56311 Reference Manual Rev 2 10 4 Freescale Semiconductor Architecture Overview The EFCOP connects to the shared memory in place of the DMA bus Simultaneous core and EFCOP accesses to the same memory module block 1024 locations of shared memory are not permitted It is your responsibility to prevent such simultaneous accesses Figure 10 3 illustrates the memory shared between the core and the EFCOP X RAM Y RAM Data Coefficients X RAM Y RAM P RAM FDM FCM A A A 1 A YDB l PDB XDB r FDB CDB i yY Y Y Y E 0 PD CORE EFCOP GDB
317. itial During assertion of RESET the value of PINIT is written into the PLL enable PEN bit of the PLL control PCTL register determining whether the PLL is enabled or disabled Nonmaskable Interrupt After RESET deassertion and during normal instruction processing this Schmitt trigger input is the negative edge triggered NMI request internally synchronized to CLKOUT 2 5 External Memory Expansion Port Port A Note When the DSP56311 enters a low power standby mode stop or wait it releases bus mastership and tri states the relevant Port A signals A 0 17 D O 23 AAO RASO AA3 RAS3 RD WR BB CAS 2 5 1 External Address Bus Table 2 6 External Address Bus Signals Signal Name Type State During Reset Signal Description A 0 17 Output Tri stated Address Bus When the DSP is the bus master A 0 17 are active high outputs that specify the address for external program and data memory accesses Otherwise the signals are tri stated To minimize power dissipation A O 17 do not change state when external memory spaces are not being accessed 2 5 2 External Data Bus Table 2 7 External Data Bus Signals Signal Name Type State During Reset Signal Description D 0 23 Input Output Tri stated Data Bus When the DSP is the bus master D 0 23 are active high bidirectional input outputs that provide the bidirectional data bus for e
318. itialize INIT bit 6 23 initializing the timer 9 3 Instruction Cache 3 3 instruction cache 1 6 Interface Control Register ICR 6 22 Double Host Request HDRQ 6 8 6 23 Host Flag 0 HFO 6 23 Host Flag 1 HF1 6 23 Host Little Endian HLEND 6 23 Initialize INIT 6 23 Receive Request Enable RREQ 6 24 Transmit Request Enable TREQ 6 24 Interface Status Register ISR 6 25 Host Flag 2 HF2 6 26 Host Flag 3 HF3 6 26 Host Request HREQ 6 26 Receive Data Full RDF 6 6 Receive Data Register Full RXDF 6 27 Transmit Data Empty TDE 6 6 Transmit Data Register Empty TXDE 6 26 Transmitter Ready TRDY 6 26 Interface Vector Register IVR 6 27 internal buses 1 10 internal I O memory map B 2 internal program memory 3 1 3 2 internal Y data Memory 3 5 Internal Y I O space 3 7 interrupt 1 8 5 2 configuring 4 14 Host Interface HIO8 6 5 6 6 priorities B 10 source priorities 4 17 sources 4 14 4 15 B 8 table 4 14 table memory map 4 15 trigger mode 4 15 vector 4 15 interrupt and mode control 2 8 interrupt conditions 5 2 interrupt control 2 8 Interrupt Control Register ICR programming sheet B 24 Interrupt Mask I bits 4 9 Interrupt Priority Register Core IPRC 4 14 IRQD IRQA Priority and Mode IDL IAL 4 14 programming sheet B 14 Interrupt Priority Register Peripherals IPRP 4 14 4 15 ESSIO Interrupt Priority Level SOL 4 15 ESSI1 Interrupt Priority Level SIL 4 15 HIOS Interrupt Priority Level HPL 4 1
319. its Mask BPSO0 BPS1 Page Logic Enable Mastership Enable Refresh Enable Software Triggered Refresh Refresh Rate Bits Mask BRFO BRF7 Refresh prescaler Bits External Access Type and Pin Definition Mask BATO BAT1 Address Attribute Pin Polarity Program Space Enable X Data Space Enable DSP56311 User s Manual Rev 2 Freescale Semiconductor M_BYEN M_BAM M_BPAC M_BNC M_BAC M_CP E Q D S lt as ZN S G con wH a A a a E T E E E E E na HH tE st FORO E Z j U Q SEES Myer t paws H E A a a a a A a a ee E Q T Es Y Ss E M_RM M_CPO M_CP1 Haw A O O On Cn On On On On en On On On On en On On en On On On Omen e c con HAW ww T DPO Hw A E M_CDP1 B T Bd E T E T T J td c T trol trol UNEO 5 6 7 SFOO SFFFO0OO and status bits in c00000 WOMANI AHAUPWNEF O I I h l f WR Oo 14 A 15 16 17 7 19 20 21 A 22 23 and status bits in 300 Internal I O Equates Y Data Space Enable Address Muxing Packing Enable Number of Address Address to SR Bits to Compare Mask Compare Bits Mask BAC0 BAC11 mask for CORE DMA priority bits in SR Carry Overflow Zero Negative Unnormalized Extension Limit Scaling
320. ity mode 3 8 Size register SZ 1 8 software polling 6 5 SRAM interfacing 1 10 Stack Counter register SC 1 9 Stack Extension Enable SEN bit 4 11 Stack Extension Overflow Flag EOV bit 4 11 Stack Extension Underflow Flag EUN bit 4 11 Stack Extension Wrap Flag WRP bit 4 11 Stack Extension XY Select X YS bit 4 11 Stack Pointer SP 1 8 standby mode Stop 1 6 Wait 1 6 Status Register SR 1 8 4 5 4 6 bit definitions 4 6 Condition Code Register CCR 4 5 Index Carry C 4 10 Extension E 4 9 Limit L 4 9 Negative N 4 9 Overflow V 4 10 Scaling S 4 9 Unnormalized U 4 9 Zero Z 4 10 Extended Mode Register EMR 4 5 Arithmetic Saturation Mode SM 4 6 Cache Enable CE 4 6 Core Priority CP 4 5 4 6 DO FOREVER FV Flag 4 7 Instruction Cache Enable CE 4 5 Rounding Mode RM 4 6 Sixteen Bit Arithmetic Mode SA 4 6 Mode Register MR 4 5 Do Loop Flag LF 4 7 Double Precision Multiply Mode DM 4 7 Interrupt Mask I 4 9 Scaling S Mode 4 8 Sixteen Bit Compatibility SC Mode 4 8 programming sheet B 12 status registers reading 5 2 Stop Delay Mode SD bit 4 13 STOP instruction 6 20 8 5 Stop standby mode 1 6 Switch mode 1 6 switching memory configuration dynamically 3 7 switching memory sizes 3 2 Synchronous mode 7 9 7 10 7 12 8 2 8 16 Synchronous Serial Interface Status Register SSISR 7 12 7 26 Receive Data Register Full RDF 7 27 Receiver Frame Sync Flag RFS 7 27 Receiver Overrun Error Fla
321. ks for the TX clock and RX clock If an external clock is used for the SCLK input it must be sixteen times the desired bit rate designated as the 16 X clock as indicated in Figure 8 6 When the internal clock is used to supply a clock to an external device the clock can use the actual bit rate designated as the 1 xX clock or the 16 x clock rate as determined by the COD bit The output clock is continuous Select 8 or 9 bit Words SN Idle Line 0 1 2 3 4 5 6 7 8 RX TX Data SSFTD 0 Start Stop Start x1 Clock x16 Clock SCKP 0 Figure 8 6 16 x Serial Clock When SCKP is cleared the transmitted data on the TXD signal changes on the negative edge of the serial clock and is stable on the positive edge When SCKP is set the data changes on the positive edge and is stable on the negative edge The received data on the RXD signal is sampled on the positive edge if SCKP 0 or on the negative edge if SCKP 1 of the serial clock 8 6 4 SCI Data Registers The SCI data registers are divided into two groups receive and transmit as shown in Figure 8 7 There are two receive registers a Receive Data Register SRX and a serial to parallel Receive Shift Register There are also two transmit registers a Transmit Data Register called either STX or STXA and a parallel to serial Transmit Shift Register DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 19 Serial Communication Interface SCI 23 16 15 8 7 0 SCI
322. l Rev 2 Freescale Semiconductor 10 7 Enhanced Filter Coprocessor 10 3 3 FIR Filter Type To select the FIR filter type clear FCSR FLT and perform the processing shown in Figure 10 4 based on the equation shown below The EFCOP takes an input x n from the FDIR saves the N w n YB x n i i 0 input while shifting the previous inputs down in the FDM multiplies each input in the FDM by the corresponding coefficient B stored in the FCM accumulates the multiplication results and places accumulation result w n in the FDOR This is done for each sample input to the FDIR FDM FCM FDIR gt xn 09 Bo gt FDOR x n 1 LO B x n 2 Come Bp x n N Hx By Figure 10 4 FIR Filter Type Processing 10 3 3 1 FIR Operating Modes There are four operating modes available with the FIR filter type E Real E Complex E Alternating complex E Magnitude mode 10 3 3 1 1 Real Mode Real mode performs FIR type filtering with real data and is selected by clearing both FOM bits in the FCSR One sample the real input is written to the FDIR and the EFCOP processes the data Then one sample the real output is read from the FDOR Four options are available with the real FIR filter type coefficient update adaptive mode multichannel mode and decimation The first DSP56311 Reference Manual Rev 2 10 8 Freescale Semiconductor EFCOP Operation thr
323. l mode disabled 1 Three Dimensional mode enabled DMA Address Mode Bits 9 4 Non Three Dimensional Addressing Modes D3D 0 DAM 2 0 source DAM 5 3 Destination DAM 5 3 Addressing Mode Counter Offset Register DAM 2 0 Mode Selection 000 2D DORO 001 2D DOR1 010 2D DOR2 011 2D DOR3 100 No update None 101 Postincrement by 1 None 110 reserved 111 reserved Three Dimensional Addressing Modes D3D 1 DAM 5 3 Addressing Mode Offset Selection 000 2D DORO 001 2D DOR1 010 2D DOR2 011 2D DOR3 100 No update None 101 Postincrement by 1 None 110 3D DORO DOR1 111 3D DOR2 DOR3 DMA Destination Space Bits 3 2 DSS 1 0 DMA Destination Memory 00 X Memory Space 01 Y Memory Space 10 P Memory Space 11 Reserved DMA Source Space Bits 1 0 DSS 1 0 DMA Source Memory 00 X Memory Space 01 Y Memory Space 10 P Memory Space 11 Reserved 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 DTM 2 0 DPR 1 0 JDCON DRS 4 0 DAM 5 0 DMA Cra Res Registers E CRD Reset 000000 aA X FFFFDC X FFFFEO X FFFFE4 X SFFFFES X FFFFEC Read Write Figure B 9 DMA Control Registers 5 0 DCR 5 0 DSP56311 User s Manual Rev 2 B 20 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 1 of 5 Host Transmit Data usually Loaded by program
324. le for use as serial I O flags Their operation is controlled by the SYN SCD 1 0 SSC1 and TE 2 1 bits in the CRB CRA The control bits OF 1 0 and status bits IF 1 0 are double buffered to and from SC 1 0 Double buffering the flags keeps the flags in sync with TX and RX The SC 1 0 flags are available in Synchronous mode only Each flag can be separately programmed The SCo flag is enabled when transmitter 1 is disabled TE1 0 The flag s direction is selected by the SCDO bit When SCDO is set SCO is configured as output When SCDO is cleared SCo is configured as input Similarly the SC1 flag is enabled when transmitter 2 is disabled TE2 0 and the SC1 signal is not configured as the transmitter O drive enabled signal Bit SSC1 0 The direction of SC1 is determined by the SCD1 bit When SCD1 is set SC1 is an output flag When SCD1 is cleared SC1 is an input flag When programmed as input flags the value of the SC 1 O bits is latched at the same time as the first bit of the received data word is sampled Once the input is latched the signal on the input flag signal SCo and SC1 can change without affecting the input flag The value of SC 1 0 does not change until the first bit of the next data word is received When the received data word is latched by RX the latched values of SC 1 0 are latched by the SSISR IF 1 0 bits respectively and can be read by software When they are programmed as output flags the value of
325. length and number of words per frame for serial data 23 22 21 20 19 18 17 16 15 14 13 12 SSC1 WL2 WL1 WLO ALC DC4 DC3 DC2 DC1 DCO 11 10 9 8 7 6 5 4 3 2 1 0 PSR PM7 PM6 PM5 PM4 PM3 PM2 PM1 PMO Reserved bit read as 0 write to O for future compatibility ESSIO X FFFFB5 ESSI1 X FFFFAS Figure 7 2 ESSI Control Register A CRA Table 7 3 ESSI Control Register A CRA Bit Definitions Bit Number Bit Name Reset Value Description 23 0 Reserved Write to 0 for future compatibility 22 SSC1 0 Select SC1 configured as output SCD1 1 Controls the functionality of the SC1 signal If SSC1 is set the ESSI is configured in Synchronous mode the CRB synchronous asynchronous bit SYN is set and transmitter 2 is disabled transmit enable TE2 0 then the SC1 signal acts as the transmitter O driver enabled signal while the SC1 signal is configured as output SCD1 1 This configuration enables an external buffer for the transmitter O output If SSC1 is cleared the ESSI is configured in Synchronous mode SYN 1 and transmitter 2 is disabled TE2 0 then the SC1 acts as the serial I O flag while the SC1 signal is Freescale Semico nductor DSP56311 User s Manual Rev 2 7 13 Enhanced Synchronous Serial Interface ESSI Table 7 3 ESSI Control Register A CRA Bit Definitions Continued Bit Number Bi
326. lexed Bus HMUX 6 17 Host Request Enable HREN 6 18 Host Request Open Drain HROD 6 17 Host Request Polarity HRP 6 16 programming sheet B 4 B 22 host processor address space 6 21 Host Receive HRX register 6 5 6 12 6 20 6 31 Host Receive Data Full HRDF bit 6 6 6 14 Host Receive Interrupt Enable HRIE bit 6 13 Host Receive Request HRRQ 6 8 Host Request Double 2 2 Single 2 2 host request 6 5 enabling 6 8 Host Request HREQ bit 6 26 Host Request Enable HREN bit 6 18 host request line 6 3 Host Request Open Drain HROD bit 6 17 host request pins 6 9 Host Request Polarity HRP bit 6 16 Host Status Register HSR 6 12 6 13 6 30 Host Command Pending HCP 6 14 Host Flags 0 1 HF 6 14 Host Receive Data Full HRDF 6 14 Host Transmit Data Empty HTDE 6 14 Host Transmit HTX register 6 6 6 12 6 20 6 31 Host Transmit Data Empty HTDE bit 6 6 6 14 Host Transmit Data Register HTDR programming sheet B 21 B 25 Host Transmit Interrupt Enable HTIE bit 6 13 Host Vector HV bits 6 25 Hosts Interface HIO8 Interrupt Control Register ICR programming sheet B 24 host to DSP transfers 6 5 HR 2 2 T O space external Y data Memory 3 7 X data Memory 3 5 Y data Memory 3 7 Idle Line Flag IDLE bit 8 16 DSP56311 User s Manual Rev 2 Index 8 Freescale Semiconductor Idle Line Interrupt Enable ILIE bit 8 12 Idle Line Wakeup mode 8 3 Infinite Impulse Response IIR filter 10 1 initialization EFCOP 10 1 In
327. lexed buses H 0 7 HAD 0 7 host data bus H 0 7 or host multiplexed address data bus HAD 0 7 HAS HAO address strobe HAS or host address line HAO HA8 HA1 host address line HA8 or host address line HA1 HA9 HA2 host address line HA9 or host address line HA2 DSP56311 User s Manual Rev 2 Freescale Semiconductor 6 1 Host Interface HI08 Note 6 2 HRW HRD read write select HRW or read strobe HRD HDS HWR data strobe HDS or write strobe HWR HCS HA10 host chip select HCS or host address line HA10 HREQ HTRQ host request HREQ or host transmit request HTRQ HACK HRRQ host acknowledge HACK or host receive request HRRQ The signals in the above list that are shown as asserted low for example HRD all have programmable polarity The default value following reset is shown in the above list Mapping HIOS registers are mapped into eight consecutive locations in the host s external bus address space The HIOS acts as a memory or I O mapped peripheral for microprocessors microcontrollers and so forth Transfer modes Mixed 8 bit 16 bit and 24 bit data transfers DSP to host and host to DSP Host command Handshaking protocols Software polled Interrupt driven Interrupts are compatible with most processors including the MC68000 8051 HC11 and Hitachi H8 Data word 8 bits Dedicated interrupts Separate request li
328. ll other chip power inputs except Voco The user must provide adequate external decoupling capacitors Vecs ESSI SCI and Timer Power An isolated power for the ESSI SCI and timer l O drivers This input must be tied externally to all other chip power inputs except Voco The user must provide adequate external decoupling capacitors Freescale Semiconductor DSP56311 User s Manual Rev 2 2 3 Signals Connections 2 2 Ground Table 2 3 Grounds Ground Name Description GNDp PLL Ground A ground dedicated for PLL use The connection should be provided with an extremely low impedance path to ground Vccp should be bypassed to GNDp by a 0 47 uF capacitor located as close as possible to the chip package GNDp PLL Ground 1 A ground dedicated for PLL use The connection should be provided with an extremely low impedance path to ground GND Ground Connected to an internal device ground plane The user must provide adequate external decoupling capacitors for all GND connections 2 3 Clock Table 2 4 Clock Signals State During Reset Signal Name Signal Description Type EXTAL Input Input External Clock Crystal Input Interfaces the internal crystal oscillator input to an external crystal or an external clock XTAL Output Chip driven Crystal Output Connects the internal crystal oscillator output to an external crystal If an external clock is used leav
329. ll the bits in the CRB Table 7 2 Mode and Signal Definitions on page 7 4 summarizes the relationship between the ESSI signals SC 2 0 SCK and the CRB bits The ESSI has two serial output flag bits OF1 and OFO The normal sequence follows for setting output flags when transmitting data by transmitter 0 through the STD signal only 1 Wait for TDE TXO empty to be set 2 Write the flags 3 Write the transmit data to the TX register Bits OFO and OF are double buffered so that the flag states appear on the signals when the TX data is transferred to the transmit shift register The flag bit values are synchronized with the data transfer The timing of the optional serial output signals SC 2 0 is controlled by the frame timing and is not affected by the settings of TE2 TE1 TEO or the receive enable RE bit of the CRB The ESSI has three transmit enable bits TE 2 0 one for each data transmitter The process of transmitting data from TX1 and TX2 is the same TXO differs from these two bits in that 1t can also operate in Asynchronous mode The normal transmit enable sequence is to write data to one or more transmit data registers or the Time Slot Register TSR before you set the TE bit The normal transmit disable sequence is to set the Transmit Data Empty TDE bit and then to clear the TE Transmit Interrupt Enable TIE and Transmit Exception Interrupt Enable TEIE bits In Network mode if you clear the appropriate TE bit and se
330. lter Coprocessor 10 The enhanced filter coprocessor EFCOP peripheral module functions as a general purpose fully programmable filter It has optimized modes of operation to perform single channel and multichannel real and complex finite impulse response FIR filtering with and without adaptive FIR filtering and decimation or single channel and multichannel infinite impulse response IIR filtering EFCOP filter operations complete concurrently with DSP56300 core operations with minimal CPU intervention For optimal performance the EFCOP has one dedicated Filter Multiplier Accumulator FMAC unit Thus for filtering the combination Core EFCOP offers dual MAC capabilities Its dedicated modes make the EFCOP a very flexible filter coprocessor with operations optimized for cellular base station applications The EFCOP architecture also allows adaptive FIR filtering in which the filter coefficient update is performed using any fixed point standard or non standard adaptive algorithms for example the well known Least Mean Square LMS algorithm the Normalized LMS and customized update algorithms In a transceiver base station the EFCOP can perform complex matched filtering to maximize the signal to noise ratio SNR within an equalizer In a transcoder base station or a mobile switching center the EFCOP can perform all types of FIR and IIR filtering within a vocoder as well as LMS type echo cancellation This chapter describes the EFCOP features ar
331. ly for use as the bit clock to shift the transmit and receive shift registers Figure 7 3 shows the ESSI clock generator functional block diagram Forg is the DSP56311 core clock frequency the same frequency as the enabled CLKOUT signal Careful choice of the crystal oscillator frequency and the prescaler modulus can generate the industry standard CODEC master clock frequencies of 2 048 MHz 1 544 MHz and 1 536 MHz Freescale Semiconductor DSP56311 User s Manual Rev 2 7 15 Enhanced Synchronous Serial Interface ESSI TX 1 or FlagO Out Flago In CRB TE1 CRB OFO SSISR IFO Sync Mode Sync Mode CRA WL2 0 RX 8 12 16 24 lt gt Word Clock Sync TX 1 or FlagO Async CRB SCDO RX clk TX lt gt Word Clock Sync TX RX clk pde CRB SCKD sells e Fcoore is the DSP56300 core internal CRA PSR CRA PM7 0 clock frequency e ESSI internal clock range min Fosc 4096 0 max Fosc 4 Fcore Opposite e n in signal name is ESSI 0 or 1 from SSI Figure 7 3 ESSI Clock Generator Functional Block Diagram CRB FSL1 RX Word CRB FSR Clock cee Internal Rx Frame Sync CRB SCD1 CRB SCD1 CRB SYN 0 a Receiv ecsive Receive Control Logic Sync TX 2 Flag or drive enb Async RX F S Frame Sync o SYN These signals are identical in sync mode Pay aay Oi ara Flag In TX 2 Flagi Out or drive enb SSISR IF1 Syne Mode
332. ly status bit 1 No initialization 0 FDIR is not empty e 1 FDIR is empty Coefficients Bit 8 0 Not shared Filter Data Output Buffer Full Bit 15 1 Shared Read only status bit 0 FDOR is not full 1 FDOR is full 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 EES SS EEE li e il EFCOP Control Status Register FCSR Y FFFFB4 Read Write Reset 000000 k Reserved Program as 0 Figure B 27 EFCOP Counter and Control Status Registers FCNT and FCSR DSP56311 User s Manual Rev 2 B 38 Freescale Semiconductor Application EFCOP Saturation Mode Bit 4 0 Disabled 1 Enabled Sixteen bit Arithmetic Mode Bit 5 0 Disabled 1 Enabled Filter Input Scaling Bit 6 0 Notused 1 Used Programming Sheets Date Programmer Sheet 2 of 2 Filter Rounding Mode Bits 3 2 00 Convergent GFE Two s complemen Filter Scaling Bits 1 0 10 Truncation 00 x 1 10 x 16 Reserved 01 x 8 11 Reserved AI AIII eT 5 a a 3 2 5 FISL FSA FSM Rounding Filter 0 0 0 0 0 0 0 0 0 ee iene EFCOP ALU Control Register FACR Y FFFFB5 Read Write Reset 000000 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 O0 Data Base Address FDM Pointer EFCOP Data Base Address FDBA Y FFFFB6 Read Write Reset 000000 15 14 13 12 11 10 9 8 76 5 4 3 2 1 0 Coefficient Base Address FDM Pointer EFCOP Coefficient Base Address FCBA Y FFFFB7 Read Write Reset 23 22 21 20 19 18 17 16
333. m execution starts in the same address wher loading started The SCI is programmed to work in asynchronous mode with 8 data bits 1 stop bit and no parity The clock source is external and the clock frequency must be 16x the baud rate After each byte is received it is echoed back through the SCI transmitter A A A NA Operation mode MD MC MB MA 1011 is reserved If MD MC MB MA 1100 then the program RAM is loaded from the Host Interface programmed to operate in the ISA mode The HOST ISA bootstrap code expects to read a 24 bit word specifying the number of program words a 24 bit word specifying the address to start loading the program words and then a 24 bit word for each program word to be loaded The program words are stored in contiguous PRAM memory locations starting at the specified starting address After the program words are read program execution starts from the same address where loading started The Host Interface bootstrap load program can be stopped by setting the Host Flag 0 HFO This starts execution of the loaded program from the specified starting address If MD MC MB MA 1101 then the program RAM is loaded from the Host Interface programmed to operate in the HC11 non multiplexed mode The HOST HC11 bootstrap code expects to read a 24 bit word specifying the number of program words a 24 bit word specifying the address
334. m the RREQ bit to assert the external HREQ signal when ISR RXDF is set This indicates that the HIOS has a full word either 8 16 or 24 bits for the host processor The host processor can program the RREQ bit to assert the external HREQ signal when ISR RXDF is set Assertion of the HREQ signal informs the host processor that the receive byte registers have data to be read When the host reads the receive byte register at host address 7 the ISR RXDF bit is cleared DSP56311 User s Manual Rev 2 Freescale Semiconductor 6 27 Host Interface HI08 Note The external host should never read the RXH RXM RXL registers if the ISR RXDF bit is cleared 6 7 6 Transmit Data Registers TXH TXM TXL The host processor views the transmit byte registers as three 8 bit write only registers These registers are the transmit high register TXH the transmit middle register TXM and the transmit low register TXL These registers send data to the high middle and low bytes respectively of the HRX register and are selected by the external host address inputs HA 2 0 during a host processor write operation If ICR HLEND is set the TXH register is located at address 7 the TXM register at 6 and the TXL register at 5 If the HLEND bit in the ICR is cleared the TXH register is located at address 5 the TXM register at 6 and the TXL register at 7 Data can be written into the transmit byte registers when the ISR transmit data register
335. mand Vector Register CVR Bit Definitions Bit Number Bit Name Reset Value Description 7 HC 0 Host Command The host processor uses the HC bit to handshake the execution of host command interrupts Normally the host processor sets HC to request a host command interrupt from the DSP56311 When the DSP56311 acknowledges the host command interrupt HIO8 hardware clears the HC bit The host processor can read the state of HC to determine when the host command has been accepted After setting HC the host must not write to the CVR again until the HIO8 hardware clears the HC Setting the HC bit causes host command pending HCP to be set in the HSR The host can write to the HC and HV bits in the same write cycle 6 0 HV 6 0 32 Host Vector Select the host command interrupt address for use by the host command interrupt logic When the DSP interrupt control logic recognizes the host command interrupt the address of the interrupt routine taken is 2 x HV The host can write HC and HV in the same write cycle The host processor can select any of the 128 possible interrupt routine starting addresses in the DSP by writing the interrupt routine address divided by 2 into the HV bits This means that the host processor can force any interrupt handler ESSI SCI IRQA IRQB and so forth and can use any reserved or otherwise unused addresses if have been pre programmed in the DSP HV is set to 32 vector location 064 by hardware software
336. memory occur up to three instructions after the instruction that changes the OMR bits CAUTION To ensure that dynamic switching is trouble free do not allow any accesses including instruction fetches to or from the affected address ranges in program and data memories during the switch cycle DSP56311 User s Manual Rev 2 Freescale Semiconductor 3 7 Memory Configuration Because an interrupt could cause the DSP to fetch instructions out of sequence and might violate the switch condition special care should be taken in relation to the interrupt vector routines CAUTION Pay special attention when executing a memory switch routine using the OnCE port Running the switch routine in trace mode for example can cause the switch to complete after the MS MSW bits change while the DSP is in Debug mode As a result subsequent instructions may be fetched according to the new memory configuration after the switch and thus may execute improperly 3 5 Sixteen Bit Compatibility Mode Configuration The sixteen bit compatibility SC mode allows the DSP56311 to use DSP56000 object code without change The SC bit Bit 13 in the SR is used to switch from the default 24 bit mode to this special 16 bit mode SC is cleared by reset You must set this bit to select the SC mode The address ranges described in the previous sections apply in the SC mode with regard to the reallocation of X and Y data memory to program memory
337. mer Module Programming Model Table 9 3 Timer Control Status Register TCSR Bit Definitions Continued Bit Number Bit Name Reset Value Description 2 TCIE 0 Timer Compare Interrupt Enable Enables disables the timer compare interrupts When set TCIE enables the compare interrupts In the timer pulse width modulation PWM or watchdog modes a compare interrupt is generated after the counter value matches the value of the TCPR The counter starts counting up from the number loaded from the TLR and if the TCPR value is M an interrupt occurs after M N 1 events where N is the value of TLR When cleared the TCSR TCIE bit disables the compare interrupts TOIE 0 Timer Overflow Interrupt Enable Enables timer overflow interrupts When set TOIE enables overflow interrupt generation The timer counter can hold a maximum value of F FFFFF When the counter value is at the maximum value and a new event causes the counter to be incremented to 000000 the timer generates an overflow interrupt When cleared the TOIE bit disables overflow interrupt generation TE 0 Timer Enable Enables disables the timer When set TE enables the timer and clears the timer counter The counter starts counting according to the mode selected by the timer control TC 3 0 bit values When clear TE bit disables the timer Note When all three timers are disabled and the signals are not in GPIO mode all three TIO
338. mit Data Register 0 TX00 FFBB FFFFBB ESSI 0 Transmit Data Register 1 TX01 FFBA FFFFBA ESSI 0 Transmit Data Register 2 TX02 FFB9 FFFFB9 ESSI 0 Time Slot Register TSRO FFB8 FFFFB8 ESSI 0 Receive Data Register RX0 FFB7 FFFFB7 ESSI 0 Status Register SSISRO FFB6 FFFFB6 ESSI 0 Control Register B CRBO FFB5 FFFFB5 ESSI 0 Control Register A CRAO FFB4 FFFFB4 ESSI 0 Transmit Slot Mask Register A TSMAO FFB3 FFFFB3 ESSI 0 Transmit Slot Mask Register B TSMBO FFB2 FFFFB2 ESSI 0 Receive Slot Mask Register A RSMAO FFB1 FFFFB1 ESSI 0 Receive Slot Mask Register B RSMBO FFBO FFFFBO Reserved Port D FFAF FFFFAF Port D Control Register PCRD FFAE FFFFAE Port D Direction Register PRRD FFAD FFFFAD Port D GPIO Data Register PDRD ESSI 1 FFAC FFFFAC ESSI 1 Transmit Data Register 0 TX10 FFAB FFFFAB ESSI 1 Transmit Data Register 1 TX11 FFAA FFFFAA ESSI 1 Transmit Data Register 2 TX12 FFA9 FFFFA9 ESSI 1 Time Slot Register TSR1 FFA8 FFFFA8 ESSI 1 Receive Data Register RX1 FFA7 FFFFA7 ESSI 1 Status Register SSISR1 FFA6 FFFFA6 ESSI 1 Control Register B CRB1 FFA5 FFFFA5 ESSI 1 Control Register A CRA1 FFA4 FFFFA4 ESSI 1 Transmit Slot Mask Register A TSMA1 FFA3 FFFFA3 ESSI 1 Transmit Slot Mask Register B TSMB1 FFA2 FFFFA2 ESSI 1 Receive Slot Mask Register A RSMA1 FFA1 FFFFA1 ESSI 1 Receive Slot Mask Register B RSMB1 FFAO FFFFAO Reserved Port E FFOF SFFFF9F Port E Control
339. mming Reference Peripheral addresses interrupt addresses and interrupt priorities for the DSP56311 programming sheets listing the contents of the major DSP56311 registers for programmer s reference Manual Conventions This manual uses the following conventions Bits within registers are always listed from most significant bit MSB to least significant bit LSB Bits within a register are indicated AA n m n gt m when more than one bit is involved in a description For purposes of description the bits are presented as if they are contiguous within a register However this is not always the case Refer to the programming model diagrams or to the programming sheets to see the exact location of bits within a register When a bit is set its value is 1 When a bit is cleared its value is 0 The word assert means that a high true active high signal is pulled high to Vcc or that a low true active low signal is pulled low to ground The word deassert means that a high true signal is pulled low to ground or that a low true signal is pulled high to Vcc See Table 1 1 DSP56311 User s Manual Rev 2 Freescale Semiconductor Manual Conventions Table 1 1 High True Low True Signal Conventions Signal Symbol Logic State Signal State Voltage PIN True Asserted Ground PIN False Deasserted Voc PIN True Asserted Voc PIN False Deasserted Ground Notes 1 PIN is a generic
340. n Bits 55 48 Scale up Bits 5 46 a olo O o Reserved Undefined Unnormalized Set if the two MSBs of the Most Significant Portion MSP of the result are identical otherwise this bit is cleared The MSP portion of the A or B accumulators is defined by the Scaling mode S1 so Scaling Mode Integer Portion No scaling U Bit 47 XOR Bit 46 Scale down U Bit 48 XOR Bit 47 Scale up U Bit 46 XOR Bit 45 a O O Reserved U undefined Freescale Semiconductor DSP56311 User s Manual Rev 2 4 9 Core Configuration Table 4 2 Status Register Bit Definitions Continued Bit Number Bit Name Reset Value Description 3 N 0 Negative Set if the MSB of the result is set otherwise this bit is cleared Zero Set if the result equals zero otherwise this bit is cleared Overflow Set if an arithmetic overflow occurs in the 56 bit result otherwise this bit is cleared V indicates that the result cannot be represented in the accumulator register that is the register overflowed In Arithmetic Saturation mode an arithmetic overflow occurs if the Data ALU result is not representable in the accumulator without the extension part that is 48 bit accumulator or the 32 bit accumulator in Arithmetic Sixteen bit mode Carry Set if a carry is generated by the MSB resulting from an addit
341. n Port for details on using the external memory interface to access external X data memory Note The X memory space at locations FF0000 FFEFFF is reserved and should not be accessed DSP56311 User s Manual Rev 2 Freescale Semiconductor 3 3 Memory Configuration 3 2 1 Internal X Data Memory The default on chip X data RAM is a 24 bit wide internal static memory occupying the lowest 48 K locations 0 BFFF in X memory space The on chip X data RAM is organized into 48 banks with 1024 locations each Available X data memory space is reduced and reallocated to program memory using the memory switch mode described in the next section 3 2 2 Memory Switch Modes X Data Memory Memory switch mode reallocates of portions of X and Y data RAM as program RAM Bit 7 in the OMR is the MS bit that controls this function as follows 3 4 When the MS bit is cleared the X data memory consists of the default 48K x 24 bit memory space described in the previous section In this default mode the lowest external X data memory location is 6000 When the MS bit is set a portion of the higher locations of the internal X memory is switched to internal program memory The memory switch MSW 1 0 configuration bits in the OMR select one of the following options MSW 1 0 00 The 32K higher locations 4000 BFFF of the internal X memory are switched to internal program memory and therefore the highest internal X memor
342. n Synchronous mode and is ignored when the ESSI is in Asynchronous mode When TE1 is set and a frame sync is detected transmitter 1 is enabled for that frame When TE1 is cleared transmitter 1 is disabled after completing transmission of data currently in the ESSI transmit shift register Any data present in TX1 is not transmitted If TE1 is cleared data can be written to TX1 the TDE bit is cleared but data is not transferred to transmit shift register 1 If the TE1 bit is kept cleared until the start of the next frame it causes the SCO signal to act as serial I O flag from the start of the frame in both Normal and Network mode The transmit enable sequence in On Demand mode can be the same as in Normal mode or the TE1 bit can be left enabled Note The setting of the TE1 bit does not affect the generation of frame sync or output flags DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 19 Enhanced Synchronous Serial Interface ESSI Table 7 4 ESSI Control Register B CRB Bit Definitions Continued Bit Number Bit Name Reset Value Description 14 TE2 0 Transmit 2 Enable Enables the transfer of data from TX2 to Transmit Shift Register 2 TE2 is functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is in Asynchronous mode When TE2 is set and a frame sync is detected transmitter 2 is enabled for that frame When TE2 is cleared transmitter 2 is disabled after completi
343. n enabled 1 MSB First 1 Transmit Interrupts Enabled Wired Or Mode Select Send Break Timer Interrupt Enable 1 Multidrop 0 Send break then revert 0 Timer Interrupts Disabled 0 Point to Point i 1 Timer Interrupts Enabled 1 Gontinyally send breaks Receiver Enable Wak Mode Select SCI Timer Interrupt Rate 0 Receiver Disabled 0 idle Line Wakeup 0 32 1 1 1 Receiver Enabled 1 Address Bit Wakeup SCI Clock Polarity 0 Clock Polarity is Positive 1 Clock Polarity is Negative SCI Receive Exception Inerrupt 0 Receive Interrupt Disable 1 Receive Interrupt Enable 23 16 15 14 13 9 8 7 6 5 4 3 2 1 0 REIE SCKP STIR TMIE TIE RIE ie TE RE i ie a ake wps2 wps1 wDso SCI Control Register SCR X FFFF9C Read Write Reset 000000 Reserved Program as 0 Figure B 18 SCI Control Register SCR DSP56311 User s Manual Rev 2 Freescale Semiconductor B 29 Programming Reference Application Date Programmer Sheet 2 of 2 Clock Divider Bits CD11 CD0 TX Clock RX Clock SCLK Pin Mode Internal Internal Output Synchronous Asynchronous CD11 CDO Icyc Rate Internal External Input Asynchronous only 000 loyo l External Internal Input Asynchronous only 001 loyo 2 002 loyo 3 External External Input Synchronous Asynchronous loyc 4095 Receiver Clock Mode Source loyc 4096 0 Internal clock for Receiver 1 External clock from SCLK
344. n performed at both ends of the line or an error in transmission has occurred WDS2 WDS1 WDSO Mode Word Formats 0 0 0 0 8 Bit Synchronous Data shift register mode 0 0 1 1 Reserved 0 1 0 2 10 Bit Asynchronous 1 start 8 data 1 stop 1 1 1 3 Reserved 1 0 0 4 11 Bit Asynchronous 1 start 8 data 1 even parity 1 stop 1 0 1 5 11 Bit Asynchronous 1 start 8 data 1 odd parity 1 stop 1 1 0 6 11 Bit Multidrop Asynchronous 1 start 8 data 1 data type 1 stop 0 1 1 7 Reserved DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 6 2 SCI Status Register SSR The SSR is a read only register that indicates the status of the SCI 23 22 21 20 19 18 SCI Programming Model 17 16 15 14 13 12 11 10 6 5 4 3 R8 FE PE OR IDLE RDRF TDRE TRNE Reserved bit read as 0 write to O for future compatibility Table 8 3 SCI Status Register Table 8 4 SCI Status Register SSR Bit Definitions Bit Number Bit Name Reset Value Description 23 8 0 Reserved Write to O for future compatibility 7 R8 0 Received Bit 8 In 11 bit Asynchronous Multidrop mode the R8 bit indicates whether the received byte is an address or data R8 is set for addresses and is cleared for data R8 is not affected by reads of the SRX or SCI status regist
345. nal is asserted as an output for three clock cycles when the chip enters debug mode as a result of a debug request or a breakpoint condition The DE has an internal pull up resistor DE is not a standard part of the JTAG TAP controller The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered debug mode All other interaction with the OnCE module must occur through the JTAG port DSP56311 User s Manual Rev 2 Freescale Semiconductor 2 19 Signals Connections DSP56311 User s Manual Rev 2 2 20 Freescale Semiconductor Memory Configuration 3 Like all members of the DSP56300 core family the DSP56311 addresses three sets of 16 Mx 24 bit memory internally program X data and Y data Each of these memory spaces includes both internal and external memory accessed through the external memory interface The DSP56311 is extremely flexible because it has several modes to allocate internal memory between the program memory and the two data memory spaces You can also configure it to operate in a special sixteen bit compatibility mode that allows the chip to use DSP56000 object code without any change this can result in higher performance of existing code for applications that do not require a larger address space This section provides detailed information on each of these memory spaces 3 1 Program Memory Space Program memory s
346. nals With a small amount of additional logic the SCI can connect to peripheral interfaces that have non TTL level signals such as the RS 232C RS 422 etc This interface uses three dedicated signals transmit data receive data and SCI serial clock It supports industry standard asynchronous bit rates and protocols as well as high speed synchronous data transmission up to 12 5 Mbps for a 100 MHz clock SCI asynchronous protocols include a multidrop mode for master slave operation with wakeup on idle line and wakeup on address bit capability This mode allows the DSP56311 to share a single serial line efficiently with other peripherals Separate SCI transmit and receive sections can operate asynchronously with respect to each other A programmable baud rate generator provides the transmit and receive clocks An enable vector and an interrupt vector allow the baud rate generator to function as a general purpose timer when the SCI is not using it or when the interrupt timing is the same as that used by the SCI DSP56311 User s Manual Rev 2 Freescale Semiconductor 1 13 DSP56311 Overview 1 9 5 Timer Module The triple timer module is composed of a common 21 bit prescaler and three independent and identical general purpose 24 bit timer event counters each with its own memory mapped register set Each timer has the following properties E A single signal that can function as a GPIO signal or as a timer signal E Uses internal or external
347. nce signal D n ORG x DES_ADDRS NCLUDE desired asm Desired signal R n 10 3 6 4 Verification for Filter Examples The following sections provide input and output program listings for the examples given in Section 10 3 6 1 through Section 10 3 6 3 10 3 6 4 1 Input Sequence input asm de 000000 de 37cc8a de 343fae da 0b63b1 de 0595b4 dc 38f46e de S6a4ea2 de 5e8562 dc 2beda5 dc 1b3cd0 dc 42f452 de 684ca0 de 5093b0 dc 128ab8 de Sf 74eel dc 15c13a de 336e48 de 15e98e dc d428d2 dc Sb76af5 dc d69eb3 dc S 749b6 dc Sdee460 DSP56311 Reference Manual Rev 2 10 32 Freescale Semiconductor a43601 S9030d59 b9999a e5744e 10 3 6 4 2 Filter Coefficients coefs asm 10 3 6 4 3 Output Sequence for Examples 10 1 10 2 and 10 3 F8125C F77839 SF4E9EE F29373 SF2DC9A SF51D6E SF688CE SF6087E SF5B5D3 SF7E65E SFBEOF8 SFEC8B7 SFF79F5 000342 02B24F 06C977 096ADD 097556 08FD54 SOA59A5 d69ea9 ccae36 Sc48f2a Sbe8b28 Sbad8c5 b9998c Sbad8cb Sbe8b2d 6759 06 Freescale Semiconductor DSP56311 Reference Manual Rev 2 EFCOP Operation 10 33 Enhanced Filter Coprocessor 10 3 6 4 4 Desired Signal for Example 10 4 dc dc dc 000000 0D310F S19EA7C 25B8E2 30312E 38F46D 3FB327 443031 4642D6 45D849 42F452 3DB126 363E7F S2CDFE8 S21EA5B 15C13A 08D2CE SFB945D SEE7E02 SE2066F D69EB2 SCCAE3C SC48
348. nd transmit data paths are double buffered for efficient high speed asynchronous transfers The host side transmit data path host writes is also the DSP side receive path the host side receive data path host reads is also the DSP side transmit path The Receive RXH RXM RXL and Transmit Data Registers TXH TXM TXL use the same host address During host writes to these addresses the data is transferred to the Transmit Data Registers while reads are performed from the Receive Data Registers 6 4 Operation The HIOS is a slave only device so the host is the master of all bus transfers In host to DSP transfers the host writes data to the Transmit Data Registers TXH TXM TXL In DSP to host transfers the host reads data from the Receive Data Registers RXH RXM RXL The DSP side has access only to the Host Receive Data Register HRX and the Host Transmit Data Register HTX Data automatically moves between the host side data registers and the DSP side data registers when it is available This double buffered mechanism allows for fast data transfers but creates a pipeline that can either stall communication if the pipeline is either full or empty or cause erroneous data transfers new data to be overwritten or old data to be read twice The HIO8 port has several handshaking mechanisms to counter these buffering effects Suppose the host is writing several pieces of data to the HIOS port The host first uses one of the handshaking protoc
349. nding on the peripheral from two to six peripheral interrupt sources are available to the programmer Example 5 2 shows a short interrupt programmed for the HI08 The main program enables the Host Receive Interrupt in the Host Control Register HCR When the interrupt is triggered during code execution the core processing jumps to the Host Receive Interrupt routine location at p 60 and executes the code there Since this is a short interrupt the core returns to normal code execution after executing the two move instructions and an RTI instruction is not necessary Example 5 2 Interrupts bset M_HRIE x M_HCR enable host receive interrupt Short Interrupt Routine orgP 60 movepx M_HRX x1 HIO8 Receive Data Full interrupt movex1 y r0 5 4 3 DMA The Direct Memory Access DMA controller permits data transfers between internal external memory and or internal external I O in any combination without the intervention of the DSP56311 core Dedicated DMA address and data buses and internal memory partitioning ensure that a high level of isolation is achieved so the DMA operation does not interfere with the core operation or slow it down The DMA moves data to from the peripheral transmit receive registers The programmer can use the DMA control registers to configure sources and destinations of data transfers Depending on the peripheral one to four peripheral request sources are available This is the most efficient meth
350. ne controls the different processing states of the DSP56300 core The PCU consists of three hardware blocks E Program decode controller Decodes the 24 bit instruction loaded into the instruction latch and generates all signals for pipeline control E Program address generator Contains all the hardware needed for program address generation system stack and loop control E Program interrupt controller Arbitrates among all interrupt requests internal interrupts as well as the five external requests IRQA IRQB IRQC IRQD and NMI and generates the appropriate interrupt vector address PCU features include the following Position independent code support Addressing modes optimized for DSP applications including immediate offsets Instruction cache controller Internal memory expandable hardware stack Nested hardware DO loops Fast auto return interrupts Hardware system stack The PCU uses the following registers Program counter register Status register Loop address register Loop counter register Vector base address register Size register Stack pointer Operating mode register DSP56311 User s Manual Rev 2 Freescale Semiconductor DSP56300 Core Functional Blocks E Stack counter register 1 6 4 PLL and Clock Oscillator The clock generator in the DSP56300 core comprises two main blocks the PLL which performs clock input division frequency multiplication and skew elimination and the clock g
351. ne for the imaginary part of the input must be written to the FDIR before two output samples one for the real part and one for the imaginary part of the output can be read from the FDOR For Alternating Complex mode two times the decimation ratio number of samples must be written to the FDIR one for the real part and one for the imaginary part of the input before one output sample alternating between the real part and the imaginary part of the output can be read from the FDOR 10 3 4 IIR Filter Type To select the IIR filter type set the FCSR FLT bit and perform the processing shown in Figure 10 5 based on the equation shown here The EFCOP multiplies each previous output value in the M y n S w n Y Ay n j j 1 DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 11 Enhanced Filter Coprocessor FDM by the corresponding coefficient A stored in the FCM accumulates the multiplication results adds the input w n from the FDIR which is optionally not scaled by S depending on the FACR FISL bit setting places the accumulation result y n in the FDOR and saves the output while shifting the previous outputs down in the FDM This is done for each sample input to the FDIR To process a complete IIR filter a FIR filter type session followed by an IIR filter type session is needed FDM FCM Lp yn 1 x Ao FDOR yn 2 HX A 3 x y A 4 y A FDIR yn N
352. negative number 8000 if underflow occurred after processing of all filter taps is completed In saturation mode the result is limited to the most positive number 7FFF if overflow occurred or the most negative number 8000 DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 5 Enhanced Filter Coprocessor if underflow occurred after every MAC operation The 16 bit result from the FMAC is stored in the EFCOP output buffer FDOR 10 3 EFCOP Operation DSP56311 EFCOP operation is determined by the control bits in the EFCOP Control Status Register FCSR described in Section 10 4 5 Further filtering operations are enabled via the appropriate bits in the FACR and FDCH registers After the FCSR is configured to the mode of choice enable the EFCOP by setting FCSR FEN Note To ensure proper EFCOP operation most FCSR bits must be changed only while the EFCOP is enabled Table 10 2 summarizes the EFCOP operating modes Table 10 2 EFCOP Operating Modes FCSR Bits Mode Description 6 5 4 3 2 1 0 FMLC FOM FUPD2 FADP2 FLT FEN EFCOP Disabled x x x x x 0 FIR Real single channel 0 00 0 0 0 1 FIR Real adaptive single channel 0 00 0 1 0 1 FIR Real coeff update single channel 0 00 1 0 0 1 FIR Real adaptive coeff update 0 00 1 1 0 1 single channel FIR Real multichannel 1 00 0 0 0 1 FIR Real adaptive multichannel 1 00 0 1 0 1 FIR Real coeff update m
353. nes for each interrupt source Special host commands force DSP core interrupts under host processor control These commands are useful for e Real time production diagnostics e Creation of a debugging window for program development e Host control protocols Interface capabilities Glueless interface no external logic required to e HCII e Hitachi H8 e 8051 family e Thomson P6 family Minimal glue logic pull ups pull downs required to interface to e ISA bus e Freescale 68K family e Intel X86 family DSP56311 User s Manual Rev 2 Freescale Semiconductor Host Port Signals 6 2 Host Port Signals The host port signals are discussed in Chapter 2 Signals Connections Each host port signal can be programmed as a host port signal or as a GPIO signal PB 0 15 See Table 6 1 through Table 6 3 Table 6 1 HIO8 Signal Definitions for Operational Modes HI08 Port Signal Multiplexed Address Data Bus Mode Non multiplexed Bus Mode GPIO Mode HAD 0 7 HAD 0 7 H O 7 PB O 7 HAS HAO HAS HAS HAO PB8 HA8 HA1 HA8 HA1 PB9 HA9 HA2 HA9 HA2 PB10 HCS HA10 HA10 HCS HCS PB13 Table 6 2 HI08 Data Strobe Signals H108 Port Signal Single Strobe Mode Dual Strobe Mode GPIO Mode HRW HRD HRW HRD HRD PB11 HDS HWR HDS HDS HWR HWR PB12 Table 6 3 HIO8 Host Request Signals HIO8 Port Signal Single Host Request Mode Double Host Request Mode GPIO Mode HREQ HREQ
354. ng transmission of data currently in the ESSI transmit shift register Any data present in TX2 is not transmitted If TE2 is cleared data can be written to TX2 the TDE bit is cleared but data is not transferred to transmit shift register 2 If the TE2 bit is kept cleared until the start of the next frame it causes the SC1 signal to act as a serial I O flag from the start of the frame in both Normal mode and Network mode The transmit enable sequence in On Demand mode can be the same as in Normal mode or the TE2 bit can be left enabled Note The setting of the TE2 bit does not affect the generation of frame sync or output flags 13 MOD 0 Mode Select Selects the operational mode of the ESSI as in Figure 7 8 on page 25 Figure 7 9 on page 26 and Figure 7 10 on page 26 When MOD is cleared the Normal mode is selected when MOD is set the Network mode is selected In Normal mode the frame rate divider determines the word transfer rate one word is transferred per frame sync during the frame sync time slot In Network mode a word can be transferred every time slot For details see Section 7 3 12 SYN 0 Synchronous Asynchronous Controls whether the receive and transmit functions of the ESSI occur synchronously or asynchronously with respect to each other See Figure 7 7 on page 24 When SYN is cleared the ESSI is in Asynchronous mode and separate clock and frame sync signals are used for the transmit and receive sections Wh
355. ngth depends on the BRW 1 0 bits a refresh access is as long as the out of page access 13 BREN 0 Bus Refresh Enable Enables disables the internal refresh counter When BREN is set the refresh counter is enabled and a refresh request CAS before RAS is generated each time the refresh counter reaches zero A refresh cycle occurs for all DRAM banks together that is all pins that are defined as RAS are asserted together When this bit is cleared the refresh counter is disabled and a refresh request may be software triggered by using the BSTR bit In a system in which DSPs share the same DRAM the DRAM controller of more than one DSP may be active but it is recommended that only one DSP have its BREN bit set and that bus mastership is requested for a refresh access If BREN is set and a WAIT instruction is executed periodic refresh is still generated each time the refresh counter reaches zero If BREN is set and a STOP instruction is executed periodic refresh is not generated and the refresh counter is disabled The contents of the DRAM are lost DSP56311 User s Manual Rev 2 Freescale Semiconductor 4 23 Core Configuration Table 4 9 DRAM Control Register DCR Bit Definitions Continued Bit Reset A Number Bit Name Value Description 12 BME 0 Bus Mastership Enable Enables disables interface to a local DRAM for the DSP When BME is cleared the RAS and CAS pins are tri stated when mastership
356. nnel filtering can be located If M lt 2 there will be a space between sequential circular buffers of 2k M The address pointer is not required to start at the lower address boundary or to end on the upper address boundary It can point anywhere within the defined modulo address range If the data address pointer FDBA increments and reaches the upper boundary of the modulo buffer it will wrap around to the lower boundary 10 4 8 EFCOP Coefficient Base Address FCBA The FCBA is a 16 bit read write counter register used as an address pointer to the EFCOP FCM bank FCBA points to the first location of the coefficient table The FCBA points to a modulo buffer of size M defined by the filter length M FCNT 11 0 1 The address range of this modulo buffer is defined by lower and upper address boundaries The lower address boundary is the FCBA value with 0 in the k LSBs where 2 gt M gt 2 it therefore must be a multiple of 2 The upper boundary is equal to the lower boundary plus M 1 Since M 2 once M has been chosen that is FCNT has been assigned a sequential series of coefficient memory blocks each of length 2 is created where multiple circular buffers for multichannel filtering can be located If M lt 2 there will be a space between sequential circular buffers of 2 M The FCBA address pointer must be assigned to the lower address boundary that is it must have 0 in its k LSBs In a compute session the coef
357. nput signal receives byte oriented serial data and transfers the data to the SCI receive shift register Asynchronous input data is sampled on the positive edge of the receive clock 1 x SCLK if the SCI Clock Polarity SCKP bit is cleared RXD can be configured as a GPIO signal PEO when the SCI RXD function is not in use 8 2 2 Transmit Data TXD This output signal transmits serial data from the SCI transmit shift register Data changes on the negative edge of the asynchronous transmit clock SCLK if SCKP is cleared This output is stable on the positive edge of the transmit clock TXD can be programmed as a GPIO signal PE1 when the SCI TXD function is not in use 8 2 3 SCI Serial Clock SCLK This bidirectional signal provides an input or output clock from which the transmit and or receive baud rate is derived in Asynchronous mode and from which data is transferred in Synchronous mode SCLK can be programmed as a GPIO signal PE2 when the SCI SCLK function is not in use This signal can be programmed as PE2 when data is being transmitted on TXD since the clock does not need to be transmitted in Asynchronous mode Because SCLK is independent of SCI data I O there is no connection between programming the PE2 signal as SCLK and data coming out the TXD signal 8 3 SCI After Reset There are several different ways to reset the SCI E Hardware RESET signal E Software RESET instruction Both hardware and software resets clear the port c
358. nual Rev 2 9 27 Triple Timer Module Table 9 4 Inverter INV Bit Operation Continued TIO Programmed as Input TIO Programmed as Output Mode INV 0 INV 1 INV 0 INV 1 6 Event is captured on the rising Event is captured on the edge of the signal from the TIO falling edge of the signal signal from the TIO signal o UN 7 Pulse generated by Pulse generated by the the timer has positive timer has negative polarity polarity 9 Pulse generated by Pulse generated by the n a the timer has positive timer has negative polarity polarity 10 Pulse generated by Pulse generated by the oan i the timer has positive timer has negative polarity polarity 9 4 5 Timer Load Register TLR The TLR is a 24 bit write only register In all modes the counter is preloaded with the TLR value after the TCSR TE bit is set and a first event occurs 9 4 6 In timer modes if the TCSR TRM bit is set the counter is reloaded each time after it reaches the value contained by the timer compare register and the new event occurs In measurement modes if TCSR TRM and TCSR TE are set the counter is reloaded with the value in the TLR on each appropriate edge of the input signal In PWM modes if TCSR TRM is set the counter is reloaded each time after it overflows and the new event occurs In watchdog modes if TCSR TRM is set the counter is reloaded each time after it reaches the value cont
359. o O 0 for future compatibility ESSIO X FFFFB3 ESSI1 X FFFFA3 Figure 7 15 ESSI Transmit Slot Mask Register B TSMB TSMA and TSMB as in Figure 7 12 and Figure 7 13 can be seen as a single 32 bit register TSM Bit nin TSM TSn is an enable disable control bit for transmission in slot number N When TSn is cleared all the data signals of the enabled transmitters are tri stated during transmit time slot number N The data still transfers from the enabled transmit data register s to the transmit shift register However the TDE and the TUE flags are not set Consequently during a disabled slot no transmitter empty interrupt is generated The DSP is interrupted only for enabled slots Data written to the transmit data register when the transmitter empty interrupt request is serviced transmits in the next enabled transmit time slot When TSn is set the transmit sequence proceeds normally Data transfers from the TX register to the shift register during slot number N and the TDE flag is set The TSM slot mask does not conflict with the TSR Even if a slot is enabled in the TSM you can chose to write to the TSR to tri state the signals of the enabled transmitters during the next transmission slot Setting the bits in the TSM affects the next frame transmission The frame being transmitted is not affected by the new TSM setting If the TSM is read it shows the current setting After a hardware RESET signal or software RESET instruction
360. od of data transfer available Core intervention is not required after the DMA channel is initialized DSP56311 User s Manual Rev 2 5 4 Freescale Semiconductor Data Transfer Methods Table 5 1 DMA Accessible Registers DMA Block Register Read Write ESSI TXO No Yes TX1 No Yes TX2 No Yes RX Yes No SCI SRX Yes No STX No Yes EFCOP FDIR No Yes FDOR Yes No HIO8 HTX No Yes HRX Yes No Timer Example 5 3 shows a DMA configuration for transferring data to the Host Transmit register of the HIOS Example 5 3 DMA Transfers belr M_D1L0 x M_IPRC disable DMA1 interrupts belr M_D1L1 x M_IPRC movep TBUFF_START x M_DSR1 DMA1 source is transmit buffer movep M_HTX x M_DDR1 DMA1 destination is HTX movep TBUFF_SIZE 1 x M_DCO1 DMA1 count is the full buffer movep INIT_DCR1 x M_DCR1 init DMA1 control register DMA requires more initialization code and consideration of DMA modes However it is the most efficient use of core resources Once these registers are programmed you must enable the DMA by triggering a DMA request off one of the peripheral control flags or enabling it in normal program flow or an interrupt service routine 5 4 4 Advantages and Disadvantages Polling is the easiest method to implement but it requires a large amount of DSP56311 core processing power The core cannot be involv
361. ode Mode 7 The external signal synchronizes with the internal clock that increments the counter This synchronization process can cause the number of clocks measured for the selected signal value to vary from the actual signal value by plus or minus one counter clock cycle DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 11 Triple Timer Module 9 3 2 1 Measurement Input Width Mode 4 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 0 1 0 0 4 Input width Measurement Input Internal In Mode 4 the timer counts the number of clocks that occur between opposite edges of an input signal After the first appropriate transition as determined by the TCSR INV bit occurs on the TIO input signal the counter is loaded with the TLR value If TCSR INV is set the timer starts on the first high to low 1 to 0 signal transition on the TIO signal If the INV bit is cleared the timer starts on the first low to high that is 0 to 1 transition on the TIO signal When the first transition opposite in polarity to the INV bit setting occurs on the TIO signal the counter stops TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is set The value of the counter which measures the width of the TIO pulse is loaded into the TCR which can be read to determine the external signal pulse width If the TCSR TRM bit is set the counter is loaded with th
362. ode is similar in that it is also for periodic transfers however it supports up to 32 words time slots per period The Network mode can be used to build time division multiplexed TDM networks In contrast the On Demand mode is for nonperiodic transfers of data This mode which offers a subset of the Freescale Serial Peripheral Interface SPI protocol can transfer data serially at high speed when the data become available Since each ESSI unit can be configured with one receiver and three transmitters the two units can be used together for surround sound applications which need two digital input channels and six digital output channels 7 1 ESSI Enhancements The DSP56000 SSI is enhanced in the following ways to make the ESSI E Network enhancements Time slot mask registers receive and transmit End of frame interrupt Drive enable signal used with transmitter 0 E Audio enhancements Three transmitters per ESSI for six channel surround sound E General enhancements Can trigger DMA interrupts receive or transmit Separate exception enable bits E Other changes One divide by 2 step is removed from the internal clock source chain The CRA PSR bit definition is reversed Gated Clock mode is not available 7 2 ESSI Data and Control Signals Three to six signals are required for ESSI operation depending on the operating mode selected The serial transmit data STD signal and serial control S
363. oes not use TIO it can be used as a GPIO signal also called TIO 0 2 9 1 1 Triple Timer Module Block Diagram Figure 9 1 shows a block diagram of the triple timer module This module includes a 24 bit Timer Prescaler Load Register TPLR a 24 bit Timer Prescaler Count Register TPCR and three timers Each timer can use the prescaler clock as its clock source DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 1 Triple Timer Module GDB 24 244 24 TPCR 24 Timer Prescaler Count Register i G Timer Prescaler Load Register et IR Timer 2 ae e CLK 2 TIOO TIO1 TIO2 Figure 9 1 Triple Timer Module Block Diagram 9 1 2 Individual Timer Block Diagram Figure 9 2 shows the structure of an individual timer block The DSP56311 treats each timer as a memory mapped peripheral with four registers occupying four 24 bit words in the X data memory space The three timers are identical in structure and function Either standard polled or interrupt programming techniques can be used to service the timers A single generic timer is discussed in this chapter Each timer includes the following 24 bit counter 24 bit read write Timer Control and Status Register TCSR 24 bit read only Timer Count Register TCR 24 bit write only Timer Load Register TLR 24 bit read write Timer Compare Register TCPR Logic for clock selection and interrupt DMA trigger generation The timer mode is controlled by the TC 3 0 bit
364. og Pulse Mode DSP56311 User s Manual Rev 2 Freescale Semiconductor Triple Timer Module 9 3 4 2 Watchdog Toggle Mode 10 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 1 0 1 0 10 Toggle Watchdog Output Internal In Mode 10 the timer toggles an external signal after a preset period The TIO signal is set to the value of the INV bit When the counter equals the value in the TCPR TCSR TCF is set and a compare interrupt is generated if the TCSR TCIE bit is also set If the TCSR TRM bit is set the counter loads with the TLR value on the next timer clock and the count resumes Therefore TRM is not useful for watchdog functions If the TCSR TRM bit is cleared the counter continues to increment on each subsequent timer clock When a counter overflow occurs the polarity of the TIO output signal is inverted The counter is reloaded whenever the TLR is written with a new value while the TCSR TE bit is set This process repeats until the timer is disabled In Mode 10 internal logic preserves the TIO value and direction for an additional 2 5 internal clock cycles after the hardware RESET signal is asserted This convention ensures that a valid reset signal is generated when the TIO signal resets the DSP56311 Mode 10 internal clock TRM 0 first event TRM 1 is not useful for watchdog function N write preload M write compare TE A tl O ee CLK
365. ogram words locations 0 3FF The lowest external program memory location in this mode is 18000 while program memory locations C000 17FFF are considered reserved and should not be accessed 3 1 3 Instruction Cache In program memory space the lowest 1024 1K program words at locations 0 3FF function as an internal instruction cache When the instruction cache is enabled that is the CE bit in the SR is set the lowest 1K program words are reserved for the instruction cache and should not be accessed for other purposes Note When using an enabled instruction cache you must assign a valid value for the vector address bus so that interrupts can be handled properly outside P 0 3FF See the memory diagrams starting with Figure 3 2 Memory Switch Off Cache On 24 Bit Mode on page 3 10 3 1 4 Program Bootstrap ROM The program memory space occupying locations FFOOO0O FFOOBF includes the internal bootstrap ROM This ROM contains the 192 word DSP56311 bootstrap program 3 2 X Data Memory Space The X data memory space consists of the following E Internal X data memory 48K by default down to 8K E Internal X I O space upper 128 locations E Optional off chip memory expansion as much as 128K in 16 bit mode or 256K in 24 bit mode using the 18 external address lines or 4 M using the external address lines and the four address attribute lines Refer to the DSP56300 Family Manual especially Section 2 Expansio
366. ols the functionality of the corresponding signal line When a PCR i bit is set the corresponding port signal is configured as an ESSI signal When a PCR i bit is cleared the corresponding port signal is configured as a GPIO signal Either a hardware RESET signal or a software RESET instruction clears all PCR bits 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCx5 PCx4 PCx3 PCx2 PCx1 PCx0 Note For Px 5 0 a O selects Pxn as the signal and a 1 selects the specified ESSI signal For ESSIO the GPIO signals are PC 5 0 and the ESSI signals are STDO SRDO SCKO and SCO 2 0 For ESSI1 the GPIO signals are PD 5 0 and the ESSI signals are STD1 SRD1 SCK1 and SC1 2 0 Reserved Read as zero Write with zero for future compatibility Figure 7 18 Port Control Registers PCRC X FFFFBF PCRD X FFFAF 7 6 2 Port Direction Registers PRRC and PRRD The read write PRRC and PRRD control the data direction of the ESSIO and ESSI1 GPIO signals when they are enabled by the associated Port Control Register PCRC or PCRD respectively When PRRC i or PRRD i is set the corresponding signal is an output GPO signal When PRRC i or PRRD i is cleared the corresponding signal is an input GPI signal Either a hardware RESET signal or a software RESET instruction clears all PRRC and PRRD bits 23 22 21 20 19 18 17 16 15 14 13
367. ols to determine whether any data previously written to the Transmit Data Registers TXH TXM TXL has successfully transferred to the DSP side If the host side Transmit Data Registers TXH TXM TXL are empty the host writes the data to these registers The transfer to the DSP side Host Receive Data Register HRX occurs only if HRX is empty that is the DSP has read it The DSP core then uses an appropriate handshaking protocol to move data from the HRX to the receiving buffer or register Without handshaking the host might overwrite data not transferred to the DSP side or the DSP might receive stale data Similarly when the host performs multiple reads from the HIO8 port Receive Data Registers RXH RXM RXL the DSP side uses an appropriate handshaking protocol to determine whether any data previously written to the Host Transmit Register HTX has successfully transferred to the host side registers If HTX is empty the DSP writes the data to this register Data transfers to the host side Receive Data Registers RXH RXM RXL occur only if they are empty that is the host has read them The host can then use any of the available handshaking protocols to determine whether more data is ready to be read The DSP56311 HI08 port offers the following handshaking protocols for data transfers with the host E Software polling E Interrupts E Core DMA access E Host requests DSP56311 User s Manual Rev 2 Freescale Semiconductor 6 5 Host Interf
368. on Design Center Sequence Manufacturer 1 Number Number Identity 0000 000110 0000010001 00000001110 1 Figure 4 11 JTAG Identification Register Configuration Revision 0 4 10 JTAG Boundary Scan Register BSR The BSR in the DSP56311 JTAG implementation contains bits for all device signals clock pins and their associated control signals All DSP56311 bidirectional pins have a corresponding register bit in the BSR for pin data and are controlled by an associated control bit in the BSR For details on the BSR consult the DSP56300 Family Manual DSP56311 User s Manual Rev 2 Freescale Semiconductor 4 33 Core Configuration DSP56311 User s Manual Rev 2 4 34 Freescale Semiconductor Programming the Peripherals 5 When peripherals are programmed in a given application a number of possible modes and options are available for use Chapters 6 through 9 describe in detail the possible modes and configurations for peripheral registers and ports This chapter presents general guidelines for initializing the peripherals These guidelines include a description of how the control registers are mapped in the DSP56311 data transfer methods that are available when the various peripherals are used and information on General Purpose Input Output GPIO configuration 5 1 Peripheral Initialization Steps Each peripheral has its own initialization process However all four peripherals share some common steps which follo
369. on Interrupt ESSIO RX Data Interrupt ESSIO Receive Last Slot Interrupt ESSIO TX Data With Exception Interrupt ESSIO Transmit Last Slot Interrupt ESSIO TX Data Interrupt ESSI1 RX Data With Exception Interrupt ESSI1 RX Data Interrupt ESSI1 Receive Last Slot Interrupt ESSI1 TX Data With Exception Interrupt ESSI1 Transmit Last Slot Interrupt ESSI1 TX Data Interrupt SCI Receive Data With Exception Interrupt SCI Receive Data SCI Transmit Data SCI Idle Line B 10 DSP56311 User s Manual Rev 2 Freescale Semiconductor Interrupt Sources and Priorities Table B 5 Interrupt Source Priorities Within an IPL Continued Priority Interrupt Source SCI Timer TimerO Overflow Interrupt Timer0 Compare Interrupt Timer1 Overflow Interrupt Timer1 Compare Interrupt Timer2 Overflow Interrupt Timer2 Compare Interrupt EFCOP Data Input Buffer Empty Lowest EFCOP Data Output Buffer Full DSP56311 User s Manual Rev 2 Freescale Semiconductor B 11 Programming Reference B 3 Programming Sheets B 12 Application Date Programmer Sheet 1 of 2 Central Processor Oven O Negative Unnormalized U Acc 47 xnor Acc 46 Extension Limit FFT Scaling S Acc 46 xor Acc 45 Interrupt Mask a Exceptions Masked None IPLO Scaling Mode IPL O 1 a Scaling Mode IPL 0 1 2 No scaling Scal
370. on the bus Otherwise the HIOS places the data on the bus 3 Strobes the data transfer DSP56311 User s Manual Rev 2 Freescale Semiconductor 6 21 Host Interface HI08 Host processors can use standard host processor instructions for example byte move and addressing modes to communicate with the HIOS registers The HI08 registers are aligned so that 8 bit host processors can use 8 16 or 24 bit load and store instructions for data transfers The HREQ HTRQ and HACK HRRQ handshake flags are provided for polled or interrupt driven data transfers with the host processor Because of the speed of the DSP56311 interrupt response most host microprocessors can load or store data at their maximum programmed I O instruction rate without testing the handshake flags for each transfer If full handshake is not needed the host processor can treat the DSP56311 as a fast device and data can be transferred between the host processor and the DSP56311 at the fastest data rate of the host processor One of the most innovative features of the host interface is the host command feature With this feature the host processor can issue vectored interrupt requests to the DSP56311 The host can select any of 128 DSP interrupt routines for execution by writing a vector address register in the HIOS This flexibility allows the host processor to execute up to 128 pre programmed functions inside the DSP56311 For example the DSP56311 host interrupts allow the
371. only if the page logic is enabled by the BPLE bit The four combinations of BPS 1 0 enable the use of many DRAM sizes 1 M bit 4 M bit 16 M bit and 64 M bit The encoding of BPS 1 0 is E 00 9 bit column width 512 words E 01 10 bit column width 1 K words M10 11 bit column width 2 K words E 11 12 bit column width 4 K words When the row address is driven all 24 bits of the external address bus are driven for example if BPS 1 0 01 when driving the row address the 14 MSBs of the internal address XAB YAB PAB or DAB are driven on address lines A 0O 13 and the address lines A 14 23 are driven with the 10 MSBs of the internal address This method enables the use of different DRAMs with the same page size 74 0 Reserved Write to zero for future compatibility 3 2 BRW 1 0 0 Bus Row Out of page Wait States Defines the number of wait states that should be inserted into each DRAM out of page access The encoding of BRW 1 0 is E 00 4 wait states for each out of page access E 01 8 wait states for each out of page access E 10 11 wait states for each out of page access E 11 15 wait states for each out of page access 1 0 BCw 1 0 0 Bus Column In Page Wait State Defines the number of wait states to insert for each DRAM in page access The encoding of BCW 1 0 is E 00 1 wait state for each in page access E 01 2 wait states for each in page access E 10 3 wait states for each in page access E 11 4
372. ontrol Direction 1 CRB SCD1 bit determines its direction Table 7 2 Mode and Signal Definitions Control Bits ESSI Signals SYN TEO TE1 TE2 RE Sco sci SC2 SCK STD SRD 0 0 X X 0 U U U U U U 0 0 Xx Xx 1 RXC FSR U U U RD 0 1 Xx Xx 0 U U FST TXC TDO U 0 1 Xx Xx 1 RXC FSR FST TXC TDO RD 1 0 0 0 0 U U U U U U 1 0 0 0 1 FO U F1 TOD U FS XC U RD 1 0 0 1 0 FO U TD2 FS XC U U 1 0 0 1 1 FO U TD2 FS XC U RD 1 0 1 0 0 TD1 F1 TOD U FS XC U U 1 0 1 0 1 TD1 F1 TOD U FS XC U RD 1 0 1 1 0 TD1 TD2 FS XC U U 1 0 1 1 1 TD1 TD2 FS XC U RD 1 1 0 0 0 FO U F1 TOD U FS XC TDO U DSP56311 User s Manual Rev 2 7 4 Freescale Semiconductor ESSI Data and Control Signals Table 7 2 Mode and Signal Definitions Continued Control Bits ESSI Signals SYN TEO TE1 TE2 RE Sco SC1 SC2 SCK STD SRD 1 1 0 0 1 FO U F1 TOD U FS XC TDO RD 1 1 0 1 0 FO U TD2 FS XC TDO U 1 1 0 1 1 FO U TD2 FS XC TDO RD 1 1 1 0 0 TD1 F1 TOD U FS XC TDO U 1 1 1 0 1 TD1 F1 TOD U FS XC TDO RD 1 1 1 1 0 TD1 TD2 FS XC TDO U 1 1 1 1 1 TD1 TD2 FS XC TDO RD TXC Transmitter clock RXC Receiver clock XC Transmitter receiver clock synchronous operation FST Transmitter frame sync FSR e Receiver frame sync FS Transmitter receiver frame sync synchronous operation TDO Transmit data signal 0 TD1 Transmit data signal 1 TD2 Transmit
373. ontrol register bits which configure all I O as GPIO input The SCI remains in the Reset state as long as all SCI signals are programmed as GPIO PC2 PC1 and PCO all are cleared the SCI becomes active only when at least one of the SCI I O signals is not programmed as GPIO E Individual reset During program execution the PC2 PC1 and PCO bits can all be cleared that is individually reset causing the SCI to stop serial activity and enter the Reset state All SCI status bits are set to their reset state However the contents of the SCR remain unaffected so the DSP program can reset the SCI separately from the other internal peripherals During individual reset internal DMA accesses to the data registers of the SCI are not valid and the data is unknown E Stop processing state reset that is the STOP instruction Executing the STOP instruction halts operation of the SCI until the DSP is restarted DSP56311 User s Manual Rev 2 8 4 Freescale Semiconductor SCI After Reset causing the SCI Status Register SSR to be reset No other SCI registers are affected by the STOP instruction Table 8 1 illustrates how each type of reset affects each register in the SCI Table 8 1 SCI Registers After Reset Reset Type Register Bit Mnemonic Bit Number HW Reset SW Reset IR Reset ST Reset SCR REIE 16 0 0 SCKP 15 0 0 STIR 14 0 0 TMIE 13 0 0 TIE 12 0
374. ord Length Control WL bits 7 14 Word Select WDS bits 8 14 Xx X data memory 1 6 3 3 X I O space 3 5 X Memory Address Bus XAB 1 11 X Memory Data Bus XDB 1 10 X Memory Expansion Bus 1 10 XTAL Disable XTLD bit 4 20 Y Y data Memory 3 5 internal 3 5 Y data memory 1 6 Y I O space 3 7 Y Memory Address Bus YAB 1 11 Y Memory Data Bus YDB 1 11 Y Memory Expansion Bus 1 10 Z Zero Z bit 4 10 DSP56311 User s Manual Rev 2 Freescale Semiconductor Index Index 15 Index DSP56311 User s Manual Rev 2 Index 16 Freescale Semiconductor
375. ority Level low M_DOL1 EQU L3 DMAO Interrupt Priority Level high M_D1L EQU C000 DMA nterrupt Priority Level Mask M_D1L0 EQU 14 DMA nterrupt Priority Level low M_D1L1 EQU 15 DMA nterrupt Priority Level high M_D2L EQU 30000 DMA2 Interrupt priority Level Mask M_D2L0 EQU 16 DMA2 Interrupt Priority Level low DSP56311 User s Manual Rev 2 Freescale Semiconductor A 13 Bootstrap Program M_D2L1 EQU 17 DMA2 Interrupt Priority Level high M_D3L EQU C0000 DMA3 Interrupt Priority Level Mask M_D3L0 EQU 18 DMA3 Interrupt Priority Level low M_D3L1 EQU 19 DMA3 Interrupt Priority Level high M_D4L EQU 300000 DMA4 Interrupt priority Level Mask M_D4L0 EQU 20 DMA4 Interrupt Priority Level low M_D4L1 EQU 21 DMA4 Interrupt Priority Level high M_D5L EQU C00000 DMA5 Interrupt priority Level Mask M_D5L0 EQU 22 DMA5 Interrupt Priority Level low M_D5L1 EQU 23 DMA5 Interrupt Priority Level high Interrupt Priority Register Peripheral IPRP M_HPL EQU 3 Host Interrupt Priority Level Mask M_HPLO EQU 0 Host Interrupt Priority Level low M_HPL1 EQU 1 Host Interrupt Priority Level high M_SOL EQU sc SS
376. ous inputs DRS 4 0 Requesting Device 00000 External IRQA pin 00001 External IRQB pin 00010 External IRQC pin 00011 External IRQD pin 00100 Transfer done from channel 0 00101 Transfer done from channel 1 00110 Transfer done from channel 2 00111 Transfer done from channel 3 01000 Transfer done from channel 4 01001 Transfer done from channel 5 01010 ESSIO receive data RDFO 1 01011 ESSIO transmit data TDEO 1 01100 ESSI1 receive data RDF1 1 01101 ESSI1 transmit data TDE1 1 01110 SCI receive data RDRF 1 01111 SCI transmit data TDRE 1 10000 Timer0 TCFO 1 10001 Timer1 TCF1 1 10010 Timer2 TCF2 1 10011 Host receive data full HRDF 1 10100 Host transmit data empty HTDE 1 10101 EFCOP input buffer empty FDIBE 1 10110 EFCOP output buffer full FDOBF 1 10111 11111 Reserved Peripheral requests 18 21 DRS 4 0 111xx can serve as fast request sources Unlike a regular peripheral request in which the peripheral can not generate a second request until the first one is served a fast peripheral has a full duplex handshake to the DMA enabling a maximum throughput of a trigger every two clock cycles This mode is functional only in the Word Transfer mode that is DTM 001 or 101 In the Fast Request mode the DMA sets an enable line to the peripheral If required the peripheral can send the DMA a one cycle triggering pulse This pulse resets the enable line If the DMA decides b
377. pace consists of the following E Internal program RAM 32 K by default up to 96 K E Instruction cache optional 1 K formed from program RAM When enabled the memory addresses used by the internal cache memory are switched to external memory The internal memory in this address range switches to cache only mode and is not available via direct addressing when cache is enabled In systems using Instruction Cache always enable the cache CE 1 before loading code into internal program memory this prevents the condition in which code loaded into program memory before cache is enabled disappears after cache is enabled E Off chip memory expansion optional as much as 64 K in 16 bit mode or 256 K in 24 bit mode using the 18 external address lines or 4 M using the external address lines and the four address attribute lines Refer to the DSP56300 Family Manual especially Chapter 9 External Memory Interface Port A for details on using the external memory interface to access external program memory E Bootstrap program ROM 192 x 24 bit Note Program memory space at locations FFOOCO FFFFFF is reserved and should not be accessed DSP56311 User s Manual Rev 2 Freescale Semiconductor 3 1 Memory Configuration 3 1 1 Internal Program Memory The default internal program memory consists of a 24 bit wide high speed SRAM occupying the lowest 32 K default in program memory space The on chip program RAM is organized in 3
378. peration of the interrupt priority registers operating modes and how they affect the processor s program and data memories E Chapter 5 Programming the Peripherals Guidelines on initializing the DSP56311 peripherals including mapping control registers specifying a method of transferring data and configuring for general purpose input output GPIO E Chapter 6 Host Interface HIO8 Signals architecture programming model reset interrupts external host programming model initialization and a quick reference to the HI08 programming model DSP56311 User s Manual Rev 2 Freescale Semiconductor 1 1 DSP56311 Overview 1 2 Chapter 7 Enhanced Synchronous Serial Interface ESSI Enhancements data and control signals programming model operating modes initialization exceptions and GPIO Chapter 8 Serial Communication Interface SCI Signals programming model operating modes reset initialization and GPIO Chapter 9 Triple Timer Module Architecture programming model and operating modes of three identical timer devices available for use as internals or event counters Chapter 10 Enhanced Filter Coprocessor EFCOP Structure and function of the EFCOP including features architecture and programming model programming topics such as data transfer to and from the EFCOP its use in different modes and examples of usage Appendix A Bootstrap Code Bootstrap code and equates for the DSP56311 Appendix B Progra
379. ptionally transmit an acknowledgment to the sender The particular message format and protocol used are determined by the user s software DSP56311 User s Manual Rev 2 8 2 Freescale Semiconductor I O Signals 8 1 3 1 Transmitting Data and Address Characters To send data the 8 bit data character must be written to the STX register Writing the data character to the STX register sets the ninth bit in the frame to zero which indicates that this frame contains data To send an 8 bit address the address data is written to the STXA register and the ninth bit in the frame is set to one indicating that this frame contains an address 8 1 3 2 Wired OR Mode Building a multidrop bus network requires connecting multiple transmitters to a common wire The Wired OR mode allows this to be done without damaging the transmitters when the transmitters are not in use A protocol is still needed to prevent two transmitters from simultaneously driving the bus The SCI multidrop word format provides an address field to support this protocol 8 1 3 3 Idle Line Wakeup A wakeup mode frees a DSP from reading messages intended for other processors The usual operational procedure is for each DSP to suspend SCI reception the DSP can continue processing until the beginning of a message Each DSP compares the address in the message header with the DSP s address If the addresses do not match the SCI again suspends reception until the next address If the
380. put Output GPIO 1 12 2 18 functions 6 3 Host Data Direction Register HDDR 6 12 6 31 Host Data Register HDR 6 12 6 31 Port B 5 6 Port C 5 7 Port D 5 7 Port E 5 7 Global Data Bus GDB 1 10 GPIO 2 2 Timers 2 2 Ground 2 4 PLL 2 4 H HACK signal 6 18 handshaking mechanisms HI08 6 5 hardware stack 1 8 HI08 1 12 2 2 ISR Transmit Data Register Empty 6 26 HI08 Interrupt Priority Level HPL bits 4 15 Host Acknowledge Enable HAEN bit 6 18 Host Acknowledge Polarity HAP bit 6 16 Host Address Line 8 Enable HA8EN 6 18 Host Address Line 9 Enable HA9EN 6 18 7 19 Host Address Strobe Polarity HASP bit 6 17 Host Base Address Register HBAR 6 12 6 15 6 31 programming sheet B 22 Host Chip Select Enable HCSEN bit 6 18 Host Chip Select Polarity HSCP bit 6 17 Host Command HC bit 6 25 Host Command Interrupt Enable HCIE bit 6 13 Host Command Pending HCP bit 6 14 Host Control Register HCR 6 12 6 29 Host Command Interrupt Enable HCIE 6 13 Host Flags 2 3 HF 6 12 Host Receive Interrupt Enable HRIE 6 13 Host Transmit Interrupt Enable HTIE 6 13 programming sheet B 23 Host Data Direction Register HDDR 6 3 6 12 6 14 programming sheet B 34 Host Data Direction Register HDRR 6 31 Host Data Register HDR 6 12 6 15 6 31 programming sheet B 34 Host Data Strobe Polarity HDSP bit 6 17 Host Dual Data Strobe HDDS bit 6 17 Host Enable HEN bit 6 17 Host Flag 0 HFO bit 6 23 Host Flag 1 HF1 bit 6 23 Host Fl
381. quates RRR IRE E E EREE E A REKEREKE ERER EREE E ERR EAEE E KEEK TRR SAN A Start equ 00100 Main program starting address FCON equ 805 EFCOP FSCR register contents DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 27 Enhanced Filter Coprocessor enable output interrupt Choose adaptive real FIR mode enable the EFCOP FIR_LEN equ 20 EFCOP FIR length DES_ADDRS equ 3200 Desired signal R n SRC_ADDRS equ 3100 Reference signal D n DST_ADDRS equ 3000 address at which to begin output signal F n SRC_COUNT equ 06003 DMAO count 7 4 word transfers DST_COUNT equ 8 number of outputs generated MU2 equ 100000 stepsize mu 0 0625 that is 2mu 0 125 FDBA_ADDRS equ 0 Input samples Start Address x 0 FCBA_ADDRS equ 0 Coeff Start Address y 0 e KKK KKK KK KKK KKK KEK KKK KKK KKK KKK KKK KKK KEK KKK KEK KKK KKK KK KKK KEK KKK KKK KKK KEK KKK KK KKK KK ARA at org p 0 jmp Start ORG p 6a jsr gt kdo nop nop KKK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KEK KKK RARA AAA at Main program e KKK KEK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KEK KKK RRA RARA a ORG p Start interrupt initialization bset 10 x M_IPRP bset 11 x M_IPRP enable EFCOP interrupts in IPRP belr 8 SR belr 9 SR enable interrupts in SR DSP56311 Reference Manual R
382. quest HTRQ output The polarity of the host request is programmable but is configured as active low HTRQ following reset The host request may be programmed as a driven or open drain output Port B 14 When the HI08 is configured as GPIO through the HPCR this signal is individually programmed through the HDDR Freescale Semiconductor DSP56311 User s Manual Rev 2 Signals Connections Table 2 10 Host Interface Continued State During Reset 1 2 Signal Description Signal Name Type HACK HACK Input Ignored Input Host Acknowledge When the HI08 is programmed to interface with a single host request host bus and the HI function is selected this signal is the Host Acknowledge HACK Schmitt trigger input The polarity of the host acknowledge is programmable but is configured as active low HACK after reset HRRQ HRRQ Output Receive Host Request When the HI08 is programmed to interface with a double host request host bus and the HI function is selected this signal is the Receive Host Request HRRQ output The polarity of the host request is programmable but is configured as active low HRRQ after reset The host request may be programmed as a driven or open drain output Port B 15 PB15 Input or When the HIO8 is configured as GPIO through the HPCR this signal is Output individually programmed through the HDDR Notes 1 Inthe Stop state the signal maintains the last state
383. r Preload Value PL 9 23 Prescaler Source PS 9 23 programming sheet B 31 Timer Reload Mode TRM bit 9 25 Timers 2 2 transcoder basestation 10 1 Transmit 0 Enable TEO bit 7 19 Transmit 1 Enable TE1 bit 7 19 Transmit 2 Enable TE2 bit 7 20 Transmit Byte Registers TXH TXM TXL 6 5 6 28 Transmit Clock Source TDM bit 8 17 Transmit Data Empty TDE bit 6 6 Transmit Data Register Empty TDE bit 7 27 Transmit Data Register Empty TDRE bit 8 16 Transmit Data Register Empty TXDE bit 6 26 Transmit Data Registers TXO TX2 7 12 7 31 Transmit Data Registers TXH TXM TXL 6 5 Transmit Data signal TXD 8 4 Transmit Enable TE bits 7 17 Transmit Exception Interrupt Enable TEIE bit 7 18 Transmit Frame Sync Flag TFS 7 27 Transmit Interrupt Enable TIE bit 7 18 Transmit Last Slot Interrupt Enable TLIE bit 7 18 Transmit Request Enable TREQ bit 6 24 Transmit Shift Registers 7 28 Transmit Slot Mask Registers TSMA and TSMB 7 12 7 31 Transmitter Empty TRNE bit 8 16 Transmitter Enable TE bit 8 12 Transmitter Ready TRDY bit 6 26 DSP56311 User s Manual Rev 2 Index 14 Freescale Semiconductor Transmitter Underrun Error Flag TUE 7 27 triple timer module 1 14 TX clock 7 10 TXD signal 8 4 TXH TXM TXL registers 6 28 U Unnormalized U bit 4 9 V Vector Base Address register VBA 1 8 vocoder 10 1 W Wait standby mode 1 6 Wakeup Mode Select WAKE bit 8 13 Wired OR Mode Select WOMS bit 8 13 W
384. r empty interrupt is disabled and the FDIBE status bit should be polled to determine whether the FDIR is empty If both FDIIE and FDIBE are set the EFCOP requests a data input buffer empty interrupt service from the DSP56300 core DMA transfer is enabled if a DMA channel is activated and triggered by this event For proper operation enable the interrupt service routine and the corresponding interrupt for core processing or enable the DMA transfer and configure the proper trigger for the selected channel Never enable both simultaneously 9 0 Reserved It is read as O and write with O for future compatibility 8 FSCO 0 Filter Shared Coefficients Mode This read write control bit is valid only when the EFCOP is operating in multichannel mode that is FMLC is set When FSCO is set the EFCOP uses the coefficients in the same memory area that is the same coefficients to implement the filter for each channel This mode is used when several channels are filtered through the same filter When the FSCO bit is cleared the EFCOP filter coefficients are stored sequentially in memory for each channel To ensure proper operation never change the FSCO bit unless the EFCOP is in individual reset state that is FEN 0 7 FPRC 0 Filter Processing FPRC State Initialization Mode This read write control bit defines the EFCOP processing initialization mode When this bit is cleared the EFCOP starts processing after a state initialization The EFCOP ma
385. ransfer is enabled by DE and initiated by every DMA request When the counter decrements to zero it is reloaded with its original value The DE bit is not automatically cleared so the DMA channel waits for a new request Note The DMA End of Block Transfer Interrupt cannot be used in this mode 110 Reserved 111 Reserved Note When DTM 2 0 001 or 101 some peripherals can generate a second DMA request while the DMA controller is still processing the first request see the description of the DRS bits DSP56311 User s Manual Rev 2 4 28 Freescale Semiconductor DMA Control Registers 5 0 DCR 5 0 Table 4 11 DMA Control Register DCR Bit Definitions Continued Bit A Reset PO Number Bit Name Value Description 18 17 DPR 1 0 O DMA Channel Priority Define the DMA channel priority relative to the other DMA channels and to the core priority if an external bus access is required For pending DMA transfers the DMA controller compares channel priority levels to determine which channel can activate the next word transfer This decision is required because all channels use common resources such as the DMA address generation logic buses and so forth DPR 1 0 Channel Priority 00 Priority level O lowest 01 Priority level 1 10 Priority level 2 11 Priority level 3 highest E if all or some channels have the same priority then channels are
386. re interrupt is generated if the TCSR TCIE bit is set If the TCSR TRM bit is set the counter is loaded with the value of the TLR when the next timer clock is received and the count resumes If the TRM bit is cleared the counter continues to increment on each timer clock This process repeats until the timer is cleared disabling the timer The TCPR TLR value sets the delay between starting the timer and toggling the TIO signal To generate output signals with a delay of X clock cycles between toggles set the TLR value to X 2 and set the TCSR TRM bit This process repeats until the timer is disabled that is TCSR TE is cleared 9 8 DSP56311 User s Manual Rev 2 Freescale Semiconductor Mode 2 internal clock TRM 1 first event N write preload Operating Modes a v M write compare i TE Clock CLK 2 or prescale CLK TLR Counter TCR xX 0 lt N X N 1 X M KN X A TCPR we TCF Compare Interrupt if TCIE 1 So TIO pin INV 0 pulse width M N clock TIO pin INV 1 periods Figure 9 7 Toggle Mode TRM 1 Mode 2 internal clock TRM 0 first event N write preload 4 M write compare ae A aN CLK 2 or prescale CLK _ TLR 7 a Counter TCR lt 0 X N N 1 MM 1 TSE TCPR gt ES TCF Compare Interrupt if TCIE 1 A TIO pin INV 0
387. read write register that controls the prescaler divide factor that is the number that the prescaler counter loads and begins counting from and the source for the prescaler input clock 23 22 21 20 19 18 17 16 15 14 13 12 PS1 PSO PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12 11 10 9 8 7 6 5 4 3 2 1 0 PL11 PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO Reserved bit Read as 0 Write to O for future compatibility Figure 9 21 Timer Prescaler Load Register TPLR DSP56311 User s Manual Rev 2 9 22 Freescale Semiconductor Triple Timer Module Programming Model Table 9 1 Timer Prescaler Load Register TPLR Bit Definitions Bit Number Bit Name Reset Value Description 23 0 Reserved Write to zero for future compatibility 22 21 PS 1 0 0 Prescaler Source Control the source of the prescaler clock The prescaler s use of a TIO signal is not affected by the TCSR settings of the timer of the corresponding TIO signal If the prescaler source clock is external the prescaler counter is incremented by signal transitions on the TIO signal The external clock is internally synchronized to the internal clock The external clock frequency must be lower than the DSP56311 internal operating frequency divided by 4 that is CLK 4 Note To ensure proper operation change the PS 1 0 bits only when the prescaler count
388. reescale Semiconductor 9 17 Triple Timer Module Period FFFFFF TLR 1 Duty cycle SF FFFFF TCPR Ensure that TCPR gt TLR for correct functionalit Mode 7 internal clock TRM 0 7 N write preload first event M write compare y TE A O E CLK 2 or prescale CLK TLR TE Counter TCR 0 N TCPR gt M if TCIE 1 TCF Compare Interrupt TCF Overflow Interrupt if TDIE 1 TIO pin INV 0 TIO pin INV 1 Pulse width gt fe Period NOTE On overflow TCR is loaded with the value of TLR Figure 9 17 Pulse Width Modulation Toggle Mode TRM 0 9 3 4 Watchdog Modes The following watchdog timer modes are provided E Watchdog Pulse E Watchdog Toggle DSP56311 User s Manual Rev 2 9 18 Freescale Semiconductor Operating Modes 9 3 4 1 Watchdog Pulse Mode 9 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Function TIO Clock 1 0 0 1 9 Pulse Watchdog Output Internal In Mode 9 the timer generates an external signal at a preset rate The signal period is equal to the period of one timer clock After the counter reaches the value in the TCPR if the TCSR TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count resumes Therefore TRM 1 is not useful for watchdog functions
389. rescaler in series with the refresh clock divider If BPR is set a divide by 64 prescaler is connected in series with the refresh clock divider If BPR is cleared the prescaler is bypassed The refresh request rate in clock cycles is the value written to BRF 7 0 bits 1 multiplied by 64 if BRP is set or by one if BRP is cleared When programming the periodic refresh rate you must consider the RAS time out period Hardware support for the RAS time out restriction does not exist Note Refresh requests are not accumulated and therefore in a fast refresh request rate not all the refresh requests are served for example the combination BRF 7 0 00 and BRP 0 generates a refresh request every clock cycle but a refresh access takes at least five clock cycles 22 15 BRF 7 0 0 Bus Refresh Rate Controls the refresh request rate The BRF 7 0 bits specify a divide rate of 1 256 BRF 7 0 00 FF A refresh request is generated each time the refresh counter reaches zero if the refresh counter is enabled BRE 1 14 BSTR 0 Bus Software Triggered Reset Generates a software triggered refresh request When BSTR is set a refresh request is generated and a refresh access is executed to all DRAM banks the exact timing of the refresh access depends on the pending external accesses and the status of the BME bit After the refresh access CAS before RAS is executed the DRAM controller hardware clears the BSTR bit The refresh cycle le
390. rite Reset 00 DRx holds value of corresponding HIO8 GPIO pin Function depends on HDDR 14 13 12 11 1 12 15 o 9 8 7 6 5 4 3 2 1 0 il a 1 0 8 i SEA Host Data Register HDR X FFFFC9 Write Reset Undefined Figure B 23 Host Data Direction and Host Data Registers HDDR HDR DSP56311 User s Manual Rev 2 B 34 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 2 of 4 GPIO Port C ESSI0 PCn 1 Port Pin configured as ESSI PCn 0 Port Pin configured as GPIO 2376 5 4 3 2 1 0 cci PCCO 0 Port C Control Register PCRC X FFFFBF Read Write Reset 000000 PDCn 1 gt Port Pin is Output PDCn 0 gt Port Pin is Input 2376 5 4 3 2 1 0 k prcs prca prc3 PRC2 PRC1 PRCO EJE Port C Direction Register PRRC X FFFFBE Read Write Reset 000000 if port pin n is GPIO input then PDn reflects the value on port pin n if port pin nis GPIO output then value written to PDn is reflected on port pin n 236 5 4 3 2 1 0 PDC5 PDC4 PDC3 PDC2 PDC1 PDCO EI Port C GPIO Data Register PDRC X FFFFBD Read Write Reset 000000 Reserved Program as 0 Figure B 24 Port C Registers PCRC PRRC PDRC DSP56311 User s Manual Rev 2 Freescale Semiconductor B 35 Programming Reference Application Date Programmer Sheet 3 of 4 GPIO Port D ESSI1 PCn 1 Port Pin configured as ESSI PCn 0 Port Pin configured as GPIO 2376
391. ritten the middle byte is transferred to the STX When STXH is written the high byte is transferred to the STX This structure makes it easy for the programmer to unpack the bytes in a 24 bit word for transmission TDXA should be written in 11 bit asynchronous multidrop mode when the data is an address and the programmer wants to set the ninth bit the address bit When STXA is written the data from the low byte on the data bus is stored in it The address data bit is cleared in 11 bit asynchronous multidrop mode when any of STXL STXM or STXH is written When either STX STXL STXM or STXH or STXA is written TDRE is cleared The transfer from either STX or STXA to the transmit shift register occurs automatically but not immediately after the last bit from the previous word is shifted out that is the transmit shift register is empty Like the receiver the transmitter is double buffered However a delay of two to four serial clock cycles occurs between when the data is transferred from either STX or STXA to the transmit shift register and when the first bit appears on the TXD signal A serial clock cycle is the time required to transmit one data bit The transmit shift register is not directly addressable and there is no dedicated flag for this register Because of this fact and the two to four cycle delay two bytes cannot be written consecutively to STX or STXA without polling because the second byte might overwrite the first byte Thu
392. rnal memory should reside in the eight Least Significant Bits LSBs of the external data bus and the packing or unpacking for external write accesses occurs in Little Endian order that is the low byte is stored in the lowest of the three memory locations and is transferred first the middle byte is stored transferred next and the high byte is stored transferred last When this bit is cleared the expansion port control logic assumes a 24 bit wide external memory Notes 1 BPAC is used only for DMA accesses and not core accesses 2 To ensure sequential external accesses the DMA address should advance three steps at a time in two dimensional mode with a row length of one and an offset size of three For details refer to Motorola application note APR23 D Using the DSP56300 Direct Memory Access Controller 3 To prevent improper operation DMA address 1 and DMA address 2 should not cross the AAR bank borders 4 Arbitration is not allowed during the packing access that is the three accesses are treated as one access with respect to arbitration and the bus mastership is not released during these accesses Reserved Write to O for future compatibility BYEN Bus Y Data Memory Enable A read write control bit that enables disables the AA pin and logic during external Y data space accesses When set BYEN enables the comparison of the external address to the BAC bits during external Y data space accesses If BYEN is cle
393. rocessor exits the WAIT state 2 7 HI08 The HIOS provides a fast 8 bit parallel data port that connects directly to the host bus The HIOS supports a variety of standard buses and can directly connect to a number of industry standard microcomputers microprocessors DSPs and DMA hardware Table 2 10 Host Interface State During np Signal Name Type Reset 1 2 Signal Description H 0 7 Input Output Ignored Input Host Data When the HI08 is programmed to interface with a non multiplexed host bus and the HI function is selected these signals are lines 0 7 of the Data bus HAD 0 7 Input Output Host Address When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected these signals are lines 0 7 of the Address Data bus PB 0 7 Input or Port B 0 7 When the HIO8 is configured as GPIO through the HPCR these Output signals are individually programmed through the HI08 Data Direction Register HDDR Freescale Semiconductor DSP56311 User s Manual Rev 2 2 9 Signals Connections Table 2 10 Host Interface Continued Signal Name Type State During Signal Description Reset 2 HAO Input Ignored Input Host Address Input 0 When the HI08 is programmed to interface with a non multiplexed host bus and the HI function is selected this signal is line O of the Host Address bus HAS HAS Input Host Address S
394. rogram then expects the following data sequence when the user program is downloaded from the HI08 1 Three bytes least significant byte first indicating the number of 24 bit program words to be loaded 2 Three bytes least significant byte first indicating the 24 bit starting address in P memory to load the user s program 3 The user program three bytes least significant byte first for each program word Once the bootstrap program finishes loading the specified number of words it jumps to the specified starting address and executes the loaded program 6 6 DSP Core Programming Model The DSP56300 core treats the HIO8 as a memory mapped peripheral occupying eight 24 bit words in X data memory space The DSP can use the HIO8 as a normal memory mapped peripheral employing either standard polled or interrupt driven programming techniques Separate transmit and receive data registers are double buffered to allow the DSP and host processor to transfer data efficiently at high speed Direct memory mapping allows the DSP56311 core to communicate with the HIOS registers using standard instructions and DSP56311 User s Manual Rev 2 Freescale Semiconductor 6 11 Host Interface H108 addressing modes In addition the MOVEP instruction allows direct data transfers between DSP56311 internal memory and the HIOS registers or vice versa There are two types of host processor registers data and control with eight registers in all The
395. rol Register Source Address Register Destination Address Register Counter Control Register Source Address Register DMA5 DMA5 DMA5 DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA Counter Control Register Source Space Mask Source Memory space 0 Source Memory space 1 Address Address Address Address Address Address Address Mode Mode Mode Mode Mode Mode Mode Mask OP WN FO DSP56311 User s Manual Rev 2 Destination Space Mask Destination Memory Space Destination Memory Space DAM5 Destination Address Register Destination Address Register DSSO I Dss1 DDS DDS1 0 1 DAMO Freescale Semiconductor Internal I O Equates M_D3D EQU 10 DMA Three Dimensional Mode M_DRS EQU SF800 DMA Request Source Mask DRSO0 DRS4 M_DCON EQU 16 DMA Continuous Mode M_DPR EQU 60000 DMA Channel Priority M_DPRO EQU 17 DMA Channel Priority Level low M_DPR1 EQU 18 DMA Channel Priority Level high M_DTM EQU 380000 DMA Transfer Mode Mask DTM2 DTMO M_DTMO EQU 19 DMA Transfer Mode 0 M_DTM1 EQU 20 DMA Transfer Mode 1 M_DTM2 EQU 21 DMA Transfer Mode 2 M_DIE EQU 22 DMA Interrupt Enable bit M_DE EQU 23 DMA Channel Enable bit DMA Status Register M_
396. rotocol or with external circuitry such as a watchdog timer The simplest way to recover synchronization is to reset the SCI 8 1 2 Asynchronous Mode Asynchronous data uses a data format with embedded word sync which allows an unsynchronized data clock to be synchronized with the word if the clock rate and number of bits per word is known Thus the clock can be generated by the receiver rather than requiring a separate clock signal The transmitter and receiver both use an internal clock that is 16 times the data rate to allow the SCI to synchronize the data The data format requires that each data byte have an additional start bit and stop bit Also two of the word formats have a parity bit The Multidrop mode used when SCIs are on a common bus has an additional data type bit The SCI can operate in full duplex or half duplex modes since the transmitter and receiver are independent 8 1 3 Multidrop Mode Multidrop is a special case of asynchronous data transfer The key difference is that a protocol allows networking transmitters and receivers on a single data transmission line Inter processor messages in a multidrop network typically begin with a destination address All receivers check for an address match at the start of each message Receivers with no address match can ignore the remainder of the message and use a wakeup mode to enable the receiver at the start of the next message Receivers with an address match can receive the message and o
397. rrupt Priority Register IPRP X FFFFFE Read Write Reset 000000 Reserved Program as 0 Figure B 4 Interrupt Priority Register Peripherals IPRP DSP56311 User s Manual Rev 2 Freescale Semiconductor B 15 Programming Reference Application PLL Predivision Factor Bits PDO PD3 PD3 PDO Predivision Factor PDF Clock Output Disable COD 0 50 Duty Cycle Clock 1 Pin Held In High State Date Programmer XTAL Disable Bit XTLD 0 Enable Xtal Oscillator 1 EXTAL Driven From An External Source Crystal Range Bit XTLR Sheet 1 of 1 0 External Xtal Freq gt 200KHz 1 External Xtal Freq lt 200KHz Division Factor Bits DFO0 DF2 DF2 DFO Division Factor DF 0 1 2 PSTP and PEN Relationship PSTP PEN Operation During STOP PLL Oscillator 7 20 21 22 27 Disabled Disabled Enabled Disabled Enabled Enabled PLL Control Register PCTL Reset 000000 Multiplication Factor Bits MF0 MF11 MF11 MF0 Multiplication Factor MF 000 001 002 Core Ne ee ae ee 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 ee ees ili i AA AEE X FFFFFD Read Write 3 Figure B 5 Phase Lock Loop Control Register PCTL B 16 DSP56311 User s Manual Rev 2 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 1 of 2 B
398. rrupt sources is set HDRQ HREQ Effect 0 0 HREQ is cleared no host processor interrupts are requested HREQ is set an interrupt is requested HTRQ and HRRQ are cleared no host processor interrupts are requested HTRQ or HRRQ are set an interrupt is requested Reserved Write to 0 for future compatibility HF3 Host Flag 3 Indicates the state of HF3 in the HCR on the DSP side HF3 can be changed only by the DSP56311 Hardware and software reset clear HF3 HF2 Host Flag 2 Indicates the state of HF2 in the HCR on the DSP side HF2 can be changed only by the DSP56311 Hardware and software reset clear HF2 TRDY Transmitter Ready Indicates that TXH TXM TXL and the HRX registers are empty If TRDY is set the data that the host processor writes to TXH TXM TXL is immediately transferred to the DSP side of the HI08 This feature has many applications For example if the host processor issues a host command that causes the DSP56311 to read the HRX the host processor can be guaranteed that the data it just transferred to the HI08 is that being received by the DSP56311 Hardware software individual and stop resets all set TRDY CAUTION TRDY TXDE and HRDF TXDE Transmit Data Register Empty Indicates that the transmit byte registers TXH TXM TXL are empty and can be written by the host processor TXDE is set when the contents of the transmit byte regist
399. rst if SHFD 0 24 bit fractional format ALC 0 32 bit mode is not shown 16 15 Transmit High Byte Transmit Middle Byte Transmit Low Byte 0 S ESSI Transmit Data Register ESSI Transmit Shift Register 0 Transmit High Byte Transmit Middle Byte Transmit Low Byte A A L _ _ _ 7 0 7 07 0 MSB 8 bit Data 0 Least Significant Zero Fill MSB 12 bit Data 16 bit Data LSB 24 bit Data b Transmit Registers NOTES Data is transmitted MSB first if SHFD 0 4 bit fractional format ALC 0 32 bit mode is not shown Figure 7 12 ESSI Data Path Programming Model SHFD 0 DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 29 Enhanced Synchronous Serial Interface ESSI 23 16 15 87 0 s s y ESSI Receive Data Receive High Byte Receive Middle Byte Receive Low Byte il Register Read Only 23 1615 07 0 Receive High Byte Receive Middle Byte Receive Low Byte ESSI Receive q 0224 q CC oe Shift Register 7 0 7 07 0 MSB 8 bit Data AH 0 0 0 Least Significant Zero Fill MSB LSB 12 bit Data LSB 16 bit Data LSB NOTES a Receive Registers Data is received MSB first it SHFD 0 24 bit fractional format ALC 0 32 bit mode is not shown ESSI Transmit Data Register Write Only 24 bit Data 2 16 15 87 3 Transmit High Byte Transmit Middle Byte Transmit Low Byte ESSI Transmit Shift Register y 24 Bit
400. s you should always poll the TDRE flag prior to writing STX or STXA to prevent overruns unless transmit interrupts are enabled Either STX or STXA is usually written as part of the interrupt service routine An interrupt is generated only if TDRE is set The transmit shift register is indirectly visible via the SSR TRNE bit In Synchronous mode data is synchronized with the transmit clock That clock can have either an internal or external source as defined by the TCM bit in the SCCR The length and format of the serial word is defined by the WDSO WDS1 and WDS2 control bits in the SCR In Asynchronous mode the start bit the eight data bits with the LSB first if SSFTD 0 and the MSB first if SSFTD 1 the address data indicator bit or parity bit and the stop bit are transmitted in that order The data to be transmitted can be written to any one of the three STX DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 21 Serial Communication Interface SCI addresses If SCKP is set and SSHTD is set SCI Synchronous mode is equivalent to the SSI operation in 8 bit data on demand mode Note When data is written to a peripheral device there is a two cycle pipeline delay until any status bits affected by this operation are updated If you read any of those status bits within the next two cycles the bit does not reflect its current status For details see the DSP56300 Family Manual 8 7 GPIO Signals and Registers Three registers
401. s cleared the counter continues to increment until it overflows DSP56311 User s Manual Rev 2 Freescale Semiconductor 9 13 Triple Timer Module Mode 5 internal clock TRM 1 first event N write preload M write compare TE clock 1 CLK 2 or prescale CLK N TLR Counter N 1 TCR period being measured TIO pin TCF Compare Interrupt if TCIE 1 NOTE If INV 1 a 1 to O edge on TIO loads the counter and a 0 to 1 edge on TIO loads TCR with count and the counter with N Figure 9 13 Period Measurement Mode TRM 1 Mode 5 internal clock TRM 0 first event N write preload M write compare TE clock 1 CLK 2 or prescale CLK TLR LN Counter 0 N N 1 M M 1 TCR M TIO pin period being measured f TCF Compare Interrupt if TCIE 1 NOTE If INV 1 a 1 to 0 edge on TIO loads the counter and a 0 to 1 edge on TIO loads TCR with count and the counter with N Figure 9 14 Period Measurement Mode TRM 0 DSP56311 User s Manual Rev 2 9 14 Counter continues counting does not stop Interrupt Service reads TCR period M N clock periods Counter continues counting does not stop Overflow may occur TOF 1 Interrupt Service reads TCR period M N clock periods Freescale Semicon
402. s cleared the receive data interrupt is disabled and the RDRF bit in the SCI status register must be polled to determine whether the receive data register is full If both RIE and RDRF are set the SCI requests an SCI receive data interrupt from the interrupt controller Receive interrupts with exception have higher priority than normal receive data interrupts Therefore if an exception occurs that is if PE FE or OR are set and REIE is set the SCI requests an SCI receive data with exception interrupt from the interrupt controller Either a hardware RESET signal or a software RESET instruction clears RIE 10 ILIE Idle Line Interrupt Enable When ILIE is set the SCI interrupt occurs when IDLE SCI status register bit 3 is set When ILIE is cleared the IDLE interrupt is disabled Either a hardware RESET signal or a software RESET instruction clears ILIE An internal flag the shift register idle interrupt SRIINT flag is the interrupt request to the interrupt controller SRIINT is not directly accessible to the user When a valid start bit is received an idle interrupt is generated if both IDLE and ILIE are set The idle interrupt acknowledge from the interrupt controller clears this interrupt request The idle interrupt is not asserted again until at least one character has been received The results are as follows e The IDLE bit shows the real status of the receive line at all times e An idle interrupt is generated once
403. s the bootstrap program option the chip uses to start up Software can also directly set the OMR MA MDJ bits A jump directly to the bootstrap program entry point FF0000 after the OMR bits are set causes the DSP56311 to execute the specified bootstrap program option except modes 0 and 8 Table 4 1 shows the DSP56311 bootstrap operation modes the corresponding settings of the external operational mode signal lines the DSP56311 User s Manual Rev 2 Freescale Semiconductor 4 1 Core Configuration OMR MA MDJ bits and the reset vector address to which the DSP56311 jumps once it leaves the Reset state Table 4 1 DSP56311 Operating Modes Mode MODD MODC MODB MODA Reset Description Vector 0 0 0 0 0 C00000 Expanded mode Bypasses the bootstrap ROM and the DSP56311 starts fetching instructions beginning at address C00000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected default Address C00000 is reflected as address 00000 on Port A signals A 0 17 1 0 0 0 1 FF0000 Reserved 2 0 0 1 0 FF0000 Reserved 3 0 0 1 1 FF0000 Reserved 4 0 1 0 0 FF0000 Reserved 5 0 1 0 1 FF0000 Reserved 6 0 1 1 0 FF0000 Reserved 7 0 1 1 1 FF0000 Reserved 8 1 0 0 0 008000 Expanded mode Bypasses the bootstrap ROM and the DSP56311 starts fetching instructions beginning at address 008000 Memory accesses are performed us
404. s which are TCSR 7 4 For a listing of the timer modes and descriptions of their operations see Section 9 3 Operating Modes on page 9 5 9 2 DSP56311 User s Manual Rev 2 Freescale Semiconductor GDB 24 TCSR Control Status Load Count Compare Register Register Register Register 24 24 24 Timer Control f Counter B Logic TIO CLK 2 Prescaler CLK Timer interrupt DMA request Figure 9 2 Timer Module Block Diagram 9 2 Operation This section discusses the following timer basics E Reset E Initialization E Exceptions 9 2 1 Timer After Reset Operation A hardware RESET signal or software reset instruction clears the Timer Control and Status Register for each timer thus configuring each timer as a GPIO A timer is active only if the timer enable bit 0 TCSR TE in the specific timer TCSR is set 9 2 2 Timer Initialization To initialize a timer do the following 1 DSP56311 User s Manual Rev 2 Freescale Semiconductor Ensure that the timer is not active either by sending a reset or clearing the TCSR TE Configure the control register TCSR to set the timer operating mode Set the interrupt enable bits as needed for the application 9 3 Triple Timer Module 3 4 Configure other registers Timer Prescaler Load Register TPLR Timer Load Register TLR and Timer Compare Register TCPR as needed for the application Enable the timer by setting the TCSR TE bit
405. s zero Write with zero for future compatibility Figure 8 10 Port Data Registers PDRE X FFFF9D DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 23 Serial Communication Interface SCI DSP56311 User s Manual Rev 2 8 24 Freescale Semiconductor Triple Timer Module 9 The timers in the DSP56311 internal triple timer module act as timed pulse generators or as pulse width modulators Each timer has a single signal that can function as a GPIO signal or as a timer signal Each timer can also function as an event counter to capture an event or to measure the width or period of a signal 9 1 Overview The timer module contains a common 21 bit prescaler and three independent and identical general purpose 24 bit timer event counters each with its own register set Each timer has the following capabilities E Uses internal or external clocking E Interrupts the DSP56311 after a specified number of events clocks or signals an external device after counting internal events E Triggers DMA transfers after a specified number of events clocks occurs E Connects to the external world through one bidirectional signal designated TIO O 2 for timers 0 2 When TIO is configured as an input the timer functions as an external event counter or measures external pulse width signal period When TIO is configured as an output the timer functions as a timer a watchdog timer or a pulse width modulator When the timer d
406. scale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 1999 2005 ey PS4 lt freescale semiconductor DSP56311 Overview Signals Connections Memory Configuration Core Configuration Programming the Peripherals Host Interface HI08 Enhanced Synchronous Serial Interface ESSI Serial Communication Interface SCI Triple Timer Module Enhanced Filter Coprocessor Bootstrap Program Programming Reference Index DSP56311 Overview Signals Connections Memory Configuration Core Configuration Programming the Peripherals Host Interface HI08 Enhanced Synchronous Serial Interface ESSI Serial Communication Interface SCI Triple Timer Module Enhanced Filter Coprocessor Bootstrap Program Programming Reference Index
407. serted HERO HREQ HTRQ 0 a Epa mrj o o mes Hro friend reso RREG ICR Enable Figure 6 3 HIO8 Host Request Structure Table 6 5 shows the operation of the HREQ pin when a single request line is used The host can test these ICR bits to determine the interrupt source Table 6 5 HREQ Pin Operation In Single Request Mode ICR 2 HDRQ 0 ICR 1 TREQ ICR 0 RREQ HREQ Pin 0 0 No interrupts 0 1 RXDF request enabled 1 0 TXDE request enabled 1 1 RXDF and TXDE request enabled Table 6 6 shows the operation of the transmit request HTRQ and receive request HRRQ lines with dual host requests enabled Table 6 6 HTRQ and HRRQ Pin Operation In Double Request Mode ICR 2 HDRQ 1 ICR 1 TREQ ICR 0 RREQ HTRQ Pin HRRQ Pin 0 0 No interrupts No interrupts 0 1 No interrupts RXDF request enabled 1 0 TXDE Request enabled No interrupts 1 1 TXDE Request enabled RXDF request enabled 6 4 5 Endian Modes The Host Little Endian bit in the host side Interface Control Register ICR 5 HLEND allows the host to access the HI08 data registers in Big Endian or Little Endian mode In Little Endian mode HLEND 1 a host transfer occurs as shown in Figure 6 4 DSP56311 User s Manual Rev 2 Freescale Semiconductor 6 9 Host Interface HI08 HTX HRX Bit Number 23 0 aa bb cc DSP side
408. sfer DPR 3 Priority 3 DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 15 Enhanced Filter Coprocessor Table 10 4 DMA Channel 1 Register Initialization Continued Register Setting Description DCON 0 Disables continuous mode DRS 16 Chooses DMA to trigger on EFCOP output buffer full D3D 0 Chooses non 3D mode DAM 2C Sets the following DMA address mode E source address no update no offset E destination address 1D post increment by 1 no offset DDS 0 Destination in X memory space DSS 1 Source in Y memory space because EFCOP is in Y memory DCO1 12 DMA Counter Register 1 Gives transfer of 9 items DSR1 address of FDOR FFFFFB1 DMA Source Address Register 1 DDR1 address of destination memory DMA Destination Address Register 1 space Setting the DCOO and DCO1 must be considered carefully These registers must be loaded with one less than the number of items to be transferred Also the following equality must hold DCO1 input length filter length Initialization e Enable DMA channel 1 output DCR1 23 DE 1 e Enable EFCOP FCSR 0 FEN 1 e Enable DMA channel 0 input DCRO 23 DE 1 Processing e Whenever the Input Data Buffer FDIR is empty that is FDIBE 1 the EFCOP triggers DMA input to transfer up to four new data words to FDIR e Compute F n The result is stored in FDOR and this triggers the DMA for an output data
409. sfer Acknowledge lf the DSP56311 is the bus master and there is no external bus activity or the DSP56311 is not the bus master the TA input is ignored The TA input is a data transfer acknowledge DTACK function that can extend an external bus cycle indefinitely Any number of wait states 1 2 infinity can be added to the wait states inserted by the bus control register BCR by keeping TA deasserted In typical operation TA is deasserted at the start of a bus cycle asserted to enable completion of the bus cycle and deasserted before the next bus cycle The current bus cycle completes one clock period after TA is deasserted The number of wait states is determined by the TA input or by the BCR whichever is longer The BCR sets the minimum number of wait states in external bus cycles To use the TA functionality the BCR must be programmed to at least one wait state A zero wait state access cannot be extended by TA deassertion At operating frequencies lt 100 MHz TA can operate synchronously with respect to CLKOUT or asynchronously depending on the setting of the TAS bit in the Operating Mode Register OMR If synchronous mode is selected the user is responsible for ensuring that TA transitions occur synchronous to CLKOUT to ensure correct operation Synchronous operation is not supported above 100 MHz and the OMR TAS bit must be set to synchronize the TA signal with the internal clock DSP56311 User s Manual
410. shared memory instead of the DMA bus so there is no DMA accessibility to shared memory Simultaneous accesses by the core and the EFCOP to the same memory bank 1024 locations of the shared memory are not permitted It is the programmer s responsibility to prevent such simultaneous accesses 3 2 3 Internal X I O Space One part of the on chip peripheral registers and some of the DSP56311 core registers occupy the top 128 locations of the X data memory FFFF80 FFFFFF This area is referred to as the internal X I O space and it can be accessed by MOVE MOVEP instructions and by bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET The contents of the internal X I O memory space are listed in Appendix A 3 3 Y Data Memory Space The Y data memory space consists of the following E Internal Y data memory 48K by default down to 16K E Internal Y I O space 16 locations FFFF80 FFFF8F E External Y I O space upper 112 locations E Optional off chip memory expansion as much as 128K in 16 bit mode or 256K in 24 bit mode using the 18 external address lines or 4 M using the external address lines and the four address attribute lines Refer to the DSP56300 Family Manual for details on using the external memory interface to access external Y data memory Note The Y memory space at locations FF0000 FFEFFF is reserved and should not be accessed 3 3 1 Internal Y Data Memor
411. side t t Y High Byte 3 gt aa bb cc lt q Low Byte read write last Host bus address 5 6 7 noel oO XX aa bb cc internal register Figure 6 5 HIO8 Read and Write Operations in Big Endian Mode DSP56311 User s Manual Rev 2 6 10 Freescale Semiconductor Boot up Using the HI08 Host Port 6 5 Boot up Using the HI08 Host Port The DSP56300 core has eight bootstrap operating modes to start up after reset As the processor exits the Reset state the value at the external mode pins MODA IRQA MODB IRQB MODC IRQC and MODD IRQD are loaded into the Chip Operating Mode bits MA MB MC and MD of the Operating Mode Register OMR These bits determine the bootstrap operating mode Modes C D E and F use the HIOS host port to bootstrap the application code to the DSP Table 6 7 describes these modes Table 6 7 HIO8 Boot Modes Mode MODD MODC MODB MODA HI08 Bootstrap Description C 1 1 0 0 ISA DSP5630x mode D 1 1 0 1 HC11 non multiplexed bus mode E 1 1 1 0 8051 multiplexed bus mode F 1 1 1 1 MC68302 bus mode The bootstrap program is factory programmed into an internal 192 word by 24 bit bootstrap ROM at locations FFOOO0 FFOOBF of P memory This program can load program RAM segment from the HIO8 host port When any of the modes in the preceding table are used the core begins executing the bootstrap program and configures the HIO8 based on the OMR mode bits The bootstrap p
412. signals are tri stated To prevent undesired spikes on the TIO signals when you switch from tri state into active state these signals should be tied to the high or low signal state by pull up or pull down resistors Table 9 4 Inverter INV Bit Operation Mode TIO Programmed as Input TIO Programmed as Output INV 0 INV 1 INV 0 INV 1 GPIO signal on the TIO signal read directly Bit written to GPIO inverted and put on TIO signal Bit written to GPIO put on TIO signal directly GPIO signal on the TIO signal inverted Counter is incremented on the rising edge of the signal from the TIO signal Counter is incremented on the falling edge of the signal from the TIO signal 2 Counter is incremented on the Counter is incremented on Initial output put on Initial output inverted rising edge of the signal from the falling edge of the signal TIO signal directly and put on TIO signal the TIO signal from the TIO signal 3 Counter is incremented on the Counter is incremented on rising edge of the signal from the falling edge of the signal the TIO signal from the TIO signal o E 4 Width of the high input pulse is Width of the low input pulse is measured measured 5 Period is measured between Period is measured between the rising edges of the input signal the falling edges of the input signal Freescale Semiconductor DSP56311 User s Ma
413. specified starting address address where loading started 108 host port The program is downloaded from the host MCU with the following rules to start loading the program r The program words is strobed in contiguous PRAM memory locations starting After the program words are read program execution starts from the same The host MCU can terminate the loading process by setting the HF1 0 and HFO 1 When the downloading is terminated the program starts executing the loaded program from the specified starting address The HI08 boot ROM program enables the following buses to download programs through the HI08 port 1 ISA Dual strobe non multiplexed bus with negative strobe pulses dual positive request 2 HC11 Single strobe non multiplexed bus with positive strobe pulse single negative request 4 i8051 Dual strobe multiplexed bus with negative strobe pulses dual negative request 5 MC68302 Single strobe non multiplexed bus with negative strobe pulse single negative request MC68302HOSTLD movep 0000000000111000 x M_HPCR DSP56311 User s A 4 Manual Rev 2 Freescale Semiconductor Bootstrap Code Configure the following conditions HAP 0 Negative host acknowledge HRP 0 Negative host request HCSP 0 Negative chip select input HD
414. status of the EFCOP module Freescale Semiconductor DSP56311 Reference Manual Rev 2 Enhanced Filter Coprocessor Table 10 1 EFCOP Registers Accessible Through the PMB Continued Register Name Description EFCOP ALU Control A 24 bit read write register used by the DSP56300 core to program the EFCOP data ALU Register FACR operating modes EFCOP Data Buffer Base A 16 bit read write register used by the DSP56300 core to indicate the EFCOP the data buffer Address FDBA base start address pointer in FDM RAM EFCOP Coefficient Buffer A 16 bit read write register by which the DSP56300 core indicates the EFCOP coefficient buffer Base Address FCBA base start address pointer in FCM RAM Decimation A 24 bit register that sets the number of channels in multichannel mode and the filter Channel Count Register decimation ratio The EFCOP address generation logic uses this information to supply the FDCH correct addressing to the FDM and FCM 10 2 2 EFCOP Memory Banks The EFCOP contains two memory banks E Filter Data Memory FDM This 24 bit wide memory bank is mapped as X memory and stores input data samples for EFCOP filter processing The FDM is written via a 4 word FIFO FDIR and its addressing is generated by the EFCOP address generation logic The input data samples are read sequentially from the FDM into the MAC The FDM is accessible for writes by the core and the DMA controller and is shared w
415. ster The timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller This feature allows DSP programmers to use the SCI baud rate generator as a simple periodic interrupt generator if the SCI is not in use if external clocks are used for the SCI or if periodic interrupts are needed at the SCI baud rate The SCI internal clock is divided by 16 to match the 1 x SCI baud rate for timer interrupt generation This timer does not require that any SCI signals be configured for SCI use to operate Either a hardware RESET signal or a software RESET instruction clears TMIE DSP56311 User s Manual Rev 2 Freescale Semiconductor 8 11 Serial Communication Interface SCI Table 8 2 SCI Control Register SCR Bit Definitions Continued Bit Number Bit Name Reset Value Description 12 TIE 0 SCI Transmit Interrupt Enable Enables disables the SCI transmit data interrupt If TIE is cleared transmit data interrupts are disabled and the transmit data register empty TDRE bit in the SCI status register must be polled to determine whether the transmit data register is empty If both TIE and TDRE are set the SCI requests an SCI transmit data interrupt from the interrupt controller Either a hardware RESET signal or a software RESET instruction clears TIE 11 RIE SCI Receive Interrupt Enable Enables disables the SCI receive data interrupt If RIE i
416. sure proper operation never change the FOM bits unless the EFCOP is in the individual reset state that is FEN 0 FUPD Filter Update This read write control status bit enables the EFCOP to start a single coefficient update session Upon completion of the session the FUPD bit is automatically cleared FUPD is automatically set when the EFCOP is in adaptive mode that is FADP 1 FADP Filter Adaptive FADP Mode This read write control bit enables adaptive mode Adaptive mode is an efficient way to implement a LMS type filter and therefore it is used when the EFCOP operates in FIR filter mode FLT 0 In adaptive mode processing of every input data sample consists of FIR processing followed by a coefficient update When FADP is set the EFCOP completes the FIR processing on the current data sample and immediately starts the coefficient update assuming that a K constant value is written to the FKIR If no value is written to the FKIR for the current data sample the EFCOP halts processing until the K constant is written to the FKIR During the coefficient update the FUPD bit is automatically set to indicate an update session After completion of the update the EFCOP starts processing the next data sample FLT Filter FLT Type This read write control bit selects one of two available filter types e FLT O FIR filter e FLT 1 IIR filter Note To ensure proper operation never change the FLT bit unless the EFC
417. t 0 24 K x 24 bit 24 K x 24 bit disabled enabled 0 1 79 Kx 24 bit 1024 x 24 bit 24 K x 24 bit 24 K x 24 bit enabled enabled 0 1 64 K x 24 bit 0 32 K x 24 bit 32 K x 24 bit disabled enabled 1 0 63 K x 24 bit 1024 x 24 bit 32 K x 24 bit 32 K x 24 bit enabled enabled 1 0 48 K x 24 bit 0 40 K x 24 bit 40 K x 24 bit disabled enabled 1 1 47 K x 24 bit 1024 x 24 bit 40 K x 24 bit 40 K x 24 bit enabled enabled 1 1 Includes 10 K x 24 bit shared memory i e memory shared by the core and the EFCOP 1 6 7 External Memory Expansion Memory can be expanded externlly as follows E Data memory expansion to two 256 K x 24 bit word memory spaces using the standard external address lines E Program memory expansion to one 256 K x 24 bit words memory space using the standard external address lines Further features of external memory include the following E External memory expansion port E Simultaneous glueless interface to static random access memory SRAM and dynamic random access memory DRAM 1 7 To provide data exchange between the blocks the DSP36311 implements the following buses Internal Buses E Peripheral I O expansion bus to peripherals Program memory expansion bus to program ROM X memory expansion bus to X memory Y memory expansion bus to Y memory Global data bus between PCU and other core structures Program data bus for carrying program data throughout the core X memory data bus for carrying X data throughout the core D
418. t 0 HREQ HTRQ HREQ 0 E HACK HRRQ HACK 1 HREQ HTRQ HTRQ HACK HRRQ HRRQ 3 HFO Host Flag 0 0 NN NN 4 HF1 Host Flag 1 0 5 HLEND Host Little Endian 0 Big Endian order 0 NN 1 Little Endian order 7 INIT Initialize 1 Reset data paths according to 0 E TREQ and RREQ Freescale Semiconductor DSP56311 User s Manual Rev 2 Host Interface HI08 Table 6 20 HIO8 Programming Model Host Side Continued Bit Reset Type Reg aw indi Name Value Function SW vi d STOP ual ISR 0 RXDF Receive Data Register Full 0 Host Receive Register is empty 0 0 0 1 Host Receive Register is full 1 TXDE Transmit Data Register 1 Host Transmit Register is 1 1 1 Empty 0 empty Host Transmit Register is full 2 TRDY Transmitter Ready 1 transmit FIFO 6 deep is 1 1 1 0 empty transmit FIFO is not empty 3 HF2 Host Flag 2 0 gt 4 HF3 Host Flag 3 0 7 HREQ Host Request 0 HREQ signal is deasserted 0 0 0 1 HREQ signal is asserted if enabled CVR 6 0 HV 6 0 Host Command Vector 32 CVR 7 HC Host Command 0 no host command pending 0 0 0 1 host command pending eee eee ee 2 A _ ________E_EEE_ EEEE gt E E E E E EAE EAEAA EE AAA A A AT RXH M 7 0 Host Receive Data Register empt L y A A A A A o A T A TXH M 7 0 Host Transmit Data empt L Register y IVR 7 0 IV 7 0 Interrupt Register 68000 family vector register 0F
419. t C and D signals are the two ESSI port signals multiplexed with the GPIO signals 4 Port E signals are the SCI port signals multiplexed with the GPIO signals Note The DSP56311 supports Clock Output CLKOUT BCLK and BCLK signals used by other DSP56300 family members at operating frequencies up to 100 MHz Therefore above 100 MHz the user must enable bus arbitration by setting the Asynchronous Bus Arbitration Enable Bit ABE in the operating mode register When set the ABE bit eliminates the required setup and hold times for BB and BG with respect to CLKOUT DSP56311 User s Manual Rev 2 Freescale Semiconductor 2 1 Signals Connections Voce VecaL Vecon Veca Veco Vecc VecH Vecs GNDp GNDpy GND EXTAL XTAL PCAP CLKOUT4 During After Reset Reset PINIT NMI A O 17 D O 23 AA O 3 RAS o 3 RD WR TA BR BG BB CAS BCLK4 BCLK Notes 1 NIR LoS N 64 18 24 DSP56311 Power Inputs PLL Core Logic 1 0 Address Bus Data Bus Bus Control HI08 ESSI SCI Timer Grounds PLL PLL General Port A External Address Bus External Data Bus External Bus Control Interrupt Mode Control Host Interface HI08 Port1 Enhanced Synchronous Serial Interface Port 0 ESSI0 Enhanced Synchronous Serial Interface Port 1 ESSI1 Serial Communications Interface SCI Port Timers JTAG OnCE Port During Reset MODA MODB MODC MODD
420. t DO loop instructions RTI return from interrupt instructions and TRAP instructions In addition the EMR bits are affected by instructions that specify SR as their destination for example DO FOREVER instructions BRKcc instructions and MOVEC During hardware reset all EMR bits are cleared The MR register bits are affected by DO instructions and instructions that directly reference the MR for example ANDI ORI or instructions such as MOVEC that specify SR as the destination During processor reset the interrupt mask bits are set and all other bits are cleared E Condition Code Register CCR SR 7 0 Defines the results of previous arithmetic computations The CCR bits are affected by Data Arithmetic Logic Unit Data ALU operations parallel move operations instructions that directly reference the CCR for example ORI and ANDI and instructions that specify SR as a destination for example MOVEC Parallel move operations affect only the S and L bits of the CCR During processor reset all CCR bits are cleared The definition of the three 8 bit registers within the SR is primarily for the purpose of compatibility with other Motorola DSPs Bit definitions in the following paragraphs identify the bits within the SR and not within the subregister Extended Mode Register EMR l Mode Register MR l Condition Code Register CCR 23 22 21 20 19 18 17
421. t Name Reset Value Description 21 19 WL 2 0 0 Word Length Control Select the length of the data words transferred via the ESSI Word lengths of 8 12 16 24 or 32 bits can be selected The ESSI data path programming model in Figure 7 12 and Figure 7 13 shows additional information on how to select different lengths for data words The ESSI data registers are 24 bits long The ESSI transmits 32 bit words in one of two ways e By duplicating the last bit 8 times when WL 2 0 100 e By duplicating the first bit 8 times when WL 2 0 101 Note When WL 2 0 100 the ESSI is designed to duplicate the last bit of the 24 bit transmission eight times to fill the 32 bit shifter Instead after the 24 bit word is shifted correctly eight zeros Os are shifted ESSI Word Length Selection WL2 WL1 WLO Number of Bits Word 0 0 8 0 1 12 1 0 16 ojyjojojo 1 1 24 1 0 0 32 valid data in the first 24 bits 1 0 1 32 valid data in the last 24 bits 1 1 0 Reserved 1 1 1 Reserved Note When the ESSI transmits data in On Demand mode that is MOD 1 in the CRB and DC 4 0 00000 in the CRA with WL 2 0 100 the transmission does not work properly To ensure correct operation do not use On Demand mode with the WL 2 0 100 32 bit word length mode 18 ALC Alignment Control The ESSI handles 24 bit fractional data Shorter data words are left align
422. t behaves as an alternative transmit data register except that rather than transmitting data the transmit data signals of all the enabled transmitters are in the high impedance state for the current time slot 7 5 9 Transmit Slot Mask Registers TSMA TSMB Both transmit slot mask registers are read write registers When the TSMA or TSMB is read to the internal data bus the register contents occupy the two low order bytes of the data bus and the high order byte is filled by 0 In Network mode the transmitter s use these registers to determine which action to take in the current transmission slot Depending on the bit settings the transmitter s either tri state the transmitter s data signal s or transmit a data word and generate a transmitter empty condition 23 22 21 20 19 18 17 16 15 14 13 12 TS15 TS14 TS13 TS12 11 10 9 8 7 6 5 4 3 2 1 0 TS11 TS10 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TSO Reserved bit read as 0 write to O O for future compatibility ESSIO X FFFFB4 ESSI1 X FFFFA4 Figure 7 14 ESSI Transmit Slot Mask Register A TSMA DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 31 Enhanced Synchronous Serial Interface ESSI 23 22 21 20 19 18 17 16 15 14 13 12 TS31 TS30 TS29 TS28 11 10 9 8 7 6 5 4 3 2 1 0 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16 Reserved bit read as 0 write t
423. t interrupt cont rti DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 23 Enhanced Filter Coprocessor nop nop nop org X SRC_ADDRS NCLUDE input asm org y FCBA_ADDRS NCLUDE coefs asm 10 3 6 2 Real FIR Filter With Decimation by M An N tap real FIR filter with decimation by M of a sequence of real numbers is represented by N 1 Fay yA D n i i 0 A DMA data transfer occurs in the following stages for both input and output The stages are the similar to the ones described in Section 10 3 6 1 1 The difference is set FDCH 11 8 FDCM M Processing 1 Whenever the Input Data Buffer FDIR is empty that is FDIBE 1 the EFCOP triggers DMA input to transfer up to four new data words to FDM via FDIR 2 Compute F n the result is stored in FDOR the EFCOP triggers DMA output for an output data transfer 3 Repeat M times Get new data word EFCOP increments data memory pointer Output Data Stream _ FO Coefficient FM Memory F 2M Bank F 3M FCM FM Figure 10 7 Real FIR Filter Data Stream With Decimation by M DSP56311 Reference Manual Rev 2 10 24 Freescale Semiconductor EFCOP Operation 10 3 6 3 Adaptive FIR Filter An adaptive FIR filter is represented in Figure 10 8 The goal of the FIR filter is to adjust the filter coefficients so that the output F n becomes as close as possible to the desired si
424. t it again then you disable the corresponding transmitter 0 1 or 2 after transmission of the current data word The transmitter remains disabled until the beginning of the next frame During that time period the DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 17 Enhanced Synchronous Serial Interface ESSI corresponding SC or STD in the case of TXO signal remains in a high impedance state The CRB bits are cleared by either a hardware RESET signal or a software RESET instruction Table 7 4 ESSI Control Register B CRB Bit Definitions Bit Number Bit Name Reset Value Description 23 REIE 0 Receive Exception Interrupt Enable When the REIE bit is set the DSP is interrupted when both RDF and ROE in the ESSI status register are set When REIE is cleared this interrupt is disabled The receive interrupt is documented in Section 7 3 3 Exceptions on page 7 7 A read of the status register followed by a read of the receive data register clears both ROE and the pending interrupt 22 TEIE 0 Transmit Exception Interrupt Enable When the TEIE bit is set the DSP is interrupted when both TDE and TUE in the ESSI status register are set When TEIE is cleared this interrupt is disabled The use of the transmit interrupt is documented in Section 7 3 3 Exceptions on page 7 7 A read of the status register followed by a write to all the data registers of the enabled transmitters clears both TUE and the pending interr
425. taking bus mastership When BG is deasserted bus mastership is typically given up at the end of the current bus cycle This may occur in the middle of an instruction that requires more than one external bus cycle for execution The default operation of this bit requires a setup and hold time as specified in DSP56311 Technical Data the data sheet An alternate mode can be invoked set the asynchronous bus arbitration enable ABE bit Bit 13 in the OMR When this bit is set BG and BB are synchronized internally This eliminates the respective setup and hold time requirements but adds a required delay between the deassertion of an initial BG input and the assertion of a subsequent BG input Input Output Ignored Input Bus Busy lIndicates that the bus is active Only after BB is deasserted can the pending bus master become the bus master and then assert the signal again The bus master can keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted Called bus parking this allows the current bus master to reuse the bus without rearbitration until another device requires the bus BB is deasserted by an active pull up method that is BB is driven high and then released and held high by an external pull up resistor The default operation of this bit requires a setup and hold time as specified in the DSP56311 Technical Data sheet An alternate mode can be invoked set the ABE bit Bit
426. tated 2 The Wait processing state does not affect the signal state DSP56311 User s Manual Rev 2 Freescale Semiconductor 2 10 SCI The SCI provides a full duplex port for serial communication to other DSPs microprocessors or peripherals such as modems SCI Table 2 13 Serial Communication Interface SCI oe Type cacti i Signal Description RXD Input Ignored input Serial Receive Data Receives byte oriented serial data and transfers it to the SCI receive shift register PEO Input or Output Port E 0 The default configuration following reset is GPIO When configured as PEO signal direction is controlled through the Port E Directions Register PRRE This signal is configured as RXD or PEO through the Port E Control Register PCRE This input is 5 V tolerant TXD Output Ignored input Serial Transmit Data Transmits data from SCI transmit data register PE1 Input or Output Port E 1 The default configuration following reset is GPIO When configured as PE1 signal direction is controlled through the SCI PRRE This signal is configured as TXD or PE1 through PCRE This input is 5 V tolerant SCLK Input Output Ignored input Serial Clock Provides the input or output clock used by the transmitter and or the receiver PE2 Input or Output Port E 2 The default configuration following reset is GPIO For PE2 signal direction is controlled through the SCI PRRE This signal is configured as SCLK or PE2 t
427. te 1 and 2 20 2 18 changed the old note 1 to note 2 Operating Mode Register layout and definition Replaced Figure 4 3 Page 4 11 Page 4 10 Operating Mode Register description Updated MSC 1 0 ATE TAS and MS Page 4 11 to Page 4 11 to descriptions in Table 4 6 4 14 4 12 Bus Control Register layout and definition Added new Figure 4 6 Page 4 21 Page 4 21 Bus Control Register description Added new Table 4 8 Page 4 21 Page 4 21 Peripheral signal designators Removed overbar from many signals in Figure 5 2 Page 5 7 Page 5 7 Peripheral signal designators Removed overbars from RXD TXD SCLK PEO PE1 Page 5 8 Page 5 8 and PE2 in Figure 5 5 In Section 8 6 4 1 changed the beginning of the fourth paragraph from In Page 8 20 Page 8 21 Synchronous mode to In Asynchronous mode Updated programming sheets e Figure B 2 Operating Mode Register OMR Page B14 Page B14 e Figure B 6 Bus Control Register BCR Page B 18 Page B 18 e Figure B 8 Address Attribute Registers AAR 3 0 Page B 20 Page B 20 e Figure B 22 Timer Load Compare and Count Registers TLR TCPR and TCR Page B 34 Page B 34 DSP56311 User s Manual Rev 2 1 4 Freescale Semiconductor Features 1 4 Features The Freescale DSP56311 a member of the DSP56300 core family of programmable DSPs supports wireless infrastructure applications with general filtering operations Like the other family members the DSP56311 uses a high performance s
428. te Registers AAR O 3 on page 4 25 13 ABE 0 Asynchronous Bus Arbitration Enable Eliminates the setup and hold time requirements for BB and BG and substitutes a required non overlap interval between the deassertion of one BG input to a DSP56300 family device and the assertion of a second BG input to a second DSP56300 family device on the same bus When the ABE bit is set the BG and BB inputs are synchronized This synchronization causes a delay between a change in BG or BB until this change is actually accepted by the receiving device 12 BRT 0 Bus Release Timing Selects between fast or slow bus release If BRT is cleared a Fast Bus Release mode is selected that is no additional cycles are added to the access and BB is not guaranteed to be the last Port A pin that is tri stated at the end of the access If BRT is set a Slow Bus Release mode is selected that is an additional cycle is added to the access and BB is the last Port A pin that is tri stated at the end of the access 11 TAS 0 TA Synchronize Select Selects the synchronization method for the input Port A pin TA Transfer Acknowledge At operating frequencies lt 100 MHz TA can operate synchronously with respect to CLKOUT or asynchronously depending on the setting of the TAS bit in the Operating Mode Register OMR If synchronous mode is selected the user is responsible for ensuring that TA transitions occur synchronous to CLKOUT to ensure correct operation
429. ter WNR O DMAO Source Address Register DSP56311 User s Manual Rev 2 A 15 Bootstrap Program M_DDRO M_DCOO M_DCRO DSR1 __DDR1 DCO1 DCR1 SSE 8 DSR2 DDR2 DCO2 DCR2 35 35 DSR3 _DDR3 _DCO3 _DCR3 BRRR DSR4 __DDR4 DCO4 DCR4 BRRR _DSR5 DDR5 __DCO5 __DCR5 35 35 Register EQU SFFFFEE SFFFFED SFFFFEC Addresses SFFFFEB SFFFFEA SFFFFE9 SFFFFE8 Addresses SFFFFE7 SFFFFE6 SFFFFE5 SFFFFE4 Addresses SFFFFE3 SFFFFE2 SFFFFE1 SFFFFEO Addresses SFFFFDF SFFFFDE SFFFFDD SFFFFDC Addresses SFFFFDB SFFFFDA SFFFFD9 Of DMA1 Of DMA4 Of DMA5 SFFFFI DMA Control Register DSS DSSO DSS1 DDS DDSO DDS1 DAM DAMO DAM1 _DAM2 DAM3 _DAM4 DAM5 E E E E E E E E z 35 A 16 A o A A o o o A o o a a a A O O 0000000000 c Q Ww DLON AUBAN NPOV Ww Mh o D8 OUD zee Source Address Register E 2 DMA2 DMAO Destination Address Register DMAO Counter DMAO Control Register Destination Address Register Counter Control Register Source Address Register DMA2 DMA2 DMA2 DMA3 DMA3 DMA3 DMA3 DMA4 DMA4 DMA4 DMA4 DMA5 Counter Control Register Source Address Register Destination Address Register Counter Cont
430. terrupts polling 0 1 RXDF request interrupt 1 0 TXDE request interrupt 1 1 RXDF and TXDE request interrupts TREQ and RREQ modes HDRQ 1 RREQ HTRQ Signal HRR Q Signal 0 0 No interrupts polling No interrupts polling No interrupts polling RXDF request interrupt TXDE request interrupt No interrupts polling TXDE request interrupt RXDF request interrupt RREQ Receive Request Enable Controls the HREQ signal for host receive data transfers RREQ enables host requests via the host request HREQ or HRRQ signal when the receive data register full RXDF status bit in the ISR is set If RREQ is cleared RXDF interrupts are disabled If RREQ and RXDF are set the host request signal HREQ or HRRQ is asserted 6 7 2 Command Vector Register CVR The host processor uses the CVR an 8 bit read write register to cause the DSP56311 to execute an interrupt The host command feature is independent of any of the data transfer mechanisms in the HIOS It causes execution of any of the 128 possible interrupt routines in the DSP core Hardware software individual and stop resets clear the CVR bits 6 24 7 6 5 4 3 2 1 0 HC HV6 HV5 HV4 HV3 HV2 HV1 HVO Figure 6 16 Command Vector Register CVR DSP56311 User s Manual Rev 2 Freescale Semiconductor Host Programmer Model Table 6 16 Com
431. tes Bits 3 2 Refresh Request Rate Bits 22 15 Bus Refresh 00 4 wait states These read write control bits define AS 13 01 8 wait states the refresh request rate The bits 7 10 11 wait states specify a divide from 1 256 1 Enable 11 15 wait states BRF 7 0 00 FF A refresh request is generated every time Bus Mastership the refresh counter reaches zero Enable Bit 12 Bus In Page if the refresh counter is enabled 0 Disable Wait States Bits 1 0 i e BREN 1 1 Enable 00 1 wait state gt 01 2 wait states ere TE 10 3 wait states 0 Disable 11 4 wait states 1 Enable Bus DRAM Page Size Bits 9 8 00 9 bit column width 512 01 10 bit column width 1 K 10 11 bit column width 2 K 11 12 bit column width 4 K y Gen ON a a 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 O as DRAM Control Register DCR X FFFFFA Read Write Reset 000000 Reserved Program as 0 Figure B 7 DRAM Control Register DCR DSP56311 User s Manual Rev 2 Freescale Semiconductor Application Programming Sheets Date Programmer Sheet 2 of 2 B 1 U it Bus Packing Enable Bit 7 2 l e J ace n O Disable internal packing unpacking logic Bus Address to Compare Bits 23 12 BAC 11 0 address to compare to the external address in order to decide whether to assert the AA pin compared to the external address reserved Bus Number of Address Bits
432. the SC 1 0 bits is taken from the value of the OF 1 0 bits The value of OF 1 0 is latched when the contents of TX transfer to the transmit shift register The value on SC 1 0 is stable from the time the first bit of the transmit data word transmits until the first bit of the next transmit data word transmits Software can directly set the OF 1 0 values allowing the DSP56311 to control data transmission by indirectly controlling the value of the SC 1 0 flags 7 5 ESSI Programming Model The ESSI is composed of the following registers Two control registers CRA CRB page 7 13 and page 7 17 One status register SSISR page 7 26 One Receive Shift Register page 7 28 One Receive Data Register RX page 7 28 Three Transmit Shift Registers page 7 28 Three Transmit Data Registers TX0 TX1 TX2 page 7 28 One special purpose Time Slot Register TSR page 7 31 Two Transmit Slot Mask Registers TSMA TSMB page 7 31 Two Receive Slot Mask Registers RSMA RSMB page 7 33 DSP56311 User s Manual Rev 2 7 12 Freescale Semiconductor ESSI Programming Model This section discusses the ESSI registers and describes their bits Section 7 6 GPIO Signals and Registers on page 7 34 covers ESSI GPIO 7 5 1 ESSI Control Register A CRA The ESSI Control Register A CRA is one of two 24 bit read write control registers that direct the operation of the ESSI CRA controls the ESSI clock generator bit and frame sync rates word
433. the debugging phase of the software development to evaluate and increase the speed of software implemented algorithms The WRP flag is a sticky bit that is cleared only by hardware reset or by an explicit MOVEC operation to the OMR 18 EOV 0 Stack Extension Overflow Flag Set when a stack overflow occurs in Stack Extended mode Extended stack overflow is recognized when a push operation is requested while SP SZ Stack Size register and the Extended mode is enabled by the SEN bit The EOV flag is a sticky bit that is cleared only by hardware reset or by an explicit MOVEC operation to the OMR The transition of the EOV flag from zero to one causes a Priority Level 3 Non maskable stack error exception 17 EUN 0 Stack Extension Underflow Flag Set when a stack underflow occurs in Extended Stack mode Extended stack underflow is recognized when a pull operation is requested SP 0 and the SEN bit enables Extended mode The EUN flag is a sticky bit that is cleared only by hardware reset or by an explicit MOVEC operation to the OMR Transition of the EUN flag from zero to one causes a Priority Level 3 Non maskable stack error exception Note While the chip is in Extended Stack mode the UF bit in the SP acts like a normal counter bit 16 XYS 0 Stack Extension XY Select Determines whether the stack extension is mapped onto X or Y memory space If the bit is clear then the stack extension is mapped onto the X memory space
434. the end of the break code the transmitter sends at least one high set bit before transmitting any data to guarantee recognition of a valid start bit Break can signal an unusual condition message and so on by forcing a frame error the frame error is caused by a missing stop bit SSFTD 0 SCI Shift Direction Determines the order in which the SCI data shift registers shift data in or out MSB first when set LSB first when cleared The parity and data type bits do not change their position in the frame and they remain adjacent to the stop bit WDS 0 Word Select Select the format of transmitted and received data Asynchronous modes are compatible with most UART type serial devices and they support standard RS 232 communication links Multidrop Asynchronous mode is compatible with the MC68681 DUART the M68HC11 SCI interface and the Intel 8051 serial interface Synchronous data mode is essentially a high speed shift register for I O expansion and stream mode channel interfaces You can synchronize data by using a gated transmit and receive clock compatible with the Intel 8051 serial interface mode 0 When odd parity is selected the transmitter counts the number of ones in the data word If the total is not an odd number the parity bit is set thus producing an odd number If the receiver counts an even number of ones an error in transmission has occurred When even parity is selected an even number must result from the calculatio
435. the serial Output Flag 0 its value is determined by the value of the serial Output Flag 0 OFO bit in the CRB If SCo is an input it functions as either serial Input Flag O or a receive shift register clock input As serial Input Flag 0 SCo controls the state of the serial Input Flag 0 IFO bit in the ESSI Status Register SSISR When SCo0 is configured as a transmit data signal it is always an output signal regardless of the SCDO bit value SCo is fully synchronized with the other transmit data signals STD and SC1 SCO can be programmed as a GPIO signal PO when the ESSI sco function is not in use Note The ESSI can operate with more than one active transmitter only in Synchronous mode 7 2 5 Serial Control Signal SC1 ESSI0 SC01 ESSI1 SCI11 To determine the function of SC1 select either Synchronous or Asynchronous mode according to Table 7 2 In Asynchronous mode as for a single codec with asynchronous transmit and receive SC1 is the receiver frame sync I O In Synchronous mode SC1 is the transmitter data out signal of transmit shift register TX2 for the transmitter 0 drive enabled signal or for serial flag I O As serial flag I O SC1 operates like SCO SCO and SClare independent flags but can be used together for multiple serial device selection they can be unencoded to select up to two CODECs or decoded externally to select up to four CODECs If SC1 is configured as a serial flag or receive frame sync signal the Serial C
436. thmetic linear modulo multiple wrap around modulo and reverse carry The AGU operates in parallel with other chip resources to minimize address generation overhead The AGU is divided into halves each with its own identical address ALU Each address ALU has four sets of register triplets and each register triplet includes an address register offset register and modifier register Each contains a 24 bit full adder called an offset adder A second full adder called a modulo adder adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register A third full adder called a reverse carry adder is also provided The offset adder and the reverse carry adder work in parallel and share common DSP56311 User s Manual Rev 2 Freescale Semiconductor 1 7 DSP56311 Overview inputs The only difference between them is that the carry propagates in opposite directions Test logic determines which of the three summed results of the full adders is output Each address ALU can update one address register from its own address register file during one instruction cycle The contents of the associated modifier register specify the type of arithmetic used in the address register update calculation The modifier value is decoded in the address ALU 1 6 3 Program Control Unit PCU The PCU fetches and decodes instructions controls hardware DO loops and processes exceptions Its seven stage pipeli
437. timer signals 5 5 1 Port B Signals and Registers Each of the 16 Port B signals not used as an HIO8 signal can be configured as a GPIO signal Three registers control the GPIO functionality of Port B host control register HCR host port GPIO data register HDR and host port GPIO direction register HDDR Chapter 6 Host Interface HIO8 discusses these registers DSP56311 Non Multiplexed Multiplexed Port B GPIO Bus Bus H O 7 HAD O 7 PB 0 7 HAO HAS HAS PB8 HA1 HA8 PB9 HA2 HA9 PB10 HCS HCS HA10 PB13 Host Intertace Single DS Double DS HI08 Port HRW HRD HRD PB11 HDS HDS HWR HWR PB12 Single HR Double HR HREQ HREQ HTRQ HTRQ PB14 HACK HACK HRRQ HRRQ PB15 Figure 5 2 Port B Signals DSP56311 User s Manual Rev 2 5 6 Freescale Semiconductor General Purpose Input Output GPIO 5 5 2 Port C Signals and Registers Each of the six Port C signals not used as an ESSIO signal can be configured as a GPIO signal Three registers control the GPIO functionality of Port C Port C control register PCRC Port C direction register PRRC and Port C data register PDRC Chapter 7 Enhanced Synchronous Serial Interface ESSI discusses these registers Port C GPIO DSP56311 sco o 2 PC 0 2 Enhanced Synchronous SCKO PC3 Serial Interface Port 0 ESSIO SRDO PC4 STDO PC5 Figure 5 3 Port C Signals 5 5 3 Port D Signals and Registers Each of the six Port D signals not used as an ESSI1 signal can be configured as a GPI
438. ting at P D00000 bits 7 0 The memory is selected by the Address Attribute AA1 and is accessed with 31 wait states The EPROM bootstrap code expects to read 3 bytes specifying the number of program words 3 bytes specifying the address to start loading the program words and then 3 bytes for each program word to be loaded The number of words the starting address and the program words are read least significant byte first followed by the mid and then by the most significant byte The program words are condensed into 24 bit words and stored in contiguous PRAM memory locations starting at the specified starting address After the program words are read program execution starts from the same address where loading started DSP56311 User s Manual Rev 2 Freescale Semiconductor A 1 Bootstrap Program If MD MC MB MA 1010 then the program RAM is loaded from the SCI interface The number of program words to be loaded and the starting address must be specified The SCI bootstrap code expects to receive 3 bytes specifying the number of program words 3 bytes specifying the address to start loading the program words and then 3 bytes for each program word to be loaded The number of words the starting address and the program words are received least significant byte first followed by the mid and then by the most significant byte After the program words are received progra
439. tion of the loaded program from the specified starting address The base address of the HI08 in multiplexed mode is 0x80 and is not modified by the bootstrap code All the address lines ar nabled and should be connected accordingly If MD MC MB MA 1111 then the program RAM is loaded from the Host Interface programmed to operate in the MC68302 IMP bus mode in single strobe pin configuration The HOST MC68302 bootstrap code expects accesses that are byte wide The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24 bit word specifying the number of program words 3 bytes forming a 24 bit word specifying the address to start loading the program words and then 3 bytes forming 24 bit words for each program word to be loaded The program words are stored in contiguous PRAM memory locations Starting at the specified starting address After the program words are read program execution starts from the same address where loading started The Host Interface bootstrap load program can be stopped by setting the Host Flag 0 HFO This starts execution of the loaded program from the specified starting address page 1327553500 0 opt mex BOOT equ D00000 this is the location in P memory on the external memory bus where the external byte wide EPROM would be located AARV equ D00409 AAR1 selects the EPROM as CE mapped as P from D00000 to
440. to internal program memory In such a case the on chip program memory occupies the lowest 80K locations 0 13FFF in the program memory space The instruction cache if enabled occupies the lowest 1K program words locations 0 3FF The lowest external program memory location in this mode is 18000 while program memory locations 14000 17FFF are considered reserved and should not be accessed MSW 1 0 10 The 16K higher locations 8000 BFFF of the internal X data memory and the 16K higher locations 8000 BFFF of the internal Y data memory are switched to internal program memory In such a case the on chip program memory occupies the lowest 64K locations 0 FFFF in the program memory space The instruction cache if enabled occupies the lowest 1K program words locations 0 3FF The lowest external program memory location in this mode is 18000 while program memory locations 10000 17FFF are considered reserved and should not be accessed DSP56311 User s Manual Rev 2 Freescale Semiconductor X Data Memory Space MSW 1 0 11 The 8K higher locations A000 BFFF of the internal X memory and the 8K higher locations A000 BFFF of the internal Y memory are switched to internal program memory In such a case the on chip program memory occupies the lowest 48K locations 0 BFFF in the program memory space The instruction cache if enabled occupies the lowest 1 K pr
441. to start loading the program words and then a 24 bit word for each program word to be loaded The program words is stored in contiguous PRAM memory locations starting at the specified starting address After the program words are read program execution starts from the same address where loading started The Host Interface bootstrap load program can be stopped by setting the Host Flag 0 HFO This starts execution of the loaded program from the specified starting address AA A NA If MD MC MB MA 1110 then the program RAM is loaded from the Host DSP56311 User s Manual Rev 2 A 2 Freescale Semiconductor Bootstrap Code Interface programmed to operate in the 8051 multiplexed bus mode in double strobe pin configuration The HOST 8051 bootstrap code expects accesses that are byte wide The HOST 8051 bootstrap code expects to read 3 bytes forming a 24 bit word specifying the number of program words 3 bytes forming a 24 bit word specifying the address to start loading the program words and then 3 bytes forming 24 bit words for each program word to be loaded The program words are stored in contiguous PRAM memory locations Starting at the specified starting address After the program words are read program execution starts from the same address where loading started The Host Interface bootstrap load program can be stopped by setting the Host Flag 0 HFO This starts execu
442. tput The source of the TIO value when it is a data output signal The TIO signal is a data output when the GPIO mode is enabled and DIR is set A value written to the DO bit is written to the TIO signal If the INV bit is set the value of the DO bit is inverted when written to the TIO signal When the INV bit is cleared the value of the DO bit is written directly to the TIO signal When GPIO mode is disabled writing to the DO bit has no effect 12 DI 0 Data Input Reflects the value of the TIO signal If the INV bit is set the value of the TIO signal is inverted before it is written to the DI bit If the INV bit is cleared the value of the TIO signal is written directly to the DI bit 11 DIR 0 Direction Determines the behavior of the TIO signal when it functions as a GPIO signal When DIR is set the TIO signal is an output when DIR is cleared the TIO signal is an input The TIO signal functions as a GPIO signal only when the TC 3 0 bits are cleared If any of the TC 3 0 bits are set then the GPIO function is disabled and the DIR bit has no effect 10 0 Reserved Write to zero for future compatibility 9 TRM 0 Timer Reload Mode Controls the counter preload operation In timer 0 3 and watchdog 9 10 modes the counter is preloaded with the TLR value after the TCSR TE bit is set and the first internal or external clock signal is received If the TRM bit is set the counter is reloaded each time after it reaches the value
443. tput or configured as a Timer Input Output through the Timer 1 Control Status Register TCSR1 This input is 5 V tolerant TIO2 Input or Output Ignored input Timer 2 Schmitt Trigger Input Output As an external event counter or in Measurement mode TIO2 is input In Watchdog Timer or Pulse Modulation mode TIO2 is output The default mode after reset is GPIO input This can be changed to output or configured as a Timer Input Output through the Timer 2 Control Status Register TCSR2 This input is 5 V tolerant Notes 1 Inthe Stop state the signal maintains the last state as follows e Ifthe last state is input the signal is an ignored input e Ifthe last state is output these lines are tri stated 2 The Wait processing state does not affect the signal state DSP56311 User s Manual Rev 2 2 18 Freescale Semiconductor JTAG and OnCE Interface 2 12 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56311 support circuit board test strategies that are based on the IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers memory or on chip peripherals Functions of the OnCE module are provided through the JTAG TAP signals For progr
444. trobe When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected this signal is the Host Address Strobe HAS Schmitt trigger input The polarity of the address strobe is programmable but is configured active low HAS following reset Port B 8 When the HI08 is configured as GPIO through the HPCR this PB8 Input or signal is individually programmed through the HDDR Output HA1 Input Ignored Input Host Address Input 1 When the HI08 is programmed to interface with a non multiplexed host bus and the HI function is selected this signal is line 1 of the Host Address bus HA8 Input Host Address 8 When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected this signal is line 8 of the Host Address bus PB9 Input or Port B 9 When the HI08 is configured as GPIO through the HPCR this Output signal is individually programmed through the HDDR HA2 Input Ignored Input Host Address Input 2 When the HI08 is programmed to interface with a non multiplexed host bus and the HI function is selected this signal is line 2 of the Host Address bus HA9 Input Host Address 9 When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected this signal is line 9 of the Host Address bus PB10 Input or Port B 10 When the HI08 is configured as GPIO through the HPCR this Output signal is individually programmed through the HDDR
445. ual Rev 2 6 6 Freescale Semiconductor Operation E Host command E Transmit data register empty E Receive data register full These interrupts are maskable via the Host Receive Interrupt Enable bit HCR 0 HRIB the Host Transmit Interrupt Enable bit HCR 1 HTIE and the Host Command Interrupt Enable bit HCR 2 HCIE respectively Receive Data Full and Transmit Data Empty interrupts move data to from the HTX and HRX data registers The DSP interrupt service routine must read or write the appropriate HIO8 data register HRX or HTX to clear the interrupt condition Enable DSP Core Interrupts Receive Data Full Transmit Data Empty Host Command Status Figure 6 2 HI08 Core Interrupt Operation Host commands allow the host to issue command requests to the DSP by selecting any of 128 DSP interrupt routines for execution For example the host may issue a command via the HIOS that sets up and enables a DMA transfer The DSP56311 processor has reserved interrupt vector addresses for application specific service routines However this flexibility is independent of the data transfer mechanisms in the HI08 and allows the host to force execution of any interrupt handler for example SSI SCI IRQx and so on To enable Host Command interrupts the HCR 2 HCIE bit is set on the DSP side The host then uses the Command Vector Register CVR to start an interrupt routine The host sets the Host Command bit CVR 7 HC to r
446. udes a filter session and a coefficient update session with minimal core intervention 10 3 3 2 3 Multichannel Mode Option Multichannel mode is only available in Real operating mode It allows several channels of data to be processed concurrently and is selected by setting the FCSR FMLC The number of channels to process is one plus the number in the FDCH FDCM bits For each time period the EFCOP expects to receive the samples for each channel sequentially This is repeated for consecutive time periods Filtering can be done with the same filter or different filters for each channel by using the FCSR FSCO bit If FCSR FSCO is set the same set of coefficients are used for all channels If FSCO is clear the coefficients for each filter are stored sequentially in memory for each channel 10 3 3 2 4 Decimation Option Decimation can be used with any four of the available FIR filter type modes It cannot be used in conjunction with Adaptive and Multichannel modes Decimation decreases downsamples the sampling rate The decimation ratio defines the number of input samples per output sample The decimation ratio is one plus the number in the FDCH FDCM bits The decimation ratio can be programmed from 1 to 16 For Real and Magnitude modes the decimation ratio number of samples must be written to the FDIR before an output sample is read from the FDOR For Complex mode two times the decimation ratio number of samples one for the real part and o
447. uest 0 HREQ HTRQ HRRA active low 0 Polarity 1 HREQ HTRQ HRRQ active high 15 HAP Host 0 HACK active low 0 Acknowledge 1 HACK active high Polarity HSR 0 HRDF Host Receive 0 no receive data to be read 0 0 0 Data Full 1 Receive Data Register is full 1 HTDE Host Transmit 1 The Transmit Data Register is 1 1 1 Data Empty 0 empty The Transmit Data Register is not empty 2 HCP Host Command 0 no host command pending 0 0 0 Pending 1 host command pending 3 HFO Host Flag 0 0 4 HF1 Host Flag 1 0 6 30 DSP56311 User s Manual Rev 2 Freescale Semiconductor Table 6 19 HIO8 Programming Model DSP Side Continued Programming Model Quick Reference Bit Reset Type Register ne Bit E HW Indivi No Bit Name Value Function SW dual STOP HBAR 7 0 BA 10 3 Host Base 80 Address Register HRX 23 DSP Receive empt 0 Data Register y HTX 23 DSP Transmit empt 0 Data Register y HDR 16 D 16 0 GPIO signal 000 0 Data 0 HDRR 16 DR 16 GPIO signal 0 Input 000 0 0 Direction 1 Output 0 Table 6 20 HI08 Programming Model Host Side Bit Reset Type Reg HW Indi Name Value Function SW vi d STOP ual ICR 0 RREQ Receive Request Enable 0 HRRQ interrupt disabled 0 NN 1 HRRQ interrupt enabled 1 TREQ Transmit Request Enable 0 HTRQ interrupt disabled 0 EE 1 HTRQ interrupt enabled 2 HDRQ Double Host Reques
448. ull VBA 6C 0 2 Reserved VBA FE 0 2 Reserved 4 4 3 Processing Interrupt Source Priorities Within an IPL If more than one interrupt request is pending when an instruction executes the interrupt source with the highest IPL is serviced first When several interrupt requests with the same IPL are pending another fixed priority structure within that IPL determines which interrupt source is serviced first Table 4 6 shows this fixed priority list of interrupt sources within an IPL from DSP56311 User s Manual Rev 2 Freescale Semiconductor 4 17 Core Configuration highest to lowest at each level The interrupt mask bits in the Status Register I 1 0 can be programmed to ignore low priority level interrupt requests Table 4 6 Interrupt Source Priorities Within an IPL Priority Interrupt Source Level 3 nonmaskable Highest Hardware RESET Stack error Illegal instruction Debug request interrupt Trap Lowest Nonmaskable interrupt Levels 0 1 2 maskable Highest external interrupt external interrupt TRQC external interrupt IRQA IRQB TRQD external interrupt DMA channel 0 interrupt DMA channel 1 interrupt DMA channel 2 interrupt DMA channel 3 interrupt DMA channel 4 interrupt DMA channel 5 interrupt Host command interrupt Host transmit data empty Host receive data full ESSIO RX data with
449. ult moves from accumulator A or B to the XDB or YDB buses during an accumulator to memory or accumulator to register move and remains set until explicitly cleared that is the S bit is a sticky bit The logical equations of this bit are dependent on the Scaling mode The scaling bit is set if the absolute value in the accumulator before scaling is gt 0 25 or lt 0 75 Limit Set if the overflow bit is set or if the data shifter limiter circuits perform a limiting operation In Arithmetic Saturation mode the L bit is also set when an arithmetic saturation occurs in the Data ALU result otherwise it is not affected The L bit is cleared only by a processor reset or by an instruction that specifically clears it that is a sticky bit this allows the L bit to be used as a latching overflow bit The L bit is affected by data movement operations that read the A or B accumulator registers Extension Cleared if all the bits of the integer portion of the 56 bit result are all ones or all zeros otherwise this bit is set The Scaling mode defines the integer portion If the E bit is cleared then the low order fraction portion contains all the significant bits the high order integer portion is sign extension In this case the accumulator extension register can be ignored If the E bit is set it indicates that the accumulator extension register is in use S1 so Scaling Mode Integer Portion No scaling Bits 55 47 Scale dow
450. ultichannel 1 00 1 0 0 1 FIR Real adaptive coeff update 1 00 1 1 0 1 multichannel FIR Full Complex single channel 0 01 0 0 0 1 FIR Complex Alternating single channel 0 10 0 0 0 1 FIR Magnitude single channel 0 11 0 0 0 1 IIR Real single channel 0 00 0 0 1 1 IIR Real multichannel 1 00 0 0 1 1 Notes 1 An x indicates that the specified value can be 1 or 0 2 Ifthe user sets the FUPD bit the EFCOP updates the coefficients and clears the FUPD bit The adaptive mode that is FADP 1 sets the FUPD bit which causes the EFCOP to update the coefficients and then automatically clear the FUPD bit Therefore the value assigned to the FUPD bit in this table refers only to its initial setting and not its dynamic state during operation 3 All bit combinations not defined by this table are reserved for future development DSP56311 Reference Manual Rev 2 10 6 Freescale Semiconductor EFCOP Operation 10 3 1 EFCOP Operation Summary The EFCOP is very easy to use To define the type of filtering to perform you need only set the following registers the settings in the FDCH and FACR are optional and then enable the EFCOP by setting FCSR FEN E FCNT E FDBA E FCBA E FCSR Polling DMA or interrupts can then be used to write data to the FDIR and read data from the FDOR As Table 10 2 shows the EFCOP operates in many different modes based on the settings of the control registers However the EFCOP per
451. umber N When RSn is cleared all the data signals of the enabled receivers are tri stated during time slot number N Data transfers from the receive data register s to the receive shift register s but the RDF and ROE flags are not set Consequently during a disabled slot no receiver full interrupt is generated The DSP is interrupted only for enabled slots When RSn is set the receive sequence proceeds normally Data is received during slot number N and the RDF flag is set When the bits in the RSMx are set the frame being transmitted is unaffected but the next frame transmission is affected If the RSMx is read it shows the current setting When the internal data bus reads RSMA or RSMB the register contents occupy the two low order bytes of the data bus and the high order byte is filled by 0 After a hardware RESET signal or a software RESET instruction the RSM register is reset to FFFFFFFF enabling all 32 time slots for data transmission DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 33 Enhanced Synchronous Serial Interface ESSI 7 6 GPIO Signals and Registers The functionality of each ESSI port is controlled by three registers port control register PCRC PCRD port direction register PRRC PRRD and port data register PDRC PDRD 7 6 1 Port Control Registers PCRC and PCRD The read write 24 bit PCRs control the functionality of the signal lines for ESSIO and ESSI1 Each of the PCR bits 5 0 contr
452. upt 21 RLIE 0 Receive Last Slot Interrupt Enable Enables disables an interrupt after the last slot of a frame ends when the ESSI is in Network mode When RLIE is set the DSP is interrupted after the last slot in a frame ends regardless of the receive mask register setting When RLIE is cleared the receive last slot interrupt is disabled The use of the receive last slot interrupt is documented in Section 7 3 3 Exceptions on page 7 7 RLIE is disabled when the ESSI is in On Demand mode DC 0 20 TLIE 0 Transmit Last Slot Interrupt Enable Enables disables an interrupt at the beginning of the last slot of a frame when the ESSI is in Network mode When TLIE is set the DSP is interrupted at the start of the last slot in a frame regardless of the transmit mask register setting When TLIE is cleared the transmit last slot interrupt is disabled The transmit last slot interrupt is documented in Section 7 3 3 Exceptions on page 7 7 TLIE is disabled when the ESSI is in On Demand mode DC 0 19 RIE 0 Receive Interrupt Enable Enables disables a DSP receive data interrupt the interrupt is generated when both the RIE and receive data register full RDF bit in the SSISR are set When RIE is cleared this interrupt is disabled The receive interrupt is documented in Section 7 3 3 Exceptions on page 7 7 When the receive data register is read it clears RDF and the pending interrupt Receive interrupts with exception have high
453. us Interface Unit NOTE All BCR bits are read write control bits Bus Request Hold Bit 23 Default Area Wait Control Bits 20 16 0 BR pin is asserted only for attempted a Ie or pending access Area 2 Wait Control Bits 12 10 1 BR pin is always asserted Area 1 Wait Control Bits 9 5 Area 0 Wait Control Bits 4 0 These read write control bits define the number of wait states inserted into each external SRAM access to the designated area The value of these bits should not be programmed as zero Bits Bit Name of Wait States Bus State Bit 21 20 16 BDFW 4 0 0 31 0 DSP is not bus master 15 13 BA3W 2 0 0 7 1 DSP is bus master 12 10 BA2W 2 0 0 7 9 5 BA1W 4 0 0 31 4 0 BAOW 4 0 0 31 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 BBS BDFW 4 0 BA1W 4 0 BAOW 4 0 ol Bus Control Register BCR X FFFFFB Read Write Reset 1FFFFF Reserved Program as 0 Figure B 6 Bus Control Register BCR DSP56311 User s Manual Rev 2 Freescale Semiconductor B 17 Programming Reference Application Date Programmer Sheet 2 of 3 Bus Interface Unit NOTE All DCR bits are read write control bits Refresh Prescaler Bit 23 Bus Software Triggered Refresh Bit 14 0 Prescaler bypassed 0 Refresh complete reset 1 Divide by 64 prescaler used 1 Software triggered refresh request Bus Row Out of Page Wait Sta
454. us Refresh Enable BREN bit 4 23 Bus Refresh Prescaler BRP bit 4 23 Bus Refresh Rate BRF bits 4 23 Bus Release Timing BRT bit 4 12 Bus Request Hold BRH bit 4 21 Bus Row Out of Page Wait States BRW bits 4 24 Bus Software Triggered Reset BSTR bit 4 23 Bus X Data Memory Enable BXEN bit 4 26 Bus Y Data Memory Enable BYEN bit 4 26 C Cache Burst Mode Enable BE bit 4 12 Cache Enable CE bit 4 5 4 6 Carry C bit 4 10 cellular base station 10 1 Central Processing Unit CPU 1 1 Chip Operating Mode MD MA bits 4 13 chip select logic 6 16 signal 6 3 clock 2 4 Clock Divider CD bits 8 17 clock generator 7 10 7 16 Clock Generator CLKGEN 1 9 Clock Out Divider COD 8 17 Clock Output Disable COD bit 4 19 Clock Polarity CKP bit 7 20 Clock Prescaler SCP 8 17 Clock Source Direction SCKD bit 7 21 CMOS 1 6 codec 7 3 7 9 7 11 COM byte 4 10 Command Vector Register CVR 6 21 6 24 Host Command HC 6 25 Host Vector HV 6 25 programming sheet B 24 Condition Code Register CCR 4 5 Carry C 4 10 Extension E 4 9 Limit L 4 9 Negative N 4 9 Overflow V 4 10 Scaling S 4 9 Unnormalized U 4 9 Zero Z 4 10 Control Register A CRA Alignment Control ALC 7 14 Frame Rate Divider Control DC 7 15 Prescale Modulus Select PM 7 15 Prescaler Range PSR 7 15 programming sheet B 26 Select SCK SSC1 7 13 Word Length Control WL 7 14 Control Register B CRB Clock Polarity CKP 7 20 Clock Source
455. ut data and F n is the output data at time n Two samples the real part then the imaginary part of the input are written to the FDIR The EFCOP processes the data Then one sample alternating between the real part and the imaginary part of the output is read from the FDOR Alternating Complex mode is selected by setting the FCSR FOM bits to 10 In Alternating Complex mode the number written to the FCNT register should be twice the number of filter DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 9 Enhanced Filter Coprocessor coefficients Also the coefficients should be stored in the FCM with the real part of the coefficient in the memory location preceding the memory location holding the imaginary part of the coefficient Alternating Complex mode can be used with the decimation option 10 3 3 1 4 Magnitude Mode Magnitude mode calculates the magnitude of an input signal based on the following equation N 1 F n Y D n iY i 0 where D n is the input data and F n is the output data at time n One sample the real input is written to the FDIR The EFCOP processes the data Then one sample the real magnitude of the input signal is read from the FDOR Magnitude mode is selected by setting both the FCSR FOM bits Magnitude mode can be used with the decimation option 10 3 3 2 FIR Filter Type Processing Options There are four processing option available for the FIR filter type E Coefficient Update E Adaptive Mode
456. v 2 5 8 Freescale Semiconductor Host Interface H108 6 The host interface HIO8 is a byte wide full duplex double buffered parallel port that can connect directly to the data bus of a host processor The HIO8 supports a variety of buses and provides glueless connection with a number of industry standard microcomputers microprocessors and DSPs The HIOS signals not used to interface to the host can be configured as GPIO signals up to a total of 16 6 1 Features The HIOS host is a slave device that operates asynchronously to the DSP core and host clocks Thus the HI08 peripheral has a host processor interface and a DSP core interface This section lists the features of the host processor and DSP core interfaces 6 1 1 DSP Core Interface Mapping Registers are directly mapped into eight internal X data memory locations Data word DSP56311 24 bit native data words are supported as are 8 bit and 16 bit words Handshaking protocols Software polled Interrupt driven Core DMA accesses Instructions Memory mapped registers allow the standard MOVE instruction to transfer data between the DSP56311 and external hosts A special MOVEP instruction for I O service capability using fast interrupts Bit addressing instructions for example BCHG BCLR BSET BTST JCLR JSCLR JSET JSSET simplify I O service routines 6 1 2 Host Processor Interface Sixteen signals support non multiplexed or multip
457. valid One Bit Length FSL1 1 FSLO 0 Serial Clock RX TX Frame SYNC NOTE Frame sync occurs for one bit time preceding the data Mixed Frame Length FSL1 0 FSLO 1 Serial Clock RX Frame Sync RXSerial Data TX Frame SYNC TX Serial Data Mixed Frame Length FSL1 1 FSLO 1 Serial Clock RX Frame SYNC RX Serial Data TX Frame SYNC ee Figure 7 6 CRB FSLO and FSL1 Bit Operation FSR 0 DSP56311 User s Manual Rev 2 Freescale Semiconductor 7 23 Enhanced Synchronous Serial Interface ESSI Asynchronous SYN 0 Transmitter Frame SYNC External Transmit Clock External Transmit Frame Internal Frame SYNC ESSI Bit Internal Clock Clock SCO External Receive Clock Frame SYNC Receiver NOTE Transmitter and receiver may have different clocks and frame syncs SYNCHRONOUS SYN 1 Transmitter External Frame SYNC Internal Frame SYNC F sco CK External Clock o ESSI Bit Internal Clock Clock Receiver NOTE Transmitter and receiver may have the same clock frame syncs Figure 7 7 CRB SYN Bit Operation DSP56311 User s Manual Rev 2 7 24 Freescale Semiconductor ESSI Programming Model peuejsues eq Aew piom e pue j0 S ew lene nooo s dn1134U1 31ON yes sBe 4 pue sanbay WING 10 1dnu1a u 1enteday Y pue isanbay VING 10 s dn113 U JeyWWSUeL y ONAS ewe
458. ve Data HRDF 1 HTIE Host Transmit Interrupt Enable Generates a host transmit data interrupt request if the host transmit data empty HTDE bit in the HSR is set The HTDE bit is set when data is transferred from the HTX to the RXH RXM or RXL registers If HTIE is cleared HTDE interrupts are disabled The bit value is indeterminate after an individual reset HRIE Host Receive Interrupt Enable Generates a host receive data interrupt request if the host receive data full HRDF bit in the host status register HSR Bit 0 is set The HRDF bit is set when data is transferred to the HRX from the TXH TXM or TXL registers If HRIE is cleared HRDF interrupts are disabled The bit value is indeterminate after an individual reset 6 6 2 Host Status Register HSR The HSR is a 16 bit read only status register by which the DSP reads the HIOS status and flags The host processor cannot access it directly The initialization values for the HSR bits are discussed in Section 6 6 9 DSP Side Registers After Reset on page 6 20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HF1 HFO HCP HTDE HRDF Reserved bit read as 0 write to O for future compatibility Figure 6 7 Host Status Register HSR X FFFFC3 Table 6 9 Host Status Register HSR Bit Definitions Bit Number Bit Name Reset Value Description 15 5 0 Reserved Write to 0 for
459. ver the RX register becomes full 7 5 6 ESSI Transmit Shift Registers The three 24 bit transmit shift registers contain the data being transmitted as in Figure 7 12 and Figure 7 13 Data is shifted out to the serial transmit data signals by the selected whether internal or external bit clock when the associated frame sync I O is asserted The word length control bits in CRA determine the number of bits that must be shifted out before the shift registers are considered empty and can be written again Depending on the setting of the CRA the number of bits to be shifted out can be 8 12 16 24 or 32 Transmitted data is aligned according to the value of the ALC bit When ALC is cleared the MSB is Bit 23 and the least significant byte is unused When ALC is set the MSB is Bit 15 and the most significant byte is DSP56311 User s Manual Rev 2 7 28 Freescale Semiconductor ESSI Programming Model unused Unused bits are read as 0 Data shifts out of these registers MSB first if the SHFD bit is cleared and LSB first if SHFD is set 23 16 15 87 0 ESSI Receive Data Receive High Byte Receive Middle Byte Receive Low Byte Register 0 7 0 7 07 23 16 15 Seria Receive Shift Register Receive PRAT Byte Receive Middle ee is des Receive Low APT WL1 WLO 8 bit Data AH 0 0 0 Least Significant Zero Fill MSB N LSB 12 bit Data LSB 16 bit Data LSB 24 bit Data a Receive Registers NOTES g Data is received MSB fi
460. w 1 Determine the Register values to be programmed using the following steps a Find the peripheral register descriptions in the manual b Choose the appropriate modes to configure for a given application c Determine the bit settings for programming those modes 2 Make sure the peripheral is in individual reset state or disabled Note Peripheral registers should not be modified while the peripheral is active 1 Configure the registers by writing the predetermined values from step 1 into the appropriate register locations 2 Enable the peripheral Once the peripheral is enabled it operates according the programmed modes determined in step 1 For detailed initialization procedures unique to each peripheral device consult the initialization section in the specific peripheral device chapter 5 2 Mapping the Control Registers The I O peripherals are controlled through registers mapped to the top 128 words of X data memory FFFF80 FFFFFF Referred to as the internal I O space the control registers are accessed by move MOVE MOVEP instructions and bit oriented instructions BCHG BCLR BSET BTST BRCLR BRSET BSCLR BSSET JCLR JSET JSCLR and JSSET The DSP56311 User s Manual Rev 2 Freescale Semiconductor 5 1 Programming the Peripherals contents of the internal X I O memory space are listed in Appendix B Programming Reference Table B 2 X Data Memory FFFFFF Internal I O Peripherals Control Registers
461. w jumps to the interrupt start address defined in Table B 4 in Appendix B Programming Reference It executes code starting at the interrupt address If it is a short interrupt that is the service routine is two opcodes long the code automatically returns to the original program flow after executing two opcodes with no impact to the pipeline Otherwise if a longer service routine is required the programmer can place a jump to subroutine JSR instruction at the interrupt service address In this case the program executes that service routine and continues until a return from interrupt RTI instruction executes The execution flow then resumes from the position the program counter was in before the interrupt was triggered DSP56311 User s Manual Rev 2 Freescale Semiconductor 5 3 Programming the Peripherals Configuring interrupts requires two steps 1 Setting up the interrupt routine a The interrupt handler is located at the interrupt starting address b The interrupt routines can be short only two opcodes long or long more than two opcodes and requiring a JSR instruction 2 Enabling the interrupts Set the corresponding bits in the applicable peripheral control register Enable peripheral interrupts in the Interrupt Priority Register IPRP Enable global interrupts in the Mode Register MR portion of the Status Register SR Events that change bits in the peripheral control registers can then trigger the interrupt Depe
462. when the EFCOP is in FIR IIR filtering mode since the core can operate independently of the EFCOP while DMA transfers data to the FDIR and from the FDOR Since the EFCOP input buffer FDIR is four words deep the DMA can input in blocks of up to four words A combination of DMA transfer for input and an interrupt request for processing the output is recommended for adaptive FIR mode This combination gives the following benefits E Input data transfers to the FDIR can occur independently of the core E There is minimal intervention of the core while the weight update multiplier is updated If the initialization mode is enabled that is if the FCSR FPRC bit is cleared the core can initialize the coefficient bank while the DMA controller concurrently transfers initial data values to the data bank The EFCOP state machine starts computation as soon as filter_count data samples are input If no initialization mode is used the FCSR FPRC bit is set the EFCOP starts computation as soon as the first data sample is available in the input buffer The filter coefficient bank must therefore be initialized before an input data transfer starts The DMA input channel DSP56311 Reference Manual Rev 2 Freescale Semiconductor 10 13 Enhanced Filter Coprocessor can continue transferring data whenever the input FIFO becomes empty while the EFCOP state machine takes data words from the FIFO whenever required 10 3 6 EFCOP Operation Examples The follo
463. wing sections provide examples of how to use the EFCOP in Real FIR Filter and Adaptive FIR filter mode Section 10 3 6 4 Verification for Filter Examples on page 10 32 lists the programming inputs and outputs for the examples in the following sections 10 3 6 1 Real FIR Filter In this example an N tap FIR filter is represented as follows N 1 F n Y Ai D n i i 0 The filter is implemented with three different data transfers using the EFCOP in data initialization mode 1 DMA input DMA output 2 DMA input polling output 3 DMA input interrupt output This transfer combination is only one of many possible combinations 10 3 6 1 1 DMA Input DMA Output A 20 tap FIR filter using a 28 input sample signal is implemented in the following stages Set up 1 Set the filter count register FCNT to the length of the filter coefficients 1 that is N 1 Set the Data and Coefficient Base Address pointers FDBA FCBA Set the operation mode FCSR 5 4 FOM 00 Set Initialization mode FCSR 7 FPRC 0 1 For information on DMA transfers refer to the Freescale application note entitled Using the DSP56300 Direct Memory Access Controller APR23 D DSP56311 Reference Manual Rev 2 10 14 Freescale Semiconductor 5 Set DMA registers EFCOP Operation DMA input A two dimensional 2D DMA transfer fills up the FDM bank via channel 0 The DMA input control registers are initialized as shown in Table 10 3 T
464. xternal program and data memory accesses Otherwise D O 23 are tri stated These lines have weak keepers to maintain the last state even if all drivers are tri stated Freescale Semiconductor DSP56311 User s Manual Rev 2 2 5 Signals Connections 2 5 3 External Bus Control Table 2 8 External Bus Control Signals Signal Name State During Reset Stop or Wait Signal Description Type AA O 3 Output Tri stated Address Attribute When defined as AA these signals are used as chip selects or additional address lines The default use defines a priority scheme under which only one AA signal is asserted at a time Setting the AA priority disable APD bit Bit 14 of the OMR disables the priority mechanism and the lines are used together as four external lines decoded externally into 16 chip select signals RAS O 3 Output Row Address Strobe When defined as RAS these signals are used as RAS for DRAM interface These signals are tri statable outputs with programmable polarity Note DRAM access is not supported above 100 MHz RD Output Tri stated Read Enable When the DSP is the bus master RD is asserted to read external memory on the data bus D 0 23 Otherwise RD is tri stated WR Output Tri stated Write Enable When the DSP is the bus master WR is asserted to write external memory on the data bus D O 23 Otherwise the signals are tri stated TA Input Ignored Input Tran
465. y The default on chip Y data RAM is a 24 bit wide internal static memory occupying the lowest 48K locations 0 BFFF in Y memory space The on chip Y data RAM is organized in 48 banks 1024 locations each Available Y data memory space is reduced and reallocated to program memory by using the memory switch mode described in the following paragraphs DSP56311 User s Manual Rev 2 Freescale Semiconductor 3 5 Memory Configuration 3 3 2 Memory Switch Modes Y Data Memory Memory switch mode reallocates of portions of X and Y data RAM as program RAM Bit 7 in the OMR is the MS bit that controls this function as follows E When the MS bit is cleared the Y data memory consists of the default 48K x 24 bit Note 3 6 memory space described in the previous section In this default mode the lowest external Y data memory location is 6000 When MS mode bit in the OMR is set a portion of the higher locations of the internal Y memory are switched to internal program memory The memory switch configuration MSW 1 0 bits in the OMR select one of the following options MSW 1 0 00 The 32K higher locations 4000 BFFF of the internal Y memory are switched to internal program memory and therefore the highest internal Y memory location is 3FFF The Y memory space at the switched locations 4000 BFFF becomes reserved and should not be accessed The lowest external Y memory location is C000 MSW 1 0 01
466. y CP 4 6 DO FOREVER FV Flag 4 7 Rounding Mode RM 4 6 Sixteen Bit Arithmetic Mode SA 4 6 Extension E bit 4 9 external address bus 2 5 external bus control 2 5 2 6 2 7 External Bus Disable EBD bit 4 13 external data bus 2 5 external memory expansion port 2 5 external Y I O space 3 7 F filter cross correlation 10 1 FIR 10 1 IIR 10 1 Filter Adaptive Mode FADP bit 10 39 Filter ALU Control Register FACR 10 40 Filter Input Scale FISL 10 40 Filter Rounding Mode FRM 10 40 Filter Saturation Mode FSM 10 40 Filter Scaling FSCL 10 41 Filter Channels FCHL bits 10 42 Filter Coefficient Base Address FCBA register 10 41 Filter Coefficient Memory FCM 10 2 Filter Coefficient Memory FCM bank 10 2 Filter Contention FCONT bit 10 37 Filter Control Status Register FCSR 10 37 Filter Adaptive Mode FADP 10 39 Filter Contention FCONT 10 37 Filter Data Input Buffer Empty FDIBE 10 37 Filter Data Input Interrupt Enable FDITE 10 38 Filter Data Output Buffer Full FDOBF 10 37 Filter Data Output Interrupt Enable FDOIE 10 38 Filter Enable FEN 10 39 Filter Multichannel Mode FMLC 10 38 Filter Operation Mode FOM 10 39 Filter Processing State Initialization Mode FPRC 10 38 Filter Saturation FSAT 10 37 Filter Shared Coefficients Mode FSCO 10 38 Filter Type FLT 10 39 Filter Update FUPD 10 39 Filter Count Register FCNT 10 36 Filter Data Base Address FDBA register 10 41 Filter Data Input Buffer Empty
467. y location is 3FFF The X memory space at the switched locations 4000 BFFF becomes reserved and should not be accessed The lowest external X memory location is C000 MSW 1 0 01 The 24K higher locations 6000 BFFF of the internal X memory are switched to internal program memory and therefore the highest internal X memory location is 5FFF The X memory space at the switched locations 6000 BFFF becomes reserved and should not be accessed The lowest external X memory location is C000 MSW 1 0 10 The 16K higher locations 8000 BFFF of the internal X memory are switched to internal program memory and therefore the highest internal X memory location is 7FFF The X memory space at the switched locations 8000 BFFF becomes reserved and should not be accessed The lowest external X memory location is C000 MSW 1 0 11 The 8K higher locations A000 BFFF of the internal X memory are switched to internal program memory and therefore the highest internal X memory location is 9FFF The X memory space at the switched locations A000 BFFF becomes reserved and should not be accessed The lowest external X memory location is C000 DSP56311 User s Manual Rev 2 Freescale Semiconductor Y Data Memory Space Note The 10K lowest locations 0 27FF of the internal X memory are shared memory which is accessible to both the core and the EFCOP The EFCOP connects to the
468. y the priority algorithm that this trigger will be served in the next cycle the enable line is set again even before the corresponding register in the peripheral is accessed 10 D3D 0 Three Dimensional Mode Indicates whether a DMA channel is currently using three dimensional D3D 1 or non three dimensional D3D 0 addressing modes The addressing modes are specified by the DAM bits Freescale Semiconductor DSP56311 User s Manual Rev 2 4 31 Core Configuration Table 4 11 DMA Control Register DCR Bit Definitions Continued Bit Name Reset Value Description 9 4 DAM 5 0 0 DMA Address Mode Defines the address generation mode for the DMA transfer These bits are encoded in two different ways according to the D3D bit 3 2 DDS 1 0 0 DMA Destination Space Specify the memory space referenced as a destination by the DMA Note In Cache mode a DMA to Program memory space has some limitations as described in the DSP56300 Family Manual in Chapter Chapter 8 Instruction Cache and Chapter Chapter 11 Operating Modes and Memory Spaces DDS1 DDSO DMA Destination Memory Space 0 0 X Memory Space 0 1 Y Memory Space 1 0 P Memory Space 1 1 Reserved 1 0 DSS 1 0 0 DMA Source Space Specify the memory space referenced as a source by the DMA Note In Cache mode a DMA to Program memory space has some limitations as described in the DSP56300 Family Manual in
469. z dc Optimized power management circuitry instruction dependent peripheral dependent and mode dependent 1 6 DSP56300 Core Functional Blocks The functional blocks of the DSP56300 core are E Data arithmetic logic unit ALU Address generation unit Program control unit PLL and clock oscillator JTAG TAP and OnCE module E Memory In addition the DSP56311 provides a set of internal peripherals discussed in Section 1 9 Peripherals on page 1 12 1 6 1 Data ALU The data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core These are the components of the data ALU E Fully pipelined 24 x 24 bit parallel multiplier accumulator E Bit field unit comprising a 56 bit parallel barrel shifter fast shift and normalization bit stream generation and parsing DSP56311 User s Manual Rev 2 1 6 Freescale Semiconductor DSP56300 Core Functional Blocks Conditional ALU instructions Software controllable 24 bit 48 bit or 56 bit arithmetic support Four 24 bit or 48 bit input general purpose registers X1 X0 Y1 and YO Six data ALU registers A2 Al AO B2 B1 and BO that are concatenated into two general purpose 56 bit accumulators A and B accumulator shifters E Two data bus shifter limiter circuits 1 6 1 1 Data ALU Registers The data ALU registers are read or written over the X data bus and the Y data bus as 16 or 32 bit operands The source operands for the data ALU can
470. z selected condition occurs Timer Control Bits 4 7 TC 3 0 TIO Clock Mode GPIO nternal Timer Direction Bit 11 Output nternal Timer Pulse adia Output nternal Timer Toggle 0 TIO pin Is input Input External Event Counter 1 TIO pin is output Input nternal Input Width Input lernal Input Period n Input nternal Capture n E Output lernal Pulse Width Modulation Data Input Bit 12 ie Racanied 0 Zero read on TIO pin Output nternal Watchdog Pulse 1 One read on TIO pin Output nternal Watchdog Toggle Reserved Reserved 2 Reserved Data Output Bit 13 Reserved 0 Zero written to TIO pin Reserved 1 One written to TIO pin Timer Enable Bit 0 Prescaled Clock Enable Bit 15 0 Timer Disabled 0 Clock source is CLK 2 or TIO 1 Timer Enabled 1 Clock source is prescaler output Timer Overflow Interrupt Enable Bit 1 0 Overflow Interrupts Disabled Timer Compare Flag Bit 21 1 Overflow Interrupts Enabled 0 1 has been written to TCSR TCF oF Tier combats interruptservicad Timer Compare Interrupt Enable Bit 2 1 Timer Compare has occurred 0 Compare Interrupts Disabled 1 Compare Interrupts Enabled Timer Overflow Flag Bit 20 0 1 has been written to TCSR TOF or timer Overflow interrupt serviced 1 Counter wraparound has occurred y 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 ESE i iE ESE i ed bi Db a T a Timer Control Status Regist

DSP56311 Users Manual - Freescale Semiconductor

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