DE2 Development and Education Board User Manual
Contents
1. GPIO 112 PIN H14 GPIO Connection 1 2 GPIO 113 PIN G15 GPIO Connection 1 3 GPIO 114 PIN E14 GPIO Connection 1 4 GPIO 115 PIN E15 GPIO Connection 1 5 GPIO 1 6 PIN F15 GPIO Connection 1 6 GPIO 4 7 PIN 616 GPIO Connection 1 7 GPIO 1 8 PIN F12 GPIO Connection 1 8 GPIO 1 9 PIN F13 GPIO Connection 1 9 GPIO 1 10 PIN C14 GPIO Connection 1 10 GPIO 1 11 PIN D14 GPIO Connection 1 11 GPIO 1 12 PIN D15 GPIO Connection 1 12 GPIO 1 13 PIN D16 GPIO Connection 1 13 GPIO 1 14 PIN C17 GPIO Connection 1 14 GPIO 1 15 PIN C18 GPIO Connection 1 15 GPIO 1 16 PIN C19 GPIO Connection 1 16 GPIO 1 17 PIN C20 GPIO Connection 1 17 GPIO 1 18 PIN D19 GPIO Connection 1 18 GPIO 1 19 PIN D20 GPIO Connection 1 19 GPIO 1 20 PIN E20 GPIO Connection 1 20 GPIO 1 21 PIN F20 GPIO Connection 1 21 GPIO 1 22 PIN E19 GPIO Connection 1 22 GPIO 1 23 PIN E18 GPIO Connection 1 23 GPIO 1 24 PIN 620 GPIO Connection 1 24 GPIO 1 25 PIN 618 GPIO Connection 1 25 GPIO 1 26 PIN 617 GPIO Connection 1 26 GPIO 1 27 PIN H17 GPIO Connection 1 27 GPIO 1 28 PIN J15 GPIO Connection 1 28 GPIO 1 29 PIN H18 GPIO Connection 1 29 GPIO 1 30 PIN N22 GPIO Connection 1 30 GPIO_1 31 PIN_N21 GPIO Connection 1 31 GPIO 1 32 PIN P15 GPIO Connection 1 32 GPIO 1 33 PIN N15 GPIO Connection 1 33 GPIO_1 34 PIN P17 GPIO Connection 1 34 GPIO 1 35 PIN P18 GPIO Connecti2. EN QC SCLK 330 83 53 x a 7 RB 29 gt c4 T 1 maias 21 22 _ E A VCC33 DCVDD AGND AGND cs 47K GND 5 App HI C o4 DBVDD ROUT HZ 1000P 3 LINEOUT Lour 12 BCLK AGND AGND 2 E T q WMB731 999 QFN28 045 AUD XCK m TC 1000 3 AUD BCLK nooo 1210 AUD DACDAT A VcC33 AGND AUD DACLRCK AUD ADCOAT AUD ADCLRCK TC2 1000 3 1210 R10 8 za BO2 BO3 B04 4TK 47K ow ow R2 0 GND AGND GND AGND AGND Figure 4 15 Audio CODEC schematic 38 AU S RYA DEI User Manual AUD ADCLRCK PIN A6 Audio CODEC ADC LR Clock AUD ADCDAT PIN B6 Audio CODEC ADC Data AUD DACLRCK PIN A5 Audio CODEC DAC LR Clock AUD DACDAT PIN B5 Audio CODEC DAC Data AUD XCK PIN B4 Audio CODEC Chip Clock AUD BCLK PIN A4 Audio CODEC Bit Stream Clock I2C_SCLK PIN_A3 I2C Data I2C SDAT PIN B3 I2C Clock Table 4 9 Audio CODEC pin assignments 4 8 RS 232 Serial Port The DEI board uses the MAX232 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver refer to the datasheet which is available on the manufacturer s web site and from the Datasheet folder on the DEI System CD ROM Figure 4 16 shows the related schematics an
3. 4 FLASH A20 9 pot 40 FLASH D5 FLASH A21 10 ag FLASH WE 11 920 pene FLASH D4 FLASH_RESET 12 fe at F_VCC33 X poH a5 FLASH D3 15 34 x FLASH A19 6 ney FLASH_D2 FLASH A18 17 A E FLASH AB 18 n 24 FLASH D1 FLASH A7 19 A7 20 FLASH A6 20 48 29 FLASH_DO FLASH A5 21 35 Q0 8 FLASH_OE A4 OE FLASH_A4 GND FLASH_A3 iB CND 26 FLASH CE FLASH A2 25 FLASH A1 AD S29ALO32DTFN TSOP 48 FLASH OE Figure 4 25 Flash schematic DRAM ADDR O PIN W4 SDRAM Address 0 ADDR 1 PIN W5 SDRAM Address 1 DRAM ADDR 2 PIN Y3 SDRAM Address 2 DRAM_ADDRI3 PIN_Y4 SDRAM Address 3 DRAM_ADDRI4 PIN_R6 SDRAM Address 4 DRAM ADDRIS PIN R5 SDRAM Address 5 DRAM ADDRI6 PIN P6 SDRAM Address 6 DRAM_ADDRI7 PIN_P5 SDRAM Address 7 DRAM_ADDRI8 PIN_P3 SDRAM Address 8 DRAM_ADDRI9 PIN_N4 SDRAM Address 9 DRAM ADDR 10 PIN W3 SDRAM Address 10 DRAM ADDR 11 PIN N6 SDRAM Address 11 DRAM PIN U1 SDRAM Data 0 DRAM DQ 1 PIN U2 SDRAM Data 1 DRAM DQ 2 PIN V1 SDRAM Data 2 DRAM DQ 3 PIN V2 SDRAM Data 3 DRAM 4 PIN W1 SDRAM Data 4 DRAM DQ 5 PIN W2 SDRAM Data 5 DRAM DQ 6 PIN Y1 SDRAM Data 6 42 R24 4 7K DEI User Manual DRAM DQ 7 PIN Y2 SDRAM Data 7 DRAM DQ 8 PIN N1 SDRAM Data 8 DRAM DQ 9
4. N DTE SYAN DE1 User Manual Chapter 4 Using the DE1 Board This chapter gives instructions for using the board and describes each of its I O devices 4 1 Configuring the Cyclone H FPGA The procedure for downloading a circuit from a host computer to the DE1 board is described in the tutorial Quartus II Introduction This tutorial is found in the DEI tutorials folder on the DEI System CD ROM and it is also available on the Altera DEI web pages The user is encouraged to read the tutorial first and to treat the information below as a short reference The DEI board contains a serial EEPROM chip that stores configuration data for the Cyclone II FPGA This configuration data is automatically loaded from the EEPROM chip into the FPGA each time power is applied to the board Using the Quartus II software it is possible to reprogram the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial EEPROM chip Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone II FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration is lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Al
5. PIN 2 SDRAM Data 9 DRAM DQ 10 PIN P1 SDRAM Data 10 DRAM DQ 11 PIN P2 SDRAM Data 11 DRAM DQ 12 PIN R1 SDRAM Data 12 DRAM DQ 13 PIN R2 SDRAM Data 13 DRAM DQ 14 PIN T1 SDRAM Data 14 DRAM DQ 15 PIN T2 SDRAM Data 15 DRAM BA 0 PIN U3 SDRAM Bank Address 0 DRAM BA 1 PIN V4 SDRAM Bank Address 1 DRAM LDQM PIN R7 SDRAM Low byte Data Mask DRAM_UDQM PIN_M5 SDRAM High byte Data Mask DRAM_RAS_N PIN_T5 SDRAM Row Address Strobe DRAM_CAS_N PIN_T3 SDRAM Column Address Strobe DRAM_CKE PIN N3 SDRAM Clock Enable DRAM CLK PIN U4 SDRAM Clock DRAM WE N PIN R8 SDRAM Write Enable DRAM_CS_N PIN_T6 SDRAM Chip Select Table 4 16 SDRAM pin assignments SRAM ADDR O PIN AA3 SRAM Address 0 SRAM ADDR 1 PIN AB3 SRAM Address 1 SRAM ADDR PIN_AA4 SRAM Address 2 SRAM ADDR 3 PIN_AB4 SRAM Address 3 SRAM ADDRIA PIN AA5 SRAM Address 4 SRAM ADDR 5 PIN AB10 SRAM Address 5 SRAM ADDR 6 PIN AA11 SRAM Address 6 SRAM ADDR 7 PIN AB11 SRAM Address 7 SRAM ADDR S PIN V11 SRAM Address 8 SRAM ADDR 9 PIN W11 SRAM Address 9 SRAM ADDR 10 PIN R11 SRAM Address 10 SRAM_ADDR 11 PIN_T11 SRAM Address 1 1 SRAM ADDR 12 PIN Y10 SRAM Address 12 SRAM ADDR 13 PIN U10 SRAM Address 13 43 N DTE SYAN DE1 User Manual SRAM ADDR 14 PIN R10 SRAM Address 14 SRAM ADDR 15 PIN T7 SRAM Address 15 SRAM ADDR 16 P
6. PIN AA13 FLASH Address 13 FL ADDR 14 PIN AB13 FLASH Address 14 FL ADDR 15 PIN AA12 FLASH Address 15 FL ADDR 16 PIN AB12 FLASH Address 16 FL ADDR 17 PIN AA20 FLASH Address 17 FL ADDR 18 PIN U14 FLASH Address 18 FL ADDR 19 PIN V14 FLASH Address 19 FL ADDR 20 PIN U13 FLASH Address 20 FL ADDR 21 PIN R13 FLASH Address 21 FL 0 PIN AB16 FLASH Data 0 FL DQ 1 PIN AA16 FLASH Data 1 FL DQ 2 PIN AB17 FLASH Data 2 FL DQ 3 PIN AA17 FLASH Data 3 FL DQ 4 PIN AB18 FLASH Data 4 FL DQ 5 PIN AA18 FLASH Data 5 FL DQ 6 PIN AB19 FLASH Data 6 FL 7 PIN AA19 FLASH Data 7 FL OE N PIN AA15 FLASH Output Enable FL RST PIN W14 FLASH Reset FL WE N PIN Y14 FLASH Write Enable Table 4 18 Flash pin assignments 45
7. Pin assignments for the toggle switches KEY 0 PIN_R22 Pushbutton 0 KEY 1 PIN R21 Pushbutton 1 2 PIN T22 Pushbutton 2 KEY 3 PIN T21 Pushbutton 3 Table 4 2 Pin assignments for the pushbutton switches LEDR 0 PIN R20 LED Red 0 LEDR 1 PIN R19 LED Red 1 LEDR 2 PIN U19 LED Red 2 LEDR 3 PIN 19 LED Red 3 LEDR 4 PIN T18 LED Red 4 LEDR 5 PIN V19 LED Red 5 LEDR 6 PIN Y18 LED Red 6 LEDR 7 PIN U18 LED Red 7 LEDR 8 PIN R18 LED Red 8 LEDR 9 PIN R17 LED Red 9 LEDGI0 PIN_U22 LED Green 0 LEDG 1 PIN U21 LED Green 1 PIN_V22 LED Green 2 LEDG 3 PIN V21 LED Green 3 LEDGIA PIN W22 LED 4 LEDG 5 PIN W21 LED Green 5 LEDG 6 PIN_Y22 LED Green 6 LEDG 7 PIN Y21 LED Green 7 Table 4 3 Pin assignments for the LEDs 29 NO amp YA DEI User Manual 4 3 Using the 7 segment Displays The DEI Board has four 7 segment displays These displays are arranged into a group of four with the intent of displaying numbers of various sizes As indicated in the schematic in Figure 4 6 the seven segments are connected to pins on the Cyclone II FPGA Applying a low logic level to a segment causes it to light up and applying a high logic level turns it off Each segment in a display is identified by an index from 0 to 6 with the positions given in Figure 4 7 Note that the dot in each display is unc
8. 3 GPIO O 4 PIN A15 GPIO Connection O 4 GPIO O 5 PIN B15 GPIO Connection O 5 O 6 PIN A16 GPIO Connection 0 6 GPIO O 7 PIN B16 GPIO Connection O 7 O 8 PIN A17 GPIO Connection O 8 O 9 PIN B17 GPIO Connection O 9 10 PIN_A18 GPIO Connection 0 10 GPIO_0 11 PIN B18 GPIO Connection 0 11 GPIO 0 12 PIN A19 GPIO Connection 0 12 GPIO_0 13 PIN_B19 GPIO Connection 0 13 GPIO_0 14 PIN_A20 GPIO Connection 0 14 6 15 PIN B20 GPIO Connection 0 15 GPIO_0 16 PIN_C21 GPIO Connection 0 16 GPIO_0 17 PIN_C22 GPIO Connection 0 17 GPIO_0 18 PIN_D21 GPIO Connection 0 18 6 19 PIN D22 GPIO Connection 0 19 GPIO O 20 PIN E21 GPIO Connection 0 20 GPIO O 21 PIN E22 GPIO Connection 0 21 GPIO 0 22 PIN F21 GPIO Connection 0 22 GPIO 0 23 PIN F22 GPIO Connection 0 23 GPIO O 24 PIN G21 GPIO Connection 0 24 O 25 PIN G22 GPIO Connection 0 25 GPIO O 26 PIN J21 GPIO Connection 0 26 GPIO_0 27 PIN_J22 GPIO Connection 0 27 GPIO O 28 PIN K21 GPIO Connection 0 28 GPIO O 29 PIN K22 GPIO Connection 0 29 GPIO O 30 PIN J19 GPIO Connection 0 30 GPIO 0 31 PIN J20 GPIO Connection 0 31 GPIO 0 32 PIN J18 GPIO Connection 0 32 0 33 PIN K20 GPIO Connection 0 33 GPIO O 34 PIN L19 GPIO Connection 0 34 GPIO_0 35 PIN_L18 GPIO Connection 0 35 GPIO_1 0 PIN_H12 GPIO Connection 1 0 GPIO 1 1 PIN H13 GPIO Connection 1 1 34 DEI User Manual
9. IN Y6 SRAM Address 16 SRAM ADDR 17 PIN Y5 SRAM Address 17 SRAM DQ O PIN 6 SRAM Data 0 SRAM DQ 1 PIN AB6 SRAM Data 1 SRAM DQ 2 PIN AA7 SRAM Data 2 SRAM DQ 3 PIN AB7 SRAM Data 3 SRAM DQ 4 PIN AA8 SRAM Data 4 SRAM DQ 5 PIN AB8 SRAM Data 5 SRAM DQ 6 PIN AA9 SRAM Data 6 SRAM DQ 7 PIN SRAM Data 7 SRAM DQ 8 PIN Y9 SRAM Data 8 SRAM DQ 9 PIN W9 SRAM Data 9 SRAM DQ 10 PIN V9 SRAM Data 10 SRAM DQ 11 PIN U9 SRAM Data 11 SRAM DQ 12 PIN R9 SRAM Data 12 SRAM DQ 13 PIN W8 SRAM Data 13 SRAM DQ 14 PIN V8 SRAM Data 14 SRAM DQ 15 PIN 8 SRAM Data 15 SRAM WE N PIN AA10 SRAM Write Enable SRAM OE N PIN T8 SRAM Output Enable SRAM UB N PIN W7 SRAM High byte Data Mask SRAM LB N PIN Y7 SRAM Low byte Data Mask SRAM CE N PIN AB5 SRAM Chip Enable Table 4 17 SRAM pin assignments FL ADDR O PIN AB20 FLASH Address 0 FL ADDR 1 PIN AA14 FLASH Address 1 FL ADDR 2 PIN Y16 FLASH Address 2 FL ADDR 3 PIN R15 FLASH Address 3 FL_ADDR 4 PIN_T15 FLASH Address 4 FL ADDR 5 PIN U15 FLASH Address 5 FL ADDR 6 PIN V15 FLASH Address 6 FL ADDR 7 PIN W15 FLASH Address 7 44 DEI User Manual FL ADDR 8 PIN R14 FLASH Address 8 FL ADDR 9 PIN Y13 FLASH Address 9 FL ADDR 10 PIN R12 FLASH Address 10 FL ADDR 11 PIN 12 FLASH Address 11 FL ADDR 12 PIN AB14 FLASH Address 12 FL ADDR 13
10. ND 5 GND 5 GND 1 VCC33 VCC33 1 VCC33 VCC33 1 VCC33 1 VCC33 1 VCC33 VCC33 2 SWO 2 Swi 2 SW2 SW3 2 SW4 2 SW5 gt Sw6 2 SW 3 GND 3 GND 3 GND 3 GND 3 GND 3 GND 3 GND 3 GND 4 GND 4 GND 4 GND 4 GND 4 GND 4 GND C4 GND 4 GND DPDT SW SW DPDT Sw DPDT Sw DPDT Sw DPDT Sw DPDT SW DPDT Sw swe swo GND GND 1 VCC33 1 VCC33 2 SWB 2 SW9 3 GND 3 GND 4 GND 4 GND PDT SW PDT SW Figure 4 4 Schematic diagram of the pushbutton and toggle switches 27 DEI User Manual RN15 p if LEDROLEDR y 7 LEDR1LEDR LEDR2LEDR ZA LEDR3LEDR y LEDR4LEDR A LEDR5LEDR RN16 LEDR6LEDR ZA LEDR7 LEDR GND ZA LEDR8 LEDR gt 330 LEDR9LEDR RN17 LED8 LED9 3 4 GND RN18 pee LED10 p LEDG1LEDG gt JA 330 LEDG2LEDG b ZA LEDG3LEDG GND Lad RN19 LEDG4LEDG 2 gt 4 LEDGSLEDG AX 330 LEDG6LEDG b LEDG7LEDG 3 GND Figure 4 5 Schematic diagram of the LEDs SW 0 PIN_L22 Toggle Switch 0 SW 1 PIN L21 Toggle Switch 1 Swi PIN_M22 Toggle Switch 2 SW 3 PIN V12 Toggle Switch 3 SWIA4 PIN W12 Toggle Switch 4 SW 5 PIN U12 Toggle Switch 5 SW 6 PIN U11 Toggle Switch 6 SWI7 PIN M2 Toggle Switch 7 28 DEI User Manual SWI8 PIN_M1 Toggle Switch 8 swig PIN_L2 Toggle Switch 9 Table 4 1
11. R 1 PIN C9 VGA Redq 1 R 2 PIN A7 VGA Red 2 VGA R 3 PIN B7 VGA Red 3 VGA_G 0 PIN_B8 VGA Green 0 VGA G 1 PIN C10 VGA Green 1 2 9 VGA Green 2 VGA G 3 PIN A8 VGA Green 3 DEI User Manual VGA 0 PIN A9 VGA Blue 0 VGA B 1 PIN D11 VGA Blue 1 VGA 2 PIN A10 VGA Blue 2 VGA PIN B10 VGA Blue 3 VGA HS PIN A11 VGA H SYNC VGA VS PIN B11 VGA V SYNC Table 4 8 ADV7123 pin assignments 4 7 Using the 24 bit Audio CODEC The DEI board provides high quality 24 bit audio via the Wolfson WM8731 audio CODEC enCOder DECoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WM8731 is controlled by a serial I2C bus interface which is connected to pins on the Cyclone II FPGA A schematic diagram of the audio circuitry is shown in Figure 4 15 and the FPGA pin assignments are listed in Table 4 9 Detailed information for using the WM8731 codec is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder on the DE1 System CD ROM vcca3 VCC33 R2 R 4 2K K C2 10 R 4 2 SCLK 2 SDAT R5 4 7K 4 7K I2C ADDRESS READ IS 0x34 126 ADDRESS WRITE IS 0x35 AGND AGND
12. d Table 4 10 lists the Cyclone II FPGA pin assignments Figure 4 16 MAX232 RS 232 chip schematic UART RXD PIN F14 UART Receiver UART_TXD PIN_G12 UART Transmitter Table 4 10 RS 232 pin assignments N DTE SYAN DE1 User Manual 4 9 PS 2 Serial Port The DE1 board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 4 17 shows the schematic of the PS 2 circuit Instructions for using a PS 2 mouse or keyboard can be found by performing an appropriate search on various educational web sites The pin assignments for the associated interface are shown in Table 4 11 vecs R36 R37 PS2 DAT R3 120 lt _ 7 1 i J 5 1 nco TOP DAT 45 BATS4S 4 3 vec Oo NOD 4 4 GND EDS e BC62 GND 5 010 GND ESE 100 GND GND vCCa3 GND ub SHIELD2 GND PS2 Figure 4 17 PS 2 schematic PS2 CLK PIN H15 PS 2 Clock PS2_DAT PIN_J14 PS 2 Data Table 4 11 PS 2 pin assignments 4 10 Using SDRAM SRAM Flash The DEI board provides an 8 Mbyte SDRAM 512 Kbyte SRAM and 4 Mbyte 1 Mbyte on some boards Flash memory Figures 4 23 4 24 and 4 25 show the schematics of the memory chips The pin assignments for each device are listed in Tables 4 16 4 17 and 4 18 The datasheets for the memory chips are provided in the Datash
13. e the 18 toggle switches and eight green LEDs are found above the pushbutton switches the 9 green LED is in the middle of the 7 segment displays Each LED is driven directly by a pin on the Cyclone II FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off A schematic diagram that shows the pushbutton and toggle switches is given in Figure 4 4 A schematic diagram that shows the LED circuitry appears in Figure 4 5 A list of the pin names on the Cyclone II FPGA that are connected to the toggle switches is given in Table 4 1 Similarly the pins used to connect to the pushbutton switches and LEDs are displayed in Tables 4 2 and 4 3 respectively RN21 VCC33 700K us GND 10 vec 20 ovCC33 RN22 KEYINO 11 2 1 KEYO T 1 g rg KEY1 I T KEYINZ 7 A 6 KEY2 i T KEYINS 5 45 86 14 KEY3 A4 15 x lt KEY0 KEY1 KEY2 KEY3 4 A Lis x 10 ig 4 1 p ig p4 3 A2 B2 12 120 coon XJA mm x PBSW PBSW PBSW PBSW 4 DIR e p GND Seed f GND VCC33 GND 74HC245 TSSOP 20 swo SW1 sw2 sw3 SWA sw5 swe Sw GND GND GND E 5 GND 5 G
14. eet folder on the DE1 System CD ROM 40 DEI User Manual R_VCC33 DRAM_DO R_VCC33 DRAM_D1 DRAM_D2 GND DRAM_D3 DRAM_D4 R_VCC33 DRAM D5 DRAM D6 GND DRAM D7 R_VCC33 DRAM_LDQM DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS DRAM_BAO DRAM_BA1 DRAM A10 DRAM A0 DRAM A1 DRAM A2 DRAM A3 R_VCC33 SRAM A0 SRAM AT SRAM_A2 SRAM_A3 SRAM_A4 SRAM CE SRAM_DO SRAM_D1 SRAM_D2 SRAM_D3 R VCC33 GND SRAM D4 SRAM_D5 D6 SRAM D7 SRAM WE SRAM_A5 SRAM A6 SRAM_AT SRAM_AS SRAM_AQ SDRAM 1Mx16x4 TSOP 54 Figure 4 23 SDRAM schematic 5611 925616 TSOP 44 Figure 4 24 SRAM schematic 41 SRAM SRAM SRAM SRAM SRAM GND DRAM_D15 GND DRAM_D14 DRAM_D13 R_VCC33 DRAM_D12 DRAM D11 GND DRAM D10 DRAM DS R_VCC33 DRAM D8 GND DRAM UDOM DRAM CLK DRAM CKE DRAM A11 DRAM A9 DRAM A8 DRAM A7 DRAM A6 DRAM A5 DRAM A4 GND A17 A16 A15 OE UB SRAM LB SRAM D15 SRAM D14 SRAM SRAM GND D13 D12 R_VCC33 SRAM D11 SRAM_D10 SRAM SRAM SRAM SRAM SRAM SRAM SRAM Da D8 A14 A13 A12 A11 A10 AN RYA DEI User Manual u9 FLASH A16 1 6 48 FASTAN A16 FLASH A17 L FLASH A15 2 FLASH 15 A14 BYTE 41 GND FLASH_A14 31214 CAE GND FLASH_A13 aua 45 FLASH AD FLASH A12 s pen or L44 FLASH D7 FLASH AT amp 7 aa FLASH 10 7 Aa poids FLASH D6 FLASH A9 6
15. he expansion headers is connected to a resistor that provide protection from high and low voltages The figure shows the protection circuitry for only four of the pins on each header but this circuitry is included for all 72 data pins Table 4 7 gives the pin assignments 32 NO YA DEI User Manual 6 824 GPIO B28 GPIO 827 GPIO B31 JP1 GPIO 0 545 f ib TO_A4 43 P 10_A5 qs D IO AG d5 P IO A7 IO A8 d X vecs O o A10 g 1 P IO 1 ND 11 D J OATS dt P 10 Al 4 IO 18 IO A20 g 21 P A21 IO A22 23 P IO A23 IO A24 20 D IO A25 eid GND VCC33 O q 29 D ET ds mp IO AZ 33 D IO A30 A31 IO A32 4 q 10_A23 10_A34 45 GPIO B63 IO l IO 81 j 10 4 P 57 1 88 1 85 GND VOCs O76 BIO E Io Bir 1GND E i ib 10_516 10 817 10 618 P 10 819 10 820 P 10 821 10 622 P 10 823 1 2 10 824 P 10 825 GND VCC33 O D DET 15 Sp DET IO 30 5 10 831 D IO B32 P lO B33 IO B34 5 10 835 Figure 4 10 Schematic diagram of the expansion headers GPIO O 0 PIN A13 GPIO Connection O 0 33 DEI User Manual O 1 PIN B13 GPIO Connection O 1 GPIO 0 2 PIN A14 GPIO Connection O 2 GPIO O 3 PIN B14 GPIO Connection O
16. hich is followed by the display interval c 36 N DTE SYAN DE1 User Manual During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next Async pulse can occur The timing of the vertical synchronization vsync is the same as shown in Figure 4 12 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Figures 4 13 and 4 14 show for different resolutions the durations of time periods a b c and d for both horizontal and vertical timing The pin assignments between the Cyclone II FPGA and the VGA connector are listed in Table 4 8 An example of code that drives a VGA display is described in Sections 5 2 and 5 3 Back porch b Front porch d Display interval c j interval DATA HSYNC I Sync a Figure 4 12 VGA horizontal timing specification Configuration Resolution HxV Pixel clock Mhz VGA 60Hz 640x480 3 8 19 254 06 25 640 Figure 4 13 horizontal timing specification Configuration Resolution HxV a lines b lines c lines d lines VGA 60Hz 640x480 2 33 480 10 Figure 4 14 VGA vertical timing specification PIN D9 VGA Red 0 VGA
17. lename extension USB Blaster Circuit PROG RUN Quartus II JTAG Config Signals Programmer JTAG UART JTAG Config Port Auto Power on Config EPCS4 Serial Configuration Device Figure 4 1 The configuration scheme Configuring the EPCS4 in AS Mode Figure 4 2 illustrates the AS configuration set up To download a configuration bit stream into the EPCS4 serial EEPROM device perform the following steps Ensure that power is applied to the DEI board Connect the supplied USB cable to the USB Blaster port on the DEI board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the PROG position The EPCSA chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCSA device to be loaded into the FPGA chip 25 N DTE YA DE1 User Manual USB Blaster Circuit RUN PROG Quartus AS Mode Programmer Config AS Mode Auto For Power on Contig EPCS4 Serial Configuration Device Figure 4 2 The AS configuration scheme In addition to its use for JTAG and AS programming the USB Blaster po
18. nt Digit 2 4 HEX2 5 PIN_E4 Seven Segment Digit 2 5 HEX2 6 PIN D3 Seven Segment Digit 2 6 HEX3 0 PIN F4 Seven Segment Digit 3 0 HEX3 1 PIN D5 Seven Segment Digit 3 1 HEX3 2 PIN D6 Seven Segment Digit 3 2 HEX3 3 PIN J4 Seven Segment Digit 3 3 HEX3 4 PIN L8 Seven Segment Digit 3 4 HEX3 5 PIN F3 Seven Segment Digit 3 5 HEX3 6 PIN D4 Seven Segment Digit 3 6 Table 4 4 Pin assignments for the 7 segment displays 4 4 Clock Inputs The DEI board includes three oscillators that produce 27 MHz 24Mhz and 50 MHz clock signals The board also includes an SMA connector which can be used to connect an external clock source to the board The schematic of the clock circuitry is shown in Figure 4 8 and the associated pin assignments appear in Table 4 5 31 DEI User Manual EXT CLOCK GND Figure 4 8 Schematic diagram of the clock circuit CLOCK 27 PIN D12 PIN E12 27 MHz clock input CLOCK 50 PIN L1 50 MHz clock input CLOCK 24 PIN A12 PIN B12 24 MHz clock input from USB Blaster EXT CLOCK PIN M21 External SMA clock input Table 4 5 Pin assignments for the clock inputs 4 5 Using the Expansion Header The DEI Board provides two 40 pin expansion headers Each header connects directly to 36 pins on the Cyclone II FPGA and also provides DC 5V VCC5 DC 3 3V VCC33 and two GND pins Figure 4 10 shows the related schematics Each pin on t
19. on 1 35 Table 4 7 Pin assignments for the expansion headers 35 ND YA DEI User Manual 4 6 Using VGA The DEI board includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone II FPGA and a 4 bit DAC using resistor network is used to produce the analog data signals red green and blue The associated schematic is given in Figure 4 11 and can support standard VGA resolution 640x480 pixels at 25 MHz n AYA ATS VGA RO DB15 RA F2 Sera tae VGA R1 VGA R2 VGA R3 R RN1 2K RO603 4R N RN2 1K RO603 4R N VGA 80 VGA B1 TERAP VGA B2 VGA B3 RN5 2K B R0803 4R N VGA_VSYNC wre 4 H AA VGA HSYNC VGA VSYNC Figure 4 11 VGA circuit schematic The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 4 12 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization Async input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs w
20. onnected and cannot be used Table 4 4 shows the assignments of FPGA pins to the 7 segment displays RN7 HEXO DO 2 AD HEXO D1 4 80 02 HEXO D3 7 2 DO 330 RNB 04 2 0 HEXO_D5 DS HEXi DO 7 B 330 RNO HEX D1 2 HEX1 02 4 HEX1 D3 D1 HEX D4 7 7Segment Display RN10 HEX3 D3 1 2 D3 HEX 3 D4 E3 lt 3 05 F3 Iz ol HEX3 D6 G3 PES 330 Figure 4 7 Position and index of each segment in a 7 segment display 30 DEI User Manual HEXO 0 PIN J2 Seven Segment Digit 0 0 HEXO 1 PIN J1 Seven Segment Digit O 1 HEXO 2 PIN H2 Seven Segment Digit O 2 HEXO 3 PIN H1 Seven Segment Digit O 3 HEXO 4 PIN F2 Seven Segment Digit O 4 HEXO 5 PIN F1 Seven Segment Digit O 5 HEXO 6 PIN E2 Seven Segment Digit O 6 HEX1 0 PIN_E1 Seven Segment Digit 1 0 HEX1 1 PIN H6 Seven Segment Digit 1 1 HEX1 2 PIN H5 Seven Segment Digit 1 2 HEX1 3 PIN H4 Seven Segment Digit 1 3 HEX1 4 PIN G3 Seven Segment Digit 1 4 HEX1 5 PIN D2 Seven Segment Digit 1 5 HEX1 6 PIN D1 Seven Segment Digit 1 6 HEX2 0 PIN_G5 Seven Segment Digit 2 0 HEX2 1 PIN_G6 Seven Segment Digit 2 1 HEX2 2 PIN_C2 Seven Segment Digit 2 2 HEX2 3 PIN_C1 Seven Segment Digit 2 3 HEX2 4 PIN_E3 Seven Segme
21. rt on the DEI board can also be used to control some of the board s features remotely from a host computer Details that describe this method of using the USB Blaster port are given in Chapter 3 42 Using the LEDs and Switches The DEI board provides four pushbutton switches Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 4 3 The four outputs called KEY3 of the Schmitt Trigger device are connected directly to the Cyclone II FPGA Each switch provides a high logic level 3 3 volts when it is not pressed and provides a low logic level 0 volts when depressed Since the pushbutton switches are debounced they are appropriate for use as clock or reset inputs in a circuit Pushbutton depressed Pushbutton released Before Debouncing Schmitt Trigger Debounced gt Figure 4 3 Switch debouncing There are also 10 toggle switches sliders on the DEI board These switches are not debounced and are intended for use as level sensitive data inputs to a circuit Each switch is connected directly to a pin on the Cyclone II FPGA When a switch is in the DOWN position closest to the edge of the board it provides a low logic level 0 volts to the FPGA and when the switch is in the UP position it provides a high logic level 3 3 volts 26 ND YA DEI User Manual There are 27 user controllable LEDs on the DEI board Eighteen red LEDs are situated abov
22. tera EPCS4 serial EEPROM chip It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the DEI board is turned off When the board s power is turned on the configuration data in the EPCSA device is automatically loaded into the Cyclone II FPGA The sections below describe the steps used to perform both JTAG and AS programming For both methods the DEI board is connected to a host computer via a USB cable Using this connection the board will be identified by the host computer as an Altera USB Blaster device The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial Getting Started with Altera s DEI Board This tutorial is available on the DE1 System CD ROM and from the Altera web pages Configuring the FPGA in JTAG Mode 24 ND SYA DEI User Manual Figure 4 1 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone II FPGA perform the following steps Ensure that power is applied to the DEI board Connect the supplied USB cable to the USB Blaster port on the DEI board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the RUN position The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof fi
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