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1. with pedestrian self service and approaching car detection Type d and press the ENTER key This will display the current time and the start and end time range for the traffic End Time 18 30 00 type ESC to abort You can display the task status using F3 similar to before The following task information will be displayed ID Start Prio State Blocked for Event Mbx Sem Timer Signal 2 986 GH 1 BLOCKED TMO 1 6166H a BLOCKED SIG 4 2ECH B BLOCKED SIG amp TMO 5 3CAH B BLOCKED THO 4GAH L BLOCKED INT 8 43AH a BLOCKED INT 39 161 2 271 272 Glossary Glossary A251 The command used to assemble programs using the A251 Macro Assembler ASI The command used to assemble programs using the A51 Macro Assembler argument The value that is passed to macro or function a synchronous In connection with real time operating systems the terms synchronous asynchronous are used to differentiate the type and way how a certain program section is to be activated The synchronous entry in a program section always occurs the same way under exactly definable circumstances data values state of CPU registers This means individual program sections are always completely processed before other program sections are executed This guarantees data consistency in the case of correct program design The asynchronous entry occurs at a point in time which is not exactly kno
2. RTX 51 RTX 251 231 unsigned char i done can bind obj 3 for done can wait Oxff amp tr 3 if done C OK done can get status if tr 3 identifier 3 for i20 i lt 7 i ts 8 c data i tr 3 c data il count 3 ts 11 c data 0 count 3 done can send amp ts 11 void send task void task SEND TASK t Start CAN Task if can task create C OK Init the CAN comm controller for a baud rate of 1000Kbauds s CAN controller with 10 MHz clock ifs 2 init for 1000KHz Baud vf can Bus freq XTAL BRP 1 1 TSEG1 1 TSEG2 1 can Bus freq XTAL 0 1 1 4 1 3 1 can Bus freq 10000 1 10 x BTRO BTR1 dummy dummy dummy done can_hw_init 0x80 0x34 0x00 0x00 0x00 done can get status Receive Objects definitions done can def obj 1 8 D REC done can get status done can def obj 2 8 D REC done can get status done can def obj 3 8 D REC done can get status dones can def obj 4 8 D REC done can get status dones can def obj 5 8 D REC done can get status Send Objects definitions dones can def obj 6 8 D SEND done can get status done can def obj 7 8 D SEND done can get status dones can def obj 8 8 D SEND done can get status 232 CAN Support done can def obj 9 8 D SEND done can get status dones can def
3. for this object can request 1200 Task waits until object 1200 received can wait Oxff amp rec mes Handle object 1200 174 CAN Support can_read Allows data to be read from every object independent of the defined object type can read cannot substitute the function can receive Can read is however useful for debugging purposes Prototype unsigned char can read unsigned int identifier void xdata buffer ptr Parameter identifier is the identification as defined in can def obj can def obj ext of the requested object buffer ptr is the pointer to a structure of the type CAN MESSAGE STRUCT in the XDATA memory The received object will be copied to this structure The structure CAN MESSAGE STRUCT defined in RTXCAN H is organised as depicted below ident 2 bytes c data 8 bytes for intel 82527 the Siemens C515C only c data 8 bytes RTX 51 RTX 251 Return Value Example 175 ident is the communication object identifier as defined in can def obj can def obj ext c data Data bytes The data length is defined as eight bytes maximum data length for the communication object for simplification reasons User structures may be defined with a data length smaller than eight bytes the first two bytes must however always represent the IDENTIFIER field The communication software always sends or receives the data length as defined with
4. Start the receiving application task and write ist task identification into the variable bbs rx tid os create task REC TASK bbs rx tid REC TASK task number of receiving task Set node address station address of this BITBUS slave bbs station addr 3 Set the configuration See 8044 documentation For BITBUS compatibility NRZI must be set PFS should be set For the peter ene clock modes use the following values Ox14 Externally clocked 0 2 4 Mbits sec 0x54 Self clocked timer overflow 244 52 4 Kbits sec 0x94 Self clocked external 16x 0 375 Kbits sec 0xB4 Self clocked external 32x 0 187 5 Kbits sec 0xD4 Self clocked internal fixed 375 Kbits sec OxF4 Self clocked internal fixed 187 5 Kbits sec All Sai rates are based on a 12 MHz crystal frequenzy bbs_konfig_smd 0xD4 Set flag bbs en sig to app to 1 upon receipt of a message the BITBUS communication task sends a signal to the receiving application task identified by bbs rx tid bbs en sig to app 1 Start BITBUS communication task for master use BBM TID os create task BBS TID Example 2 Receipt of Messages by a Slave 250 m In incl incl defi defi void BITBUS Support example 2 the receiving application task is a standard task ude lt rtx51 h gt ude bbs_rtx h ne TRUE 1 ne FALSE 0 rec exampl
5. Ra ey variation of bit time due to resynchronisation MAX baud rate 1 2Qis 4 2 5us 100 Kbauds s ey MAX baud rate 1 2Q1s 4 2 5s 33 3 Kbauds s fs e Set output control register to FFH fe 27 can hw init 0xd3 0xa3 0xff 1 0 Example 2 intel 82527 include rtxcan h Init the CAN communication controller for a baud rate of 1000Kbauds s CAN controller with 16 MHz clock fai 4 SJW Resynchronisation jump width 2 BRP Baud rate prescaler 0 Spl Sampling mode 0 Z TSEG1 2 TSEG2 3 CoBy Comparator bypass 1 G Pol Polarity 0 DeTl Disconnect TX1 output 1 DcT2 Disconnect Rx1 input 1 DcRO0 Disconnect RX0 input 0 RstSt Hardware reset status 0 E DSC Divide system clock 1 DMC Divide memory clock O0 PwD Power down mode enabled 0 Sleep Sleep mode enable O0 e MUX Multiplex for ISO low speed physical layer 0 Cen Clockout enable 1 if G Baud rate XTAL DSC 1 BRP 1 3 TSEG1 TSEG2 Baud rate 16000 1 1 0 1 3 3 5 1000KHz can hw init 0x80 0x23 0x5E 0x41 dummy 144 CAN Support Example 3 Siemens 81C90 91 include lt rtxcan h gt Init the CAN communication controller for a baud rate of 1000Kbauds s CAN controller with 16 MHz clock fe e Bit Length Register 1 s
6. echec KK HK e ke ke khe hehehe hehehe e KK HK HK e e he he IK IK KK ke kk ke he hehe hehehe He ke kk e He e de e ee IK KK KKK e e eek f void car detl void task CAR DETI1 os attach interrupt 0 Attach INTO TCON 0x01 Use edge triggered RTX 51 RTX 251 267 while 1 endless loop os wait K INT Oxff 0 Wait for interrupt if phaseno gt 3 phaseno 4 7 if cardetected2 amp amp keypressedl amp amp cardetectedl os send signal LIGHTS send signal to lights cardetectedl 1 2 H k e e He e ke ke ke ke he hehe KKK KK HK de e e e he he IK IK KK kk kk he he e he hehehe He ke kk e He e He e He He de He eee ee eek f Task 7 car det2 process interrupt from car detector 2 RRR RIKKI KKK KKK HK hehe he IK KK KK HK e e e he he he hehe KK KK AAA KIKI KK KKK KKK KEK IKI KKK KKK KKK EK f void car_det2 void _task_ CAR_DET2 os_attach_interrupt 2 Attach INT1 TCON 0x04 Use edge triggered while 1 endless loop os wait K INT Oxff 0 Wait for interrupt if phaseno 4 phaseno 0 3 if cardetectedl amp amp keypressed2 amp amp cardetected2 os send signal LIGHTS send signal to lights cardetected2 1 BERRI IK IK HK HK He He e He He He e e He He KKK HK AIA AAA IKK KKK KKK KKK IK IKK KKK KKK KEK KKK IAA AIA AA AAA MAIN Start the system e BERRI IK IK ke e ke e KIKI KK
7. m 22 bytes for general system variables segment RTX RTX RELBYTE SEG and RTX PBP m 2 bytes for each INTERRUPT ENABLE register supported by the 8051 processor are used segment RTX INT MASK RTXCONF gt 2 bytes for processors with one IE register e g 8xC251SB gt 4 bytes for processors with two IE registers gt 6 bytes for processors with three IE registers Direct Addressable External Memory EDATA The EDATA area of the processor is assigned by RTX 251 in the following way 122 Configuration m 32 bytes for general system variables segment RTX RTX EDATA SEG m Task context save areas one per declared task Free stack space stack grows from lower to higher addresses Context data of task a maximum of approx 32 bytes Stack data of task temporary stored data by Push Pop and return addresses of subroutine calls Saved stack pointer 2 bytes Figure 10 RTX 251 Task Context Layout task not running Each task uses its own private stack area Upon a task switch all the context data belonging to a task is stored on its stack and the stack pointer is changed to the next task s stack area If a task is interrupted by a C251 interrupt function then the interrupt function uses the interrupted task s stack area Depending on the task state and the occurrence of interrupts for C251 interrupt functions basically the context layouts shown in Figure 10 Figure 11 and Figure 12 exist Free
8. typedef struct void xdata block signed char task number t rtx blockinfo 255 block identifies a certain block non existent blocks are identified with a null pointer task number is the identification of a task which controls the block OK 0 Function executed successfully NOT OK 1 Function not executed RTX 51 RTX 251 107 Example include lt rtx51 h gt Use rtx251 h for RTX 251 void xyz task void task 0 priority 0 t rtx blockinfo xdata table os check pool 2 amp table Evaluation of the table RTX 51 RTX 251 109 Chapter 5 Configuration By means of configuration file RTXSETUP DCL RTX 51 251 can be adapted to various members of the 8051 MCS 251 processor family and to application specific requirements The easiest way to do the configuration is by use of the configuration utility RTXSETUP EXE under MS WINDOWS This setup program displays the current contents of the configuration file RTXSETUP DCL By use of a menu display all the user configurable values may be set The following system values can be configured above all Type of 8051 MCS 251 family CPU used 8051 MCS 251 hardware timer to be used for the system clock Initial interrupt enable register values Fast task stack and environment size RTX 51 Standard task context stack size RTX 51 Task stack size RTX 251 Reentrant stack size Timesharing option round robin scheduling Bankswitching supp
9. 1 recessive 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IM ee oy ey ey RICO CONO IMRORLIONLRO ee fap rey MCN Sleep and BR Prescale Register MSB SME Sleep mode enable BRP5 Baud rate prescaler BRP4 BRP3 BRP2 BRP1 BRPO LSB SME Sleep mode enable One The sleep mode is enabled the crystal oscillator is deactivated all other activates are inhibited The wake up is done by a reset signal or by an active signal at the CS pin or by an input edge going from recessive to dominant at pin Rx0 or Rx1 Zero Normal operation 206 CAN Support Clock Control Register MSB e 5 E mi x 13 cca 2 cc cct SR o cco Output frequency fosc fosc 2 fosc 4 fosc 6 fosc 8 fosc 10 fosc 12 fosc 14 switched off low level o o o o o o oo ve SS et e llc i gt e gt ev gt US 0 0 0 0 1 1 1 1 x 81C90 91 Programming Example Init the CAN communication controller 81C91 for a baud rate of 1000Kbauds s CAN controller with 16000 kHz clock Baud rate prescaler reg BRP5 BRP4 BRP3 BRP2 BRP1 BRPO 0 0 0 0 0 0 0 0 00H fscl BRP 1 2 fosc fosc 1 fcrystal fscl BRP 1 2 fcrystal 0 1 2 16000 1 8000 0 000125 mS RTX 51 RTX 251 207 Bit Length Register 1 SAM TS2 2 TS2 1 TS2 0 TS1 3 TS1 2 TS1 1 TS1 0 0 0 1 0 0 0 1 1 23H TS1 3 TS2 2 TSEGI TS1 1 fscl 3 1 fscl 4 0 000125 0 0005 mS TSEG2
10. Debug Functions os check tasks table os check task task number table os check mailboxes table os check mailbox mailbox table os check semaphores table os check semaphore semaphore table os check pool block size table 42 Programmer s Reference Initialize and Start the System Function Call Overview A C51 C251 application typically will start its program execution by the main function after the C runtime environment has been set up The startup of the run time environment is handled by a C51 C251 library function whose source code can be seen in file STARTUP A51 STARTxxx A51 xxx designating a special version or in file START251 A51 respectively The function main called main program contains the first user statement at its beginning It establishes the subroutine level 0 of every user application The first subroutine called by it will run on the subroutine level 1 and so on During its execution the following environment elements are used by the main program independent of use of RTX 51 251 1 Register bank 0 2 System stack top 2STACK An application with RTX 51 251 will behave just like an application without RTX 51 251 until the moment the os start system function is called By use of this function the normal C program will be transformed into a multitasking system The following steps will take place during os start system disable all interrupts clear the
11. include lt rtx51 h gt Use rtx251 h for RTX 251 void fast int void interrupt 7 using 1 C51 C251 int function waits for int 7 Uses register bank 1 ISR code void isr manager void task 4 priority 1 Disable the interrupt with vector number 7 if os disable isr 7 error handling task code 60 Programmer s Reference oi set int masks Task ISR function The system operation oi set int masks sets one or more interrupt mask bits immediately Since this function is dedicated to non standard cases it does not contain any parameter checks Its use should be restricted to the following special cases to manipulate special bits which are part of the interrupt enable registers Example watchdog control bits on 80C517 80C537 processors to modify interrupt enable bits from inside a C51 C251 interrupt function Not to be used for interrupt sources attached to RTX 51 251 tasks Prototype signed char oi set int masks unsigned char ien0 unsigned char ien1 unsigned char ien2 Parameter ien ien1 ien2 represent the bit masks of the interrupt enable registers An interrupt source to be enabled explicitly has to set its associated bit For this parameter the same bit layout is used as defined for the corresponding interrupt enable registers Depending on the processor type used zero or more of these masks are insignificant Use as follows ienO ienl ien2 for processors
12. 1 Message 6 ts datas datas of received message for i20 i lt 7 i ts 6 c data i tr 1 c data i l count 1 count gt 1 data of Message 9 ts 9 c_data 0 count 1 send Message 9 done can send amp ts 9 void rec_task_2 void _task_ REC_TASK_2 _priority_ 1 unsigned char i done can bind obj 2 for done can wait Oxff amp tr 2 if done C OK done can get status if tr 2 identifier 2 for i20 i lt 7 i ts 7 c data i tr 2 c data il count 2 ts 10 c_data 0 count 2 done can_send amp ts 10 void rec task 3 void task REC TASK 3 priority 1 t unsigned char i done can bind obj 3 for L done can wait Oxff amp tr 3 if done C OK done can get status if tr 3 identifier 3 for i20 i lt 7 i ts 8 c data i tr 3 c data i l count 3 ts 11 c data 0 count 3 done can send amp ts 11 void send task void task SEND TASK RTX 51 RTX 251 221 Start CAN Task if can task create C OK Init the CAN comm controller 82527 for a baud rate of 1000Kbauds s CAN controller with 16 MHz clock SJW Resyncronization jump width 2 BRP Baud rate prescaler 0 wf Spl Sampling mode 0 wu TSEG1 2 TSEG2 3 v CoBy Comparator bypass 1 E Pol Polarity 0 DeTl Disconnect TX1 output 1 DcT2 Disconnect Rx1
13. 1 Bit Cyele terr Baud rate 191 f crystal INSYNC SJW1 TSEGI TSEG2 SJW2 nn f crystal 2 Baud rate prescaler 1 INSYNC SJW1 TSEG1 TSEG2 SJW2 1 terr Variation in baud rate due to resynchronisation 1 MAX Baud rate terr SJW2 teri 1 MIN Baud rate terr SJWI tg Programming the Intel 82526 Function CAN_HW_INIT allows the CAN controller bus timing to be programmed The parameters refer to 82526 hardware registers in the following way BUS TIMING 0 BUS TIMING 1 SYNCON Bus Timing Register 0 MSB SJW B l6 SUWA 5 BRP 5 mi BRP 4 E BRP 3 Bus timing register 0 Bus timing register 1 SYNCON bit in the control register Synchronisation Jump Width Baud Rate Prescaler 192 CAN Supporti 9 BRP 2 ao BRP 1 LSB o BRP 0 Baud Rate Prescaler BRP The BTL cycle time is determined by programming the six bits of the baud rate prescaler The BTL cycle time is derived from the system cycle time the system cycle time is twice the crystal time The desired baud rate is determined by the BTL cycle time and the programmable bit timing segments BRP 2 BRP5 2 BRP4 2 BRP3 2 BRP2 2 BRP1 BRPO Synchronisation Jump Width SJW The synchronisation jump width defines the maximum number of BTL cycles that a bit may be shortened or lengthened by one resynchronisation during transmission of a data frame or remote frame Synchron
14. Example 1 Standard task with task number 8 and priority 0 void example 1 void task 8 priority 0 or void example_1 void _task_ 8 Example 2 Fast task with task number 134 and register bank 1 Note registerbank declarations are required for RTX 51 only pragma REGISTERBANK 1 void example 2 void task 134 priority_ 3 m Example of typical task layouts 22 Programming Concepts Initialisation Initialisation Function to b Function to be unction to be performed performed once once for each event System call delete itself System call wait for event Figure 4 Typical Task Layouts Task 1 shown in the figure above has to perform a certain action each time an event occurs Such an event may be a received message a signal or a time out just to mention a few After completing its action it will start to wait for a new event In this way the task will not consume time just waiting for the next event Task 2 shown in the figure above has to perform just one specific action It will delete itself after completing its job Such a task may be for example a self test which has to be executed once at power up Itis often desirable to write such a self test routine as a separate task than packing it in a routine Interrupt Management The management and processing of hardware interrupts is one of the major jobs of a Real Time Multitaskin
15. The individual members of the 8051 MCS 251 family differentiate between one another for RTX 51 251 in number and addresses of the INTERRUPT ENABLE registers and in the assignment of the interrupt number to ENABLE bits Configuration file RTXCONF A51 contains the required data for all different processors To select a certain processor the configuration file must be reassembled with the Keil 8051 MCS 251 Assembler Before this is done the desired CPU number has to be defined in the configuration header file RTXSETUP DCL Supported types for RTX 51 are Manufacturer Model Pod laa essaie mos 003 fe messer maa n 5 laa agr amors 8 E Es 2 5 3 Intel 88F51FC 83F51FC 14 Siemens 80515 80C515 80535 80535 3 Siemens 80517 80C537 Siemens 80C517A 80C517A 5 Es RTX 51 RTX 251 129 Philips 80C552 83C552 6 Philips 80C592 83C592 87C592 Philips 800652 830652 10 Supported types for RTX 251 are Manufacturer Model TOC Intel 8xC251SB tb d mE The list depicted above only provides a brief overview on the most important processor types supported A detailed list of all processor types currently supported by RTX 51 251 is contained at the top of the configuration header file designated RTXSETUP DCL Assembling the Configuration File RTX 51 A51 RTXCONF A51 DEBUG RTX 251 A251 RTXCONF A51 DEBUG The option DEBUG is required when the RTX debug macro shall be used under dScope 51 251
16. can get status os wait K TMO 5 0 count 3 BRR KKK ee ee e He HH KKK KKK he he e He ke KKK HK KKK KKK IKK ke e ee e He e He KKK KK KK KK KK KK KK KK IK MAIN PROGRAM RRR RK RRR KKK e He e KKK de He e He KKK KKK KIRK KK KKK KK KKK e He e He e He de KK KEKE KKK KKK EK void main void os_start_system SEND_TASK END of MODULE ICANDEMO Compiling and Linking the Program for the Siemens C515C c51 exe icandemo c51 define EXTEND a5l exe icanconf a51 a5l exe rtxconf a51 SET proc type 21 BL51 icandemo obj icanconf obj rtxconf obj rtxican lib rtx51 ramsize 256 Depending on the CAN controller chip and CPU used above shown sequence has to be modified slightly see examples contained on distribution disk Meaning of define EXTEND in batch files For Intel 82527 and Siemens C515C by using Define EXTEND in Header file RTXCAN H can message struct will be defined as struct can message struct 234 CAN Support unsigned long identifier unsigned char c data 8 h and the identifiers in those functions will be according to can message struct as unsigned long defined unsigned char can bind obj unsigned long identifier unsigned char can unbind obj unsigned long identifier unsigned char can request unsigned long identifier unsigned char can read unsigned long identifier void xdata buffer ptr In addition all following functions related to last 15
17. define REC TASK 1 define REC TASK 2 define REC TASK 3 LJ M A Global variables CAN send and receive data struct can message struct xdata ts 14 230 CAN Support struct can message struct xdata tr 14 unsigned char i j done unsigned int inx unsigned int ident unsigned char count 14 BRR RK IKI ee ke ke KKK KK KKK IK KK e He KKK e He e KKK KKK KKK KKK KKK KKK IK KK KK KK KK KKK k Test Tasks E RRR RK IKK kk echec hehe hehe IKK KK KKH KKK KKK IKI KK KK KKK eee KKK e He KK KK KK KR KR KK KK IK void rec task 1 void task REC TASK 1 _priority_ 1 unsigned char i done can bind obj 1 for wait for Message 1 done can wait Oxff amp tr 1 if done C OK done can get status if tr 1 identifier 1 Message 6 ts datas datas of received message for i20 i lt 7 i ts 6 c data i tr 1 c data i l count 1 count 1 data of Message 9 ts 9 c data 0 count 1 send Message 9 done can send amp ts 9 void rec task 2 void task REC TASK 2 priority 1 unsigned char i done can bind obj 2 for done can wait Oxff amp tr 2 if done C OK done can get status if tr 2 identifier 2 for i20 i lt 7 i ts 7 c data i tr 2 c data il count 2 ts 10 c_data 0 count 2 done can send amp ts 10 void rec task 3 void task REC TASK 3 priority 1
18. eee 126 Number of the Processor Type Used ii 128 Chapter 6 CAN TT O rincari nananana 131 Introducti h enam Dr d petiere de 131 lev 133 Application Interface het eee ere e e i edi EE 135 Function Call Overview iii 136 Furiction Call Description uiii eph ere Pete ee PER 138 LE SUT E iii iso eee Se te ET 179 Hardware Requirements iii ei rt RO EE RR ERRAT 179 Configuration Files 3 5 51 0 ipe ERE RH REPERI i 179 Memory System Requirements ii 181 Adapting Stack Sizes nu Red DRAN etie ete gta 181 Linking REXGAN X51 uei dede TURO UR A 181 DEC ICH EE 183 Timing Imtialization o aee ee RR ge Ores 184 QUICK Starts UR 184 Bit Tinga iiie URSI DI ERU TR D 186 Sample Point Configuration Requirements eee eee eee eee eee 190 Intel 825206 Bus Timmins eite teri e eX ER ia 190 Intel 82527 Bus Timings ne iis pis 195 Siemens 81C90 91 Bus Timing iii 201 Philips 82C200 80C592 Bus Timing ii 208 Siemens C515C Bus Timing ne eerie Aia 212 Application Exaniples 5 3 sala ed p ee Hee iii oil 215 Piles Delivered ous 2 7572 e iit RUE LE RUE be 1 Toi 235 Chapter 7 BITBUS Support RTX 51 4 eee eese eee reete eene tennnue 237 Introduction 1 Ie er eere eee e X eb e OES E ae ERES 237 Abbrevi tlols ei rot net ee ere Pa p eR p een 238 iS 239 Requirements siete tdi Oe aan 242 B
19. m Upon the occurrence of a sequence error in a received command message this message is returned to the master with response code E PROTOCOL ERROR m Upon a wrong length parameter field LENGTH does not correspond to the number of transmitted bytes the received command message is returned to the master with response code E PROTOCOL ERROR m Upon the receipt of an invalid I field less than five bytes or greater than 18 bytes the received command message is returned to the master with response code E PROTOCOL ERROR m If the application sets up a message with an invalid value in the LENGTH field greater than 20 the communication task does not transfer the message and the field BUFFER FULL remains unchanged because the message has not been transmitted The master driver does not transfer messages with an invalid value in the LENGTH or NODE field The message is returned to the application task with the response code E PROTOCOL ERROR Files Delivered All files are located in the BITBUS sub directory of the C51 C251 tools directory Libraries BBM20 LIB Library with BITBUS master task BBS20 LIB Library with BITBUS slave task RTX 51 RTX 251 253 PLM51 LIB Dummy library for the linker The BITBUS communication task is written in PL M 51 but fully compatible to the KEIL C 51 Libraries BBM20 LIB and BBS20 LIB contain all the references required for linking However the linker detects the code inside the BITBUS
20. unsigned int identifier Reads an object data direct Communication object identifier 0 2031 void xdata buffer_ptr pointer to a structure of type CAN MESSAGE STRUCT can read last obj void xdata buffer ptr Reads last object data direct pointer to a structure of type CAN MESSAGE STRUCT Function Call Description The RTXCAN x51 function calls are explained in detail in the following sections Each description contains the following Verbal explanation of the function call Function prototype as declared in RTXCAN H Detailed explanation of each parameter List of all return codes defined for this function Notes on any special features of this function Example for use All function calls are the same for the Philips 82C200 Philips 80C592 the Intel 82526 82527 the Siemens 81C90 91 C515C CAN controllers Differences are noted in the description of the corresponding function call The names of RTXCAN x51 function calls begin with can to differentiate them from standard RTX 51 251 system functions RTXCAN x51 function calls may be used solely by RTX 51 251 tasks calling any CAN function from a C51 C251 interrupt function will lead to a system malfunction RTX 51 RTX 251 139 can task create Creates the CAN task Must be the first function call before any other CAN functions are used Prototype Parameter Return Value Note Example unsigned char can task create void none C OK CAN c
21. 0000 IU LQ LA a c G K A UN 184 CAN Support Timing Initialization Quick Start The CAN protocol provides many parameters for fine tuning the bus timing for application specific requirements cable length noise on the bus output driver configuration etc This step requires an extensive understanding of the CAN protocol see the following sections and the CAN controller documentation To simplify the beginning with CAN the following tables provide some typical configuration values for a number of bit rates All values are calculated for a CAN controller crystal frequency of 16 MHz The values BUS TIMING 0 BUS TIMING 1 and SYNCON are the parameters for the function call CAN HW INIT The values MIN B and MAX B represent the allowed baud rate variation due to resynchronisation in Kbits s Intel 82526 Baud Rate BRP SJW TSE TSE SAM BUS BUS Kbit s G1 G2 PLE TIMING O TIMING 1 RTX 51 RTX 251 185 Philips 82C200 80C592 Baud Rate BRP SJW TSE TSE SAM MIN BUS _ BUS _ Kbit s G2 28 2 TIMING O TIMING 1 Intel 82527 BUS TIMING 0 BUS TIMING 1 BUS CONFIG CPU INTERFACE are the relevant parameters for this CAN controller Baud Rate BRP SJW SPL TSEG1 TSEG2 DSC BUS BUS Kbit s TIMING_0 TIMING 1 Siemens 81C90 91 BIT LENI BIT LEN 2 and BRP are the relevant parameters for this CAN controller Baud Rate BRP SJW TSEGi TSEG2 BIT LEN1 BIT LEN2 Kbit s
22. A project definition file named SAMPLE PRJ contains all required settings and automatically identifies all required files Use Open project from the Project menu to select this file SAMPLE PRJ can be found in the sub directory RTX51 for RTX 51 or RTX251 for RTX 251 in the C51 C251 tools directory By use of the Make Build project selection out of the Project menu the sample program is compiled and linked in one step RTX 51 RTX 251 7 Extract from the MAP file generated by BL51 L251 BL51 L251 generates a task list which lists all tasks defined in the system along with their identification number the defined priority and the register bank used RTX 51 MS DOS BL51 BANKED LINKER LOCATER V3 11 INVOKED BY BL51 EXE SAMPLE OBJ RTXCONF OBJ RTX51 MEMORY MODEL LARGE INPUT MODULES INCLUDED SAMPLE OBJ SAMPLE RTXCONF OBJ RTX CONFIGURATION C51 LIB RTX51 LIB RTXINIT C51 LIB RTX51 LIB RTXDATA C51 LIB RTX51 LIB RTXCLK C51 LIB RTX51 LIB RTXCREA C51 LIB RTX51 LIB RTXINT C51 LIB RTX51 LIB RTXWAIT C51 LIB RTX51 LIB RTXSEND C51 LIB RTX51 LIB RTX51 LIB VERSION 0V500 C51 LIB RTX51 LIB RTXBLOCK C51 LIB RTX51 LIB RTXDISP C51 LIB RTX51 LIB RTXQUOP C51 LIB RTX51 LIB RTXIHAND C51 LIB RTX51 LIB RTXINS C51 LIB RTX51 LIB RTX2C51 C51 LIB C51L LIB C STARTUP QQ0Q000000000000202 TASK TABLE OF MODULE SAMPLE SAMPLE TASKID PRIORITY REG BANK SEGM
23. C CAN FAILURE Errors while starting the communication Example include rtxcan h Stop the CAN communication can stop Restart the CAN communication can start 154 CAN Support can_send Sends an object which is pre defined with can def obj with new data via the CAN bus Prototype unsigned char can send void xdata msg ptr Parameter msg ptr is the pointer to a structure of the type CAN MESSAGE STRUCT in the XDATA memory The structure CAN MESSAGE STRUCT defined in RTXCAN H is organised as depicted below c data 8 bytes for intel 82527 the Siemens C515C only c data 8 bytes ident is the communication object identifier as defined in can def obj c data Data bytes The data length is defined as eight bytes maximum data length for the communication object for simplification reasons RTX 51 RTX 251 155 User structures may be defined with a data length smaller than eight bytes the first two or four bytes must however always represent the IDENTIFIER field The communication software always sends or receives the data length as defined with can def obj can def obj ext Return Value C OK Object sent C OBJ ERROR Object undefined or object has the wrong type the parameter object type in the function call can def obj does not have the value D SEND or D SEND R REC C SEND ERROR Object not sent bus access errors this error is an indicati
24. Disable interrupts globally EA 0 Copy data using multiple data pointers memcpy newbuf oldbuf sizeof newbuf Re enable interrupts globally EA 1 Disable usage of multiple data pointers pragma NOMODAMD Code Bankswitching RTX 51 is fully compatible with the code banking scheme implemented by BL51 version X2 04 or above RTX 251 does not support code bank switching since code size may exceed 64 Kbytes in any case Building of a banked system requires the following steps RTX 51 only m Adapt the file LSI BANK ASI to your requirements see BL51 documentation m Set the symbol 7RTX_BANKSWITCHING in RTXSETUP DCL to 1 38 Programming Concepts m Link the system as described in the BL51 documentation All defined banks can be used freely by the RTX 51 tasks m The following code sections are automatically located in the common area RTX 51 system functions Reset and interrupt vectors Code constants C51 interrupt functions Bank switch jump table Intrinsic C51 run time library functions Stack usage with code bankswitching m Add 3 Bytes to each fast task stack for the bankswitch handling m Standard tasks use no extra stack space for the bankswitching RTX 51 RTX 251 39 Chapter 4 Programmer s Reference RTX 51 251 and the application built on it are linked with each other via a C51 C251 compatible procedural interface This interface provides all functions for managi
25. End E hh mm ss set end time I n U 4 4 n include lt reg517 h gt special function registers 80517 include lt rtx51 h gt RTX 51 functions amp defines include stdio h standard I O h file include lt ctype h gt character functions include lt string h gt string and memory functions extern getline char idata char external function input line extern serial init external function init serial T define INIT 0 task number of task init define COMMAND 1 task number of task command define CLOCK 2 task number of task clock define BLINKING 3 task number of task blinking define LIGHTS 4 task number of task signal define KEYREAD 5 task number of task keyread define GET_ESC 6 task number of task get escape define CAR DET1 7 task number of task car detl define CAR_DET2 8 task number of task car det2 struct time structure of the time record unsigned char hour hour unsigned char min minute lp unsigned char sec second struct time ctime 12 0 0 storage for clock time values RTX 51 RTX 251 261 struct time start 7 30 0 storage for start time values struct time end 18 30 0 storage for end time values unsigned char keypressedl status flag pedestrian button 1 unsigned char keypres
26. Insignificant if no wait for time out is specified unsigned int xdata message Address of buffer 2 bytes in XDATA space where received message shall be stored Insignificant if no wait for message is specified 81 Description Send a token to semaphore This is the general wait function of RTX 51 251 Any combination of events may be selected If one of the specified events occurs then task is made ready again i e waiting for events is terminated For details see separate chapter about os wait 82 Programmer s Reference os send token Task function The system operation os send token sends one or more tokens to semaphore Prototype Parameter Return Value See Also Example signed char os send token unsigned char semaphore semaphore is the number of the desired semaphores Permissible values are 8 15 OK Token was sent successfully NOT OK Function not completed successfully One of the following exceptions was determined m Specified semaphore does not exist m Semaphore contains already a token os wait include lt rtx51 h gt Use rtx251 h for RTX 251 void userapp_task5 void task 5 priority 3 We send a token to semaphore 14 if os send token 14 Token could not be sent to semaphore exception handling RTX 51 RTX 251 83 Memory Management Function Call Overview Available functions are Function Name Parameter Descrip
27. Mailboxes e D EET 28 DSEMAP HOLES rian EP 30 Dynamic Memory Management eee eee eee 31 Generate Memory PoOl ie 32 Request Memory Block from Pool nenne 32 Return Memory Block to Pool 32 Time Management toute idee re eO pe e eere ede 32 Set Lime S685 des eed eee rte mee tee 33 Delay RT eden etin eo eve eee eee eiie een 33 Cychlic Task Activatiofi 2 eie eeten tet ertet LED e tete tet Atene teat 33 Specific C51 C251 Support nandi iddio 33 RTX 51 RTX 251 vii C51 C25 1 Memory Models 04 pei ue eie Re 33 Reentranit FUnetoris eie beet DR IR EDDA 34 Floating Point Operations nennen nennen enne enne 34 Use of the C51 C251 Runtime Library eene eene 35 Register Bank Default 1 0 iii Li eee 36 Use of the C51 Special Library i iii ii 36 Code Banks wit Chins 22 2 2 tt er Eee ete ER Er eee e ER REY 37 Chapter 4 Programmer s Reference eee eeee esee reete eee see neeseonenseneone 39 Name Conventions ss oir OA E ERE REP a 39 Return Values E 40 INCLUDE Elles n e ca E UHR REUS LT DAME EAS 40 OVervVieW 2x nadie e er AEQ EREMO AI EE EDI RI AE PvE eA de 40 Imtiahze and Start the System eee ette eR pe ER IR RSS 42 Function Call Overview Fask Management t5 M OR RH OR RA EM E Function Call Overview Interrupt Management iet eere TR SZT eR SER REOR ESAE EU ERA Function Call Overview Wait Function e DDR e E
28. NB and LOOP may be set according to the specific application for details see 8044 manual m bbs en sig to app bbm en sig to app Flag to control the sending of a signal to task bbs rx tid bbm rx tid when a message has been received If a signal has to be sent then this flag can be initialised to 1 and does not have to be changed during operation Parameter used only by a slave station m bbs station addr This is the address of the slave within the BITBUS network A slave address must be unique and may be in the range of 1 to 250 0 is used by the master 251 to 255 are reserved by the Intel BITBUS specification Parameter used only by a master station m bbm timeout This is the maximum time to wait for a response frame from the slave after a frame has been sent The number in bbm timeout is in units of the RTX 51 system tick Standard value according to the BITBUS specification is 10 ms define a RTX 51 system tick of 10 ms and a TIMEOUT of 1 RTX 51 RTX 251 249 The initialisation has to be performed prior starting the BITBUS communication task The rest of the BITBUS communication variables are initialised by the communication task itself Application Examples Example 1 Initialisation m Illustrates the initialisation for a slave BITBUS communication m Theinitialisation must be executed before messages are sent or received include lt rtx51 h gt include bbs_rtx h void init example void task INIT
29. TS2 1 fscl 2 1 fscl 3 0 000125 0 000375 mS Bit Length Register 2 IPOL DI SIM SJW 1 SJW 2 0 0 0 0 0 0 1 0 02H SJWidth SJW 1 fscl 2 1 fscl 0 000375 mS Bit length fbl TSEG1 TSEG2 1 fscl 0 0005 0 000375 0 000125 0 001mS Baud rate BR ferystal 2 BRP 1 TS1 TS2 3 16000 2 0 1 3 2 3 1000 kHz 208 CAN Support Philips 82C200 80C592 Bus Timing Only a few differences exist between the bus timing calculation for the Intel and Philips CAN controller The two controllers are fully communication compatible however when the baud rate is programmed the same 82C200 80C592 Bit Time Calculation 2 Baud rate prescaler 1 1 BTL Cycle terr crystal Bit Cycle terr INSYNC TSEGI TSEG2 terr f crystal Baud rate 2 Baud rate prescaler 1 INSYNC TSEGI TSEG2 1 terr Variation in baud rate due to resynchronisation 1 MAX Baud rate terr SJW2 teri 1 MIN Baud rate terr SIWI terr Programming the Philips 82C200 80C592 Function CAN HW INIT allows the CAN controller bus timing to be programmed The parameters refer to 82C200 hardware registers in the following way BUS TIMING 0 Bus timing register 0 BUS TIMING 1 Bus timing register 1 RTX 51 RTX 251 209 SYNCON SPEED MODE bit in the control register Bus Timing Register 0 MSB SJW B Synchronisation Jump Width SJ
30. and number of tasks which are waiting to store a message write task cnt Return Value OK 0 Function executed successfully NOT OK 1 The function could not be executed See Also os check mailbox Example include lt rtx51 h gt Use rtx251 h for RTX 251 void xyz task void task 0 priority 0 t rtx allmbxtab xdata table RTX 51 RTX 251 99 if os check mailboxes amp table error handling Evaluation of the table 100 Programmer s Reference os_check_mailbox Task function The system operation os_check_mailbox returns detailed information about the state of a certain mailbox The information is stored in a table in XDATA memory to be declared by the user Prototype signed char os_check_mailbox unsigned char mailbox t_rtx_onembxtab xdata table Parameter mailbox is the identification of the desired mailbox Values between 0 and 7 are allowed according to the eight predefined mailboxes table points to a table in XDATA memory which was declared by the user The system call stores the determined information in this table The table contains the following structure defined in RTX51 H RTX251 H typedef struct unsigned char message cnt unsigned char read task cnt unsigned char write task cnt unsigned char wait tasks 16 unsigned int messages 8 t rtx onembxtab The following is allocated for the desired mailbox the three count values for number of
31. os free block Task function The system operation os free block returns a memory block to the associated pool After calling this function the calling task must not execute any more operations in this memory block Prototype signed char os free block unsigned int block size void xdata block Parameter block size is the actual block size A pool must exist which contains the blocks of the required size block designates the returned block Return Value OK 0 Block was returned correctly NOT OK 1 Block could not be returned One of the following exceptions occurred m Invalid block address m Block was never referenced with os get block See Also os create pool os get block os check pool Note The system operation os free block has limited capabilities to detect wrong block addresses Because of this a return value of OK may be returned even if an invalid block address was specified Example include lt rtx51 h gt Use rtx251 h for RTX 251 void pool task void task 0 priority 0 int xdata new ptr Request an element if new ptr os get block 2 0 error handling Assign value 3291 to the received block new ptr 3291 90 Programmer s Reference A esrb further processing Return block depending on application to pool os free block 2 new ptr RTX 51 RTX 251 91 Management of the System Clock Function Call Overview Ava
32. see the data sheet for details bit_length_2 CAN controller bit length 2 register see the data sheet for details sleep_br_prsc CAN controller bit0 bit5 baud rate prescaler register bit6 SME Sleep Mode Enable bit of control register see the data sheet for details clock_control CAN controller clock control register sets the output frequency at the pin CLK Bit_timing_0 CAN controller bit timing 0 register Bit_timing_1 CAN controller bit timing 1 register C_OK Hardware initialisation finished C_CONF_ERROR Impossible bus timing or not allowed parameter value C_CAN_FAILURE General errors with the CAN controller Bus timing calculation examples can be found in the chapter Timing Initialisation below The CAN controller clock divider register for the CLKOUT pin can be written directly by the application Philips 82C200 or 80592 include lt rtxcan h gt Init the CAN communication controller for a baud rate of 50Kbauds s CAN controller with 16 MHz clock Baud rate prescaler 19 G INSYNC 1 A TSEG2 3 RTX 51 RTX 251 143 SJW1 SJW2 4 SAMPLING 1 three samples bit taken SYNCH Mode 1 transitions from recessive to dominant and vice versa ifs are used for resynchro nization 3 27 tBTL 2 1941 16 MHz 2 41s 1 bit cycle 1 4 3 2 51s 20 us Baud rate 16 MHz 2 19 1 8 50 Kbits s
33. unsigned char task number Identification number of task t rix onetasktab xdata table Address of a memory area where atask state table can be stored t rix allmbxtab xdata table Address of a memory area where a mailbox state table can be stored unsigned char mailbox Identification number of mailbox t rix onembxtab xdata table Address of a memory area where a mailbox state table can be stored t rix allsemtab xdata table Address of a memory area where a semaphore state table can be stored unsigned char semaphore Identification number of semaphore t rix onesemtab xdata table Address of a memory area where a semaphore state table can be stored unsigned int block size Identification of pool size of blocks contained in it t rix blockinfo xdata table Address of a memory area where a pool state table can be stored 93 Description Extracts task state information from RTX System data This data is stored at a user declared memory area Extracts detailed status information about a particular task from RTX system data This data is stored at a user declared memory area Extracts mailbox state information from RTX system data This data is stored at a user declared memory area Extracts detailed status information about a particular mailbox from RTX system data This data is stored at a user declared memory area Extracts semaphore state information from RTX system data This dat
34. 0 task code void first task void task 0 priority 0 Function count task is started as a task if os create task 2 error handling RTX 51 RTX 251 47 void main void if os_start_system 0 error handling 48 Programmer s Reference os_delete task Task function The system operation os_delete_task stops a task and removes it from all system lists Releases all operating resources assigned to the task Prototype Parameter Return Value See Also Note Example signed char os_delete_task unsigned char task_number task_number identifies the task to be deleted The same number is to be used which was used in the task declaration Only tasks which were created with os_create_task can be deleted The running task can also stop itself OK 0 Task was stopped successfully NOT OK 1 The designated task was never created with os create task os create task os check task os check tasks If the calling task specifies itself as a task to be deleted a task switching to the next READY task subsequently occurs include rtx51 h Use rtx251 h for RTX 251 void first task void task 0 priority 0 task code void main void Task stopped itself if os delete task 0 error handling RTX 51 RTX 251 49 os running task id Task function The system operation os running task id returns the task numb
35. 186 CAN Support Siemens C515C 10MHz Clock BIT TIMINGO BIT TIMINGI and BRP are the relevant parameters for this CAN controller Baud Rate BRP SJW TSEG1 TSEG2 BIT BIT Kbit s TIMINGO TIMING1 Bit Timing A bit time is subdivided into a certain number of BTL cycles This number results from the addition of segments SJW1 TSEG1 TSEG2 and SJW2 plus general segment INSYNC see Figure 2 One Bit Time TSEGI One BTL Cycle Time Sample Point Transmit Point Figure 16 Bit Timing intel 82526 and Philips 82C200 80592 RTX 51 RTX 251 One Bit Time SYNC SEGI TSEGI TSEG2 One BTL Cycle Time Sample Point Transmit Point Figure 17 Bit Timing intel 82527 INSYNC SJW1 and SJW2 TSEGI The incoming edge of a bit is expected during this state This segment corresponds to one BTL cycle Synchronisation jump widths are used to compensate for phase shifts between clock oscillators of different bus nodes Both segments SJW1 and SJW2 determine the maximum jump width for resynchronisation and are programmable from 1 to 4 BIL cycles The width of SJWI is increased to twice the programmed width max during resynchronisation The width of SJW2 is reduced or cancelled to shorten the bit time during resynchronisation Resynchronisation can be performed on both edges of the bus signal recessive to dominant and dominant to recessive or on the recessive to dominant edge only depending
36. 34 Register Bank 36 Runtime Library 35 Special Library 36 C51 Support 33 CAN Interface can def obj 145 147 can get status 169 can hw init 139 can read 167 can receive 155 can request 165 can start 150 can stop 149 can task create 138 can unbind obj 160 can wait 161 can_write 153 CAN MESSAGE STRUCT 151 153 155 161 167 CLKOUT 141 Clock Divider Register 141 Configurable Values 126 Configuration 109 Constants 171 File 170 Hardware 170 Utility 109 Controller Status 169 Data Reception 237 Transmission 236 DBG RTX INC 260 Debug Functions 98 102 Debug Functions Overview 93 dScope 51 245 E PROTOCOL ERROR 242 Example 245 Examples Bitrate Configuration 175 Compiling and Linking 209 214 220 224 Simple Application 207 Full CAN 132 Function Calls can bind obj 158 can send 151 Differences 137 Glossary 262 Hardware configuration 170 Header File 135 Index 265 Initialization 238 Functions 44 Installation 11 Interrupt Connection 170 Enable Register 25 External 170 Functions 24 26 Handling 23 Management 22 Overview 50 Priority Register 26 INTERRUPT ENABLE bits 126 Introduction 1 ISR defined 262 L251 11 Mailbox 28 230 Lists 29 Overview 74 Read Message from 30 Send Message to 29 Memory Assignement 116 Assignement for RTX 251 121 DATA for RTX 251 121 DATA for RTX 51 116 EDATA for RTX 251 121 Example 83 IDATA for RTX 51 117 Management 31 Mapping 170 Pool 32 Pool Overview 83 Request from Po
37. A51 A251 The following adaptations can be made in the configuration files CONTROLLER_BASE for 82526 and 80C200 same definition for the Intel Philips and Siemens CAN controller Defines the start address of the CAN controller in the microcontroller XDATA space An arbitrary value between 0 and FFFFH may be used USED CAN INT NBR for 82526 and 80C200 same definition for Intel Philips and Siemens CAN controller Defines the interrupt source for the CAN controller The constant has the same definition as in RTX 51 251 see RTX 51 251 function call os attach interrupt OBJ BUFFER LENGTH only for the Philips CAN controllers Defines the number of bytes for the object buffer The object buffer will be allocated in the XDATA space of the microcontroller The first object occupies 28 bytes each further object occupies 14 bytes from the buffer With an object buffer length of 28 bytes 1 object can be defined With a length of 42 bytes 2 objects can be defined With a length of 56 bytes 3 objects can be defined RTX 51 RTX 251 181 Memory System Requirements System utilising the Intel 82526 82527 and 81C90 91 CAN controller 4 6 Kbytes code 256 bytes XDATA space for the CAN controller hardware One bit internal RAM for RTXCAN x51 system variables 220 byte XDATA RAM for system variables RTX 51 251 mailbox number 7 and a fast task Number 3 for RTX 51 with the task number 0 are employed by the CAN communicati
38. BRP 5 Baud Rate Prescaler BRP 4 BRP 3 BRP2 BRP 1 LSB BRP 0 Baud Rate Prescaler BRP The valid programmed values are 0 63 The baud rate prescaler programs the length of one time quantum as follows tq tSCLLK BRP 1 BRP 2 BRP5 2 BRP4 2 BRP3 2 BRP2 2 BRP1 BRPO Synchronisation Jump Width SJW The synchronisation jump width defines the maximum number of BTL cycles that a bit may be shortened or lengthened by one resynchronisation during transmission of a data frame or remote frame Synchronisation jump width is programmable by bits SJW B and SJW A as depicted in the following table SJW B SJW A SJW 1 SJW 2 1 BTL cycle 2 BTL cyles 3 BTL cycles 4 BTL cycles RTX 51 RTX 251 197 Bus Timing Register 1 SAMPLE TSEG 2 2 Time Segment 2 TSEG 2 1 TSEG 2 0 TSEG 1 3 Time Segment 1 TSEG 1 2 TSEG 1 1 TSEG 1 0 MSB LSB SAMPLE This determines the number of samples of the serial bus which are made by the CAN controller IF SAMPLE is set to low a bit is sampled once If SAMPLE is set to high three samples per bit are made SAMPLE 0 allows higher bit rates whereas SAMPLE 1 provides better rejection to noise on the bus SAMPLE is not recommended at bit rates over 125 Kbits s Time Segment 1 and Time Segment 2 TSEG1 TSEG2 TSEGI and TSEG2 are programmable as illustrated in the tables below 1 BTL cycle 2 BTL cycle 3 BTL cycle 4 BTL cycle 16 BTL
39. Input signal is sampled three times per bit Zero Input signal is sampled once per bit Note Bit SAM should only be set to 1 using very low baud rates TS2 2 TS2 0 Length of segment 2 TSEG2 TSEG2 TS2 1 fscl TS1 3 TS1 0 Length of segment 2 TSEGI TSEGI TSI 1 fscl RTX 51 RTX 251 203 Bit Length Register 2 MSB IPOL Input polarity 6 DI Digital Input 2 SM Speed mode a SJW 1 Maximum synchronisation jump width SR o suwo SJW 1 SJW 0 Maximum synchronisation jump width SJWidth SJW 1 fscl SM Speed mode Determines which edges are used for synchronisation One Both edges are used Zero Recessive to dominant is used Note According to CAN specification this bit should not be set to 1 DI Digital input One The input signal on pin RXO is evaluated digitally The input comparator is inactive Pin RX 1 should be on Vss Zero The input signal is applied to the input comparator IPOL Input polarity One The input level is inverted Zero The input level remains unaltered 204 CAN Support Output Control Register MSB OCTP 1 OCTN 1 OCP 1 OCTP 0 OCTN 0 OCP 0 OCM 1 OCM 0 LSB Output modes OCM 1 OCM 0 Output mode Normal mode TXO Bit sequence TX1 Bit sequence Test mode TXO Bit sequence TX1 RXO Clock mode TXO Bit sequence TX1 Bit clock RTX 51 RTX 251 205 Output programming OCTP x OCTN x OCP x Data Txx Level 0 dominant o
40. KK KKH HK e e he he he KKK ke kk kk ke he he he he IK KK ke kk e ke e de e KIKI KK KKK KKK eek f void main void t os start system INIT start the first task SERIAL C BRR RIKKI KK AAA AIA AIA AAA AAA AIA e e he he AIA de KK He AAA AIA IK KKK KKK KKK AAA AAA AAA e e eek f A SERIAL C Interrupt Controlled Serial Interface for RTX 51 Jo A Coke ke ke ek e ke he he he IKK KKK HK e e e he he hehehe ke KK ke kk khe he he he ke KK KKK ke e He e de e He He He He He He He de e e eek f pragma CODE DEBUG OBJECTEXTEND include reg52 h special function register 8052 include lt rtx51 h gt RTX 51 functions amp defines define OLEN 8 size of serial transmission buffer unsigned char ostart transmission buffer start index unsigned char oend transmission buffer end index idata char outbuf OLEN storage for transmission buffer unsigned char otask Oxff task number of output task define ILEN 8 size of serial receiving buffer unsigned char istart receiving buffer start index unsigned char iend receiving buffer end index 268 Glossary idata char inbuf ILEN storage for receiving buffer unsigned char itask Oxff task number of output task define CTRL_Q 0x11 Control Q character code define CTRL_S 0x13 Control S character code bit sendfull flag marks transmit buffer full bit sendactive flag marks transmitter act
41. Several tasks are time and logic independent from one another and should therefore execute simultaneously on a processor System ISR s The first item is also referred to as a requirement for guaranteed response RTX Kernel times also designated as real time The second item designates the typical situation of multi program operation multiprogramming multi tasking In this case the individual tasks are organized as independent computer processes normally designated as a task System Tasks noe Tasks The RTX 51 251 Real Time User ISR s Multitasking Executive contains the functions to solve these types of x problem definitions in a simple and Figure ido Overview effective way with all processors of the 8051 MCS 251 processor family The sequence control required for simple applications could of course be implemented by the user himself This however is not very efficient since a large part of the functions which a multitasking executive already offers would have to be re implemented Advantages in using a Real Time Multitasking Executive m A program can be more easily implemented tested and maintained by breaking down the problem to be solved into individual easily comprehensible tasks m The modular approach allows individual tasks to be used in other projects m Since the real time and multitasking problems which occur are already solved the time required for creating programs and testing is considera
42. accuracy in this manual and to give appropriate credit to persons companies and trademarks referenced herein 06 04 99 RTX 51 RTX 251 iii Preface RTX 51 is a runtime library that together with C51 allows real time systems to be implemented for all processors of the 8051 family e g 8051 8052 80515 etc except for the 8 C751 and 8 C752 RTX 251 extends the functionality of the RTX 51 to the new intel MCS 251 family of processors It is available as a set of runtime libraries supporting the binary and the source mode to be used with the C251 This user s manual assumes that the user is familiar with the programming of 8051 MCS 251 processors experienced with the KEIL C51 C251 high level programming language and has basic knowledge of real time programming The following literature is recommended as an extensive introduction in the area of real time programming a Deitel H M Operating Systems second edition Addison Wesley Publishing Company 1990 contains many additional literature references and is praxis orientated Ripps David A Guide to Real Time Programming Englewood Cliffs N J Prentice Hall 1988 a Allworth S T Introduction to Real Time Software Design Springer Verlag Inc New York m Richter Lutz Betriebssysteme Teubner Stuttgart 1985 theoretical view german language m Goldsmith Sylvia A practical guide to Real Time Systems Development Prentice Hall iv Preface Man
43. another operation In order to guarantee this certain precautionary measures must be assured No restrictions apply in the use of floating point operations in the following two cases m Only one task with optional priority in the system executes floating point operations Since no other task executes floating point operations a running operation cannot be interrupted by another m Only tasks with the priority 0 execute floating point operations If no round robin scheduling is used no problems occur since the tasks cannot mutually interrupt When the round robin scheduling is used the task change during floating point operations is delayed up to the end of the operation see scheduling rules If several tasks assigned to different priorities use floating point operations the standard C51 functions fpsave and fprestore must be used see C51 documentation In this case the present state of an interrupted floating point operation must be stored with fpsave prior to floating point operations After the operation the state must be restored again with fprestore same as using floating point operations in interrupt functions for C51 programs without RTX 51 If fpsave is called then no RTX function is to be called until the function fprestore is executed i e no RTX functions are allowed between fpsave and fprestore m The use of floating point operations is unproblematic only in one task or exclusively in t
44. be set to one to activate the VCC 2 reference voltage Zero RXO is enabled and the RXO input is connected to the non inverting input of the input comparator CPU Interface Register MSB RstSt DSC DMC PwD Sleep MUX 0 Cen LSB Hardware reset status RstSt One The hardware reset of the 82527 is active RESET is low While reset is active no access to 82527 is possible Zero Normal operation the CPU must insure this bit is zero before the first access to the 82527 after reset is done This bit is written by the 82527 200 CAN Support Divide system clock DSC The SCLK may not exceed 10 Mhz One The system clock SCLK is equal to XTAL 2 Zero The system clock SCLK is equal to XTAL This bit is written by the CPU Divide memory clock DMC The memory clock may not exceed 8 MHz One The memory clock MCLK is equal to SCLK 2 Zero The memory clock MCLK is equal to SCLK This bit is written by the CPU Power down mode enable PwD and Sleep mode enable Sleep PwD Sleep Zero Zero Both Power Down and Sleep Mode are not active one Zero Power Down Mode is is active Zero one Sleep Mode is active This bit is written by the CPU Multiplex for ISO Low Speed Physical Layer MUX If VCC 2 is used to implement the basic CAN physical layer pin 24 provides the voltage output VCCC 2 and pin 11 is the interrupt output transmitted to the CPU Otherwise only the interrupt is available on pin 24 VCC
45. being used by RTX 51 fast tasks RTX 251 fast tasks use register bank 0 m Without Register Bank Switching If no using attribute is used all registers required are saved on the stack This produces longer run times and increased stack requirement for this purpose register banks used by RTX 51 251 may also be used RTX 51 RTX 251 27 m C51 C251 interrupt functions with using attribute must never use register bank 0 or one of the register banks used by a RTX 51 fast task m C51 C251 interrupt functions without using attribute can be used without any restrictions if enough stack is available Task Communication The individual tasks within a real time system can be dependent upon each other in various ways These can use common data exchange information with each other or coordinate the activities for solving tasks RTX 51 251 provides the mailbox and signal concept for handling these types of task related jobs Signals Signals represent the simplest and fastest form of task communication These can always be used when a pure task synchronisation is required without data exchange Each active task contains its own signal flag with which the following operations can be executed m Wait for a signal m Send signal m Clear signal The task number see section section Task Declaration page 20 of the receiver task is used for identifying the signals for the individual operations Wait for a Signal Each task ca
46. bit cycle 1 4 3 2 5ms 20 ms Baud rate 16 MHz 2 19 1 8 50 Kbits s e Variation of bit time due to resynchronisation MAX Baud rate 1 20ms 4 2 5ms 100 Kbauds s MAX Baud rate 1 20ms 4 2 5ms 33 3 Kbauds s A Set output control register to FFH Jes ey can hw init 0xd3 0xa3 0x 1 0 Object definition can def obj 1 8 D SEND can def obj 2 8 D REC Set the RTX 51 system clock to 20 ms 12 MHz clock os set slice 20000 Create the receive task os create task REC TASK Start communication can start 0 0 tl count t2 count Init the send object ts identifier 1 for i20 i lt 7 i ts c data i i for Send an object every 100 ms 218 CAN Support can_send amp ts os_wait K_TMO 5 0 Fill object with new data for i 0 i lt 7 i ts c data i ts c data i 1 tl_count Akkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkx MAIN PROGRAM eek e e e He He He de he he he e e e He He He K e e e e He KKK KKK He e e e He He He He KEKE de e e e He He He He He He He He e e e e ke ke K void main void os start system SEND TASK END of MODULE BCANDEMO Compiling and Linking the Program for the Philips 80C592 c51 exe bcandemo c51 a5l exe cconf592 a51 a5l exe rtxconf a5l BL51 bcandemo obj cconf 592 0bj
47. boards Full compatibility on the layers data link protocol and message protocol ensures communication with stations containing the Intel BEM processor BEM BITBUS Enhanced Microcontroller The BITBUS communication software runs as a task under the RTX 51 Real Time Executive Two versions of the communication task exist RTX 51 BBS for BITBUS slave stations and RTX 51 BBM for BITBUS master stations This user s guide assumes that the reader is familiar with the BITBUS specifications with the 8044 microprocessor and with the RTX 51 Real Time Executive 238 BITBUS Support For detailed information on the BITBUS specification the 8044 microprocessor and the BEM microprocessor see m Distributed Control Modules Databook Intel USA order no 230973 004 m The BITBUS Interconnect Serial Control Bus Specification Intel USA order no 280645 001 BITBUS is a subset of SDLC Serial Data Link Control a serial communication standard defined by IBM Detailed knowledge of SDLC is not required Consult Synchronous Data Link Control Concepts IBM document GA27 3093 3 for more information concerning SDLC Abbreviations Abbreviations used in this document BITBUS Serial communication standard based on SDLC defined by Intel SDLC Synchronous Data Link Control Standard protocol for serial data communication defined by IBM BBS BBM BITBUS Slave BITBUS Master An SDLC network always contains one BITBUS master station a
48. brief overview stating the major points on how to generate a RTX 51 251 application 1 Implement the application using the RTX 51 251 system functions defined in INCLUDE file RTX51 H RTX251 H 2 Compile the individual files like for an application without RTX 51 251 3 Link the application with the BL51 L251 Linker and option RTXSI RTX251 RTX 51 BL51 input list RTX51 RTX 251 L251 input list RTX251 Using the option RTX51 RTX251 library RTX51 LIB RTX251x LIB x S or B for source binary mode is automatically linked to the application Special specifications to locate the RTX 51 251 segments are not necessary These can however be used if desired 4 The application can be tested with standard debugging tools example dScope 51 251 source level debugger The integrated development environment pVision 51 251 may be used to automate these steps Example Program TRAFFIC2 The example program TRAFFIC2 is derived from the example program TRAFFIC written for RTX 51 TINY This example shows how easy a complex task can be solved using RTX 51 251 256 Glossary It is included on the distribution disk together with all files required to build and run the application under dScope 51 251 This example was written for demonstration purposes and may require re working to be applied to the real world The lamp outputs and all inputs are defined in such a way an MCB 517A evaluation board could be easily used to build a
49. buffer to the pool The front end ISR requests a buffer from this buffer pool each time it is activated The implementation of solution 1 with RTX 51 251 is straightforward But for an implementation of solution 2 the fact that an ISR cannot request a buffer from a pool directly seems to be a disadvantage This problem however may be solved easily with RTX 51 251 when the following approach is used m Oneofthe consuming tasks creates a buffer pool by use of os create pool It then requests as many buffers from it as shall be used for data exchange between tasks and the front end ISR It then writes all these buffer addresses to a mailbox by os send message m The front end ISR obtains a buffer by reading a buffer address from this mailbox by isr recv message It then fills in its collected data and sends the buffer reference to a processing task via a different mailbox m The processing task may now modify or consume this data It then passes the buffer reference to another task if further processing is required Or it may return it to the mailbox containing all the free buffer addresses by an os send message RTX 51 RTX 251 85 os create pool Task function The system operation os create pool produces a selectable number of blocks in a memory pool The individual blocks can be referenced or returned again afterwards with the system functions os get block or with os free block respectively The memory ar
50. cycle 198 CAN Support 1 BTL cycle 2 BTL cycle 8 BTL cycle Bus Configuration Register MSB 0 CoBy Pol 0 DCT1 0 DcR1 DcRO LSB Comparator Bypass CoBy One The input comparator is bypassed and the RXO input is regarded as the valid bus input DcRO must be set to zero Zero Normal operation RX0 and RXI are the inputs to the input comparator Polarity Pol One if the input comparator is bypassed then a logical one is interpreted as dominant and a logical zero is recessive on the RXO input Zero If the input comparator is bypassed then a logical one is interpreted as recessive and a logical zero is dominant bit on the RXO input Disconnect TX1 output DcT1 RTX 51 RTX 251 199 One Disables the TX1 output driver This mode is for use with a single wire bus line or in the case of a differential bus when the two bus lines are shorted together Zero Enables the TX1 output driver default after hardware reset Disconnect RX1 input DcR1 One RX1 is disabled and the RX1 input is disconnected from the inverting comparator input and is replaced by a VCC 2 reference voltage Zero RX1 is enabled and the RX1 input is connected to the inverting input of the input comparator Disconnect RX0 input DcRO One RXO is disabled and the RXO input is disconnected from the non inverting comparator input and replaced by a VCC 2 reference voltage The MUX bit is in the CPU Interface register 02H must
51. e KKK e He de He KKK KKK KKK KKK KKK KIRK IKKE e He e He e He de KK He de He KKK KK EK void main void os start system SEND TASK END of MODULE GCANDEMO Compiling and Linking the Program for the Intel 82527 c5l exe gcandemo c51 define EXTEND a5l exe gcanconf a51 a5l exe rtxconf a51 BL51 gcandemo obj gcanconf obj rtxconf obj rtxgcan lib rtx51 ramsize 256 Depending on the CAN controller chip and CPU used above shown sequence has to be modified slightly see examples contained on distribution disk Example 3 Siemens 81C90 91 pragma large pragma debug pragma registerbank 0 pragma pagelength 80 pagewidth 110 RRR KK HK ecce KKK IK IKK KK HH KKK ii hee He e ke eec ec ehe eee e He e He He He KK KKK KKK KK METTLER amp FUCHS AG CH 8953 Dietikon Tel 01 740 41 00 e ke ke e e e ee eee e e ee e ee eee ce ce ce e e e e e e e ce ce e e e ee e e e e ce e ce ce ke ke e e e e ce ce ce ce ke ke e e e ve ke e e e e A A e ke ke e ee e e e ce ee e e e e e e e e ce ce ce ce e e e e e e e ce ce e ee ee e e e e ce ce ce ce ke ke e e e e e ce ce ce ke ke ke e e kv e e e e e A Ax HCANDEMO E A k ke ke ke ke ke ke ke ke ke ke ke e ke k k ke ke k k k k ke k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k kkk kkk kkk kk Ae k ke e ke ke ke ke ke ke ke k ke de ke k ke ke ke k ke k k ke k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k kk kkk kk P
52. e ee e ce ee e ke e e ke x Versionen 17 January 1996 K Birsen Version 0 1 First Version L FF FF XR 00 HF HF X 0X 0X 0 FF F HF F HF X 0X Ae ke ke e He ke ke He ke ke e ke ke de ke ke KK ke ke ke ke ke ke k KEE KEKE ke ke k k KKK k k k k k k k k k k k k k k k k k k k k kkk kkk kkk k all rigths reserved by METTLER amp FUCHS AG CH 8953 DIETIKON eek ke kk kk kk KK KKK e e e e ek ok KK KK KK KKK III KK KKK KK KK KAKA EEEE EEEE EEE E KKK A AK IMPORTS gf ecc2ccacct include lt rtx51 h gt RTX 51 function calls include rtxcan h CAN function calls DEFINES define SEND TASK define REC TASK 1 define REC TASK 2 define REC TASK 3 LJ M A Global variables CAN send and receive data struct can message struct xdata ts 14 struct can message struct xdata tr 14 unsigned char i j done unsigned int nx unsigned int dent unsigned char count 14 BRR ke e H ee ee KK HK KK KK IK he eee ke ke KKK he he de He ke eek KK eee He e He e eee He e He KK KK KK KK KK IK Test Tasks n BRK k e H ee ee KK KKK KKK IK he eee ke ke eee KK KKK KKK KK KK ee e He e eje eee e KK KK KK KK KK KK IK void rec_task_1 void _task_ REC_TASK_1 _priority_ 1 unsigned char i done can bind obj 1 for L wait for Message 1 done can wait Oxff amp tr 1 if done C OK 219 220 CAN Support done can get status if tr 1 identifier
53. equal to 20000 times received Untie the object from the task and terminate the task can unbind obj 220 os delete task REC TASK 172 CAN Support can_request Sends a remote frame for a defined object via the CAN bus The corresponding data frame will be sent to the application in the usual way can wait or can receive Prototype unsigned char can request unsigned int identifier Parameter identifier is the identification as defined in can def obj of the requested object Return Value C OK Remote frame sent C OBJ ERROR Object undefined or object has the wrong type the parameter object type in the function call can def obj does not have the value D REC R SEND C SEND ERROR Remote frame not sent bus access errors this error is an indication that no other node is on the bus C BUS OFF The CAN controller is in the off bus state because it has detected too many errors on the CAN bus restart with can start C CAN FAILURE Unrecoverable CAN error Example include rtxcan h struct xdata can message struct rec mes Define an object with identifier 1200 and with 6 data bytes The object can receive data and send remote frames can def obj 1200 6 D REC R SEND RTX 51 RTX 251 173 Bind object with identifier 1200 to this task can bind obj 1200 for loop forever Request object 1200 send a remote frame
54. for a full message list The parameter can have the following values in this case 0 254 Number of system intervals to be waited for in the case of a full mailbox If the value 0 was specified and the mailbox is already full when the function is called no wait is made conditional waiting 255 Wait until space exists in the mailbox again end less waiting Return Value OK 0 The message was sent to the mailbox successfully NOT OK 1 RTX 51 RTX 251 77 The message could not me sent to a mailbox One of the following exceptions occurred m Task wait list for writing tasks is full this is only possible if more than 16 tasks want to write to the same mailbox m Specified mailbox does not exist wrong mailbox parameter m Time out when waiting for a full message list See Also Os wait isr send message isr recv message os check mailboxes os check mailbox Note timeout 0 If message list is full return value NOT OK is immediately returned timeout 255 Identical to timeout infinite Example include lt rtx51 h gt Use rtx251 h for RTX 251 void producer void task 6 priority 2 int data data 0x1250 Send data in the var data to mailbox 3 If the mailbox is already full wait for a maximum of 10 system clock cycles if os_send message 3 data 10 error handling 78 Programmer s Reference isr send message Interrupt Service Ro
55. gt SOFTWARE RTX 51 RTX 251 Real Time Multitasking Executives for the 8051 and MCS 251 Microcontrollers User s Guide 09 97 Keil Software Information in this document is subject to change without notice and does not represent a commitment on the part of the manufacturer The software described in this document is furnished under license agreement or nondisclosure agreement and may be used or copied only in accordance with the terms of the agreement It is against the law to copy the software on any medium except as specifically allowed in the license or nondisclosure agreement The purchaser may make one copy of the software for backup purposes No part of this manual may be reproduced or transmitted in any form or by any means electronic or mechanical including photocopying recording or information storage and retrieval systems for any purpose other than for the purchaser s personal use without written permission Copyright 1988 1996 Keil Elektronik GmbH Mettler amp Fuchs AG and Keil Software Inc All rights reserved Keil C51 and dScope are trademarks of Keil Elektronik GmbH Microsoft MS DOS and Windows are trademarks or registered trademarks of Microsoft Corporation IBM PC and PS 2 are registered trademarks of International Business Machines Corporation Intel MCS 51 MCS 251 ASM 51 and PL M 51 are registered trademarks of Intel Corporation Every effort was made to ensure
56. has to be entered in a hexadecimal representation IE Initialization Value Enter here the initial value for the IE register RTX 51 sets all unused ENABLE bits to 0 in the INTERRUPT ENABLE masks of the processor For some 8051 processors certain bits of the INTERRUPT ENABLE masks are used for purposes other than to enable disable the interrupt sources e g for 80515 the watchdog start bit in the IEN1 register The respective initial value of these types of special bits can be defined using this constant Note that this number has to be entered in a hexadecimal representation RTX 51 RTX 251 115 IENI Initialization Value Enter here the initial value for the IEN1 register RTX 51 sets all unused ENABLE bits to 0 in the INTERRUPT ENABLE masks of the processor For some 8051 processors certain bits of the INTERRUPT ENABLE masks are used for purposes other than to enable disable the interrupt sources e g for 80515 the watchdog start bit in the IEN1 register The respective initial value of these types of special bits can be defined using this constant Note that this number has to be entered in a hexadecimal representation IEN2 Initialization Value Enter here the initial value for the IEN2 register RTX 51 sets all unused ENABLE bits to 0 in the INTERRUPT ENABLE masks of the processor For some 8051 processors certain bits of the INTERRUPT ENABLE masks are used for purposes other than to enable disable the interru
57. input 1 DcRO Disconnect RX0 input 0 wf RstSt Hardware reset status 0 EA DSC Divide system clock 1 DMC Divide memory clock 0 PwD Power down mode enabled 0 Sleep Sleep mode enable 0 E MUX Multiplex for ISO low speed physical layer 0 Cen Clocckout enable 1 Baud rate XTAL DSC 1 BRP 1 3 TSEG1 TSEG2 Baud rate 16000 1 1 0 1 3 2 Set 1000KHz fs E init for 1000KHz Baud 27 can Bus freq XTAL DSC 1 BRP 1 3 TSEG1 TSEG2 can Bus freq 16000 2 1 8 BTRO BTR1 BUS_CONFIG CPU_IF dummy done can hw init 0x80 0x23 Ox5E 0x41 00 done can get status Receive Objects definitions done can def obj 1 8 D REC done can get status dones can def obj 2 8 D REC done can get status done can def obj 3 8 D REC done can get status done can def obj 4 8 D REC done can get status dones can def obj 5 8 D REC done can get status Send Objects definitions dones can def obj 6 8 D SEND done can get status done can def obj 7 8 D SEND done can get status dones can def obj 8 8 D SEND done can get status dones can def obj 9 8 D SEND done can get status 222 CAN Support dones can def obj 10 8 D SEND done can get status done can def obj 11 8 D SEND done can get status load send identification a
58. interrupt vector at address 8 interrupt 3 The vector number which is permissible depends on the microcontroller type used from the 8051 MCS 251 family RTX 51 251 checks whether the specified interrupt is supported by the microcontroller used see configuration The standard 8051 microcontroller supports the following vector numbers 0 External 0 interrupt 1 Timer counter 0 interrupt can be reserved for the system clock 2 External 1 interrupt 3 Timer counter 1 interrupt can be reserved for the system clock RTX 51 RTX 251 53 4 Serial port Different processor versions of the 8051 MCS 251 family may support additional interrupt sources see literature of chip manufacturer Return Value OK 0 Function executed successfully NOT_OK 1 Function not executed one of the following errors was determined m Vector number does not exist for this processor type m The interrupt source requested was already assigned to another task m Interrupt is already used by a C51 C251 interrupt function m Interrupt is used by the system clock See Also os detach interrupt os wait Note More than one interrupt may be assigned to a particular task It is not allowed however to assign a particular interrupt source to more than one task Example include rtx51 h Use rtx251 h for RTX 251 void count task void task 2 priority 0 Assign external 0 interrupt to this task if os attac
59. message 7 number of bytes in files PARMS BUFFER FULL lt 1 Jfstation is a master write slave address into NODE All the other fields requested by the Message Protocol ROUTE NODE TASKS CMD RSP have to be set according to the BITBUS standard 2 Write start address of message buffer into mailbox 7 As soon as the BITBUS communication task has sent the message successfully i e receiving station RTX 51 RTX 251 247 confirmed the receipt of the message it clears the flag BUFFER_FULL This releases the message buffer for the next message If the sending station is the master and if it could not transmit the message successfully to the requested slave station the message is returned as an error message to the application through the receiver buffer BBx_RX_BUF The contents of the error message is the same as the transfer message except the field CMD RSP is setto E PROTOCOL ERROR When the BITBUS task has written the error message into BBx_RX_BUF it clears BUFFER FULL marking the transmission buffer empty Receipt of Messages The BITBUS communication task requires an application task which reads the received messages This task is triggered when a message is ready Received messages are written into the buffer bbs rx buf bbm rx buf which is declared in external RAM by the BITBUS communication task A maximum of two received messages may be pending at any time one in bbs rx buf bbm rx buf and one in the internal bu
60. message can represent the actual data to be transferred or the identification of a data buffer defined by the user In comparison to the signals mailboxes are not assigned a fixed task but can be freely used by all tasks and interrupt functions These are identified with a mailbox number Mailboxes allow the following operations m Senda message m Reada message RTX 51 RTX 251 29 Mailbox Lists Each mailbox internally consists of three wait lists The user does not have direct access to these lists Knowledge of their functions is however an advantage for understanding mailbox functions Wait lists can comprise the following states in operation State Description Message List Write Wait List Read Wait List No messages empty empty empty no wait tasks No messages empty empty not empty tasks exist that want to read Messages exist not empty empty empty no wait tasks Message list is full not empty empty tasks exist that want to write The three lists do have the following functions 1 Message list List of the messages written in the mailbox These comprise a maximum of eight messages 2 Write wait list Wait list for tasks which want to write a message in the message list of the mailbox maximum 16 tasks 3 Read wait list Wait list for tasks which want to read a message from the message list of the mailbox maximum 16 tasks All three lists are implemented as a FIFO queue First In First Out w
61. object will also be as prototype defined unsigned char can def last obj unsigned long last msg mask unsigned char data length unsigned char can def last obj ext unsigned long last msg mask unsigned char data length unsigned char can read last obj void xdata buffer ptr unsigned char can bind last obj void unsigned char can unbind last obj void In all other CANs the use of define EXTEND is not allowed RTX 51 RTX 251 235 Files Delivered All files are located in the CAN sub directory of the C51 C251 tools directory Libraries RTXBCAN LIB Library for the Philips 82C200 CAN controller Basic CAN RTXFCAN LIB Library for the Intel 82526 CAN controller Full CAN RTXGCAN LIB Library for the Intel 82527 CAN controller Full CAN RTXHCAN LIB Library for the Siemens 81C90 91 CAN controller Full CAN RTXICAN LIB Library for the Siemens C515C CAN controller Full CAN CANP592 LIB Library for the Philips 80C592 microcontroller with integrated CAN interface Basic CAN Configuration files BCANCONF AS1 Configuration file for the Philips 82C200 CAN controller FCANCONF AS1 Configuration file for the Intel 82526 CAN controller GCANCONF AS1 Configuration file for the Intel 82527 CAN controller HCANCONF A51 Configuration file for the Siemens 81C90 91 CAN controller ICANCONF A51 Configuration file for the Siemens C515C CAN controller CCONF592 A51 Configuration file for the Philips 80C592 I
62. of a certain task 1 e a signal possibly stored for the task is cleared This function is primarily intended for creating defined output states Prototype signed char os clear signal unsigned char task number Parameter task number is the identification of the task whose signal flag state is to be cleared Return Value OK 0 Signal flag was cleared successfully NOT OK 1 Function was not executed The specified task does not exist See Also os wait os send signal isr send signal Example include lt rtx51 h gt Use rtx251 h for RTX 251 void xyz task void task 89 priority 0 task code Clear signal from task 19 os clear signal 19 RTX 51 RTX 251 73 isr send signal ISR Function A C51 C251 interrupt function sends a signal to a task If this task is already waiting for a signal then it is made READY again by this Otherwise the signal is stored in the signal flag of the addressed task Prototype signed char isr send signal unsigned char task number Parameter task number is the identification of the task to where a signal is to be sent Return Value OK 0 Signal was sent successfully NOT OK 1 No signal was sent The specified task does not exist See Also os wait os send signal os clear signal Example include rtx51 h Use rtx251 h for RTX 251 void fast int void interrupt 7 using 1 C51 C251 int function wait for int 7 Uses regist
63. or later m RTX 51 Real Time Executive Version 5 10 or later RTX 251 m C251 Compiler Version 1 20 or later m L251 Linker Version 1 20 or later m A251 Assembler Version 1 20 or later m RTX 251 Real Time Executive Version 1 0 or later Backing Up Your Disks We strongly suggest that you make a backup copy of the installation diskettes using the DOS COPY or DISKCOPY commands Then use the backup disks to install the software Be sure to store the original disks in a safe place in case your backups are lost or damaged 12 Installation Installing the Software RTX 51 251 come with an installation program which allows easy installation under MS WINDOWS The following versions are supported m MS WINDOWS Version 3 1 m MS WINDOWS Version 3 11 m MS WINDOWS 95 or later m MS WINDOWS NT Version 3 5 or later To install RTX 51 RTX 251 m Insert the first product diskette into Drive A m Select the Run command from the File menu in the Program Manager m Enter A SETUP at the Command Line prompt m Select the OK button Then follow the instructions displayed by the installation program NOTE m Under Windows 95 or NT a slightly different procedure may be required m The PK51 PK251 product must be installed before installing RTX 51 251 Directory Structure The installation program copies the RTX 51 251 files into sub directories of the PK51 PK251 base directories After creating the appropriate directory if
64. out If a task is waiting for an event e g interrupt message from mailbox or signal it is often desired to reactive a task despite this after completion of a certain time in the case this event does not occur This time limit is referred to as a time out Similar to this activating of a task after completion of a set time is referred to as a time out time out event is perhaps more exact RTX 51 RTX 251 Index a synchronous defined 262 RTX FLT BITSEG 117 121 IRTX FTASKCONTEXT 1 120 RTX FTASKCONTEXT 2 120 RTX FTASKCONTEXT 3 120 RTX FTASKDATA 118 RTX FTASKDATA 2 117 RTX FTASKDATA 3 117 RTX INT MASK RTXCONF 117 121 RTX PBP 117 RTX PBP 121 RTX RTX AUX PAGE 119 124 RTX RTX BT RELBYTE S EG 117 121 RTX RTX BIT SEG 117 121 RTX RTX MBX PAGE 119 124 RTX RTX SEM PAGE 119 124 RTX RTX SYS PAGE 119 124 IRTX TASKCONTEXT x 119 RTX USER NUM TABLE S 119 124 RTX CPU TYPE 126 RTX EXTRENTSIZE 119 120 RTX EXTSTKSIZE 119 RTX INTSTKSIZE 117 118 RTX STKSIZE 123 STACK 117 118 A251 11 A251 defined 262 A51 11 275 A51 defined 262 application defined 262 argument defined 262 Banked Linker 245 Basic CAN 132 BBM 228 BBM_RTX H 243 BBM_TID 230 BBS 228 BBS_RTX H 243 BBS_TID 230 BEM 227 Bit Time 177 Bitbus Release 2 233 BL51 11 245 BTL Cycles 177 Bus Timing 174 C251 11 C51 11 Code Bankswitching 37 Floating Point Operations 34 Memory Model 33 Reentrant Functions
65. priority 0 t rtx alltasktab xdata table os check tasks amp table 96 Programmer s Reference os_check_task Task function The system operation os_check_task returns detailed information about a certain task The information is stored in a table to be declared by the user Prototype signed char os check task unsigned char task number t rtx onetasktab xdata table Parameter task number is the identification of the task where information is to be returned table is a table which was declared by the user The system call stores the determined information in this table The table contains the following structure defined in RTX51 H RTX251 H typedef struct unsigned char state unsigned int flags t rtx onetasktab state designates the task state K READY Task is READY K RUNNING Task is RUNNING ACTIVE K BLOCKED Task is WAITING BLOCKED K DELETED Task does not exist or is deleted flags contains the signal and all wait flags value 1 gt task waits The individual bits are assigned as depicted below 15 14 1D 12 11 109 8 7 6 5 4 3 2 1 0 I Z 96 daa a SR Signal flag stored signal for task WT Task waits for time out interval WS Task waits for signal RTX 51 RTX 251 97 WI Task waits for interrupt WM WN 00 Task waits not for mailbox semaphore 01 Task waits for semaphore 10 Task waits for message mailbox READ wait list 11 Task waits for room in message
66. red I i yellowl 1 yellow2 0 red 2 1 os_clear_signal LIGHTS keypressedl 0 keypressed2 0 cardetectedl 0 cardetected2 0 os_wait K_TMO 30 0 PHASE 1 dir 1 switch to green dir 2 stick to red allow walk phaseno 1 red 1 0 yellowl 0 green_1 1 stop__2 0 walk 2 1 i os_wait K_TMO 30 0 PHASE 2 dir 1 accept pedestrian button dir 2 accept car detect phaseno 2 265 if signal time over start blinking stop lights E i e wait for timeout 30 ticks Pu x7 wait for timeout 30 ticks x M x os wait K TMO K SIG 250 0 wait for timeout amp signal PHASE 3 dir 1 switch to yellow dir 2 stick to red forbid walk phaseno 3 green 1 0 yellowl 1 stop__2 1 walk 2 0 os wait K TMO 30 0 PHASE 4 dir 1 switch to red dir 2 prepare for green phaseno 4 red 17 7 1 yellowl 0 yellow2 1 os clear signal LIGHTS keypressedl 0 keypressed2 0 cardetectedl 0 cardetected2 0 os wait K TMO 30 0 wait for timeout 30 ticks v 7 x wait for timeout 30 ticks 266 Glossary PHASE 5 dir 1 stick to red allow walk dir 2 switch to green phaseno 5 stop 1 0 walk 1 1 red 2 0 yellow2 0 green_2 1 os_wait K_
67. rtxconf obj canp592 1lib rtx51 ramsize 256 Depending on the CAN controller chip and CPU used above shown sequence has to be modified slightly see examples contained on distribution disk Example 2 intel 82527 pragma large pragma debug pragma registerbank 0 pragma pagelength 80 pagewidth 110 RRR KKK KIKI HK KKK KK IK HK KKK HK IK HK IK HK He He HII He He He He HK He He He HK He He He HK IK HK IK HK IK KKK KKK BRR KKK KKK KK HHH KKK KKK IK IK KK KKK KK KK KIKI KK KKH HK KKK KKK KKK KK KKK KKK KKK KK IK METTLER amp FUCHS AG CH 8953 Dietikon Tel 01 740 41 00 oe ke ke e e ee e e eee ee e e ee e e ce ce ce e e e e e e e e ce ce e e e ke e e e e se ce ce ee ke ke e e e e e ke ce ce ke ke ke e kv kv ke ke ke e x A oe e ke ce e e e e e ee e e ke e e e e ee e ce ce ce e e e e e e e ce ce e e e ke e e e e e ce ce e ce ke ke e e e e e ke ce cce ke ke e ke kv ke ke ke x Ax GCANDEMO KKK KKK KKK KKK KKK KKK RIKKI KKK HK KI HK KKK IKK KKK KKK KKK ke e e e e KKK ke ke k k k KEK KKK KKK KKK KI HK KKK ke e ke ke RIK KKK KKK KI HK KKK IKK RIK He He ke ke ek KEK KKK He ke He ke ke k KKK KEK Purpose Simple demo program for the RTX 51 CAN Interface Y Targetsystem RTX 51 RTX 251 8051 system with Intel 82527 CAN Controller HW specific features resides in the file GCANCONF A51 Filename GCANDEMO C51 3 ke ke ke e ee e ce e e e efe eee ee e ZE ZZZ ZZZ ZZZ ee ee e ce e ee e ce he ce e ee e ce e ce
68. stack space stack grows from lower to higher RTX 51 RTX 251 123 addresses Stack data of task temporary stored data by Push and return addresses of subroutine calls Reserved 2 bytes Figure 11 RTX 251 Task Context Layout task running Size of task context data and saved SPX The system constant RTX REGSIZE indicates how many bytes are required to store a full task context including the stack pointer This constant is declared public and equals to about 32 bytes Its value is given by the context storage scheme and can not be changed by the user Size of task stack area This includes the Stack data of task and the Free stack space as shown in the pictures above Each declared task gets assigned its private context area by C251 L251 Its size is determined by the sum of the two constants 7RTX_REGSIZE and RTX STKSIZE The task stack space can be configured by the user The size in bytes of the task stack area can be defined in the configuration file using the constant 7RTX_STKSIZE It should not be selected smaller than 32 bytes Such an area will be allocated by L251 for each declared task Free stack space stack grows from lower to higher addresses 124 Configuration Stack data of C251 interrupt function temporary stored data by Push and return addresses of subroutine calls Stack data of task temporary stored data by Push and return addresses of subroutine call
69. starts up using an initialization file TRAFFIC2 IND It loads the correct CPU driver 80517 DLL the traffic program TRAFFIC2 and an include file for displaying task status DBG_RTX INC Then it activates watch points for the traffic lights defines functions for the pedestrian buttons and starts the TRAFFIC2 application RTX 51 RTX 251 When dScope 51 251 starts executing TRAFFIC2 the serial window will display the following text T TRAFFIC LIGHT CONTROLLER using C51 and RTX 51 xx This program is a simple Traffic Light Controller Between start time and end time the system controls a traffic light Outside of this time range the yellow caution lamp is blink ing Display D display times Time T hh mm ss set clock time Start S hh mm ss set start time End E hh mm ss set end time 4 4 Command TRAFFIC2 waits for you to enter a command light For example Start Time 07 30 00 Clock Time 12 00 11 As the program runs you can watch the red yellow and green lamps of the traffic light change the update watch window option has to be activated The pedestrian buttons are simulated using F2 direction 1 and F6 direction 2 The car detectors are simulated using F7 direction 1 and F8 direction 2 Press for example F2 to see the traffic light switch to RED and the WALK light switch to on command syntax function 2
70. stored messages message cnt number of tasks waiting for messages read task cnt and number of tasks waiting to store a message write task cnt Since either write task cnt or read task cnt is equal to Zero only a single list is necessary for the waiting tasks wait tasks The identifications of the waiting tasks assigned according to the waiting period index 0 for longest waiting task are stored in this RTX 51 RTX 251 101 Stored messages are placed in the message list messages Return Value OK 0 Function executed successfully NOT OK 1 Function not executed See Also os check mailboxes Example include lt rtx51 h gt Use rtx251 h for RTX 251 void xyz task void task 0 priority 0 t rtx onembxtab xdata table if os check mailbox 2 amp table error handling Evaluation of the table 102 Programmer s Reference os_check_semaphores Task function The system operation os_check_semaphores returns information about the state of all semaphores The information is stored in a table in XDATA memory to be declared by the user Prototype Parameter Return Value See Also signed char os_check_semaphores t_rtx_allsemtab xdata table table is a table declared by the user in XDATA memory The system call stores the determined information in this table The table contains the following structure defined in RTX51 H RTX251 H typedef stru
71. task is put on a waiting list until the first task finishes its operations on this resource Task Switching RTX 51 251 contains an event driven task switching mechanism that switches tasks according to their priority preemptive multitasking An additional task switching mechanism which switches according to the time slice mode can be optionally used round robin scheduling RTX 51 251 recognizes four priority levels priorities 0 1 and 2 can be assigned to standard tasks Priority 3 is reserved for fast tasks The individual tasks can wait for various events to occur without requiring processor time no processor burdening Events can be characterized as the receipt of messages signals interrupts and time outs or a combination of these Three wait forms are supported m Normal the WAITING BLOCKED task can be blocked for an arbitrary amount of time until the corresponding event occurs Overview m Conditional the waiting task is never blocked the task can recognize if the corresponding event existed by evaluating the return value m With time out the task is blocked for a certain time if the corresponding event does not occur Interrupt System RTX 51 251 performs task synchronisation for external events by means of the interrupt system Two types of interrupt processing are basically supported in this case 1 C51 C251 Interrupt Functions Interrupts are processed by C51 C251 interrupt functions 2 Task Interru
72. therefore not be mutually interrupted m Can be interrupted by C251 interrupt functions m The maximum number of fast tasks is limited by the maximum number of active tasks in the system 16 and the available on chip RAM for context storage RTX 251 Standard Tasks m Require somewhat more time for the task switching compared to fast tasks m Contain a context save area located in off chip direct RAM m Canbe interrupted by fast tasks m Can interrupt themselves mutually m Can be interrupted by C251 interrupt functions m A maximum 16 standard and fast tasks can be active in the system 20 Programming Concepts Each RTX 251 task contains a context area in the external memory During a task change all required registers of the running task are stored in the corresponding context area Afterwards the registers are reloaded from the context area of the task to be started swapping Each task has its own private stack area inside of its context save area therefore no stack swapping is required Additionally each task has its own private reentrant stack area as part of its context save area if any reentrant functions are declared in the system In the case of RTX 251 fast tasks a task change occurs faster than for standard tasks since the context save areas of all fast tasks are automatically located in on chip RAM faster access Task Declaration C51 251 provides an extended function declaration for defining tasks A t
73. time out when no object received 255 Wait until an object is received infinite waiting buffer ptr is the pointer to a structure of the type CAN MESSAGE STRUCT in the XDATA memory The received object will be copied to this structure The structure CAN MESSAGE STRUCT defined in RTXCAN H is organised as depicted below c data 8 bytes RTX 51 RTX 251 169 for intel 82527 the Siemens C515C only c_data 8 bytes ident is the communication object identifier as defined in can def obj can def obj ext can def last obj can def last obj ext c data Data bytes The data length is defined as eight bytes maximum data length for the communication object for simplification reasons User structures may be defined with a data length smaller than eight bytes the first two bytes must however always represent the IDENTIFIER field The communication software always sends or receives the data length as defined with can def obj can def obj ext can def last obj can def last obj ext Return Value C OK Object received C TIMEOUT Time out reached no object received C CAN FAILURE Unrecoverable CAN error Note The application always receives the newest object data When an object receives new data before the application has read the old data the latter will be overwritten by the new 170 CAN Support data A new notification will not be sent to the application unless it has responde
74. token is available or an optional time limit is exceeded Send Token After completing its operation on a resource a task will return the associated token to the semaphore by a send function see system function os send token Dynamic Memory Management Dynamic memory space is often desired in a multitasking system for generating intermediate results or messages The requesting and returning of individual memory blocks should be possible within constant time limits in a real time system Memory management which functions with memory blocks of variable size such as the standard C functions malloc and free is less suitable for this reason RTX 51 251 uses a simple and effective algorithm which functions with memory blocks of a fixed size All memory blocks of the same size are managed in a so called memory pool A maximum of 16 memory pools each a different block size can be defined A maximum of 255 memory blocks can be managed in each pool 32 Programming Concepts Generate Memory Pool The application can generate a maximum of 16 memory pools with various block sizes The application must provide an XDATA area for this purpose The pool is stored and managed by RTX 51 251 in this area see system function os_create_pool Request Memory Block from Pool As soon as a pool has been generated the application can request memory blocks The individual pools are identified by their block size in this case If an
75. traffic light application will operate without using interrupt driven serial I O but will not perform as well 1s the command line editor for characters received from the serial port 260 Glossary TRAFFIC2 C SERIAL C and GETLINE C are listed below TRAFFIC2 C RRR RIKKI IA HK KKK KI IK IK KKK KK e e e he KKK KK KK KKK He e he he de hehe AAA AAA AAA AIA AIA AA AAA e ke ke fa M TRAFFIC2 C Traffic Light Controller using RTX 51 J ey 17 NOV 1994 EG e BRR KKK HK HK HK ke ke ke hehehe KKK KKK HK ke e he IKK KKK ke He kk He ke he he he ke ke KK KKK e He e de KIKI KKK KKK KKK f Derived from TRAFFIC C originally written for RTX tiny Shows advanced features of the full version of RTX 51 Coke KH HK ke ke e ke hehe hehehe KK KKK e e e he IKK KK KK KKK He e he he he IKK KKK HK kk e de KIKI KKK KKK e eek f pragma CODE DEBUG OBJECTEXTEND code char menu n TRAFFIC LIGHT CONTROLLER using C51 and RTX 51 n This program is a simple Traffic Light Controller Between n start time and end time the system controls a traffic light n with pedestrian self service and approaching car detection n Outside of this time range the yellow caution lamp is blink n i ing I n command syntax Putunction cscazzeee nzecete n Display D display times An Time T hh mm ss set clock time An Start S hh mm ss set start time I n
76. unit can be used along with RTX 51 Note however that these functions are not interrupt capable For this reason only one task or only tasks with the priority O may use the arithmetic unit Multiple data pointers are not supported by RTX 51 If special library is to be used the option MOD517 NODP8 must be used There is only one way to take advantage of multiple data pointers when running RTX 51 sections using multiple data pointers must be globally protected against interrupts Solely under this condition the option MOD517 or MODAMD is acceptable The C51 special library uses multiple data pointers to speed up the functions memcpy memmove memcmp strcpy and strcmp If locking out of interrupts is not a problem concerning the interrupt response time then a sequence like shown below is acceptable with RTX 51 Example for Siemens 80C517 A 537 A RTX 51 RTX 251 37 unsigned int oldbuf 100 unsigned int newbuf 100 Enable usage of multiple data pointers pragma MOD517 Disable interrupts globally EA 0 Copy data using multiple data pointers memcpy newbuf oldbuf sizeof newbuf Re enable interrupts globally EA 1 Disable usage of multiple data pointers pragma NOMOD517 Example for Dallas 80C320 and some AMD chips unsigned int oldbuf 100 unsigned int newbuf 100 Enable usage of multiple data pointers pragma MODAMD DP2
77. with 3 interrupt enable registers ien0 ienl for processors with 2 interrupt enable registers ien2 is insignificant ienO for processors with 1 interrupt enable register ien1 and ien2 are insignificant Return Value OK 0 Function was executed successfully This return code is always used as this function does no parameter checking at all See Also oi_reset_int_masks RTX 51 RTX 251 Note Example 61 Never change an interrupt enable bit whose interrupt source is attached to a RTX 51 251 task This function can not modify the global interrupt enable bit EA bit This bit can be manipulated by the user directly include lt rtx51 h gt Use rtx251 h for RTX 251 void isr manager void task 4 priority 1 Enable the serial interrupt of a 8051 MCS 251 processor oi_set_int_masks 0x10 0 0 task code 62 Programmer s Reference oi reset int masks Task ISR function The system operation oi reset int masks resets one or more interrupt mask bits immediately Since this function is dedicated to non standard cases it does not contain any parameter checks Its use should be restricted to the following special cases to manipulate special bits which are part of the interrupt enable registers Example watchdog control bits on 80C517 80C537 processors to modify interrupt enable bits from inside a C51 C251 interrupt function Not to be used for interrupt sources at
78. your hardware This number may be determined from a table shown in the section RTX USE IDLE This flag determines if the CPU is switched to idle mode during system idle time During idle mode the program execution is stopped while all peripherals including the interrupt controller stay active If switched OFF then a busy wait loop is done during system idle time Please note that not all CPUs support this idle mode function see manufacturer s data sheet Do not select this option if the CPU is not able to support it Number of the Processor Type Used page 128 RTX System Timer Enter here the number of the hardware timer to be used by RTX 51 251 as the system clock source Depending on the particular CPU type timer 0 1 or 0 1 and 2 may be selected If timer 2 is selected and the specified CPU does not support this option then an error message will appear while assembling RTXCONF ASI Use Round Robin Click on this box to switch option On Off If the time sharing option is enabled tasks of priority 0 will be switched in a round robin scheme This switching will take place each time a system interval system tick ends and is restricted to ready tasks of priority 0 Use Bankswitching for RTX 51 only Click on this box to switch option On Off If the C51 bank switching scheme is to be used then this option must be switched ON Otherwise some memory space and execution time can be saved when this option is switc
79. 15C only This function can only be executed after can hw init or can stop The communication can be started after the completion of the object definition using can start Prototype Parameter Return Value Example unsigned char can def obj unsigned long last msg mask unsigned char data length last obj mask is the last standard communication object mask corresponding to the CAN definition 0 2047 data length is the number of data bytes 0 8 C OK Object definition successful C NOT STOPPED can hw init or can stop must be called prior to can def last obj C OBJ ERROR Attempt was made to define an pre existing object C TOO LONG data length cannot be greater than 8 bytes include rtxcan h Define the standart last object with mask 1200 and with 6 data bytes 37 can_def_last_obj 1200 6 RTX 51 RTX 251 151 can def last obj ext Defines the last extended communication object for intel 82527 the Siemens C515C only This function can only be executed after can hw init or can stop The communication can be started after the completion of the object definition using can start Prototype unsigned char can def obj unsigned long last msg mask unsigned char data length Parameter last msg mask is the last extended communication object mask corresponding to the CAN definition 0 536870911 data length is the number of data bytes 0 8
80. 2 1s only available during normal operation and during Sleep Mode and not during Power Down Mode NOTE The DcRI bit address 2FH must be set to enable VCC 2 on pin 24 One ISO low speed physical layer active pin 24 VCC 2 pin 11 INT Zero Normal operation pin24 INT pin 1 P2 6 RTX 51 RTX 251 201 Clockout enable Cen One Clockout signal is enabled Zero Clockout signal is disabled Siemens 81C90 91 Bus Timing 81C90 91 Bit Time Calculation fosc 1 fcrystal fscl BRP 1 2 fosc Tacl BRP 1 2 fcrystal TSEGI TS1 1 fscl TSEG2 TS2 1 fscl SJWidth SJW 1 fscl Bit length fbl TSEG1 TSEG2 1 fscl f crystal Baud rate 2 BRP 1 3 TSEGI TSEG2 Programming the Siemens 81C90 91 Function CAN HW INIT allows the CAN controller bus timing to be programmed The parameters refer to 81C90 91 hardware registers in the following way BIT LENGTH 1 REG Bit length register 1 BIT LENGTH 2 REG Bit length register 2 OUT CONTROL REG Output control register SLEEP AND BR PRESCALE Combination of Sleep mode enable SME of 202 CAN Support Control register and baud rate prescaler CLOCK CONTROL REG Clock control register Determines the output frequency at pin CLK Bit Length Register 1 MSB SAM Sample rate TS2 2 Length of segment 2 TS2 2 TS2 0 TS1 3 Length of segment 1 TS1 2 TS1 1 TS1 0 LSB SAM Sample rate One
81. 53 DIETIKON w FR KI IK ek e e e e KK KK IIE e ee eje KKK e e e He A KK KKK IK He He He He e KKK KKK e e e e He He KKK KKK KICK f IMPORTS Yih ee include lt reg51 h gt Processor specific registers include lt rtx51 h gt RTX 51 function calls Use file RTX251 H for RTX 251 include rtxcan h CAN function calls DEFINES define SEND_TASK 1 define REC_TASK 2 Global variables struct can message struct xdata ts tr CAN send and receive data unsigned char i unsigned int tl count t2 count Akkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkx TEST TASK ke e e e e He He He He He he he he e e e He He He KIKI e e e e He He He KK KKK He e He KKK KEKE de e e e He He KARE He e e e e e He ke RTX 51 RTX 251 217 void rec task void task REC TASK _priority_ 1 for can receive Oxff amp tr t2_count void send_task void _task_ SEND_TASK Start CAN Task if can_task_create C_OK Init the CAN communication controller for a baud rate of 50 Kbauds s CAN controller with 16 MHz clock Baud rate prescaler 19 INSYNC t TSEG1 4 x TSEG2 3 SJW1 SJW2 4 SAMPLING 1 three samples bit taken SYNCH Mode 1 transitions from recessive to dominant and vice versa are used for resynchronisation e tBTL 2 19 1 16 MHz 2 5ms 1
82. DS EDI TIR RIVERA Function Call Overview Sienal Eunctions iine eR ER falena falla TT Function Call Overview Message Punctions 5 e o OR CR ROI Function Call Overview S maphore F rncCtloris 4 n or epe Pent eR RARE LOIRE HRS Function Call Overview Memory Management aiee rU 9252990271222 SNA SORIA RAR GRANA EVER E ye RAV ESAE TS Function Call Overview Example for a Buffer Pool Application esee 83 Management of the System Clock eren 91 F nction Call Overview cnain a ariana 91 Debug Functions sees 2055 He Lilia Hte fee ates D Ete le ae D Eea PUE RR saves la 93 Function Call Overview nennen nennen nre nnne nnns 93 Chapter 5 Configuration c eeeee ee eere eene eee eene esee etae sette tn esset etae eset 109 Graphical Configuration Utility i 109 Running the Configuration Utility ii 110 Configuration Optrons ss sis ione ee OH Ro hag reece 111 Memory Assignment for RTX 51 oe i 116 Direct Addressable Internal Memory DATA 116 Indirect Addressable Internal Memory DATAR 117 External Memory XDATA ii 119 Memory Assignment for RTX 251 i 121 Direct Addressable Internal Memory DATA 121 Direct Addressable External Memory EDATA 121 viii Content External Memory X DATA Jeee terere n e Ea EK E KSEE 124 Summary of the User Configurable Values
83. ENT NAME 0 0 0 PR PRODUCER TASK SAMPLE 1 1 0 PR CONSUMER TASK SAMPLE RTX 251 DOS LINKER LOCATER L251 V1 10 INVOKED BY C C251 BIN L251 EXE SAMPLE OBJ RTXCONF OBJ RTX251 CPU MODE BINARY MODE INTR FRAME 4 BYTES SAVED ON INTERRUPT MEMORY MODEL LARGE INPUT MODULES INCLUDED SAMPLE OBJ SAMPLE COMMENT TYPE 0 C251 V1 10 8 Overview RTXCONF OBJ RTX CONFIGURATION COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXINIT COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXDATA COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXCLK COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXSNDM COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXCREA COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXINT COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXWAIT COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXIHNDM COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTX251 LIB VERSION 0V100 COMMENT TYPE 0 A251 V1 10 C NC251NLIBNRTX251BD LIB RTXBLOCK COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXDISP COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXQUOP COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXIHNDS COMMENT TYPE 0 A251 V1 10 C C251 LIB RTX251BD LIB RTXINS COMMENT TYPE 0 A251 V1 10 C NC251NLIBNC251BL LIB C START COMMENT TYPE 0 A251 V1 10 C NC251NLIBNC251BL LIB C INIT COMMENT TYPE 0 A251 V1 10 TASK TABLE OF MODULE SAMPLE SA
84. HK kk e he he he ke ke e He ke kk kk e de e He He He He KKK ee eek f bit readtime char idata buffer unsigned char args number of arguments rtime sec 0 preset second args sscanf buffer bd bd bd scan input line for amp rtime hour hour minute and second amp rtime min amp rtime sec if rtime hour gt 23 rtime min gt 59 check for valid inputs rtime sec 59 Il args 2 args EOF printf n ERROR INVALID TIME FORMAT n return 0 return 1 define ESC 0x1B ESCAPE character code bit escape flag mark ESC character entered RRR RIKKI KKK He He e ke hehe he IK KK KKK e e e he he he KKK AA AAA AIA AAA AAA AAA ee eek f Task 6 get escape check if ESC escape char was entered 2 H H de e hee HK ke ke ke hehehe IKK KKK kk e e he he IKK KKK HK kk He KIKI KK He ke ke ke kk e de e KIKI KKK KK e e eek f void get escape void task GET ESC while 1 endless loop if getkey ESC escape 1 set flag if ESC entered if escape if esc flag send signal os send signal COMMAND to task command RRR RIKKI IA AAA AIA KIKI IK KK KKK KKK KKK KK KK KK AAA AIA AIA AIA AAA AAA AAA AAA AA AAA Task 1 command command processor BERRI KK IK HK HK HK HK KIKI KK KK KKK e He He KK IK IK KK KK AAA He e He AIA AIA AAA KEK AIA AIA AA AAA He ke ke void command void _task_ COMMAND unsigne
85. ITBUS Standard rivi iaia lina ao ge al iva P 243 Application Interface ili A Lal dta e dps 243 Structure of the Message Buffer essere nennen 244 Transf r of Messages sioe E pieni ieri 246 ReGeiptiof Messages s ou e GR ERR ER Senate rota oro 247 Imtialisation i e p ene Pe ety t D EXE EU ea 248 Application Examples pde tentes b deer imde pisa 249 Remote Access and Control Functions RAC i 251 Outstanding Responses eene era Eee Fee ali fabs Fes ERE Rei Fen doas 251 Error Handling uos P o eR E e ERR ORAE 252 Files Delivered ccssssscsscccccccssssvesccccceeeessvescecccenensvsseccesceensusesscesscseessuvesssess 252 RTX 51 RTX 251 Chapter 8 Application Example cccsssssscssccssssssssssssscssssssssssssscsessssees 255 5 TTT 255 Example Program TRAFFIC2 i 255 Principle of Operation eet etti 256 Traffic Light Controller Commands eene 258 ST ATT 258 TRAFFIC rana aa e aaa aan 260 SERIAL C see e Ee NER e AE Nee RI 267 GETLINE C i5 nitet tti teet ariana 269 Compiling and Linking TRAFFIC2 rennen eene 270 Testing and Debugging TRAFFIC2 nennen nere 270 eu cla P 272 RTX 51 RTX 251 1 Chapter 1 Overview There are two fundamental problems of many modern microprocessor applications m A task must be executed within a relatively short time frame m
86. K light as soon as possible Example 2 a car approaches on direction no 1 When it is detected and no pedestrian request or car detect event on direction 1 arises then the RED phase on direction 1 is terminated prematurely By this the arriving car gets a GREEN light as soon as possible The Figure 22 illustrates the eight different control phases 258 Glossary 1 2 3 4 5 6 7 8 ios green green yellow red red red red stop walk stop pedestrian button 2 car detector 1 1 2 3 4 5 6 7 8 red red red red rede green green yellow yellow stop walk stop car detector 2 pedestrian button 1 Figure 22 TRAFFIC2 Control Phases Traffic Light Controller Commands You can communicate with the traffic light controller via the serial port interface of the 8051 You can use the serial window of dScope 51 to test the traffic light controller commands The serial commands that are available are listed in the following table These commands are composed of ASCII text characters All commands must be terminated with a carriage return Command Serial Text Description Display D Display clock start and ending times Time T hh mm ss Set the current time in 24 hour format Start S hh mm ss Set the starting time in 24 hour format The traffic light controller operates normally between the start and end times Outside these times the yellow light flashes Set the ending time in 24 hour format Software The TRAFFIC2 application is composed of th
87. MPLE TASKID PRIORITY SEGMENT NAME 0 0 PR PRODUCER TASK SAMPLE 1 1 PR CONSUMER TASK SAMPLE Debugging the Program The dScope debugger is started automatically upon completion of the link step A predefined dScope initialization file SAMPLE INT is used to set breakpoints inside of the two tasks and to define two watch variables The application code and an include file named DBG_RTX INC are loaded This file contains declarations of dScope macros to support debugging of RTX 51 251 code The defined macros may be called as follows RTX 51 RTX 251 9 m With the key F3 a table of all declared tasks may be displayed It shows some important information about them and the associated task states Prio State Blocked for Event Mbx Sem Timer Signal RUNNING BLOCKED ID Task number as defined in the task declaration Start Task start address Prio Task priority State Actual task state Blocked for Event Defines for which event the task is blocked the task is waiting for Event codes used here are MSG wait for message mailbox read INT wait for interrupt SIG wait for signal TMO wait for time out WRITE MAILBOX wait until enough space in message list of mailbox mailbox write TKN wait for a token from a semaphore Mbx Sem When the task is blocked for a mailbox read write then this field shows the mailbox number 0 7 When the task is blocked for a semaphore then this field shows the se
88. NCLUDE file 236 RTXCAN H Example files BCANDEMO C51 BCANDEMO BAT BCANS92 BAT GCANDEMO C51 GCANDEMO BAT HCANDEMO CS51 ICANDEMO C51 HCANDEMO BAT CAN Support Header file for KEIL C51 C251 applications C51 C251 example for the Philips CAN controller Compile and link the example for the 80C200 Compile and link the example for the 80C592 C51 C251 example for the intel 82527 CAN controller Compile and link the example for the intel 82527 C51 C251 example for the Siemens 81C90 91 CAN controller C51 C251 example for the Siemens C515C CAN controller Compile and link the example for the Siemens 81C90 91 RTX 51 RTX 251 237 Chapter 7 BITBUS Support RTX 51 PREFACE This chapter forms the user s guide for the RTX 51 BITBUS Interface software The RTXBITBUS 51 Interface allows a RTX 51 system to communicate with a BITBUS network Since this software is based on a 8051 family processor it is not available for the RTX 251 This chapter is sub divided into four sub chapters outlined below Introduction provides a brief overview on RTXBITBUS 51 BITBUS Standard describes the relation between the RTXBITBUS 51 software and the Intel BITBUS standard Application Interface contains detailed information about the application interface Files Delivered lists all files on the distribution disk Introduction The RTXBITBUS 51 task supports BITBUS communication of Intel 8044 8344 microprocessor based
89. RTX 51 RTX 251 131 Chapter 6 CAN Support Overview This chapter forms the user s manual for the RTXCAN x51 Interface software The RTXCAN x51 Interface allows a RTX 51 251 system to communicate with a CAN Network This chapter is sub divided into eight sub chapters outlined below Introduction provides a brief overview on RTXCAN x51 Concept describes the underlying software concept Application Interface contains a detailed listing of all RTXCAN x51 system functions Configuration describes the hardware requirements of RTXCAN x51 and the system configurable constants Return Values shows the return values of all system functions Timing Initialisation gives an overview on the bus timing calculations Application Example contains a short application example Files Delivered lists all files on the distribution disk Introduction CAN Controller Area Network is a serial communication protocol designed for automotive and industrial applications CAN offers many important features such as m Multi master serial communication network with an unlimited number of participating network nodes m Programmable transmission speed up to 1 Mbits s m Very low probability of undetected errors due to powerful error handling 132 CAN Support m Atleast 40 meters maximum distance between two bus nodes at 1 Mbits s speed The distance increases with decreasing transmission speed m Guaranteed latency time supporti
90. RTX 51 251 Even in normal operation all interrupts at the same hardware priority RTX 51 251 ensures that ISR interrupts are handled with preference If desired however the ISR interrupts of the application can be set to a higher interrupt priority RTX 51 251 does not provide any operations for the management of the Interrupt Priority registers All RTX 51 251 task interrupts must run at the same hardware interrupt priority ISR interrupts may also run on an optional hardware interrupt priority An optimal ISR processing is not guaranteed however if task and ISR interrupts are set to the same hardware priority Declaration of C51 C251 Interrupt Functions Interrupt functions are declared as follows see also C51 C251 documentation void func void model reentrant interrupt n using n m When interrupt functions are used a difference must be made whether register bank switching using attribute is used or not m With Register Bank Switching When entered the interrupt function saves the registers ACC B DPH DPL and PSW PSWI with C251 to the stack of the interrupted task when necessary Since not all registers are stored the user must ensure that the interrupt function does not use a register bank used by RTX 51 251 Register bank 0 must also not be used reason it is always used by RTX 51 standard tasks or any RTX 251 task and by the system clock Register banks 1 2 or 3 may only be used if they are not simultaneously
91. RTX system memory space initialization of RTX system tables initialization of the system clock hardware startup of the RTX system clock handler system ISR creation of the first user task initialization of the interrupt hardware enable interrupts start dispatcher By os start system the first user task is created and the system clock handler system ISR is started RTX 51 RTX 251 43 Some considerations concerning the C51 C251 main function The code part of the function main which is executed before os_start_system is called is executed like any C application without RTX 51 251 The code part following the call of os_start_system is entered only when the system function os start system fails Otherwise the first user task will be entered There is no return from the function os start system in this case Upon completion of os start system when entering the first user task the interrupt system will be globally enabled EA 1 Unless the user disables it explicitly it will stay enabled almost all the time also during system code of RTX 51 251 Available functions Function Name Parameter Description OS Start system unsigned char task number Initializes the system and starts the first Identification of first user task user task number used in C51 task It is the first RTX function which may be declaration called in a program 44 Programmer s Reference os_s
92. RTXGCAN LIB Special locate controls are not required for the RTXCAN x51 software A system for the Siemens 81C90 91 CAN controller is built in the following way Assembling of HCANCONF A51 Linking the application with HCANCONF OBJ and RTXHCAN LIB Special locate controls are not required for the RTXCAN x51 software A system for the Siemens C515C CAN controller is built in the following way Assembling of ICANCONF A51 Linking the application with ICANCONF OBJ and RTXICAN LIB Special locate controls are not required for the RTXCAN x51 software A system for the Philips 82C200 CAN controller is built in the following way Assembling of BCANCONF AS1 Linking the application with BCANCONF OBJ and RTXBCAN LIB RTX 51 RTX 251 183 Special locate controls are not required for the RTXCAN x51 software A system for the Philips 80C592 is built in the following way Assembling of CCONF592 A51 Linking the application with CCONF592 OBJ and CANP592 LIB Special locate controls are not required for the RTXCAN x51 software Return Values Contained in the INCLUDE file designated RTXCAN H define C OK define C NOT STARTED define C CONF ERROR define C OBJ ERROR define C TOO LONG define C INVALID TYPE define C MEM FULL define C NOT STOPPED define C OB REBIND define C TIMEOUT define C CAN FAILURE define C ERR ACTIVE define C ERR PASSIVE define C BUS OFF define C SEND ERROR
93. Require somewhat more time for the task switching compared to fast tasks m Share a common register bank and a common stack area register bank 0 m The current contents of registers and stack are stored in the external XDATA memory during a task change m Can be interrupted by fast tasks m Can interrupt themselves mutually m Can be interrupt by C51 interrupt functions A maximum 16 standard tasks can be active in the system RTX 51 RTX 251 19 Each RTX 51 standard task contains a context area in the external memory During a task change with standard tasks all required registers of the running task and of the standard task stack are stored in the corresponding context area Afterwards the registers and the standard task stack are reloaded from the context area of the task to be started swapping In the case of RTX 51 fast tasks a task change occurs considerably faster than for standard tasks since each fast task has a separate register bank and a separate stack area During a task change to a fast task only the active register bank and the current stack pointer value must be changed RTX 251 see section above for RTX 51 basically recognizes two classes of tasks RTX 251 Fast Tasks m Contain short responses m Contain a context save area located in on chip RAM for fastest access m Contain the highest task priority priority 3 and can therefore interrupt standard tasks m All contain the same priority and can
94. Return Value C OK Object definition successful C NOT STOPPED can hw init or can stop must be called prior to can def lat obj ext C OBJ ERROR Attempt was made to define an pre existing object C TOO LONG data length cannot be greater than 8 bytes Example include rtxcan h Define the extended last object with mask 100000 and with 6 data bytes A can def last obj ext 100000 6 152 CAN Support can_stop Stops the CAN communication New objects can now be defined with can def obj Can stop does not erase the pre defined communication objects in contrast to can hw init Can start can be used to restart the CAN communication Prototype unsigned char can stop void Parameter none Return Value C OK CAN communication stopped C CAN FAILURE Errors while stopping the communication Example include rtxcan h Stop the CAN communication can stop Define object 200 can def obj 200 8 D REC Restart the CAN communication can start RTX 51 RTX 251 153 can_start Restarts the CAN communication after can stop or can def obj can def obj can only be executed after can stop or can hw init After a return status value of C BUS OFF the CAN communication can be restarted with can start no initialisation required Prototype unsigned char can start void Parameter none Return Value C OK CAN communication started
95. S sendstop 1 if Control S stop transmission break case CTRL OQ start trans sendstop if Control Q start transmission sendstop 0 break default read all other characters into inbuf if istart ILEN iend inbuf iendt amp ILEN 1 c if task waiting signal ready if itask OxFF isr send signal itask break if TI start trans if transmitter interrupt TI 0 clear interrupt request flag if ostart oend if characters in buffer and if sendstop if not Control S received SBUF outbuf ostart amp OLEN 1 transmit character sendfull 0 clear sendfull flag if task waiting signal ready if otask OxFF isr send signal otask else sendactive 0 if all transmitted clear sendactive BERRI IAA IAA he KK IAA AA e e he he AIA ke KK ke KKK IKI KK KKK HK KEKE KIKI AIA AAA AA ke ke ke serial init initialize serial interface 2 H k e e He ke ke ke ke ke ke hehe he IK KK KK de e e e hehe IK IK KK He kk He ke he he KI KK He ke kk kk e He e He He He de He He He e e e KEK f serial init SCON 0x50 mode 1 8 bit UART enable receiver TMOD 0x20 timer 1 mode 2 8 Bit reload TH1 0x 3 reload value 2400 baud TR1 1 timer 1 run os enable isr 4 enable serial port interrupt GETLINE C BERRI KKK KK e ke e ke he he hehe he KK KK HK HEIKKI KKK KK He kk He H
96. SSAGE STRUCT unsigned char timeout time out when no object received void xdata buffer ptr pointer to a structure of type CAN MESSAGE STRUCT unsigned int identifier Communication object identifier 0 2031 unsigned int identifier Communication object identifier 0 2031 0 65535 137 Description Defines the communication objects Use this function to define objects according to CAN standard 2 0A 11 bit identifier Defines the communication objects Use this function to define objects according to CAN standard 2 0B 29 bit identifier NOTE 29 bit identifiers also called ExtendedCAN are not supported by all CAN controllers Defines the 15 Sandard communication object Use this function to define objects according to CAN standard 2 0B 11 bit identifier Defines the 15 Extended Communication object Use this function to define objects according to CAN standard 2 0B 29 bit identifier Sends an object over the CAN bus Writes new data to an object without sending it Receives all not bound objects Binds an object to a task The task will be started when the object is received Unties the binding between a task and an object made with CAN BIND OBJ Binds last object to a task The task will be started when the object is received Unties the binding between a task and an last object made with CAN BIND LAST OBJ 138 CAN Support Function Name Parameter Description
97. TBUS communication task m Declared by the BITBUS header file m Used by the application software to send a signal to this task when the message has been read from the buffer bbs rx buf bbm rx buf The Figure 20 illustrates the context of the different variables BITBUS Communication Task The BITBUS communication task waits for one of the following events by means of an os wait system call m Message in mailbox 7 The application software prepares messages that it wants to transfer on the BITBUS and writes the pointer of the message to mailbox 7 When the BITBUS communication task receives the pointer in mailbox 7 it begins to transfer the message on the BITBUS RTX 51 RTX 251 241 m BITBUS message received serial interrupt When the BITBUS communication task receives a BITBUS message it writes the message into the buffer bbs_rx_buf bbm_rx_buf and checks the flag bbs en sig to app bbm en sig to app If this flag is set it sends a signal to the receiver application task identified by bbs rx tid bbm rx tid Ns BBx_RX_BUF MBX_7 N TX BUFFER BBx_ VJ Task BBx EN SIG TO DRV Signal BBx TID Signal BBx RX TID NY BBx_EN_SIG_TO_APP Figure 20 BITBUS Communication Concept m Signal If the BITBUS communication task has more than one message to pass to the receiver application task it sets the flag bbs en sig to drv bbm en sig to drv After reading a message from the buffer the receiver application task checks th
98. TMO 30 0 wait for timeout 30 ticks PHASE 6 dir 1 accept car detect dir 2 accept pedestrian button phaseno 6 os_wait K_TMO K_SIG 250 0 wait for timeout amp signal PHASE 7 dir 1 stick to red forbid walk dir 2 switch to yellow phaseno 7 stop 17 1 walk 1 0 green 2 0 yellow2 1 os wait K TMO 30 0 wait for timeout 30 ticks III HK ke ke ke hehehe IK KKK HK HK e e e he he he hehehe KK KKK He He he he he ke KK KKK ke e He e He e KK IKK KKK KKK eek f Task 5 keyread process key strokes from pedesttrian push ie buttons BRR RIKKI KK HK HK HK KIKI IK KKK KKK e e he e KK KK KKK KKK he he hehe IKK KKK He e He KEK IKI KKK KKK e e eek f void keyread void _task_ KEYREAD while 1 endless loop if phaseno lt 4 phaseno 0 3 if key2 if key pressed keypressed2 1 os_send signal LIGHTS send signal to lights os_wait K_TMO 5 0 wait for timeout 5 ticks else phaseno 4 7 if keyl if key pressed keypressedl 1 os send signal LIGHTS send signal to lights os wait K TMO 5 0 wait for timeout 5 ticks os wait K TMO 2 0 wait for timeout 2 ticks BERRI KK IK HK HK KKK KIKI AIA IAA AIA KIKI KK KK KK KKK HK IKK IKK KKK KKK AIA IKK AAA AAA AAA Task 6 car detl process interrupt from car detector 1
99. TXSETUP DCL Configuration Options When the RTXSETUP utility is started up and a valid configuration file is selected then the setup menu is displayed 112 Configuration da RTX Configuration File M RTX SRC51Y5 RTXSETUP DCL Use Round Robin Use Bankswitching General CPU Type RTX Code fi 7 RTX System Timer oz r r Interrupt Options Int Table Base hex IE Init Value hex IEN1 Init Value hex IEN2 Init Value hex joo Stack Configuration Fast Task Stack Standard Task Stack Reentrant Stack Size mz J032 Joso System Functions Use Mailbox Support Iv Use Semaphore Support v Use Idle Mode E Cancel Figure 5 Configuration menu for RTX 51 da RTX Configuration File M ARTXXSRC251VIXRTXSETUP DCL General RTX System Timer Use Round Robin CPU Type RTX Code S joo r Interrupt Options Int Table Base hex 000 pn joo IE Init Value hex IENI Init Value hex IEN2 Init Value hex Stack Configuration Task Stack Size Reentrant Stack Size fosa ner System Functions Use Mailbox Support Iv Use Semaphore Support v Use Idle Mode ni o ose a Figure 6 Configuration menu for RTX 251 The configuration menu shows different option groups for a configuration GENERAL RTX 51 RTX 251 113 CPU type Enter here the RTX code appropriate for
100. The untied object can now be received with can receive Prototype unsigned char can unbind obj unsigned int identifier Parameter identifier is the identification as defined in can def obj of the object that must be untied from the calling task Return Value C OK Object untied C OBJ ERROR Object undefined or never bound to the calling task See Also can bind obj can bind Example see can wait RTX 51 RTX 251 165 can_bind_last_obj Binds the last object to a certain application task This task will be started if the CAN software receives the determined object and if the application task is waiting with can wait can bind last obj and can wait can be used to implement specialised application tasks which handle the receiving of important objects In comparison to can receive no FIFO buffering is made The last object cannot be bound to more than one task A task that uses can bind last obj and can wait is comparable to a task that services a hardware interrupt the receiving of the bound object is the interrupt A maximum of eight objects may be bound to application tasks Prototype unsigned char can bind obj void Return Value C OK Binding successful C MEM FULL 8 can bind obj have already been made can unbind obj can be used to until an object from a task C OBJ REBIND This message is only a warning the object was already bound toatask The prior binding was u
101. The receive and the transmit buffers are used for interfacing the application to the communication task These two buffers have the same structure and are located in the external RAM Uu lt gt o PtrMessage gt BUFFER FULL LENGTH ROUTE 0 N OO oO FF WO ND PARMS n Bytes N 0 13 n 7 Field Description BUFFER FULL Is set to 1 TRUE when data has been loaded into the buffer Is set to 0 FALSE when data has been read from the buffer RES Reserved LENGTH Number of bytes length in the buffer Its value is 7 n where n is the number of bytes in the field PARMS The range of LENGTH is 7 to 20 No bytes in the data field PARMS will result in a length of 7 since the bytes 1 RTX 51 RTX 251 245 to 7 are always present The maximum length of 20 results if transmitting the maximum of 13 data bytes ROUTE See BITBUS specification ROUTE consists of the following bits wr se Joe ra RESERVED MT Message Type SE Source Extension DE Destination Extension TR Track For details see Intel BITBUS documentation Not used by RTX 51 BBx it transmits receives ROUTE without changing it CAUTION To be fully compatible with the BITBUS standard the application software of a slave station must always Set bit 7 MT for response Clear bit 4 TR Read the other bits from order and write them unchanged into response NODE Node contains the address of the sele
102. W A BRP 5 Baud Rate Prescaler BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 LSB Baud Rate Prescaler BRP The BTL cycle time is determined by programming the six bits of the baud rate prescaler The BTL cycle time is derived from the system cycle time the system cycle time is twice the crystal time The desired baud rate is determined by the BTL cycle time and the programmable bit timing segments BRP 2 BRP5 2 BRP4 2 BRP3 2 BRP2 2 BRP1 BRPO Synchronisation Jump Width SJW The synchronisation jump width defines the maximum number of BTL cycles that a bit may be shortened or lengthened by one resynchronisation during transmission of a data frame or remote frame Synchronisation jump width is programmable by bits SJW B and SJW A as depicted in the following table SJW B SJW A SJW 1 SJW 2 1 BTL cycle 2 BTL cycles 3 BTL cycles 4 BTL cycles 210 CAN Support Bus Timing Register 1 SAMPLE TSEG 2 2 Time Segment 2 TSEG 2 1 TSEG 2 0 TSEG 13 Time Segment 1 TSEG 1 2 TSEG 1 1 TSEG 1 0 MSB LSB SAMPLE This determines the number of samples of the serial bus which are made by the CAN controller IF SAMPLE is set to low a bit is sampled once If SAMPLE is set to high three samples per bit are made SAMPLE O allows higher bit rates whereas SAMPLE 1 provides better rejection to noise on the bus SAMPLE 1 is not recommended at bit rates over 125 Kbits s Time Segment 1 and Time S
103. _priority_ 1 unsigned char i done can bind obj 0x10 for wait for message done can wait Oxff amp tr if done C OK count 1 done can get status 225 RTX 51 RTX 251 if tr identifier 0x10 ts identifier 0x11 for i 0 i lt 7 i ts c data i tr c data i ts c data 0 count 1 done can send amp ts task REC TASK 2 priority 1 void rec task 2 void t unsigned char i can bind obj 0x20 done for wait for message done can wait Oxff amp tr if done C OK count 2 done can get status if tr identifier 0x20 ts identifier 0x21 for i 0 i lt 7 i ts c data i tr c data i ts c data 0 count 2 done can send amp ts task REC TASK 3 priority 1 void rec task 3 void t unsigned char i can bind obj 0x30 done for wait for message done can wait Oxff amp tr if done C OK count 3 can get status if tr identifier 0x30 ts identifier 0x31 i ts c data i tr c data i for i 0 i lt 7 ts c_data 0 count 3 can send amp ts done done void send task void task SEND TASK 226 CAN Support Start CAN Task if can task create C OK Init the CAN communication controller 81C91 for a baud rate of 1000Kbauds s CAN controller with 16 MHz clock PI n Bit Length Regi
104. a When an object receives new data before the application has read the old data the latter will be overwritten by the new data A new notification will not be sent to the application unless it has responded to the last notification it has read the objects data can bind obj can unbind obj can bind last obj can unbind last obj can wait for other methods to receive objects RTX 51 RTX 251 161 Example include lt rtxcan h gt struct xdata can message struct rec_mes Receive objects with no timeout for Endless loop can receive 0xff amp rec mes If object 220 received do routine if rec mes identifier 220 if object 300 received do other routine else if rec mes identifier 300 162 CAN Support can_bind_obj Binds an object to a certain application task This task will be started if the CAN software receives the determined object and if the application task is waiting with can wait can bind obj and can wait can be used to implement specialised application tasks which handle the receiving of important objects In comparison to can receive no FIFO buffering is made An application task can be bound to more than one object multiple call of can bind obj An object cannot be bound to more than one task A task that uses can bind obj and can wait is comparable to a task that services a hardware interrupt the receiving of the bound object is
105. a is stored at a user declared memory area t rix onesemtab xdata table Address of a memory area where a semaphore state table can be stored Extracts detailed status information about a particular memory pool from RTX System data This data is stored at a user declared memory area 94 Programmer s Reference os check tasks Task function The system operation os check tasks returns information about the status of all tasks in the system The information is stored in a table in XDATA memory to be declared by the user Prototype Parameter Return Value See Also signed char os check tasks t rtx alltasktab xdata table table points to a table in XDATA memory which was declared by the user The system call stores the determined information in this table The table contains the following structure defined in RTX51 H RTX251 H typedef struct unsigned char task_number unsigned char state t_rtx_alltasktab 19 task number designates the number assigned to the task in the C51 C251 task declaration state designates the task state K_READY Task is READY K_RUNNING Task is RUNNING ACTIVE K_BLOCKED Task is WAITING BLOCKED K DELETED Task does not exist or is deleted OK 0 Function executed successfully NOT_OK 1 Function not executed os_check_task RTX 51 RTX 251 95 Example include lt rtx51 h gt Use rtx251 h for RTX 251 void xyz task void task 0
106. ach_interrupt os_detach_interrupt os_wait unsigned int event_selector Specification of requested wait events Any combination of wait for interrupt message semaphore signal time out and interval is allowed Optionally identification of mailbox or semaphore unsigned int timeout Time out in system ticks Insignificant if no wait for time out is specified unsigned int xdata message Address of buffer 2 bytes in XDATA space where received message shall be stored Insignificant if no wait for message is specified unsigned char interrupt_nbr Identification vector number of interrupt source the ISR waits for os enable isr unsigned char interrupt nbr Identification trap number of interrupt source the ISR waits for os disable isr unsigned char ien0 ient ien2 Interrupt register masks containing a 1 at each bit position to be enabled oi set int masks Programmer s Reference Description Assigns an interrupt to the calling task Reverses assignment of an interrupt source to a task This is the general wait function of RTX 51 251 Any combination of events may be selected If one of the specified events occurs then task is made ready again i e waiting for events is terminated For details see separate chapter about os wait Enables the interrupt source assigned to an ISR Disables the interrupt source assigned to an ISR Enable one or more interrupt s not associated to RTX
107. additional block is still free in the pool RTX 51 251 supplies the start address of this block to the application If no block is free a null pointer is returned see system function os_get_block Return Memory Block to Pool If the application no longer needs a requested memory block it can be returned to the pool for additional use see system function os_free_block Time Management RTX 51 251 maintains an internal time counter which measures the relative time passed since system start The physical source of this time base is a hardware timer that generates an interrupt periodically The time passed between these interrupts is called a system time slice or a system tick This time base is used to support time dependent services such as pause or time out on a task wait Three time related functions are supported m Set system time slice m Delaya task m Cyclic task activation RTX 51 RTX 251 33 Set Time Slice The period between the interrupts of the system timer sets the granularity of the time base The length of this period also called a time slice can be set by the application in a wide range see system function os_set_slice Delay a Task A task may be delayed for a selectable number of time slices Upon calling this system function the task will be blocked sleep until the specified number of system ticks has passed see system function os_wait Cyclic Task Activation For many real time a
108. ard Task Context Layout for RTX 51 Size configurable with RTX EXTRENTSIZB space is only reserved if reentrant functions are used Size can be configured with RTX EXTSTKSIZE Constant size 17 bytes Segment RTX TASKCONTEXT x where x task number is divided into three parts 120 Configuration m Area for storing the processor registers and RTX 51 status information This area has a constant size of 17 bytes m Area for storing the task stack The current contents of segment 2STACK are copied into this area during a task change The size of this area is selected with the constant 7RTX EXTSTKSIZE It is purposeful that the size of segment STACK somewhat agrees with this This area is assigned with addresses lowest to highest corresponding to the 8051 stack conventions m Area for the reentrant stack of the C51 functions with the reentrant attribute This area is as stored by RTX 51 only if reentrant functions actually exist in the system This area is assigned with addresses highest to lowest corresponding to the C51 conventions NOTE RTX 51 only supports reentrant functions in the COMPACT model A context segment is stored in XDATA for each standard task This segment is required for storing the registers and the stack during a task change If necessary this segment also contains the reentrant stack for the standard task The size of the area for the task stack and the reentrant stack can be configured b
109. ask os create task COMMAND start command task os create task LIGHTS start lights task os create task KEYREAD start keyread task os create task CAR DET1 start cardetl task os create task CAR DET2 start cardet2 task os delete task INIT stop init task no longer needed bit display time 0 flag cmd state display time BERRI KKK HK HK ke ke e ke hehe KI KK KKK HK e e e he he IK KK KK ke kk He he he he he ke KK KKK He He ke e He e He He He He He He He e ee eek f Task 2 clock 2 H k e e He IA HK KKK KIKI IAA KK HK e He He de KIKI KK KKK AAA IAA AAA AAA AAA AIA KK KKK KKK f void clock void task CLOCK _priority_ 1 while 1 clock is an endless loop if ctime sec 60 calculate the second ctime sec 0 if ctime min 60 calculate the minute ctime min 0 if ctime hour 24 calculate the hour ctime hour 0 if display time if command status display time os send signal COMMAND signal to command time changed 262 Glossary os_wait K_TMO 100 0 wait for 1 second struct time rtime temporary storage for entry time BERRI KK IKK HK HK HK HI KI KKK KKK AIA e e he he KK KKK ke ke kk khe he he he hehe AAA AAA AAA AIA ASA AAA KKK KEK f readtime convert line input to time values amp store in rtime Coke hehehe ke HK He He e ke he KKK KK KKK e he he KK KKK KK
110. ask is declared as follows void func void model task lt taskno gt priority prio m Tasks cannot return a value return type void m No parameter values can be passed to tasks void in parameter list m taskno is a number assigned by the user in the range 0 255 Each task must be assigned a unique number This task number is required in RTX 51 251 system function calls for identifying a task A maximum of 256 tasks can be defined However only 19 RTX 51 or 16 RTX 251 tasks can be active at the same time Note If the XDATA memory requirement of RTX 51 251 is to be minimized the tasks must be numbered sequentially beginning with the number 0 m prio determines the priority of the task The value 0 corresponds to the lowest possible priority value 3 corresponds to the highest possible priority The priorities define implicitly the task class Standard tasks Priorities 0 1 and 2 Fast tasks Priority 3 If no priority is specified RTX 51 251 uses the task priority 0 RTX 51 RTX 251 21 m RTX 51 standard tasks must be compiled for register bank 0 which 1s the default value of the C51 compiler RTX 51 fast tasks must be compiled for register banks 1 2 or 3 This must be guaranteed using the directive pragma REGISTERBANK x where x 2 1 2 3 If this rule is violated C51 BL51 generates an error message No special compiler directives are required for RTX 251 standard and fast tasks
111. asks with priority 0 also with round robin scheduling Tn all other cases the standard C51 functions fpsave and fprestore must be used If fpsave is called then no RTX function call is allowed unless fprestore is executed Use of the C51 C251 Runtime Library No restrictions apply for all standard library functions which are reentrant see C51 C251 documentation In regard to the small number of functions which are not reentrant the user must ensure that these are not simultaneously used by several tasks 36 Programming Concepts Register Bank Default RTX 51 see section below for RTX 251 assigns register bank 0 to all standard tasks Fast tasks receive register banks 1 2 or 3 selectable with the pragma REGISTERBANK x directive During a task change RTX 51 automatically selects the currently required register bank RTX 51 tasks and functions used by it must not be provided with the using attribute RTX 51 generates the register bank switching The using attribute is only permissible for C51 interrupt functions RTX 251 makes use of the MCS 251 register file with register bank 0 selected for all tasks C251 interrupt functions may therefore use register banks 1 2 and 3 freely Use of the C51 Special Library C51 contains a special library for supporting the arithmetic unit and multiple data pointers of some 8051 derivatives 80C517 537 DALLAS 80C320 and some AMD chips The arithmetic
112. ations are not allowed BRP 0 AND SAMPLE 0 AND TSEG2 SJW2 lt 3 BTL cycles BRP 0 AND SAMPLE 1 AND TSEG2 SJW2 lt 4 BTL cycles BRP 0 AND TSEGI SJWI lt 4 BTL cycles TSEGI 1 AND SJWI lt 3 BTL cycles 82526 Programming Example Baud rate prescaler 0 Crystal frequency 16 MHz INSYNC 1 BIL cycle is always 1 SIWI 1 BIL cycle TSEGI 3 BIL cycles TSEG2 2 BIL cycles SJW2 1 BIL cycle SAMPLE 0 ter 2 0 1 16 MHz 0 125ms 1 bit cycle 1 1 3 24 1 0 125ms 8 0 125ms 1ms Baud rate 16 MHz 2 0 1 8 1 Mbits s Variation in baud rate due to resynchronisation MAX baud rate 1 Ims 1 0 125ms 1 14 Mbits s MIN baud rate 1 1ms 1 0 125ms 0 89 Mbits s Parameters for CAN HW INIT RTX 51 RTX 251 195 BUS_TIMING_0 0H BUS TIMING 1 12H SYNCON 0 baud rate exceeds 100 Kbits s Intel 82527 Bus Timing 82527 Bit Time Calculation f cyrstal Baud Rate DSC 1 BRP 1 3 TSEG1 TSEG2 Programming the Intel 82527 Function CAN HW INIT allows the CAN controller bus timing to be programmed The parameters refer to 82527 hardware registers in the following way BUS TIMING 0 Bus timing register 0 BUS TIMING 1 Bus timing register 1 BUS CONFIG Bus configuration register CPU INTERFACE CPU interface register 196 CAN Support Bus Timing Register 0 MSB SJWA Synchronisation Jump Width SJW B
113. bly reduced 2 Overview Advantages of RTX 51 251 are m Simple use of RTX 51 251 by integration in the Keil C51 C251 development system m Complete support of all C51 C251 features such as floating point operations re entrant functions and interrupt functions m User friendly configuration of RTX 51 251 for all members of the 8051 MCS 251 family m Flexibility only requires a few system resources and can also be applied for time critical applications Summary of the Major System Features Tasks RTX 51 see section below for RTX 251 recognizes two classes of tasks m Fasttasks with especially short responses and interrupt times Each fast task uses an individual register bank of the 8051 and contains its own stack area RTX 51 supports a maximum of three fast tasks active at a time m Standard tasks that require somewhat more time for the task switching therefore less internal memory than the fast tasks All standard tasks share a register bank and a stack area during a task change the current contents of registers and the stack are stored in the external RAM RTX 51 supports a maximum of 16 standard tasks active at a time RTX 251 recognizes two classes of tasks m Fasttasks with especially short response and interrupt times Fast tasks use context storage located in on chip RAM for fastest access RTX 251 supports a maximum of 16 tasks of fast or standard type active at a time A lower limit may be set for fast task
114. c fosc 1 fcrystal fscl BRP 1 fcrystal Bit length fbl TSEG1 TSEG2 1 fscl Baud rate BR fcrystal BRP 1 TS1 TS2 3 BR 10000 0 1 4 3 3 can_hw_init 0x80 0x34 0x00 0x00 0x00 Hi HA Hi SH HI Hi A S Hi SH S S Hi SH S S S Hi 145 146 CAN Support can def obj Defines a new communication object This function can only be executed after can hw init or can stop Objects can be defined until the object memory is full or the maximum number of 255 objects is reached with the Intel 82526 82527 the SiemensC90 91 C515C controller the object memory size is limited by the CAN controller internal RAM With the Philips 82C200 80C592 controllers the object memory size is user configurable and is allocated in the XDATA space of the microcontroller Each object identifier must be unique The function returns an error status if attempt is made to define an object twice The communication can be started after the completion of the object definition using can start Prototype unsigned char can def obj unsigned int identifier unsigned char data length unsigned char object type Parameter identifier is the communication object identifier corresponding to the CAN definition 0 2047 for intel 82527 and Siemens 81C90 91 0 2031 for the others data length is the number of data bytes 0 8 object type is the object definition D REC 0 Data frame r
115. can def obj can def obj ext can def last obj can def last obj ext C OK Object received C OBJ ERROR Object undefined include rtxcan h struct xdata can message struct read mes Read object 200 can read 200 amp read mes 176 CAN Support can_read_last_obj Allows data to be read from last object can read last obj cannot substitute the function can receive can read last obj is however useful for debugging purposes Prototype unsigned char can read void xdata buffer ptr Parameter buffer ptr is the pointer to a structure of the type CAN MESSAGE STRUCT in the XDATA memory The received object will be copied to this structure The structure CAN MESSAGE STRUCT defined in RTXCAN H is organised as depicted below c data 8 bytes ident is the communication object identifier as defined in can def last obj can def last obj ext c data Data bytes The data length is defined as eight bytes maximum data length for the communication object for simplification reasons User structures may be defined with a data length smaller than eight bytes the first two bytes must however always represent the IDENTIFIER field The communication software always receives the data length as defined with can def last obj can def last obj ext Return Value C OK Object received RTX 51 RTX 251 Example C_OBJ_ERROR Object undefined include lt rtxcan h gt struct
116. configuration of the BTL refer to the location of the sample point The correct location of the sample point is important for proper function of a transmission especially at high speed and maximum cable length For this reason the following items should be considered m Atthestartofa frame all CAN controllers in the system synchronise hard on the first recessive to dominant edge start bit During arbitration however more than one node may simultaneously transmit Two times the bus delay plus the time of the output driver and the input comparator may be required until the bus line is stable m The duration of TSEGI should reflect at least the total delay time two times the bus delay plus the internal delay in the range 100 200 ns m Toimprove the behaviour with respect to spikes on the bus line an additional synchronisation buffer is recommended on the left and right side of the sample point to allow one or more non synchronisation without sampling the wrong position within a bit frame This buffer should correspond to the time of the SJW segments TSEGI and TSEG2 should not be smaller than SJW Intel 82526 Bus Timing Only a few differences exist between the bus timing calculation for the Intel and Philips CAN controller The two controllers are fully communication compatible however when the baud rate is programmed the same 82526 Bit Time Calculation 2 Baud rate prescaler 1 RTX 51 RTX 251 1BTL Cycle ter
117. ct unsigned char status t_rtx_allsemtab 8 The following is allocated for each semaphore a status byte which can accept one of three different values 0 token stored 1 no token stored no waiting task s 2 no token stored waiting task s t Use semaphore_number 8 as index to this table OK 0 Function executed successfully NOT_OK 1 The function could not be executed os_check_semaphore RTX 51 RTX 251 103 Example include lt rtx51 h gt Use rtx251 h for RTX 251 void xyz task void task 0 priority 0 t rtx allsemtab xdata table if os check semaphores amp table error handling Evaluation of the table 104 Programmer s Reference os_check_semaphore Task function The system operation os_check_semaphore returns detailed information about the state of a certain semaphore The information is stored in a table in XDATA memory to be declared by the user Prototype Parameter Return Value signed char os_check_semaphore unsigned char semaphore t_rtx_onesemtab xdata table semaphore is the identification of the desired semaphore Values between 8 and 15 are allowed according to the eight predefined semaphores table points to a table in XDATA memory which was declared by the user The system call stores the determined information in this table The table contains the following structure defined in RTX51 H RTX251 H typedef s
118. cted slave station The master application software determines the slave to be addressed by writing the corresponding address into NODE NODE is not used by the slave application software TASKS See BITBUS specification Not used and not changed by the BITBUS communication software Can be used by the application task CMD RSP Contains the command or the response code Usually used by the application software Only upon the occurrence of an irrecoverable protocol error during the transmission of a command this field is set to E PROTOCOL ERROR by the BITBUS communication 246 BITBUS Support software and returned as a response Only bytes 3 n 7 are transferred on the BITBUS bytes 1 and 2 are used for local data control The type declaration of a message buffer is contained in the BITBUS header file typedef struct unsigned char buffer_full unsigned char res unsigned char length unsigned char route unsigned char node unsigned char tasks unsigned char cmd_rsp unsigned char parms 13 struct_msg_buf Transfer of Messages Data to transfer are passed to the BITBUS communication task by writing the start address of the message buffer into mailbox 7 The message buffers have to be declared in the application software Data transfer procedure 1 Prepare data in the transmit message buffer located in external RAM The following fields must be initialised LENGTH according to the number of bytes in the
119. ctions see os enable isr and os disable isr Interrupt sources assigned to a task are only enabled if the task is actually waiting for an interrupt to occur This prevents unexpected interrupts from occurring in the system If the running task is a RTX 51 fast task all RTX 51 task interrupts are disabled not ISR interrupts however relatively unimportant interrupt therefore cannot interrupt the fast tasks RTX 251 uses a more relaxed rule task interrupts are accepted anywhere outside of system code but a preemption takes place only if the interrupt task has a higher execution priority than the running task If the running task is a RTX 51 standard task or any RTX 251 task it can be interrupted by all interrupts which occur If another RTX 51 standard task or any RTX 251 task is waiting for one of these occurring interrupts it is made READY by RTX 51 251 However it is only allocated to the processor if it contains a higher priority than the currently running task standard scheduling All RTX 51 standard task or any RTX 251 task interrupts are disabled during the execution of system functions The system clock interrupt hardware Timer 0 or 1 is handled the same as for a fast task interrupt 25 26 Programming Concepts Handling of the 8051 MCS 251 Interrupt Priority Register The Interrupt Priority registers of the 8051 MCS 251 not to be confused with the software task priorities are not influenced by
120. cycles then perform this section else The int occurred within 10 system cycles task code Example 3 include lt rtx51 h gt Use rtx251 h for RTX 251 void multiple wait void task 19 static unsigned int xdata mes switch os_wait K_MBX K_TMO K_SIG 2 10 amp data case MSG_EVENT Message receipt from mbox 2 in DATA break case SIG EVENT Signal receipt break RTX 51 RTX 251 69 case TMO_EVENT No int or message receipt within 10 system cycles gt time out break 70 Programmer s Reference Signal Functions Function Call Overview Available functions are Function Name Parameter Description os send signal unsigned char task number Send a signal to a task Identification number of signal receiving task os clear signal unsigned char task number Clear signal of a task Identification number of task whose signal shall be cleared isr send signal unsigned char task number Send a signal to a task Identification number of signal receiving task os wait unsigned int event selector This is the general wait function of RTX Specification of requested wait 51 251 events Any combination of wait for Any combination of events may be interrupt message semaphore selected If one of the specified events signal time out and interval is occurs then task is made ready again allowed Optionally identification of i e waitin
121. d char i printf menu display command menu while 1 endless loop printf nCommand display prompt getline amp inline sizeof inline get command line input for i 0 inline i 0 i convert to uppercase inline i toupper inline i for i 0 inline i itt skip blanks switch inline i proceed to cmd function case D Display Time Command RTX 51 RTX 251 263 printf Start Time 02bd 02bd 02bd T End Time 02bd 02bd 02bd n start hour start min start sec end hour end min end sec printf type ESC to abort r os_create_task GET_ESC ESC check in display loop escape 0 clear escape flag display_time 1 set display time flag os clear signal COMMAND clear pending signals while escape while no ESC entered printf Clock Time 02bd 02bd 02bd r display time ctime hour ctime min ctime sec os wait K SIG 0 0 wait for time change ESC os delete task GET ESC ESC check not longer needd display time O0 clear display time flag printf n n break case T Set Time Command if readtime amp inline i 1 read time input and ctime hour rtime hour store in ctime ctime min rtime min ctime sec rtime sec break case E Set End Time Command if readtime amp inline i 1 read time input and
122. d in list of ready tasks Event for task occurs which has higher priority than running task it preempts it Task starts waiting for an event Processor is assigned to next ready task Figure 2 Task States The figure shows the three active task states and their interaction Task Switching The RTX 51 251 system section which the processors assigns to the individual tasks is referred to as the scheduler also dispatcher The RTX 51 251 scheduler works according to the following rules RTX 51 RTX 251 17 m Thetask with the highest priority of all tasks in the READY state is executed m If several tasks of the same priority are in the READY state the task thay has been ready the longest will be the next to execute m Task switchings are only executed if the first rule would have been otherwise violated exception round robin scheduling These rules are strictly adhered to and never violated at any time As soon as a task yields a state change RTX 51 251 checks whether a task change is necessary based on the scheduling rules Time slice task change round robin scheduling are executed if the following conditions are satisfied m Round robin scheduling must be enabled see configuration m The RUNNING task has the priority of 0 and is currently not executing a floating point operation see section Floating Point Operations page 34 m At least one task with the priority zero must be in the READY state m Th
123. d to the last notification it has read the objects data See Also can bind obj can unbind obj Example 1 Wait for an object include rtxcan h struct xdata can message struct rec mes Bind object with identifier 220 to this task can bind obj 220 for Endless loop Task waits until object 220 received If ok then handle object 220 if can wait Oxff amp rec mes C OK If data byte 1 of the object 220 is equal to 3 then if rec mes c data 0 3 Example 2 Wait for two objects include lt rtxcan h gt struct xdata can message struct rec_mes Bind objects with identifier 220 and 230 to this task can bind obj 220 can bind obj 230 for Endless loop Task waits until object 220 or 230 received RTX 51 RTX 251 171 can_wait 0xff amp rec mes Determine the received object if rec mes identifier 220 If data byte 1 of the object 220 is equal to 3 then if rec mes c data 0 3 else if rec mes identifier 230 Example 3 Unbind a bound object include rtxcan h Bind object with identifier 220 to this task can bind obj 220 counter 0 for Endless loop Task waits until object 220 received can wait Oxff amp rec mes increment counter counter if counter 20000 If object 220 is greater than or
124. demonstration hardware The example shown is written for RTX 51 running on a MCB 517A evaluation board Running it on a MCB251SB under RTX 251 requires minor modifications not shown here in detail On the RTX 251 distribution disk you can find a separate version for RTX 251 ready to run Principle of Operation TRAFFIC2 is a time controlled traffic light controller During a user defined clock time interval the traffic light is operating Outside this time interval the yellow light flashes The traffic flow of a simple crossing is controlled based upon a timing scheme Pedestrians have the possibility to reduce the wait time until the walk light goes on by pressing a request button On the other side approaching cars are detected by sensors thus shortening the red phase if there is no crossing traffic The Figure 21 shows the numbering of the traffic directions as they are used throughout this program The large arrows show car traffic and the small arrows show pedestrian traffic There is a repeated control cycle consisting of a total of eight different phases The length of the RED and GREEN phases may be shortened by the request buttons and or car detectors Wi RTX 251 257 Figure 21 TRAFFIC2 Direction Numbering Scheme Example 1 if a pedestrian presses the request button to cross direction no 2 then the GREEN phase of direction no 1 is terminated prematurely Because of this the pedestrian gets a WAL
125. ding to the 8051 conventions lowest to highest addresses Segment STACK Size given by the remaining free memory minimal 20 bytes Segment RTX FTASKDATA 3 Size configurable with RTX INTSTKSIZE minimal 9 bytes Segment RTX FTASKDATA 2 Size configurable with RTX INTSTKSIZE minimal 9 bytes 118 Configuration Segment RTX FTASKDATA 1 Size configurable with RTX_INTSTKSIZE minimal 9 bytes Figure 7 Stack Layout for RTX 51 m Segments 7 RTX FTASKDATA 1 2 3 The fast tasks stack areas are each used from one individual fast task Only the stack pointer must be reset during a task change especially fast task change possible The stack area of a fast task is used in the following manner by RTX 51 m 3 bytes are required for internal purposes m 2 bytes contain the start address of the tasks m 4 bytes maximum are required for RTX 51 system calls The size in bytes of the fast task stacks can be defined in the configuration file using the constant RTX_INTSTKSIZE It should not be selected smaller than 9 bytes m Segment STACK Segment STACK is used by RTX 51 for all standard task stacks In the case of a task change the current contents of this stack segment must be stored in the XDATA RAM in the task context of the corresponding task Afterwards the stack of the new task must be fetched in this segment see section External Memory XDATA below Segment STACK is used by RTX 51
126. e void task REC TASK priority 1 xdata unsigned char i xdata unsigned char command xdata unsigned char data 13 os Wait for a message no timeout specified endless wait _ wait K SIG Oxff 0 Test if message is in the buffer if bbs rx buf buffer full TRUE Read copy message command bbs rx buf cmd rsp if bbs rx buf length 7 for i 0 i bbs rx buf length 8 i data i bbs rx buf parms i Set flag for buffer empty bbs rx buf buffer full FALSE If required then send a signal to the BITBUS comm task if bs en sig to drv rtx send signal BBS TID Example 3 Transfer of Messages by a Slave st tx ruct msg buf xdata tx buffer Prepare data to send A Example with command response 30H and one data byte with the value 67H If the buffer tx buffer was used before make sure the buffer is empty and available see example 4 buffer buffer full TRUE tx buffer length 8 tx buffer route 0x90 tx buffer node bbs station address tx buffer tasks 0 tx buffer cmd rsp 0x30 tx buffer parms 0 0x67 transfer data to the BITBUS communication task RTX 51 RTX 251 251 os send message 7 amp tx buffer Oxff Example 4 Test if Transmission Buffer is Empty if tx buffer buffer full FALSE Buffer is empty o De allocate buffer or e write new data into trans
127. e application The methods can be combined in any form within a program The following summary illustrates the special features of the individual methods for handling interrupts Method C51 Interrupt Fast Task Standard Task Function ISR Interrupt Response very fast fast slow RTX 51 Time medium RTX 251 Interrupts Disabled very short critical system all system functions During System functions functions fast tasks other fast tasks Interruptable With 7 ISR ISR fast tasks standard tasks with higher priority 24 Programming Concepts System Resources many many RTX 51 few RTX 51 Used stack and usually extra stack and extra register stack and register bank register bank bank is shared with other few RTX 251 standard tasks on chip RAM for few RTX 251 context save off chip RAM for context save Interrupt Assignment static dynamic dynamic only one interrupt multiple interrupt multiple interrupt source per ISR sources per task sources per task allowed allowed Allowed RTX 51 251 some special all all System Calls There are considerable differences in timing between the different methods Please refer to timing specifications for more details The following points of emphasis deal with the features of the individual methods for handling interrupts mentioned above m C51 251 Interrupt Functions Very sudden periodically occurring interrupts without large coupling with the rest of the system on
128. e e e e e ce ce e ke e ke e e e e e ce e ce ce ke ke e e Se e e ce ce ce ke ke ke e e kv ke ke kk Ax e e ke e e e e e eee e e e e e e e e ee ce ce e e e e e e e e ce ce e e ke ke e e e e e ce e ce ce ke ke e e Se e e ce ce ce ke ke ke e ke kv ke ke ke e Ax ICANDEMO v k ke ke ke He ke e He He ke ke ke ke de ke ke ke He ke ke ke ke ke de ke k ke ke k k k k ke ke k k k k k k k k k k k k k k k k k k k k k k k k k kkk kkk kkk k k k ke ke ke ke ke ke ke ke ke k ke ke ke k k k ke k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k kkk k kkk kkk kkk k Purpose v S Simple demo program for the RTX 51 CAN Interface G Targetsystem G S Siemens C515C v Filename ICANDEMO C51 vi ke k ke ke ke ke ke He ke ke e ke ke He ke ke ke ke ke ke ke k ke ke k k k ke k k k k k k k k k k k k k AAA A k k k k k k k k k k k kk k kkk kkk kkk k Versionen ti 17 Jun 1997 K Birsen Version 0 1 First Version p Ae ke ke ke ke ke ke He ke ke ke k ke de ke k ke ke ke k k k k ke EKER k k k k k k k k k k k k k k k k k k k k k k k k k k k kkk k kkk kkk kkk k all rigths reserved by METTLER amp FUCHS AG CH 8953 DIETIKON e ck KK KK KKK IK e ke KK KKK KKK ehe e e ke ke KKK KKK he deje KKK He He ee ee eee ee dee KK KKK KK KK KK KK k IMPORTS Page yt te include lt rtx51 h gt RTX 51 function calls include rtxcan h CAN function calls DEFINES define SEND TASK
129. e for supported parameters RTX 51 RTX 251 bus_timing_0 CAN controller bus timing 0 register see the data sheet of the respective CAN controller bus_timing_1 CAN controller bus timing 1 register out_control CAN controller output control register see the data sheet of the respective CAN controller syncon CAN controller resynchronisation mode Resynchronisation can be performed on both edges of the bus signal recessive to dominant and dominant to recessive or on the recessive to dominant edge only depending on the syncon byte syncon 1 Synchronisation on both edges not recommended at bit rates over 100 Kbits s syncon 0 Synchronisation on the edge of a dominant level only if the bus level monitored at the last sample point was a recessive level sleep mode CAN controller SLEEP mode see data sheet of the CAN controller sleep mode 1 SLEEP mode on sleep mode 0 SLEEP mode off RTXCAN x51 currently supports SLEEP mode only with the Intel 82526 CAN controller and the Siemens 81C90 91 see parameter sleep br presc This byte is insignificant for all remaining controllers bus config CAN controller bus configuration register see the data sheet for details cpu interface CAN controller bus configuration register see the data sheet for details dummy Not used parameter 141 142 Return Value Note Example 1 CAN Support bit_length_1 CAN controller bit length 1 register
130. e he he de ke KKK HK de e ke e He e KKK KK KKK ee eek f I M GETLINE C Line Edited Character Input jo it 269 270 Glossary BRR RIKKI KKK KKK IKK IKK KKK de e He KKK IK AAI AAA AAA AAA AIA AAA AAA AAA AA AAA He ke ke include lt stdio h gt define CNTLQ define CNTLS define DEL 0x11 0x13 Ox7F define BACKSPACE 0x08 define CR define LF 0x0D Ox0A fee eee eee eee Line Editor f eee k k eee eee k void getline char idata line unsigned char cnt 0 char c do if c _getkey if c BACKSPACE if cnt 0 cnt line putchar putchar putchar else if c CNTLO amp amp c CNTLS 0x08 CEO 0x08 putchar line line cnt while cnt lt n 1 line 0 c amp amp CR eh c DEL c LF unsigned char n LF read character process backspace decrement count and line pointer echo backspace ignore Control S Q echo and store character increment line pointer and count check limit and line feed mark end of string Compiling and Linking TRAFFIC2 The project file TRAFFIC2 PRJ contains all settings to compile link and run the example under dScope 51 251 Testing and Debugging TRAFFIC2 m x7 x x7 x7 m 7 7 n7 K The dScope 51 251 is started automatically upon completion of the link step It
131. e last task change must have occurred after the selected system time interval see system function os set slice The system time interval can be changed dynamically during program execution The operating mode preferred by RTX 51 251 is the preemptive scheduling If desired by the user the tasks with the priority zero can additionally be managed by means of the round robin scheduling Task Classes RTX 51 see section below for RTX 251 basically recognizes two classes of tasks RTX 51 Fast Tasks m Contain especially short responses and interrupt disable times m Contain a separate register bank and a separate stack area register banks 1 2 and 3 m Contain the highest task priority priority 3 and can therefore interrupt standard tasks m All contain the same priority and can therefore not be mutually interrupted m Can be interrupted by C51 interrupt functions 18 Programming Concepts m A maximum of three fast tasks can be active in the system Internal RAM External RAM ack Area for ormal Tasks ack Area Fast Task 3 ack Area ast Task 2 ack Area Fast Task 1 Normal Task context Registerbank 3 for Fast Task 3 Normal Task Registerbank 2 for context Fast Task 2 Registerbank 1 for Fast Task 1 Normal Task Registerbank 0 for context Normal Tasks Figure 3 RTX 51 Task Classes and Memory Allocation RTX 51 Standard Tasks m
132. ea to be managed is defined by the user and is always located in the XDATA address space Several groups of various block sizes can be defined corresponding to the requirements of the application RTX 51 251 can manage a maximum of 16 pools with up to 255 blocks each Prototype signed char os create pool unsigned int block size void xdata memory unsigned int mem size Parameter block size defines the usable size of the individual blocks Only one pool can be defined per block size memory designates the start address of the memory area to be managed mem size defines the size of the area to be managed Return Value OK 0 The memory pool was produced successfully NOT OK 1 No memory pool could be produced The following exception occurred m The specified values for block size and mem size do not permit the creation of a pool m 16 pools were already defined See Also os get block os free block os check pool Note In addition to the memory blocks the management data of the system is also stored in the memory area available An additional two bytes are required by the system for each defined memory block For this reason the number of 86 Example Programmer s Reference produced blocks is sometimes smaller than the value calculated by mem size DIV block size include rtx51 h Use rtx251 h for RTX 251 void pool task void task 0 priority 0 int pool mem 1000 if os c
133. eception only D SEND 1 Data frame transmission only D REC R SEND 2 Data frame reception and remote frame transmission D SEND R REC Q3 Data frame transmission and remote frame reception with automatic answer to the remote frame With the Intel 82526 CAN controller objects defined as D SEND can also respond to remote frames The object definitions D SEND and D SEND R REC are identical to the Intel 82526 CAN controller RTX 51 RTX 251 Return Value Example 147 C_OK Object definition successful C_NOT_STOPPED can hw init or can stop must be called prior to can def obj C OBJ ERROR Attempt was made to define an pre existing object C TOO LONG data length cannot be greater than 8 bytes C INVALID TYPE Invalid object type C MEM FULL The object memory is full or 255 objects have already been defined All objects can be erased with can hw init include rtxcan h Define a send only object with the identifier 1200 and with 6 data bytes a can def obj 1200 6 D SEND 148 CAN Support can def obj ext Defines a new extended communication object for intel 82527 the SiemensC90 91 C515C only This function can only be executed after can hw init or can stop Objects can be defined until the object memory is full or the maximum number of 14 objects is reached Each object identifier must be unique The function returns an error status if attempt is made to d
134. efine an object twice The communication can be started after the completion of the object definition using can start Prototype unsigned char can def obj unsigned long identifier unsigned char data length unsigned char object type Parameter identifier is the communication object identifier corresponding to the CAN definition 0 65535 data length is the number of data bytes 0 8 object type is the object definition D REC 0 Data frame reception only D SEND 1 Data frame transmission only D REC R SEND 2 Data frame reception and remote frame transmission D SEND R REC Q3 Data frame transmission and remote frame reception with automatic answer to the remote frame Return Value C OK Object definition successful C NOT STOPPED can hw init or can stop must be called prior to can def obj ext RTX 51 RTX 251 Example 149 C_OBJ_ERROR Attempt was made to define an pre existing object C_TOO_LONG data_length cannot be greater than 8 bytes C_INVALID_TYPE Invalid object type C MEM FULL The object memory is full or 14 objects have already been defined All objects can be erased with can hw init include rtxcan h Define a send only object with the identifier 10000 and with 6 data bytes A can def obj ext 10000 6 D SEND 150 CAN Support can def last obj Defines the last standard communication object for intel 82527 the Siemens C5
135. egment 2 TSEGI TSEG2 TSEGI and TSEG2 are programmable as illustrated in the tables below 1 BTL cycle 2 BTL cycle 3 BTL cycle 4 BTL cycle 16 BTL cycle RTX 51 RTX 251 211 1 BTL cycle 2 BTL cycle 16 BTL cycle SYNCON CAN controller resynchronisation mode Resynchronisation can be performed on both edges of the bus signal recessive to dominant and dominant to recessive or on the recessive to dominant edge only depending on the SYNCON value SYNCON 1 Synchronisation on both edges not recommended at bit rates over 100 Kbits s SYNCON 0 Synchronisation on the edge of a dominant level only if the bus level monitored at the last sample point was a recessive level 82C200 80592 Programming Example Baud rate prescaler 9 Crystal frequency 16 MHz INSYNC 1 BIL cycle is always 1 SJW1 4BTL cycles TSEGI 4 BTL cycles TSEG2 3 BTL cycles SJW2 4BTL cycle SAMPLE 1 tert 2 9 1 16 MHz 1 25ms 1 bit cycle 1 4 3 1 25ms 8 1 25ms 10 ms Baud rate 16 MHz 2 9 1 8 100 Kbits s 212 CAN Support Variation in baud rate due to resynchronisation MAX baud rate 1 10ms 4 1 25ms 200 Kbits s MIN baud rate 1 10ms 4 1 25ms 66 6 Kbits s Parameters for CAN_HW_INIT BUS TIMING 0 C9H BUS_TIMING_1 A3H SYNCON 0 Siemens C515C Bus Timing Only a few differences exist between the bus timing calculation for the Intel and Siermen
136. eiving if an object is not already in the FIFO buffer 1 254 Number of RTX 51 251 system ticks until time out when no object received 255 Wait until an object is received infinite waiting buffer ptr is the pointer to a structure of the type CAN MESSAGE STRUCT in the XDATA memory The received object will be copied to this structure The structure CAN MESSAGE STRUCT defined in RTXCAN H is organised as depicted below c data 8 bytes RTX 51 RTX 251 159 for intel 82527 the Siemens C515C only c_data 8 bytes ident is the communication object identifier as defined in can_def_obj can_def_obj_ext can def last obj can def last obj ext c data Data bytes The data length is defined as eight bytes maximum data length for the communication object for simplification reasons User structures may be defined with a data length smaller than eight bytes the first two bytes must however always represent the IDENTIFIER field The communication software always sends or receives the data length as defined with can def obj Return Value C OK Object received C TIMEOUT Time out reached no object received C BUS OFF The CAN controller is in the off bus state because it has detected too many errors on the CAN bus restart with can start C CAN FAILURE Unrecoverable CAN error 160 Note See Also CAN Support The application always receives the newest object dat
137. emoving undesired messages m Notify to application task that a data frame was received with a signal or through the mailbox 7 m Sending data and remote frames as requested by the application The interface between the application tasks and the CAN communication task is built by function calls similar to the RTX 51 251 system calls The CAN interface enhances the RTX 51 251 system calls with functions common to the CAN communication 134 Figure 15 Concept Application Task2 MBX 7 CAN Communication Task Fast Task CAN Controller CAN Support RTX 51 RTX 251 135 Application Interface The CAN communication interface is similar to the RTX 51 251 interface Using RTXCAN x51 with the KEIL C51 C251 compiler is straightforward The header file RTXCAN H is provided to simplify application programming Each CAN function returns status information which can be tested by the application program For example include rtxcan h Define object 1000 if can def obj 1000 2 D REC C OK Return status indicates not okay 136 Function Call Overview Function Name Parameter can_task_create void can_hw init unsigned char parameter1 chip dependent register unsigned char parameter2 chip dependent register unsigned char parameter3 chip dependent register unsigned char parameter4 chip dependent register unsigned c
138. end hour rtime hour store in end end min rtime min end sec rtime sec break case S Set Start Time Command if readtime amp inline i 1 read time input and start hour rtime hour store in start start min rtime min start sec rtime sec break default Error Handling printf menu display command menu break RRR IATA AIA IAA hehehe IK KK KK HK ke e he he IK KK KK AAA he he he ke AIA AAA IAA AAA AIA AAA AA AAA signalon check if clock time is between start and end BRR IKK IK HK ke ke e ke IKK KK KK HK HK e he he IK IKK KK e ke khe he he he ke KK ke ke ck He He e He e ke IKK KKK ee eek f bit signalon if memcmp amp start amp end sizeof struct time lt 0 if memcmp amp start amp ctime sizeof struct time lt 0 amp amp memcmp amp ctime amp end sizeof struct time lt 0 return 1 264 Glossary else if memcmp amp end amp ctime sizeof start gt 0 amp amp memcmp amp ctime amp start sizeof start gt 0 return 1 return 0 signal off blinking on BRR RIKKI IA AAA AIA AIA AAA IAA AIA e e he he KK KKK AAA AAA he he he IKK ke AAA kk e ke e IKI KKK KKK e e eek f Task 3 blinking runs if current time is outside start fs amp end time s BERRI KI KKK He He e He KIKI IKK KKK HK e He IKI He He KKK KKK HHI He e He He KKK KKK e He He He e He He de He KKK KK ke He ke ke void blinki
139. end of segment 1 The segment is programmable from 1 to 16 fscl see bit length register BL 1 TSEG2 Timing segment 2 provides extra time for internal processing after the sampling point The segment is programmable from 1 to 8 fscl see bit length register BL1 RTX 51 RTX 251 189 SJW To compensate for phase shifts between the oscillator frequencies of the different bus stations each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal The synchronisation jump width SJW determines the maximum number of system clock pulses by which the bit period can be lengthened or shortened for re synchronisation The synchronisation jump width is programmable from 1 to 4 fscl see bit length register BL2 One Bit Time Sample Point Transmit Point Figure 19 Bit Timing Siemens C515C SYNC SEG is always one time quantum Sync Seg 1 tq tq BRP 1 1 fosc BRP Baud rate prescaler see bit timing register BTRO TSEGI1 Timing segment 1 determines the sampling point within a bit period This point is always at the end of segment 1 The segment is programmable from 1 to 16 fscl see bit timing register BTRI TSEG2 Timing segment 2 provides extra time for internal processing after the sampling point The segment is programmable from 1 to 8 fscl see bit timing register BTR1 190 CAN Support Sample Point Configuration Requirements Special requirements for the
140. er bank 1 If interrupt 7 occurs the ISR sends a signal to task 19 isr_send signal 19 74 Message Functions Function Call Overview Available functions are Function Name OS send message isr send message isr recv message Parameter unsigned char mailbox Identification number of mailbox a message shall be sent to Unsigned int message Message to be sent 2 byte value Unsigned int timeout Timelimit for waiting in case the message list is full unsigned char mailbox Identification number of mailbox a message shall be sent to unsigned int message Message to be sent 2 byte value unsigned char mailbox Identification number of mailbox a message shall be received from unsigned int xdata message Address of buffer 2 bytes in XDATA space where received message shall be stored Programmer s Reference Description Send a message to a mailbox If message list is full then the task will wait until enough space is available a timelimit may be chosen Send a message to a mailbox If message list is full at the moment then the message will be lost Receive a message from a mailbox if any is stored in it RTX 51 RTX 251 75 Function Name Parameter Description os wait unsigned int event selector This is the general wait function of RTX Specification of requested wait 51 251 events Any combination of wait Any combination of events may be for inter
141. er of the running task This is the number which was used in the task declaration Using this system function a C51 C251 function can for example determine the task from which it was called Prototype signed char os running task id void Parameter None Return Value The number of the task currently being executed by the processor is returned The task number corresponds to the number used in the task declaration in this case 0 255 See Also os create task os check task os check tasks Note A C51 C251 function can use this system function to determine from which task it was actually called Example include rtx51 h Use rtx251 h for RTX 251 void first task void task 0 priority 0 unsigned char task num task code Interrogate own task number task num os running task id task num contains 0 void main void Task stopped itself if os delete task 0 error handling 50 Interrupt Management Function Call Overview Available functions are Function Name Parameter unsigned char interrupt_nbr Vector number of interrupt source to be attached unsigned char interrupt_nbr Vector number of interrupt source to be attached unsigned int event_selector Specification of requested wait events Any combination of wait for interrupt message semaphore signal time out and interval is allowed Optionally identification of mailbox or semaphore os_att
142. erview Function Name Parameter Description os wait unsigned int event selector This is the general wait function of RTX Specification of requested wait 51 251 events Any combination of wait Any combination of events may be for interrupt message semaphore selected If one of the specified events signal time out and interval is occurs then task is made ready again allowed Optionally identification i e waiting for events is terminated of mailbox or semaphore unsigned int timeout Time out in system ticks Insignificant if no wait for time out is specified unsigned int xdata message Address of buffer 2 bytes in XDATA space where received message shall be stored Insignificant if no wait for message is specified RTX 51 RTX 251 65 os_wait Task function This is the general RTX 51 251 wait function All wait functions of tasks are executed using this function os wait can be used to wait for one or more events Events can be any combination of an interrupt signal interval time out or message token arrived If one of the specified events occurs the called task is made READY again OR ing the individual events Prototype signed char os wait unsigned char event selector unsigned char timer ticks unsigned int xdata message Parameter event selector specifies the events which are to be waited for The value is calculated according to the following simple equation event selector event1
143. ete 4 Program Example on rete ae eaa Eee Dale ranieri 5 Example Program for a Simplified RTX 51 251 Application eeeeeeeeee 5 Compiling and Linking the Program i 6 Extract from the MAP file generated by BL51 L251 eese 7 Debugging the Program i 8 Chapter 2 Installation eese eee e eee eee eerte eene eene eee tetas neo nesso seo nenneneose 11 Software Requirements 5 ned cte Ee fte Ee Fete re teni E eb Deve doe ud 11 Backing Up Your Disks coe eaten easier ten e aaa a 11 Installing the Software iii 12 Directory StU eiii Rm 12 Chapter 3 Programming Concepts eee e ecce cete e eere eene eee sense seo neeneneoso 15 Task Managemetit ceteris eere ee ER siva 15 Task States 1s eere aea tee tet te tees tet tete S 15 Task Switching 2t oie be EO EE Gee HD He Oi Dg reete 16 PAaSkiGlasses sci eodein oet eee ee es 17 Task Declaration crnan eoe e eee e en een ied 20 Interrupt Management oreet tee et ente ae 22 Methods for Interrupt Handling eene eene 23 Handling of the 8051 MCS 251 Interrupt Enable Register 25 Handling of the 8051 MCS 251 Interrupt Priority Register 26 Declaration of C51 C251 Interrupt Functions eene 26 Task Communication ina bee RPG ERU e o ee EEG EU Free 27 SIGNALS use ce de nde ee donehoi 27
144. event2 event3 event4 event5 mbxsem_nbr event K MBX 10H to wait for a message or a token event2 K INT 20H to wait for interrupt event3 K SIG 40H to wait for signal event4 K TMO 80H to wait for time out eventS K IVL 00H to wait for interval mbxsem nbr 0 7 Selects the mailbox from which a message is to be received This specification is only necessary if the waiting for a message semaphore K_MBX was also specified Note Simultaneous waiting on several mailboxes or semaphores is not allowed mbxsem nbr 8 15 Selects the semaphore from which a token is to be received This specification is only necessary if the waiting for a message semaphore K_MBX was also specified 66 Programmer s Reference Note Simultaneous waiting on several semaphores or mailboxes is not allowed Example 1 Wait for interrupt or signal event_selector K_INT K_SIG Example 2 Wait for message from mailbox 3 or time out event selector K_MBX K TMO 3 Example 3 Wait for interrupt or message from mailbox 1 event_selector K_MBX K_INT 1 Example 4 Wait for interrupt or token from semaphore 9 event_selector K_MBX K_INT 9 timer ticks determines the number of system intervals to occur until a time out event occurs if K_TMO was specified in event selector Determines the length of interval if K_IVL was specified in event selector Must be set to 0 or 255 if no wait for time ou
145. ew 81 Send Token 31 Send Message 29 Sequence Error 242 Serial Interrupt 231 Signal Clear 28 Functions 71 Overview 70 Send 28 Wait for 27 Signals 27 Sleep Mode 140 Software Requirements 11 Stack 232 Stack Requirements 172 stack defined 263 System Clock Function 92 Overview 91 System Functions 39 System Variables bbm en sig to app 230 bbm en sig to drv 229 bbm rx buf 229 bbm rx tid 230 bbs en sig to app 230 bbs en sig to drv 229 bbs rx buf 229 bbs rx tid 230 tx buffer 229 system defined 263 Task Classes 17 Communication 27 Declaration 20 Layouts 21 Management 46 Number 20 Priority 15 20 Register bank 21 Return value 20 Signals 27 States 15 Switching 16 task context defined 263 task interrupts defined 263 Task Management 15 task stack 119 task suspended defined 263 task switching defined 264 task defined 263 time out defined 264 TRAFFIC2 245 Wait Function 65
146. fer buffer Remote Access and Control Functions RAC The BITBUS standard defines the Remote Access and Control RAC commands as optional In the current version of the RTX 51 BITBUS communication software these are not implemented Only the RAC command 0 reset slave is implemented in the slave communication task All other RAC commands are sent to the application and may be implemented by the application task in an easy manner Outstanding Responses The message protocol defines that no more than seven commands from the master to a specific slave are outstanding i e without response To fulfil this requirement the slave software must guarantee that the eighth command message will not be accepted The RTXBITBUS 51 communication task fulfills this requirement The slave communication task sends a maximum of six command messages to the application The seventh command message remains in the SIU receiver buffer which guarantees that no more messages from the master are accepted The seventh command message is transferred to the application immediately as soon as a response has been sent and after the master has confirmed this response 252 BITBUS Support Error Handling Data Link Error Error handling in the layer data link protocol is defined by SDLC and the BITBUS specifications and is implemented according to these specifications Message Protocol Error The following error handling is implemented in the slave driver
147. ffer of the BITBUS communication task If the messages are not read from the buffer bbs rx buf bbm rx buf a SDLC protocol message buffer not ready is sent to the transmitting station The transmitter will not send any data until the receiver is ready again Receiving procedure 1 When the BITBUS communication task receives a message it performs the following Writes the message into the message buffer bbs rx buf bbm rx buf Sets the field BUFFER_FULL 1 buffer occupied Sends a signal to the receiving application task identified by bbs rx tid bbm rx tid 2 Upon receipt of the signal the receiving application task reads the message from the buffer bbs rx buf bbm rx buf Afterwards it sets the field BUFFER FULL 0 buffer free 248 BITBUS Support 3 Ifthe flag bbs en sig to drv bbm en sig to drv is set the receiving application task sends a signal to the BITBUS communication task The BITBUS communication task then recognises that the buffer is empty and ready for the next message Initialisation The following parameters are declared by the BITBUS communication task as variables and must be initialised by the application software Parameters used by master and slave stations m bbs rx tid bbm rx tid Task identification of the receiving application task m bbs konfig smd bbm konfig smd Hardware parameters The format corresponds to the hardware register SMD of the 8044 All parameters except NFCS
148. for most of the system functions when purposeful INCLUDE Files The declarations for the RTX 51 251 system functions and all constant definitions are contained in the files RTX51 H RTX251 H These declarations must be specified at the beginning of the source program in an INCLUDE statement include rtx51 h finclude lt rtx251 h gt Overview Initialize and Start the System os_start_system task_number Task Management os_create_task task_number os_delete_task task_number os running task id Interrupt Management os attach interrupt interrupt os detach interrupt interrupt os enable isr interrupt os disable isr interrupt os wait event selector timeout 0 oi set int masks ienO ienl ien2 oi reset int masks ien0 ienl ien2 Signal Functions os send signal task number os wait event selector timeout 0 RTX 51 RTX 251 41 os_clear_signal task_number isr_send_ signal task_number Message Functions os_send_message mailbox message timeout os_wait event_selector timeout message isr_send_message mailbox message isr_recv_message mailbox message Semaphore Functions os_send_token semaphore os wait event_selector timeout 0 Dynamic Memory Management os create pool block size memory mem size os get block block size os free block block size block Functions with the System Clock Os set slice timeslice os wait event selector timeout 0
149. from which the message is to be received message is a 2 byte variable in the XDATA area where the message read by mailbox is stored Return Value OK 0 A message was received and stored in message NOT OK 1 No message could be received One of the following exceptions was determined m Specified mailbox does not exist m No message was available mailbox empty See Also Os wait os send message isr send message os check mailboxes os check mailbox Note An Interrupt Service Routine ISR always waits only for the interrupt assigned to it Waiting for a message is therefore not possible Example include rtx51 h Use rtx251 h for RTX 251 void fast int void interrupt 7 using 1 C51 C251 int function wait for int 7 Uses register bank 1 static unsigned int xdata data Read from mailbox 2 in the variable data isr recv message 2 amp data 80 Programmer s Reference RTX 51 RTX 251 Semaphore Functions Function Call Overview Available functions are Function Name os_send_ token os wait Parameter unsigned char semaphore Identification number of semaphore token shall be sent to unsigned int event selector Specification of requested wait events Any combination of wait for interrupt message semaphore signal time out and interval is allowed Optionally identification of mailbox or semaphore unsigned int timeout Time out in system ticks
150. g Executive RTX 51 251 provides various types of interrupt handling The usage depends on the application requirements RTX 51 RTX 251 23 Methods for Interrupt Handling RTX 51 251 provides two different methods for handling interrupts One of the two methods can be additionally divided into two sub classes 1 C51 C251 Interrupt functions 2 RTX 51 251 task interrupts Fast task interrupts Standard task interrupts Method 1 corresponds to the standard C51 C251 interrupt functions which can even be used without RTX 51 251 also referred to as ISR Interrupt Service Routine When an interrupt occurs a jump is made to the corresponding interrupt function directly and independent of the currently running task The interrupt is processed outside of RTX 51 251 and therefore independent of the task scheduling rules With method 2 a fast or standard task is used to handle an interrupt As soon as this interrupt occurs the WAITING BLOCKED task is made READY and started according to the task scheduling rules This type of interrupt processing is completely integrated in RTX 51 251 A hardware interrupt is handled identical to the receipt of a message or a signal normal event within RTX 51 251 The possible methods to handle interrupts have specific advantages and disadvantages as described in greater detail in the following section One of the methods can be selected depending on the requirements of the interrupt source and th
151. g for events is terminated mailbox or semaphore For details see separate chapter about os wait unsigned int timeout Time out in system ticks Insignificant if no wait for time out is specified unsigned int xdata message Address of buffer 2 bytes in XDATA space where received message shall be stored Insignificant if no wait for message is specified RTX 51 RTX 251 71 os_send signal Task function The system operation os_send_signal sends a signal to another task If the task is already waiting for a signal then it is made READY again by this Otherwise the signal is stored in the signal flag of the addressed task Prototype signed char os_send_signal unsigned char task_number Parameter task_number is the identification of the task to where a signal is to be sent Return Value OK 0 Signal was sent successfully NOT_OK 1 No signal was sent The following exception occurred m The specified task does not exist m The signal flag was already set since the task still has not finished processing received a previously sent signal See Also os wait isr send signal os clear signal Example include lt rtx51 h gt Use rtx251 h for RTX 251 void xyz task void task 89 priority 0 task code Send signal to task 19 os send signal 19 72 Programmer s Reference os_clear_signal Task function The system operation os clear signal clears the signal flag
152. g task immediately receives the message It must not wait in this case Semaphores By means of the semaphore concept resources can be shared free of conflicts between the individual tasks In a multi tasking system there is often competition for resources When several tasks can use the same portion of memory the same serial I O channel or another system resource you have to find a way to keep the tasks out of each other s way The semaphore is a protocol mechanism which is used primarily to control access to shared resources mutual exclusion A semaphore contains a token that your code acquires to continue execution If the resource is already in use the requesting task is blocked until the token is returned to the semaphore by its current owner RTX 51 RTX 251 31 There are two types of semaphores binary semaphores and counting semaphores As its name implies a binary semaphore can only take two values zero or one token is in or out A counting semaphore however allows values between zero and 65535 RTX 51 251 provides a fixed number of eight semaphores of the binary type Semaphores allow the following operations m Wait for token m Return send token Wait for Token A task requesting a resource controlled by a semaphore can obtain a token from this semaphore by a wait operation see system function os wait If a token is available the task will continue its execution Otherwise it will be blocked until the
153. get status dones can def obj 0x31 8 D SEND done can get status dones can def obj 0x12 8 D SEND done can get status dones can def obj 0x22 8 D SEND done can get status dones can def obj 0x32 8 D SEND done can get status Send Request read answer objekt done can def obj 0x13 8 D REC R SEND done can get status dones can def obj 0x23 8 D REC R SEND done can get status dones can def obj 0x33 8 D REC R SEND done can get status Automatic answer to request object definition dones can def obj 0xff 8 D SEND R REC done can get status ts identifier OxFF for i20 i lt 7 i ts c_data i 0xFF done can write amp ts Set the RTX 51 System Clock to 10 ms 12MHz Clock os set slice 10000 Create the receive tasks os create task REC TASK 1 os create task REC TASK 2 os create task REC TASK 3 for inx 0 inx lt 13 inx count inx 0 start CAN controller done can start for L if count 1 gt 0 ts identifier 0x12 for i 0 i lt 7 i ts c data i 20x12 ts c_data 0 count 1 done can send amp ts done can get status done can request 0x13 done can get status count 1 228 CAN Support if count 2 gt O ts identifier 0x22 for i 0 i lt 7 i ts c data i 20x22 ts c_data 0 count 2 done can send amp ts done can get statu
154. h interrupt 0 error handling fore cy Endless loop os wait K INT Oxff 0 Wait for int task code 54 Programmer s Reference os_detach_interrupt Task function The system operation os_detach_interrupt cancels the assignment of an interrupt source to the calling task The only interrupt sources that can be used are those that were previously assigned to a task with os_attach_interrupt Prototype signed char os_detach_interrupt unsigned char interrupt Parameter interrupt designates the vector number of the desired interrupt source Permissible values are 0 31 RTX 51 251 stores a corresponding interrupt vector at address 8 interrupt 3 The vector number which is permissible depends on the microcontroller type used from the 8051 MCS 251 family RTX 51 251 checks whether the specified interrupt is supported by the microcontroller used see configuration The standard 8051 microcontroller supports the following vector numbers 0 External 0 interrupt 1 Timer counter 0 interrupt can be reserved for the system clock 2 External 1 interrupt 3 Timer counter 1 interrupt can be reserved for the system clock 4 Serial port Different processor versions of the 8051 MCS 251 family may support additional interrupt sources see literature of chip manufacturer Return Value OK 0 Function executed successfully RTX 51 RTX 251 55 NOT_OK 1 Function not executed
155. har parameter5 chip dependent register CAN Support Description Creates the CAN communication task Must be the first instruction to the RTXCAN x51 software CAN controller hardware initialisation defines the bus timing and the output driver configuration NOTE depending on the CAN controller used the naming and the purpose of the different parameters may vary see function call description for details RTX 51 RTX 251 Function Name can_def_obj can_def_obj_ext can_def_last_obj can_def_last_obj_ext can_send can_write can_receive can_bind_obj can_unbind_obj can_bind_last_obj can_unbind_last_obj Parameter unsigned int identifier Communication object identifier 0 2031 unsigned char data_length number of data bytes 0 8 unsigned char object_type type of object D_REC D_SEND D REC R SEND D SEND R REC unsigned long identifier Communication object identifier 0 65535 unsigned char data length number of data bytes 0 8 unsigned char object type type of object D REC D SEND D REC R SEND D SEND R REC unsigned long last msg mask Last object mask unsigned char data length number of data bytes 0 8 unsigned long last msg mask Last object mask 0 53687091 1 unsigned char data length number of data bytes 0 8 void xdata msg ptr pointer to a structure of type CAN MESSAGE STRUCT void xdata msg ptr pointer to a structure of type CAN ME
156. he BITBUS standard requires satisfaction of the following minimum requirements A Hardware Electrical B Software Data Link Protocol Message Protocol The RTX 51 BBx BITBUS communication software satisfies the minimum requirements of B and may be run with any hardware containing a Intel 8044 processor and satisfying the requirements of A The BITBUS standard uses a subset of SDLC as a base for the layer data link protocol Application Interface This chapter describes the interface between the application and the BITBUS driver task The interface for a master and a slave station are basically the same differences are mentioned in the document The BITBUS standard header is supported which contains five bytes and a data field containing maximum 13 bytes Release 2 of BITBUS with a total message size of 54 bytes is not supported as this would require too much internal RAM for data buffering Version 1 with 18 byte messages requires 2 18 bytes of internal RAM 18 bytes for the transmit buffer and 244 BITBUS Support 18 bytes for the receive buffer Version 2 with 54 bytes would require 2 54 bytes of internal RAM This would provide insufficient RAM for the application Since all Intel BEM processors with release 2 automatically boot with the small message size there is no problem to interface with this type of board as long as it is not switched to the larger message size Structure of the Message Buffer
157. hed OFF Please note that the switch B_RTX contained in file L51_BANK A51 V1 4b up required has to be set to 1 if bank switching is used See the PK51 User s Manuals for details about the bank switching implementation STACK CONFIGURATION Fast Task Stack for RTX 51 only 114 Configuration Enter here the number of the bytes to be used per Fast Task by stack and environment size More details about this configuration are shown in the section ndirect Addressable Internal Memory IDATA page 117 Standard Task Stack for RTX 51 only Enter here the number of bytes available per Standard Task to save stack data in the context More details about this configuration are shown in the section External Memory XDATA page 119 Task Stack Size for RTX 251 only Enter here the number of the bytes to be used per Standard or Fast Task by stack and environment size More details about this configuration are shown in the section Direct Addressable External Memory EDATA page 121 Reentrant Stack Size Enter here the number of bytes available per Task to keep its private reentrant stack More details about this configuration are shown in the section External Memory XDATA page 119 for RTX 51 page 119 for RTX 251 INTERRUPT OPTIONS Interrupt Table Base Enter here the desired base address for the 8051 interrupt table For a standard system this value is 0000H Note that this number
158. ilable functions are Function Name Parameter Description OS Set slice unsigned int timeslice Sets a new system time interval New timeslice in number of processor cycles 92 Programmer s Reference os_set slice Task function The system operation system os set slice sets the system time interval i e the time period between the interrupts of the system clock This period is the basic system interval for all RTX 51 251 time out functions and for the round robin scheduling Prototype signed char os set slice unsigned int timeslice Parameter timeslice defines the time interval in number of processor cycles corresponding to microseconds with a processor clock of 12 Mhz Permissible values are 1000 40000 Values above 10000 are recommended After os start system a time interval is automatically set to 20000 Return Value OK 0 Time interval was reset NOT OK 1 Function not executed since an invalid value specifies time Example include rtx51 h Use rtx251 h for RTX 251 void xyz task void task 0 priority 0 os set slice 3000 RTX 51 RTX 251 Debug Functions Function Call Overview Available functions are Function Name os_check_tasks os_check_task os_check_mail boxes os_check_mailbox os_check_sema phores os_check_sema phore os_check_pool Parameter t rix alltasktab xdata table Address of a memory area where atask state table can be stored
159. in the following way m O bytes are assigned by the system clock in the case of periodic occurrence of the system clock interrupt m 4bytes are required for RTX 51 system calls assigned by RTX 51 if the standard task is interrupted by an interrupt RTX 51 RTX 251 m 2 bytes contain the start 119 The minimum size of the standard task stack is 20 bytes The size cannot be configured directly Instead the entire IDATA memory is used for the standard task stack If this space is smaller than 20 bytes the linker issues an error message External Memory XDATA The XDATA memory of the processor is assigned by RTX 51 with the following areas fixed in size cannot be configured m Approximately 825 bytes for common system variables segments ORTX RTX SYS PAGE RTX RTX AUX PAGE RTX SEM PAGE and RTX RTX MBX PAGE If semaphore support is not configured then 128 bytes can be saved If mailbox support is not configured then 256 bytes can be saved m Segment O RTX USER NUM TABLE S with a size corresponding to the largest used task number 1 The following segment whose size can be configured is stored in XDATA memory by RTX 51 for each standard task Size max 256 bytes Segment 7RTX TASKCONTEXT x where x task number Area for the reentrant stack of the standard task compact reentrant stack Area for storing the task stack during a task change Area for storing registers during a task change Figure 8 Stand
160. in the stack are removed on a LIFO last in first out basis system Used instead of RTX 51 251 Real Time Operating System This designates program sections of RTX 51 251 task Independent section of an entire program Several tasks execute quasi parallel in a multitasking system The operating system allocates the processor time to the individual tasks The relevance of the individual tasks is controlled by priorities task interrupts These are all interrupts which are served via the system interrupt handler Non task interrupts are those types of interrupts which use a private interrupt handler C51 C251 interrupt function gt ISR task context This is to be understood as all types of information which must be stored during a task switching so that this task can be continued at the same position at a later time Depending on which time a task is to be stopped in its execution by a task switching the task context can be of various complexity task suspended Understood as a task switching with limited marginal conditions If a task is suspended so that another task can execute then suspended task must first be 274 Glossary reactivated in the next task switching Suspended tasks represent an especially efficient form of task switching task switching Procedure which stops a running task stores it in a form that it can be continued later at the same position and reactivates another task which is stored in the same way time
161. is flag and if set sends a signal to the BITBUS communication task identified by 242 BITBUS Support BBS_TID BBM_TID This informs the BITBUS communication task that the buffer is free and that the next message may be written into the buffer Application Task The application task waits for the following event by means of an os wait system call m Signal The receiver application task waits for a signal This signal is sent by the BITBUS communication task only if the flag bbs_en_sig_to_app bbs_en_sig_to_app is set Upon the occurrence of the signal the receiver application task reads the message from the buffer Requirements The BITBUS slave communication task requires the following 12 bytes stack 1 byte internal RAM for bit variables Approximately 37 bytes external RAM Approximately 1 2 Kbytes code Register bank 3 task number 0 priority 3 The BITBUS master communication task requires the following 12 bytes stack 1 byte internal RAM for bit variables Approximately 4 3 Kbytes external RAM Approximately 2 7 Kbytes code Register bank 3 task number 0 priority 3 RTX 51 RTX 251 243 BITBUS Standard In 1984 Intel defined a standard for a field bus called BITBUS In the document The BITBUS Interconnect Serial Control Bus Specification the standard is defined within the following groups Electrical interface Data link protocol Message protocol Remote access and control Mechanical Compatibility to t
162. isation jump width is programmable by bits SJW B and SJW A as depicted in the following table SJW B SJWA SJW 1 SUW 2 1 BTL cycle 2 BTL cyles 3 BTL cycles 4 BTL cycles Bus Timing Register 1 MSB SAMPLE TSEG 2 2 Time Segment 2 TSEG 2 1 TSEG 2 0 TSEG 13 Time Segment 1 TSEG 1 2 TSEG 1 1 TSEG 1 0 RTX 51 RTX 251 193 SAMPLE This determines the number of samples of the serial bus which are made by the CAN controller IF SAMPLE is set to low a bit is sampled once If SAMPLE is set to high three samples per bit are made SAMPLE O allows higher bit rates whereas SAMPLE 1 provides better rejection to noise on the bus SAMPLE 1 is not recommended at bit rates over 125 Kbits s Time Segment 1 and Time Segment 2 TSEG1 TSEG2 TSEGI and TSEG2 are programmable as illustrated in the tables below 1 BTL cycle 2 BTL cycle 3 BTL cycle 4 BTL cycle 16 BTL cycle 1 BTL cycle 2 BTL cycle 16 BTL cycle SYNCON CAN controller resynchronisation mode Resynchronisation can be performed on both edges of the bus signal Recessive to dominant and dominant to recessive or on the recessive to dominant edge only depending on the SYNCON value SYNCON 1 on both edges not recommended at bit rates exceeding 100 Kbits s 194 CAN Support SYNCON O on the edge of a dominant level only if the bus level monitored at the last sample point was a recessive level 82526 Programming Restrictions The following configur
163. ithout priority assignment i e when read the task which waits the longest first in the queue becomes the oldest messages in the mailbox Send a Message to a Mailbox Each task can send a message to any arbitrary mailbox In this case the message to be sent is copied in the message list The sending task therefore has free access to the message after the sending 30 Programming Concepts If the message list of the mailbox is already full during the sending the task is placed in the wait state entered in the write wait list It remains in the wait state until another task fetches a message from the mailbox and thus provides space As an alternative a time limit can also be specified for the sending after the waiting is aborted if the message could not be entered in the mailbox If the message list is not full when the sending occurs the message is immediately copied in the message list and the task must not wait Read a Message from a Mailbox Each task can read a message from an arbitrary mailbox If the message list of the mailbox is currently empty no message available the task is placed in the wait state entered in the read wait list It remains in the wait state until another task sends a message to the mailbox As an alternative a time limit can also be specified for the reading after which the waiting is to be aborted if no message is available If the message is not empty when reading then the readin
164. ive bit sendstop flag marks XOFF character Coke KH HK ke ke ke hehehe IK KK KK ke e e e he he he KKK KK ke kk ke e he he he IKK ke ke kk e He e de e IKI KKK KKK e KEK f putbuf write a character to SBUF or transmission buffer BERRI KKK HK HK KKK KIKI IK KK KK HK e He He KK IKK KKK HK KK KKK IKI KK KKK KKK KEK KIKI KKK KKK KKK EK f putbuf char c if sendfull transmit only if buffer not full if sendactive amp amp sendstop if transmitter not active sendactive 1 transfer the first character direct SBUF c to SBUF to start transmission else otherwize outbuf oend amp OLEN 1 c transfer char to transm buffr if oend ostart amp OLEN 1 0 sendfull 1 set flag if buffer is full BERRI KI KH AIA AIA KIKI IK KK KK ke e e e he he IK KK KK KKK HK KIKI KK AAA AAA de e He He IK KK AAA e eek f putchar interrupt controlled putchar function 2 H H e e He He KK HK ke ke ke IKI KK KK KKK e e e he he IK KK KK KKK He e he de he hehehe kk He He e de e AIA IAA AAA ke He e We char putchar char c TE boe expand new line character while sendfull wait for transmission buffer empty otask os running task id set output task number os wait K SIG 0 0 RTX 51 call wait for signal otask Oxff clear output task number putbuf 0x0D send CR before LF for lt new line gt while sendfu
165. kkkkkkkkkkkkkkkkkk xkkkkkkkk kxkkkkkkkkkkkkkkkkkkkkkkkkkkkk ke ke ke ke e e e ce ce ce e e ce e e e e e e e e e e e e e he e e e be e ee bebe eee de eee be e e e e e e e e e e e e e e e e e e e e e e e e 215 216 CAN Support BCAN DEMO PROGRAMM Fe e ke He He He He Fe e ke He He KEKE KKK KK KEKE He He He KK KKK KKK KK EKER KKK KKK LALA LALA ke ke ke ke ke k ke k k k k k k k k k k k kkk Fe e e He He He He Fe e ke He He He He He He He He He e He He He He He He e He He He He e He He He He He He e He ke He He He He ke ke He He He ke ke ke ke ke ke ke ke k k k k k k k k k k k kk k Purpose Simple demo program for the RTX 51 CAN interface Target system 8051 system with Philips 82C200 or 80592 CAN controller Hardware specific features reside in file BCANCONF A51 or CCONF592 A51 File name BCANDEMO C51 IE Y Y E Y Y Y A X E Y XR Y Y Y o T ok ke ke ke ke e e ce ce e ce e ce e e e ce e e e e e e e e e he hee e he e ehe e bee ee eee e bee e e be e e e e e e e e e e e e e e e e e e e e A hi Versions 19 November 1990 Th Fischler Version 0 1 First Version 14 October 1991 Th Fischler Version 1 0 adapted to RTX 51 V4 0 Y Y Fe e e Fe He He Fe Fe e ke He He He He He He He He He e He He He He He He e He He He He He He He He He He He e He ke He He He He e ke ke He ke ke ke ke ke ke k k k k k k k k kk k kk k kkk All rigths reserved by METTLER amp FUCHS AG CH 89
166. library as being generated by the PL M 51 compiler and therefore searches for the file PLM51 LIB in the current C5ILIB directory If no PLMS1 LIB file is contained in the C51LIB directory the dummy library file PLM51 LIB must be copied from the BITBUS disk to the current C51LIB directory All C51 libraries reside in the current C51LIB directory INCLUDE files BBM RTX H C 51 header file with the definitions for the BITBUS master communication task BBS RTX H C 51 header file with the definitions for the BITBUS slave communication task Example files BBM_DEMO C51 Demo program for the use of the BITBUS master task BBS_DEMO C51 Demo program for the use of the BITBUS slave task BBM_DEMO BAT Compile and link BBM_DEMO C51 BBS_DEMO BAT Compile and link BBS_DEMO C51 Source code files RTX PLM DCL RTX 51 system call declarations for the PL M 51 language 254 BBS_TASK P51 BBS UTIL A51 MAKEBBS BAT BBM_TASK P51 MAKEBBM BAT BITBUS Support Source code of the BITBUS slave task written in PL M 51 language Source code of the BITBUS slave task utilities written in KEIL 8051 assembler language Batch file to generate the library BBS20 LIB and the dummy library PLM51 LIB Source code of the BITBUS master task written in PL M 51 language Batch file to generate the library BBM20 LIB and the dummy library PLM51 LIB RTX 51 RTX 251 255 Chapter 8 Application Example Overview This chapter provides a
167. list mailbox WRITE wait list MO M1 and M2 contain the identification of the type of mailbox semaphore for which the task waits not defined if task does not wait for mailbox semaphore Permissible values are 0 7 If WM WN indicates a semaphore wait then 8 has to be added to this number to obtain the semaphore number Return Value OK 0 Function executed successfully NOT_OK 1 Function not executed See Also os_check_tasks Example include lt rtx51 h gt Use rtx251 h for RTX 251 void xyz_task void _task_ 0 _priority_ 0 t_rtx_onetasktab xdata table os check task 12 amp table 98 Programmer s Reference os_check_mailboxes Task function The system operation os_check_mailboxes returns information about the state of all mailboxes The information is stored in a table in XDATA memory to be declared by the user Prototype signed char os_check_mailboxes t_rtx_allmbxtab xdata table Parameter table is a table declared by the user in XDATA memory The system call stores the determined information in this table The table contains the following structure defined in RTX51 H RTX251 H typedef struct unsigned char message_cnt unsigned char read task cnt unsigned char write task cnt t rtx allmbxtab 8 The following is allocated for each mailbox three counter values for the number of stored messages message cnt number of tasks waiting for messages read task cnt
168. ll wait for transmission buffer empty otask os running task id set output task number os wait K SIG 0 0 RTX 51 call wait for signal otask Oxff clear output task number putbuf c send character return c return character ANSI requirement BERRI KKK ke HK HK ke e HRI KKK KKK KK HK ke e he he hehehe e ke KKK HK He ke he e He IK KK ke kk e ke e e e He He KKK KKK e e KEK f getkey interrupt controlled _getkey 2 H k e e He KK HK HK HK He e ke he he he KKK KKK e e e e he KKK KKK He He kk He He he he he KKK KKK He e ke e de e KKK de KK KKK e e eek f char _getkey void while iend istart itask os running task id set input task number os_wait K_SIG 0 0 RTX 51 call wait for signal itask Oxff clear input task number return inbuf istart amp ILEN 1 BERRI KKK HK HK e ke ke hehehe KK KK KKK KK e he he he he KK KK KKK He he he he de ke KKK ke ke He e ke e ke KIKI KKK KKK e eek f Serial serial receiver transmitter interrupt RTX 51 RTX 251 BERRI KKK ke e ke IAA AAA IAA AAA e e he he hehehe IAA AAA he he he ke AAA AAA KKK KKK KK KK KKK KEK f serial interrupt 4 using 1 use registerbank 1 for interrupt unsigned char c bit start_trans 0 if RI if receiver interrupt c SBUF read character RI 0 clear interrupt request flag switch c process character case CTRL_
169. ly infrequent communication with RTX 51 251 tasks etc Very important interrupts which must be served immediately independent of the current system state m Fast Task Interrupts Important or periodic interrupts which must heavily communicate with the rest of the system when they occur m Standard Task Interrupts Only seldom occurring interrupts which must not be served immediately RTX 51 shows considerable different response times for fast and standard tasks RTX 251 on the other side shows a superior performance based on the advanced MCS 251 architecture However the benefits in faster response times using fast tasks compared with standard tasks may be small especially if fast external RAM is used RTX 51 RTX 251 Handling of the 8051 MCS 251 Interrupt Enable Register RTX 51 251 must have sole control over the Interrupt Enable register of the 8051 MCS 251 in order to adhere to the dispatcher rules and guarantee error free execution of interrupt functions The INTERRUPT ENABLE registers of the 8051 MCS 251 are managed by RTX 51 251 and must not be directly manipulated by the user RTX 51 251 controls the INTERRUPT ENABLE bits of the 8051 MCS 251 according to the following rules ISR interrupts can interrupt all tasks and system functions at any time The ISR interrupts are disabled only during a few very short system code sequences The ISR interrupts can be disabled and enabled at the user s option using two system fun
170. maphore number 8 15 Timer When the task is blocked for a time out then this field shows the remaining number of system ticks to time out Signal State of task signal flag 1 set O reset m With the key F4 a list of all pre defined mailboxes may be displayed 10 Overview 0001H 1200H 34FFH 5888H A109 01 8 C2 IND I G Seqoogorwed Mbx Mailbox number 0 7 Msg Number of messages in this mailbox Read Number of tasks which are blocked for reading a message Write Number of task which are blocked for writing a message Messages Shows the messages contained in the mailbox m With the key lt F5 gt a list of all pre defined semaphores may be displayed a 3 1 1 a Sem Semaphore number 8 15 Tkn State of token flag 1 token available O else Wait Number of tasks which are blocked for a token RTX 51 RTX 251 11 Chapter 2 Installation This chapter explains how to setup an operating environment and how to install the software on your hard disk Before starting the installation program you must do the following m Verify that your computer system meets the minimum requirements m Make a copy of the installation diskette for backup purposes Software Requirements The following products are required to use RTX 51 251 together with Keil C51 C251 RTX 51 m C51 Compiler Version 5 02 or later m BLSI Linker for Code Banking Version 3 52 or later m A51 Assembler Version 5 02
171. mber of task to be started dispatching number used for task declaration os delete task unsigned char task number Terminates a task Number of task to be terminated os running task id void Returns the number identification of the running task 46 Programmer s Reference os_create task Task function The system operation os_create_task starts a function defined with the C51 C251 attribute _task_ as a RTX 51 251 task The task is assigned to the necessary operating resources and is placed in the list of READY tasks Prototype signed char os create task unsigned char task number Parameter task number identifies the task to be started The same number is to be used which was used in the task declaration 0 255 Return Value OK 0 Task was started successfully no error NOT OK 1 Task could not be started One of the following errors was determined m Register bank already assigned error only possible when starting RTX 51 fast tasks m Maximum number of tasks already running 16 standard tasks for RTX 51 16 tasks of any type for RTX 251 m Notask with this number was declared wrong number Task already started See Also os delete task os check tasks os check task n Note If the new task has a higher priority than the running task a task switching occurs to the new task Example include lt rtx51 h gt Use rtx251 h for RTX 251 void count task void task 2 priority
172. mp width is programmable by bits SJW B and SJW A as depicted in the following table SJIWB SJWA 1 BTL cycle 2 BTL cycles 3 BTL cycles 4 BTL cycles 214 CAN Support Bus Timing Register 1 MSB 0 TSEG 2 2 Time Segment 2 TSEG 2 1 TSEG 2 0 TSEG 1 3 Time Segment 1 TSEG 1 2 TSEG 1 1 TSEG 1 0 LSB Time Segment 1 and Time Segment 2 TSEG1 TSEG2 TSEGI and TSEG2 are programmable as illustrated in the tables below 1 BTL cycle 2 BTL cycle 3 BTL cycle 4 BTL cycle 16 BTL cycle 1 BTL cycle 2 BTL cycle 16 BTL cycle RTX 51 RTX 251 C515C Programming Example Baud rate prescaler 9 Crystal frequency 16 MHz SJW 4BTL cycles TSEGI 4 BTL cycles TSEG2 3 BTL cycles ter 9 1 16 MHz 0 625ms 1 bit cycle 1 4 3 0 625ms 8 0 625ms 5 ms Baud rate 16 MHz 9 1 8 200 Kbits s Variation in baud rate due to resynchronisation MAX baud rate 1 Sms 4 0 625ms 400 Kbits s MIN baud rate 1 Sms 4 0 625ms 133 3 Kbits s Parameters for CAN_HW_INIT BUS TIMING 0 C9H BUS_TIMING_1 34H Application Examples Example 1 Philips 82C200 80592 pragma large pragma debug pragma registerbank 0 pragma pagelength 80 pagewidth 110 RRR zhe He zhe KIKI HK KKK HK KKK KK IK HK IK HK IK He He He HK He He He He He He He He He He I HK KKK HK IK HK IK HK KKK KKK KKK METTLER amp FUCHS AG CH 8953 Dietikon Tel 01 740 41 00 kkkkkkkkkkkkkkkkk
173. mpatible 8051 MCS 251 system any of the MCS 51 251 based microcontrollers supported by RTX 51 251 m Intel 82526 82527 or Philips 82C200 or Siemens 81C90 91CAN controller addressable as memory mapped I O device anywhere in the XDATA space of the microcontroller XDATA address is user configurable Also Philips 80C592 83C592 87C592 Siemens C515C microcontroller with integrated CAN controller m The CAN controller interrupt must be connected to an external interrupt pin of the microcontroller the used interrupt is user configurable Note The Intel 82526 82527 the Philips 82C200and the Siemens 81C90 91 CAN controller generate an active low interrupt signal An external interrupt must be used which can handle active low interrupt signals either level or negative transition activated The external interrupts 4 5 and 6 of the 80515 535 microcontroller can only handle signals with a positive transition The Intel 82527 generates an interrupt on pinll if MUX 1 and DcR1 1 on pin 24 if MUX 0 Configuration Files A separate configuration file exists for each supported CAN controller Philips 82C200 Basic CAN gt BCANCONF AS1 Philips 80C592 Basic CAN gt CCONF592 A51 Intel 82526 Full CAN gt FCANCONF AS1 180 CAN Support Intel 82527 Full CAN gt GCANCONF AS1 Siemens 81C90 91 Full CAN gt HCANCONF AS1 Siemens C515C Full CAN gt ICANCONF A51 The configuration file must be assembled with
174. n wait for its signal flag system function os_wait It waits until its signal flag is set by another task system function os_send_signal After a signal is received the waiting task clears its signal flag again and enters the task state READY or RUNNING depending on priority relationships 28 Programming Concepts If the signal flag is already set when the task calls the wait function when the signal flag was previously set by another task then it immediately receives the signal The task does not first enter the WAIT state BLOCKED The waiting time for a signal can be restricted If the specified time has expired without receiving the signal the waiting task is made READY again with the return status time out see system function os_wait page 65 Send Signal Each task and each interrupt function can set the signal flag of any other task send a signal to this task Only one signal which has been sent can be stored per task signal flag As long as a task has not received a signal each additional signal sent is lost Clear Signal A task can clear the signal flag of any other task even its own This allows defined signal states in the system at any time Mailboxes By means of the mailbox concept messages can be exchanged free of conflicts between the individual tasks RTX 51 251 provides a fixed number of eight mailboxes Messages can be exchanged in words 2 bytes via these mailboxes In this case a
175. nd datas for inx 6 inx lt 11 inx ts inx identifier inx for i 0 i lt 7 i ts inx c_data i 0 done can_write amp ts inx Automatic answer to request object definition dones can def obj 12 8 D SEND R REC done can get status load identification and datas ts 12 identifier 12 for i20 i lt 7 i ts 12 c_data i 0 done can_write amp ts 12 Set the RTX 51 System Clock to 10 ms 12MHz Clock os_set_slice 10000 Create the receive tasks os create task REC TASK 1 os create task REC TASK 2 os create task REC TASK 3 for inx 0 inx lt 13 inx count inx 0 start Can controller done can start for if Object 1 received send Object 6 if count 1 gt 0 ts 6 c data 0 count 1 done can send amp ts 6 done can get status os_wait K_TMO 5 0 count 1 if Object 2 received send Object 7 if count 2 O ts 7 c data 0 count 2 done can send amp ts 7 done can get status os wait K TMO 5 0 count 2 if Object 3 received send Object 8 if count 3 O ts 8 c data 0 count 3 done can send amp ts 8 done can get status RTX 51 RTX 251 223 os_wait K_TMO 5 0 count 3 BRR hehe ee ee KK KKK KKK KKK ee e KK KKK KK KKK KKK KK KK KKK He e He KKK KK KK KK KK KR KK KK KK MAIN PROGRAM RRR RRR KKK e He
176. nd one or more BITBUS slave stations BBS TASK Driver task for the BITBUS slave communication BBM TASK Driver task for the BITBUS master communication RTX 51 Real Time Multitasking Executive for processors of the 8051 family RTX 51 RTX 251 239 Concept The BITBUS communication software runs as a fast task register bank 3 priority 3 and task number 0 under the RTX 51 Real Time Executive It handles the messages received from the BITBUS network as well as the messages to transfer as requested by the application It requires an application task which reads the received BITBUS messages from the buffer and handles the flags and signals as required The receiver application task is usually configured as a standard task The messages to be sent may be set up either by the same application task or by another one To ensure that no CPU time is required while waiting for messages the application task and the communication task function with the RTX 51 system call os wait Variables To understand the concept the user must be familiar with buffers and flags used by the application and the communication software bbs_rx_buf bbm rx buf Buffer for received BITBUS messages m Name must not be changed m Structure definition see section Structure of the Message Buffer page 244 m Declared by the BITBUS header file tx buffer Buffer for BITBUS messages to be transferred m Arbitrary name user selectable m Structure definition m
177. ng void _task_ BLINKING blink yellow light red 1720 all lights off yellowl 0 green 1 0 stop__1 0 walk__1 0 red 2 0 yellow2 0 green 2 0 stop__2 0 walk 2 0 while 1 endless loop phaseno 10 yellowl 1 yellow light on yellow2 1 os_wait K_TMO 30 0 wait for timeout 30 ticks yellowl 0 yellow light off yellow2 0 os_wait K_TMO 30 0 wait for timeout 30 ticks if signalon if blinking time over os_create_task LIGHTS start lights os delete task BLINKING and stop blinking RRR RIKKI KK HK KKK KIKI IK KK KK HHI KKK KK KK KKK HK KIKI KKK KKK KK He He e He He de de KKK KK e eek f Task 4 lights executes if cur time is between start P amp end time e BERRI KK KK HK HK e He e khe he hehe he he KK KK de e e e he he hehehe KKK KK ke He He he he he ke ke e KKK kk ke e de e ee He de He He He ee eek f void lights void task LIGHTS traffic light operation PHASE 9 kkk dir 1 all red dir 2 all red phaseno 9 red 1 1 red amp stop lights on yellowl 0 green_1 0 stop i I walk 1 0 red 2 1 yellow2 0 green_2 0 stop_ 2 1 walk 2 0 while 1 endless loop RTX 51 RTX 251 if signalon os create task BLINKING os delete task LIGHTS PHASE 0 dir 1 prepare for green dir 2 stick to red phaseno 0
178. ng real time applications m Non destructive bit wise arbitration m Broadcast message transfer m Data length 0 8 bytes The RTXCAN x51 software is used to implement a fast task under RTX 51 251 The CAN task serves as an interface between the user application tasks the Intel 82526 82527 the Siemens 81C90 91 C515C often called Full CAN or the Philips PCA82C200 called Basic CAN CAN controller The Philips 80C592 microcontroller is also supported with integrated CAN controller This user s guide assumes familiarity with the CAN specifications with the CAN controllers and with the Real Time Executive RTX 51 251 Refer to the following publications for detailed information on the CAN specifications and the CAN controllers m 82526 Serial Communications Controller Architectural Overview Intel Order Number 270678 001 m 82526 Controller Area Network Chip Intel Order Number 270573 003 m 82C200 Philips Stand alone CAN Controller Philips Functional Description No KIE 31 88 ME m Application of the PCA82C200 CAN Controller Philips Report No PCALH KIE 02 90 ME m INTEL 82527 Serial Communication Controller Architectural Overwiew February 1995 Order No 272410 002 m Siemens SAE81C90 91 Data Sheet 06 95 m Siemens C515C User s Manual 08 96 RTX 51 RTX 251 133 Concept The RTXCAN x51 software runs as fast task under RTX 51 251 and supports the following functions m Receiving objects from the CAN network m R
179. ng tasks for task communication and for all other services All RTX 51 251 system functions are reentrant and are implemented independent of the register bank used This chapter contains an extensive description of all RTX 51 251 system functions Each of the following descriptions covers m Function of the call m Declaration in C51 C251 like contained in RTX51 H RTX251 H m Explanation of the parameters m Explanation of the return value m Call example m Cross reference to other calls The function descriptions are contained in normal print examples are each printed in a different font Name Conventions The name of the respective system function describes its type of use m System functions whose name begins with os may be used solely by RTX 51 251 tasks m System calls whose name begins with isr_ may be used solely by C51 C251 interrupt functions m System calls whose name begins with oi may be used by RTX 51 251 tasks and by C51 C251 interrupt functions as well 40 Programmer s Reference Return Values Each system function returns an execution status as a return value This provides information whether the function could be executed successfully Other status information is passed to the caller in the same way In the description of the individual system functions the return values currently possible are explained including their meaning The value 0 is returned after an error free execution
180. ntied and the new binding is made Note All normal RTX 51 251 priority rules apply To ensure that the application task will be started immediately after receiving the bound object the application task must have a high priority higher than the task priority which calls CAN RECEIVE Objects can be bound to a RTX 51 251 fast task if a fast response time is required No more than 8 objects can be bound to application tasks 166 CAN Support See Also can unbind last obj Example gt see can wait RTX 51 RTX 251 167 can unbind last obj Unties a binding previously made between an application task and an object The untied object can now be received with can receive Prototype unsigned char can unbind last obj void Return Value C OK Object untied C OBJ ERROR Object undefined or never bound to the calling task See Also can bind obj Example see can wait 168 CAN Support can_wait can wait is related to can bind obj can bind last obj If an application task calls can wait and an object is received which is bound with can bind obj can bind last obj to this task then the task will be started Prototype unsigned char can wait unsigned char timeout void xdata buffer ptr Parameter timeout is the time out when no object is received Same definition as in RTX 51 251 0 No time out do not wait for receiving object 1 254 Number of RTX 51 251 system ticks until
181. obj 10 8 D SEND done can get status dones can def obj 11 8 D SEND done can get status load send identification and datas for inx 6 inx lt 11 inx ts inx identifier inx for i 0 i lt 7 i ts inx c_data i 0 done can_write amp ts inx Automatic answer to request object definition dones can def obj 12 8 D SEND R REC done can get status load identification and datas ts 12 identifier 12 for i20 i lt 7 i ts 12 c_data i 0 done can write amp ts 12 dones can def obj 13 8 D SEND dones can def obj 14 8 D SEND Set the RTX 51 System Clock to 10 ms 12MHz Clock os set slice 10000 Create the receive tasks os create task REC TASK 1 os create task REC TASK 2 os create task REC TASK 3 for inx 0 inx lt 13 inx count inx 0 start Can controller done can start for if Object 1 received send Object 6 if count 1 O ts 6 c data 0 count 1 done can send amp ts 6 done can get status os wait K TMO 5 0 count 1 if Object 2 received send Object 7 if count 2 O ts 7 c data 0 count 2 done can send amp ts 7 done can get status os wait K TMO 5 0 RTX 51 RTX 251 233 count 2 if Object 3 received send Object 8 if count 3 gt 0 ts 8 c_data 0 count 3 done can send amp ts 8 done
182. ocated by L251 for each declared task 126 Configuration If the size of this area is exceeded the linker issues a warning message If no reentrant functions were declared in the system the size of this segment is shrinked to the minimum value of 1 byte Summary of the User Configurable Values The following system constants are defined in configuration file RTXCONF A51 RTX 51 251 can be adapted to application specific requirements by means of these values m RTX CPU TYPE RTX code of microprocessor used For a detailed list of all supported 8051 MCS 251 family microprocessors see the following chapter m RTX SYSTEM TIMER 0 If hardware Timer 0 of the processor is to be used default 1 If hardware Timer 1 of the processor is to be used 2 If hardware Timer 2 of the processor is to be used not supported by all CPU s see comments contained in file RTXSETUP DCL m RTX IE INIT RTX IENI INIT RTX IEN2 INIT RTX 51 251 sets all unused ENABLE bits to 0 in the INTERRUPT ENABLE masks of the processor For some 8051 MCS 251 processors certain bits of the INTERRUPT ENABLE masks are used for purposes other than to enable disable the interrupt sources e g for 80515 the watchdog start bit in the IENI register The respective initial value of these types of special bits can be defined using these three constants However the actual INTERRUPT ENABLE bits must not be set to 1 with these constants RTX 51 251 must contain
183. ol 32 Return to Pool 32 XDATA for RTX 251 124 XDATA for RTX 51 119 Memory Pools Functions 85 Message Functions 76 Message Buffer 234 MS WINDOWS 109 multitasking defined 262 Object Identifier 145 147 Object Memory Size of 145 Size of 147 Outstanding Responses 241 parameter defined 262 PLMSI LIB 243 RTX 51 RTX 251 pointer defined 263 preemption defined 263 Program Example 245 RAC Commands 241 Read Message 30 real time defined 263 reentrant functions 120 reentrant stack 120 Remote Frames 145 Resynchronization 178 RTX 51 Bitbus Task 229 CAN Task 133 Fast Tasks 159 Priority Rules 159 RTXSI LIB 245 RTX 51 251 Functions 39 Include Files 40 isr recv message 79 isr send message 78 isr send signal 73 Name Conventions 39 oi reset int masks 62 oi set int masks 60 os check mailbox 100 os check mailboxes 98 os check pool 106 os check semaphore 104 os check semaphores 102 os check task 96 os check tasks 94 os clear signal 72 os create pool 85 os delete task 48 os detach interrupt 54 os disable isr 58 os enable isr 56 os free block 89 os get block 87 os running task id 49 os send message 76 os send signal 71 os send token 82 os set slice 92 os wait 65 277 Return Values 40 RTX 5I RTX 251 Functions os create task 46 Os start system 44 RTXCAN H 135 RTXCONF A51 126 128 RTXSETUP 109 RTXSETUP DCL 109 128 Sampling Point 178 181 SDLC 228 Semaphore 30 Functions 82 Overvi
184. ommunication task is created C NOT STARTED Errors while creating the CAN communication task The CAN task uses the task number 0 This number is not to be used for application tasks Under RTX 51 the CAN task is assigned to register bank 3 no special assignment is done under RTX 251 include rtxcan h Create the CAN task if can task create C OK CAN task create failed 140 CAN Support can hw init Basic initialisation of the CAN controller hardware Erases all defined communication objects After can hw init all communication objects can be redefined for RTXCAN x51 Prototype unsigned char can hw init unsigned char bus timing 0 unsigned char bus timing 1 unsigned char out control unsigned char syncon unsigned char sleep mode intel 82527 only unsigned char can hw init unsigned char bus timing 0 unsigned char bus timing 1 unsigned char bus config unsigned char cpu interface unsigned char dummy Siemens 81C90 91 only unsigned char can hw init unsigned char bit length 1 unsigned char bit length 2 unsigned char out control unsigned char sleep br prsc unsigned char clock control Siemens C515C only unsigned char can hw init unsigned char bit timing 0 unsigned char bit timing 1 unsigned char dummy unsigned char dummy unsigned char dummy Parameter Depending on the CAN controller type not all parameters shown are significant see declarations abov
185. on that no other node exists on the bus C BUS OFF The CAN controller is in the off bus state because it has detected too many errors on the CAN bus restart with can start C CAN FAILURE Unrecoverable CAN error Example include rtxcan h struct xdata can message struct send mes unsigned char xdata i Send the defined object 1200 over the CAN bus Init the send structure send mes identifier 1200 for i20 i lt 7 i send mes c data i i can send amp send mes 156 CAN Support can_write Writes new data to a pre defined object Can write does not send an object over the CAN bus as can_send does It only updates the data field in the object buffer When this object receives a remote frame the new data is sent via the CAN bus Prototype unsigned char can_write void xdata msg_ptr Parameter msg ptr is the pointer to a structure of the type CAN MESSAGE STRUCT in the XDATA memory The structure CAN MESSAGE STRUCT defined in RTXCAN H is organised as depicted below ident 2 bytes c data 8 bytes for intel 82527 the Siemens C515C only c data 8 bytes ident is the communication object identifier as defined in can def obj can def obj ext c data Data bytes The data length is defined as eight bytes maximum data length for the communication object for simplification RTX 51 RTX 251 Return Value Example 157 reasons User s
186. on should work error free regardless task priorities The priorities only serve for time optimizing Task States RTX 51 251 recognizes four task states READY All tasks which can run are READY One of these tasks is the RUNNING ACTIVE task RUNNING ACTIVE Task which is currently being executed by the processor Only one task maximum can be in this state at a time BLOCKED WAITING Task waits for an event SLEEPING All tasks which were not started or which have terminated themselves are in this state 16 Programming Concepts An event may be the reaching of a period of time the sending of a message or signal or the occurrence of an interrupt These types of events can lead to state changes of the tasks involved this on the other hand can produce a task switching task change task switch The states READY RUNNING and BLOCKED are called active task states since they can only be accepted by tasks which were started by the user see system function os_create_task SLEEPING is an inactive task state It is accepted from all tasks which were declared but still have not been started Processor is released by running task which starts waiting for an event Highest priority ready task starts running Event for task occurs Task has lower priority than running task it is inserted in Event for task with higher list of ready tasks priority occurs It preempts running task which is inserte
187. on software System utilising the Philips 82C200 80C592 CAN controller 4 2 Kbytes code 32 bytes XDATA space for the CAN controller hardware only 82C200 One bit internal RAM for RTXCAN x51 system variables 89 byte XDATA RAM for system variables Number of bytes defined with OBJ BUFFER LENGTH in the XDATA RAM RTX 51 251 mailbox number 7 and a fast task Number 3 for RTX 51 with the task number 0 are employed by the CAN communication software Adapting Stack Sizes Set the stack size for the fast tasks to 18 bytes minimum in the RTX 51 configuration file RTX_INTSTKSIZE in RTXSETUP DCL Set the stack size to at least 30 bytes in the RTX 251 configuration file QRTX STKSIZE in RTXSETUP DCL Linking RTXCAN x51 Except for GCANCONF A51 FCANCONF A51 HCANCONF AS1 BCANCONF A51 and CCONF592 A51 all modules of RTXCAN x51 are contained in the libraries RTXGCAN LIB intel 82527 RTXICAN LIB Siemens C515C RTXFCANLLIB intel 82526 RTXHCAN LIB Siemens 81C90 91 RTXBCAN LIB Philips 80C200 and CANP592 LIB Philips 80C592 182 CAN Support A system for the Intel 82526 CAN controller is built in the following way Assembling of FCANCONF AS1 Linking the application with FCANCONF OBJ and RTXFCAN LIB Special locate controls are not required for the RTXCAN x51 software A system for the Intel 82527 CAN controller is built in the following way Assembling of GCANCONF A51 Linking the application with GCANCONF OBJ and
188. on the SYNCON byte in the function call CAN HW INIT The sampling point is based on the number of BTL cycles programmed by TSEGI The sampling point is located at the end of TSEGI SAM 0 TSEGI is used to compensate delay times on the bus and to reserve time to tolerate one ore more miss synchronisation pulses caused by spikes on the bus line TSEGI is programmable from 1 187 188 CAN Support to 16 BIL cycles The number of samples which are made for one bit can be programmed One SAM 0 or three SAM 1 not recommended at bit rates over 125 Kbits s samples per bit may be made One sample allows higher bit rates whereas three samples gives better rejection to noise on the bus TSEG2 Defines the time between the sampling point and the transmit point programmable from 1 to 8 BTL cycles This segment is necessary to tolerate one or more miss synchronisation spikes on the bus line It is also necessary to guarantee sufficient time for the CAN controller to analyse the sample taken from the bus and to decide if it has lost arbitration One Bit Time TSEGI INSYNC SLWJ One BTL k Cycle Time Sample Point Actual Bit Length Nominal Bit Length Figure 18 Bit Timing Siemens 81C90 91 INSYNC The edge of the input signal is expected during the sync segment duration 1 system clock cycle 1 fscl TSEGI1 Timing segment 1 determines the sampling point within a bit period This point is always at the
189. one of the following errors was determined m Interrupt does not exist for this processor type m Interrupt source requested is not assigned to the calling task See Also os attach interrupt os wait Note More than one interrupt may be assigned to a particular task It is not allowed however to assign a particular interrupt source to more than one task Example include rtx51 h Use rtx251 h for RTX 251 void count task void task 2 priority 0 Assign external 0 interrupt to this task if os attach interrupt 0 error handling fors Endless loop os wait K INT Oxff 0 Wait for int task code After the int processing has finished the assignment to this task is canceled if os detach interrupt 3 error handling 56 Programmer s Reference os enable isr Task function The system operation os enable isr enables an interrupt source which is assigned to a C51 C251 interrupt function the assignment is determined in the interrupt function definition see section Declaration of C51 C251 Interrupt Functions page 26 The interrupt must be enabled with this function in order for an interrupt to trigger a C51 C251 interrupt function Prototype signed char os enable isr unsigned char interrupt Parameter interrupt designates the vector number which the desired C51 C251 interrupt function Interrupt Service Routine ISR is assigned to Permissible val
190. ort RTX 51 Interrupt table base address Mailbox support Semaphore support Graphical Configuration Utility The configuration utility allows an easy modification of all of the values above It uses a menu display to show the current contents of the configuration file RTXSETUP DCL All these values may be modified just by use of the cursor key mouse and the numeric keypad The graphical configuration utility may be run under MS WINDOWS 3 1 3 11 95 or NT The recommended way to use the configuration utility is to add it to the pull down menu of the uVision integrated development environment This may be done by 110 Configuration the user during the installation process or any time later A detailed description of how to do this is contained in Chapter 2 Installation On the other side the configuration utility RTXSETUP EXE may be started like any other EXE file under for example the Windows File Manager or Windows Explorer see Windows manuals for details about how to start an EXE file In the following description it is assumed that RTXSETUP EXE was added to the pull down menu of the ui Vision IDE by the user Running the Configuration Utility The configuration utilities for RTX 51 and RTX 251 are designed in the same way They differ only in particular configuration options explained in the sections Configuration Options for below Start up the configuration utility RTXSETUP EXE from the Vi
191. owever If an optimization level larger than three is used the local message variable should be provided with the attribute static C51 C251 does not store these types of variables in the registers If a wait for time out is combined with a wait for interval then the wait for time out supersedes In this case only a wait for time out is done A wait for time out is based on the actual system time while a wait for interval is based on the last wake up time of the calling task thus establishing a regular interval If there is no last wake up time stored for a task then the actual time will be used this is the case when waiting for interval the first time Waiting for a mailbox combined with waiting for a semaphore is not supported These two wait types are mutually exclusive Example 1 include lt rtx51 h gt Use rtx251 h for RTX 251 void delay task void task 54 priority 2 for Wait only for Time out os_wait K_TMO 100 0 The following functions are all 68 Programmer s Reference executed 100 system cycles Example 2 include lt rtx51 h gt Use rtx251 h for RTX 251 void count task void task 2 priority 0 Assign external 0 interrupt to this task if os_attach_interrupt 0 error handling for Endless loop Wait for interrupt or time out if os wait K_INT K_TMO 10 0 TMO_EVENT If int 0 does not occur within 10 system
192. owing section presents a general overview on the memory assignment of RTX 51 For RTX 251 users a similar description can be found in a following section Values which can be adapted by the user in the configuration file are characterized as such Direct Addressable Internal Memory DATA The DATA area of the processor is assigned by RTX 51 in the following way m Register bank 0 for standard tasks gt 8 bytes m Register banks 1 2 and 3 for fast tasks or C51 interrupt functions if defined gt Maximal 3 8 bytes RTX 51 RTX 251 117 m 31 bits for system flags in the bit addressable area segments IRTX RTX_BIT_REL BYTE_SEG RTX RTX BIT SEG and RTX FLT BITSEG m 35 bytes for general system variables segment RTX RTX RELBYTE SEG and RTX PBP m 3 bytes for each INTERRUPT ENABLE register supported by the 8051 processor are used segment RTX INT MASK RTXCONF gt 3 bytes for processors with one IE register e g 8051 gt 6 bytes for processors with two IE registers e g 80C515 gt 9 bytes for processors with three IE registers e g 80C517 Indirect Addressable Internal Memory IDATA RTX 51 stores the three maximum possible fast task stacks corresponding to the maximum three active fast tasks in the system and the stack for the standard tasks in the IDATA area of the 8051 The stacks are normally stored at the end of the IDATA area In this case the individual stack areas are assigned correspon
193. pplications it is a requirement to do something on a regular basis A periodic task activation can be achieved by the RTX interval wait function see system function os_wait The amount of time spent between two execution periods of the same task is controlled using os_wait and is measured in number of system ticks and may be set by the application Specific C51 C251 Support Apart from the use of C51 C251 interrupt functions for fast processing of hardware interrupts RTX 51 251 also supports the most extensions of the C51 C251 compiler The following sections provide an overview on the use of C51 C251 specific features together with RTX 51 251 C51 C251 Memory Models A RTX 51 251 application can use all memory models supported by C51 C251 SMALL COMPACT LARGE However the COMPACT model is normally reserved for reentrant functions see section Reentrant Functions below 34 Programming Concepts The selected memory model influences only the location of the application objects A part of the RTX 51 251 system variables is always stored in external XDATA memory All RTX 51 251 applications require external memory Applications without external memory are not possible Typical RTX 51 251 applications are normally implemented in the LARGE model Variables whose access is time critical can optionally be located in internal RAM Reentrant Functions Normal C51 C251 functions must not be simultaneously used by several task
194. pt sources e g for 80515 the watchdog start bit in the IEN1 register The respective initial value of these types of special bits can be defined using this constant Note that this number has to be entered in a hexadecimal representation SYSTEM FUNCTIONS Use Mailbox Support Click on this box to switch option On Off If switched OFF then no FIFO space is allocated and any operation that involves a mailbox FIFO will return an error status Use Semaphore Support Click on this box to switch option On Off If switched OFF then no FIFO space is allocated In this case any operation that involves a semaphore FIFO will return an error status Use Idle Mode Click on this box to switch option On Off If switched ON then the CPU is set to idle mode During idle mode the program execution is stopped while all peripherals including the interrupt controller stay active If switched OFF then a busy wait loop is done during system idle time 116 Configuration Please note that not all CPUs support this idle mode function see manufacturer s data sheet Do not select this option if the CPU is not able to support it Exiting from Configuration Upon completing the configuration the configuration utility may be exited by clicking on the OK button The successful modification of the selected configuration file is confirmed by a message box Message Nr 1 Data saved Memory Assignment for RTX 51 The foll
195. pts Interrupts are processed by fast or standard tasks of RTX 51 251 The methods of interrupt processing can be selected depending on the application The individual methods can also be combined in an application System Clock The RTX 51 251 system clock is based on hardware Timer 0 or 1 can be configured of the 8051 MCS 251 processor It supplies the basic pulse clock frequency required for the time outs and for the round robin scheduling Operating Resources RTX 51 see section below for RTX 251 requires the following 8051 system resources m CODE Memory Approx 6 to 8 Kbytes depending on the function scope used m Internal DATA and IDATA RAM 40 to 46 bytes for system data depending on the selected processor type 20 to 200 bytes for the stack can be configured by the user RTX 51 RTX 251 5 Register bank 0 for standard tasks register banks 1 2 and 3 for fast tasks or C51 interrupt functions m External XDATA RAM Minimal 450 bytes m Timer O or 1 for the system clock can be configured by the user RTX 251 see section above for RTX 51 requires the following MCS 251 system resources m CODE Memory Approx 3 to 7 Kbytes depending on the function scope used m Internal DATA and IDATA RAM 28 to 32 bytes for system data depending on the selected processor type m External EDATA RAM 32 bytes for system data 64 bytes up max 64 Kbytes for task system and reentrant stack data and con
196. re details about using a bank switching in your hardware m RTX INTBASE Normally the interrupt table is located at address 0000H For special hardware configurations like flash EPROM systems interrupts may need to be rerouted to a table at a different address If an address different than 0000H is used then the user has to supply code to reroute each used interrupt vector to an address with the offset declared as RTX INTBASE m RTX MAILBOX SUPPORT This flag determines if memory is allocated for the mailbox FIFO s or not If set to 0 then no wait for a mailbox is possible Associated RTX calls will return a NOT OK in this case Set to 1 if mailbox functions are to be used 128 Configuration m RTX SEMAPHORE SUPPORT This flag determines if memory is allocated for the semaphore FIFO s or not If set to 0 then no wait for a semaphore is possible Associated RTX calls will return a NOT OK in this case Set to 1 if semaphore functions are to be used m RTX USE IDLE This flag determines if the CPU is switched to idle mode during system idle time During idle mode the program execution is stopped while all peripherals including the interrupt controller stay active If switched OFF then a busy wait loop is done during system idle time Please note that not all CPUs support this idle mode function see manufacturer s data sheet Do not select this option if the CPU is not able to support it Number of the Processor Type Used
197. reate pool 128 pool mem sizeof pool mem error handling RTX 51 RTX 251 87 os get block Task function The system operation os get block gets a memory block from the memory pool referenced by the block size A pool which contains the required block size must have been created in advance parameters block size for os create pool Prototype void xdata os get block unsigned int block size Parameter block size is the desired block size A pool must exist which contains the blocks of the required size Return Value lt gt 0 Pointer to a memory block of desired size The pointer returned is of the type void it can therefore point to every data type application specific 0 null pointer No block could be allocated One of the following errors was determined m Noblockis available all used m No pool exists which contains the blocks of the required size See Also os create pool os free block os check pool include rtx51 h Use rtx251 h for RTX 251 Example void pool task void task 0 priority 0 int pool mem 1000 int xdata new ptr Create a memory pool with a block size of 2 bytes if os create pool 2 pool mem sizeof pool mem error handling Request an element if new ptr os get block 2 0 error handling Assign value 3291 to the received block new ptr 3291 88 Programmer s Reference RTX 51 RTX 251 89
198. ree files that can be found in the RTX sub directory of the C51 C251 tools directory RTX 51 RTX 251 259 TRAFFIC2 C contains the traffic light controller program which is divided SERIAL C GETLINE C into the following tasks Task 0 Initialize initializes the serial interface and starts all other tasks Task 0 deletes itself since initialization is only needed once Task 1 Command is the command processor for the traffic light controller This task controls and processes serial commands received Task 2 Clock controls the time clock Task 3 Blinking flashes the yellow light when the clock time is outside the active time range between the start and end times Task 4 Lights controls the traffic light phases while the clock time is in the active range between the start and end times Task 5 Button reads the pedestrian push button 1 and 2 depending on the active control phase It signals the Lights task Task 6 Quit checks for an ESC character in the serial stream If one is encountered this task terminates a previously specified display command Task 7 Detect1 waits for cars approaching from direction 1 It signals the Lights task Task 8 Detect2 waits for cars approaching from direction 2 It signals the Lights task implements an interrupt driver serial interface This file contains the functions putchar and getkey The high level I O functions printf and getline call these basic I O routines The
199. required the installation program copies the files into the sub directories listed in the following table RTX 51 RTX 251 13 Subdirectory Description BIN Executable files configuration utility ARTX51 RTX 51 configuration files sample applications RTX251 RTX 251 configuration files sample applications CAN CAN support BITBUS BITBUS support INC C include files ALIB Library files This table shows a complete installation Your installation may vary depending on the products you installed RTX 51 RTX 251 15 Chapter 3 Programming Concepts Task Management The main function of tasks within a Real Time Multitasking Executive is the time critical processing of external or internal events A priority can be assigned to the individual tasks to differentiate between which are most important In this case value 3 corresponds to the highest priority and value 0 corresponds to the lowest priority RTX 51 251 always assigns the READY task with the highest priority to the processor This task only maintains control over the processor until another task with a higher priority is ready for execution or until the task itself surrenders the processor again preemptive multitasking If several READY tasks exist with the priority 0 a task switching can optionally occur after completion of a time slice round robin scheduling Use the following guideline when assigning task priorities The applicati
200. rupt message semaphore selected If one of the specified events signal time out and interval is occurs then task is made ready again allowed Optionally identification i e waiting for events is terminated of mailbox or semaphore For details see separate chapter about os wait unsigned int timeout Time out in system ticks Insignificant if no wait for time out is specified unsigned int xdata message Address of buffer 2 bytes in XDATA space where received message shall be stored Insignificant if no wait for message is specified 76 Programmer s Reference os send message Task function The system operation os send message sends a message to a certain mailbox A message is a 2 byte value which can be defined by the user according to requirements either directly as a data value or as pointer to a data buffer If the message list of the mailbox is full the calling task is blocked The task is made READY again only after another task receives a message and therefore has made space or the selectable time limit has exceeded A mailbox can store a maximum of 8 messages A maximum of 16 tasks can wait at a full mailbox Prototype signed char os send message unsigned char mailbox unsigned int message unsigned char timeout Parameter mailbox is the identification of the mailbox Permissible values are O 7 message is the message to be sent 2 byte value timeout is the time limit for the wait time
201. s done can request 0x23 done can get status count 2 if count 3 gt 0 ts identifier 0x32 for i 0 i lt 7 i ts c_data i 0x32 ts c_data 0 count 3 done can send amp ts done can get status done can request 0x33 done can get status count 3 BRR RK IKI KKK HK KKK KKK KK IK IK KK HK KKK KKK IKI KKK KKK KK eee eee e KK ee KK KK KK KK IK MAIN PROGRAM RRR KERR KERRI KKK KKK e He e He de He e He de He he KK KKK KK KKK KKK KKK e He e He e He He He de He e KEK KKK EE void main void os_start_system SEND_TASK END of MODULE HCANDEMO Compiling and Linking the Program for the Siemens 81C90 91 c51 exe hcandemo c51 a51 exe hcanconf a51 a51 exe rtxconf a51 BL51 hcandemo obj hcanconf obj rtxconf obj rtxhcan lib rtx51 ramsize 256 Depending on the CAN controller chip and CPU used above shown sequence has to be modified slightly see examples contained on distribution disk RTX 51 RTX 251 229 Example 4 Siemens C515C pragma large pragma debug pragma registerbank 0 pragma pagelength 80 pagewidth 110 BRK HK IK KIKI HK AIA AA IATA IK HK IK HK IK HII He He He He He KKK HK He He He HK ARIA IK HK IK KKK KKK KKK BRR ke e H IKK KK HK KKK KK KK KKK IK ke ke HK KKK KIKI KI KK KK HK KKK KKK KKK KKK KKK KKK KKK KK METTLER amp FUCHS AG CH 8953 Dietikon Tel 01 740 41 00 e e ke e e e e e eee e e e e e e ee ee ce ce e ee
202. s Reserved 2 bytes Figure 12 RTX 251 Task Context Layout task running but currently interrupted by a C251 interrupt function External Memory XDATA The XDATA memory of the processor is assigned by RTX 251 with the following areas m Approximately 825 bytes for common system variables segments ORTX RTX SYS PAGE RTX RTX AUX PAGE RTX SEM PAGE and RTX RTX MBX PAGE If semaphore support is not configured then 128 bytes can be saved If mailbox support is not configured then 256 bytes can be saved m Segment O RTX USER NUM TABLE S with a size corresponding to the largest used task number 1 m Task reentrant stack areas one per declared task Reentrant stack data of task stack grows from higher to lower addresses RTX 51 RTX 251 125 Free stack space Figure 13 RTX 251 Reentrant Stack Layout task running or blocked Reentrant stack data of task stack grows from higher to lower addresses Reentrant stack data of C251 interrupt function Free stack space Figure 14 RTX 251 Reentrant Stack Layout C251 interrupt function running The segment shown in Figure 13 and Figure 14 whose size can be configured is stored in XDATA memory by RTX 251 for each task The size of the reentrant stack area can be defined in the configuration file using the constant RTX REENT STKSIZE Due to the page addressing mode its size is restricted to a maximum of 256 bytes Such an area will be all
203. s CAN controller The two controllers are fully communication compatible however when the baud rate is programmed the same C515C Bit Time Calculation Baud rate prescaler 1 BTL Cycle terL crystal 1 Bit Cycle terr INSYNC TSEGI TSEG2 terr f crystal Baud rate Baud rate prescaler 1 INSYNC TSEGI TSEG2 1 terr Programming the Siemens C515C Function CAN HW INIT allows the CAN controller bus timing to be programmed The parameters refer to C515C hardware registers in the following way RTX 51 RTX 251 213 BUS TIMING 0 Bus timing register 0 BUS TIMING 1 Bus timing register 1 Bus Timing Register 0 MSB SJW B Synchronisation Jump Width l6 SUWA 5 BRP 5 Baud Rate Prescaler 4 BRP4 3 BRP3 2 BRP2 1 BRP LsB o BRPO Baud Rate Prescaler BRP The BTL cycle time is determined by programming the six bits of the baud rate prescaler The BTL cycle time is derived from the system cycle time the system cycle time is twice the crystal time The desired baud rate is determined by the BTL cycle time and the programmable bit timing segments BRP 2 BRP5 2 BRP4 2 BRP3 2 BRP2 2 BRP1 BRPO Synchronisation Jump Width SJW The synchronisation jump width defines the maximum number of BTL cycles that a bit may be shortened or lengthened by one resynchronisation during transmission of a data frame or remote frame Synchronisation ju
204. s by the amount of available on chip RAM m Standard tasks require somewhat more time for the task switching because their context storage is located in slower external RAM RTX 251 supports a maximum of 16 tasks of fast or standard type active at a time RTX 51 RTX 251 3 RTX 51 251 tasks are declared as parameterless C functions with the attribute _task_ Task Communication and Synchronisation RTX 51 251 provides two mechanisms so that the individual tasks can communicate with each other and synchronize tasks which normally execute independent of one another m signals are the fastest form of task synchronisation No actual information is exchanged only a stimulus is activated for a task m Messages are exchanged via so called mailboxes Mailboxes allow the buffered exchange of data Tasks can be entered in queues for these in order to wait for a message to be received The individual messages are managed by the mailbox according to the FIFO principle First In First Out If several tasks are waiting for a message to be received the task which is waiting the longest first in the queue receives the message m Semaphores are simple protocol mechanisms that share common resources without access conflicts By use of token s resources may be managed in such a way that only one task at a time is allowed to use them If more than one task requests access to a resource then the first task will be granted access while the second
205. s or interrupt functions These functions store their parameters and local data in static memory segments For this reason this data is overwritten in the case of multiple calls In order to solve this problem C51 C251 provides reentrant functions see C51 C251 documentation In the case of reentrant functions the parameters and local data are protected against multiple calls since a separate stack is created for them RTX 51 251 supports the use of reentrant functions in the COMPACT model In this case a separate reentrant stack whose size can be configured is managed for each task Interrupt functions use the reentrant stack of the interrupted RTX 51 251 task m RTX 51 251 only supports reentrant functions in the COMPACT model m Each task contains a separate reentrant stack configurable in size m Reentrant functions may be used in combination with non reentrant functions of the SMALL and LARGE models Simultaneous use of reentrant functions and non reentrant functions is not allowed in the COMPACT model Floating Point Operations The following section is intended for users of C51 versions older than V5 0 No special restrictions apply for other C51 and C251 users In principle RTX 51 tasks can execute all types of operations with floating point numbers Since the C51 floating point library is not implemented as reentrant DK PK51 versions older than V5 0 a running operation must not be interrupted RTX 51 RTX 251 35 by
206. sed2 status flag pedestrian button 2 unsigned char cardetectedl status flag car detector 1 unsigned char cardetected2 status flag car detector 2 unsigned char phaseno Traffic control phase number Direction 1 sbit red 1 P1 2 I O Pin red lamp output sbit yellowl P1 1 I O Pin yellow lamp output sbit green 1 P1 0 I O Pin green lamp output sbit stop 1 P1 3 I O Pin stop lamp output sbit walk 1 P1 4 I O Pin walk lamp output sbit keyl P1 5 I O Pin self service key input sbit red 2 P4 2 I O Pin red lamp output sbit yellow2 P4 1 I O Pin yellow lamp output sbit green 2 P4 0 I O Pin green lamp output sbit stop 2 P4 3 I O Pin stop lamp output sbit walk 2 P4 4 I O Pin walk lamp output sbit key2 P4 5 I O Pin self service key input idata char inline 16 storage for command input line RRR RIKKI e ke KKK ke he he he IK KK KKH e e e he he IK IKK He ke kk He He he he he ke KK KKK He e ke e He e He He He He He He ee KEK f Task 0 init Initialize A BRR RIKKI e ke ke ke ke hehe he IKK KKK HK HK e he he he hehe KKK He kk He He he he he ke KKK ke kk e He e de e ke He He de KK KKK ee eek f void init void task INIT program execution starts here serial init initialize the serial interface os set slice 10000 set the system timebase to 10ms os create task CLOCK start clock t
207. sion integrated development environment IDE Now a file selection window allows to select the particular configuration file to modify The default file is RTXSETUP DCL located in the directory the configuration utility was started up Upon a successful file selection the main configuration menu appears It shows the different configuration options A particular option may be selected by clicking on it with your mouse When you are finished click on the OK button to store a modified configuration file A display box will tell you that it has been modified successfully When you need help then click on the Help button Context sensitive help is available by positioning the cursor on a particular option and pressing the F1 key If you want to abort the configuration a click on the CANCEL button will close the active window Repeat this step until the top window is closed A display box will confirm this premature program termination RTX 51 RTX 251 111 See the chapter Configuration Options below for a full discussion of all configuration options Important Notes The configuration utility RTXSETUP EXE modifies the selected configuration file but does not reassemble the module RTXCONF A51 The following command is required to re build RTXCONF OBJ RTX 51 A51 RTXCONF A51 DEBUG RTX 251 A251 RTXCONF A51 DEBUG Please note that the RTXCONF A51 expects a configuration include file named R
208. sole control over the INTERRUPT ENABLE bits m RTX INTSTKSIZE for RTX 51 only Stack size for each fast task see section Indirect Addressable Internal Memory IDATA page 117 Default value is 12 bytes RTX 51 RTX 251 127 m RTX EXTSTKSIZE for RTX 51 only Size of the area in the XDATA memory to store the standard task stack see section External Memory XDATA page 119 Default value is 32 bytes m RTX EXTRENTSIZE for RTX 51 only Size of the reentrant stack This is only required if reentrant functions are used in the system see section External Memory XDATA page 119 Default value is 100 bytes m RTX STKSIZE for RTX 251 only Stack size for each task system see section Direct Addressable External Memory EDATA page 121 Default value is 64 bytes m RTX REENT STKSIZE for RTX 251 only Size of the reentrant stack This is only required if reentrant functions are used in the system see section Reentrant Functions page 34 Default value is 64 bytes m RTX TIMESHARING 0 The task switching without round robin scheduling is used 1 Round robin scheduling is used m RTX BANKSWITCHING for RTX 51 only 0 No bank switching support is provided by RTX 51 Use this setting if your application does not require bank switching Some code and data dedicated to this purpose is left away in this case l The BL51 bank switching scheme is supported by RTX 51 See BL51 documentation for mo
209. ster 1 e JE a SAM TS2 2 TS2 1 TS2 0 TS1 3 TS1 2 TS1 1 TS1 0 0 0 1 0 0 0 1 1 ifs L TSEG1 TS1 1 fscl TSEG2 TS2 1 fscl JP n Bit Length Register 2 L PP see se eS oo Riot ii e cocci cela SIM SIW 1 SJW 2 SO 1 0 0 0 0 1 0 x Pa x SJWidth SJW 1 fscl SIM 1 J n sleep and br prescale sets bits BRPX Bit 0 Bit 5 of e Baud rate and SME Bit 6 of Control reg i j Baud rate prescaler reg G JX BRP5 BRP4 BRP3 BRP2 BRP1 BRPO 2 0 0 0 0 0 0 o 0 Control reg G P SMER if 127 JP m fscl BRP 1 2 fosc fosc 1 fcrystal fscl BRP 1 2 fcrystal e F3 x Bit length fbl TSEG1 TSEG2 1 fscl L Baud rate L BR fcrystal 2 BRP 1 TS1 TS2 3 J vin Out Control Register x mmm OCTP1 OCTN1 OCP1 OCTPO OCTNO OCPO OCM1 OCMO Nx 1 1 1 1 1 0 0 0 s a x B LRO BLR1 OUT CNTRL SLEEP BRP CLK CTRL done can hw init 0x23 0x42 OxF8 0x00 0x04 done can get status Receive Objects definitions done can def obj 0x10 8 D REC done can get status dones can def obj 0x20 8 D REC done can get status dones can def obj 0x30 8 D REC done can get status RTX 51 RTX 251 227 Send Objects definitions done can def obj 0x11 8 D SEND done can get status dones can def obj 0x21 8 D SEND done can
210. t or interval has been specified 0 254 Number of system intervals for which the event should wait If the value 0 was specified the system checks to see if one of the other specified events has already occurred interrupt already pending signal already set etc If no other event was specified or if no other event occurred the system function returns to the time out return value TMO EVENT Otherwise the corresponding event value is returned 255 Endless waiting message is a variable 2 bytes in the XDATA area where the message that is read by the mailbox is to be stored This parameter is insignificant if no wait for a mailbox message was specified a null pointer can be specified RTX 51 RTX 251 67 Return Value MSG_EVENT 1 A message was received from mailbox and stored in message INT_EVENT 2 An interrupt occurred SIG EVENT 3 A signal was received TMO EVENT 4 A time out or interval end occurred SEM EVENT 5 A token arrived from semaphore NOT OK 1 Task wait list is full more than 16 tasks waiting on a mailbox semaphore this error can only occur with the event K_MBX See Also os_send_message os_send_token isr_send_message isr_recv _message os_check_mailboxes os_check_mailbox os_set_slice Note If C51 C251 operates with an optimization level larger than OPTIMIZE 3 local variables can be kept in registers The function os_wait expects message variables in the XDATA area h
211. tached to RTX 51 251 tasks Prototype signed char oi reset int masks unsigned char ien0 unsigned char ien1 unsigned char ien2 Parameter ien ien1 ien2 represent the bit masks of the interrupt enable registers An interrupt source to be disabled explicitly has to set its associated bit For this parameter the same bit layout is used as defined for the corresponding interrupt enable registers Depending on the processor type used zero or more of these masks are insignificant Use as follows ienO ienl ien2 for processors with 3 interrupt enable registers ien0 ienl for processors with 2 interrupt enable registers ien2 is insignificant ienO for processors with 1 interrupt enable register ien1 and ien2 are insignificant Return Value OK 0 Function was executed successfully This return code is always used as this function does no parameter checking at all See Also oi_set_int_masks RTX 51 RTX 251 Note Example 63 Never change any interrupt enable bit whose interrupt source is attached to a RTX 51 251 task This function can not modify the global interrupt enable bit EA bit This bit can be manipulated by the user directly include rtx51 h Use rtx251 h for RTX 251 void isr manager void task 4 priority 1 Disable the serial int of a 8051 MCS 251 processor oi_reset_int_masks 0x10 0 0 task code 64 Programmer s Reference Wait Function Function Call Ov
212. tart_system Initialize RTX 51 251 and start the first task This function is normally called in the main program main of the C51 C251 application Prototype Parameter Return Value See Also Example signed char os_start_system unsigned char task_number task_number identifies the task to be started first The same number is to be used which was used in the task declaration 0 255 If the initialization was successful the first task begins to run Therefore the program normally never returns from this call If the program does however return from this call the initialization was not successful NOT_OK 1 System could not be started One of the following errors was determined m Generalerror during starting No task with this number was declared wrong number m The interrupt source which is normally assigned by the system clock Timer 0 or 1 is used by a C51 C251 interrupt function from the application This state is not allowed since the system clock would not function correctly as a result os create task include rtx51 h Use rtx251 h for RTX 251 void first task void task 0 priority 0 task code void main void if os start system 0 error handling RTX 51 RTX 251 45 Task Management Function Call Overview Available functions are Function Name Parameter Description os_create_task unsigned char task_number Creates a task and includes it in Nu
213. tasks Modifies physical registers and logical mirrors kept by RTX RTX 51 RTX 251 Function Name Parameter oi reset int masks unsigned char ienO ient ien2 Interrupt register masks containing a 1 at each bit position to be disabled 51 Description Disable one or more interrupt s not associated to RTX tasks Modifies physical registers and logical mirrors kept by RTX 52 Programmer s Reference os_attach_interrupt Task function The system call os_attach_interrupt dynamically assigns an interrupt source to the calling task Before wait is made for an interrupt using os_wait this must first be assigned to the task This assignment remains in force until it is canceled with os_detach_interrupt Each interrupt source can not be assigned to more than one task However several interrupt sources can be assigned to a single task a task can wait for several interrupts to occur Using os_attach_interrupt the corresponding interrupt is still not enabled in the processor hardware INTERRUPT ENABLE register All assigned interrupts are enabled see section Handling of the 8051 MCS 251 Interrupt Enable Register page 25 only after the task waits for an interrupt to occur with os wait Prototype signed char os attach interrupt unsigned char interrupt Parameter interrupt designates the vector number of the desired interrupt source Permissible values are 0 31 RTX 51 251 stores a corresponding
214. text storage m External XDATA RAM Minimal 450 bytes m Timer O or 1 for the system clock can be configured by the user Program Example The following simplified example illustrates the basic design of a RTX 51 251 application and the procedure for compiling and linking Example Program for a Simplified RTX 51 251 Application pragma large include rtx51 h RTX 51 definitions NOTE use rtx251 h for RTX 251 define PRODUCER NBR 0 Task number for the producer task define CONSUMER NBR 1 Task number for the consumer task void producer task void task PRODUCER NBR unsigned int send_mes Overview os create task CONSUMER NBR Create the consumer task send mes 1 for end less loop Send actual value of send mes to the mailbox 0 If the mailbox is full wait until there is room for the message os send message 0 send mes Oxff send mestt void consumer task void task CONSUMER NBR priority 1 t unsigned int rec mes for Read from the mailbox 0 to the variable rec mes Wait for a message if the mailbox is empty os wait K_MBX 0 Oxff amp rec mes Perform some calculations with rec mes void main void t Initialize the system and start the producer task os start system PRODUCER NBR Compiling and Linking the Program The most convenient way is to use pVision 51 251 for this purpose
215. the interrupt A maximum of eight objects may be bound to application tasks Prototype unsigned char can bind obj unsigned int identifier Parameter identifier is the identification as defined in CAN DEF OBJ of the object that must be bound to the calling task The binding will always be made with the task which calls can bind obj Return Value C OK Binding successful C OBJ ERROR Object undefined or object has the wrong type the parameter object type in the function call can def obj does not have the value D REC or D REC R SEND C MEM FULL 8 can bind obj have already been made can unbind obj can be used to until an object from a task C OBJ REBIND This message is only a warning the object was already bound toatask The prior binding was untied and the new binding is made RTX 51 RTX 251 Note See Also Example 163 All normal RTX 51 251 priority rules apply To ensure that the application task will be started immediately after receiving the bound object the application task must have a high priority higher than the task priority which calls CAN RECEIVE Objects can be bound to a RTX 51 251 fast task if a fast response time is required No more than 8 objects can be bound to application tasks 55 66 can unbind obj can bind see can wait 164 CAN Support can unbind obj Unties a binding previously made between an application task and an object
216. tion The system operation os disable isr disables an interrupt source assigned to a C51 C251 interrupt function This is used to temporarily inactivate an Interrupt Service Routine ISR Prototype Parameter Return Value signed char os disable isr unsigned char interrupt interrupt designates the vector number which is assigned to the desired C51 C251 interrupt function Permissible values are 0 31 C51 C251 stores a corresponding interrupt vector at address 8 interrupt 3 The vector number which is permissible depends on the microcontroller type used from the 8051 MCS 251 family RTX 51 251 checks whether the specified interrupt is supported by the microcontroller used see configuration The standard 8051 microcontroller supports the following vector numbers 0 External 0 interrupt 1 Timer counter 0 interrupt can be reserved for the system clock 2 External 1 interrupt 3 Timer counter 1 interrupt can be reserved for the system clock 4 Serial port Different processor versions of the 8051 MCS 251 family may support additional interrupt sources see literature of chip manufacturer OK 0 Function was executed successfully RTX 51 RTX 251 See Also Example 59 NOT_OK 1 Function not executed one of the following errors was determined m Interrupt does not exist for this processor type m No C51 C251 interrupt function exists for this vector number os_enable_isr
217. tion os_create_pool unsigned int block_size Create and initialize a memory pool which Size of memory blocks to be contains blocks of a selectable size managed in pool void xdata memory Address of user defined memory area to be used for pool unsigned int mem size Size of memory area to be used for pool number of bytes os get block unsigned int block size Obtain a block of memory from a pool Identification of pool from which a memory block shall be obtained Memory pools are identified by the size of blocks they contain os free block unsigned int block size Return a memory block to a pool Identification of pool to which a memory block shall be returned Memory pools are identified by the size of blocks they contain void xdata block The starting address of the block to be returned Example for a Buffer Pool Application In many data collecting systems data is acquired by a fast interrupt driven routine typically an ISR and then passed to one or more tasks for subsequent processing Basically there are two ways to implement the data passing between such an ISR and tasks 84 Programmer s Reference 1 The complete collected data is written to one or more of the mailboxes that tasks are waiting for 2 The collected data is stored in a buffer and the buffer address is passed via one or more mailboxes to tasks A pool of buffers is used The task which processes the buffer data finally returns the freed
218. truct unsigned char token flag unsigned char task count unsigned char wait tasks 15 t rtx onesemtab The following is allocated for the desired semaphore the state of the token flag 1 token available O no token number of tasks waiting for token s and a list of all waiting tasks if any Use semaphore_number 8 as index to this table OK 0 Function executed successfully NOT OK 1 Function not executed RTX 51 RTX 251 105 See Also os_check_semaphores Example include lt rtx51 h gt Use rtx251 h for RTX 251 void xyz task void task 0 priority 0 t rtx onesemtab xdata table if os check semaphore 12 amp table error handling Evaluation of the table 106 Programmer s Reference os_check_pool Task function The system operation os_check_pool returns information about the use of all blocks of a memory pool The information is stored in a table to be declared by the user Prototype Parameter Return Value signed char os check pool unsigned int block size t rtx blockinfo xdata table block size selects the pool where information is to be returned block size is the block size of the desired pool table is a table which was declared by the user The system call stores the determined information in this table The table contains an entry for each block of the pool and contains the following structure defined in RTX51 H RTX251 H
219. tructures may be defined with a data length smaller than eight bytes the first two bytes must however always represent the IDENTIFIER field The communication software always sends or receives the data length as defined with can_def_obj can_def_obj_ext C_OK Object data updated C_OBJ_ERROR Object undefined or object has the wrong type the parameter object type in the function call can def obj does not have the value D SEND or D SEND R REC C CAN FAILURE Unrecoverable CAN error include rtxcan h struct xdata can message struct send mes unsigned char xdata i Write new data to the defined object 1200 Init the structure write mes identifier 1200 for i20 i lt 7 i write mes c data i i can write amp write mes 158 CAN Support can_receive Receives all objects that are not bound see can bind obj can bind last obj via the RTX 51 251 mailbox 7 The waiting objects are handled in a FIFO First In First Out manner i e the first received object top of the queue will be removed first When the FIFO buffer is full eight objects received and the application does not read from the buffer with can receive then all further objects are lost Prototype unsigned char can receive unsigned char timeout void xdata buffer ptr Parameter timeout is the time out when no object is received Same definition as in RTX 51 RTX 251 0 No time out do not wait for rec
220. ual Organization This user s guide is divided into eight chapters Chapter 1 Overview provides a brief overview on RTX 51 251 Chapter 2 Installation describes the installation of RTX 51 251 and provides an overview on the necessary software tools Chapter 3 Programming Concepts describes the ways RTX 51 251 functions can be used by your application and how the kernel handles C51 C251 specific aspects Chapter 4 Programmer s Reference contains a detailed listing of all RTX 51 251 system functions including examples Chapter 5 Configuration describes the adaptation of RTX 51 251 to various members of the 8051 MCS 251 processor family and the system configurable constants Chapter 6 CAN Support introduces the driver software for a CAN bus interface using different controller hardware Chapter 7 BITBUS Support introduces the driver software for a BITBUS interface using the intel 8044 on chip controller Chapter 8 Application Example describes as an example the software required to control the traffic lights at an intersection vi Content Contents Chapter 1 OVErVICW ssiscicscsscectcsiscececssssvettsesscontessoeoacesosececesssecsceessuceseceveccseesseeee 1 Summary of the Major System Features eee eee eee 2 BK N EEEE E NO E NO E saath neri 2 Interrupt System zio Re TRE AT E TATT 4 Systeni Clock s cete T T N EEEE A 4 Operating Resources isisisi i pde e e a e d
221. ues are 0 31 C51 C251 stores a corresponding interrupt vector at address 8 interrupt 3 The vector number which is permissible depends on the microcontroller type used from the 8051 MCS 251 family RTX 51 251 checks whether the specified interrupt is supported by the microcontroller used see configuration The standard 8051 microcontroller supports the following vector numbers 0 External 0 interrupt 1 Timer counter 0 interrupt can be reserved for the system clock 2 External 1 interrupt 3 Timer counter 1 interrupt can be reserved for the system clock 4 Serial port Different processor versions of the 8051 MCS 251 family may support additional interrupt sources see literature of chip manufacturer RTX 51 RTX 251 57 Return Value OK 0 Function was executed successfully NOT_OK 1 Function not executed one of the following errors was determined Interrupt does not exist for this processor type m No C51 C251 interrupt function exists for this vector number See Also os disable isr Example include rtx51 h Use rtx251 h for RTX 251 void fast int void interrupt 7 using 1 C51 C251 int function waits for int 7 Uses register bank 1 ISR code void isr manager void task 4 priority 1 Enable the interrupt with vector number 7 if os enable isr 7 error handling task code 58 Programmer s Reference os disable isr Task func
222. urpose x Simple demo program for the RTX 51 CAN Interface x Targetsystem 8051 system with Siemens 81C90 91 CAN Controller HW specific features resides in the file HCANCONF A51 224 CAN Support Filename HCANDEMO C51 e KIKI KKK RIK KI ke ke KK IK e e e ke EI KKK e He e KK IK RIKKI e e e e e de He He He KEKE ke ke k KK Versions vi 21 Maerz 1996 K Birsen Version 0 1 First Version KIKI KI KKK ke LICEI II ELITE EI LITI EEE koe He e e e koe He He He He KKK e e ke KKK all rigths reserved by METTLER amp FUCHS AG CH 8953 DIETIKON ccce KK I KK e e e ke ke ke KK KK KKK KK e e ke KKK KKK KKK KKK KK KK KKK eee eee KK KK KK KKK KR KK KK KK IMPORTS L include lt rtx51 h gt RTX 51 function calls include rtxcan h CAN function calls DEFINES define SEND TASK define REC TASK 1 define REC TASK 2 define REC TASK 3 LJ M A Global variables CAN send and receive data struct can message struct xdata ts struct can message struct xdata tr unsigned char i j done unsigned int inx unsigned int ident unsigned char xdata count 14 BRR KKK IKK KK HK ke ecce hehe hehe de eee e He KKK KK KKK IKK ek ek eee eee eee e He KK KK KK KK KK KK IK Test Tasks sy RRR e H de e KK He ke HK KKK KKK he e e KK KKK e He KKK IKK He e KK HH e He He He He He He e He KK KKK KK KR KKK ke ke ke ke void rec task 1 void task REC_TASK_1
223. ust conform to section Structure of the Message Buffer page 244 m Declared by the application software bbs en sig to drv bbm en sig to drv Flag to enable disable signal to BITBUS communication task Meaning of name ENable SIGnal TO DRiVer Declared by the BITBUS header file Configured by the BITBUS communication task Must not be changed by the application software 240 BITBUS Support m Must be tested by the application software after every read of bbs_rx_buf bbm_rx_buf and if set a signal must be sent to the BITBUS communication task bbs en sig to app bbm en sig to app Flag to enable disable signal to receiver application task Meaning of name ENable SIGnal TO APPlication Declared by the BITBUS header file Configured by the application software Not changed by the BITBUS communication software Tested by the BITBUS communication software after every transfer of a message on the BITBUS and if set a signal is sent to the application task m Recommendation Set to 1 at initialisation and never change it wait for BITBUS messages by means of os wait for a signal bbs rx tid bbm rx tid Task identification number of receiver application task m Declared by the BITBUS header file m Loaded by application software after starting up the receiver application task m Used by the BITBUS communication task to send a signal to this task when a BITBUS message has arrived BBS TID BBM TID Task identification number of BI
224. utine ISR Function A C51 C251 interrupt function sends a message to a certain mailbox A message is a 2 byte value which according to requirements is either directly defined by the user as a data value or as a pointer to a data buffer If the message list of the mailbox is full the message is lost A mailbox can store a maximum of 8 messages Prototype signed char isr send message unsigned char mailbox unsigned int message Parameter mailbox is the identification of the mailbox Permissible values are O 7 message is the message to be sent 2 byte value Return Value OK 0 Message was sent successfully NOT OK 1 Function was not executed The specified mailbox does not exist See Also Os Wait os send message isr recv message os check mail boxes os check mailbox Example include lt rtx51 h gt Use rtx251 h for RTX 251 void fast_int void interrupt 7 using 1 C51 C251 int function wait for int 7 Uses register bank 1 Sends value 1 to mailbox 2 isr send message 2 1 RTX 51 RTX 251 79 isr_recv_message Interrupt Service Routine ISR Function A C51 C251 interrupt function receives a message from a mailbox providing one is available C51 C251 interrupt function can not wait at a mailbox if no message is available Prototype signed char isr recv message unsigned char mailbox unsigned int xdata message Parameter mailbox is the identification of the mailbox
225. wn by an interrupt in a single processor system whereby no guarantee can be made for the complete execution of individual program sections without additional measures being taken application These are programs or program sections written by the user of RTX 51 251 ISR Interrupt Service Routine This designates a processor which is jumped to in the fastest way when an interrupt occurs direct via interrupt vector It is executed for each interrupt from the start of the function up to the end It runs asynchronous to the operating system and may only call a restricted set of system functions self synchronized multitasking Software system allowing several independent program sections to be executed virtually in parallel parameter The value that is passed to a macro or function RTX 51 RTX 251 273 pointer A variable that contains the address of another variable function or memory area preemption If an event e g interrupt occurring message or signal etc occurs which a task has waited for this having a higher execution priority than the currently running task this triggers a task switching This means the running task is preempted real time Real time describes software whose functional requirement is restricted to certain time limits stack An area of memory indirectly accessed by a stack pointer that shrinks and expands dynamically as items are pushed onto the stack and popped off of the stack Items
226. xdata can message struct read mes Read last object can_read last_obj amp read mes 177 178 CAN Support can_get status Gets the actual CAN controller status This function is useful for debugging purposes Prototype Parameter Return Value Example unsigned char can_get_status void none Gets the actual CAN controller status as defined in the CAN protocol C_ERR_ACTIVE This is the normal mode of operation An error active node is able to receive and or transmit in the usual manner and can send a dominant error flag C ERR PASSIVE The controller has detected that the CAN bus is presently severely disturbed An error passive node may send and receive messages in the usual manner It is not able to signal this by transmitting a dominant but only recessive error flag in the case of a detected error condition Thus an error passive node may not block all bus activities due to a failure in its transmit logic C BUS OFF The CAN controller is in the off bus state because it has detected too many errors on the CAN bus restart with can start include rtxcan h Get the CAN controller status if can get status C BUS OFF Too many errors on the bus detected restart the communication can start RTX 51 RTX 251 179 Configuration Hardware Requirements RTXCAN x51 software requires the following hardware configuration m RTX 51 251 co
227. y SAM TS2 2 TS2 1 TS2 0 TS1 3 TS1 2 TS1 1 TS1 0 0 0 1 0 0 0 1 1 ie L TSEG1 TS1 1 fscl Mi TSEG2 TS2 1 fscl S Pa wid Bit Length Register 2 ff IPOL DI SIM SJW 1 SJW 2 0 1 0 0 0 0 1 0 e Js e SJWidth SJW 1 fscl SIM 1 up i wp sleep and br prescale sets bits BRPX Bit 0 Bit 5 of Baud rate and SME Bit 6 of Control reg as S Baud rate prescaler register BRP5 BRP4 BRP3 BRP2 BRP1 BRPO 0 0 0 0 0 0 0 0 Control register SME pa E fscl BRP 1 2 fosc fosc 1 fcrystal fscl BRP 1 2 fcrystal fd sy Bit length fbl TSEG1 TSEG2 1 fscl Baud rate e BR fcrystal 2 BRP 1 TS1 TS2 3 VE i Out Control Register OCTP1 OCTN1 OCP1 OCTPO OCTNO OCPO OCM1 OCMO 1 1 1 al 1 0 0 0 can_hw_init 0x23 0x42 0xF8 0x00 0x04 Example 4 Siemens C515C include lt rtxcan h gt Init the CAN communication controller for a baud rate of 1000Kbauds s CAN controller with 10 MHz clock fe E Bit Timing Register 0 E SWJ BRP RTX 51 RTX 251 1 0 0 0 0 0 0 0 TSEG1 TS1 1 fscl TSEG2 TS2 1 fscl Bit Timing Register 1 0 TS2 TS1 0 0 1 1 0 1 0 0 SJWidth SJW 1 fscl fscl BRP 1 fos
228. y the user The entire segment is restricted to a size of maximum 256 bytes If the size of this area is exceeded the linker issues a warning message If reentrant functions are used in the system the following segment whose size can be configured is stored in XDATA memory for each fast task by RTX 51 Segment RTX FTASKCONTEXT 1 IRTX FTASKCONTEXT 2 IRTX FTASKCONTEXT 3 Size max 256 bytes Area for the reentrant stack of the fast Size configurable with task compact reentrant stack RTX EXTRENTSIZE space is only reserved if reentrant functions are used Figure 9 Fast Task Context Layout for RTX 51 RTX 51 RTX 251 121 If reentrant functions were declared in the system a separate segment is stored in XDATA memory for the reentrant stack for each fast task Memory Assignment for RTX 251 The following section presents a general overview on the memory assignment of RTX 251 For RTX 51 users a similar description can be found in a preceding section Values which can be adapted by the user in the configuration file are characterized as such Direct Addressable Internal Memory DATA The DATA area of the processor is assigned by RTX 251 in the following way m Register bank O for all tasks gt 8 bytes m Register banks 1 2 and 3 for C251 interrupt functions if defined gt Maximal 3 8 bytes m 27 bits for system flags in the bit addressable area segments ORTX RTX BIT REL BYTE SEG and RTX RTX BIT SEG

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