TB-KU-xxx-ACDC8K Hardware User Manual
Contents
1. 1 CLK_DIR 225 AN4 DP1_M2C_P 2 225 AN3 DP1_M2C_N 3 4 DP9_M2C_P 5 DP9 M2C N 225 AP2 DP2 M2C P 6 225 AP1 DP2 M2C N 7 8 DP8 M2C P 9 DP8 M2C N 225 M2C P 10 225 AR3 DP3 M2C N 11 12 DP7 M2C P AT2 224 13 DP7 M2C N AT1 224 224 AUA DP4 M2C P 14 224 AUS DP4 M2C N 15 16 DP6 M2C P AV2 224 17 DP6 M2C N AVI 224 224 AW4 DP5 M2C P 18 224 AW3 DP5 M2C N 19 20 AP10 224 21 AP9 224 225 ANS DP1 C2M P 22 225 AN7 DP1 C2M N 23 24 DP9 C2M P 25 DP9_C2M_N 225 AP6 DP2 C2M P 26 225 AP5 DP2 C2M N 27 28 DP8 C2M P 29 DP8_C2M_N 225 ARS DP3 C2M P 30 225 AR7 DP3 C2M N 81 32 DP7 C2M P AT6 224 33 DP7_C2M_N AT5 224 224 AU8 DP4 C2M P 34 224 AUT DP4 C2M N 35 36 DP6 C2M P AV6 224 37 DP6 C2M N AV5 224 224 AW8 DP5 C2M P 38 224 AW7 DP5 C2M N 39 40 RESO Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 35 inreviun FMC 1 J2 225 DPO C2M N 3 4 224 5 224 225 pp 6 225 DPO_M2C_N 7 44 44 44 44 44 44 45 44 45 44 45 45 45 45 45 45 45 45 45 45 44 45 44 452. FMC 6 J19 Bank Pin C D Pin Bank GND 1 128 R34 DPO C2M P 2 GND 128 R35 DPO C2M N 3 GND GND 4 T32 128 GND 5 T33 128 128 P36 DPO M2C P 6 GND 128 P37 DPO M2C N 7 GND GND 8 LAO1 P CC GND 9 LAO1 N CC 06 10 GND LAO6 N 11 LAO5 P GND 12 LAO5 N GND 13 GND LA10 P 14 LAO9 P LA10 N 15 LAO9 N GND 16 GND GND 17 EAI P LA14 P 18 LA13 N LA14 N 19 GND GND 20 LA17 P CC GND 21 LA17 N CC LA18 P CC 22 GND LA18 N CC 23 LA23 P GND 24 LA23 N GND 25 GND LA27 P 26 LA26 P LA27 N 27 LA26 N GND 28 GND GND 29 30 31 2 GND 32 GND 33 34 amp 35 GND 36 37 GND GND 38 5 39 GND GND 40 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 71 inreviun FMC 6 J19 Bank Pin E F Pin Bank GND 1 4 2 GND 3 GND GND 4 GND 5 6 GND 7 GND 8 5 9 GND 10 GND ti 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 5 GND 23 24 GND 25 GND 26 27 GND 28 2 GND 29 30 GND 31 GND 32
3. FMC 3 J8 Bank Pin G H Pin Bank GND 1 7 NREF A M2C 24 AL30 CLK1 M2C P 2 24 AM30 CLK1 M2C N 3 GND GND 4 CLKO M2C P AM31 24 GND 5 CLKO M2C N AN31 24 24 AM32 LAOO P CC 6 GND 24 AN32 LAOO N CC 7 LA02_P AT29 24 GND 8 LA02_N AT30 24 24 AV29 LA03_P GND 24 AW29 LAO3 N 04 AU29 24 GND LA04 N AU30 24 24 AW30 LAO8 P GND 24 AW31 LAO8 N LAO7 P AU31 24 GND LAO7 N AV31 24 24 AP30 LA12 P GND 24 AP31 LA12 N LA11 P AR31 24 GND LA11_N AR32 24 25 AU36 LA16_P GND 25 AV36 LA16_N LA15 P AN33 24 GND LA15 N AP33 24 25 AV38 LA20 P GND 25 AV39 LA20_N LA19 P AT39 25 GND LA19 N AU39 25 25 AN38 LA22 P GND 25 AP38 LA22 N LA21 P AN39 25 GND LA21 N AP39 25 25 AL39 LA25 P GND 25 AM39 LA25 N LA24 P AM34 25 GND LA24 N AM35 25 24 AJ31 LA29 P GND 24 AK31 LA29 N LA28 P AN36 25 GND LA28 N AN37 25 24 AJ33 P GND 24 AK33 LA31_N LA30_P AK37 25 GND LA30_N AK38 25 25 AK35 LA33 P GND 25 AK36 LA33 N LA32_P AL34 25 GND LA32_N AL35 25 GND Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 52 inreviun FMC 3 J8 Bank Pin J K Pin Bank GND 1 7 VREF B M2C CLK3 M2C P 2 GND CLK3 M2C N 3 GND GND 4 CLK2 M2C P GND 5 CLK2 M2C N 6 GND
4. 8 VIO B M2C GND 8 VIO B M2C Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 53 inreviun For FMC 3 J8 1 GBTCLK 0 1 M2C P N These clocks are connected to Quad 126 of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 127 The other pair is provided by the system clock buffer 2 SCL SDA The board provides test points with pull up options to enable I2C communication with the FPGA By default the pull ups are not populated 8 GAO GA1 This board provides pull up or pull down options for these connections by default they are floating 4 TDI TDO The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG C2M PG M2C PRSNT M2C These all have a pull up or pull down resistor option However the resistors are not populated by default these pins are floating 6 Power Rails This card provides a 12V output through the 12V0 pins and 3 3V output through the 3V3 and 3V3 AUX pins It is important to note that all the FMC connectors present on this board are equipped with a fuse on the 12VO rail Lastly the VADJ pins provide a 1 8V rail to FPGA mezzanine cards 7 VREF A M2C VREF B M2C These terminals can be monitored by test points TP83 and TP84 M2C Both pins J39 and K40 for this terminal can also be monitored by test point TP81 Rev 1 04 TOKYO ELECT
5. Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 67 inreviun For FMC 5 J14 1 GBTCLK 0 1 M2C P N These clocks are connected to Quad 230 XCKU085 only of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 231 XCKU085 only The other pair is provided by the system clock buffer 2 SCL SDA The board provides test points with pull up options to enable I2C communication with the FPGA By default the pull ups are not populated 3 GAO GA1 This board provides pull up or pull down options for these connections by default they are floating 4 TDI TDO The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG C2M PG M2C PRSNT M2C These all have a pull up or pull down resistor option However the resistors are not populated by default these pins are floating 6 Power Rails This card provides a 12V output through the 12V0 pins and 3 3V output through the 3V3 and 3V3 AUX pins It is important to note that all the FMC connectors present on this board are equipped with a fuse on the 12VO rail Lastly the VADJ pins provide a 1 8V rail to FPGA mezzanine cards 7 VREF A M2C VREF B M2C These terminals can be monitored by test points TP91 and TP92 8 VIO B M2C Both pins J39 and K40 for this terminal can also be monitored by test point TP89 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 68 inreviun
6. e o eso GND LA27 P AE STA DP8 COM GND DpP3 COM P GND DP7C2MP co Demn co GND eL OO NN 39 GND VioBMoc GD 40 LPC Connector LPC Connector LPC Connector LPC Connector Figure 7 10 High Pin Count FMC 7 4 1 FMC HPC 0 J1 This FMC connects all of the available LA signals and 6 HA differential pairs to banks on the FPGA High Speed No GTH channels connected Low Speed Bank 64 e 18 differential LA pairs e differential HA pairs Bank 65 e 2 differential clock pairs e 16 differential LA pairs e differential HA pair Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 26 TB KU xxx ACDC8K Hardware User Manual Table 7 5 FMC 0 J1 to FPGA Pinout inreviun 1 CLK DIR DP1 M2C P 2 DP1 M2C N 3 4 DP9 M2C P 5 DP9 M2C N DP2 M2C P 6 DP2 M2C N 7 8 DP8 M2C P 9 DP8 M2C N M2C P 10 DP3 M2C N 11 12 DP7 M2C P 13 DP7_M2C_N DP4 M2C P 14 DP4 M2C 15 16 DP6 M2C P 17 DP6_M2C_N DP5 M2C 18 DP5 M2C N 19 20 21 DP1 C2M P 22 DP1 C2M N 23 24 DP9 C2M P 25 DP9 C2M N DP2 C2M P 26 DP2 C2M N 27 28 DP8 C2M P B 29 DP8 C2M N DP3 C
7. Figure 7 1 Power Supply Structure Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 16 inreviun 7 1 1 Power Sequencing The UCD9090 chip features power sequencing and monitoring of the different power supplies available on this board The sequencer s outputs are connected to the power supplies enable pin which activates each device 7 1 2 TB KU xxx ACDC8K has two power input connectors on the board a 4 pin header or red and black 1V8 VCCAUX SENS 1V0 MGTAVCC SENS 1V2 MGTAVTT SENS VCC HR SENS 1V8 FMC SENS 3V3 SENS 2V5 DDR4 1V2 DDR4 SENS UCD9090 O O Power Input connectors binding posts UCD9090RGZ All power good 1V8_VCCAUX_EN Reconfiguration Push Switch Figure 7 2 Power Sequencer 1 0 MGTAVCC EN 1V2 MGTAVTT EN 1V8 MGTVCCAUX EN FPGA PROGRAM B AND FMC 6 0 PGOOD J34 2 3 3 aq dl 8180275 1 350848 0 CONN HEADER 4 250 RTANG 12V0 J35 P23 J36 1 1 2 i 1 ala 1 ti 214 7 1 11 08 14 3 4 1902 14 RvR S1911 46R 18 03 13 RK 111 0702 001 JUMPER TIN SMD 35 POST BINDING INSULATED RED FUSE HOLDER BLADE 500V 20A PCB De x SMAJ12A 337 T 1 4 R379 _ _ 2 mas 3 3k L i T8324 RR 2297 14 08 111 0703 001 CM3440217 1R 10 POST BINDING INSUL GROUNDED BLCK CHOKE ARRAY COM MODE 170 OHM 20A SMD x P24 16 12 4 110614 51011468 JUMPER TIN SMD Rev 1 04
8. FMC3 total LA CLK 18pair LA10 LA13 LA14 total LA CLK 18pair LADO i LA LAOS i LAO LAOS LADB i LAO7 LAOB i LAOS LA11 LA12 LA15 LA27 LA29 LA31 CLKO_M2C CLK1 M2C FMC1 total LA CLK 18pair LA10 LA13 LA14 200MHz IDT ci 4MA200000Z4AACUGI LVDS 2 200MHZ DDR4 MIG1 BANK48 BANK47 Gc BANK46 inreviun BANK68 200MHz IDT 4MA200000Z4AACUGI LVDS CLK_DDR4_1_200MH4 25MHz OSC 40MHz osc DDRA MIG2 BANK67 Gc BANK66 ForGTHx5 4 Bank64 HR PLL 1 5849 2021 IDT Feed Back Clock LVDS Fanout Buffer DDR4 Bank Bank70 GC Bank67 GC Figure 7 9 User Assigned Clocks Architecture TOKYO ELECTRON DEVICE LIMITED BANK65 FMC0 0 LA28 CC MEUS 0 LA18 CC GC QBC LA10 LASS 0 LA17 CC Gc LAM LM6 148 5MHz LVDS s IDT OK VIDEO mi ac ILA 4MA148500Z4AACUGI LM8 1 19 LADO 1 21 QBC LA2 LA23 apc LA24 LA25 QBC LA26 LA28 DBC D04 LAGO LAS
9. Q ds RHE AE EVE l mi xu E 5 aj su m a 11 a A 9 5 Gh ttr iz5z1 T 1 2 Nu B P mm oam Da e OM m li z LI gt laj E EN laj va imu SE om 53 e n 34 s Lu 24 ER E sama ma ta m ii i 412313 1 433WvHZ Wid v mm Figure 6 1 Board Dimensions inclusive of wastable substrate top view Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 14 inreviun Nw or m gt Om mr o 4 e o000 2 9 9 vo o vo o o o dI o o 8184 MILI GAO alo E jsej peed freq Prejekrej pre m me lt 3 7 oo o E H LI se ADU ku g i plia mm man ata 48 a LLI T e ou 3 kar O aE l m annpnmnnununnnnun In ena ie um es Nu Nu Nu HH m La meme mama r a Be Ie WEE d E E rko T E Hu 4 li Eli s j ua mm 4 6 c m En ya l LI Q J ki 8 am meg gt e
10. 33 GND 34 GND 35 36 GND 37 GND 38 39 GND GND 40 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 72 inreviun FMC 6 J19 Bank Pin G H Pin Bank GND 1 7 VREF A M2C CLK1_M2C_P 2 CLK1_M2C_N 3 GND GND 4 CLK0_M2C_P GND 5 CLK0_M2C_N 24 AH29 LA00_P_CG 6 GND 24 AJ29 LA00_N_CC 7 LA02_P GND 8 LA02_N 24 AH31 LA03_P 9 GND 24 AH32 LA03_N 10 LA04_P GND 11 LA04_N 24 AH28 LA08_P 12 GND 24 AJ28 LAO8 N 13 LAO7 P GND 14 LAO7 N 24 AE30 LA12 P 15 GND 24 AF30 LA12_N 16 LA11 P GND 17 LA11 N 24 AF29 LA16 P 18 GND 24 AG29 LA16_N 19 LA15 P GND 20 LA15 N LA20 P 21 GND LA20 N 22 LA19 P GND 23 LA19 N 24 AE28 LA22 P 24 GND 24 AF28 LA22 N 25 LA21 P GND 26 LA21 N LA25 P 27 GND B LA25 N 28 LA24 P GND 29 LA24 N LA29 P 30 GND LA29 N 31 LA28 P GND 32 LA28 N LA31 P 33 GND LA31 N 34 GND 35 LA30_N LA33_P 36 GND LA33 37 LA32_P GND 38 LA32_N i 39 GND GND 40 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 73 inreviun
11. X1Y12 X1Y15 GTH Quad 226 1 8 1 11 2 8Lane RCAL GTH Quad 225 X1Y4 X1Y7 FMC1 GTH Quad 224 8Lane X1Y0 X1Y3 ug575 c1 03 031515 FMGG GTH Quad 128 X0Y16 X0Y19 4Lane RCAL GTH Quad 127 FMC3 X0Y12 X0Y15 8Lane GTH Quad 126 X0Y8 X0Y11 GTH Total 32CH XCKU060 Banks GTH Quad 228 FMC4 X1Y16 X1Y19 4Lane XCKU085 Banks FMC6 4Lane FMC3 gt 8Lane GTH Quad 128 X0Y16 X0Y19 RCAL GTH Quad 127 X0Y12 X0Y15 GTH Quad 126 8 11 GTH Quad 232 X1Y32 X1Y35 GTH Quad 231 X1Y28 X1Y31 RCAL GTH Quad 230 X1Y24 X1Y27 GTH Quad 229 X1Y20 X1Y23 GTH Quad 228 X1Y16 X1Y19 GTH Quad 227 X1Y12 X1Y15 GTH Quad 226 X1Y8 X1Y11 RCAL 1 SFP 4Lane FMC5 8Lane FMC4 8Lane FMC2 8Lane 1 GTH Quad 225 4 1 7 GTH Quad 224 lt 8Lane X1Y0 X1Y3 04575 c1 04 031515 GTH Total 480 XCKUOBS Banks Figure 7 6 FPGA Banks Assignments Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 22 inreviun 7 3 Clock System 7 3 1 VCCINT Clock Architecture The diagram below represents the clocking architecture of 6 LMZ31710 modules interconnected to provide 60A output current sharing for the FPGA The LTC6909 chip provides phase synchronized outputs with 60 offsets LMZ3
12. A D Q JI esl Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 43 inreviun FMC 2 J5 Bank Pin E F Pin Bank GND 1 4 2 GND 3 GND GND 4 GND 5 6 GND 7 GND 8 5 9 GND 10 GND ti 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 5 GND 23 24 GND 25 GND 26 27 GND 28 2 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 GND 38 39 GND GND 40 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 44 inreviun FMC 2 J5 Bank Pin G H Bank GND 7 VREF_A_M2G CLK1 M2C P CLK1_M2C_N GND CLK0_M2C_P GND CLK0_M2C_N 25 AW33 LA00_P_CG GND 25 AW34 LA00_N_CC LA02_P GND LA02_N 25 AR33 LA03_P GND 25 AT33 LAO3 N LAO4 P GND LAO4 25 AT34 LAO8 P GND 25 AU34 LA
13. Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 36 inreviun FMC 1 J2 Bank Pin E F Pin Bank GND 1 4 2 GND 3 GND GND 4 GND 5 6 GND 7 GND 8 5 9 GND 10 GND ti 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 5 GND 23 24 GND 25 GND 26 27 GND 28 2 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 GND 38 39 GND GND 40 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 37 inreviun FMC 1 J2 Bank Pins G H Pins Bank GND 7 VREF A M2C 44 AK22 CLK1 M2C P 44 AL22 CLK1_M2C_N GND GND CLKO M2C P AK23 44 GND CLKO M2C N AL23 44 44 AM21 00 CC GND 44 AN21 LAOO CC LAO2 P AJ20 44 GND LAO AJ21 44 44 AP21 LAO3_P GND 44 AR21 LAO3 N 04 P AH22 44 GND LAO4 AH23 44 44 AV21 08 GND 44 21 08 07 P AU21 44 GND LA07_N AV22 44 44 AV24 LA12 P GND 44 AW24 LA12 N 11 P AT23 44 GND LATIN 24 44 45 26 LA16 P GND 45 AV27 LA16_N LA15 P AL20 44 GND
14. 1 04 TOKYO ELECTRON DEVICE LIMITED 81 inreviun Table 7 16 SPI Flash Memory Pin Assignment FPGA Signal Name FPGA Bank Pin Primary Flash SPIFLASH 1 CS 0 AB9 SPIFLASH HR 1 IO 0 0 AE11 SPIFLASH HR 1 IO 1 0 AD10 SPIFLASH HR 1 IO 2 0 AC9 SPIFLASH HR 1 IO 3 0 AD9 CLK FPGA CCLK 0 AC11 Secondary Flash SPIFLASH HR 2 CS N 65 AW16 SPIFLASH HR 2 IO 0 65 AF14 SPIFLASH HR 2 IO 1 65 AG14 SPIFLASH HR 2 IO 2 65 AE13 SPIFLASH HR 2 IO 3 65 AF13 CLK FPGA CCLK 0 AC11 Xilinx Core User IO SPIFLASH ZYNQ CS N 47 P29 SPIFLASH ZYNQ IO 0 47 N29 SPIFLASH ZYNQ IO 1 47 L32 SPIFLASH ZYNQ IO 2 47 L33 SPIFLASH ZYNQ lO 3 47 R30 SPIFLASH ZYNQ CFG OD 65 AV16 CLK_ZYNQ_CONFIG_CCLK 47 P30 7 10 JTAG and Pmod Interface 7 10 1 JTAG Connector The TB KU xxx ACDC8K provides JTAG interface that follows the Xilinx 14 pin JTAG standard Table 7 17 Xilinx 14 pin JTAG Pinout Pin Xilinx 14 pin JTAG Pin 1 GND VREF 2 3 GND TMS 4 5 GND TCK 6 7 GND TDO 8 9 GND TDI 10 11 GND NC 12 13 GND NC 14 Table 7 18 FPGA Bank 0 JTAG Pin Assignment Signal Name TMS TCK TDO TDI FPGA Bank 0 Pin W11 AA11 T10 U11 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 82 inreviun 7 10 2 Pmod Interface Digilent s Pmod standard for system boards that provide I2C connectors is to use a male header This board features a 0 1 st
15. CLE GLOBAL SELT 25 uoj 4 FeedBack input Clock gt From FPGA GTREFCLK 0 P N CLK QUAD231 CLK GOBAL CONFIG 1 Y oa Output Clock gt 148 50MHz XTAL CLK_MMCX_QUAD231 CLK_GLOBAL_OE 1 25192059 GTREFCLK_1_P N E CLK PLL P N output to Fanout Buffer TXC PLL CLK PLL BYPASS 1 70 25 000MBA T IDT PLL Bypassed ICS849N202l Banke4 CLK EXT REF n v HR G azen Quad230 085 Only l CLK PLL P N CE CLK FMC 5 GTH REFO GTREFCLK 0 P N 4 GBTCLKO M2C P Fanout Buffer IDI GTREFCLK 1 P N SMES GBTCLK1_M2C_P ICS854S0061 Um EM 9 z 5 m FMC6 Quad229 085 Only 4 GTREFCLK 0 P N CLK QUAD229 GTREFCLK 1 P N MMCX QUAD229 I F MMOCX Quad128 Quad228 CLK FMC 6 GTH REFO In the CLK FMC 4 GTH REFO GTREFCLK 0 P N 4 GBTCLKO M2C P case of GTREFCLK 0 P N 4 GBTCLKO M2C P CLK FMC 6 GTH 060 CLK FMC 4 GTH GTREFCLK 1 P N 4 GBTCLK1 M2C P GTREFCLK 1 P N 4 GBTCLKI M2C P T Quad127 FMC3 Quad227 FMC2 CLK_QUAD130 GTREFCLK 0 P N CLK QUAD227 GTREFCLK 0 P N 4 k CLK_MMCX_QUAD130 GTREFCLK_1_P N CLK_MMCX_QUAD227 GTREFCLK 1 PAN cx PP eee la MCX Quad126 Quad226 CLK FMC 3 GTH REFO CLK FMC 2 GTH REFO GTREFCLK 0 P N 4 GBTCLKO M2C P GTREFCLK 0 P N La GBTCLKO M2C P CLK FMC 3 GTH CLK FMC 2 GTH GTREFCLK 1 P N 4 GBTCLK1 M2C P GTREFCLK 1 P N 4 GBTCLKi M2C P Quad225 FMC1 CLK Q
16. DBC DOS LASS i DBC NEN 1 DBC 64 FMCO total LA CLK FMC 0 LAD1 CC oc DNE LA00 CLK_FMC_0_CLK1_M2C J aciaBc LA01 LA02 0 M2C GC LA03 LA04 FMC_0_LA00 CC rsc LA05 LA06 LA07 apc LA08 LA09 QBC LA11 LA12 LA15 MMCX DBC LA27 CLK EXT IN Non LA29 Term DBC LA31 DBC CLKO M2C M2C CLK GLBL FPGA IN BEG _GLBL_FPGA BANK44 1 CLK_FMC_1_CLK1_M2c GC oo 1 CLKO 2 Gc aBc ven 1 FMC 1 LA00 CC 6 LAOZ LAOS 1 LAO CC ac LAO4 LAOS LAO i QBC LA07 LADB apc LAO i LAN LA LM5 DBC LAS DBC LA2 LAS DBC DBC CLK1_M2C inreviun 7 4 Connector Interface The TB KU xxx ACDC8K board has 7 high pin count HPC 400 pin FMC connectors FMC 0 to 6 on board as shown on the block diagram These FMC connectors follow the VITA 57 1 standard with Samtec ASP 134486 01 connectors Presented below is the standard pin assignment on FMC HPC connectors Not all the pins are connected on the FMC connectors Please follow this section for more details on all the FMC pinouts G F K J H E m JE w ao GXSBORT oT Mcp wo a BIDIR N GND CLKI voc N 152 GND CLKO M2 BDR N GND marc 7 8 3 GW 10 11 ME
17. the product may break down or it may cause a fire smoking or electric shock Q O oooo o Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to static electricity Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 7 inreviun N Caution Do not use or place the product in the following locations e Humid and dusty locations e Airless locations such as closet or bookshelf e Locations which receive oily smoke or steam e Locations exposed to direct sunlight e Locations close to heating equipment e Closed inside of a car where the temperature becomes high e Staticky locations e Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Do place heavy things the product Otherwise the product may be damaged E Disclaimer This product is an evaluation board intended for development of video data with Xilinx Kintex UltraScale FPGA Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused
18. 085 M6 DP5 C2M P 38 230 085 M5 DP5 C2M N 39 40 RESO Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 63 inreviun FMC 5 J14 231 085 E8 231 085 E7 230 085 230 085 231 085 E4 231 085 E3 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 64 inreviun FMC 5 J14 Bank Pin E F Pin Bank GND 1 4 2 GND 3 GND GND 4 GND 5 6 GND 7 GND 8 5 9 GND 10 GND ti 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 5 GND 23 24 GND 25 GND 26 27 GND 28 2 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 GND 38 39 GND GND 40 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 65 inreviun FMC 5 J14 Bank Pin G H Bank GND 7
19. 12V0 pins and 3 3V output through the 3V3 and 3V3 AUX pins It is important to note that all the FMC connectors present on this board are equipped with a fuse on the 12VO rail Lastly the VADJ pins provide a 1 8V rail to FPGA mezzanine cards 7 VREF A M2C VREF B M2C These terminals can be monitored by test points TP95 and TP96 8 VIO B M2C Both pins J39 and K40 for this terminal can also be monitored by test point TP93 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 75 inreviun 7 5 DDR4 SDRAM This TB KU xxx ACDC8K development board includes 8 DDR4 SDRAM memory components Micron EDY4016AABG DR F Control and address signals are wired in a fly by routing topology DDR4 SDRAM Capacity 4Gbit 32M words x 16 bits x 8 x 8 components Address Bus 15bit Row Address 15bit Column Address 10bit Bank Address 2bit Bank Group 1bit Data Bus Byte access with data strobe DQS Data Mask for each byte HP HP Bank67 A a 0 BA 1 0 BG O CK CK CS RAS CAS Bank47 a 18 0 BAr1 0 BG OJCKJCKJCSJRASJGAS CKE WEJODT RESET CKE WE ODT RESET ACT PAR TEN ALEAT ACT PAR TEN ALEAT I SDRAM 4Gbil N DDR4 SDRAM 4Gbit DQU 7 0 DQL 7 0 DQSU DQSU DQU 7 0 DQL 7 0 DQSU DQSU DQSL DQSL DMU DML U10 DQSL DQSL DMU DML di 014 T HP N N Bank48 N Banks DQ
20. AD32 126 AD33 126 126 AG38 DPOM2OP i 126 AG39 DPO M2C N AL29 24 AM29 24 24 AP29 24 AR30 AK32 24 AL32 24 25 AM36 AU32 24 25 AM37 AV32 24 AU37 25 25 AR37 AV37 25 25 AT37 AP36 25 AR36 25 25 AR38 25 AT38 AN34 25 AP34 25 24 AJ30 AL37 25 24 AK30 AL38 25 6 7 EN EN 1 04 TOKYO ELECTRON DEVICE LIMITED 50 inreviun FMC 3 J8 Bank Pin E F Pin Bank GND 1 4 2 GND 3 GND GND 4 GND 5 6 GND 7 GND 8 5 9 GND 10 GND ti 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 5 GND 23 24 GND 25 GND 26 27 GND 28 2 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 GND 38 39 GND GND 40 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 51 inreviun
21. Binding 5 18 7 1 4 Voltage Rails Test rte eaaet tenet 19 7 1 5 Power and Miscellaneous LEDs sse eene 20 7 1 6 Board Power BU E u res 21 7 1 7 FPGA HR Bank Voltage 21 7 1 8 HR Banks Voltage and SFP LOS TX FAULT 21 72 FPGABanks Assignments it ed deemed d dado od eR nda 22 23 7 3 1 VCCINT Clock Architecture irnir eninin iaria aiaiai aaa iaai 23 7 3 2 GT 601606 __k u at 24 7 3 3 User Assigned ClOCKS iei certi eate regi d aao o ted ed 25 7 4 Connector Interface eene nnne entente inttr intente sinis anna nn 26 7 4 1 FMC AHRC O e E EE A N A E ANR 26 7 4 2 FMCG HPC A J2 u 34 7 4 3 FMO HPO 2 Jb sss sesto rt eet gemo ag 41 7 4 4 FMC HPO 3 UE 48 7 4 5 FMO HPC Lp 55 7 4 6 5 IPA PER 62 7 4 7 FMEHPG 6 19 S L i asi e qiie RIDERS 69 7 9 DDRA BLU 76 7 6 SEPH m m 77 74 USB to VART Controller dic e deae der codage seed dla 79 758 PARO Scie ay Sere ci va ste ce x ire itat emiten a 80 7 9 Dual Quad x8 SPI Flash ie eet de tee perc aati dete Pee banu ciate device 81 7 10 JT
22. GTH 8ch FMC4 GTH 4ch or 8ch FMC2 GTH 8ch FMC1 GTH 8ch Quad230 231 Quad228 229 Quad226 227 Quad224 225 060 NC 060 Quad228 LA Group B 1 8V Fix LA Group A 36pair 1 8V Fix LA Group B 1 8V Fix LA Group B 1 8V Fix 12pin bank 25 47 72pin bank 44 45 12pin bank 45 12pin bank 44 Figure 4 1 Block Diagram Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 11 inreviun 5 External View of the Board The TB KU xxx ACDC8K board s components are shown on the top side view in Figure 5 1 Sequencer HR Voltage GTH CLK FMC Connector 6 HPC 12V Input PMBUS Header Select Header MMCX Inputs LA Group B 6pairs Dual Quad TH 4L Fuse Holder FPGA Progra ncommitted pDR4spRAM 4965 Coin Cel 20A Button l Flash Memorv 20A 5 Headers Pushbuttons 2 banks Connector Battery Holder TK FAULT RX LOS Power Input Binding Posts JTAG Power Input Connector FMC Connector 3 HPC LA Group A 36pairs GTH 8Lanes Power Switch FPGA Program GTH CLK DONE LED i 1 Uv MMCX Inputs Micro USB A U T PMOD Type AB UART t 5 2 E I FPGA POR_OVERRIDE Switch T LA 7 m FPGA FMC Connector 0 HPC LA Group A 36pairs HA 5pairs SFP Modules 4ch Supported 1 8 2 5 3 3V 060 not connected No GTH PLL GTH CLK Ta MMOX Inputs TEMG IEY Fuse Holders 2A FMC Connector 5 HPC FMC Connector 4 HPC FMC Connector 2 HPC FMC Connector 1 HPC LA Group B 6pai
23. LA15 N AM20 44 45 AH26 LA20 P GND 45 AJ26 LA20 N LA19 P AK27 45 GND LA19 N AK28 45 45 AR28 LA22 P GND 45 AT28 LA22 N LA21 P AL24 45 GND LA21 N AL25 45 45 AN28 LA25 P GND 45 AP28 LA25 N LA24 P AV28 45 GND LA24 N AW28 45 44 AN23 LA29 P GND 44 AP23 LA29 N LA28 P AM26 45 GND LA28 N AN26 45 44 AN24 LA31 P GND 44 AP24 LA31 N LA30 P AP25 45 GND LA30 N AR25 45 45 AU25 LA33 P GND 45 AU26 LA33 N LA32 P AR26 45 GND LA32 AR27 45 GND Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 38 inreviun FMC 1 J2 Bank Pin J K Pin Bank GND 1 7 NREF B M2C CLK3 M2C P 2 GND CLK3 M2C N 3 GND GND 4 CLK2 M2C P GND 5 CLK2 M2C N 6 GND 7 GND 8 9 GND 10 GND 11 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 2 GND 23 24 GND 2 25 GND 26 27 GND 28 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 2 GND 38 8 VIO B M2C 39 GND GND 40 8 VIO B M2C Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 39 inreviun For FMC 1 J2 1 GBTCLK 0 1 M2C P N These clocks are connected to Quad 224 of the FPGA while t
24. P 38 228 AB5 DP5 39 40 RESO Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 56 inreviun FMC 4 J11 229 085 N8 229 085 N7 229 085 N4 229 085 N3 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 57 inreviun FMC 4 J11 Bank Pin E F Pin Bank GND 1 4 2 GND 3 GND GND 4 GND 5 6 GND 7 GND 8 5 9 GND 10 GND ti 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 5 GND 23 24 GND 25 GND 26 27 GND 28 2 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 GND 38 39 GND GND 40 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 58 inreviun FMC 4 J11 Bank Pin G H Bank GND
25. SE i x A BB 5 zJ 3 mi TT aT 20 a 6 His alae em WA Eis pun mo up D mi ii 5 psum oo om m og mm Figure 6 2 Board Dimensions inclusive of wastable substrate bottom view Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 15 TB KU xxx ACDC8K Hardware User Manual 7 Description of Components 7 1 Power Supply Structure TB KU xxx ACDC8K board s power supply structure is shown in the figure below ome Fuse l ad bs from a from Sequender from Sequender 9 from from from 1 731710 x 6 60A current share Y Y TPS53318 In 1 5 22V Out 0 6 5 5V 8A NO TPS53318 In 1 5 22V Out 0 6 5 5V 8A ON TPS53355 In 1 5 15V Out 0 6 5 5V 30A TPS53355 In 1 5 15V Out 0 6 5 5V 30A TPS53318 In 1 5 22V Out 0 6 5 5V 8A TPS51206 Termination 3A TPS73801 In 2 2 20V Out 1 21 20V 1A TPS53319 In 1 5 22V Out 0 6 5 5V 14A TPS53319 In 1 5 22V Out 0 6 5 5V 14A from TPS73801 In 2 2 20V Out 1 21 20V 1A Fuse UCD9090 Sequencer 10 A to power devices 5V0_USB_VBUS SVO TLV70433 3 3V LDO TPS73801 In 2 2 20V Out 1 21 20V 1A 1V8 USB PWR USB UART
26. TOKYO ELECTRON DEVICE LIMITED 17 R378 GRN D10 LNJ347W83RA inreviun 7 1 3 DC 4 pin Header and Binding Posts Important There are two 2 power inputs available on this board Connect one OR the other 12VDC inputs NEVER connect both power inputs simultaneously Figure 7 4 12VDC Input Connector and Binding Posts Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 18 inreviun 7 1 4 Voltage Rails Test Points Use the development board s power rail test points for board debugging and troubleshooting or for other types of measurements Table 7 1 Voltage Rails Test Points Voltage Rail TestPoint Power Supply for 0V95 TP37 FPGA VCCINT 0V95_VCCBRAM TP23 FPGA VCCBRAM 1V8_VCCAUX TP40 FPGA VCCAUX amp VCCAUX IO 3V3 VCC HR TP36 FPGA HR I O Banks 3V3_UCD9090 TP43 Power Sequencer and Monitor 1V8_FMC TP19 FPGA HP I O Banks amp FMC VADJ 1V2 DDR4 TP31 DDR4 and corresponding FPGA Banks 2V5 DDR4 TP30 VPP generation OV6 VTT DDR4 TP32 DDR4 SDRAM 1 Termination 0V6 VREF DDR4 TP34 DDR4 SDRAM 1 Reference OV6 VTT DDR4 2 TP33 DDR4 SDRAM 2 Termination OV6 VREF DDR4 2 TP35 DDR4 SDRAM 2 Reference 1 0 MGTAVCC TP39 FPGA MGTAVCC 1V2 MGTAVTT TP41 FPGA MGTAVTT 1V8 MGTVCCAUX TP38 FPGA MGTVCCAUX 3V3 TP20 FMC and SFP modules 12V0 TP42 12V Master Power VBATT TP68 Coin Cell Battery 5V0 USB VBUS TP57 Micro USB 5V input 5V0 USB FILT TP59 Micro
27. VREF_A_M2C CLK1_M2C_P CLK1_M2C_N GND CLK0_M2C_P GND CLK0_M2C_N 45 AD25 LAOO P CC GND 45 AE25 LAOO N CC LAO2 P GND LAO2 N 45 AG26 LAO3 P GND 45 AG27 LAO3 N LAO4 P GND LAO4 N 45 AE27 LAO8 GND 45 AF27 LAO8 N LAO7_P GND LAO7 N 45 AD26 LA12 P GND 45 AE26 LA12 N LA11 P GND LA11 N 45 AF25 LA16 P GND 45 AG25 LA16 N LATS P GND LA15 N LA20 P GND LA20 N LA19 P GND LA19 N 45 AF24 LA22 P GND 45 AG24 LA22 N LA21 P GND LA21 N LA25 P GND LA25 N LA24 P GND LA24 N LA29 P GND LA29 N LA28 P GND LA28 N LA31 P GND LA31 N LA30_P GND LA30_N LA33_P GND LA33_N LA32_P GND LA32_N GND Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 66 inreviun FMC 5 J14 Bank Pin J K Pin Bank GND 1 7 NREF B M2C CLK3 M2C P 2 GND CLK3 M2C N 3 GND GND 4 CLK2 M2C P GND 5 CLK2 M2C N 6 GND 7 GND 8 9 GND 10 GND 11 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 2 GND 23 24 GND 2 25 GND 26 27 GND 28 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 2 GND 38 8 VIO B M2C 39 GND GND 40 8 VIO B M2C
28. 1710 LMZ31710 LMZ31710 U23 not U24 U25 se used SYNC_OUT sg Used SYNC_OUT sd Used SYNC_OUT RT CLK ml RT CLK RT CLK LMZ31710 LMZ31710 LMZ31710 not U26 not U27 not U28 yo used SYNC_OUT sg Used SYNC_OUT s used SYNC_OUT NI RT CLK Or RT CLK II RT CLK LTC6909 250kHz 0deg 250kHz 60deg 250kHz 120deg 250kHz 180deg 250kHz 240deg 250kHz 300deg Figure 7 7 VCCINT Clock Synchronization 23 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 3 2 GTH Clocks The diagram below represents the GTH clock architecture present in the TB KU xxx ACDC8K board Some clocks are internally driven by the system while others can be externally provided through MMCX connectors DIP SW SW2 DIP SW OFF Quad232 085 Only 156 25MHz LVDS TT CBN CLK_SFP_QUAD232 IDT eedBack input Clock gt 2 LO P N f CLK_GLOBAL_CONFIG 0 4MA156250Z4AACUGI Output Clock gt 156 25MHz CLK GLOBAL OE 0 CLK_MMCX_QUAD232 GTREFCLK 1 P N t TT MMCX No CLK PLL P N to Fanout Buffer 40MHz X tal e PLL BYPASS 0 PLL Mode default 7M 40 000MAHE T Quad231 085 Only FMC5 DIP SW ON
29. 2M P 30 DP3 C2M N 31 32 DP7 C2M P 33 DP7_C2M_N DP4 C2M 34 DP4 C2M N 35 36 DP6 C2M P 37 DP6_C2M_N DP5 C2M P 38 DP5_C2M_N 39 40 RESO 7 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 27 inreviun FMC 0 J1 Kuwa DPO C2M N 3 DPO M2C N 7 65 65 65 AU12 65 AV12 65 65 64 AJ16 65 64 AK16 65 64 64 AP19 64 64 AP18 64 64 64 AL17 64 AM17 64 64 65 AT15 64 65 AU15 64 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 28 inreviun FMC 0 J1 Bank Pin E F Pin Bank GND 1 4 65 AD14 2 GND 65 AD13 3 GND GND 4 AE12 65 GND 5 AF12 65 64 AE18 6 GND 64 AF18 7 AP15 65 GND 8 AR15 65 9 GND 10 GND ti 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 5 GND 23 24 GND 25 GND 26 27 GND 28 2 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 GND 38 39 GND GND 40 Rev 1 04 TOKYO ELE
30. 7 4 7 FMC HPC 6 J19 This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA High Speed Quad 128 e 4GTH lanes 2 differential clock pairs Low Speed Bank 24 e 6 differential LA pairs Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 69 TB KU xxx ACDC8K Hardware User Manual inreviun B Table 7 11 FMC 6 J19 to FPGA Pinout 1 CLK DIR 128 U38 DP1 M2C P 2 128 U39 DP1 M2C N 3 4 DP9 M2C P 5 DP9_M2C_N l 128 R38 DP2 M2C P 6 128 R39 DP2 M2C 7 8 DP8 M2C P 2 9 DP8_M2C_N B 128 N38 DP3 M2C P 10 128 N39 DP3 M2C N 11 12 DP7_M2C_P 13 DP7_M2C_N 2 DP4 M2C P 14 DP4 M2C N 15 16 DP6 M2C P 17 DP6_M2C_N DP5 M2C P 18 DP5 M2C 19 20 P32 128 21 P33 128 128 U34 DP1 C2M P 22 128 U35 DP1 C2M N 23 24 DP9 C2M P 25 DP9 C2M N 128 T36 DP2 C2M P 26 128 T37 DP2 C2M N 27 28 DP8 C2M P 29 DP8_C2M_N 128 N34 DP3 C2M P 30 128 N35 DP3 C2M N 31 32 DP7 C2M P 33 DP7 C2M N E DP4 C2M P 34 DP4 C2M N 35 36 DP6 C2M P 37 DP6_C2M_N gt DP5 C2M P 38 DP5_C2M_N 39 40 RESO Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 70 inreviun
31. 7 VREF A M2C CLK1_M2C_P CLK1_M2C_N GND CLK0_M2C_P GND CLK0_M2C_N 44 AG21 LA00_P_CC GND 44 AG22 LA00_N_CC LA02_P GND LA02_N 44 AE23 LA03_P GND 44 AF23 LAO3 N LAO4 P GND LAO4 N 44 AD20 LAO8 GND 44 AD21 LAO8 N LAO7_P GND LAO7 N 44 AE20 LA12 P GND 44 AE21 LA12_N LA11 P GND LA11 N 44 AE22 LA16 P GND 44 AF22 LA16 N LATS P GND LA15 N 20 GND 20 19 GND LA19 N 44 AF20 LA22 P GND 44 AG20 LA22 N LA21 P GND LA21 N 25 GND LA25 N LA24 P GND LA24 N s LA29 P GND x LA29 N LA28 P GND LA28 N LA31 P GND LA31 N LA30_P GND LA30_N x LA33 P GND LA33 N LA32_P GND LA32_N GND Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 59 inreviun FMC 4 J11 Bank Pin J K Pin Bank GND 1 7 NREF B M2C CLK3 M2C P 2 GND CLK3 M2C N 3 GND GND 4 CLK2 M2C P GND 5 CLK2 M2C N 6 GND 7 GND 8 9 GND 10 GND 11 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 2 GND 23 24 GND 2 25 GND 26 27 GND 28 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 2 GND 38 8 VIO B M2C 39 GND GND 40 8 VIO B M2C R
32. 86 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 5 inreviun Introduction Thank you for purchasing the TB KU xxx ACDC8K board Before using the product be sure to carefully read this user manual and fully understand how to correctly use the product First read through this manual and always keep it handy SAFETY PRECAUTIONS Observe the precautions listed below to prevent injuries to you or other personnel or damage to property e Before using the product read these safety precautions carefully to ensure proper use e These precautions contain serious safety instructions that must be followed e After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled Danger incorrectly Indicates the possibility of serious injury or death if the product is handled LAK warning incorrectly household goods if the product is handled incorrectly Indicates the possibility of injury or physical damage in connection with houses or A Caution The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch KG KI Do not disassemble the product Do attempt this Rev 1 04 TOKYO ELECTRON D
33. AG and Pmiod Interface oct teet er er d 82 7 10 1 JTAG u u y L E 82 1710 2 Pmod Mera O ice uu TTT eee eel ete 83 7 11 General Purpose LEDS uuu te nee dei e ia Runden 84 7 12 General Purpose Switches I enne nnne enne nnns nnne nenas 85 7 12 DIP SWiHtCh S es Rb hand eg en OL asi 85 712 2 Push L ea dd eade ani aa Y oda 85 7 12 83 JumperSwitohes irte tre ar beati iud saa Ee are etus 86 B APPNO LL LLL I UU E LL E 87 Default Settings a ep REO e deiude i ira ies uiui 87 8 2 Power Sequencer Timings 4 2 intenti nnne ns 88 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 3 inreviun List of Figures Figure 4 1 Block oct tret eire Vi dan 11 Figure 5 1 Board VIEW iii u pa i iive Testi indan ER ap 12 Figure 6 1 Board Dimensions inclusive of wastable substrate top view 14 Figure 6 2 Board Dimensions inclusive of wastable substrate bottom view 15 Figure 7 1 Power Supply Structure aa 16 Figure 7 2 Power Sequencoer entrent enn sinn ns st nrt sentent 17 Figure 7 3 Power Input Circuit enne nennen am
34. C connects GTH lanes XCKUO85 only and 6 differential pairs of LA signals to banks on the FPGA High Speed No GTH XCKUO60 Quad 230 and 231 XCKU085 e 8 GTH lanes XCKUO85 2 differential clock pairs Low Speed Bank 45 e 66 differential LA pairs Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 62 inreviun Table 7 10 FMC 5 J14 to FPGA Pinout 1 CLK DIR 231 085 F2 DP1 M2C P 2 231 085 F1 DP1 M2C N 3 4 DP9 M2C P 5 DP9 M2C N 231 085 G4 DP2 M2C P 6 231 085 G3 DP2 M2C N 7 8 DP8 M2C P z 9 DP8 M2C N 231 085 H2 DP3 M2C P 10 231 085 H1 DP3 M2C N 11 12 DP7 M2C P J4 230 085 13 DP7 M2C N J3 230 085 230 085 K2 DP4 M2C P 14 230 085 K1 DP4 M2C N 15 16 DP6 M2C P L4 230 085 17 DP6 M2C N L3 230 085 230 085 M2 DP5 M2C P 18 230 085 M1 DP5 M2C N 19 20 M10 230 085 21 M9 230 085 231 085 F6 DP1 C2M P 22 231 085 F5 DP1 C2M N 23 24 DP9 C2M P 25 DP9 C2M N 231 085 G8 DP2 C2M P 26 231 085 G7 DP2 C2M N 27 28 DP8 C2M P B 29 DP8 C2M N 231 085 H6 DP3 C2M P 30 231 085 H5 DP3 C2M N 31 32 DP7 C2M P J8 230 085 33 DP7 C2M N J7 230 085 230 085 K6 DP4 C2M P 34 230 085 K5 DP4 C2M N 35 36 DP6 C2M P L8 230 085 37 DP6 C2M N L7 230 085 230
35. CTRON DEVICE LIMITED 29 inreviun FMC 0 J1 Bank Pin G H Pin Bank GND 7 VREF A M2C 65 AL12 CLK1 M2C P 65 AM12 CLK1_M2C_N GND GND CLKO M2C P AM14 65 GND CLKO M2C AN14 65 65 AN13 00 P CC GND 65 AN12 LAOO CC LAO2 P AR12 65 GND LAO2 N AT12 65 65 AR13 LAO3 P GND 65 AT13 LAO3 N LAQA P AT14 65 GND LAO4 AU14 65 65 AV14 LAO8 P GND 65 AW14 08 LAO7 P AH13 65 GND 07 AJ13 65 65 AH14 LA12 P GND 65 AJ14 LA12 N 11 P AP14 65 GND LATIN AP13 65 64 AH19 LA16 P GND 64 AH18 LA16 LA15 P AJ15 65 GND LA15 N AK15 65 64 AU17 LA20 P GND 64 AU16 LA20 N LA19 P AT19 64 GND LA19 N AU19 64 64 AJ19 LA22 P GND 64 AJ18 LA22 N LA21 P AH17 64 GND LA21 N AH16 64 64 AT18 LA25 P GND 64 AT17 LA25 N LA24 P AV18 64 GND LA24 N AV17 64 65 AG12 LA29 P GND 65 AH12 LA29 N LA28 P AL19 64 GND LA28 N AL18 64 65 AF15 LASi P GND 65 AG15 LA31 N LA30 P AV19 64 GND LA30 N AW18 64 64 AR20 LA33 P GND 64 AT20 LA33 N LA32 P AW20 64 GND LA32 N AW19 64 GND Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 30 inreviun FMC 0 J1 Bank Pin J K P
36. EVICE LIMITED 6 inreviun A Warning In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact our sales personnel for repair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that no smoking is observed contact our sales personnel for repair Do not disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates in high speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise
37. FMC 6 J19 Bank Pin J K Pin Bank GND 1 7 NREF B M2C CLK3 M2C P 2 GND CLK3 M2C N 3 GND GND 4 CLK2 M2C P GND 5 CLK2 M2C N 6 GND 7 GND 8 9 GND 10 GND 11 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 2 GND 23 24 GND 2 25 GND 26 27 GND 28 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 2 GND 38 8 VIO B M2C 39 GND GND 40 8 VIO B M2C Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 74 inreviun For FMC 6 J19 1 GBTCLK 0 1 M2C P N These clocks are connected to Quad 128 of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 232 XCKU085 only The other pair is provided by the system clock buffer 2 SCL SDA The board provides test points with pull up options to enable I2C communication with the FPGA By default the pull ups are not populated 8 GAO GA1 This board provides pull up or pull down options for these connections by default they are floating 4 TDI TDO The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG C2M PG M2C PRSNT M2C These all have a pull up or pull down resistor option However the resistors are not populated by default these pins are floating 6 Power Rails This card provides a 12V output through the
38. MCX interface for one pair of clocks on Quad 227 The other pair is provided by the system clock buffer 2 SCL SDA The board provides test points with pull up options to enable I2C communication with the FPGA By default the pull ups are not populated 3 GAO GA1 This board provides pull up or pull down options for these connections by default they are floating 4 TDI TDO The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG C2M PG M2C PRSNT M2C These all have a pull up or pull down resistor option However the resistors are not populated by default these pins are floating 6 Power Rails This card provides a 12V output through the 12V0 pins and 3 3V output through the 3V3 and 3V3_AUX pins It is important to note that all the FMC connectors present on this board are equipped with a fuse on the 12VO rail Lastly the VADJ pins provide a 1 8V rail to FPGA mezzanine cards 7 VREF A M2C VREF B M2C These terminals can be monitored by test points TP79 and TP80 M2C Both pins J39 and K40 for this terminal can also be monitored by test point TP77 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 47 inreviun 7 4 4 FMC HPC 3 J8 This FMC connects GTH lanes and all of the available LA signals to banks on the FPGA High Speed Quad 126 and 127 e 8 GTH lanes 2 differential clock pairs Low Speed Bank 24 e 16 differential LA pairs 2
39. NTON 4 7 3V3 SC1 SD1 INT1_N R155 SFP I2C OD 18 SDA 122 OD 19 17 SCL sc2 SDA SD2 Slave Address INT_N INT2_N SC3 N 1 SD3 2 M INT3 3 1 A2 GND 18 10 13 RK PCA9544APW _ 4 TO 1 I2C SMBL Fixed Hardware Selectable Texas Instruments PCA9544A datasheet p 12 of 34 Figure 7 13 I2C MUX Hardware selectable Address Pins By default the I2C address for this device is 1110101 If the last bit of the address is set to a logic 1 a read is selected and 0 for a write Please refer to Tl s PCA9544A datasheet for additional information concerning this component Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 77 inreviun The SFP I2C multiplexed data and multiplexed clocks are connected to the FPGAS Bank 64 Table 7 12 SFP I2C Bus Pin Assignment 2 Signal FPGA Bank Pin SCL SFP I2C FPGA OD 64 AF19 SDA SDA SFP 2 FPGA OD 64 AG19 Also pins RSO and RS1 have been connected together to efficiently make use of available connections By connecting these together the optical transmit and receive signals operate at the same rate They both have a 0 ohm resistor option on each of the SFP connectors which can be depopulated as required Table 7 13 RX LOS TX FAULT and RS Pin Assignment SFP FPGA Connector Signal Name Desc
40. O8 N LAO7 P GND LAO7 N 25 AV33 LA12 P GND 25 AV34 LA12_N LA11 P GND LA11 N 25 AT35 LA16 P GND 25 AU35 LA16_N GND LA15 N LA20 P GND LA20_N LA19 P GND LA19 N 25 AW35 LA22 P GND 25 AW36 LA22 N LA21 P GND LA21 N LA25_P GND LA25_N LA24 P GND LA24 N LA29 P GND 5 LA29_N LA28 P GND LA28 N LA31 P GND LA31_N LA30_P GND LA30_N LA33_P GND LA33_N LA32_P GND LA32_N GND Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 45 inreviun FMC 2 J5 Bank Pin J K Pin Bank GND 1 7 NREF B M2C CLK3 M2C P 2 GND CLK3 M2C N 3 GND GND 4 CLK2 M2C P GND 5 CLK2 M2C N 6 GND 7 GND 8 9 GND 10 GND 11 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 2 GND 23 24 GND 2 25 GND 26 27 GND 28 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 2 GND 38 8 VIO B M2C 39 GND GND 40 8 VIO B M2C Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 46 inreviun For FMC 2 J5 1 GBTCLK 0 1 M2C P N These clocks are connected to Quad 226 of the FPGA while this board provides an M
41. P 1 RX LOS TX FAULT No Supply 8 J24 Open SFP 2 RX LOS TX FAULT No Supply 9 J27 Open SFP 3 RX LOS TX FAULT No Supply 10 J28 Open SFP 4 RX LOS TX FAULT No Supply 11 J45 Open VCCINT Sense A jumper must be installed when links removed Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 87 inreviun 8 2 Power Sequencer Timings Vccint VccintI O Vccbram LMZ31710 9 8ms startup time Control 0V95 INH OD sequencer output GPIO1 Vccaux VccauxlO TPS53318 1 4ms startup time Control 148 VCCAUX EN sequencer output GPIO2 Vcco 3V3 TPS53335 2 8ms startup time Contol 3 3 EN sequencer output GPIOS HR bank Vcco FMC TPS53318 1 4ms startup time Control EN sequencer output GPIO6 1V8 Vcco FMC 553335 2 8ms startup time Control 1V8 FMC EN sequencer output GPIO7 2V5 DDR4 VPP TPS73801 Oms startup LDO Control 2V5 DDR4 EN sequencer output GPIO9 DDR4 1V2 TPS53318 1 4ms startup time Control 1 2 DDR4 EN sequencer output GPIO10 must always be lessthan DDR4 VPP Vmgtavcc 55 3319 1 4ms startup time Control LVO_MGTAVCC_EN sequencer output GPIO3 Vmgtavtt TP553319 1 4ms startup time Control 1 2 EN sequencer GPIO4 Vmgtvaccaux TPS73801 Oms startup LDO Control 1 8 MGTVCCAUX EN sequencer GPIOS The above sequence must be adhered to on power up The times given are the startup times for the power supplies All power supp
42. RON DEVICE LIMITED 54 inreviun 7 4 5 FMC HPC 4 J11 This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA High Speed Quad 228 XCKUO060 Quad 228 and 229 XCKU085 4 GTH lanes XCKUO60 8 GTH lanes XCKUO85 e 2 differential clock pairs Low Speed Bank 44 e 6differential LA pairs Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 55 inreviun Table 7 9 FMC 4 J11 to FPGA Pinout 1 CLK_DIR 229 085 P2 DP1 M2C P 2 229 085 P1 DP1 M2C N 3 4 DP9 M2C P 5 DP9_M2C_N 229 085 R4 DP2 M2C P 6 229 085 R3 DP2 M2C N 7 8 DP8 M2C P z 9 DP8_M2C_N 229 085 T2 DP3 M2C P 10 229 085 Ti DP3_M2C_N 11 12 DP7 M2C P V2 228 13 DP7 M2C N Vi 228 228 W4 DP4 M2C P 14 228 W3 DP4 M2C 15 16 DP6 M2C P Y2 228 17 DP6 M2C N Yi 228 228 AB2 DP5 M2C P 18 228 AB1 DP5 M2C N 19 20 ws 228 21 W7 228 229 085 P6 DP1 C2M P 22 229 085 P5 DP1 C2M N 23 24 DP9 C2M P 25 DP9_C2M_N 229 085 T6 DP2 P 26 229 085 T5 DP2 C2M N 27 28 DP8 C2M P B 29 DP8 C2M N 229 085 U4 DP3 C2M P 30 229 085 U3 DP3 C2M N 31 32 DP7_C2M_P V6 228 33 DP7_C2M_N V5 228 228 Y6 DP4 C2M P 34 228 Y5 DP4 C2M N 35 36 DP6 C2M P AM 228 37 DP6 C2M N AA3 228 228 AB6 DP5 C2M
43. Selection Various different devices are connected on the FPGA HR banks The FMCO connector and SFP modules are connected to the FPGA s HR 64 and 65 banks as shown in blue on this board s block diagram Figure 4 1 The SPI flash components are connected to HR bank 0 and bank 65 Banks 0 64 and 65 have a selectable voltage which is identical on these three banks Table 7 3 HR Banks Connected Peripherals Bank Connected Peripherals Voltage Dedicated Config 0 Dual Quad SPI Flash Primary FMCO Selectable HR 64 SFP 1 and 2 1 8V 2 5V FMCO 3 3V Dual Quad SPI Flash Secondary HR 65 SFP 3 and 4 7 1 8 HR Banks Voltage and SFP LOS TX FAULT Selection The 3V3_VCC_HR power can be selected through the use of a 3 pin jumper J44 The user can also select between RX LOS or TX FAULT on each of the 4 SFP modules Table 7 4 HR Banks Voltage and RX LOS TX FAULT Selection JumperNo Description Status Function No Jumper 1 8V Default J44 id 2 1 2 2 5V 3 2 3 3V Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 21 TB KU xxx ACDC8K Hardware User Manual inreviun 7 2 FPGA Banks Assignments This board supports Xilinx Kintex Ultrascale XCKUO60 and XCKUO85 FPGA in the FFVA1517 FLVA1517 packages The figure below presents bank assignments on this board XCKUO60 Banks GTH Quad 227
44. Table 7 4 HR Banks Voltage RX LOS TX FAULT Selection 21 Table 7 5 FMC JI to FPGA Pinout AA aa aa ek 27 Table 7 6 1 J2 to ia 35 Table 7 7 FMC 2 J5 to FPGA 42 Table 7 8 FMC J8 to eene nennen nennen nnn nennen ani 49 Table 7 9 4 J11 to FPGA PinOUlL eite entente as eksl lal lamaa nail 56 Table 7 10 FMC 5 J14 to FPGA 63 Table 7 11 FMC 6 J19 to 70 Table 7 12 SFP 2 Bus Pin 88 78 Table 7 13 LOS TX FAULT and RS Pin 78 Table 7 14 Micro USB Type B and AB Compatibilitv 79 Table 7 15 UART Interface Pin 79 Table 7 16 SPI Flash Memory Pin Assignment sse 82 Table 7 17 Xilinx 14 pin JTAG Pinout 82 Table 7 18 FPGA Bank 0 JTAG Pin Assignment sess 82 Table 7 19 Pmod Pin AsslgnMent ccce ceil neat e Dub dee RE nei ala 83 Table 7 20 Uncommitted LEDs Pin 84 Table 7 21 DIP Switches Pin Assignment 85 Table 7 22 Push button Switches Pin 8 85 Table 7 23 Jumper Switches Pin Assignment
45. UAD225 GTH Assignment GTREFCLK 0 P N 2 MMCX QUAD225 FMC1 GTH8CH Quad224 225 GTREFCLK 1 P N MMCX FMC2 GTH8CH Quad226 227 FMC3 GTH8CH Quad126 127 FMC4 GTH4 8CH Quad228 229 085 Only FMCS GTHO 8CH Quad230 085 Only 231 085 Only Quad224 FMC6 GTH4CH Quad128 SFP GTH4CH Quad232 085 Only 1 GTH REFO GTREFCLK 0 P N 4 GBTCLKO M2C P CLK FMC 1 GTH GTREFCLK 1 P N La GBTCLK1_M2C_P Figure 7 8 GTH and MMCX Clocks Architecture Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 24 TB KU xxx ACDC8K Hardware User Manual 7 3 3 User Assigned Clocks This board provides a way to make use of dedicated LA signals on the FMC cards allowing them to be configured as global clocks on the FPGA as shown in the figure below The figure states the GC and GBC clock assignments on the FPGA for the FMCs and the DDR4 banks BANK25 3 LA28 J 9 3 LA17 gt Gc abc FMC_3_LA18 ec FMC_3_LA14 ec ABC QBC QBC DBC DBC DBC DBC BANK24 3 LAO CC c CLK_FMC_3_CLK1_M2c ac aac 2 c 3 00 CC GC QBC QBC QBC DBC DBC DBC DBC BANK45 FMC 1 LA18 CC GC 1 LA19 CC 9 0 1 LA28 CC GC 1 LA17 CC es QBC QBC ABC DBC DBC DBC DBC Rev 1 04
46. UI7 0 DAL 7 0 DQSU DQSU DDRA o DQU 7 0 DQL 7 0 DQSU DQSU DORA UO lt DOSL DQSL DMU DML fis DQSL DQSL DMU DML DQUI7 0 DAL 7 0 DQSU DQSU DDRA Wi di DQU 7 0 DQL 7 0 DQSU DQSU PEM e aa DQOSL DQSL DMU DML gt WE DQOSL DQSL DMU DML 46 ank66 gt 0084 SDRAM 4Gbit DDR4 SDRAM 4Gbit DQUI7 0 DAL 7 0 DQSU DQSU DQU 7 0 DQL 7 0 DQSU DQSU DOSL DQSL DMU DML U8 DQSL DQSL DMU DML gt 012 FPGA FPGA Termination Termination Figure 7 12 DDR4 SDRAM Structure Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 76 inreviun 7 6 SFP Connectors Located on the front panel of the TB KU xxx ACDC8K are 4 SFP slots available to the user These ports are standard single SFP modules For each of these modules a 3 pin connector is available to jumper between either RX LOS or TX FAULT A jumper between pins 1 2 connects RX LOS and between 3 2 connects TX FAULT RX LOS to FPGA TX FAULT Each SFP connector has a TX and an RX differential data pair that connect to Quad 232 on the FPGA They also connect to 2 bus through TI s PCA9544A 4 to 1 2 MUX with four available interrupt inputs for each of the downstream pairs Available on the same component is a global interrupt input pin which acts as a logic AND for the four interrupts The PCA9544A chip s I2C address can be set through the A 0 2 inputs through available 4 7k resistors on the board SD0 I
47. USB filtered 5V 1V8 USB PWR TP58 USB UART controller 1 8V I O Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 19 inreviun 7 1 5 Power and Miscellaneous LEDs Shown below are the different LEDs present on the board which serve as power indication or general purpose programmable LEDs Table 7 2 Board LEDs LED Color Used for FPGA Programming DONE signal Bicolor Red Programming in progress D1 Green or Red Green Programming complete D3 Green Clock generation LOCK_IND indicator for U20 D4 Red Clock generation CLKO BAD indicator for U20 D5 Red Clock generation CLK1 BAD indicator for U20 D6 Red Clock generation XTAL BAD indicator for U20 D10 Green 12V Input Uncommitted Green D12 D13 D16 D17 D20 D21 D24 D25 D12 D27 Green amp Red Red D14 D15 D18 D19 D22 D23 D26 D27 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 20 inreviun 7 1 6 Board Power Button This board features a power button rocker switch on the chassis front panel along with 4 SFP connectors a micro USB port and a green and red LED to signal the FPGA programming and idle states The power sequencer monitors the rocker switch power button which disables power supplies on the board when turned off The I position turns ON the power supplies and the O position turns them OFF The FPGAs fan however will be active as long as the 12V supply is live Figure 7 5 Board Power Button 7 1 7 FPGAHR Bank Voltage
48. azi 17 Figure 7 4 12VDC Input Connector and Binding Posts nn ne 18 Figure 7 5 Board Power Button e ec tp bulo denn tore n 21 Figure 7 6 FPGA Banks Assignments 22 Figure 7 7 VCCINT Clock Synchronization eene nennen nennen 23 Figure 7 8 and MMCX Clocks Architecture 24 Figure 7 9 User Assigned Clocks Architecture sse 25 Figure 7 10 High Pin Count FMC se 26 Figure 7 11 FMC 0 to 6 SCL SDA GAO GA4 TD TDO L 32 Figure 7 12 DDR4 SDRAM Structure 76 Figure 7 13 2 MUX Hardware selectable Address Pins 77 Figure 7 14 USB UART 79 Figure 15 Ballery Clrcuil u terrier petere l pee deti dE CE e Ree ode cedo 80 Figure 7 16 FPGA SPI Flash Configuration 81 Figure 7 17 Pmod Connection esee einen enses ns wania 83 Figure 7 18 Jumper Switches Structure 86 Figure 8 1 Jumper and Switch location Component Side sse 87 Figure 8 2 Power Sequencer Default Settings sse 88 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 4 inreviun List of Tables Table 7 1 Voltage Rails Test POINTS ia a tnde d 19 Table 7 2 Board ABIIT 20 Table 7 3 HR Banks Connected Peripherals 21
49. by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising from use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation It is not authorized for use in any system or application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 8 inreviun 1 Related Documents and Accessories Relat
50. ctions by default they are floating 4 TDI TDO The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG C2M PG M2C PRSNT M2C N Referring to the figure above they all have a resistor option for either pull up or pull down However the resistors are not populated by default these pins are floating 6 Power Rails This card provides a 12V output through the 12V0 pins and 3 3V output through the 3V3 and 3V3_AUX pins It is important to note that all the FMC connectors present on this board are equipped with a fuse on the 12VO rail Lastly the VADJ pins provide a 1 8V 2 5V 3 3V rail to FPGA mezzanine cards 7 VREF A M2C VREF B M2C These terminals can be monitored by test points TP83 and TP84 8 VIO B M2C Both pins J39 and K40 for this terminal can also be monitored by test point TP81 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 33 inreviun 7 4 8 FMC HPC 1 J2 This FMC connects GTH lanes and all of the available LA signals to banks on the FPGA High Speed Quad 224 and 225 e 8 GTH lanes 2 differential clock pairs Low Speed Bank 44 e 16 differential LA pairs 2 differential clock pairs Bank 45 e 18 differential LA pairs Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 34 TB KU xxx ACDC8K Hardware User Manual inreviun fa Table 7 6 FMC 1 J2 to FPGA Pinout
51. differential clock pairs Bank 25 e 18 differential LA pairs Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 48 TB KU xxx ACDC8K Hardware User Manual inreviun B Table 7 8 FMC 3 J8 to FPGA Pinout 1 CLK_DIR 126 AF36 DP1 M2C P 2 126 AF37 DP1 M2C N 3 4 DP9 M2C P 8 5 DP9_M2C_N 126 AE38 DP2 M2C P 6 126 AE39 DP2 M2C N 7 8 DP8 M2C P 9 DP8 M2C N 126 AC38 DP3 M2C P 10 126 AC39 DP3 M2C N 11 12 DP7 M2C P AB36 127 13 DP7_M2C_N AB37 127 127 AA38 DP4 M2C P 14 127 AA39 DP4 M2C N 15 16 DP6 M2C P W38 127 17 DP6 M2C N W39 127 127 V36 DP5 M2C P 18 127 V37 DP5 M2C N 19 20 AB32 126 21 AB33 126 126 AG34 DP1 C2M P 22 126 AG35 DP1 C2M N 23 24 DP9 C2M P 25 DP9_C2M_N 5 126 AE34 DP2 C2M P 26 126 AE35 DP2 C2M N 27 28 DP8 C2M P i 29 DP8 C2M N 126 AD36 DP3 C2M P 30 126 AD37 DP3 C2M N 31 32 DP7_C2M_P AC34 127 33 DP7_C2M_N AC35 127 127 AA34 DP4 C2M P 34 127 AA35 DP4 C2M N 35 36 DP6 C2M P Y36 127 37 DP6_C2M_N Y37 127 127 W34 DP5 C2M P 38 127 W35 DP5 C2M N 39 40 RESO 1 04 TOKYO ELECTRON DEVICE LIMITED 49 TB KU xxx ACDC8K Hardware User Manual inreviun FMC 3 J8 126 AH36 DPO C2M P 126 AH37 DPO C2M N
52. ed documents All documents relating to this board can be downloaded from our website Please see attached paper on the products Xilinx FPGA document http www xilinx com support index html content xilinx en supportNav silicon devices fpga kintex ultras cale html DS892 UltraScale device data sheets Kintex UltraScale Architecture Data Sheet DC and AC Switching Characteristics DS890 UltraScale Architecture and Product Overview UG570 UltraScale Architecture Configuration User Guide UG571 UltraScale Architecture SelectlO Resources User Guide UG572 UltraScale Architecture Clocking Resources User Guide UG573 UltraScale Architecture Memory Resources User Guide UG574 UltraScale Architecture Configurable Logic Block User Guide UG575 UltraScale Architecture Packaging and Pinouts User Guide UG576 UltraScale Architecture GTH Transceivers User Guide UG580 UltraScale Architecture System Monitor User Guide UG583 UltraScale Architecture PCB and Pin Planning User Guide PG150 UltraScale Architecture Based Memory Interface Solutions Product Guide Board accessories Power supply brick DC 12V and cable to board qty 1 FMC spacer set Standoff 2 6M x 30mm qty 14 Screw 2 6M x 6mm qtv 14 Power Strip Cord with Individual Switches qty 1 2 Overview The TB KU xxx ACDC8K evaluation board for the Xilinx Kintex UltraScale provides a hardware environment with a purpose of evaluating and developing designs targeting the Kintex Ul
53. een GRN LED 8 66 C16 D26 Red RED LED 4 67 L17 D27 Red RED LED 8 67 N19 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 84 inreviun 7 12 General Purpose Switches 7 12 1 DIP Switches This board is equipped of 4 Copal Electronics CHS 04TA SPST 4 positions DIP switches Slide in the ON position for a logic Low Table 7 21 DIP Switches Pin Assignment Switch RefDes Signal Name FPGA Bank FPGA Pin SWITCH 1 67 N18 SWITCH 2 67 T18 SWITCH 3 67 T17 SW17 SWITCH 4 67 N17 SWITCH 5 67 N16 SWITCH 6 67 R16 SWITCH 7 67 P16 SW18 SWITCH 8 67 P19 SWITCH 9 67 P18 SWITCH 10 68 A23 SWITCH 11 68 C24 SW19 SWITCH 12 68 F22 SWITCH 13 68 H22 SWITCH 14 68 L22 SWITCH 15 68 J21 SW20 SWITCH 16 68 R23 7 12 2 Push Switches The board also features 8 C amp K Components KMR211GLFS push buttons Pressing the button sends logic low in the default position they are set to logic high Table 7 22 Push button Switches Pin Assignment Push button RefDes Signal Name FPGA Bank FPGA Pin SW7 PUSHBUTTON 1 46 A33 SW8 PUSHBUTTON 5 46 F34 SW9 PUSHBUTTON 6 46 F35 SW11 PUSHBUTTON 2 46 D36 SW12 PUSHBUTTON 3 46 F39 SW13 PUSHBUTTON 7 46 J36 SW15 PUSHBUTTON 4 46 E38 SW16 PUSHBUTTON 8 47 B29 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 85 inreviun 7 12 3 Jumper Switches Lastly 8 jumper switches were conveniently placed at the user s di
54. ell as flow control signals Using the PC s virtual COM port drivers there are different supported baud rates that are compatible with this controller and can be set during the COM port configuration TB KU 060 075 ACDC8K Terminal Debug Register Veco RX D Micro USB MicroUSB IX e D Connector Cable RTS CP2103 FPGA lt Ts Type AB Bank46 D ESD Protection Figure 7 14 USB UART Interface Table 7 15 UART Interface Pin Assignment FPGA Bank USB_UART_TX USB_UART_RX USB_UART_RTS_N USB_UART_CTS_N 24 AG30 AL33 AN29 AT32 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 79 inreviun 7 8 Battery This board contains an 11 6 mm coin cell battery connected to the VBATT pin which serves as a battery backup supply for the FPGA s internal volatile memory that stores the key for AES decryption More information is available in Xilinx s UltraScale configuration UG570 document It is possible to monitor the battery s voltage through test point TP68 Figure 7 15 Battery Circuit Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 80 inreviun 7 9 Dual Quad x8 SPI Flash This board has a 256Mbit dual quad SPI flash x8 memory for FPGA configuration purposes Please refer to Xilinx s UltraScale configuration UG570 document on Master SPI Dual Quad x8 for more information The multi I O SPI Flash memory is used to provide non vola
55. ev 1 04 TOKYO ELECTRON DEVICE LIMITED 60 inreviun For FMC 4 J11 1 GBTCLK 0 1 M2C P N These clocks are connected to Quad 228 XCKUO060 and 085 of the FPGA while this board provides an MMCX interface for one pair of clocks on Quad 229 XCKUO85 The other pair is provided by the system clock buffer 2 SCL SDA The board provides test points with pull up options to enable I2C communication with the FPGA By default the pull ups are not populated 8 GAO GA1 This board provides pull up or pull down options for these connections by default they are floating 4 TDI TDO The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG C2M PG M2C PRSNT M2C These all have a pull up or pull down resistor option However the resistors are not populated by default these pins are floating 6 Power Rails This card provides a 12V output through the 12V0 pins and 3 3V output through the 3V3 and 3V3 AUX pins It is important to note that all the FMC connectors present on this board are equipped with a fuse on the 12VO rail Lastly the VADJ pins provide a 1 8V rail to FPGA mezzanine cards 7 VREF A M2C VREF B M2C These terminals can be monitored by test points TP87 and TP88 8 VIO B M2C Both pins J39 and K40 for this terminal can also be monitored by test point TP85 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 61 inreviun 7 4 6 FMC HPC 5 J14 This FM
56. his board provides an MMCX interface for one pair of clocks on Quad 225 The other pair is provided by the system clock buffer 2 SCL SDA The board provides test points with pull up options to enable I2C communication with the FPGA By default the pull ups are not populated 3 GAO GA1 This board provides pull up or pull down options for these connections by default they are floating 4 TDI TDO The JTAG TDO pin is connected with a loopback to TDI through a 0 ohm resistor that is not populated by default 5 PG C2M PG M2C PRSNT M2C These all have a pull up or pull down resistor option However the resistors are not populated by default these pins are floating 6 Power Rails This card provides a 12V output through the 12V0 pins and 3 3V output through the 3V3 and 3V3_AUX pins It is important to note that all the FMC connectors present on this board are equipped with a fuse on the 12VO rail Lastly the VADJ pins provide a 1 8V rail to FPGA mezzanine cards 7 VREF A M2C VREF B M2C These terminals can be monitored by test points TP75 and TP76 M2C Both pins J39 and K40 for this terminal can also be monitored by test point TP73 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 40 inreviun 7 4 8 FMC HPC 2 J5 This FMC connects GTH lanes and 6 differential pairs of LA signals to banks on the FPGA High Speed Quad 226 and 227 e 8GTH lanes 2 differential clock pairs Low Speed Bank 25 e 66 d
57. ifferential LA pairs Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 41 TB KU xxx ACDC8K Hardware User Manual inreviun fa Table 7 7 FMC 2 J5 to FPGA Pinout 1 CLK_DIR 227 AD2 DP1 M2C P 2 227 AD1 DP1 M2C N 3 4 DP9 M2C P 5 DP9 M2C N 227 AF2 DP2 M2C P 6 227 AF1 DP2 M2C N 7 8 DP8 M2C P 9 DP8 M2C N 227 AG4 DP3 M2C P 10 227 AG3 DP3 M2C N 11 12 DP7 M2C P AH2 226 13 DP7_M2C_N AH1 226 226 AJ4 DP4 M2C P 14 226 AJ3 DP4 M2C N 15 16 DP6 M2C P AK2 226 17 DP6 M2C N AK1 226 226 AL4 DP5 M2C P 18 226 AL3 DP5 M2C N 19 20 AF10 226 21 AF9 226 227 AE4 DP1 C2M P 22 227 AES DP1 C2M N 23 24 DP9 C2M P 25 DP9_C2M_N 227 AF6 DP2 C2M P 26 227 AF5 DP2 C2M N 27 28 DP8 C2M P 29 DP8_C2M_N 227 AG8 DP3 C2M P 30 227 AG7 DP3_C2M_N 31 32 DP7_C2M_P AH6 226 33 DP7_C2M_N AH5 226 226 AJ8 DP4 C2M P 34 226 AJ7 DP4 C2M N 35 36 DP6 C2M P AK6 226 37 DP6 C2M N 5 226 226 AL8 DP5 C2M P 38 226 AL7 DP5 C2M N 39 40 RESO Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 42 inreviun FMC 2 J5 1 227 DP0_C2M_P 2 227 DPO C2M N 3 4 226 ID 5 226 227 DP0_M2C_P 6 227 DP0_M2C_N 7 8 9 lo
58. in Bank GND 1 7 VREF B M2C CLK3 M2C P 2 GND CLK3 M2C N 3 GND GND 4 CLK2 M2C P GND 5 CLK2 M2C N 64 AD16 6 GND 64 AE16 7 AG17 64 GND 8 AG16 64 9 GND 10 GND 11 12 GND 13 GND 14 15 GND 16 GND 17 18 GND 19 GND 20 21 GND 22 2 GND 23 24 GND 2 25 GND 26 27 GND 28 GND 29 30 GND 31 GND 32 33 GND 34 GND 35 36 GND 37 2 GND 38 8 VIO B M2C 39 GND GND 40 8 VIO B M2C Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 31 inreviun 12V0 R620 R621 GAO GA1 PG C2M PG M2C PRSNT M2C N 3V3 AUX SCL 11 SDA VADJ VADJ RESO VADJ VADJ TCK TDI VIO_B_M2C TDO VIO_B_M2C TMS TRST_N VREF_A_M2C VREF_B_M2C 30 05 14 RvR ASP 134486 01 CONN ARRAY SOCKET SKT 400 POS 1 27MM SOLDER ST SMD TRAY Figure 7 11 FMC 0 to 6 SCL SDA GA0 GA1 TDI TDO Note The above structure is identical for all FMC connectors on this board with the exception of test points and reference designators being different per FMC Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 32 inreviun For FMC 0 J1 1 There are no GTH channels on this connector so the GBTCLK1_M2C_P N signals are not connected 2 SCL SDA The board provides test points with pull up options to enable I2C communication with the FPGA By default the pull ups are not populated 3 GAO GA1 This board provides pull up or pull down options for these conne
59. inreviun Rev 1 04 TB KU xxx ACDC8K Hardware User Manual Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 1 inreviun Revision History Version Date Description Publisher Rev 1 00 2014 10 15 Initial Release DM Rev 1 01 2015 01 19 Updated content with board pictures and FMC pinout DM tables Rev 1 02 2015 02 18 Updated Figure 4 1 7 2 7 6 7 16 KM Rev 1 03 2015 07 21 Released for 060 Morita Added Standoffs and Power Strip cord Odajima Updated Figure 5 1 7 6 7 8 7 9 7 12 Updated Table 7 16 7 22 7 23 Added 8 1 Default Settings Rev 1 04 2015 09 28 7 12 1 Updated DIP Switches polarity Morita Slide in the ON position for a logic Low Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 2 inreviun Table of Contents 1 Related Documents and Accessories 9 2 OVeIVIBW TTT tete eset a eio ese eie feos vivi rts ese 9 d baa tat 10 4 u m 11 5 External View of the Board c coo A INGAS 12 6 Board Specifications utu E M EE E aut 13 7 Description of Componenits kibaka el a 16 74 Power SUpplyStruoture sees a ee 16 7 1 1 Power i 17 7 1 2 Power Input connectors aaa 17 7 1 3 DC 4 Header and
60. lies to the Xilinx including Veco must be at 90 within 40ms i e total startup times plus sequencer delay must be 40ms for all Xilinx rails Figure 8 2 Power Sequencer Default Settings Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 88 inreviun l TOKYO ELECTRON DEVICE Inrevium Company URL http solutions inrevium com http solutions inrevium com jp E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4031 FAX 81 45 443 4063 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 89
61. raight 2x6 male header for Pmod connections which includes 3 3V and ground signals and eight I O 1 8V 3 3 Pmod TI 2x6 Bank 44 and 45 Voltage amp SMT PMOD 7 0 FPGA Translator PMOD 7 0 Molex 15912120 J31 Figure 7 17 Pmod Connection Table 7 19 Pmod Pin Assignment Pmod Pin Signal Name FPGA Pin Pmod Pin Signal Name FPGA Pin 1 PMOD 0 AU24 7 PMOD 4 AT25 2 PMOD 1 AP20 8 PMOD 5 AP26 3 PMOD 2 AJ23 9 PMOD 6 AK26 4 PMOD 3 AH21 10 PMOD_7 AH27 5 GND GND 11 GND GND 6 VCC 3V3 lt gt 1 8 FMO 12 VCC 3V3 lt gt 1V8_FMC Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 83 inreviun 7 11 General Purpose LEDs The TB KU xxx ACDC8K has 16 user programmable LEDs There are 8 green colored LEDs and 8 red ones The FPGA can be programmed to output a logic high to turn on a LED and a logic low to turn it off Table 7 20 Uncommitted LEDs Pin Assignment LED Signal FPGA FPGA RefDes Color Name Bank Pin D12 Green GRN LED 1 66 A12 D13 Green GRN LED 5 66 H13 D14 Red RED_LED_1 67 H16 D15 Red RED_LED_5 67 K17 D16 Green GRN_LED 2 66 G12 D17 Green GRN_LED 6 66 N13 D18 Red RED_LED 2 70 M32 D19 Red RED_LED 6 67 R18 D20 Green GRN LED 3 66 E15 D21 Green GRN LED 7 67 D20 D22 Red RED LED 3 67 M16 D23 Red RED LED 7 67 R17 D24 Green GRN LED 4 66 H12 D25 Gr
62. ription Bank Pin 1 021 SFP 1 RX L TX FA FPGA OD Selected RX_LOS or TX FAULT signal 64 AD18 SFP 1 RS FPGA RS optical transmit and receive signaling rate 64 AM16 2 022 SFP 2 RX L TX FA FPGA OD Selected RX_LOS or TX FAULT signal 64 AN16 SFP 2 RS FPGA RS optical transmit and receive signaling rate 64 AU20 J25 SFP 3 RX L TX FA FPGA OD Selected RX LOS or TX FAULT signal 65 AE15 SFP 3 RS FPGA RS optical transmit and receive signaling rate 65 AL15 4 J26 SFP 4 RX L TX FA FPGA OD Selected RX_LOS or TX FAULT signal 65 AM15 SFP 4 RS FPGA RS optical transmit and receive signaling rate 65 AW15 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 78 inreviun 7 7 USB to UART Controller The TB KU xxx ACDC8K features a Silicon Labs CP2103 USB to UART interface to communicate with a PC This module creates a virtual COM port on the computer to allow the user to connect through standard USB The USB interface on this card is Micro USB Type AB which mates with either Micro A or Micro B cables Table 7 14 Micro USB Type B and AB Compatibility Receptacle Plug Micro B Micro A 2 G HHHH GHARI Micro B A Curr Micro AB Micro A Hi gt E gt Micro B 7 The UART signals are connected to the FPGA s single ended pins on Bank 24 Provided below is a table indicating where the signals connect Both the UART transmit and receive data signals are connected as w
63. rs LA Group B 6pairs LA Group B 6pairs LA Group A 36pairs GTH 8Lanes 060 not connected GTH 8Lanes 060 4Lanes GTH 8Lanes GTH 8Lanes Figure 5 1 Board Top View Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 12 inreviun 6 Board Specifications Figure 6 1 shows the board specifications External Dimensions Number of Layers Board Thickness Material FPGA FMC HPC CC Connector Micro USB Connector Xilinx JTAG Connector Pmod Connector Power Input Connector 313 08 mm W x 208 28 mm H 20 layers 2 0828 mm 10 Megtron 4 Xilinx Kintex UltraScale XCKU060 XCKU085 FFVA1517 FLVA1517 package Samtec ASP 134486 01 Hirose Electric s ZX62D AB 5P8 Molex s 87832 1420 Molex s 15912120 TE Connectivity s 1 350948 0 Emerson Network s 111 0702 001 and 111 0703 001 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 13 inreviun or J e mre wet 224 o 200 n e e 12 1 e e e va o a H d ISSO eh Ur 3 nz wA E seis iy SE e gn gn uuu m 3 um wa 3 Pu T7131 mus TEF 4 ka D tul mma F ae l PEI 1 E u H E 3 et pied r Mri CET gr m 4 Kana 5 fili M Df 3 i 7 i SUN 9 m uu 1 T T T 4 E ali C Ed EJ FA el
64. sposal available as a standard 16 pin header It provides uncommitted GPOs that connect to the board s FPGA 1V2_DDR4 18 03 13 RK TSM 108 01 T DV P TR CONN HEADER 16POS 100IN DBL SMD Figure 7 18 Jumper Switches Structure The signals output logic high by default when there is no jumper connected Connect an odd numbered pin to the even numbered pin across from it to output a logic low to the FPGA The header s reference designator on the board is J42 Table 7 23 Jumper Switches Pin Assignment Jumper Option Signal Name FPGA Bank FPGA Pin 1 2 HDR1 47 J29 3 4 HDR2 47 H33 5 6 HDR3 47 J30 7 8 HDR4 47 J31 9 10 HDR5 47 M30 11 12 HDR6 47 L30 13 14 HDR7 47 M29 15 16 HDR8 47 L29 Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 86 TB KU xxx ACDC8K Hardware User Manual 8 Appendix 8 1 Default Settings Following Figure shows a _ Jumper and DIP switches Figure 8 1 Jumper and Switch location Component Side Table 8 1 Default Settings No Silk No Initial Setting Function 1 SW1 1 2 POR Override ON OFF 2 SW2 ALL OFF Video Clock setting 3 SW17 18 19 20 ALL OFF User DIP Switches setting 4 J44 Open HR Bank voltage 1 8V 2 5V 3 3V 5 J40 Open PMBUS ADDRO GND 90 9K 196 GND 41 2K 196 No Supply 6 J41 Open PMBUS ADDR1 GND 90 9 1 GND 41 2K 196 No Supply 7 J23 Open SF
65. tile code and data storage Access to programming the FPGA Flash has been provided to the Xilinx core and can be programmed through GPIO pins UserlO shown on figure below Devices N25Q256A11EF840E Micron 256Mbit x1 x2 x4 x8 support Devices Data Rate 108 MHz maximum clock frequency in single transfer rate mode VCCO VCCO DDR4 1V8 VCCAUX DDR4 L VCCO 70 UserlO Doo T Use lO D01 Level Bango do D02 shift VCCO HR SR TXS 1 8V 2 5V 3 3V UserlO CS 0108 Selectable UserlO CCLK UserlO FET VCCO HR 1V8_VCCAUX VCCO HR 1V8_VCCAUX Level VCCO_0 D01 shift 002 TXS 5 QSPI VCCO HR Banko DOJ 0108 4 N25Q256 Voltage cs l E CFGBVS CCLK L gt OE VCCO HR VCCO HR 1V8_VCCAUX 1V8 VCCAUX VCCO 65 D04 005 po QSPI Bank65 TXS N25Q256 or 0108 cs UserlO NA Figure 7 16 FPGA SPI Flash Configuration Structure In order to pre configure the flash using the Zynq s interface via JTAG it is necessary that the user drives signal SPIFLASH_ZYNQ_CFG_OD low prior to programming using JTAG SPIFLASH_ZYNQ_CFG_OD is high default Bank 0 used for configuration SPIFLASH_ZYNQ_CFG_OD is low Zynq UserlO programs flash through JTAG Rev
66. traScale XCKUO60 and XCKUO85 featuring FFVA1517 package Speed grade 2 FPGA is mounted on this board The TB KU xxx ACDC8K platform provides a common feature set including DDR4 SDRAM memory components general purpose I O a USB to UART interface four SFP modules seven VITA 57 high pin count FPGA mezzanine cards FMC connectors a JTAG and a PMOD interface Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 9 inreviun 3 Feature Xilinx Kintex UltraScale Memory FMC Connector On Board Clocks Interface XCKUO60 XCKUO85 2 speed grade in FFVA1517 package 4GByte DDR4 SDRAM 16Gbits 4 ICs x 32M words x 16 bits x 8 banks x 2 banks of ICs 256Mbit Dual Quad SPI Flash TI s UCD9090 power supply sequencer and monitor 7 x Samtec s ASP 134486 01 CC HPC 10 1 IDT s ICS849N2021 clock generator IDT ICS849N2021 PLL 25MHz CMOS oscillator 4OMHz crystal IDT 148 50MHz LVDS oscillator IDT 156 25MHz LVDS oscillator IDT 200 00MHz LVDS oscillator 4x SFP modules MMOX for external clocks Standard Xilinx JTAG 14 pin header Digilent Pmod M compatible header 2x6 Push switches DIP switches jumpers and LEDs Single chip USB to UART bridge Micro USB 2 0 Type AB connector Note 1 Refer to VITA 57 FMC Standard http www samtec com standards vita aspx Rev 1 04 TOKYO ELECTRON DEVICE LIMITED 10 inreviun 4 Block Diagram The following figure shows the block diagram of TB KU xxx ACDC8K FMCO does not ha
67. ve any high speed GTH lanes XCKUO60 FMC1 2 and 3 have 8 high speed GTH lanes FMCA and 6 have 4 high speed GTH lanes FMC5 and SFP do not have any high speed GTH lanes XCKUO85 FMC1 2 3 4 and 5 have 8 high speed GTH lanes FMC6 and SFP have 4 high speed GTH lanes There are two groups of FMC HP connections LA group A and group B LA group A has 72 I O connected to the FPGA and group B has 12 FMC6 GTH 4ch 4GTH Quad128 I O LA Group B 1 8V Fix HRI O 12pin bank 24 46 c Power Power Supplies 0V95 VCCINT FMC3 GTH 8ch Quad126 127 LA Group A 36pair 1 8V Fix 72pin bank 24 46 25 47 DDR4 x 2 Banks Xtal Contig 222 senm Pin header TES Front panel LED 2pin Total 8ch RESEPE Config DONE connected DDRA bank ice Push switches 8pin 200MHz ki cid Total 8ch for DDR4 2 connected DDR4 bank 2pin FMCO GTH 0ch xu IO voltage select 3 3V 2 5V LEDs 16pin al Rehd 148 5MHz al oaa b n for User 84 VO pin bank 64 65 aa eo SFPRIGTHJON connected DDR4 bank pim ES EFE DIP switches 16pin X tal Total 16ch 200MHz connected DDR4 bank for DDR4 1 10pin bank 64 65 2pin USB type AB UART PMOD 8pin FMC5
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