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Microwind & Dsch Version 2 User`s Manual

1. MicroWind simulation parameters 20 01 02 DSCH amp MICROWIND USER S MANUAL deltaT 0 30e 12 Minimum simulation interval dT vdd 1 2 hvdd 3 3 temperature 27 riseTime 0 05 End CMOS 0 12um 101 13 Design Rules File for 0 12um 20 01 02 DSCH amp MICROWIND USER S MANUAL 13 References 14 References 1 R J Bakcer H W Li D E Boyce CMOS design layout and simulation IEEE Press 1998 www ieee org 2 M John S Smidth Application Specific Integrated Circuits Addison Wesley 1997 ISBN 0 201 50022 1 www awl com cseng 3 B Razavi Design of Analog CMOS integrated circuits McGraw Hill ISBN 0 07 238032 2 2001 www mhhe com 4 Y P Tsividis Operating and Modeling of the MOS transistor McGraw Hill 1987 ISBN 0 07 065381 X 5 S M Sze Physics of Semiconductor devices John Wiley 1981 ISBN 0 471 05661 8 6 Y Cheng C Hu MOSFET Modeling amp BSIM3 user s guide Kluwer Academic Publishers 1999 7 A Hastings The Art of Analog Layout Prentice Hall 2001 ISBN 0 13 087061 7 8 N Weste K Eshraghian Principles of CMOS VLSI design Addison Wesley ISBN 0 201 53376 6 1993 9 K Lee M Shur T A Fjeldly T Ytterdal Semiconductor Device Modeling for VLIS Prentice Hall 1993 ISBN 0 13 805656 0 10 W Liu Mosfet Models for SPICE simulation including Bsim3v3 and BSIM4 Wiley amp Sons 2001 ISBN 0 471 39697 4 11 C Mot
2. INSR TOULOUSE National Institute of Applied Sciences Toulouse FRANCE Department of Electrical amp Computer Engineering Microwind amp Dsch Version 2 User s Manual February 2002 Etienne Sicard Etienne sicard insa tlse fr http intrage insa tlse fr etienne 1 20 01 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction About the author ETIENNE SICARD was born in Paris France in June 1961 He received a B S degree in 1984 and a PhD in Electrical Engineering in 1987 both from the University of Toulouse He was granted a Monbusho scholarship and stayed 18 months at the University of Osaka Japan Previously a professor of electronics in the department of physics at the University of Balearic Islands Spain E Sicard is currently an associate professor at the INSA Electronic Engineering School of Toulouse His research interests include several aspects of design of integrated circuits including crosstalk fault tolerance and electromagnetic compatibility of integrated circuits Etienne SICARD is the author of several educational software in the field of microelectronics and sound processing Copyright Copyright 1997 2002 Etienne Sicard Address Etienne Sicard INSA DGEI 135 Av de Rangueil 31077 TOULOUSE Cedex 4 FRANCE Tel 33 561 55 98 42 Fax 33 561 55 98 00 e mail etienne sicard insa tlse fr Web information http intrage insa tlse fr etienne 2 20 01 02
3. high voltage l3v3to 0 7 LS 0 02 13t30x 7e 9 BSIM4 parameters Nmos NMOS b4vtho 0 4 b4k1 0 45 b4k2 0 1 b4xj 1 7e 7 b4toxe 3 5e 9 b4ndep 1 8e17 b4d0vt 2 3 b4dlvt 0 54 b4vfb 0 9 b4u0 0 068 b4ua le 15 b4uc 0 047e 15 b4vsat 100e3 b4pscbel 230e6 b4ute 1 8 b4ktl 0 1 b4lint 0 0le 6 b4wint 0 02e 6 b4xj 1 5e 7 b4ndep 1 7e17 b4pclm 1 1 high speed b4v2to 0 3 100 13 Design Rules File for 0 12um b4t2ox 3e 9 high voltage b4v3to 0 7 b4t30x Te 9 Pmos BSIM4 PMOS b4vtho 0 4 b4k1 0 45 b4k2 0 1 b4xj 1 7e 7 b4toxe 3 5e 9 b4ndep 1 8el7 b4d0vt 2 3 b4divt 0 54 b4vfb 0 9 b4u0 0 028 b4ua le 15 b4uc 0 047e 15 b4vsat 60e3 b4pschel 230e6 b4ute 1 8 b4kt1 0 1 b4lint 0 01le 6 b4wint 0 02e 6 b4xj 1 5e 7 b4ndep 1 7e17 b4pclm 0 7 NEGAR Ss peed b4v2to 0 3 b4t2ox 3e 9 lt hagh voltage b4v3to 0 7 b4t3ox 7e 9 CIF Layers MicroWind layer CIF layer overetch cif nwell 1 0 0 cif diffp 17 0 5 CIE diff dos 05 cif aarea 2 0 5 cift p ly T 0 Gur contact 19 07025 cif metal 23 0 0125 cif via 25 0 0125 cif metal2 27 0 0125 cif via2 32 0 0125 cif metal3 34 0 0125 cif via3 35 0 0125 cif metal4 36 0 0125 cif via4 52 0 0125 cif metal5 53 0 0 Gif viaj 54 0s 0 cif metal6 55 O cif passiv 31 0 0 0 cif text 56 0
4. arn rea E Sab EEE Fig 9 3 Simulation of the analog digital converter ADC MSK In the simulation shown in Figure 9 3 the comparators CO and C1 work well but the comparator C2 is used in the upper limit of the voltage input range The generation of combinations 00 01 and 10 is correct TI 20 01 02 MICROWIND amp DSCH USER S MANUAL 9 Converters Digital Analog Converter The digital analog converter converts a digital three bit input AO A1 A2 into an analog value Vout The polysilicon resistive net gives intermediate voltage references which flow to the output via a transmission gate net The resistance symbol is inserted in the layout to indicate to the simulator that an equivalent resistance must be taken into account for the analog simulation The schematic diagram and layout of the digital analog converter are shown in Figure 9 4 Analog output Vout V ojo ojo fh loss o ro fo fs oo ho h prs Palv E aro l 7 Paim REN E pz i REE any Tt E de E i R ae el iae Slee H eee e ana Braai p l MEEL E ee ms ae tal f me ETE ity pS FHE BH Fej Farrag OS EN Ca O ad A2 nA2 Ha T H eet che HFH cee EERIE ES are ait amis ESSE Te 2 ote ee Al nAl AO nAO Fig 9 4 Schematic diagram and implementation of the digital analog converter DAC MSK 78 20 01 02 9 Converters MICROWIND amp DSCH USER S MANUAL ns 18 0 analog conver
5. 4 Li 1 i j sotem TEA 0 20 Lai gee te V varies from the difference Power 4 39 mw 1 L O 0 00 1 8 to 2 0V Se ae anaes ON 3 e ara a de ss a asa A daa aha tees a V is constant 1 9V 5 Figure 8 12 Layout and transient simulation of the differential amplifier AmpliDiff MSK 71 20 01 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells MEASURE THE GAIN 1 Click Voltage vs Voltage to select static characteristics mode 2 Select Slope in the Evaluate menu 3 Click More to compute the static characteristics of the differential amplifier The value of the gain is added on the simulation window MEASURE THE INPUT RANGE The best way to measure the input range is to connect the differential amplifier as a follower that is Vout connect to V In this case a slow ramp is applied on the input V and the result is observed on the output The valid input range 0 5 1 9V is the value of V for which the output copies the same voltage in a reasonable time Wide Range Amplifier The wide range amplifier is built using a voltage comparator and a power output stage Its schematic diagram is reported in Fig 8 13 The difference between V and V is amplified and it produces a result codified Vout The gain near 2 5V is very high more than 100 Use the Voltage vs Voltage simulator mode to get the transfer characteristics Vout V Current Mirror tL tN Vout Output V
6. NAME DESCRIPTION VALUE aF um Metal to metal at 4A distance 4A width CM2M2 Metal to metal 2 91 20 01 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules s The crosstalk capacitance value per unit length is H H Metal 3 given in the design rule file for a predefined interconnect width w 4A and spacing d 4A CM2M2 nm H In Microwind2 The computed crosstalk capacitance 1s not CMeMe dependant on the interconnect width w H H Meral The computed crosstalk capacitance value is a asd proportional to 1 4 where d is the distance between 12 6 Resistance NAME DESCRIPTION VALUE Resistance per square for polysilicon Resistance per square for polysilicon2 0 05 12 7 Vertical Aspect of the Technology The vertical aspect of the layers for a given technology is described in the RUL file after the design rules using coed HE height and TH thickness for all layers The figure 12 3 below illustrates the altitude 0 which corresponds to the channel of the MOS The height of diffused layers can be negative for P EPI layer for example a Layer altitude in um 2 0 1 0 Altitude 0 0 control E 7 o y 1 0 STI height is 2 0 negative EPI height is negative 92 20 01 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules Figure 12 3 Description of the 2D aspect of the CMOS technology DESCRIPTION PARAMETERS Buried layer made of P used to create a HE
7. V B Vbias ESA Amplifier Symbol E we y Differential pair Output stage Wide Range Amplifier Fig 58 13 Node description and schematic diagram of the analog amplifier AMPLI2 MSK 72 20 01 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells HHRHH HFH e EEN ye EH A ee a r A rra ye O o e E rr e ee qe O EA EEE EEE E O EE EE EEE A Wee nl E tt A do e A e AA Y TAN A AA Fig 8 14 Design of the analog amplifier AMPLI2 MSK r cn I I I l Wt l eaters out MENTSE Oeste hed Lat 0 0 2 0 40 6 0 8 0 10 0 12 0 14 0 16 0 19 0 ns Fig 8 15 Transient simulation of the analog amplifier AMPLI2 MSK connected as a follower You can easily build a follower by designing an extra connection from Vout to V This layout is shown in Figure 8 14 The output stage 1s not strong enough to be able to drive large loads such as output pads 13 20 01 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells 8 6 Voltage Controlled Oscillator The voltage controlled oscillator is able to produce a square wave with a frequency varying depending on an analog control Vc Ideally the frequency dependence with Vc should be linear One example of voltage controlled oscillator is given in figure 8 16 It consists of a ring oscillator with three stages Vc acts on the resistance of the supply path which acts on the speed response of the inverters rill ai a as pl Voltage Ctr Osc C Fig
8. 8 16 Schematic diagram of a voltage controlled oscillator Voltage Contraled Oscillator EPA TT PT Ana ae A E A E salee a iw L Pre HE at ol E Ke AAA DEF Ao L 7 TS LERLE A E aw gt l E i sat Ca a Ca Ca Ca Ca Ca Ca Ca Ca Ca Ca a et at a at at a Ca Ca nan na nan na Hel nan na mr aan ATE uN iat an Eph an El pel En ERE AE i aang bese an E eS ES Fig 8 17 Implementation of a voltage controlled oscillator based on a 5 stage ring oscillator 74 20 01 02 EA q AA 8 Analog Cells ee ee E SAS L i I i AAA IEA i i 7 03 6 27 CEST a os ete E FO Nee Ss en oe E AI TES E ag wo em tote th ce See eg eS ge ae eel AE 1 A 1 7 ere ER aa eee ry Pee Yo a ce ca ty be ee ae ge ghee Ee MON TI AR Bow teat ee et ot a Frequency GHiz ae _ A A A a 7 10 00 8 00 eno phm MICROWIND amp DSCH USER S MANUAL aE ee o A E 20 01 02 m obcego SS E A E gay Ae aa t pa oj A S A AA SS AA AAN we use the specific mode Frequency and Voltages to plot the gt 18 frequency variation with Vc The VCO output is a frequency varying square wave Its 0 00 Fig 8 18 Simulation of the voltage controlle
9. ClockDiv2 MSK 60 20 01 02 7 5 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories RAM Memory The schematic diagram of the static memory cell used in High Capacity Static RAMs is given in figure 7 11 The circuit consists of 2 cross coupled inverters and two nMOS pass transistors The cell has been designed to be duplicated in X and Y in order to create a large array of cells Usual sizes for Megabit SRAM memories are 256 x 256 cells or higher An arrangement of 4x4 RAM cells is also shown in figure 6 14 The selection line Sel concerns all the cells of one row The lines Data and nData concern all the cells of one column Memory Cell Fig 7 11 The schematic diagram of the static RAM cell RAM1 SCH The RAM layout is given in Figure 7 12 Click on File gt Open gt RAM MSK to read it The Data and nData signals are made with metal2 and cross the cell from top to bottom The supply lines are horizontal made with metal3 This allows easy matrix style duplication of the RAM cell The cross section shows the nMOS devices and the connection to VSS using metal3 situated on the middle of the cell The Data and nData lines in metal2 are on both sides 61 20 01 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories Fitri JEE Ree EEEE LEESI FFFFF H IO Fig 7 12 The layout of the static RAM cell RAM1 MSK WRITE CYCLE Values 1 or O must be placed on Data and the data inverted value on nData Then
10. Duplicate X Y has been used to duplicate the full adder layout vertically An E AE AAA VERA aa pep aa aa e a EEE EEEE F r nar AE BLAS ya ie A ue poeta E ay ae d A aa oe al aoe mui rg ead El AA Pe arcs ner She Amalie eee att Fa Gres rt deg ieee oma 2 et EFA BIE oo pe a mur BE FF Ein P asne Ar E pes ESA re a ER i B ae ae ae ese BLA EE ee Alo EIA man rele Ra an HF e HPE FIRE kj BFI ta Nicaea sity et Hie TA H E rana PF Each iL oe HET TE tne coe eee raat ett tt m peed 13 ES A io Pa pl ne r E Ae ee e IIA jo El A Y LLL A Y a WET Pere eee SI ara IP 777 aur ieee dE E e e aoa VE Eee pe ees ES ME 1 oo bil Fe E E TA Helg T PA M Pa Fi rH pos ene ge at A LH ea IE tne A i F H fr pd ala io E 03 EIF ES E eat mE EAS ails asl HE PB ink A I AH F Lu maA E gt Fj i fe AE E trea a 1 PEET a eS ae L mi Fa aie FE IF un a itil brie ae mE a as k aeh AE boa A O E pap n F Ml i i A EAN id ER ARTE HEA Za ae ps Fig 6 7 Design and simulation of the four bit adder ADD4 MSK 90 20 01 02 6 6 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics Comparator The truth table and the schematic diagram of the comparator are given below The A B equality represents
11. Fig 4 4 int i out anout Load Capa l Charge Discharge Fig 4 4 Short circuit current in CMOS inverters The second is the charging discharging power which depends on the output wire capacitance With small loading the short circuit current is dominant But as the number of gates connected to the inverter increase the load capacity increases Consequently the charging and discharging current starts to dominate the short circuit current 31 20 01 02 4 3 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Fanout effect The fanout corresponds to the number of gates connected to the inverter output Physically a large fanout means a large number of connections that is a large load capacitance An inverter circuit is simulated using different clock fanout and supply conditions The initial configuration is a 1OOMHz clock one output connected to the inverter and a supply voltage 2 5V To investigate the fanout effect on the consumption we simulate first the inverter with one single output In the simulation chronograms we observe that 0 018 mW with a fanout The corresponding file is FANOUT1 SCH Now we add other lights to the output node thus increasing the charge capacitance In the simulation chronograms both the inverter delay and the power consumption have increased 0 059 mW with a fanout of 4 The power consumption linearly increases with the load capacitance This is mainly due to the current needed
12. The BSIM4 MOS Model A family of models has been developed at the University of Berkeley for the accurate simulation of sub micron technology The Berkeley Short channel IGFET Model BSIM exist in several version BSIMI BSIM2 BSIM3 The BSIM3v3 version promoted by the Electronic Industries Alliance EJA is an industry standard for deep submicron device simulation A new MOS model called BSIM4 has been introduced in 2000 A simplified version of this model is supported by Microwind2 and recommended for ultra deep submicron technology simulation BSIM4 still considers the operating regions described in MOS level 3 linear for low Vds saturated for high Vds subthreshold for Vgs lt Vt but provides a perfect continuity between these regions BSIM4 introduces a new region where the impact ionization effect 1s dominant The number of parameters specified in the official release of BSIM4 is as high as 300 A significant portion of these parameters is unused in our implementation We concentrate on the most significant parameters for educational purpose The set of parameters is reduced to around 20 MOS Viewer for Meme Wih 0070 Length 0 120 pe ld ws Wd ide wg lagid veia Thrashold votage Mabilite Dubug ds mo E THO o 00 Bro foso Y AAA MS ty 1 20 Tose 2500 55 INE s fr curo 2300 4 LS aT 60 FT e ro o ars A IE IE ee ce 15 gy T IM j UA 1 000 E A IA ES 50 PAT e at o
13. The addition and subtraction are realized using the ADDER user symbols A digital multiplexer made from MOS devices selects one of the 4 operations results and directs it to a single output line Result Ll 3 Carry Sump Borrow Res Alu Fig 6 10 The 1 bit ALU operates the and or addition and substraction ALUIbit SCH 52 20 01 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories 7 Latches Memories 7 1 This chapter details the structure and behavior of latches and memory circuits The RS Latch the D Latch and the edge sensitive register are presenter Then the concepts of ROM static RAM and dynamic RAM memories are introduced together with simulations RS Latch The RS Latch also called Set Reset Flip Flop SR FF transforms a pulse into a continuous state The RS latch can be made up of two interconnected NAND gates In that case the Reset and Set inputs are active low The memory state corresponds to Reset Set 1 The combination Reset Set 0 should not be used as Q nQ 1 Furthermore the simultaneous change from Reset Set 0 to Reset Set 1 provokes what is called the metastable state that corresponds to a parasitic ring effect that may jeopardize the behavior of the whole circuit RS Latch NAND Fig 7 1 The truth table and schematic diagram of a RS latch made RSNor SCH FULL CUSTOM LAYOUT You may create the layout of RS latch manually The two NAND gates may share the VDD an
14. an XNOR gate and A gt B A lt B are operators obtained by using inverters and AND gates Comparator A B A gt B _A lt B__A B 0 0 0 0 0 1 0 1 0 0 0 0 0 Fig 6 8 The truth table and schematic diagram of the comparator COMP SCH Using DSCH2 the logic circuit of the comparator is designed and verified at logic level Then the conversion into Verilog is invoked File gt Make verilog File Microwind2 compiles the verilog text into layout The simulation of the comparator is given in Figure 6 9 The XNOR gate is located at the left side of the design The inverter and NOR gates are at the right side After the initialization A B rises to 1 The clocks A and B produce the combinations 00 01 10 and 11 Fig 6 9 Simulation of a comparator COMP MSK file 91 20 01 02 6 7 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics Arithmetic and logic Units ALU The digital function that implements the micro operations on the information stored in registers is commonly called an arithmetic logic unit ALU The ALU receives the information from the registers and performs a given operation as specified by the control A very simple ALU design is proposed to illustrate its principle The control unit is made up of a 4 1 multiplexor The operation part consists of four kinds of operations listed as follows and or addition and subtraction The and and or operation are realized by using the basic logic gates
15. l Sortie He 0 224nsi 0 228ns 224n8 0 224ns J 228ns 0 224ns 0 224ns i 0 228ns d a NE A 4 NA ae aie 4 386GHZ i i A l 0 0 0 2 0 4 0 6 0 8 1 0 1 2 14 1 6 1 8 ns Fig 2 5 Improvement in speed thanks to deep submicron technology HOW TO SIMULATE O Start Microwind2 By default the software is configured with 0 25um technology Click File gt Open Select INV3 Click Simulate gt Start Simulation The oscillation figure 2 5 appears Click Close Click File gt Select Foundry Click cmos08 rul Run again the simulation Observe the change of VDD and the slow down of the oscillating frequency 9 20 01 02 MICROWIND amp DSCH USER S MANUAL 2 Technology Scale Down 2 3 Increased Layers The table below lists a set of key parameters and their evolution with the technology Worth of interest is the increased number of metal interconnects the reduction of the power supply VDD and the reduction of the gate oxide down to atomic scale values Notice also the slow decrease of the threshold voltage of the MOS device and the increasing number of input output pads available on a single die Lithography Year Metal Oxide Threshold Input output Microwind2 rule layers a V a voltage V pads file 12m 1986 2 50 os 250 Cmosi2rall Omm 198 2 fso 2 o7 3s0 Cmos08rall Osum fi 3 h3 rm fos foo Cmon 025um 199 fo 25 6 Joss i000 Cmos025rul OI8um 1998 fo 20 s 0500 Cmo
16. l S Mp a loa 0 50 do Ve h TT eni ar ee a eh 0 ar e a 0 00 0 20 040 0 50 oag 100 12 o El El vitonotofiz0 gt Forvgiomoto i20 sapu fi ef LES Ad measure y OF E Draw a Ft fe 0pm L 0 4 20r lo leakage T times lt Pros Fig 3 13 Implementation of BSIM4 within Microwind2 The general equation of the threshold voltage is presented below vth VTHO KIN P Vbs D K2Vbs AVt c AVt yoo FAVE 51 21 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter where VTHO is the long channel threshold voltage at Vbs 0 Around 0 5V K1 is the first order body bias coefficient 0 5 V Ds is the surface potential Vbs is the bulk source voltage K2 is the second order body bias coefficient AVtsck is the short channel effect on Vt AVtuyp 1s the non uniform lateral doping effect and AVtpjp _ 1s the drain induced barrier lowering effect of short channel on Vt Concerning the formulations for mobility of channel carriers he generic parameter 1s UO the mobility of electrons and holes The effective mobility Uey1s reduced due to several effects the bulk polarization and the gate voltage The equation implemented in Microwind2 is the most recent mobility model proposed in BSIM4 reported in 3 xxx UO Nastere t 2 VTHO Vep a v TOXE Mor 1 UA UCV o Al where UA is the low field mobility in m V s Its default value is around 0 06 for n channel MOS and 0 025 for p channel MOS UA
17. 3 3 3 3 3 3 3 3 3 3 3 3 3 0 high speed MOS 1 2V in 0 12um low leakage MOS 1 2W in 0 2um high voltage MOS Up to 3 34 thin gate oxide 3nm thin gate oxide 3nm thick gate oxide Fnm Fig 3 17 High speed low leakage and high voltage MOS The high voltage MOS has a minimum length longer than for the other MOS The gate oxide is also thicker to handle high voltage operation 3 14 Temperature effects on the MOS The MOS device 1s sensitive to temperature Two main parameters are concerned the threshold voltage VTO and the transconductance coefficient KP that decrease with temperature increase The physical background is the degradation of mobility of electrons and holes when the temperature increase due to a higher atomic volume of the crystal underneath the gate and consequently less space for the current carriers The modeling of the temperature effect 1s as follows KP T KP To T To et VTO T VTO To 0 002 T To With To 300 K generally lds uA LSO r5 a C ee ee SNE cl EE en AAA HE E 2 pa A A A a A AAA A dE EA ET al ie lS ae A nt E AAA A a E AA E AA 0 EA E vb 0 00 bo O e D a O E EAN 0 00 0 50 1 00 1 50 2 01 25 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Fig 3 18 Effect of temperature on the MOS device characteristics To obtain this curve proceed as follows ME O Click the icon MOS characteristics 2 Select one MOS in the design or
18. 6 Arithmetics command File gt Save As Generate the Verilog text by using the command File gt Make Verilog File In Microwind2 click on the command Compile gt Compile Verilog File Select the text file fadd txt Click on Compile When the compiling is complete the resulting layout appears shown below The XOR gate is routed on the left and the AND gate is routed on the right Click on Simulate gt Start Simulation The timing diagrams appear Figure J A e Fig 6 5 Simulation of a full adder File FADD MSK 6 5 Four Bit Adder The four bit adder circuit includes adders in serial to perform the arithmetic addition The result of each stage propagates to the next one from the top to the bottom The circuit allows a four bit addition between two numbers A3 A2 A1 A0 and B3 B2 B1 B0 Insert the user defined Fadd sym symbol using the command Insert gt User Symbol In DSCH2 the A and B numbers are generated by keyboard symbols as reported below Also notice the hexadecimal display with a ground connected to the K input to activate the display A o huun CARRY EEH T Efa ELE mH SUMO Hee THe l E Br LI FullAdder Sm La Fig 6 6 Schematic diagram of the four bit adder ADD4 SCH 49 20 01 02 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics Figure 6 7 details the four bit adder layout based on the full custom cell design with the corresponding simulation In Microwind2 the command Edit gt
19. Chapter 8 analog cells are presented including voltage references current mirrors operational amplifiers and phase lock loops Chapter 9 concerns analog to digital and digital to analog converter principles The input output interfacing principles are illustrated in Chapter 10 The detailed explanation of the design rules is in Chapter 11 Electrical rules are described in chapter 12 The program operation and the details of all commands are given in the help files of the programs 7 20 01 02 MICROWIND amp DSCH USER S MANUAL 2 Technology Scale Down 2 Technology Scale Down The evolution of integrated circuit IC fabrication techniques is a unique fact in the history of modern industry The improvements in terms of speed density and cost have keep constant for more than 30 years By the end of 2000 System on Chips with about 100 000 000 transistors will be fabricated on a single piece of silicon no larger than 2x2 cm In this chapter we present some information illustrating the technology scale down 2 1 Evolution of Microprocessors and Memories Figure 2 1 describes the evolution of Intel microprocessors figure 2 2 describes the evolution of memory size during the last decades In figure 3 it is shown that industry has started to produce ICs in deep submicron technology starting 1995 Research has always kept around 5 years ahead mass production Nbr of device Memory size bi 1 GIGA 10 GIGA 100 MEG 1 GIGA 10 M
20. Click on the MOS characteristics icon The screen shown in Figure 2 6 appears It represents the Id Vd Static characteristics of the nMOS device 14 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter MOS Wise Ine Hor Wah 250 Lermgib 0 250 pm les vd ia ve io Togga we Yo gaase ve Klee wo pao et Lo nis LP jooo 4 1500 O fro a amwa no 10010 a gt us e ea THETA fo S ae LE att 150 T EE a DA ron eee por a p E osal Tema 27 00 S 0 00 100 2 00 nds Forvgtomoto scy Shep va ps OK le Dis Ue Fit Y 3 250um b 0 251 5 Fig 3 6 N Channel MOS characteristics is Add Measure T Hino 4c Pra The MOS size width and length of the channel situated at the intersection of the polysilicon gate and the diffusion has a strong influence on the value of the current In Figure 3 6 the MOS width is 3 25um and the length is 0 25um A high gate voltage Vg 2 5V corresponds to the highest Id Vd curve For Vg 0 no current flows A maximum current around 1 5mA is obtained for Vg 2 5V Vd 2 5V with Vs 0 0 The MOS parameters correspond to SPICE Level 3 A tutorial on MOS model parameters is proposed later in this chapter 3 6 Dynamic MOS behavior This paragraph concerns the dynamic simulation of the MOS to exhibit its switching properties The most convenient way to operate the MOS is to apply a clock to the gate another to the source and to observe the drain The summary of av
21. MICROWIND amp DSCH USER S MANUAL 1 Introduction Table of Contents T IMONE ON ese O 6 2 Fechnolooy Scale TDI OWI rnnr eNO ATE O RN EET 8 2 1 Evolution oF Microprocessors and Memories tia id dia 8 22 ETE QUEN CO IMPONE men OS 9 Zi nere asc dave o o ade 10 I DWC MOS MONO a Il Ded Ee WIOS as as Sl id ii 11 32 LOS gt IMulation OF the MO Sis si dis 12 Oho MO SA OU A A Ds 12 oe N ericalaspect ot Me MO ss a a Et lts 14 o ed MOS e A A A A 14 A e MO A e OE O PO E E 15 Dl ANOS SIM AU Orar i n 16 DO BS A A A A A A 17 uot TINE MOS Model las ll T E 18 310 TEMOS Mode Sora El ds 19 34L The BSIMIMOS Models ata 21 Ded Low leaks e MOS A a Aeaeauante feeb eineencnaeys 23 SS MORO lar MOS as it Mica 24 SL Tempere ciiects OM tne MO tds it ito os 25 So TEPMOS Trams stot ia 26 LO The Transmission Crate iss olarak A A A a A 28 d A RAS A E sites csusnceuen O O E ASER 30 A ENE BOICOT ita 30 42 THE CMOS TN VERTER ado 31 As A E IO DU A ET A AOO 32 4 4 MANUAL GA YOUT OF THE TINY ER TER cs E A Ed usted 33 AS 2Analos simulation ocithe UN VBR TER oserei ineeie er an E EE E EERE EN 34 Ao 2D Vow Ol Ne PrO ESS usa o A AN 35 AET DD VEW 0 i 101 POCO S aae a a a Ree a 35 AS O LATE INVER CER cid nts 36 D BASU GALON TS A T E sae es ema 37 Seb Phe Nand Gaee a a a A 37 A A A nee che ale ae a ated tc asta daca a een atts 39 I EROS A A A IR 39 e A IYD A 40 E E PE En In toh doe ia a euice anes acer aie 42 ys ay MUU E OM facets ey ciate att
22. can be implemented in a complex gate style You may find useful to invoke the one line compiler to create successively one inverter nd d and two complex gates which include the AND NOR cells using the syntax Q nQ nd h and nQ 0 d h Build the interconnections and run the Design Rule Checker Assign a clock to CLK and a clock to DATA An example of such an implementation can be found in the file DLatchLevel MSK Its layout an corresponding simulation are illustrated in figure 7 5 ge de ANA Hl Fa a psi ese ae A Sak Sao rE fic F A La AA a a ke i a A OO O E gt i E Th Th T y ari EEE icf EEIE J E oe CA EY qe AT Arg F E EZ En E DES E SS EN dd Sa ae ae E ETE E at eke E e FEEEEEI Ea dee Od A Qe F d sE gt dd E pe ye EF fe Es ty Es Ea ENEE TE ay FE ak E EE i j AE we FE ZE dE SE EEE EF EE O E F A HE sE da En 1 RekeRokeR ES drid Tr ee i AA ho a ep kerk Lise 3 rhe fE FeR El e o E E E ql Ea o pm HHHIHHH s eee eee ee i pea Tie SEHH e Bii E a FF A LE e A HIRE o Ona E TaT Gi Er FERH E Di bel TH mo AM Bat cD APRA OT ara E Gaus Ji a E al ER a CACAO F Frrr P a 00 10 20 30 40 50 60 70 80 90ns Fig 7 5 Implementation and simulation of the D Latch File DLatchLevel MSK Edit the schematic diagram called DLATCH SCH using DSCH2 Generate the Verilog text by using the command File gt Make Ve
23. capacitance between nets Extract net resistance Create SPICE netlist Figure 12 1 Extraction of the electrical circuit from layout The first step consists in cleaning the layout Mainly redundant boxes are removed overlapping boxes are transformed into non overlapping boxes In the case of complex circuits MICROWIND2 may skip this cleaning step as it required a significant amount of computational time Capacitance Each deposited layer is separated from the substrate by a S102 oxide and generated by a parasitic capacitor The unit is the aF um2 atto 10 18 Basically all layers generate parasitic capacitors Diffused layers generate junction capacitors N P P N The list of capacitance handled by MICROWIND2 is given below The name corresponds to the code name used in CMOS025 RUL CMOS 0 25um Surface capacitance refers to the body Vertical crosstalk capacitance refer to inter layer coupling capacitance while lateral crosstalk capacitance refer to adjacent interconnects 90 20 01 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules Inter layer Frindging Surface capacitance To body Adjacent layers SUBSTRATE BODY Figure 12 2 Capacitances 12 3 Surface Capacitance aF um aF um capacitance CpoBody Polysilicon to substrate n c prey Sowa FO e CM4Body Metaldonbody 30 CMSBody Metal5 on body CM6Body Metal6 on body 12 4 Interlayer Capacitance 12 5 Crosstalk Capacitance
24. click anywhere Select the curve Id Vg el Enable the screen memory mode by a click on this icon Tempo f100 00 2 Change the temperature The change in the slope 1s shown You may reduce the number of Id curves by putting a 0 0 in the field For Vb from 0 to In Microwind2 you can get access to temperature using the command Simulate gt Simulation Parameters The screen below appears The temperature is given in C 3 15 The PMOS Transistor The p channel transistor simulation features the same functions as the n channel device but with opposite voltage control of the gate For the nMOS the channel is created with a logic 1 on the gate For the pMOS the channel is created for a logic 0 on the gate Load the file pmos msk and click the icon MOS characteristics The p channel MOS simulation appears as shown in Figure 3 19 Note that the pMOS gives approximately half of the maximum current given by the nMOS with the same device size The highest current is obtained with the lowest possible gate voltage that is 0 VDrain f 1 i 1 F 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 n Fig 3 19 Layout and simulation of the p channel MOS pMOS MSK 26 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Fig 3 20 Summary of the performances of a pMOS device From the simulation of figure 3 19 we see that the pMOS device is able to pass well the logic level 1 But the logic level O is trans
25. cm3body 550 cm4body 550 cmSbody 450 cm6body 450 cgsn 500 Gate source capa of nMOS cgsp 500 550 Strong value due to cmelineic cm2lineic cm3lineic cm4lineic cm5lineic oO OO OO CO emolineic Vertical crosstalk cmepoly 60 cm2me 50 cm3m2 50 cm4m3 50 cm5m4 50 cmom5 50 Lateral Crosstalk cmextk 70 Lineic capacitance for crosstalk coupling in aF um cm2xtk 100 C is computed using Cx cmextk 1 spacing cm3xtk 100 cm4xtk 100 cm5xtk 100 cmoxtk 100 Junction capacitances cdnpwell 350 n psub cdpnwell 300 p nwell cnwell 250 nwell psub cpwell 100 pwell nsub cldn 100 Lineic capacitance N P aF pm cldp 100 Idem for P N MOS ek tit Eon MOS1 low leakage MOS2 high speed MOS3 high voltage Nmos Model 3 parameters NMOS l3vto 0 4 L310 0 06 LSCOX 8 9 l3vmax 170e3 l3gamma 0 4 13theta 0 3 l3kappa 0 06 13phi 0 2 20 01 02 DSCH amp MICROWIND USER S MANUAL 131d 8e 9 l3nss 0 06 high speed l3v2to 0 3 l3u2 0 06 13t20x 3e 9 high voltage 13v3to 0 7 l3u3 0 06 13t30x 7e 9 PMOS Model PMOS 13vto 0 4 l13u0 0 02 13tox 3e 9 l3vmax 120e3 l3gamma 0 4 l3theta 0 3 l3kappa 0 06 l3phi 0 2 131d 8e 9 l3nss 0 06 o high speed l3v2to 0 3 l3u2 0 02 13t20x 3e 9
26. in 3 3V I Os The high voltage MOS uses a gate width which is slightly larger than the one of the regular MOS As the high voltage MOS device is generally used in I O structures the MOS width is usually large even sometimes very large 100 500um 10 4 1 0 Pad We give here some details about input output pad structure The basic bonding pad size is 100x100um The pad consists of a sandwich of metal layers For advanced technologies all metal layers are stacked on the top of each other The passivation oxide has been removed from over the pad so that a gold connection can be fixed upon it 82 20 01 02 10 5 MICROWIND amp DSCH USER S MANUAL 10 Input Output Interfacing The input output pad contains one input stage with a polysilicon resistor and two protection diodes The output stage contains a chain of inverters The last stage is a 3 state inverter so that the buffer can be turned off Data Out eee rererererererererererecercrerece nece Fig lw wk ke f FERSRIRRRHINIHHENIHHHR e II t Input Resistor F Fig 10 4 Design of an input output pad PAD MSK ESD Protections The input pad includes some voltage boosting and under voltage protections linked with problems of electrostatic discharge ESD Such protections are required as the oxide of the gate connected to the input could be destroyed by over voltage One of the most simple ESD protection is made up of a set of tw
27. is fixed to half of the minimum available lithography of the technology The default technology is a CMOS 6 metal layers 0 25um technology consequently lambda is 0 125 um gt Microeind 2 exemple Be Hen Edi Sua Corods nakas Hei Marama do Hermed a 04 71 1005 Ha Ema ET O 25 en 6 12 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Fig 3 3 The MICROWIND2 window as it appears at the initialization stage The palette is located in the lower right corner of the screen A red color indicates the current layer Initially the selected layer in the palette is polysilicon By using the following procedure you can create a manual design of the n channel MOS O Fix the first corner of the box with the mouse While keeping the mouse button pressed move the mouse to the opposite corner of the box Release the button This creates a box in polysilicon layer as shown in Figure 3 4 The box width should not be inferior to 2 A which is the minimum width of the polysilicon box Change the current layer into N diffusion by a click on the palette of the Diffusion N button Make sure that the red layer is now the N Diffusion Draw a n diffusion box at the bottom of the drawing as in Figure 3 4 N diffusion boxes are represented in green The intersection between diffusion and polysilicon creates the channel of the nMOS device Fig 3 4 Creating the N channel MOS transistor 3 4 Vertical aspect of the MOS
28. that specific effort for supply routing is not required The input output nodes are routed on the top and the bottom of the active parts with a regular spacing to ease automatic channel routing between cells The AND gate As can be seen in the schematic diagram and in the compiled results the AND gate is the sum of a NAND2 gate and an inverter The layout ready to simulate can be found in the file AND2 MSK In CMOS the negative gates NAND NOR INV are faster and simpler than the non negative gates AND OR Buffer The cell delay observed in the figure 5 5 are significantly higher than for the NAND2 gate alone due to the inverter stage delay Fig 5 5 Layout and simulation of the AND gate The 3 Input OR Gate The truth table and the schematic diagram of the three input OR gate are shown in Figure 5 6 You may use the DSCH2 logic editor to design a schematic diagram based on the OR gate generate a Verilog description and compile the text file in Microwind2 As can be seen again in the final layout the OR gate is the sum of a NOR3 gate and an inverter 39 20 01 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates OR 3 Inputs A B C Or3 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 1 1 1 1 Fig 5 6 The truth table and symbol of the OR3 gate 5 lambda Fig 5 7 Layout and simulation of the OR3 gate OR3 MSK 5 4 The XOR Gate Et XOR 2 inputs A B OUT 00 0 01 l
29. the logic model of the MOS device 1s not working the same way as for the real MOS switch In the case of the logic implementation the logic signal flows only from the source to the drain This is not the case of the real switch where the signal can flow both ways Use the Verilog compiler to generate the edge trigged latch using the following text dreg txt or by creating a schematic diagram including the D register symbol in the symbol palette of DSCH2 As can be seen the register is built up from one single call to the primitive dreg For simulation 57 20 01 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories RESET is active on a level 1 RESET is activated twice at the beginning and later using a piece wise linear description included in the pulse property CLK is a clock with 10ns at O and 10ns at 1 D is the data chosen here not synchronized with CLK in order to observe various behaviors of the register To compile the DREG file use the command Compile W Compile Verilog Text The corresponding layout is reported below The piece wise linear data is transferred to the text rst automatically igre aud imeem E SERT WIE HERY a izi gt l col roe Tn Oe eed Le E EL EZ DELILE DEDEDE DLE LED EDEL DEED DEE PEE AZZZZZZZZHA Fig 7 7 Compiled version of the Edge trigged D Flip Flop The simulation of the edge trigged latch is reported in figure 7 8 The s
30. to charge and discharge that capacitance The corresponding file is FANOUT4 SCH 0 Smsidi LILI 0 0 5 0 10 0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 ns div liada d a CIk100M clock1 0 EREA SRR ERA TETEE eo E AN n fight ce ecc EEE ec E ao PERRA arae E comer ID Idd m L A A L J L J Laos darnos Los da A honnn peon gt dee cen 000708 FANOUTI SCH 3 00 L L Bestest TEEN ot Power dissip 0 018m w Sn en 0 0 5 0 100 150 200 20 300 30 400 450 hab a CIk100M clock1 Out light1 Out3 light2 out flight3 Out light4 FANOUT4 SCH Fig 4 5 Power consumption increase with the fanout Fanoutl SCH and Fanout4 SCH 32 20 01 02 4 4 MICROWIND amp DSCH USER S MANUAL 4 The Inverter In summary three factors contribute to the power consumption the load capacitance C the supply voltage VDD and the clock frequency f For a CMOS inverter this relation is represented by the equation below The equation remains valid for more complex gates although some extra considerations have to be taken into account Po ke VYDD E Where k technological factor close from 1 C Output load capacitance Farad VDD supply voltage V f Clock frequency Hz MANUAL LAYOUT OF THE INVERTER In this paragraph the procedure to create manually the layout of a CMOS inverter is described Click the icon MOS generator on the palette The following window a
31. 1 2 in 0 1 thin gate oxide 3nm thin gate oxide nm Fig 3 15 High speed and Low leakage MOS layout The only difference is the option layer configured for the low leakage option 3 13 High voltage MOS Integrated circuits with low voltage internal supply and high voltage I O interface are getting common in deep sub micron technology The internal logic of the integrated circuit operates at very low voltage Typically 1 0V in 0 12um while the I O devices operate in standard voltages 2 5 3 3 or 5V The input output structures work at high voltage thanks to specific MOS devices with thick oxide while the internal devices work at low voltage with optimum performances 3 3V 1 2V I Os at high voltage Core logic operating at low voltage Fig 3 16 Interfacing low voltage logic signals with high voltage I Os requires specific circuits operating in high voltage mode For I Os operating at high voltage specific MOS devices called High voltage MOS are used We cannot use high speed or low leakage devices as their oxide is too small A 2 5V voltage would damage the gate oxide of a high speed MOS in 0 12um technology The high voltage MOS is built using a thick oxide two to three times thicker than the low voltage MOS to handle high voltages as required by the I O interfaces 24 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 5 lambda 0 300pm j 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
32. 10 l 11 0 The truth table and the schematic diagram of the CMOS XOR gate are shown above There exist many possibilities for implementing the XOR function into CMOS The least efficient design but the most forward consists in building the XOR logic circuit from its Boolean equation 40 20 01 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates The proposed solution consists of a transmission gate implementation of the XOR operator The truth table of the XOR can be read as follow IF B 0 OUT A IF B 1 OUT Inv A The principle of the circuit presented below is to enable the A signal to flow to node N1 if B 1 and to enable the Inv A signal to flow to node N1 if B 0 The node OUT inverts N1 so that we can find the XOR operator Notice that the nMOS and pMOS devices situated in the middle of the gate serve as pass transistors ys mas O 25um 2 um prnos a 0 25uMm 2 um SOR amog o 2S5um b Sum amog o 25umt0 Sum 0 um 0 Suni Fig 5 8 The schematic diagram of the XOR gate xXORCmos SCH You may use DSCH2 to create the cell generate the Verilog description and compile the resulting text In Microwind2 the Verilog compiler is able to construct the XOR cell as reported in Figure 5 9 You may add a visible property to the intermediate node which serves as an input of the second inverter See how the signal called internal is altered by Vtn when the nMOS is ON and Vtp when the pMOS is ON Fortu
33. 13 The main drawback is the need for two control signals Enable and Enable thus an inverter 1s required Enable signalln signalOut signalln Signali Fig 5 13 The transmission gate used as a multiplexor 43 20 01 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates In DSCH2 a transmission gate symbol exists It includes the nMOS pMOS and inverter cells Concerning the layout the channel length is usually the minimum length available in the technology and the width is set large in order to reduce the parasitic on resistance of the gate 5 7 4to 1 Multiplexer The multiplexer is a very useful function and has a multitude of application The selection of a particular input line is controlled by a set of selection lines Normally there are 2 input lines and n selection lines whose bit combinations determine which input is selected Figure 5 14 shows the transmission gate implementation of the 4 to 1 multiplexer In the configuration S1 1 S2 0 the input C is connected to the output E gt O 51 Sl Mo Li e Fig 5 14 4 to I multiplexing based on transmission gates Mux4tol sch 5 8 Keyboard multiplexor Figure 5 15 gives an example of 2 multiplexed hexadecimal keyboards sharing the same hexadecimal display using transmission gates We use a clock to generate an alternative selection of the keyboard information Op O es Up Ode Fig 5 15 Keyboard multiplexing ba
34. EG 100 MEG 1 MEG 10 MEG 100 K 1 MEG 10K 100K 82 85 89 92 95 98 01 04 82 85 89 92 95 98 01 04 Year Year Fig 2 1 Evolution of microprocessors Fig 2 2 Evolution of memories Cnannel um 2 0 o Deep submicron y technology 1 0 Industry Research 0 1 82 85 89 92 95 98 01 04 Year Fig 2 3 Evolution of lithography 8 20 01 02 MICROWIND amp DSCH USER S MANUAL 2 Technology Scale Down 2 2 Frequency Improvements 0 5 um 0 25 um 0 12um MOS Devices 4995 1998 i 2001 Sayer 5 layers 7 layers _ mmea m JH dd frequency JA 120MHz 350MHz 800 MHz Fig 2 4 Reduced device features and increased interconnect layers Figure 2 4 illustrates the main improvements in terms of feature size reduction for MOS devices increased number of metal interconnects to link MOS together within the chip Consequently the clock frequency of the chip has never stopped increasing with an expected 800MHz in 2001 An illustration is given below Figure 5 with a ring oscillator made from 3 inverters simulated with MICROWIND2 using 0 8um and 0 25um technologies Although the supply voltage has been cut by half VDD is 5V in 0 8um 2 5 in 0 25um the ar in lane 1S close from a factor of five 0 8 um f i 7 N O 845ns 1 915g 2 67 1 153GHI l i if 1 093GHI i i l 0 0 02 0 4 0 6 08 10 12 14 16 18 ns 2 52 353 2 356 2 355 2 356 2 356 12 354 _ aie 2 356 _ r 2 355 2 355 0 25 um
35. EPI for height negative in good ground reference underneath the active respect to the origin area THEPI for thickness active areas THSTI for thickness layer THPASS for thickness Final oxide on the top of the passivation HENIT for height usually Si3N4 THNIT for thickness NISO Buried N layer to isolate the Pwell HENBURRIED for height underneath the nMOS devices to enable THNBURRIED for thickness forward bias and back bias 12 8 Dielectrics Some options are built in Microwind to enable specific features of ultra deep submicron technology Details are provided in the table below HVTOX Substrate Metal 4 LOWK HIGHK HIGHK HIGHK Metal 1 LOWK HIGHK Substrate Substrate Using LOWK HIGHK with Using Lkii L ij with non homogeneous oxide structure homogeneous oxide structure Fig 12 4 Illustration of the use of LOWK HIGHK dielectric constants left figure or detailed permittivity for each layer right figure 4 4 3 3 3 3 3 93 20 01 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules 12 9 Simulation Parameters The following list of parameters is used in Microwind2 to configure the simulation CODE DESCRIPTION TYPICAL VALUE Supply voltage of the chip High voltage supply DELTAT Simulator minimum time step to ensure 0 Se 12 s convergence You may increase this value to speed up the simulation but instability problems may rise TEMPERATURE _ Operating temperature of the chip
36. LE ll ie 2 ee i Ja esis a il as Flin amp L 21 15 at rarer a rere SER E mi TH El ri pista eae re a meee E E ae ho ae Hti E ETHE a a pie ne eat Segal HE ita Ee z He at a ier prt ace l dan Ba ils jki di llc Miles a Peat irae tt IE BHH E a tH F a E sl de pa E bi n F Ei Ili E Pie 7 An ERE idiei A ERS ERR E EHE aL IN ot a aoe T T bd 5 lll ee pe rE HES Brey eae ZEEE EERE E EH EI HH El H Bizi EHHH Ela Sef Fig 7 14 Duplicating the RAM Cell in X and Y 63 20 01 02 7 Latches and Memories MICROWIND amp DSCH USER S MANUAL 7 7 RAM Line decoder The line decoder is based on the following schematic diagram One line is asserted while all the are at zero In this circuit one line was picked out from a choice of four lines Using other lines AND gates would be an easy solution but in order to save the inverter we choose NOR gates with inverted inputs Fig 7 15 A line selection circuit L 0 0 9 1 ET I I I a ee is 5 00 o Line Adressi a E 2 Line_ Adress 4 L5 00 s 2 0 4 0 6 0 8 0 10 0 2420 14 0 16 0 18 0 0 0 Fig 7 16 A line selection layout and its corresponding simulation RamLineSelect MSK 20 01 02 64 7 8 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories The NOR gate height should be adjusted to that of the RAM cell height When making the final assembly between
37. RISETIME Typical rise and fall time of clocks 12 10 Models Level1 and Level3 for analog simulation Four types of MOS devices may be described as detailed in figure 12 4 Data from SIA 0 12um CMOS technology In the rule file the keyword MOS1 MOS2 MOS3 and MOS4 are used to declare the device names appearing in menus In 0 12um technology three types of MOS devices are declared as follows Also NMOS amp PMOS keywords are used to select n channel Mos or p channel Mos device parameters MOS MOS2 MOS3 E Speed T Leakage E voltage Vt nmos Vt pmos Keomo ho ho bo KP pmos MOS definition MOS1 low leakage MOS2 high speed MOS3 high voltage Figure 12 5 Description of MOS options in 0 12um technology cmos012 RUL The list of parameters for level 1 and level 3 is given below PARAMETER KEYWORD _ DEFINITION TYPICAL VALUE 0 25um NMOS pMOS vIO i3vto Threshold voltage Low field mobility 0 06 mV s 0 025 IV s TSpha Surface potential at strong 0 3V 0 3V inversion 94 20 01 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules rotad Lateral diffusion into 0 0lum 0 0lum channel GAMMA Bulk threshold parameter KAPPA Saturation field factor 0 01 V 0 01 V VMAX Maximum drift velocity 150Km s 100Km s THETA 13theta Mobility degradation 0 3 V 0 3 V factor Substhreshold factor 0 07 V 0 07 V Gate oxide thickness For MOS2 MOS3 and MOS4 only the threshold
38. Vk lt Vt a diode with an interesting high resistance when Vk gt Vt where Vt is the threshold voltage of the device The main application of this circuit is the design of a big resistance in a very small silicon area Source vk drain qate Anos Source Figure 8 1 MOS connected as a diode y ES Figure 8 2 Layout and simulation of the MOS connected as a diode O In the palette click the icon MOS generator Enter a large length and a small width For example enter W 0 5um L 5um This sizing corresponds to a long and narrow channel featuring a very high resistance channel with poor current performances 66 20 01 02 8 2 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells Add a poly metal contact and connect the gate to one diffusion Add a clock on that node Add a VSS property to the other diffusion Click Simulation on Layout In a small window the MOS characteristics are drawn with the functional point drawn as a color dot Figure 7 2 It can be seen that the I V characteristics correspond to a diode The resistance varies with Vk but can be estimated around 30KQ The resistance obtained using such a circuit can reach easily 100KQ in a very small silicon area The same resistance can be drawn in poly but would require a much larger area Voltage Reference The voltage reference is usually derived from a voltage divider made from resistance The main problem is that the value of the resi
39. W 0 1 0 l 0 0 l l 0 0 l 0 l 1 l Fig 6 3 The truth table and schematic diagram of a full adder FADD SCH 6 3 Full Adder Symbol in DSCH Schema jo Sydal D gt Eyrabal Popes Hama lisid sn G ariago P Demang onder af OK K Teal Bie Fig 6 4 Create a symbol from the schematic diagram Tide flaca Ss n L ach 20 In order to build hierarchical designs using the adder we detail the procedure to generate the symbol of the full adder from its schematic diagram In DSCH2 click the above icon the screen of figure 6 4 appears Simply click OK The symbol of the full adder is created with the name Fadd sym in the current directory Use the command Insert gt Symbol to include this symbol into a new circuit 47 20 01 02 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics 6 4 Full Adder Layout ER puma LE KE LE ZZZZZZZZ ZA AAA AAAADIAN Y AAA A a quin 7 ao ee ee pin AFEEF FERT EE Ka E EE I Geran UN Ce ng aan age 7 neg G4 3 ME CETHI AR W FER 5 ig ET EI sie a 4 PAS ae 5 Hae ia Te liati thy ae AB ES Er tana ERE aoe EEE SHE Le HHH z2 ES nZ EA EF E ao et laa ey ee fa ee ha La q taa ii ss a WH Fh i gi Hi a ge Tati eet Hae EEFE ee Tipi AM EA E A EL Aa E E a a MEL A l o E L I iti ji cae a FER el ao DE E PE gE EnF EEE E El Er PIII E rs PEN S A lt i ts ee co rik
40. ailable properties that can be added to the layout is reported below At IL Y VDD property VSS property Node visible Clock property Sinusoidal wave Pulse property O Apply a clock to the gate Click on the Clock icon and then click on the polysilicon gate The clock menu appears again Change the name into Vgate and click on OK to apply a clock with 2 1ns period 1ns at 0 50ps rise Ins at 1 SOps fall 15 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Add a Clock Label name Jet VDD vss Clock pulse Sinus variable Parameters Low level 4 0 00 High Level yy 2 50 Time lo Rise time Time high Fall time rs 1 00 0 05 foo fos PU Slower JW Faster SZ Invert UH a Assign JE Cancel M Visible in simulation Fig 3 7 The clock menu O Apply a clock to the drain Click on the Clock icon click on the left diffusion The Clock menu appears Change the name into Vdrain and click on OK A default clock with 4 2ns period is generated The Clock property is sent to the node and appears at the right hand side of the desired location with the name Vdrain O Watch the output Click on the Visible icon and then click on the right diffusion Click OK The Visible property is then sent to the node The associated text sl is in italic meaning that the waveform of this node will appear at the next simulation Always save BEFORE any simulat
41. ak to peak output 482mV peak to peak volt Figure 8 10 Single Stage amplifier with high gain 8 5 Simple Differential Amplifier The goal of the differential amplifier is to compare two analog signals and to amplify their difference The differential amplifier formulation is reported below Usually the gain K is high ranging from 10 to 1000 The consequence is that the differential amplifier output saturates very rapidly because of the supply voltage limits Vout K Vp Vm 70 20 01 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells Differential Amplifier pMOS current mirror nmos nmos nMOS differential pair Equivalent symbol vp Vout Ym Figure 8 11 Schematic diagram of the differential amplifier The differential amplifier layout is reported in figure 8 12 The differential pair 1s built from n channel MOS devices Their size must be identical and drawn with the same orientation to minimize the offset generated by transistor mismatch In the simulation it can be seen that a small voltage difference between V and V induces the saturation of the output either near VSS and VDD SS4current mirror N X gt BS een We PEE PEIE ak EE PEF PISA A Eto a E CGO OO GE IIA a aaa A AAA e E O A A A a iddmax 0 678mA a ml i i issMax 0 690mA 0 80 ae rd ee SSS SS A an ee I 1 i out 1 1 i i 1 il 1 00 ft iy High power i at consumption 0 40
42. amp DSCH USER S MANUAL 10 Input Output Interfacing Input Output Interfacing Create a Pad Ring had Click on the chip library icon and click on Pads Enable the pad ring option A pad ring with 3 pads in X and 3 pads in Y is generated by a click on Generate Pad In that case a set of pads is added to your circuit The VSS pad is situated at the bottom and the VDD pad at the top with the associated power rings VDD VSS Floor planning The supply network of a typical integrated circuit is shown in figure 10 1 Bars of metal wires cross the circuit to supply the active parts of the circuit The metal wires are designed very large to enable strong currents to flow within the supply interconnects Basic cells VDD Pad TH dws Fig 10 1 Supply of an integrated circuit 81 20 01 02 MICROWIND amp DSCH USER S MANUAL 10 Input Output Interfacing A sar i El A EE ii PETE I O at with its F f Hi mi dif ESD iio Hi pl i m a eo o E gE or boi aM See ee te VDD supply ring Fig 10 2 Supply network in a real case circuit 10 3 High Voltage MOS For interfacing with input output specific high voltage MOS are introduced These MOS devices are called high voltage MOS They use a thick gate oxide to handle the high voltage of the I Os An example of high voltage MOS device 1s reported below Normal MOS High Voltage MOS 1 8V 3 3V Fig 10 3 The High voltage MOS device is used
43. are derived from the model 1 and take into account a set of physical limitations in a semi empirical way CUT OFF MODE Ves lt 0 Ids 0 NORMAL MODE Vgs gt Von Ids Keff bal 1 KAPPA vds Vde Vgs vth ve LEFF 2 with von 1 2 vth vth VTO GAMMA PHI vb 4PHI vde min vds vdsat vdsat vc vsat 4 vc vsat vsat vgs vth 19 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter ve VMAX 0 06 LEFF L 2LD Repo XRP_____ 1 THETA ves vth SUB THRESHOLD MODE Ves lt Von Vds 1s replaced by von in the above equations Ids Ids von vds e aves atom nkT TEMPERATURE EFFECTS un un T 300 e gt up upo T 300 e gt vt vto 0 002 T 300 Mos MODEL 3 PARAMETERS PARAMETE DEFINITION TYPICAL VALUE 0 25um R p Theshold voltage Transconductance coefficient 3 ic PHI Surface potential at strong 0 3V ae 0 LD NSS LD Lateral diffusion into channel O Olum__ O 100Km s 0 3 V The curve shown in Figure 3 12 is used to fit VTO KP and GAMMA Act on VTO cursors in order to shift the curves right or left KP to adjust the slope and GAMMA to fit the spacing between curves l 10x10 um Beta 155 AE 123 10 AAS o VTO BLA me A yA a e ld a See yi 0 00 0 50 1 00 1 50 2 1 2i Fig 3 12 The Id Vg curves used to fit KP VTO and GAMMA Nb10x10 MES 20 20 01 02 3 11 MICROWIND amp DSCH USER S MANUAL 4 The Inverter
44. ation shown in the above picture You are back to the editor Click the above icon to get access to the chronograms of the simulation Double click on the INV symbol the symbol properties window is activated In this window appears the VERILOG description left side and the list of pins right side A set of drawing options is also reported in the same window Notice the gate delay 0 06ns in the default technology the fanout that represents the number of cells connected to the output pin 1 cell connected and the wire delay due to this cell connection An extra 0 1ns delay 30 20 01 02 4 2 MICROWIND amp DSCH USER S MANUAL 4 The Inverter THE CMOS INVERTER The CMOS inverter design is detailed in the figure below Here the p channel MOS and the n channel MOS transistors function as switches When the input signal is logic O Fig 4 2 left the nMOS is switched off while PMOS passes VDD through the output When the input signal is logic 1 Fig 4 3 right the pMOS is switched off while the nMOS passes VSS to the output ind Source WES Fig 4 3 The MOS Inverter File Cmoslnv sch The inverter consumes power during transitions due to two separate effects The first is short circuit power arising from momentary short circuit current that flow from VDD to VSS when the transistor functions in the incomplete on off state This state occurs briefly during transitions of the output either from 0 to 1 or from 1 to O
45. blocks the command Edit gt Move Area is very important This command helps to move a selected block with a lambda step RAM Column Selection The column selection circuit is based on the same principles as those of the line decoder The major modification is that the data flows both ways that is firstly from the cell to the read circuit Read cycle and secondly from the write circuit to the cell Write cycle Fig 7 17 proposes an architecture for this The n channel MOS device is used as a switch controlled by the column selection When the n channel MOS is on and Write is asserted the data issued from DatalIn is amplified by the buffer flows from the bottom to the top and reaches the memory If Write is off the 3 state inverter is in high impedance which allows one to read the information Circuit principles for one column selection Dataln is amplified validated and sent to vertical data bus TTT e e e e e e e e e e e e o e e o o e e e e e e e e e e e e o o o o g ColumnSelect n goo BF ta i Todata TonData ee ee ee en ee ae ee lt gt AAA Fig 7 17 Row selection and Read Write circuit RamColumn SCH 65 20 01 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells 8 Analog Cells 8 1 Diode connected MOS The schematic diagram of the diode connected MOS is proposed in figure 8 1 The question rises is this device a capacitance a diode or a resistance The answer is a capacitance for
46. chenbacher J A Connely Low Noise Electronic System Design Wiley amp sons 1993 ISBN 0 471 57742 1 12 A K Sharma Semiconductor Memories IEEE Press 1996 ISBN 0 7803 1000 4 102 20 01 02
47. d as nEnable is the opposite of Enable The operation of the transmission gate is illustrated in figure 3 24 A sinusoidal wave with a frequency of 2GHz is assigned to Dataln With a zero on Enable And a 1 on nEnable the switch is off and no signal is transferred When Enable is asserted the sinusoidal wave appears nearly identical to the output al a a ee A A EE SN 250 4 1 4 pt pg T re ee JN ae hy y A A A A A ah oo 05 10 165 20 25 Fig 3 24 Simulation of the transmission gate TGATE MSK 29 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 4 The Inverter 4 1 This chapter describes the CMOS inverter at logic level using the logic editor and simulator DSCH2 and at layout level using the tool MICROWIND2 The LOGIC Inverter In this section an inverter circuit 1s loaded and simulated O Click on the icon above to activate the Dsch2 software O Click File gt Open in the main menu Select INV SCH in the list In this circuit are on button situated on the left side of the design namely A an inverter and a led Click Simulate gt Start simulation in the main menu Fig 4 1 The schematic diagram including one single inverter Inverter SCH Now click inside the buttons situated on the left part of the diagram The result is displayed on the lamps The red value indicates logic 1 the black value means a logic 0 Click the button Stop simul
48. d VSS supply achieving continuous diffusions The internal routing may also save routing area leading to the layout shown in Figure 6 2 VERILOG COMPILING Use DSCH2 to create the schematic diagram of the RS latch Verify the circuit with buttons and lamps Save the design under the name RS sch using the command File gt Save As Generate the Verilog text by using the command File gt Make Verilog File In Microwind2 click on the command Compile gt Compile Verilog File gt Select the text file 53 20 01 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories RS txt Click on Compile When the compiling is complete the resulting layout appears as shown below The NOR implementation of the RS gate is completed module RSNor Reset Set Q nQ input Reset Set Suk put 0 100 nor norl Q nQ Reset nor Hor noraa endmodule With the Reset and Set signals behaving like clocks the memory effect is not easy to illustrate A much better approach consists in declaring pulse signals with an active pulse on RESET followed by an active pulse on SET Consequently you must change the CLOCK property into a PULSE property For NOR implementation the pulse is positive 1 Select the PULSE icon Click on the RESET node 2 Click the brush to clear the existing pulse properties of the pulse 3 Enter the desired sequence for example 01000 An click INSERT A piece wise linear sequence is generat
49. d oscillator In the simulation of figure 8 dependence with Vc is not linear 19 MICROWIND amp DSCH USER S MANUAL 9 Converters 9 Converters 9 1 Analog Digital Converter The analog digital converter converts an analog value Vin into a two bit digital value called A0 A1 The flash converter uses three converters and a coding logic to produce AO and Al Figure 9 1 A very complex logic circuit and 255 comparators would be used for an ADC eight bit flash The polysilicon has a high resistance 50 per square and can be used as a resistor network Left of Figure 9 2 which generates intermediate voltage references used by the voltage comparators located in the middle The resistance symbol is inserted in the layout to indicate to the simulator that an equivalent resistance must be taken into account for the analog simulation Open loop amplifiers are used as voltage comparators The comparisons address the decoding logic situated to the right and that provides correct AO and Al coding Analog Input Vin C Vinst25Y fo Vin gt 3 75 Poly resistor Fig 9 1 Node description and schematic diagram of the analog digital converter ADC MSK 76 20 01 02 MICROWIND amp DSCH USER S MANUAL 9 Converters Lal a p e o os J hal O da AI ARES RES EE eet diaz E E ER coat ES EF 230 ET q R E a E 3 EE E p to LE A y q oni ne ee dle 7 ne Rp im F so bed o ih UE de TER coe ce E at 7 aE E E FEl
50. ed in the table describing the 01000 waveform in an analog way 4 Repeat the same procedure to change the clock into a pulse for node SET This time the sequence must be 000100 to delay the pulse 5 Click on Simulate gt Start Simulation The timing diagrams of figure 7 2 appear Click on Close to return to the editor LLE oH i o z eae ee pe ee ee Fig 7 2 Layout of the RS latch made RSNor MSK In the simulation of Figure 7 3 a positive pulse on SET turns Q to a stable high state Notice that when SET goes to 0 Q remains at 1 which is called the memory state When a positive 54 20 01 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories pulse occurs on RESET Q goes low nQ goes high In this type of simulation the combination Reset Set 1 is not present 0 0 40 5 0 6 0 1 0 2 0 3 0 Fig 7 3 Simulation of the RSNOR latch RSNor MSK 7 2 D Latch The truth table and schematic diagram of the static D latch also called Static D Flip Flop are shown in Figure 7 4 The data input D is transferred to the output 1f the clock input is at level 1 When the clock returns to level O the latch keeps its last value D Latch NOR D Clock Q nQ 0 l 0 l Fig 7 4 The truth table and schematic diagram of a D Latch File DLATCH SCH 595 20 01 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories MANUAL DESIGN Note that the NOR2 AND combination
51. ent 30014 A V 120uA V HI L P Surface potential at strong 0 3V 0 3V inversion Bulk threshold parameter MOS channel width 0 5 20um 0 5 40um L MOS channel length 0 25um 0 25um 20 01 02 3 10 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Let us compare the simulation and the measurement for a 10x10um device O Click Simulate gt Mos characteristics Or the icon Click Add Measure Select the data file Nb10x0 25 MES The N means an n channel MOS device The b corresponds to a chip called BETA fabricated in 0 25um technology The values 10x0 25 means W 10um L 0 25um O Select Level 1 in the parameter list to compare LEVEL1 simulated characteristics with the measurements ASMA 11 0 0004m L 0 250um simul Model 1 predicts 25mA maximum 251 2 008 100 25 um Beta 200 1 50 LN R HEEE SS The measured A maximum current is Nt 0 00 a a Hi a vos Fig 3 11 The model 1 predict a current 4 times higher than the measurement When dealing with sub micron technology the model 1 is more than 4 times too optimistic regarding current prediction compared to real case measurements as shown above for a 10x0 25um n channel MOS The MOS Model 3 For the evaluation of the current Ids as a function of Vd Vg and Vs between Drain and Source we commonly use the following equations close from the SPICE model 3 formulations The formulations
52. er Logic Simulation of the MOS At logic level the MOS is considered as a simple switch Moreover the logic switch is unidirectional meaning that the logic signal always flows from the source to the drain This major restriction has no physical background In reality the current may flow both ways The reason why the logic MOS device enables the signal to propagate only from source to drain is purely a software implementation problem In the logic simulator of DSCH2 an arrow indicates whether or not the current flows and its direction Figure 3 2 When the device is OFF the drain keeps its last logic value thus acting as an elementary memory Notice that you cannot pass any logic information from the drain to the source Such a circuit would fail Gate gate The arrow indicates that l the channel is ON l nmos Bh Ee source drain nMiOS_Out 1 l l l 1 i source drain pMOS Out E Data goes to pMos_out keeps its previous value gate Fig 3 2 the logic simulation of the MOS device MosExplain SCH MOS layout We use MICROWIND2 to draw the MOS layout and simulate its behavior Go to the directory in which the software has been copied By default MICROWIND2 Double click on the MicroWind2 icon The MICROWIND2 display window includes four main windows the main menu the layout display window the icon menu and the layer palette The layout window features a grid scaled in lambda A units The lambda unit
53. erify the circuit with buttons and lamps Save the design under the name hadd sch using the command File gt Save As Generate the Verilog text by using the command File gt Make Verilog File In Microwind2 click on the command Compile gt Compile Verilog File Select the text file hadd txt module Hadd B A sum carry Liou BA OULPUC SUM Carry Or xOrl Ssum B A and andl carry AB endmodule Click on Compile When the compiling is complete the resulting layout appears shown below The XOR gate is routed on the left and the AND gate is routed on the right Now click on Simulate gt Start Simulation The timing diagrams of figure 6 2 appear and you should verify the truth table of the half adder Click on Close to return to the editor Fig 6 2 Compiling and simulation of the half adder gate Hadd MSK Full Adder Gate The truth table and schematic diagram for the full adder are shown in Figure 6 3 The SUM is made with two XOR gates and the CARRY is a combination of NAND gates as shown below The most straightforward implementation of the CARRY cell is AB BC AC The weakness of such a circuit is the use of positive logic gates leading to multiple stages A more efficient circuit consists in the same function but with inverting gates 46 20 01 02 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics FULL ADDER B SUM CARRY 0 A 0 0 0 0 l l l l O DOD m e m O O FPF Oo Or Onm O
54. etal 5 rag 8 width rd02 8 spacing x yie 5 re01 5 Via width re02 5 Spacing re04 2 border of metalS amp metalo6 metal 6 rd0l 8 width rd02 15 spacing Pad rules rp01 800 Pad width rp02 800 Pad spacing rp03 40 Border of Vias rp04 40 Border of metals rp05 200 to unrelated active areas Thickness of conductors for process aspect 20 01 02 DSCH amp MICROWIND USER S MANUAL All in pm P epitaxial thepi 1 0 Keep 2 0 Shallow tretch isolation thsti 0 8 hesti 048 POLY thpoly 0 20 hepoly 0 01 Poly2 thp2 0 2 hep2 0 22 Diffusions thdn 0 4 thdp 0 4 thnw 1 0 Metallisation thme 0 heme thm2 hem2 thm3 hem3 thm4 hem4 thms hem5 thm6 hemo thpass hepass thnit 0 6 henit 8 4 al Odd OUO gt OwWON op JO ann ABPNA N ON ON OI LD oo Ui Resistances Copper Unit is ohm squarfe repo 4 rep2 4 reme 0 06 rem2 0 06 rem3 0 06 rem4 0 06 rem 0 05 remo 0 05 x Resistances vias unit is ohm via reco 20 revi 2 rev2 2 rev3 2 rev4 1 rev5 1 Parasitic capacitances cpoOxyde 4600 Surface capacitance Poly Thin oxyde aF ym2 99 13 Design Rules File for 0 12um cpobody 400 No lineic Capa cp2body 400 cmebody upper and lower capa emZ body 550 to metal grid i e 2 Cg
55. formed into a positive voltage equal to the threshold voltage of the MOS device The summary of the p channel MOS performances is reported in figure 3 20 27 20 01 02 3 16 MICROWIND amp DSCH USER S MANUAL 4 The Inverter The Transmission Gate Both NMOS devices and PMOS devices exhibit poor performances when transmitting one particular logic information The nMOS degrades the logic level 1 the pMOS the logic level 0 Thus a perfect pass gate can be constructed from the combination of nMOS and pMOS devices leading to improved performances Enable signalln signalOut Signalut Fig 3 21 The transmission gate The transmission gate let a signal flow if Enable is asserted To pass logic signals well both a n channel device and a p channel device are used as shown in figure 3 21 The main drawback is the need for two control signals Enable and Enable thus an inverter is usually required en Good 1 1 en me Transmission gate 0 0 0 Good 0 1 A Fig 3 22 The transmission gate used to pass logic signals escrros Mercere 2 tettetett TETTEI TE RERET 224 taQu 1 h eo Fig 3 23 Layout of the transmission gate IGATE MSK 28 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter The layout of the transmission gate is reported in figure 3 23 The n channel MOS is situated on the bottom the p channel MOS on the top Notice that the gate controls are not connecte
56. i gt Click on this icon to access process simulation Command Simulate gt Process section in 2D The cross section is given by a click of the mouse at the first point and the release of the mouse at the second point 13 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Interlayer oxide Field oxide Ny Lateral drain diffusion Source Thin gate oxide Fig 3 5 The cross section of the nMOS devices In the example of Figure 3 5 three nodes appear in the cross section of the n channel MOS device the gate red the left diffusion called source green and the right diffusion called drain green over a substrate gray A thin oxide called the gate oxide isolates the gate Various steps of oxidation have lead to stacked oxides on the top of the gate The physical properties of the source and of the drain are exactly the same Theoretically the source 1s the origin of channel impurities In the case of this nMOS device the channel impurities are the electrons Therefore the source is the diffusion area with the lowest voltage The polysilicon gate floats over the channel and splits the diffusion into 2 zones the source and the drain The gate controls the current flow from the drain to the source both ways A high voltage on the gate attracts electrons below the gate creates an electron channel and enables current to flow A low voltage disables the channel 3 5 Static Mos Characteristics IE
57. ie r403 Extra diffusion over contact 2 A MA C r404 Extra poly over contact 2 4 r405 Extra metal over contact 2 A r406 Distance between contact and poly gate 3 A r405 gt e 7 y ti ae diffusio metal gate 86 20 01 02 MICROWIND amp DSCH USER S MANUAL 11 9 Metal amp Via Design Rules r501 Metal width 4 2 r502 Between two metals 4 r510 Minimum surface 32 7 1601 Via width 2 A 1602 Between two Via 5 A r603 Between Via and contact 0 r604 Extra metal over via 2 r605 Extra metal2 over via 2 When r603 0 stacked via over contact is allowed 11 10 Metal2 amp Via2 Design Rules r701 Metal width 4 r702 Between two metal2 4 r710 Minimum surface 32 7 r801 Via2 width 2 r802 Between two Via2 5 r804 Extra metal2 over via2 2 r805 Extra metal3 over via2 2 11 11 Metal3 amp Via3 Design Rules 1901 Metal3 width 4 A 1902 Between two metal3 4 1910 Minimum surface 32 7 87 11 Design Rules r501 gt metal r502 metal r604 ZA r602 via Stacked via over gt lt contact r601 when r603 is 0 r603 contact r804 A r802 F via2 r901 metal 3 20 01 02 MICROWIND amp DSCH USER S MANUAL 11 Design Rules ra01 Via3 width 2 A ra04 ra02 Between two Via3 5 A ip T ra04 Extra metal3 over via3 2 A Ss ra05 Extra metal4 over via3 2 S via3 Meal raOl 11 12 Metal4 8 Via4 Design Rules rb01 Meta
58. iew of the Process The Process Simulator shows the vertical aspect of the layout as when fabrication has been completed This feature is a significant aid to understand the fabrication principles A click of the mouse at the first point and the release of the mouse at the second point give the cross section Polysilicon Sl Thick oxide a oxides S102 Drain N Source N diffusion diffusion Fig 4 9 The 2D process section of the Inverter circuit near the nMOS device 3D View of the Process AS PAMELA Click Simulate gt Process steps in 3D or the icon above The simulation of the CMOS fabrication process is performed step by step On figure 4 10 the picture represents the nMOS device pMOS device common polysilicon gate and contacts together with the metal layers stacked on the top of the active devices Fig 4 10 The step by step fabrication of the Inverter circuit 35 20 01 02 4 8 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 3 STATE INVERTER Until now all the symbols produced the value logic 0 and logic 1 However if two outputs are connected together as the left circuit shown below it will provoke a circuit error In order to avoid such conflicts specific symbols are used featuring the possibility to remain in a high impedance state The 3 state symbol used below is Bufif and it consists of the logic buffer and an enable control There al
59. ignals Q and nQ always act in opposite When RESET is asserted the output Q is 0 nQ is 1 When RESET is not active Q takes the value of D at a fall edge of the clock For all other cases Q and nQ remain in memory state The latch is thus sensitive to the fall edge of the clock 58 20 01 02 7 Latches and Memories MICROWIND amp DSCH USER S MANUAL 0 17 r cc OO sss anes Fig 7 8 Simulation of the DREG cell DREG MSK 20 01 02 59 7 4 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories Counter The one bit counter is able to produce a signal featuring half the frequency of a clock The most simple implementation consists of a D flip flop where the output nQ is connected to D as shown in figure 7 9 In the logic simulation shown in figure 7 9 the clock Clock1 changes the state of Clock_Div_2 at each fall edge The RESET is active high and stuck the output to 0 Clock_Div_2 LN clock Clock1 Fig 7 9 Schematic diagram of the 2 bit counter DivFreg MSK EV ZZZZZZZZZZZZA i eee E Bpi i e le halal FIFE Hi Vi ali SRI a la il fork A a PPP PPLE LL LLL LARRY ZZZZZERZZZZ ZAR LLL ELLE LLL ZE RE ZZZ ER ZZZ AN A fy 4 Fag ZZZZIZZZZZZZIZIZIZZTZIZIZIZITTA ABV OZ ZZ LLL LLL LLL 2 ZZZARZZ ZAS Ea pa a a Clock 0 701ns 0 701ns 1 0 6995 0 700ns 0 700n 4 428GHZ 1428GHZ 1431GHZ 1 428GHZ 1 4286 Fig 7 10 Layout and analog simulation of the divider by two
60. ion The analog simulation algorithm may cause run time errors leading to a loss of layout information Click on File gt Save as A new window appears into which you enter the design name Type for example myMos Then click on Save The design is saved under that filename 3 Analog Simulation Click on Simulate gt Start Simulation The timing diagrams of the nMOS device appear as shown in Figure 3 8 16 20 01 02 3 8 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Scan of C imasna lanun ma il A AE iran 0 00 zan Pla Lt ae Mir bio A Free re Wgaba 4 4 a 1 z1 1000 jips 1070ne 1 00 if a _ ai ig RI BO zi E 0 ne A Wicd Laa ii Urra i cagas ard cuna rs olga ra Olor y Fig 3 8 Analog simulation of the MOS device When the gate is at zero no channel exists so the node sl is disconnected from the drain When the gate is on the source copies the drain It can be observed that the nMOS device drives well at zero but poorly at the high voltage The highest value of s1 is around 2 0V that is VDD minus the threshold voltage This means that the n channel MOS device do not drives well logic signal 1 as summarized in figure 3 9 Click on More in order to perform more simulations Click on Close to return to the editor e Y en ZN o A Goao 1 A A Pori VDD Vt Fig 3 9 The nMOS device behavior summary Layout co
61. is the first order mobility degradation coefficient in m V Its default value is around 10 UC is the body effect coefficient of mobility degradation in m V Its default value is 0 045x10 VFB is the flat band voltage in V TOXE is the oxide thickness in m A typical value for TOXE in 0 12um is 3nm 3 10m EU is a coefficient equal to 1 67 for n channel MOS and 1 0 for p channel MOS The current Ids is computed using one single equation as described below Weff Ids0 V Leff Help TOXE este ApuikY dseff V aseff 2V stef 4 vt V 1 dseff d sat Leff Parameter Description NMOS value NMOS value in in 0 12um 0 12um O 03Y_ o3w S Long channel threshold voltage at Vbs OV 0 3V 0 3V VFB Flat bandvoltage OD DVTO First coefficient of short channel effect on threshold 2 2 22 voltage 1 DVT1 Second coefficient of short channel effect on Vth 0 53 0 53 ETAO Drain induced barrier lowering coefficient 0 08 NFACTOR Sub threshold turn on swing factor Controls the exponential increase of current with Vgs Low field mobility 0 060 m2 Vs 0 025 m2 Vs UA Coefficient of first order mobility degradation due to 11 0e 15 m V 11 0e 15 m V vertical field Coefficient of mobility degradation due to body bias 0 04650e 15 0 04650e 15 V 1 effect v 1 VSAT 8 0e4 m s 8 004 m s 1 22 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter WINT Channel width offse
62. l4 width 4 rb02 Between two metal4 4 A rb10 Minimum surface 32 7 rc01 Via4 width 2 rc02 Between two Via4 5 rc04 Extra metal4 over via2 3 A rc05 Extra metal5 over via2 3 11 13 Metal5 amp Via5 Design Rules rd01 Metal5 width 8 rd02 Between two metal5 8 rd10 Minimum surface 100 X re01 Via5 width 4 re02 Between two Via5 6 re04 Extra metal5 over via5 3 re05 Extra metal6 over via5 3 M etal 5 6 11 14 Metal6 Design Rules rf0l Metal6 width 8 A rf02 Between two metal6 15 ase eta rf10 Minimum surface 300 24 de 88 20 01 02 MICROWIND amp DSCH USER S MANUAL 11 Design Rules 11 15 Pad Design Rules rp01 Pad width 100 um rp02 Between two pads 100 um rp03 Opening in passivation v s via Sum E rp04 Opening in passivation v s metals rp05 Sum Between pad and unrelated active rp01 area 20 um 89 20 01 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules 12 Electrical Rules 12 1 12 2 Electrical Circuit Extraction MICROWIND2 includes a built in extractor from layout to electrical circuit Worth of interest are the MOS devices capacitance and resistance The flow is described in figure 12 1 Layout Skip in case of big circuits Clean layout P ne Extract MOS width Fatra devices Eo Extract MOS length Extract MOS option Eae e i Extract all electrical nets ER gt Extract net capacitance Extract coupling
63. le file cmos018 RUL C microwind2 Microwind2 exe test cmos018 rul Nwell Design Rules rl101 Minimum well size 12 r102 Between wells 12 r110 Minimum surface 144 24 p substrate 84 20 01 02 MICROWIND amp DSCH USER S MANUAL 11 Design Rules 11 4 Diffusion Design Rules 1201 Minimum N and P diffusion width 4 A ies polarization r205 1202 Between two P and N diffusions 4 1203 Extra nwell after P diffusion 6 A 1204 Between N diffusion and nwell 6 A 1205 Border of well after N polarization 2 A 1206 Distance between Nwell and P polarization 6 1210 Minimum surface 24 27 P polarization 11 5 Polysilicon Design Rules 1301 Polysilicon width 2 1302 Polysilicon gate on diffusion 2 A 1303 Polvysilicon gate on diffusion for high voltage MOS 4 A r304 Between two polysilicon boxes 3 A 1305 Polysilicon vs other diffusion 2 1306 Diffusion after polysilicon 4 A 1307 Extra gate after polysilicium 3 A 1310 Minimum surface 8 1 r301 H igh voltage MOS 85 20 01 02 MICROWIND amp DSCH USER S MANUAL 11 Design Rules 11 6 2 Polysilicon Design Rules 1311 Polysilicon2 width 2 A r311 1312 Polysilicon2 gate on diffusion 2 A Poly2 r312 11 7 Option Design Rules rOpt Border of option layer over diff N and diff P 11 8 Contact Design Rules r401 Contact width 2 A a r402 Between two contacts 5
64. log simulation ooccocccocncocnconncnnnoncnonnnncnoncnoncnoncnonnnnnnnncnnncnonnnonnnos 94 12 11 BSIM4 Model for analog simulation 0 0 0 0 cece ceccc ence eeeceeeaeee ence ence eee eeeeeeeae eee eeeeeeeeeeeeeseeeaaeeaeeeeeeees 96 2 12 TECA DS CZ acs a E 97 13 Design Rule File for O12 UM lt A ASAS 98 14 Referentes oo 101 5 20 01 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction 1 Introduction The present manual introduces the design and simulation of CMOS integrated circuits in an attractive way thanks to user friendly PC tools Dsch2 and Microwind2 About Dsch2 EMALE Ee Eb piai vee Grados Hep e ws aa a ara E a La 3 oe Av 41 al wa de ee Pal par eE E Sun i l a TA piss do a E LA LI A edd Car mols EJ aie 1 A a feji Lary a ET E z idi wa fedd a e a HE CF FLET el Rated Peres T Arg state _ y P DE Kasboard Hi aj 42 About Microwind2 A jpn ma er h Bie Yes Edd giis Dok graai Hef ED roer helera ta w pE oe G T PMT l E ae Palija CA ATEN AE i T The DSCH2 program is a logic editor and simulator DSCH2 is used to validate the architecture of the logic circuit before the microelectronics design is started DSCH2 provides a user friendly environment for hierarchical logic design and simulation with delay analysis which allows the design and validation of complex logic structures A key innova
65. nal sketch of the fabrication are also described The MOS as a switch The MOS transistor is basically a switch When used in logic cell design 1t can be on or off When on a current can flow between drain and source When off no current flow between drain and source The MOS is turned on or off depending on the gate voltage In CMOS technology both n channel or nMOS and p channel MOS or pMOS devices exist The nMOS and pMOS symbols are reported below The n channel MOS is built using polysilicon as the gate material and N diffusion to build the source and drain The p channel MOS is built using polysilicon as the gate material and P diffusion to build the source and drain The symbols for the ground voltage source 0 or VSS and the supply 1 or VDD are also reported in figure 3 1 drain source gate gate nrpos pros source drain n channel MOS p channel MOS Ground for 55 supply for DD 0 1 nMOS VV gt 0 1 pMOS Y Y Fig 3 1 the MOS symbol and switch The n channel MOS device requires a logic value 1 or a supply VDD to be on In contrary the p channel MOS device requires a logic value O to be on When the MSO device 1s on the link between the source and drain is equivalent to a resistance The order of range of this on resistance is 100Q 5KQ The off resistance 1s considered infinite at first order as its value is several MQ 11 20 01 02 3 2 3 3 MICROWIND amp DSCH USER S MANUAL 4 The Invert
66. nately the inverter regenerates the signal Fig 5 9 Layout and simulation of the XOR gate XOR MSK 41 20 01 02 5 5 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates Complex Gates The complex gate design technique applies for any combination of operators AND and OR The technique produces compact cells with higher performances in terms of spacing and speed than conventional logic circuits To illustrate the concept of complex gates let us take the example of the following Boolean equation F A B C The logic circuit corresponding to this equation is reported below The circuit is built using a 2 input NOR and a 2 input AND cell that is 10 transistors and three delay stages F AHB 10 transistors Fig 5 10 The conventional schematic diagram of the function F A B C A much more compact exists in this case Figure 5 11 consisting in the following steps 1 For the nMOS network translate the AND operator into nMOS in series and the OR operator in nMOS in parallel 2 For the pMOS network translate the AND operator into pMOS in parallel and the OR operator in pMOS in series 3 If the function is non inverting as for F A B C an inverter is mandatory pmos 0 25um 2 A pmos 0 25um 2 Oum pinos a 2Ssum 2 Cum a 7 F nmo Amos 0 2Sum O TS c 0 2S5um 0 Sum nmozs 0 2S5um 0 Sum F i 4 8 0 6 transistor
67. ned meaning high amplifier gains Vds for Source pMOS Load resistance sinus Out bl sinus In nan Daly Sinus In 5 sinus Out Vds for nMOS a b Figure 8 7 Single stage amplifier with passive resistance a and active resistance b Single stage amplifier Active load pMOS Input MOS Figure 8 8 Single Stage amplifier layout AmpliSingle MSK 69 20 01 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells In the simulation window click Voltage vs voltage and More to compute the static response of the amplifier Figure 8 9 The range of voltage input that exhibits a constant gain appears clearly For Vps higher than 0 6V and lower than 0 8V the output gain is around 5 Therefore an optimum offset value is 0 7V Change the parameter Offset of the input sinusoidal wave to place the input voltage in the correct polarization a a Ta ae ar CS rie es Mee CUM ODIN DQO US O A I I I sinus qu offset 0 3 Ee ej Linear behavior 1 50 ponini es ee E T ssp A A E i sarcs L Eo i i l A Offset 0 IN A ee IE Valid fap 3 e A o voltage range i enan ni i T Sinus 000 900 BD 80 0 LL aT 2 20 Figure 8 9 Single Stage amplifier static response We change the sinusoidal input offset and start again the simulation A gain of 5 is observed as predicted from the static simulation when the offset is 0 8V input 100mV pe
68. nput Output INTACTAS SS SS ele E NN l 10 1 Greaca Pad RINS cesi n 81 10 2 MDDIV SS Poo PATINANDO 81 10S M h Voltase MOS 0 A ia ia 82 DA MOP e aaa 82 MI A teas 83 El lt Deston Rules iodo iria 84 Mets Selecta Desen RUC E ens ea E a E 84 11 2 Start Microwind with a specific design Rule File ooocooccoocncccnoccnocnnncnnncnoncnoncnonnnonnnncnoncnonnnonanos 84 LTS AN WelDest oni Wes ia c n 84 114 Diffusion Desin RUES air A Sioadad teed eniwaecan a deena Raabe deve on ew meeaaiedeienrebede 85 15 Polysiicon Weston Rules iS rac vedas ieee esa ti 85 11 6 2 Polysilicon Design Rules ui 86 LES Option IDES On Rules unit taa 86 ES Contact Destilados ciada 86 ile Metal Via Des On RUS etc ii lcd 87 IEO Metal2us Va Deston Roles a uate alae uaa 87 EEL Metals Y tas Deston Roles i tee a ns lad ants acid a 87 HI Meane Viat DESORDEN A AA EIA nance 88 LAS MetalSvez Vian DES RUNES ceci 88 4 20 01 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction EA Metal Deston les ooo obre scale E T E T 88 E Jace Sto AMES coto E E ues cats 89 12 Electrical RUES eses 90 2 Bl ctrical t Tont Ex aC WOM ar 90 1212 Capacitan o ao o ita 90 2 5 S rece Capac INCE ea a 91 124 Inca Capacitan Cites aes eset da 91 125 Crosstalk CapaCian Ce A A AAA OAE EA 91 O RE A ROO 92 AF Vertical sASpect Ol the Technolo oy erien eE A EDE EEN cubetas 92 1240 We EO teta 93 12 20 Station AU AIC US aia 94 12 10 Models Levell and Level3 for ana
69. nsiderations The safest way to create a MOS device is to use the MOS generator In the palette click the MOS generator icon A window appears as reported below The programmable parameters are the MOS width length the number of gates in parallel and the type of device n channel or p channel By default metal interconnects and contacts are added to the drain and source of the MOS You may add a supplementary metal2 interconnect on the top of metal 1 for drain and source 17 20 01 02 3 9 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Lap GBe oralos Palette Pads inductor Contacts aus ace Path Logo Access to MOS NJ Ka m El Moe Parameters enerator a manos 6 150 rn if L a Lenpihwoe 0 260 um AULA bbr of Gates ij Add melal odin and sowie THE _J E PE hana pEhannal ae Generate Darica JE canal Fig 3 10 Analog simulation of the MOS device The MOS Model 1 For the evaluation of the current Ids between the drain and the source as a function of Vd Vg and Vs you may use the old but nevertheless simple MODEL 1 described below Mone CUT OFF W Vds2 LINEAR Vds lt V gs Ids KP Vgs Vt Vds gt Vt SATURAT Vds gt Vgs Ids KP 2 Ves Wt 2 ED Vt With vt VTO GAMMA PHI vb PHI MOS MODEL 1 PARAMETERS PARAMETE DEFINITION TYPICAL VALUE 0 25um R NMOS pMOS Theshold voltage Transconductance coeffici
70. o draw the NAND gate manually as for the inverter gate An alternative solution is to compile directly the NAND gate into layout with Microwind2 In this case complete the following procedure lt gt CMOS Cell Compiler Enter equation In Microwind2 click on Compile gt Compile One Line Select the line corresponding to the 2 input NAND description as shown above The input and output names E Compile HE Show aig JE Cancel can be by the user modified 4 lambda ere Click Compile The result is reported above a fe i z zA The compiler has fixed the position of VDD power supply B i a and the ground VSS The texts A B and S have also been a te a i fixed to the layout Default clocks are assigned to inputs A ae dal OOO and B FA Pe ee Fig 5 3 A NAND cell created by the CMOS compiler The 2D process viewer is a useful tool to display the two nMOS in series and the two pMOS in parallel Select the corresponding icon and draw an horizontal line in the layout in the middle of the nMOS channels The figure below appears In fig 5 4 the output is connected to the VSS supply only if A 1 and B 1 Fig 5 4 The nMOS devices in serial in the NAND gate 38 20 01 02 9 2 9 3 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates The cell architecture has been optimized for easy supply and input output routing The supply bars have the property to connect naturally to the neighboring cells so
71. o diodes and a resistance Fig 10 5 One diode handles the negative voltage flowing inside the circuit N P substrate the other diode P N well handles the positive voltage ESD protection Resistance To internal logic Fig 10 5 Diodes for electrostatic discharge protection 83 20 01 02 11 11 1 11 2 11 3 MICROWIND amp DSCH USER S MANUAL 11 Design Rules Design Rules Select a Design Rule File The software can handle various technologies The process parameters are stored in files with the appendix RUL The default technology corresponds to a generic 6 metal 0 25um CMOS process The default file is CMOS025 RUL To select a new foundry click on File gt Select Foundry and choose the appropriate technology in the list To set a specific foundry as the default foundry click Files gt Properties Set as Default Technology Start Microwind with a specific design Rule File To start Microwind with a specific design rule file click with the right button of the mouse on the Microwind icon select the Properties item then the target The default target may be C microwind2 Microwind2 exe The command line may include two more parameters The First parameter is the default mask file loaded at initialization The Second parameter is the design rule file loaded at initialization The following command executes MICROWIND2 with a default mask file test MSK gt and the ru
72. o eu k PE J El E E i 7 j E po i j i I a h a E 3 a i l i i ML a Ar e ei o er a i i il E B E pl i Pler ti s E gt pr H a H H T 1 i si i i j i j j i iE SS E rrr Pe tn torre To f In Pos Pl rl i pss i a i j x re ida I Jairo 13d jme mac poo AE fra ss a a x i gt y EF mi j li I j Ino PS Ee ee A ho rr a A ML un L5 4 u 15 u 3 3 4u 4 Le Fig 6 5 The full custom implementation of the full adder and its simulation FullADD MSK You may create the layout of the full adder by hand in order to create a compact design Notice that the AND OR combination of cells may be replaced by a complex gate An example of full custom layout of the full adder is proposed in Figure 6 5 Notice that the carry propagates vertically within the cell to ease multiple addition The typical delay is less than 100ps in 0 25um technology module fulladd sum carry a b c IMU ayo output sum carry wire suml xor xorl suml a D xor xor2 sum suml c and and el a b and and2 c2 b c and and3 c3 a c ar orl carry cl c2 c3 endmodule Alternatively you may use DSCH2 to create the schematic diagram of the full adder and compile it directly into layout Verify the circuit with buttons and lamps Save the deign under the name fadd sch using the 48 20 01 02 MICROWIND amp DSCH USER S MANUAL
73. ppears The proposes size is 1 25um for the width 0 25um for the length Simply click Generate Device and click on the middle of the screen to fix the MOS device Click again the icon MOS generator on the palette Change the type of device by a tick on p channel and click Generate Device Click on the top of the nMOS to fix the pMOS device The result is displayed in figure 3 7 Bar apout Generabor Pads inductor Contacts Bus MOS Path Logo Mos Paramelers whith WGS 1 250 um Lengih MOS jo 20 Lift Nbr of Gates fi T Add rn tall ta drain and soume Qpiuns Tepe Y iF DIETE aei Sie Channel Tf micron pm j gt m ella m ie e ge ee A Generale Diga x Cancel Fig 4 6 nMOS and pMOS devices placed on the layout 33 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 4 lambda on AAA A D 625um E EN Hi EESE eae VDD supply ERTS SEP URI vores fess Beg PMOS device Poly Gate ee NMOS device LLL Ap LL Fig 4 7 The circuit Inverter compiled into layout 4 5 Analog simulation of the INVERTER Click Simulate gt Start Simulation or the icon above The simulation of the circuit is performed You may verify the correct behavior of the inverter cell Fig 4 8 The analog simulation of the circuit Inverter MSK using Microwind2 34 20 01 02 4 6 4 7 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 2D V
74. rilog File In Microwind2 click on the command Compile gt Compile Verilog File Select the text file DLATCH txt Click on Compile 56 20 01 02 7 3 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories Edge Trigged Latch The most common example of an edge trigged flip flop is the JK latch Anyhow the JK is rarely used a more simple version that features the same function with one single input D is preferred This simple type of edge trigged latch is one of the most widely used cells in microelectronics circuit design The cell structure comprises two master slave basic memory stages The most compact implementation of the edge trigged latch is reported below The schematic diagram is based on inverters and pass transistors On the left side the two chained inverter are in memory state when the pMOS pass transistor Pl is on that is when CLK 0 The two chained inverters on the right side act in an opposite way The reset function is obtained by a direct ground connection of the master and slave memories using nMOS devices The logic siganl flows from source to drain Css pr ema one A a D source drain mynot inat mynot outsource drain mynot out mynot out a nms Lomos P Ou L 0 25u tj gate drain source gate drain source mos lnmos drain O drain source Source O nmos nmos reset gate gate gate i gate ek gt Figure 7 6 The edge trigged latch and its logic simulation Dreg MSK Notice that
75. rinciples in nMOS and pMOS versions The illustration of the current mirror behavior is performed on the layout of figure 8 6 The circuit includes a voltage reference using N1 and P1 as described above a device N2 which has an identical size as N1 and a device N3 with L 0 5um leading to a ratio equal to 10 W L of N1 What we expect is a current I2 equal to I1 in most operating conditions and a current I3 10xI1 W 0 50 L 5u 0 5u L 5u 0 5u L 0 5u Me Figure 8 6 Illustration of the current mirror principles Mirror MSK 68 20 01 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells You may observe each MOS characteristics by using the command Simulate Simulate on Layout During the transient simulation the functional point of the select MOS device appears in the characteristics which provides a valuable aid to understand the current mirror behavior For most values of Vload N2 produces the same current as N1 except when Vload is lower than 0 5V 8 4 Single Stage Amplifier The single stage amplifier is described in figure 8 7 It consists of a MOS device we choose here a n channel MOS and a load resistance The resistance can be made from polysilicon or diffusion As the gain of this amplifier is proportional to the load resistance a MOS device with gate and drain connected as shown in figure 8 7 could replace the resistance This is called an active resistance Using a small silicon area high resistance can be obtai
76. s 1 stage Fig 5 11 The complex gate implementation of the function F A B C 42 20 01 02 9 6 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates Microwind2 is able to generate the CMOS layout corresponding to any description based on the operators AND and OR using the command Compile gt Compile one line Using the keyboard enter the cell equation or modify the items proposed in the list of examples In the one line equation the first parameter is the output name In the present case that name is s The sign is obligatory The sign corresponds to the operation NOT and can be used only right after the sign The parenthesis are used to build the function where is the AND operator and is the OR operator a ill Fig 5 12 A compiled complex gate dnd its es se eee ComplexABCD MSK Multiplexor Multiplexing means transmitting a large amount of information through a smaller number of connections A digital multiplexer is a circuit that selects binary information from one of many input logic signals and directs it to a single input line The main component of the multiplexer is a basic cell called the transmission gate The transmission gate let a signal flow if Enable is asserted Remember that the n channel MOS is only good for low signals and the p channel MOS is only good for high signals To pass logic signals well both a n channel device and a p channel device must be used as shown in figure 5
77. s O E cae oh ates eee neat ae E eee uine alae TE aids 43 Ded ATO IVP le KC e E E pasate ang wsoneneiarauenmaneesoensa ue en serumeacte eens 44 520 Keyboard multiple dd 44 3 20 01 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction PATTI CLIC a ds 45 Gal TE GT CC Gas ia at ds 45 62 ULEAD ta at 46 6 3 Ful Adder Symbolin IDSC Hita ooo id cal Seas 47 O24 Bula ddr ay OU iaria a a a cleat a a icant amedusaleaucbaiounnseaees 48 050 POMAR oca 49 CO C00 4 021122 O a a E E eee ear eer eey a Cen eerene eeeae ea 51 67 AmC and Oric Units ALU a o cta 52 Te ALCOR IMC aos 53 A a anche atest a dated ca saa i aap el aetah dats a hacmainildeen nee lane antec 53 Te D AUC A sees ends a awe a a eaalondets 55 Edge Vil OCC Laienes o wi as T E A naamieee meas 57 E E i A A A I E E E E E E E A T 60 73 RAM MeMO oa a dd e dead 61 PO RAMAI A a A 63 CS N E scccstart Metaannad seems shavacoesccdetewshietestadcee les 64 TO RAM Column SCLC CHOI aiii 65 o Analor Coll aia 66 Sal Diode comected MOS ataco 66 0 2 Volta se Retroceder dia 67 So BN O O O eadnes se reaadontannigead Missateagiscanhaheeisuadeetouress 68 de MIN le taco Ampli idas 69 6 5 pimple Differential Ampli 70 5 0 Voltade Controlled OSC aOR rca tal il load aa a ato losa 74 O CONVOCVICIS A EE es vosasuaseasacs eaucecosetsens ia 76 O A E E sates nustaeemen S aiaeaanwe ee cacnen aaa 76 2 MieitaleAiialoe Conve Merea canoes cress a 78 93 Sample ana Hold Ci Cull acid ladera dla 19 10 I
78. s018rul O 10um 2002 8s fio 3 020 2000 Cmos010 ru E e E E 5 metal layer technology San EE EE im scillate2 Fig 2 6 A three inverter ring oscillator routed with 2 metal layers and 5 metal layers technologies As can be noticed the number of metal layers used for interconnects has been continuously increasing in the course of the past ten years More layers for routing means a more efficient use of the silicon surface as for printed circuit boards Active areas 1 e MOS devices can be placed closer from each other if many routing layers are provided Figure 2 6 HOW TO SIMULATE O Start Microwind2 By default the software is configured with 0 25um technology Click File gt Open Select INV3 Click Simulate Process section in 2D Draw a line representing the location for 2D process view The 2D view appears Click OK Click Simulate gt Start Simulation Observe the oscillator frequency Click File Select Foundry Select ams08 rul 0 8um technology Ask again for the 2D view Observe the change in the process aspect Ask again for analog simulation Observe the change in frequency and voltage supply 10 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 3 The MOS device 3 1 This chapter presents the CMOS transistor its layout static characteristics and dynamic characteristics The vertical aspect of the device and the three dimensio
79. sed on transmission gates Mux2Kbd sch 44 20 01 02 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics 6 Arithmetics 6 1 This chapter introduces basic concepts concerning the design of arithmetic gates The adder circuit is presented with its corresponding layout created manually and automatically Then the comparator multiplier and the arithmetic and logic unit are also discussed This chapter also includes details on a student project concerning the design of binary to decimal addition and display Half Adder Gate The Half Adder gate truth table and schematic diagram are shown in Figure 6 1 The SUM function is made with an XOR gate the Carry function is a simple AND gate HALF ADDER A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Fig 6 1 Truth table and schematic diagram of the half adder gate HADD MSK FULL CUSTOM You may create the layout of the half adder fully by hand in order to create a compact design Use the polysilicon and metall layers for short connections only because of the high resistance of these materials Use Poly Metal Diff Metal contact macros situated in the upper part of the Palette menu to link the layers together LAYOUT Load the layout design of the Half Adder through the File gt Open and LIBRARY HADD MSK sequence 45 20 01 02 6 2 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics VERILOG COMPILING Use DSCH2 to create the schematic diagram of the half adder V
80. so exists a 3 state inverter Notif The output remains in high impedance as long as the enable En is set to level The truth table of the 3 state inverter is reported below Fig 4 11 Truth table of the three state inverter 36 20 01 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates 5 Basic Gates 9 1 The Nand Gate The truth table and logic symbol of the NAND gate with 2 inputs are shown below In DSCH select the NAND symbol in the palette add two buttons and one lamp as shown above Add interconnects if necessary to link the button and lamps to the cell pins Verify the logic behavior of the cell A B Out 00 1 01 1 10 1 11 0 Fig 5 1 The truth table and symbol of the NAND gate In CMOS design the NAND gate consists of two nMOS in series connected to two pMOS in parallel The schematic diagram of the NAND cell is reported below The nMOS in series tie the output to the ground for one single combination A 1 B 1 For the three other combinations the nMOS path is cut but a least one pMOS ties the output to the supply VDD Notice that both nMOS and pMOS devices are used in their best regime the nMOS devices pass 0 the pMOS pass 1 0m 0 751m Fig 5 2 The truth table and schematic diagram of the CMOS NAND gate design 3 20 01 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates You may load the NAND gate design using the command File gt Read gt NAND MSK You may als
81. stance must be high to keep the short cut current low to avoid wasted power consumption A key idea is to use MOS devices rather than polysilicon or diffusion resistance to keep silicon area very small HRP ref ref Small W EAS large L i Figure 8 3 Voltage reference using PMOS and NMOS devices as large resistance i 1 Wref i 1 L Figure 8 4 Voltage reference of 1V Vref MSK 67 20 01 02 8 3 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells In the layout of figure 8 5 the PMOS and NMOS have the same size Due to lower PMOS mobility the resulting Vref is not VDD 2 but 1V You may change the temperature Simulate gt Simulate Options and see how the voltage reference is altered by temperature Current Mirror The current mirror is one of the most useful basic blocs in analog design In its most simple configuration it consists in two MOS devices as presented in figure 8 5 A current Il flowing through the nMOS device Master is copied to the MOS device Slave If the size of Master and Slave are identical in most operating conditions the currents are the same The remarkable point is that the current is almost independent of the drain voltage of the slave V2 If the ration W L of the Slave is 10 times the ratio of the Master the current on the right branch is 10 times the current on the left branch v2 l i2 Vi 1 mos i prgos nms Argos Master Slave T 1 2 0 Figure 8 5 Current mirror p
82. t parameter 0 01 6um 0 01 6um Channel length offset parameter 0 01 6um 0 01 64m reduction reduction KTI Temperature coefficient of the threshold voltage 01V 0V mE WORF offer voltage in subthreshold region oov loov 3 12 Low leakage MOS A new kind of MOS device has been introduced in deep submicron technologies starting the 0 18um CMOS process generation The new MOS called low leakage or High Vt MOS device is available as well as the normal one recalled high speed MOS The main objective is to reduce significantly the Ioff current that is the small current that flows from between drain and source with a gate voltage 0 Supposed to be no current in first order approximation On the figure below the low leakage MOS device right side has an Ioff current reduced by a factor 50 thanks to a higher threshold voltage 0 45V rather than 0 35V Small lon reduction pepe AAA O AAA A TEENE RS A Fig 3 14 Low leakage MOS for lower loff current The main drawback of the Low leakage MOS device is a 30 reduction of the Ion current leading to a slower switching High speed MOS devices should be used in the case of fast operation linked to critical nodes while low leakage MOS should be placed whenever possible for all nodes where a maximum switching speed is not required 23 20 01 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter high speed MOS 1 2 in O 12um lowleakage MOS
83. tage in subthreshold region 0 08V 0 08V Parameter for channel length modulation Function depth For MOS2 MOS3 and MOS4 only the threshold voltage mobility ant oxides thickness are user accessible All other parameters are identical to MOSI 96 20 01 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules 12 12 TEC file for DSCH2 The logic simulator includes a current evaluator To run this evaluation the following parameters are proposed in a TEC file example cmos012 TEC DSCH 2 0 technology file NAME CMOS 0 12um VERSION 14 12 2001 Time unit for simulation TEMEUNTET 0 Supply voltage VDD le eZ Typical gate delay in ns TDelay 0 02 Typical wire delay in ns TWireDelay 0 07 TypoLceal current in mA TCurrent 0 5 Default MOS length and width Mi 380s Lu MNW 1 0u MPW 2 0u 97 20 01 02 DSCH amp MICROWIND USER S MANUAL 13 Design Rules File for 0 12um 13 Design Rule File for 0 1 2um MICROWIND 2 0 Rule File for CMOS 0 12um Date 27 Apr 99 created by Etienne Sicard 04 Jan 00 smaller dt is 03 Avr 01 2d cross section x 17 Apr 01 update params add high voltage tox level3 20 Apr 01 various lowK 4 types of MOS 10 Dec O1 Bsim4 model gatek NAME CMOS 0 12um 6 Metal lambda 0 06 Lambda is set to half the gate size metalLayers 6 Number of metal layers Dielectrics lowK 3 2 inter me
84. tal oxide permittivity gateK 5 0 HighK gate dielectric Design rules associated to each layer Well riol 10 well width r102 11 well spacing Diffusion r201 4 diffusion width r202 4 diffusion spacing r203 6 border of nwell on diffp r204 6 nwell to next diffn Poly r301 2 poly width r302 2 gate length r303 4 high voltage gate length r304 3 poly spacing r305 1 spacing poly and unrelated diff r306 4 width of drain and source diff r307 2 extra gate poly Poly 2 Pol e poly2 width 98 r312 2 poly2 spacing x Contact r401 2 contact width r402 3 contact spacing r403 2 metal border for contact r404 2 poly border for contact r405 2 diff border for contact r406 3 contact to gate r407 2 poly2 border for contact x metal r501 3 metal width r502 4 metal spacing via r601 2 Via width r602 4 Spacing r604 2 border of metal amp metal2 metal 2 r701 3 Metal 2 width r702 4 via 2 r801 2 Via width r802 4 Spacing r804 2 border of metal2 amp metal3 metal 3 r901 3 width r902 4 spacing via 3 ra01l 2 Via width ra02 4 Spacing ra04 2 border of metal3 amp metal4 metal 4 rb01 3 width rb02 4 spacing via 4 EC Od 2 Via width rc02 4 Spacing rc04 2 border of metal4 amp metal 5 m
85. ter DAC MSK 16 0 Aa 14 0 A nae oe 12 0 shows a regular increase of the output voltage Vout with sat A 5 the input combinations from 000 OV to 111 4 375V Each input change provokes a Bunn wn i ee SS Transmission gate Used as sample Hol D Fig 9 5 Simulation of the digital During the conversion from analog to digital the input signal must be kept constant This operation is called sample and hold The transmission gate can be used as a sample and hold circuit The layout of the transmission gate is reported below capacitance network charge and discharge The simulation of the DAC Fig 9 9 3 Sample and Hold circuit 20 01 02 6 The transmission gate used to sample analog signals SampleHold MSK Fig 9 79 MICROWIND amp DSCH USER S MANUAL 9 Converters The effect of sample and hold is illustrated in figure 9 7 When sampling the transmission gate is turned on so that the sampled data DataOut reaches the value of the sinusoidal wave DataIn When the gate is off the value of the sampled data remains constant This is mainly due to the parasitic capacitance of the node which is the order of several fF i i l 25i l I I I I A AE ERs A A IA l l l l l I I l 1 l l I I l l wil A SE AA j eS er ae AAA ry Fig 9 7 Effect of sampling on a sinusoidal wave SampleHold MSK 80 20 01 02 10 10 1 10 2 MICROWIND
86. the line Sel goes to 1 The two inverter latch takes the Data value When the line Sel returns to O the RAM is in a memory state See figure 7 13 for the analog simulation of the WRITE cycle READ CYCLE In order to read the cell the line Sel must be asserted The RAM value propagates to Data and its inverted value propagates to nData SIMULATION The simulation parameters correspond to the write cycle in the RAM The simulation steps describe din figure 6 16 are as follows Mem reaches 1 after an unstable period unpredicatable value Data gets to value O and nData to value 1 Sel is asserted The memory cell Mem goes down to 0 Data gets to a value of 1 and nData gets to a value of 0 Sel is still asserted The memory cell fights against Data 1 and surrenders Mem 1 Selis inactive The RAM is in a memory state 62 20 01 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories 2 50 Fig 7 13 Write cycle for the static RAM cell RAMI1 MSK 7 6 RAM Array You can duplicate the RAM cell into a 4x4 bit array using the command Edit gt Duplicate XY Select the whole RAM cell and a new window appears Enter the value 4 for X and 4 for Y into the menu Click on Generate The result is shown below ee lo A OL A AA if LE Et ERBE Eros et a z Api EBH EEE Fl E H E HE HE he HB EEE Ei TAGE El ES TT DI Jiel E Hee i EER a PE o E ne p Es EJER rif Petr ame HE
87. tive feature is the possibility to estimate the power consumption of the circuit Some techniques for low power design are described in the manual The MICROWIND2 program allows the student to design and simulate an integrated circuit at physical description level The package contains a library of common logic and analog ICs to view and simulate MICROWIND2 includes all the commands for a mask editor as well as original tools never gathered before in a single module 2D and 3D process view VERILOG compiler tutorial on MOS devices You can gain access to Circuit Simulation by pressing one single key The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately The chapters of this manual have been summarized below Chapter 2 describes the technology scale down and the major improvements given by deep sub micron technologies Chapter 3 is dedicated to the presentation of the single MOS device with details on the device modeling simulation at logic and layout levels Chapter 4 presents the CMOS Inverter the 2D and 3D views the comparative design in micron and deep submicron technologies Chapter 5 concerns the basic logic gates AND OR XOR complex gates Chapter 6 the arithmetic functions Adder comparator multiplier ALU The latches and memories are detailed in Chapter 7 20 01 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction As for
88. voltage mobility ant oxides thickness are user accessible All other parameters are identical to MOSI NMOS pMOS MOS2 MOS3 U0 Mos2 Mobility for MOS2 006 U0 Mos3 Mobility for MOS3 006 MOS2 MOS3 Nmos Model parameters NMOS LSVEO 0 4 Toug O 06 LSCOX 36 9 l3vmax 170e3 l3gamma 0 4 LO Nea S Do l3kappa 0 06 LSM 032 131d 8e 9 Lonss Oe O16 high speed Lovato Uns Lua 0206 13t2ox 3e 9 high voltage 13v3to 0 7 ESS SO 6 13t30x 7e 9 95 20 01 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules 12 11 BSIM4 Model for analog simulation The list of parameters for BSIM4 is given below Parameter Keyword Description VEB b4vfb Flat bandvoltage 09 09 KI baxl First order body bias coefficient 045 VI2_ 045V1 2 K2 b k2 Second order body bias coefficient 01 Joi b4d0vt First coefficient of short channel effect on 22 22 threshold voltage b4divt Second coefficient of short channel effect 0 53 0 53 on Vth 1 Drain induced barrier lowering coefficient NFACTOR B4nf Sub threshold turn on swing factor 1 cad dl Controls the exponential increase of current OS with Ves degradation due to vertical field body bias effect v 1 v 1 WINT Channel width offset parameter 0 01 6um 0 01 6um Channel length offset parameter 0 01 6um 0 01 6um mobility reduction effect mobility reduction voltage mobility UO Offset vol

Microwind & Dsch Version 2 User`s Manual

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Microwind &amp; Dsch Version 2 User`s Manual

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Microwind & Dsch Version 2 User`s Manual