EVBUM2276 - KAI-2093 Image Sensor Evaluation Timing
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1. LINE XFR FRAME_VALID q j Count 1214 falling edge Set INTEGRATE on INTG_START a falling edge y z Issue INTG_START INTG START ENTRY 1 Y F Execute LT5 SEA E AA 7 al Wait for VD_TG Set INTEGRATE VD_TG Wait for INT ctr FRAME_VALID Y L Issue VD_TG o e e asebe o Reset INTEGRATE Y ENTRY 2 Execute LT1 DIODE XFR y Count 1 Wait for FRAME_VALID g j rising edge W ENTRY 3 Jump to FT0 Entry 0 Count 1 Figure 9 Free Running Mode Timing Sequence http onsemi com 16 EVBUM2276 D V1_CCD V2 COD j r H1A CCD ml Tami H2A CCD _ mmm mam INTEGRATE VD TG _ FRAME_ VALID LINE_VALID FTO Entry Line Table Counts PLD STATE V_TRANSFER TIMED_INTEGRATION DIODE_TRANSFER not to scale Figure 10 Frame Table 0 Default Timing Frame Table 1 Sequence Frame Table 1 contains the 2x2 Binning Mode timing sequence used to sum the charge collected in four photosites into one CCD pixel The sequence is identical to that of INTEGRATE Frame Table 0 except that the Vertical Clocks are asserted twice per line which dumps charge from two vertical CCD pixels into each Horizontal register CCD pixel cH VD_TG _ FRAME_VALID o Eoo o LINE_VALID PLD STATE V_TRANSFER TIMED_INTEGRATION DIODE_TRANSFER not to scale Figure 11 Frame Table 1 Default Timing Electronic Shutter Timing The electronic shutter timing is2. No Shutter I e2 O No Shutter No Shutter No Shutter No Shutter s S No Shutter No Shutter No Shutter No Shutter 4 060 5 060 6 060 7 060 8 060 No Shutter No Shutter No Shutter No Shutter http onsemi com 20 EVBUM2276 D Integration Time Tint s 10 000 1 000 0 100 a Tint Free Running 0 010 0 001 0 4 8 12 16 20 24 28 32 DIO 11 7 Figure 15 Programmed Integration Times wco YL 7p V2 CCD 1 2 1103 1104 VES shutter Shutter Line 2040 No shutter pulse INTEGRATE ims Clock Integration Count 0 1 VD_TG FRAME_ VALID LINE_VALID FTO Entry Line Table Counts DIO 11 7 not to scale Figure 16 Free Running Mode Default Integration Timing http onsemi com 21 V1_CCD V2_CCD VES shutter INTEGRATE 1ms Clock VD_TG FRAME_ VALID LINE_VALID FTO Entry Line Table Counts DIO 11 7 V1_CCD v2_CCD VES shutter INTEGRATE 1ms Clock VD_TG FRAME_VALID LINE_VALID FTO Entry Line Table Counts DIO 11 7 EVBUM2276 D 1 2 3 4 5 965 966 1103 1104 _ I Integration Count 0 1 Shutter Line 966 not to scale Figure 17 Free Running Mode Integration Timing with Shutter not to scale Figure 18 Free Running Mode Extended Integration Timing http onsemi com 22 EVBUM2276 D BOARD INTERFA
3. Register Entry 1 channel 2 channel Evaluation Board oe Name Register 6 Pixel Rate Signal Offset The default settings written to Register 6 depend on the position of SWO on the Timing Board used to select between 1 channel and 2 channel operation Table 16 REGISTER 6 DEFAULT SETTING Data Data Register Entry channel channel CCD Signal Name H6 Cell HG_OFFSET O 5 0 Cell HG_OFFSET O 5 J 2 o NotUsed Used r S Crore 5 o ta E o l mms sr w RG Re OFFSETS 5 l Ugasl RESET SOS n _OFFSET 0 5 E A SH1_OFFSET 0 5 SHP2 SH4_OFFSET 0 5 SHD1 SH3_OFFSET 0 5 SHD2 DATACLK1_OFFSET 0 5 ADCLK to AFEs DATACLK2_OFFSET 0 5 DATACLK to Framegrabber Register 7 Pixel Rate Signal Width The default settings written to Register 7 depend on the position of SWO on the Timing Board used to select between 1 Channel and 2 Channel operation Table 17 REGISTER 7 DEFAULT SETTING Data Data Register Entry 1 channel 2 channel CCD Signal Name Not Use Wate re wore ADGLK fo AFES http onsemi com 10 EVBUM2276 D Register 8 Frame Tables Several Frame Tables are written by default to the KSC 1000 Frame Table registers but only one Frame Table is active at one time as determined by the Frame Table Pointer Register 0 Frame Table 0 is used for Free Running Single Channel and Dual Channel modes and Frame T
4. EVBUM2276 D effect either by pressing the BOARD_RESET button S1 on the Timing Board or by setting and resetting the Remote Reset DIO14 input Integration amp Electronic Shutter Control In the Full Field Timing Modes PLD inputs DIO 11 7 may be used to select the integration time See Table 25 for timing details In general when making a change to the DIO 11 7 settings the user must initiate a Board Reset for the change to take effect either by pressing the BOARD_RESET button S1 on the Timing Board or by setting and resetting the Remote Reset DIO14 input Binning Control PLD input SW2 is used to select between 2x2 Binning Single Output and normal operation no binning When making a change to the switch settings the user must initiate a Board Reset for the change to take effect either by pressing the BOARD_RESET button S1 on the Timing Board or by setting and resetting the Remote Reset DIO14 input Video Mux Switch The PLD input SW6 controls the Video Mux Switch which steers either CCD output VoutL or VoutR to the auxiliary video output connector J1 ALTERA CODE I O Inputs The Altera PLD has multiple inputs that may be used to control certain functions The inputs include user selectable switches SW 7 0 on the Timing Board remote digital inputs DIO 15 0 and a 3 wire serial interface through Timing Board connector J7 Timing Board signals and various outputs from the KSC 1000 Timing Generat
5. Pointer Register 0 must be changed to a value of 2 This is done by setting SW2 HIGH and pressing the BOARD_RESET button S1 on the Timing Board or by setting and resetting the Remote Reset DIO14 input VOUT_CCD o r i gt lt Tr RESET_CCD H2A_CCD H1A_CCD SHP C 2 j j Jj gt lt Tshp ns gt lt Tshd SHD 4 4 4 4 DATACLK f f f ae Figure 14 Binning Mode Horizontal Timing Integration amp Shutter Timing The default Integration Time in Free Running Mode is approximately one Frame Time or the time between Frame Transfers during which the photodiodes are collecting charge Figure 16 This time may be decreased by use of the Electronic Shutter Figure 17 and may be increased by lengthening the Frame Time Figure 18 The user may control the Integration Time through the DIO connector bits DIO 11 7 This connector is optional and when disconnected all bits are pulled LOW The available pre programmed Integration Times are detailed in Table 25 The Electronic Shutter is controlled by changing the Integrate Start Pulse Line Number value of the KSC 1000 Register 4 The Altera PLD has 8 pre programmed Shutter settings controlled through the DIO 11 7 bits as shown in Table 14 and Table 25 These settings result in Integration times of one Frame Time or less in increments of 1 8 of the Frame Time See Figure 17 When the Integrate Start Pulse Line Number value is set
6. 6 Analog Devices AD9840A Product Data Sheet 3 KAI 2001 KAI 2020 KAI 2093 Imager Board 40 MHz operation Schematic ON Semiconductor and the are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into
7. sequence that transfers charge from all the photodiodes to the vertical registers See Figure 5 Table 21 LINE TABLE 1 DEFAULT SETTING LT1 Entry CCD Signal Line Table Data Name 4 5 6 Count 0 12 HCLK_H Enable aie SRI S SOI Pe SE ZSI SISI http onsemi com 12 EVBUM2276 D Line Table 2 is the Integration sequence The vertical clocks are not active and the Horizontal register is continually flushed of charge See Figure 6 Table 22 LINE TABLE 2 DEFAULT SETTING LT2 Entry CCD Signal Line Table Data Name 0 1 Count 0 12 1 0 HCLK_H Enable 1 0 Line Table 3 is the Binning Mode Line Transfer sequence interval followed by Horizontal Register readout See Two V1 and V2 pulses occur during each Vertical clocking Figure 7 Table 23 LINE TABLE 3 DEFAULT SETTING LT3 Entry saslar a L ee t eee Eee r cea eS a el ee ae eee ee eee Line Table 4 is an Integration sequence Neither the Vertical clocks nor the Horizontal clocks are active See Figure 8 Table 24 LINE TABLE 4 DEFAULT SETTING Count 0 12 HCLK_H Enable V6 V5 V4 V3 V2 V1 http onsemi com 13 EVBUM2276 D KAI 2093 TIMING Line Table 0 Line Transfer Line Table 0 is the Line Transfer timing sequence that is moved down the vertical CCD registers and the last row transfers one entire row of charge toward the horizontal of charge is dumped into the horizontal register The VCCD
8. the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 chief ee Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Ema
9. B and the default VGA gain is set to maximize the dynamic range of the AFE See Table 9 and References Timing Board Analog Digital Front Eng Out ble AFE 2 stage Op Amp Buffer 2 prog gain Av 1 25 Figure 19 Video Signal Path Block Diagram WARNINGS AND ADVISORIES When programming the Timing Board the Imager Board must be disconnected from the Timing Board before power is applied If the imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of a ON Semiconductor Evaluation Board Kit may at their discretion make changes to the Timing Generator Board firmware ON Semiconductor can only support firmware developed by and supplied by Truesense Imaging Changes to the firmware are at the risk of the customer ORDERING INFORMATION Please address all inquiries and purchase orders to Truesense Imaging Inc 1964 Lake Avenue Rochester New York 14615 Phone 585 784 5500 E mail info truesenseimaging com ON Semiconductor reserves the right to change any information contained herein without notice All information furnished by ON Semiconductor is believed to be accurate http onsemi com 24 EVBUM2276 D REFERENCES 1 KAI 2093 Device Specification 4 KSC 1000 Timing Generator Board User Manual 2 KAI 2001 KAI 2020 KAI 2093 Imager Board 5 KSC 1000 Timing Generator Board Schematic User Manual
10. CE CONNECTOR SIGNAL MAP For reference the board interface timing signals from the shown in Table 26 Note that the power connections are not 3F5054 Timing Board to the 3F5121 Imager Board are shown here Table 26 TIMING BOARD IMAGER BOARD SIGNAL MAP KSC 1000 Timing Board KAI 2093 Imager Board KSC 1000 LVDS Interface LVDS Interface Imager Board Signal Name Signal Name 3F5054 J6 Pins 3F5121 J1 Pins Signal Name Signal Name TIMING_OUTO INTG_START TIMING_OUT1 IMAGER_IN11 TIMING_OUT2 9 10 9 10 IMAGER_IN10 manua mam mm maa ms O v meo me m wes Wa mama umum mama mamam TIMING_OUT13 AMP_EN TIMING_OUT14 IMAGER_IN0 AMP_ENABLE SCLOCK TIMING_OUT15 IMAGER_IN15 pour meom wo reo http onsemi com 23 EVBUM2276 D VIDEO SIGNAL PATH The entire video signal path through the Imager Board and Timing Board is represented in Figure 19 The individual blocks are discussed in the Imager Board User Manual and the Timing Board User Manual The hardware gain for the entire pre AFE signal path can be calculated by multiplying the gains of the individual stages 0 96 x 1 25 x 0 5 x 1 25 0 75 eq 1 Imager Board Emitter Follower Av 0 96 Op Amp Buffer Av 1 25 Coax Cab 75ohm terminated Av 0 5 The gain of the hardware signal path is designed so that the saturation output voltage of the KAI 2093 CCD will not overload the AFE input The AFE default CDS gain is set at 1 0 0 0 d
11. EVBUM2276 D KAI 2093 Image Sensor Evaluation Timing Specification 10 bit 40 MHz AFE Altera Code Version Description The Altera code described in this document is intended for use in the KSC 1000 Timing Boar The code is developed specifically for use with the following system configuration Table 1 SYSTEM CONFIGURATION ON Semiconductor www onsemi com EVAL BOARD USER S MANUAL Evaluation Board Kit PN 4H0705 Timing Generator Board PN 3F5054 AD9840A 40 MHz KAI 2001 KAI 2020 KAI 2093 CCD Imager Board PN 3F5121 Framegrabber Board National Instruments PCI 1424 The 3F5054 Timing Generator Board features the KSC 1000 Timing Generator chip The KSC 1000 provides all of the signals necessary for an imaging system using Full Frame KAF or Interline KAI family of image sensors It also provides the signals necessary for operation of two analog front end AFE chips enabling independent optimization of the AFE chips for dual channel readout devices ALTERA CODE FEATURES FUNCTIONS The Altera Programmable Logic Device PLD serves as a state machine which performs a variety of functions Three basic functions are required common to all CCD image sensor configurations serial input steering AFE default programming and KSC 1000 default programming In addition certain other functions specific to the KAI 2093 Image Sensor are implemented Serial Input Steering The 3 wire serial in
12. OPERATION The following modes of operation are available to the user Electronic Shutter Modes The Evaluation Board electronic shutter circuitry provides a method of precisely controlling the image exposure time without any mechanical components Charge may be cleared from the CCD photodiodes at some time during the readout of the previous frame This allows integration times of less than one frame time to compensate for high light exposures that would otherwise saturate the CCD In Free Running Mode the default integration time can be set from 1x to 1 8x frame time via the digital inputs DIO 11 7 See Table 14 and Table 25 When changing the integration time the user must initiate a Board Reset for the change to take effect either by pressing the BOARD_RESET button S1 on the Timing Board or by setting and resetting the Remote Reset DIO14 input Black Clamp Mode One of the features of the AD9840A AFE chip is an optical black clamp The black clamp CLPOB is asserted during the CCD s dark pixels and is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD s black level The location of these pulses is fixed in the default KSC 1000 settings but can be adjusted dynamically through the 3 wire serial interface The default settings are shown in Table 11 POWER ON BOARD RESET INITIALIZATION When the board is powered up the Board Reset button is pressed or the Remote Re
13. Signal Output SCLOCK 3 wire Serial Interface CLOCK Signal Output Not Used for KAI 2093 Operation Asynchronous Reset to KSC 1000 from DIO14 KAI 2093 TIMING CONDITIONS System Timing Conditions Table 6 SYSTEM TIMING Description Symbol Time Notes System Clock Period Tsys 12 5 ns 80 MHz System Clock Unit Integration Time Uint 1 0 ms Generated by PLD CCD Timing Conditions Table 7 CCD TIMING Description Symbol Time Notes H1 H2 RESET Period Tpix 25 00 ns 40 MHz Clocking of H1 H2 RESET VCCD Delay Tay 25 00 ns Delay after Hclks Stop VCCD Transfer Time 1 95 us V2 Rising Edge to V2 Falling Edge Worcs w e 1002660 ies 7 vec tres http onsemi com 5 EVBUM2276 D Table 7 CCD TIMING continued Pixel Description Symbol Time Counts T3p Photodiode Pedestal Time Photodiode Transfer Time 12 28 us Photodiode Delay Tsp 20 00 us 491 800 V2 3rd Level Photodiode Frame Delay 32 75 us 1310 Delay before 1 Line Transfer Photodiode Transfer Period 90 03 us 3601 Teer Tae Tayak T3p T3E Shutter Pulse Setup TEL Poe m S Shutter Pulse Time Ts Shutter Pulse Delay Tsp PCI 1424 Timing Conditions Table 8 PCI 1424 TIMING 15 00 us 1 60 us 600 64 Pixel Description Symbol Time Counts PIX Period 25 00 ns 40 MHz Clocking of DATACLK Sync Signal FRAME Time 59 60ms 2 383 825 Terame Tpix Vperiod Hpix Vpix Tapr MODES OF
14. able 18 FRAME TABLE 0 DEFAULT SETTING Table is used for Single Channel 2x2 Binning mode Note that the last row in Table 18 and Table 19 are the mnemonics associated with the Flag Count and Address bits See the KSC 1000 Device Specification References for more details FTO Entry Clear Line Counter 1 Force INTG_STRT Horizontal Binning Factor x 5 o eo o s T o s C meues 6 T o j arate arena e o 5 AFE Clock Enable CLPDM2 Enable 11 CLPDM1 Enable 2 Gomes _ s o ara ere x 4 ra r o L esa a C rm _ j s es s s r 33 Address 3 Mnemonic Table 19 FRAME TABLE 1 DEFAULT SETTING 0 0 0 ELTO ExLTNVD 4 ELT 1 Bit Location Frame Table Data FT1 Entry 3 4 Horizontal Binning Factor E 25 U CLPDM2 Enable 11 CLPDM1 Enable http onsemi com 11 EVBUM2276 D Table 19 FRAME TABLE 1 DEFAULT SETTING continued FT1 Entry Bit Location Frame Table Data 13 CLPOB1 Enable 14 PBLK Enable ose tl 15 Pblk_Idle_ Val a Address 2 0 Address 3 Mnemonic ELTO ExLTNVD 5 ELT 1 JMPFT 1 Register 9 Line Tables There are five Line Tables written by default to the KSC 1000 Line Table registers Line Table 0 is the normal Line Transfer sequence See Figure 4 Table 20 LINE TABLE 0 DEFAULT SETTING LTO Entry Count 0 12 Line Table 1 is the normal Photodiode Transfer
15. controlled by the values in Register 3 of the KSC 1000 There are two methods of actuating the Electronic Shutter pulse by setting the Integrate Start Pulse Line Number value in Register 4 so that the pulse occurs on a specific line or by setting the Force INTG_START bit in a Frame Table entry In either case the Electronic Shutter pulse setup width and hold times are determined by the values in Register 3 The shutter sequence is inserted before the specified line causing that particular line time to be extended accordingly If the Integrate Start Pulse Line Number value in Register 4 is set to 0 the Electronic Shutter will occur immediately following the Diode Transfer sequence before the first line is read out If the Integrate Start Pulse Line Number value is greater than the number of vertical lines in the Frame Table there will be no Electronic Shutter This is the method used to disable the Electronic Shutter http onsemi com 17 EVBUM2276 D idth Reg3 Entry oig Line Table 0 Petain J 801 000 ee not to scale Figure 12 Electronic Shutter Timing Horizontal Timing Figure 13 depicts the basic theoretical relationship between the pixel rate clocks to the CCD the Video output of the CCD and the pixel rate clocks to the AFE VOUT_CCD RESET_CCD H2A_ CCD J Tpix H1A_CCD SHP SHD DATACLK lt gt lt Tshp gt lt Tshd Figure 13 Horizontal Timing Binning Mode Horizon
16. e the Electronic Shutter pulse occurs during the previous frame readout The line number Table 14 REGISTER 4 DEFAULT SETTING Pom 7 Frame Flush values are chosen to allow integration times adjustable in increments of one eighth the Frame or Flush time If the line number is greater than the number of lines specified in a Frame Table Register 8 the Electronic Shutter will not occur This is the method used to turn the Shutter off in this case the integration time is controlled by a counter in the Altera PLD See Table 25 Free Running Mode Integrate Start Pulse Line Number 0 12 2040 Default No Pulse 966 See Table 25 2040 No Pulse Register 5 Signal Polarity The default settings written to Register 5 depend on the position of SWO on the Timing Board used to select between 1 channel and 2 channel operation Table 15 REGISTER 5 DEFAULT SETTING Register Entry 1 channel 2 channel Evaluation Board Signal Name H6_IDLE_VAL 0 0 Not Used Not Used x nEw o r e DATACLK2_IDLE_VAL ADCLK to AFEs DATACLK to Framegrabber CLPOB_IDLE_VAL CLPOB CLPDM_IDLE_VAL CLPDM AMP_ENABLE_IDLE_VAL 0 0 AMP_ENABLE FRAME_VALID_IDLE_VAL 0 0 FRAME_VALID LINE_VALID_IDLE_VAL 0 0 LINE_VALID INTEGRATE_START_IDLE_VAL p o f INTG_START VES Not Used http onsemi com EVBUM2276 D Table 15 REGISTER 5 DEFAULT SETTING continued
17. il orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2276 D
18. oard Kit user to operate the CCD image sensor with minimal KSC 1000 Default Initialization I intervention and no programming The default settings are Upon power up or when the BOARD RESET button is chosen to comply with the CCD device specification See pressed the Alter a PLD programis the registers of the References The registers line tables and frame tables KSC 1000 chip on the AFE Timing Generator Board to described in this document also serve as examples for those their default settings via the 3 wire serial interface who wish to create their own KSC 1000 timing http onsemi com 2 EVBUM2276 D SLOAD_TG Dummy Bits Figure 3 KSC 1000 Initialization Timing The data for each KSC 1000 register is formatted into bytes of data as shown in Figure 3 The Read Write bit is always low and the Address bits specify the register being programmed as shown in Table 3 Each byte is read into an 8 bit shift register and is shifted out of the PLD as a serial stream of eight bits The last byte of data sent to a particular Table 3 KSC 1000 REGISTERS Register Address Register Description Data Bits 2 General Control register may need to be padded with extra dummy bits the SLOAD_TG signal is brought HIGH at the appropriate time so that the correct number of bits are streamed into each register and the extra bits are ignored Each register in the KSC 1000 is programmed in this fashion until the entire device is prog
19. or Table 4 ALTERA INPUTS The KSC 1000 outputs are monitored by the PLD to control auxiliary timing functions and keep the KSC 1000 and Altera PLD synchronized The remote digital inputs DIO 15 0 are optional and are not required for KAI 2093 operation but may be used to control integration time and remote triggering Binning Mode HIGH 2 x 2 Binning Single Output LOW No Binning s s s W Ww W W Not Used W W W 0 1 2 3 SW4 Not Used 5 Not Used 6 7 6 swe We Sc Cantor HGH Voor LOW Vom SDATA_INPUT 3 wire Serial Interface DATA Signal Input SCLOCK_INPUT 3 wire Serial Interface CLOCK Signal Input LINE_VALID Used to Monitor KSC 1000 FRAME_VALID Used to Monitor KSC 1000 AUX_SHUT Not Used for KAI 2093 Operation INTG_START Used to Monitor KSC 1000 http onsemi com 4 EVBUM2276 D Outputs The Altera PLD outputs include the 3 wire serial synchronization the PLD 2 0 signals which are auxiliary interface control signals to the KSC 1000 Imager Board control bits and the GIO 2 0 bits which are the INTEGRATE signal used for external monitoring and used for PLD monitoring and testing Table 5 ALTERA OUTPUTS Not Used for KAI 2093 Operation Not Used for KAI 2093 Operation GIOf 2 0 Not Used for KAI 2093 Operation SLOAD_AFE_2 Serial Load Enable Ch2 AD9840A AFE SLOAD_TG Serial Load Enable KSC 1000 SDATA 3 wire Serial Interface DATA
20. or Free Running References for details of the KSC 1000 registers Single Channel and Dual Channel modes and Frame Table 1 is used for Single Channel 2x2 Binning mode The default setting depends on the position of SW2 Table 10 REGISTER 0 DEFAULT SETTING Register Entry Data Normal Mode Data Binning 2x2 Register 1 General Setup The default settings written to Register 1 depend on the position of SWO on the Timing Board used to select between 1 channel and 2 channel operation Table 11 REGISTER 1 DEFAULT SETTING The vaigPatsano ray s s j O Sd CLPOB1_ Pix Start 0 12 1982 1000 CLPOB1_Pix_End 0 12 1992 1004 x o 5 C eeoa I S n j XE x O 5 x Gippo CP o j 12 CLPDM2_Pix_Start 0 12 _Start 2 0 1 1 1 1 1 http onsemi com 7 EVBUM2276 D Table 11 REGISTER 1 DEFAULT SETTING continued Register Entry Data 1 channel Data 2 channel DATACLK1_Enable DATACLK2_Enable 1 1 PIXCLK_Enable H3_ Enable H1_Enable H2_Enable RG 24 mA Output Enable SH2 24 mA Output Enable SH4 24 mA Output Enable DATACLK1 24 mA Output Enable DATACLK2 24 mA Output Enable H2 24 mA Output Enable SH1 24 mA Output Enable Register 2 General Control Register 2 controls the Power Management and Operation state of the KSC 1000 The Low Power Mode is not used on the KAI 2093 so this bit is always LOW The Memo
21. rammed 3 02 2 30 13 4 INTG_STRT Line 6 7 65 8 Frame Table Access Variable 9 Line Table Access Variable PLD State Machine The Altera PLD contains a State Machine that parallels the operation of the KSC 1000 The PLD controls the KSC 1000 through the VD_TG output and monitors several of the KSC 1000 outputs enabling it to track and control the operation of the Timing Generator Remote Board Reset The DIO14 input is used as a remote Board Reset control line The Altera PLD monitors this input and when DIO14 goes HIGH the ARSTZ active low output to the KSC 1000 is asserted disabling and clearing the timing generator When DIO14 goes LOW the ARSTZ output is de asserted and the Power up Board Reset initialization sequence is executed This allows programmable control of the timing sequences to change the Electronic Shutter position for example Integration Clock The Altera PLD uses the System Clock and an internal counter to generate a 1 0 ms period clock This clock is used to generate an internal delay after power up or Board Reset It may also be used to control precise integration times for the image sensor Output Channel Control PLD input SWO is used to select one of the supported operation modes Full Field Single Output and Full Field Dual Output When making a change to the switch settings the user must initiate a Board Reset for the change to take http onsemi com 3
22. register V1 and V2 are asserted with overlap adjustability clocking interval is followed by the Horizontal clocks to compensate for the clock driver rise and fall times Charge which shift one line out through the output amplifier s VMID not to scale Figure 4 Line Table 0 Default Timing Line Table 1 Diode Transfer into the vertical CCD registers The V1 and V2 clocks have Line Table 1 is the Photodiode Transfer timing in which overlap adjustability to compensate for the clock driver rise the V2 clock 3 level shifts charge from all the photodiodes and fall times VMID LT1 Entry Pix Counts Symbol not to scale Figure 5 Line Table 1 Default Timing http onsemi com 14 EVBUM2276 D Line Table 2 Integration clocks are running continuously This sequence runs until Line Table 2 is the Integration timing sequence during Integration is complete signaled by the assertion of the which the Vertical clocks are inactive and the Horizontal VD_TG signal from the Altera PLD VMID V1_CCD Vclks not active V2_CCD VLOW k ee HCLK_ENABLE i H1A_CCD 1 H2A_CCD LT2enty 0 Pix Counts not to scale Figure 6 Line Table 2 Default Timing Line Table 3 Binning Mode Line Transfer This effectively sums two pixels worth of charge into each Line Table 3 is the Binning Mode Line Transfer sequence Horizontal CCD pixel After the binning line transfer during which the Vertical clocks are asserted t
23. ry Table Mode bit is used to halt execution of the KSC 1000 timing sequences and to enable programming of Table 12 REGISTER 2 SETTINGS the registers The KSC 1000 Initialization sequence begins with setting the Memory Table Mode bit in Register 2 to Program Mode and ends by setting the bit to Execution Mode See the KSC 1000 Device Specification References for more details Register Entry Program Mode Execution Mode Register 3 INTG_START Setup The default settings written to Register 3 establish the setup pulsewidth and hold timing of the Electronic Shutter pulse The Shutter Pulse may occur on a particular line as controlled by Register 4 or may be asserted by setting the Table 13 REGISTER 3 DEFAULT SETTING Force INTG_STRT bit in the Frame Table Register 8 In either case the Electronic Shutter Pulse occurs before the vertical clocking interval of the Frame Table entry Figure 12 Register Entry Data Electronic Shutter Setup Clocks 0 9 60 Electronic Shutter Hold Clocks 0 9 64 http onsemi com EVBUM2276 D Register 4 INTG_START Line Short integration times may be controlled through use of the Electronic Shutter The default setting written to Register 4 controls the line number on which the Electronic Shutter will occur The DIO 11 7 inputs are used to control the Integration time by selecting pre programmed line numbers as shown in Table 14 In Free Running Mod
24. st DIO14 is toggled the Altera PLD is internally reset When this occurs state machines in the PLD will first serially load the initial default values into the AFE registers and will then load the KSC 1000 frame tables line tables and registers Upon completion the KSC 1000 will be ready to proceed according to its programmed configuration In the background the Altera PLD monitors the activity of the 3 wire Serial Interface and monitors and interacts with the KSC 1000 AFE Register Default Settings On power up or board reset the AFE registers are programmed to the default levels shown in Table 9 See the AD9840A specifications References for details of the AFE registers http onsemi com 6 EVBUM2276 D Table 9 DEFAULT AD9840A AFE REGISTER PROGRAMMING Register Value Address Description decimal Operation 28 VGA Gain KAI 2093 Corresponds to a VGA Stage Gain of 9 9 dB CDS Gain Enabled Corresponds to a CDS Stage Gain of 0 0 dB w The Output of the AD9840A will be Clamped to Code 96 during the CLPOB Period KSC 1000 Timing Generator Default Settings Register 0 Frame Table Pointer On power up or board reset The KSC 1000 is RegisterO contains the Frame Table Pointer which programmed to the default settings as detailed in Table 10 instructs the KSC 1000 to perform the timing sequence through Table 24 See the KSC 1000 Device Specification defined in that table Frame Table 0 is used f
25. stream depends on the device being addressed with the Device Select bits For the KSC 1000 device they are Register address bits A 0 3 LSB first For the AD9840A AFE they are Register Address bits A 0 2 LSB first followed by a Test bit which is always set LOW AFE Default Initialization Upon power up or when the BOARD_RESET button is pressed the PLD programs the registers of the two AFE chips on the Timing Generator Board to their default settings via the 3 wire serial interface See Table 9 for details The AD9840A AFE must be reprogrammed on power up as it does not retain register settings when power is removed DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 SLOAD_AFE_x Figure 2 AFE Initialization Timing The data for each AFE register is formatted into two bytes The default settings are selected by the user through the PLD of data as shown in Figure The Read Write bit is always inputs SW 7 0 and DIO 15 0 See Table 10 through low and the Address bits specify the register being Table 24 for details The KSC 1000 must be programmed as shown in Table 9 Each byte is read into an reprogrammed on power up as it does not retain register 8 bit shift register and is shifted out as a serial stream of settings when power is removed eight bits Each register in the AFE is programmed in this The KSC 1000 default settings automatically fashion until the entire AFE is programmed programmed by the PLD allow the Evaluation B
26. tal Timing In order to sum the charge from two Horizontal CCD pixels into one the Reset clock is suspended on alternating Horizontal clock cycles In this way two pixels of charge are dumped onto the floating diffusion of the output amplifier before this node is reset to VRD the Reset Drain voltage See the KAI 2093 Device Specification References for further details In order to correctly convert the output amplifier voltage to digital data the AFE clocks must be adjusted accordingly The Clamp pulse SHP samples the output after the Reset pulse has been issued but before the Horizontal clocks have moved charge onto the floating diffusion The Sample pulse SHD samples the output after two Horizontal clock cycles have moved two charge packets onto the floating diffusion The DATACLK then clocks the AFE to perform the conversion The KSC 1000 has the capability of implementing the Horizontal Timing necessary to bin up to four pixels This feature is controlled by setting bits 3 4 of the active Frame Table Register 8 in the KSC 1000 Figure 14 depicts the basic theoretical relationship between the pixel rate clocks to the CCD the Video output of the CCD and the pixel rate clocks to the AFE in 2x Horizontal Binning Mode http onsemi com 18 EVBUM2276 D The Altera PLD default KSC 1000 settings contain 2x2 Binning Mode timing in Frame Table 2 See Figure 11 In order to activate the 2x2 Binning Mode the Frame Table
27. terface enters the Timing Board through the DIO Interface connector and is routed to the Table 2 SERIAL INPUT DEVICE SELECT PLD The Altera PLD decodes the addressing of the serial input and steers the datastream to the correct device The serial input must be formatted so that the Altera PLD can correctly decode and steer the data to the correct device The serial interface can be used to dynamically change the operating conditions of the AFE or KSC 1000 chips by reprogramming the appropriate registers Reprogramming these registers through the serial interface will have no effect on the default settings that are automatically programmed into these devices on power up or board reset oe mm 0 101 110 1 Semiconductor Components Industries LLC 2014 1 October 2014 Rev 2 1 Publication Order Number EVBUM2276 D EVBUM2276 D SLOAD_INPUT SLOAD_xxx decoded PLD output i SDATA_INPUT SCLK_INPUT Figure 1 Serial Input Timing The first 3 bits in the datastream are the Device Select bits The remaining bits in the bitstream are Data bits LSB DS 2 0 sent MSB first as shown in Figure 1 The Device first with as many bits as are required to fill the appropriate Select bits are decoded as shown in Table 2 register The next bit in the datastream is the Read Write bit R W Only writing is supported therefore this bit is always LOW The definition of next four bits in the data
28. to 2040 the Shutter is never pulsed as this value exceeds the number of lines in a frame Figure 16 and Figure 18 Either the BOARD RESET switch must be pressed or the Remote Reset DIO14 must be toggled after changing the DIO 11 7 bits in order for the change to the KSC 1000 to take effect The Integration time is controlled by the Altera PLD In Free Running mode the KSC 1000 waits for a trigger signal VD_TG before beginning the Diode Transfer sequence See Figure 16 The Altera PLD issues this trigger pulse when the Integration Counter has reached a pre programmed value as shown in Table 25 The Integration counter is clocked by an internally generated 1 ms clock The default value of 0 means that the VD_TG trigger is issued on the next rising edge of the 1 ms clock after the frame readout is complete A value greater than 0 adds that many milliseconds to the Integration Time allowing Integration times greater than 8 seconds Figure 18 http onsemi com 19 EVBUM2276 D Table 25 PROGRAMMED INTEGRATION TIMES Int Count Free Run Mode Reg4 Entry N oa Ol N 276 138 No Shutter No Shutter No Shutter No Shutte No Shutter ss s s No Shutter No Shutte No Shutter 0 130 0 160 0 260 ajla e a a a N ee Se LE Se sss ae eee 5657 0 0 0 0 Gw mami No Shutter iy fo ee So No Shutter A No Shutter a fo
29. wice per line the Horizontal clocks are run in Binning Mode VMID V1_CCD VLON I VMI i v2_CCD VOW HCLK_ENABLE i _ i i H1A_CCD 1 1 1 oa H2A_CCD Di 2 tat ES not to scale Figure 7 Line Table 3 Default Timing Line Table 4 Trigger Hold Line Table 4 is a sequence one pixel time in length used PLD Neither the Vertical clocks nor the Horizontal Clocks when the KSC 1000 is waiting to be triggered by the Altera are active during this sequence VMID V1_CCD V2CCD Vclks not active I i VLOW i HCLK ENABLE Low I i HMID I HIACCD Hclks not active H2A CCD HLOW not to scale Figure 8 Line Table 4 Default Timing http onsemi com 15 Frame Table 0 Sequence Frame Table 0 contains the Free Running video mode timing sequence used to continuously read out all rows of the CCD The sequence begins with the Line Transfer sequence followed by the Timed Integration sequence When V_TRANSFER TIMED_ INTEGRATION DIODE_ TRANSFER EVBUM2276 D integration is complete the Altera PLD asserts the VD_TG signal to the KSC 1000 This initiates the Photodiode transfer and the cycle repeats with the next Line Transfer sequence Altera PLD KSC 1000TG State Machine Sequence Frame Table 0 Sequence ENTRY 0 1 Execute LTO Wait for FRAME_VALID
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