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HSP50215EVAL User Guide

1. 5 ES 5 25 o C2 5 lt C2 4 9 10771024 016 1 32 aids mH 16 A15 35 2 14 Z 14 2 5 ADT 51212 VE FE 2 6 81 AZ amp A2 7 AG AD 8 ADM A2 9 2 2 G 5 EE A2 0 c2 15 Q C2 8 C2 14 22 0 c2 13 1 C2 10 C2 12 5 11 10771024 5 121652 C2 0 15 lt V 3 24 intersil HSP50215EVAL Appendix E Detailed Schematics continued CHANNEL 3 COMPOSITE IF OUTPUT SIGNAL TO U3 PAGE 3 5 OEPULLUP 2 383 OF CHANNEL 3 HSP50215 MODULATOR Sag 2995835332935 INPUT C2 0 15 BUS 1 vroneropnpunrseptsePr 20 zjom 55552554842452348444 3 ne2 0000500 5 5 79 FX CASZ 2 3 7817 X wm 5 CASZ bag OUT 5 CASO 14 75 pa ci H3 E g 5407 NC74 3 X CAS2 VCC73 175 mu e 79 CAS3 C12 5i 7 ASA Cio LIO C210 ERES x 11
2. OEPULLUP 1 ACTELEN 1 CSEL2 1 vec CSEL1 1 CSELO 1 FIFOTP 1 2 HEADER 8X2 U13 oro 1 Ai 16 Net eu A16 Als 1 5 14 cs2 17 12 WE Ai_6 6 A13 175 gt 46 1_4 5 g 4 Ait Al_2 10 OE ATA 17 2 A10 9 ATO 12 csi m 9 cia 15 0 gi d 14 YOO te 195 E E 38 02 1 04 Ces E GND 1 03 71024 7 gt o A1 18 NC 517 4 M Al 14 73 16 A15 35 ALT tdi 1 E A17 ME 28 ut A1 6 ___ ra prar Att 5 ALS 7 K a a 55 AS 5 25 11 8 173 97 4 Alt 57 1 AL MEAN Qu cA o2 TT 1 AT 0 i I 651 57 TE 13 0 55 guis q7 X eic 05 o 22 16 Vos 7 Cio Q 6 i Q 1 0 15 3 22 intersil HSP50215EVAL 4TH STAGE COMPOSITE IF OUTPUT SIGNAL 4 OUT1 0 15 TO U2 PAGE 2 SOC rele
3. 2 42 22 2 2 3 38 FIGURE 10 RRC2A4X IMP FREQUENCY RESPONSE 14 2 3 38 FIGURE 11 GS5T16X IMP FREQUENCY 11 1 1 1 5 142 1 3 39 FIGURE 12 S95MOD IMP FREQUENCY RESPONSE 11 1 2 3 39 FIGURE 13 AMPS2 IMP FREQUENCY 41 14 3 40 FIGURE 14 RRC35A4X IMP FREQUENCY RESPONSE 1 21 2 22 2 3 40 FIGURE 15 GP1 IMP FREQUENCY 1 4 2 4 3 41 FIGURE 16 GP2 IMP FREQUENCY 1 11 14 3 41 Example Stimulus Files reta I eurer p eub Le eec Solas Se der era ere efe dt 3 42 Appendix Detailed Menu Item Descriptions 3 43 3 2 intersil HSP50215EVAL Control Software Program The control software program written for DOS based PC s is included in the evaluation kit This software supports operation of the evaluation circuit board in basic quadrature ASK and FM modulation configurations The control software MAIN MENU offers six submenus for various confi
4. PARAMETER VALUE Taps 128 8xFsamp IP DS 8 16 3dB BW 70 225 x FSAMP 13 5kHz Fgamp 60kHz DC Gain 0 500 6 02dB Peak Coef Value 0 244 Maximum Output 0 728 2 76dB NBW 0 456 x double sided Description Post modulation filter for AMPS type FM signals Signals With Fsamp 60kHz response is gt 36dB down at 20kHz and gt 70dB down for frequencies gt 23kHz Passband ripple is 0 5dB peak to peak Frequency Response DC to of the Shaping FIR Filter 0 10 EM 20 30 al 40 __ 50 XS 60 70 80 90 100 oo FIGURE 13 AMPS2 IMP FREQUENCY RESPONSE PARAMETER VALUE Taps 32 IP DS 4 8 3dB BW 0 5 x FSAMP DC Gain 0 50 6dB Peak Coef Value 0 610 Maximum Output 0 757 2 41dB NBW 0 989 x double sided Description Square root of raised cosine filter for higher rate to 1 5 Mbaud Satcom type signals Frequency Response DC to of the Shaping FIR Filter 0 4 10 20 30 4 40 50 A 32 60 70 80 90 E 100 4 112 128 4 144 160 224 240 FIGURE 14 RRC35A4X IMP FREQUEN
5. PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 OUT4_1 2ND TO LSB OF OUTPUT OF 2 OPOUT1 OUTPUT LSB 1 CHANNEL 1 OUTPUT 3 OUT4_0 LSB OF OUTPUT OF CHANNEL Q 4 OPOUTO OUTPUT LSB OUTPUT 5 CASSYNC OFF BOARD J1 SYNC DRIVER 6 OPCASSYNC CASCADE SYNC OUTPUT ON INPUT AND SYNCIN SYNCOUT OUTPUT CONNECTOR J2 JUMPER POINTS 7 SYNCIN HSP50215 SYNCIN INPUT FOR 8 U11 11 AND JP5 8 OFF BOARD J1 SYNC DRIVER CHANNELS 1 2 3 AND 4 10 INPUT AND SYNCIN SYNCOUT JUMPER POINTS 9 SYNCOUT SYNCOUT OUTPUT FROM CHAN 10 U11 2 4 6 8 OFF BOARD J1 SYNC DRIVER NEL 1 HSP50215 AS SOURCE FOR INPUT AND SYNCIN SYNCOUT SYNC SIGNAL JUMPER POINTS JP6 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 GND CHIPSELECT 2 GROUND CHIPSELECT HARDWIRE ZERO 3 GND UNUSED 4 GROUND UNUSED 5 GND PULLUP AND ISA CARD 6 GROUND CARD ADDRESS HARDWIRE ADDRESS DECODE BIT 9 MSB ZERO 7 GND PULLUP AND ISA CARD 8 GROUND CARD ADDRESS HARDWIRE ADDRESS DECODE BIT 8 ZERO 9 GND PULLUP AND ISA CARD 10 GROUND CARD ADDRESS HARDWIRE ADDRESS DECODE BIT 7 ZERO 11 GND PULLUP AND ISA CARD 12 GROUND CARD ADDRESS HARDWIRE ADDRESS DECODE BIT 6 ZERO 13 GND PULLUP AND ISA CARD 14 GROUND CARD ADDRESS HARDWIRE ADDRESSDECODE BIT 5 ZERO 15 GND PULLUP AND ISA CARD 16 GROUND CARD ADDRESS HARDWIRE ADDRESS DECODE BIT 4 ZERO 17 GND PULLUP AND ISA CARD 18 GROUND CARD ADDRESS HARDWIRE ADDRESS DECODE ENABLE BIT ZERO 19 GND ISA CARD DECODE 20 U23 4 5 9 AND 12 ENABLE FOR ISABUS READ
6. Channel 1 Channel 2 Channel 3 Channel 4 6 5kHz sine waves Filter file RRC35A4X RRC35A4X RRC35A4X RRC35A4 x EX07FM EXAMPLE CONFIGURATION FILE IP DS 4 8 4 8 4 8 4 8 Channel 1 Channel 2 Channel 3 Channel 4 Center Fre 4000000 4360000 4720000 5080000 NTN quency IP DS 8 16 8 16 8 16 8 16 Input 256000 256000 256000 256000 Center 4000000 4120000 4240000 4480000 Sample Frequency Rate Input 60000 60000 60000 60000 Stimulus QPSKPN QPSKPN QPSKPN QPSKPN Sample File Rate Stimulus FM1K8K FM1K7K FM1K6K FM1K8K File 3 36 intersil HSP50215EVAL File Name EX08FSK Description This file is similar to EXO7FM but with different stimulus patterns Channel 1 is modulated with a 10 kbps Manchester encoded length 511 PN sequence at a deviation of 8kHz Channel 2 through 4 are 1kHz sine waves with deviations of 3 4 and 5kHz respectively EX08FSK EXAMPLE CONFIGURATION FILE Channel 1 Channel 2 Channel 3 Channel 4 Filter file AMPS2 AMPS2 AMPS2 AMPS2 IP DS 8 16 8 16 8 16 8 16 Center 4000000 4120000 4240000 4480000 Frequency Input Sam 60000 60000 60000 60000 ple Rate Stimulus FSKPN FM1K3K FM1K4K FM1K5K File File 09 Description This is an example of multi tone modulation Each channel modulates 7 tones onto its carrier 8 slots 1 unoccupied The tone spacing is 16kHz With all channels enabled there is a total of 28
7. d o 240 g st N N 208 CQ sf C CN TNT ORM v7 v File name BYPASS IMP PARAMETER VALUE Taps 16 4xFsamp IP DS 4 4 3dB BW N A DC Gain 32767 32768 0 00027dBFS Peak Coef Value 32767 32768 Maximum Output 32767 32768 0 00027dBFS NBW N A Description Shaping filter bypass mode Input samples are scaled by 32767 32768 and repeated for one input sample time four shaping filter output cycles Use for evaluating carrier NCO purity as AM from the filtering is produced Frequency Response Sin X X with nulls aligned with the interpolation filter nulls 3 41 intersil HSP50215EVAL Example Stimulus Files When the program loads stimulus vectors it first counts the sample pairs to calculate the first RAM address for loading It then reads in the data and writes it to the pattern RAM The maximum number of sample pairs is 65536 the RAM holds up to 128kwords File Name BPSKPN IMP Samples 511 Description Stimulus file for BPSK modulation PN sequence Same data on I and Vector Length 1 0 0 dBFS 0 7071 on I and File Name QPSKPN IMP 3t Samples 511 Description Stimulus file for QPSK modulation PN sequence Same sequence on and Q offset by 64 samples Vector Length 1 0 0 dBFS 0 7071 on and File Name 16QAMPN IMP Samples 511 Description Stimulus file for 16 QAM modulation
8. 1 0 3 6 FIGURE 6 MODULATOR CHANNEL CONFIGURATION SUBMENU 1 4 4 3 6 FIGURE 7 BOARD INTERFACE 1 5 2 2 2 2 3 6 FIGURE 8 CONFIGURE CHANNEL 1 1 1 2 4 3 6 Learning Your Way Around s iope seca neadi onare inad Ea eee te AG RR YR RR RR EE Y REA Pd SEE 3 7 Exercise 1 Generating CW Tone 2 3 7 Exercise 2 Adjusting the level of the CW 1 22 3 8 Exercise 3 Modulating the CW Tone with PN Data 3 8 Exercise 4 CW a Modulated 2 3 9 Exercise 5 A Fourier Series Composite 3 9 Exercise 6 Generating Additive White Gaussian Noise AWGN 1 4 3 9 Background on Eb No and SNR Calculations 2 4 1 2 2 3 10 An Example Eb No Calculation A rc ee wn ieee M DUE SE MGS ae eth 3 11 Exeicise 47 PRBS D ta oc ons
9. NBW 0 53 x FsAMP double sided Description Gaussian filter for GSM GMSk BT 0 3 Filter must be stimulated with 0 03125 for proper spectrum Frequency Response into FM Modulator DC to Four 2 of the Pre modulation Shaping FIR Filter 10 20 4 30 40 50 60 70 80 90 100 112 128 gt 144 160 FIGURE 11 GS5T16X IMP FREQUENCY RESPONSE File name S95MOD IMP PARAMETER VALUE Taps 48 xFsamp IP DS 4 12 3dB BW Approx 0 5 x FSAMP DC Gain 0 543 5 3dB Peak Coef Value 0 498 Maximum Output 1 05 0 42dB NBW 1 012xFsAMp double sided Description Filter coefficients from IS95 Specification rounded and then scaled to minimize AM Frequency Response DC to Foyrt 2 of the Shaping FIR Filter 10 20 30 40 50 60 70 80 90 100 DON x rrr Tr TN CN CN FIGURE 12 S95MOD IMP FREQUENCY RESPONSE 3 39 intersil HSP50215EVAL File name AMPS2 IMP File name RRC35A4X IMP
10. HSP50215EVAL Appendix G Descriptive File List PC PROGRAM FILE DESCRIPTION HSP50215 EXE HSP50215EVAL CONTROL SOFTWARE PROGRAM MISCELLANEOUS FILE DESCRIPTION EXxxname CFG EXAMPLE CONFIGURATION FILES filename IMP REFERENCE EXAMPLE FILTER FILES filename IMP REFERENCE EXAMPLE STIMULUS FILES Example Configuration Files The example configuration files are located in the EXAMPLES subdirectory Load the desired example configuration file using menu item 5 in the main menu The naming convention for the example configuration files is EX XX NAME FE FILE NAME EXAMPLE NUMBER EXAMPLE CONFIGURATION FILE File Name EXO1QPSK Description This example illustrates high dynamic range QPSK modulation It is similar to 15136 but with a continuous 511 sample long PN sequence and QPSK modulation instead of Pi 4DQPSK modulated in bursts The filter is a square root of raised cosine with a 0 35 The channel spacing is 120kHz with one unoccupied channel With the supplied 50MHz oscillator the maximum input sample rate supported by this File Name EXO2GMSK Description This is an example of GMSK using the FM with pre filter The BT product is 0 3 GSM The input sample rate is 270 833kHz The data is a 511 sample PN The PN codes for channels 2 and 4 are pre coded to give the proper data when demodulated as OQPSK at 135 417 kbaud When using this configuration with bursts for GSM it do
11. 22 co as N 35 95028 EN 28 30 29 sr LAM C4 1 31 51 56 cao 32 31 TEN Tao N M V 5 GND gt o 442 23992993 ge 33333333 agados 2 a i is ne he 9 J3 TLL 94 ze 43343383 Ol ACTELEN 4 3 28 intersil HSP50215EVAL RSIP 10 RZ6 OEPULLUP 4 FROM U4 RESETS CSEL2 4 ACTELEN 4 QFMT 4 CEPULLUP 4 GND CHANNEL 1 COMPOSITE IF OUTPUT SIGNAL 4 FROM U4 when sending data to HSP50214 ON ST 114 JP4 HEADER 10X2 1 2 and 3 4 enables lower two bit outputs to header Disable CASSYNC signal can come in from the output header SYNCIN connected by 5 6 or from the last HSP50215 SYNCOUT connected by 7 8 and 9 10 OPCASSYNC JP5 HEADER 5X2 CASSYNC J6 SMA SMACUK U19 S 32 NC we Be M Cem 3 GNO ve A HEADER
12. 3 24 5 GND ajal anaes 40 ACTELEN 2 lt OUT2 10 15 SYNCIN A MASTERCLR STAT 27 7 3 25 intersil HSP50215EVAL Appendix E Detailed Schematics continued CHANNEL 2 CASCADE INPUT IS CHANNEL 3 MODULATOR OUTPUT OUT2 0 15 gt vcc RSIP 1G 1 RZ FROM U2 PAGE 2 un 9 CEPULLUP 3 TO U3 OEPULLUP 3 ACTELEN 3 i CSELS 3 NC CSEL2 3 vec lt 3 CSELO 3 FIFOTP JP3 SND HEADER 8X2 GND 54 HH Nc vee A3 16 35 PUES 3 18 A15 2 7 14 CS2 54412 1 AD 6 61 AB Fo 71 AG AB AS A9 4 8 11 971 4 A11 2377 10 un ii 2 A10 aen 157 csi ax c3 0 13 10 Vor 8 TEES q4 O0 Bane 157 Vet 105 IE E 18 02 104 C33 GND Vos 10771024 NC 8 I 16 A15 A3 14 3 2532 iau 52 TED A12 WE ALI A13 Anii 5 lis AB 8 A3 5 7 5 NI A9 9 4 5 AA AM 2 10 GE ES 1 11 AU 33 cst 3 0 VO c3 8 13 C3 14 VOO vos rS CAD 75 1 05 FEE i16 02 O4 ET GND 103 10721024 p irse C3 0 151 3 26
13. An example of the IMP file format is shown below FILTER FOR IS 136 WAVEFORMS ROOT RAISED COSINE ALPHA 0 35 256 TAPS 16X BAUD DC GAIN 0 658 3 64dBFS PEAK COEF 0 721 MAXIMUM OUTPUT 1 054 0 4dB C 2 256 Filter file GP2 GP2 GP2 GP2 IP DS 16 16 16 16 16 16 16 16 Center 4000000 4128000 4256000 4384000 Frequency Input Sam 192000 192000 192000 192000 ple Rate Stimulus MTONE1 MTONE1 MTONE1 MTONE1 File File Name EXxxNAME Description This is a blank table for your own example configuration files EX EXAMPLE CONFIGURATION FILE Channel 1 Channel 2 Channel 3 Channel 4 Filter file 0 000213623 0 000213623 0 000671387 0 000671387 0 000640869 0 000640869 6 10352E 05 6 10352E 05 0 000640869 0 001312256 0 001922607 0 002410889 0 002746582 0 002929688 0 00289917 0 002685547 0 000640869 0 001312256 0 001922607 0 002410889 0 002746582 0 002929688 0 00289917 0 002685547 IP DS Center Frequency Input Sam ple Rate Stimulus File When loading filter coefficients the program will report an error if the number of samples exceeds the number allowed for the selected IP value 3 37 intersil HSP50215EVAL File name IS136B IMP PARAMETER VALUE TAPS 256 16XFsAMP DS 16 16 3dB BW 0 5 x FSAMP DC Gain 0 658 3 64dBFS Peak Coef Value 0 72114562 M
14. INITIAL JUMPER SETTINGS LOCATION SETTING J1 3 4 J1 5 6 J1 7 8 J1 9 10 J1 11 12 J1 13 14 J1 15 16 J1 17 18 J1 23 24 J1 25 26 J1 27 28 J1 29 30 J1 31 32 J1 33 34 J1 35 36 J1 37 38 The J1 jumpers are installed to terminate the Channel 4 cascade input which is unused in the standard configuration JP1 5 6 JP1 9 10 JP1 11 12 JP1 13 14 The JP1 jumpers set the control signals such as chip enables out put enables and chip select controls for the ACTEL and HSP50215 for Channel 4 JP6 9 10 JP6 11 12 JP6 13 14 JP6 15 16 JP6 17 18 JP6 19 20 The JP6 jumpers set the card address to 110000 and connecting the card decode to the board circuitry JP7 2 3 JP7 sets the clocking configuration to be from the on board crystal oscillator JP8 1 2 JP8 3 4 The JP8 jumpers connect the selected clock to the on board clock drivers and connect one driver output to the output connector J2 JP9 1 2 JP2 1 2 JP2 5 6 JP2 9 10 JP2 11 12 JP2 13 14 The JP2 jumpers set the control signals such as chip enables out put enables and chip select controls for the ACTEL and HSP50215 for Channel 3 JP9 5 6 The JP9 jumpers set the control to be from the ISAbus rather than from the parallel port interface JP10 1 2 The JP10 jumper terminates an external clock input in 500 While this jumper is set no external clock is used in the standard config uration
15. 2 The standard deviation of the and Q components of the noise pattern vector 3 The DC gains of the data and noise filters 4 The input sample rates for the data and noise modulators it is assumed that the noise sample rate is higher than the data sample rate 5 The noise bandwidth of the noise filters 6 The multiplier settings for the gain in the modulators Items 1 through 5 are listed in the headers of the file or in the control software menus Item 6 can be obtained from the computed register values found in the 1 2 3 and 4 files Background on Eb No and SNR Calculations The signal to noise ratio C N is equal to 1010 2 262 where o is the standard deviation of the and Q noise vectors they are equal and A is the average length of the vector The length of the vector in the stimulus file is modified by the gain of the shaping filter and the gain of the programmable attenuator in the HSP50215 The standard deviation of the noise vector is likewise modified by the gains of the filter and the attenuator After obtaining C N conversion to Eb No is done by normalizing for the data rate NBW of the noise filter and the modulation type as follows Ep Ng C N ModFactor 10LOG symbol rate 10LOG NBW where NBW is the double sided noise bandwidth of the noise filter 3 10 intersil HSP50215EVAL Adding the log of the noise bandwidth converts from C N to C No Subtracti
16. 4 4 3 13 Non ISA PG installed Operation s ar Ch Bob eee ee Sok erre eR p ee dir greet Perd Mur sui 3 13 Direct Modulator Controls os ences AE eae dae UN eb epe nda 3 14 Using SERINADE Designed Filters Lee tr RR nre 3 14 Appendix Circuit Board Layout 3 14 Appendix B Initial Jumper 06 2 4 3 15 Appendix C Connector Pin 2 3 17 Appendix D Test Header Pin 3 19 Appendix E Detailed 1 1 3 22 Appendix F Parts List doe eret Pt e a e RE ea Ax kaker o rece STAT e VEE wee 3 34 Appendix Descriptive File 164 1 4 2 3 35 Example Configuration Files cessit ga le daa 3 35 Example Filter Files Rel ete fa alk nt ack 3 37 FIGURE 9 5136 FREQUENCY
17. O Returns to main menu Select Item 3 and set the following parameters 8 511 9 48 O Returns to main menu Select Item 4 and set the following parameters 1 500 000Hz 2 501 000Hz 3 QASK 4 Filters oypass 8 16384 9 3 0 Returns to main menu Select main menu 7 to compute the register values Select main menu 8 to configure the board Select submenu item 5 to configure all channels Select submenu item 3 to load both the modulator and Pattern RAM When the submenu reappears the download is complete The output is a Gaussian Noise signal sampled at 351kHz and modulated to 500kHz IF On a spectrum analyzer the outline of the shaping filter is depicted On the scope a noisy signal that is 0 4Vpp is displayed Now lets add back in a modulated signal Go to the main menu Select Item 1 and set the following parameters 9 3 0 Returns to main menu Select main menu 7 to compute the register values Select main menu 8 to configure the board Select submenu item 1 to configure channel 1 Select submenu item 1 to load the modulator When the submenu reappears the download is complete The output is AWGN summed with modulated signal The final step is to determine how to set a particular Signal to Noise Ratio SNR In order to determine a C N or Ep Ng the following system information must be known 1 The vector length of the I Q data vector This is the magnitude of the input vector
18. Description Stimulus file for FM modulation FM with post modulation filtering AMPS type At 60 ksps input the modulation is a 1kHz sine wave with peak deviation of 6kHz Q samples are zeroed Vector Length Peak amplitude 8 30 0 2 13 98 dBFS File Name IMP Samples Description Vector Length dBFS on and 3 42 intersil HSP50215EVAL Appendix H Detailed Menu Descriptions Board Interface Menu Board Configuration ITEM 1 INTERFACE CURRENT VALUE 0 1 Parallel 0 ISA 1 Enter New Value Current Value ITEM 2 LPT NUMBER CURRENT VALUE Enter New Value Current Value ITEM 3 CHANNEL 1 FPGA ADDRESS CURRENT VALUE 0 to 7 Enter New Value Current Value ITEM 4 CHANNEL 2 FPGA ADDRESS CURRENT VALUE 0 to 7 Enter New Value Current Value ITEM 5 CHANNEL 3 FPGA ADDRESS CURRENT VALUE 0 to 7 Enter New Value Current Value ITEM 6 CHANNEL 4 FPGA ADDRESS CURRENT VALUE 0 to 7 Enter New Value Current Value ITEM 7 OSCILLATOR FREQUENCY 1 000Hz to 52 000 000Hz Current Value Enter New Value Current Value MODULATOR CHANNEL 1 OR 2 4 CONFIGURATION MENU ITEM 1 CARRIER CENTER FREQUENCY Range is 52 000 000Hz to 52 000 000Hz Current Value Current Value Enter New Value Current Value ITEM 2 INPUT SAMPLE RATE Range is 0 01 to 3 25e6 Current Value Current Value Enter New Value Current Value This field identifies
19. WRITE AND DATA BUS JP7 TEST HEADER PIN ASSIGNMENTS JP8 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 SMACLK J3 SMA CLOCK INPUT 1 OSCLCK SELECTED CLOCK SOURCE 2 OSCLCK CLOCK SELECTION OUTPUT 2 DU3A9 CLOCK DRIVER INPUT 3 CRYSTALCLK CRYSTAL CLOCK OUTPUT 3 J2 17 OUTPUT CONNECTOR PIN 17 4 MASTERCLK MASTER CLOCK OUTPUT 3 20 intersil HSP50215EVAL JP9 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 GND ISA INPUT ADDRESS 2 A ADDRESS 3 PARA PARALLEL INPUT ADDRESS 4 A ADDRESS 5 LIOW ISA INPUT WRITE 6 WR WRITE 7 PARWR PARALLEL INPUT WRITE 8 WR WRITE JP10 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION 1 SMACLK J3 SMA CLOCK INPUT 2 500 GND TERMINATION RESISTOR JP11 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 REGULATED 5 2V REGULATED 5 2V SOURCED 2 CARD Veg VEE FROM ISA BUS INTERFACE 3 21 intersil HSP50215EVAL CASCADE INPUT VCC 4TH MODULATOR CHANNEL CONNECTOR 40 38 mane 36 34 32 30 28 26 24 22 20 18 16 14 39 37 35 33 31 28 27 25 23 21 19 17 FROM U11 PAGE 4 gt gt CASSYNC2 J RSIP 10 FROM U11 PAGE 4 CONNINCLK CEPULLUP_1_ TO U1
20. see jumper JP7 JP11 1 2 JP3 3 4 JP3 5 6 JP3 9 10 JP3 11 12 JP3 13 14 The JP3 jumpers set the control signals such as chip enables out put enables and chip select controls for the ACTEL and HSP50215 for Channel 2 The JP11 jumper connects the 12V from the ISAbus interface which is regulated down to the 5V required for the Vgg onboard to the board Vgg runs JP4 1 2 JP4 3 4 JP4 5 6 3 15 intersil HSP50215EVAL Evaluation Board Layout Showing Jumper Configuration for Evaluation Board Layout Showing Jumper Configuration for ISAbus Configuration Parallel Bus Configuration JP6 pl 8 3 16 intersil HSP50215EVAL Appendix C Connector Pin Assignments J1 CONNECTOR PIN ASSIGNMENTS J3 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL PIN SIGNAL 1 N C 21 NC 2 GND 22 GND 3 CAS15 23 CAS7 4 GND 24 GND 5 CAS14 25 CAS6 6 GND 26 GND 7 CAS13 27 55 8 GND 28 GND 9 CAS12 29 CAS4 10 GND 30 GND 11 CAS11 81 CAS3 12 GND 32 GND 13 CAS10 33 CAS2 14 GND 34
21. ALE A3 55 X 10 5V A2 14 3MHZ A13 GND AO CON 628 V SET CARD ADDRESS TO 110000 JP6 CHIPSELECT 019 30 3 5 3 JAG U20 30 4 JAT 5 4 JAG a 6 5 7 4 1 c NA 520 RZ7 90 HEADER 10X2 RSIP 10 co co ofl A 17111714 SIN G 58888858 021 74 520 718 lt lt a 2 5 1 5 3 32 intersil HSP50215EVA L RSIP 10 91 4 AT62 072 18 PCD7 PCD7 AT62 D63 45 5547 6 PCDE 4 AT62 054 3 83 16 PCDS PCDS 5 AT62 045 B4 15 PCD4 PCD4 6 AT62 036 5 14 PCD3 PCD3 7 AT62 D27 ag 13 PCD2 PCD2 8 62 018 7 87 12 PCD1 PCD1 9 AT62 009 PCDO PCDO 15 RZ8 1 DIR RSIP 10 To 74ACT245 1 2 and 5 6 WR and A comes T from ISA slot 3 4 and 7 8 signals lt from parallel port 1 2 4 4 1 4 lt 5 6 7 8 WR d TO PAGES 1 4 lt HEADER 4X2 PC0 0 7 TO PAGES 1 4 lt 74 2 STAT U23A 5 1 4 lt 1 U23B 3 4 2 1 7 8ta 5 6 9 10 11 12 13 14 74 32 15 16 17 18 aa EET C4 U23C 21 2
22. CASI3 GND56 55 CAS14 OUTZ 15 27 jg CAS15 co H NC28 53 5 NC29 gt 52 FIN X 2 s SYNCOUT X 9 a o a 5 9 x 2 o A 9 692152212622350w 06 5 8 m 5 fey col cola of ol ao 5 e sr e t t t EE EEE E 4 SYNCIN CEPULLUP 3 FROM RZ3 _ GND EM FROM U11 PAGE 4 lt WR FROM 49 PAGE 6 FROM J9 PAGE 6 WRRAM3 OERAM 3 CSEL2 3 3 SYMBLCLK 3 3 029 STAT Str dd elo TO U24 J9 PAGE 6 dg FANE Hyer gu ecg BSSESRERGE 12 9 9 ui C338 4 H 315 1 3 SH 3 c312 17116 71 91 18117 E en 5 m E 19 ACTEL FPGA 68 z7 4 43 10 20 67 a 5 21 66 0 vera veces o ES us a 5 C38 25 3 8 25 FPGA 62 45 357 155 81 AT C34 7 436 55127 60 90028 29 c32 30 x RE csi My 26 32 o C3 0 E 31 54 0 5 59 2 gt O10 00 00 0 ay wv ON sk M ts eto 2 PCDIO 7 Lu lo FROM U24 J9 PAGE 6 x ACTELEN 3 3 27 i i intersil HSP50215EVAL ICS Continued E Detailed Schemat Appendix CASZ 4 CH
23. Channel 2 selection of the modulation type QASK bandlimited FM and shaped FM Resampler frequency IF frequency gain control as well as shaping and interpolation filter configuration JP2 and RZ2 provide control and selection for the channel 3 ACTEL FPGA and associated Digital UpConverter U15 and 16 provide the memory storage for data being processed by the ACTEL FPGA Care must be taken to ensure that the cascade input summed with the modulation output of channel two do not limit inside the digital upconverter for channel two The gain control can be used to provide sufficient back off The output of the digital upconverter for modulation channel 3 U2 is routed to the cascade input of modulation channel 2 sheet 3 U3 Modulation Channel 2 Sheet 3 of the schematic details the control and access circuitry for Modulation Channel 2 U3 is the Digital upconverter and U8 is the associated ACTEL FPGA The control software allows Modulation channel 2 selection of the modulation type QASK bandlimited FM and shaped FM Resampler frequency IF frequency gain control as well as shaping and interpolation filter configuration JP3 and RZ3 provide control and selection for the channel 2 ACTEL FPGA and associated Digital UpConverter U17 and 18 provide the memory storage for data being processed by the ACTEL FPGA Care must be taken to ensure that the cascade input summed with the modulation output of channels 4 and 3 do n
24. J3 HEADER 2 X 20 2x20 QPL SULLINS PTC20DAAN 15 10 RZ RZ10 22K RPACK TO PIN SM SIP 10 PIN SIP PANASONIC EXB H110223J 16 1 XU10 14 PIN SOCKET SOCKET QPL AUGAT 814 AG11D 17 1 U10 XTAL OSC 50MHz 14 DIP QPL CTS MX 45T 50 000 18 1 021 IC 20 SOIC NATIONAL 74 5205 19 1 023 14 SOIC Intersil 74ACT32M 20 1 U24 IC 20 SOIC Intersil 74ACT245M 21 2 011 022 20 SOIC Intersil 74ACT244M 22 1 U12 VOLT REGULATOR 5 2V TO220 NATIONAL SEMI LM29905 5 2 23 1 C6 CAPACITOR SM 0 1uF 1210 QPL PANASONIC ECH U1C104JB5 24 8 C5 61 66 69 CAPACITOR 10uF RADIAL QPL MALLORY TDC106M025NSF 25 58 C1 2 7 60 67 68 CAPACITOR SM 0 01uF 1206 QPL PANASONIC ECH U1C103JB5 26 2 R6 7 RESISTOR SM 620 1210 QPL PANASONIC ERJ 14YJ62 27 1 R8 RESISTOR SM 9100 1210 QPL PANASONIC ERJ 14YJ910 28 6 R1 5 11 RESISTOR SM 200 1210 QPL PANASONIC ERJ 14YJ20 29 2 RA1 R31 RESISTOR SM 500 1210 QPL PANASONIC ERJ 14YJ50 30 2 J5 6 ANGLE PCB MOUNT AMPHONEL DIGIKEY ARF1232 ND 31 50 SHORTING JUMPERS QPL SULLINS STCO2SYAN 32 2 J7 8 DJ0058 POWER PLUG QPL LZR RL30B 33 2 CABLE DC10B QPL LZR DC10B 34 15 R15 28 30 RESISTOR SM 200Q 1206 QPL PANASONIC ERJ 8GEYJ200 35 RIBBON CABLE W CONN DIGLKEY M1AXA 2636R ND 36 1 CONNECTOR 25D IDC QPL 3M 8225 6000 37 C3 C4 C100 R9 OPTIONAL PARTS FOR R10 R12 14 R29 PARALLEL CONTROL R100 38 1 TBD BOLT 39 1 TBD WASHER 1 TBD NUT 41 1 PWB 42 1 DISKETTE 43 1 MANUAL 40 1 STATIC BAG 44 1 BOX 3 34 intersil
25. Summed PN sequences and Q vectors constructed by the Equation 0 5 PN1 0 25 PN2 where PN1 and PN2 can take the values 1 Same PN sequence is used for PN1 PN2 for I and Q with offsets of 0 64 25 and 80 Vector Length 0 78995 RMS 2 05 dBFS 1 061 Max 40 5 dBFS 0 25 0 75 on and File Name GMSKPN IMP 3t Samples 511 Description Stimulus file for GMSK GSM type BT 0 3 PN sequence on channel only Q channel is zeroed Vector Length 1 32 30 1 dBFS 0 03125 on 0 on File Name GMSKPNPC IMP Samples 1022 Description Stimulus file for GMSK GSM type BT 0 3 511 PN sequence on I channel only repeated twice and precoded to output the PN code when modulated as shaped FM and demodulated as OQPSK Vector Length 1 32 30 1 dBFS 0 03125 on 0 Q File Name FM1K8K IMP Samples 60 Description Stimulus file for FM modulation FM with post modulation filtering AMPS type At 60 ksps input the modulation is a 1kHz sine wave with a peak deviation of 8kHz Q samples are zeroed Vector Length Peak amplitude 8 30 0 2667 11 48 dBFS File Name FM1K7K IMP Samples 60 Description Stimulus file for FM modulation FM with post modulation filtering AMPS type At 60 ksps input the modulation is a 1kHz sine wave with a peak deviation of 7kHz Q samples are zeroed Vector Length Peak amplitude 8 30 0 2333 12 64 dBFS File Name FM1K6K IMP Samples 60
26. address without inducing a RESET on the various channels ITEM 5 READ FROM LOCATION WHILE RUNNING This menu item reads to a specific address without inducing a RESET on the various channels ITEM 6 TEST BOARD This menu item is used to test the board and verify the data is properly written and read from the various channel modulators and RAM devices ITEM 0 RETURN TO MAIN MENU This item is used to return to the main menu All Intersil semiconductor products are manufactured assembled and tested under 1509000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site http www intersil com 3 45 intersil
27. and 5 0Vpc at J8 The figure at the end of Appendix B Initial Jumper Settings is a visual reference jumper configuration for this configuration The control processor must then be connected to the parallel interface on J9 PDC 7 0 is the data bus PARWR is the Write signal and PARA is the Address signal The installation of R13 and R14 as well as C3 and C4 may help reduce signal distortion for long cable interfaces Once the parallel port connection is made and the jumpers set the board is ready for operation and control from the parallel interface rather than the ISAbus interface As in the ISAbus configuration stimulus and filter files are used to operate the board 3 13 intersil HSP50215EVAL Direct Modulator Control The HSP50215EVAL Board provides a configuration that allows a user direct access to the HSP50215 control busses as well as to the ACTEL FPGA bus interface This mode is intended for single channel only operation as bus contention will result if other channels are attempted to be controlled via the parallel or ISA bus while the local control is active Modulation channel 1 is the channel that has connectors for the local control of the DUC and ACTEL J4 provides the HSP50215 interface and J3 provides the ACTEL interface The user must design a cable to match the appropriate data and control signals for these parts if local control is to be effective Disable the ACTEL by removing JP4 9 10
28. and set at decreasing amplitude The result is a cyclical output Note that the relative start phase of each CW tone on each channel is determined by the relative time of the channel configuration load For example by reconfiguring individual channels modulator only you can change the relative phase of the CW s changing the Fourier Series resulting in a different shape output waveform You may also find it interesting to adjust the amplitudes to try and approximate a square wave Adding the fourth modulator will improve the approximation remembering that these exercises depend on the configuration returning to the last one called out in order for the next exercise to work Exercise 6 Generating Additive White Gaussian Noise AWGN This exercise will demonstrate the use of the gn stimulus files Noise will be considered alone at first then a modulated signal will be added The Gaussian Noise stimulus files were generated with MATLAB using the code commands a randn 8192 2 b 0 25 a 1 std a 1 a 2 std a 2 This is a Sequence of numbers that are randomly selected in the range of 1 to 1 scaled by 0 25 for 46 limiting normalized to set the standard deviation to exactly 0 25 This baseband signal is input at the sample rate and will be modulated to the IF set in parameter 1 of the modulator channel being used for noise generation As a rule of thumb set the AWGN sample rate to either a value that is at
29. eee te Pe eU REA SNL AA UAE DEW EA UN NERONE RE ORC ER S ONE nent 3 11 Generating User ua drakk tenkeren iden RU REA LUE Opa ae QUE ARS 3 11 Detailed Circuit Description a mem edo ae e tee ia ee ate UP x e OUR e oe ee ete EM ee 3 12 Arey be M aeta dil Due e Rod ete Aen eee ROS E WE eR ce Or me Ete et 3 12 Modulation Ghiannel sed had oe ete ess KIM eS eee teed eee tur _____ 3 12 Modulation Ghannel 3 ise p rne kp eee it 4 3 12 Modulation Channel 2 ee ubetalt same per edu Dept vp ex eR NDS nore nde dens 3 12 Modulation Channel caer ck seek mE ated FUP eed A UP dete welch RSV IEEE 3 12 PC Controller Interface 2 3 13 ISA Interface M 3 13 Parallel Interface Configuration 2 2 3 13 Glocking cete EM MD MeL PELLUS 3 13 Jumpeted Options 3556 och xm qa hebt BERE ERR RENE en I REGE es ONE e 3 13 Power Supply Connections S ee E ud e M ee tes e e es te dades 3 13 Advanced Evaluation Configurations
30. intersil HSP50215EVAL CHANNEL 2 COMPOSITE IF OUTPUT SIGNAL lt OUT3 0 15 3 TO U9 PAGE 4 RZ4 OEPULLUP 3 RSIP 10 OF CHANNEL 2 m MODULATOR OUS INPUT VIA 0034 7 eas oli HSP50215 M QUI33 6 Gj D o oy oe EM Gf co c 0 ca co C3 0 15 BUS 0082 5 00131 4 FROM 030 OFMI 3 H orm 0558499585955525 ouro 50 030 3 X 2 8888598050 20004000 HFX MG MX 78 77 X Ar Lu tios Em 4 24 7 CAS1 c13 RZ5 Y 22 e NC74 73 RSIP 10 QUI2 3 TH CASS uc 72 Be 15 10 QUI2 4 n an 017314 9 x nett Ca 10 00751378 1 am ape am as eae 74 CASE xx OUT3 10 5 75 CAST HSP50215 C8 175 01730 4 vers NC66 Has X ay Oue 3 g 6 AM oe 18 case U3 cs 8 23 50 CASS VCC62 67 Gui 020 C4 7 QUT2 11 22 CASIO SAMPCK 59 kg 23 CAST1 58 2 A V 23 C2 4 QUI12 2 CAS12 NC57 ex 13 35
31. is an example of a higher rate QPSK modulator for Channel 1 Channel 2 Channel 3 Channel 4 Filter file 15136 15136 15136 15136 IP DS 16 16 16 16 16 16 16 16 Center 4000000 4034000 4068000 4034000 Frequency Input 24300 2 24300 24300 3 24300 1 Sample Rate Stimulus QPSKPN QPSKPN QPSKPN QPSKPN File File Name EXO7FM Description The is an example of analog FM modulation with post applications such as Satellite Communication The filter is a square root of raised cosine response 0 35 The filter impulse response is short to support higher data rates For lower data rates the filter in EX01QPSK is recommended The channel spacing is 1 4 times the symbol rate With the 50MHz oscillator the maximum input sample rate for this modulation filtering The filter is a fairly tight low pass design This is probably tighter than would be necessary or desired for AMPS modulation The tight filtering introduces some harmonic distortion in the recovered baseband signal The stimulus files are all 1kHz sine waves at 60ksps with 8 7 6 configuration is 1 5625 MSPS EX05QPSK EXAMPLE CONFIGURATION FILE and 8kHz deviations for channels 1 4 respectively The channel spacing is 120kHz with one channel unoccupied With the 50MHz oscillator the maximum input sample rate would be 390 625kHz At this rate the modulation would be
32. least 10 times the data sample rate or at a value close to the IF BW but make it a prime number not an even multiple of the data sample rate The other parameter that determines the randomness of the noise is setting 8 the number of data samples Two stimulus files have been created and the file name includes the number of samples The pn16k file has 16K data samples and the pn8K has 8K data samples Since the noise is averaged over the number of samples once the number becomes relatively large the differences is primarily 3 9 intersil MATLAB is a registered trademark of MathWorks Inc HSP50215EVAL the amount of time you care to wait to load the file A rule of thumb is to use as large a number as possible Note that the start of the noise sequence is determined by when the stimulus file for that channel is loaded If multiple channels are required to be started together then the board should be set to use the internal synchronization logic to respond to a single external SYNCIN command In noise applications a random start on the various channels is often the desired condition The purpose of this example is to demonstrate both using noise stimulus for filter shape evaluation and for establishing signal plus noise configurations Go to the main menu Select Item 1 and set the following parameters 8 511 9 48 0 Returns to main menu Select Item 2 and set the following parameters 8 511 9 48
33. line The Digital Upconverter provides the primary DSP processing for each channel The control software allows Modulation Channel 4 selection of the modulation type QASK bandlimited FM and shaped FM Resampler frequency IF frequency gain control as well as shaping and interpolation filter configuration The output of the digital upconverter for modulation channel 4 U1 is routed to the cascade input of modulation channel 3 sheet 2 U2 Modulation Channel 4 also allows for external digital cascade input via connector J1 This input can be used for cascading several evaluation boards together or for inclusion of any digitized IF signal with the digital IF output of the modulation channel 4 upconverter U1 The sync and clock signals are supplied to the connector from the clock and sync selection circuitry found on sheet 4 of the schematic JP1 and RZ1 provide control and selection for the channel 4 ACTEL FPGA and associated Digital UpConverter U13 and 14 provide the memory storage for data being processed by the ACTEL FPGA Four modulation channels are provided so that HSP50215 evaluation can include processing a signal of interest in the presence of two adjacent channel signals and an interferer signal Modulation Channel 3 Sheet 2 of the schematic details the control and access circuitry for modulation channel 3 U2 is the Digital upconverter and U7 is the associated ACTEL FPGA The control software allows Modulation
34. site is found at www intersil com and SERINADE is found under the Products column of the home page Select Digital Signal Processing Products Listing menu item Select the Develop ment Tools menu item Select the SERINADE menu item Download of SERINADE can be done from this location The software must be run from the new target directory established on the C drive Verifying the Control Software and Board Installation te 2 __ __ On the PC change the directory to the target direc tory where the control software has been installed Start the program by typing HSP50215 lt Enter gt The MAIN MENU screen will appear It will look like Figure 3 HSP50215 EVALUATION BOARD SOFTWARE Board Configuration Modulator Channel 1 Configuration Modulator Channel 2 Configuration 3 Modulator Channel 3 Configuration 4 Modulator Channel 4 Configuration 5 Load Configuration File 6 Save Configuration File 7 Compute Registers 8 Configure Board 9 Test Menu 10 Exit ENTER SELECTION C Intersil Corporation 1997 Version 1 0 4 __ FIGURE 3 MAIN MENU Select item 0 for board configuration and type lt En ter gt The BOARD INTERFACE MENU will appear as shown in Figure 4 Use the menu items to change the default board configuration to match the evaluation board interface printer FPGA addressing and oscil lator frequency that you desire Verify that these set tings match the jumper configurat
35. the sample rate of the stimulus file to be used as input data Set this value at the desired symbol rate noting that AWGN stimulus files should be set at least 10x the associated data channel symbol rate or the IF bandwidth Neither should be set at an even multiple of the symbol rate ITEM 3 MODULATION TYPE 0 QASK 1 FM w Postfilter 2 FMw Prefilter Enter New Value Current Value This field identifies the modulation type as QASK FM or prefiltered FM When implementing PSK or QAM waveforms select 0 and identify a stimulus file that matches the desired modulation format Some modulation formats are determined by an input stimulus file and a particular filter coefficient file ITEM 4 COEFFICIENT FILE Current File Prefix Enter File Prefix imp extension assumed This field identifies the filter coefficient file to be used in the shaping filter of the channel selected See Appendix G Descriptive File List for details on the format of this file type ITEM 5 INTERPOLATION IP Interpolation Phases Current Phases 0 4 phases 1 8 phases 2 16 phases Enter New Value Current Value This field identifies the number of interpolation phases in the filtering ITEM 6 IMPULSE RESPONSE LENGTH Current Value Current IRL Range is 4 16 Enter New Value Current Value This field identifies the number of data samples in the shaping filter of the identified channel ITEM 7 STIMULUS FILE Current File
36. tones The filter file is slightly wider than the 52 file to pass the tones without attenuating the outer tones The tones in each channel are phase aligned at zero phase Due to the pipeline delays in the cascade data path the four channels will not be phase aligned EXO9TONE EXAMPLE CONFIGURATION FILE Channel 1 Channel 2 Channel 3 Channel 4 Example Filter Files IMP File Format The IMP file is an ASCII text file containing filter coefficients or stimulus vectors An example of the IMP file format is shown below This format matches the format used by SIGLAB a DSP simulation program by the Athena Group Inc of Gainesville Florida In SIGLAB the first four lines are used for comments the fifth line for x axis labels the sixth line for y axis labels and the seventh line contains t c r where t is r for real data and c for complex data c is the number of columns and r is the number of rows In the evaluation board software the first seven lines are ignored by the program so all seven lines may be used for comments The program requires complex sample pairs even if a real signal is modulated such as in FM The first sample of the pair is the data and the second is the Q data The values of the samples can range from 1 0 to 1 0 When the program reads in the data it multiplies it by 215 and rounds to 16 bits If the scaled data exceeds the range 32767 to 32767 the program saturates it to those values
37. used to select carrier center frequency input sample rate modulation type coefficient file name interpolation factor impulse response length Stimulus file name number of data samples output attenuation output enabling cascade input control synchronization synchronization polarity FIFO depth Output Format and test register settings There is a menu for each of the four modulator channels on the evaluation board C Save Configuration File Executing MAIN MENU item 6 brings up a screen with the current file name and a request for a file name to be saved Once the new file name is entered this command stores the configuration setup to the new file WARNING Failure to change the cfg file name may result in overwriting of an example file with an edited version of that file D Compute Registers This command will use the configuration data entered in MAIN menu items 0 4 and generate a number of files which contain the register values for the IC s on the evaluation circuit board The computation is based on a cfg file which contains filter imp and stimulus imp files for each of the 4 channels The computed register values are stored in a set of files identified by the suffix of 1 2 3 and 4 indicating the channel to which the parameters apply The actual filename preceding the 1 2 3 or 4 suffix is automatically assigned to be the Configuration file filename 5 LOAD CONFIGURATION FILE 6 SAVE CONFIGURA
38. 01 NP 0 01NP T c23 5524 EIU aS C26 IT 1627 0 01 NP 0 01 NP 0 01 0 01 0 01 e I zb C28 C30 C31 IS C32 0 01 NP 0 01 NP 0 01 NP 0 01 NP 0 01NP i ale caa I C34 af C35 NS C36 4537 0 01 NP 0 01 NP 0 01 NP 0 01 NP 0 01 NP Mi I C38 C39 C40 IT Q4 2 0 01 NP 0 01 NP 0 01 NP 0 01 NP 0 01 NP i I C42 Q4 C44 C45 46 0 01 NP 0 01 NP 0 01 NP 0 01 NP 0 01 NP gt Ld t EE C48 C49 I C50 3 20651 0 01 NP 0 01 NP 0 01 NP 0 01 NP 0 01 NP e 1 7 IE C62 C63 C64 065 066 10 10 10 L 10 4 C67 n 1 55 3 31 intersil HSP50215EVAL STAT STAT lt lt FROM 99 AT62 010 71 U22 R11 9 J10 i x 1i 2 13 385 17 1 74 244 10 V IOCHRDY 144 X SMEMW 15 SMEMR A19 45 25 IOW A18 44 X IOR 17 5 X DACK3 A16 15 DREQ3 A15 X DACK1 A14 5 96 DREQI A13 gS REFSH A12 Pg SYSCLK AM 517 9 2 IRQ7 A10 7555 X 5 23 CAB LH TN RZ9 24 7 5 IRQ4 35 PCAS RSIP 10 A6 26 PCAS 7 DACK2 AS 27 PCA4 8 TC A4 58 ct E
39. 2 E zl 9 1 raid 1 2 terminates si 500hm 25Watt S the clock A3 AZ iy AD input in 50 stam ohms 100 106 E BH 2 7 on EE 1 GND 103 10771024 es WRRAMS J JP7 1 2 selects the connector for the clock 2 3 selects the da x 34 oscillator for the clock 1 venen Uto NEAN 5 7 AS 13 rmm 9 R 3 M 11 CRYSTALCLK 8 ja mo E N 15 osc 5 Der ss ef ono 14 uei vos He e If the OUTPUT connector is driving the clock lines bod 38 102 04 37 2 then 2 3 headered If either the BNC or crystal 9 mE 108 oscillator is clocking the board then 1 2 and 3 4 10771024 20 headered The clock signal is sent out the M OUTPUT connector through the 3 4 connection E 5 4 KTO PAGE T 4 16 2 R1 Ad 15 PES 4 TO J1 PAGE 1 200hm 3 4 HEADER T R2 1y1 ore MASTERCLK KFO UT PAGET 200 TEM Raet U2 PAGE 2 m eT 5 Rart U3 PAGE 3 x H 13 U4 PAGE 4 XH 2 14 XJ 2 4 Q 36 CASSYNC2 lt lt X 16 p a 7 TO J1 PAGE 1 200hm 26 p Lu 19 74ACT244 ae 20 RS DE CON20 200hm Ra y 5 US PAGE 5 3 29 intersil HSP50215EVAL ICS Continued E Detailed Schemat Appendix 0 15
40. 2 GND J8 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL 1 SVCC 2 GND J9 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL PIN SIGNAL 1 N C 1 N C 2 PCDO 2 N C 3 PCD1 3 PARWR 4 PCD2 4 PARA 5 PCD3 5 GND 6 PCD4 6 GND 7 PCD5 7 GND 8 PCD6 8 GND 9 PCD7 9 GND 10 NC 10 GND 11 STAT 11 GND 12 N C 12 GND 13 N C 13 GND PIN SIGNAL PIN SIGNAL 1 IOCHK 32 GND 2 D7 33 RESDRV 3 D6 34 5V 4 05 35 IRQ9 5 D4 36 5V 6 D3 37 DREQ2 7 D2 38 12V 8 D1 39 OWS 9 DO 40 12V 10 IOCHRDY 41 GND 11 AEN 42 SMEMW 12 A19 43 SMEMR 13 A18 55 IOW 14 A17 45 IOR 15 A16 46 DACK3 16 A15 47 DREQ3 17 A14 48 DACK1 18 A13 49 DREQ1 19 A12 50 REFSH 20 A11 51 SYSCLK 21 A10 52 IRQ7 22 A9 53 IRQ6 23 A8 54 IRQ5 24 A7 55 IRQ4 25 A6 56 IRQ3 26 A5 57 DACK2 27 A4 58 TC 28 A3 59 ALE 29 A2 60 5V 30 A1 61 14 3MHz 31 AO 62 GND intersil HSP50215EVAL Appendix D Test Header Pin Assignments JP1 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 GND Ground 2 CSELO_1 CSELO_1 3 GND Ground 4 CSEL1_1 CSEL1_1 5 GND Ground 6 CSEL2_1 CSEL2_1 7 GND Ground 8 Unused Unused 9 GND Ground 10 ACTELEN_1 ACTEL ENABLE FOR U6 11 GND Ground 12 OEPULLUP_1 OUTPUT ENABLE
41. 3 Channel 4 IP DS 16 16 16 16 16 16 16 16 Frequency Input 614400 614400 614400 614400 Center 4000000 4120000 4240000 4480000 Sample Frequency Rate Sample File Rate Stimulus QPSKPN QPSKPN QPSKPN QPSKPN File 3 35 intersil HSP50215EVAL File Name EX04QAM Description This file demonstrates 16QAM modulation The filter is a square root of raised cosine response a 0 2 The stimulus file is 511 PN codes on each data bit The channel spacing is 1 5 times the symbol rate With the supplied 50MHz oscillator the maximum input sample rate supported by this configuration is 1 041667MHz EX04QAM EXAMPLE CONFIGURATION FILE File Name EXO6QPSK Description This example is similar to EX01QPSK but used for co channel and adjacent channel testing The desired signal is in channel 2 Channels 1 and 3 are at 1 4 times the symbol rate offsets and 10dB higher than the desired signal Channel 4 is in the same channel as the desired signal and 10dB lower The data rates are offset slightly to randomize the phasing of the channels EX06QPSK EXAMPLE CONFIGURATION FILE Channel 1 Channel 2 Channel 3 Channel 4 Filter file RRC2A4X RRC2A4X RRC2A4X RRC2A4X IP DS 4 12 4 12 4 12 4 12 Center Fre 4000000 4768000 5536000 6304000 quency Input 512000 512000 512000 512000 Sample Rate Stimulus 16QAMPN 16QAMPN 16QAMPN 16QAMPN File File Name EX05QPSK Description This
42. 4 Channels Digital or Analog Composite Output Baseband Pattern Stimulus Files with Lengths to 64Kbits Example Baseband Patterns for BPSK QPSK t 4QPSK 16QAM FM GMSK and AWG Noise Baseband Patterns Loaded to RAM Via PC ISAbus or Parallel Port for Use as Modulator Baseband Data DOS Based Configuration Status Software Applications Evaluation Tool for the Performance of the Digital UpConverter Configured as PSK Quadrature Amplitude QAM FM and Shaped FM MSK Modulators at Rates from 1 KBPS to 1 5 MBPS Performance Evaluation Tool for Digital Upconversion Communications Test Equipment 40 PIN 40 PIN CONNECTOR CONNECTOR HSP50215 HSP50215 HSP50215 HSP50215 16 DIGITAL DIGITAL DIGITAL DIGITAL 16 amp UPCONVERTER UPCONVERTER UPCONVERTER UPCONVERTER CHANNEL 3 CHANNEL 2 CHANNEL 1 14 CASCADE CHANNEL 4 INPUT g D A I a 12V DATA INTERFACE BUS ADDRESS INPUT DATA PATH AND CONTROL STATUS INTERFACE p OPTIONAL FINAL STAGE BASEBAND DATA INPUT PATH 8 4 ADDRESS zlL mm IP 8 DATA ese INTERNAL ADDRESS E x CLOCKS 2 WR ADDRESS DECODE o Vcc 12V 3 1 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures 1 888 INTERSIL or 321 724 7143 Intersil and Design is a trademark of Intersil Corporation Copyright Intersil Corporation 2000 HSP50215EVAL Table of Contents PAGE Fun
43. 7 E Ee T uF NP ME 23 24 9 8 25 26 R14 R13 E 10 HEADER 26 OHMS OHMS c 74ACT32 2 U23D o L 12 V V Wow GND GND 13 74ACT32 E JP11 HEADER 2 Da 912 5 LM7905CK 5 2V FROM REGULATOR 3 2 IN OUT 9 lt 2 cs C6 GND GND 5 10uF AuFNP O1uF NP lt lt LI GND GND GND GND GNO 5 Q 3 33 intersil HSP50215EVAL Appendix F Parts List INTERSIL CORPORATION HSP50215EVAL REV B REV B 3 23 98 QTY LINE PER REFERENCE MANUFACTURER S ITEM PCB DESIGNATOR DESCRIPTION PKG MANUFACTURER PART 1 4 U1 U4 DIGITAL UPCONVERTER 100 MQFP Intersil HSP50215VC 2 8 U13 U20 1 MBIT STATIC RAM 32 SOJ IDT IDT71024S15TY 3 4 U6 U9 FPGA 84 PLCC ACTEL A1225XL PL84C 4 4 REF U6 U9 Label to read on FPGA HSP50215 FPGA REVA 5 1 U5 14 BIT D A 28 SOIC Intersil HI5741BIB 3 JP1 JP3 HEADER 2 8 2x8 QPL SULLINS PTC8DAAN 6A 1 J9 HEADER 2 x 13 SHROUDED 2x13 CIRCUIT ASSEMBLY CA 28HL 1C CORP T 2 JP4 6 HEADER 2x 10 2x10 QPL SULLINS PTC10DAAN 8 1 JP9 HEADER 2 x 4 2x4 QPL SULLINS PTC4DAAN 9 2 JP10 11 HEADER 1 x 2 1x2 QPL SULLINS PTC2SAAN 10 1 JP7 HEADER 1 x3 1x3 QPL SULLINS PTC35SAAN 11 1 JP8 HEADER 1 x 4 1x4 QPL SULLINS PTC4SAAN 12 1 J4 HEADER 1 x 20 1x20 QPL SULLINS PTC20SAAN 13 1 JP5 HEADER 2x5 2x5 QPL SULLINS 14 3 J1 J2
44. AL BOARD INTERFACE MENU CONFIGURE BOARD ITEM 1 CONFIGURE CHANNEL 1 This command downloads the configuration files necessary to configure only modulator channel 1 All other modulator channels remain unchanged from the current settings ITEM 2 CONFIGURE CHANNEL 2 This command downloads the configuration files necessary to configure only modulator channel 2 All other modulator channels remain unchanged from the current settings ITEM 3 CONFIGURE CHANNEL 3 This command downloads the configuration files necessary to configure only modulator channel 3 All other modulator channels remain unchanged from the current settings ITEM 4 CONFIGURE CHANNEL 4 This command downloads the configuration files necessary to configure only modulator channel 4 All other modulator channels remain unchanged from the current settings ITEM 5 CONFIGURE ALL CHANNELS This command downloads the configuration files necessary to configure all four modulator channels TEST MENU ITEM 1 RESET BOARD This item resets the HSP50215 Digital UpConverters and puts the ACTEL PLD s in their initial state on all four channels ITEM 2 WRITE TO LOCATION WHILE RESET This menu item writes to a specific address while the various channels are RESET ITEM 3 READ FROM LOCATION WHILE RESET This menu item reads from a specific address while the various channels are RESET ITEM 4 WRITE TO LOCATION WHILE RUNNING This menu item writes to a specific
45. ANNEL 1 CASCADE INPUT IS CHANNEL 2 MODULATOR OUTPUT QUT3 10 15 gt FROM U3 PAGE 3 Pecon 02275 PAGE 6 LAR S OEPULLUP 4 4 3 d 8 ib CHANNEL 1 HSP50215 CHANNELS ESEBEXPPE INPUT om 5886056868 202484488 c4 0 15 Bus NC3 NC78 77 15 p HE T CAS A Jak GND7 NC74 75 X CAS2 VCC73 72 CASS A case en C10 m CAS5 ce 68 CAS6 64068 87 8 HSP50215 GND18 7 6 REFCLK 55 r7 CASS C5 62 CASS NC20 U4 X 4 CAS10 SAMPCK 58 511 58 aD 23 co 57 512 NC57 55 X CAS13 GND56 55 1 51 casts co 54 CA 0 NC28 NC53 2 3 NC29 NC52 30 2 SYNCOUT 21 SYNCOUT ke I TO JP5 9 i 522338212 E ald 8 FIF TP4 3 X 8 TO RZ 88 FROM IPS PAGE 2 lt CEPULLUP 1 FROM U11 PAGE 4 lt lt MASTERCLK FROM JP9 PAGE 6 wn FROM JP9 6 4 4 ns STAT TO U24 J9 PAGE 6 j C4 3i 18 69 Sem ACTEL FPGA es AN 4 20 P x N 2112 us ga pe I 0 C47 24 vec23 VCC64 C48 25 24 GND63 Y 25 62 8 26 25 ESI LEAN
46. CY RESPONSE 3 40 intersil HSP50215EVAL File name GP1 IMP PARAMETER VALUE Taps 256 16xFsamp IP DS 16 16 3dB BW 70 3 x FSAMP DC Gain 0 518 5 7dB Peak Coef Value 0 345 Maximum Output 0 835 1 57dB NBW 0 606 x double sided Description High dynamic range filter for general purpose interpolation Passband ripple is 0 3dB peak to peak Frequency Response DC to Foyrt 2 of the Shaping FIR Filter 10 20 30 40 50 60 70 80 90 100 00 DAN FT gt FIGURE 15 GP1 IMP FREQUENCY RESPONSE File name GP2 IMP PARAMETER VALUE Taps 256 16xFsamp IP DS 16 16 3dB BW 0 38 x DC Gain 0 51 5 7dB Peak Coef Value 0 433 Maximum Output 0 835 1 57dB NBW 0 77 x FsAMP double sided Description High dynamic range filter for general purpose interpolation Passband ripple is 0 1dB peak to peak Frequency Response DC to Foyrt 2 of the Shaping FIR Filter 0 T T T 152 Sale a 20 30 pet MAINE 40 Lt 50 4 60 1 70 1 80 90 100 o FIGURE 16 GP2 IMP FREQUENCY RESPONSE dtu QN oO to
47. GND 15 CAS9 85 CAS1 16 GND 36 GND 17 CAS8 37 CASO 18 GND 38 GND 19 CONNINCLK 39 CASSYNC2 20 GND 40 GND J2 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL PIN SIGNAL 1 N C 21 NC 2 GND 22 GND 3 OUT4 15 23 OUT4_7 4 GND 24 GND 5 OUT4_14 25 OUT4_6 6 GND 26 GND 7 OUT4_13 27 OUT4_5 8 GND 28 GND 9 OUT4_12 29 OUT4_4 10 GND 30 GND 11 OUT4_11 31 OUT4_3 12 GND 32 GND 13 OUT4_10 33 OUT4_2 14 GND 34 GND 15 OUT4_9 35 OUT4_1 16 GND 36 GND 17 OUT4_8 37 OUT4_0 18 GND 38 GND 19 MASTERCLK 39 OPCASSYNC 20 GND 40 GND PIN SIGNAL PIN SIGNAL 1 GND 2 GND 3 A3 0 4 OERAM4 5 FIFOTP_4 6 C4 15 7 CEPULLUP 4 8 C4 14 9 SYMBLCLK 4 10 C4 13 11 WR215 4 12 C4 12 13 OE215 4 14 11 15 RESET4 16 C4_10 17 GND 18 GND 19 DU4A9 20 C4 9 21 DU4A8 22 C4 8 23 DU4A7 24 C4 7 25 DU4A6 26 C4 6 27 DU4A5 28 C4 5 29 DU4A4 30 C4 4 31 DU4A3 32 C4 3 33 DU4A2 34 C4 2 35 DU4A1 36 C41 37 DU4A0 38 C4_0 39 GND 40 GND J4 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL 1 GND 2 4 16 3 4 15 4 4 14 5 4 13 6 A4 12 7 4 11 8 4 10 9 GND 10 A4 9 11 A4 8 12 A4 7 13 A4 6 14 A4 5 15 A4 4 16 A4 3 17 A4 2 18 A4 1 19 A4 0 20 GND 3 17 intersil HSP50215EVAL J5 CONNECTOR PIN ASSIGNMENTS J10 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL 1 ANALOG IF 2 GND J6 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL 1 SMACLK 2 GND J7 CONNECTOR PIN ASSIGNMENTS PIN SIGNAL 1
48. N MENU 1 with the excep tion of the Channel Number and the names of the co efficient file and stimulus file Select MAIN MENU item 6 by typing 6 Enter This will save the edited configuration file You are prompted for a file name for your new configuration WARNING Failure to change the cfg file name may result in overwriting of an example file with an edited version of that file ___ Select MAIN MENU item 7 by typing 7 lt Enter gt This will compute the configuration register values and generate the 1 2 3 and 4 files Filter and stimulus files with imp file extensions must be created prior to running the HSP50215EVAL software See Appen dix G Descriptive File List Note that MAIN MENU items 1 through 7 can be executed without the evalu ation circuit board installed 17 18 19 20 ___ Select MAIN MENU item 8 by typing 8 Enter The Board Interface Menu will appear as shown in Figure 7 If you have identified more than one channel for oper ation selection of menu item 5 will load all the chan nels with one command See step 25 for this action In testing there are times when most of the channels will remain the same and one channel or one channel input will change Menu items 1 through 4 are for selective channel or channel input configuration Se lect the menu item 1 CONFIGURE CHANNEL 1 MENU of the BOARD INTERFACE MENU by typing 1 lt Enter gt A menu will appear with three
49. P9 PAGE 6 WRRAM1 FRO OERAM 1 CSEL2 1 CSELI 1 SYMBLCLK 1 CSELO 1 OFMT 1 02 CASZ 1 BEAT STAT TO U24 J9 PAGE 6 ol 9 r j e ul eu 7 991 99 991 Len Ee FPGA Erongo nog 2 OA a 12 6 13 74 A1 16 Ci 15 14 1715 114 15 2 At 14 1 13 16 15 115 2 c1 12 17 70 Cr 48 14 ACTEL FPCA ENDT 12 19 68 AL 20 19 68 ALIO 20 97 55 C18 2 66 ALS 2 o U6 voces 55 23 64 o veezs 28124 GND63 757 ALB 25 62 C1 5 26 61 AUT G C14 27 26 s1 AT 6 28 56 A 5 E cia 29 UA 2 58 ATA C12 30 27 31 a 57 2 X 32 3 58 55 22 54 AIO x 2 9 ogoourooo a sooroZzocun t gt tE OONO Sae S99 s sv eoo cu 4 5 Y Q daaaddaaddaa 586 ACTELEN 1 GND 1 FROM U24 J9 PAGE 6 ly gt gt PCD O 7 2 3 23 i i Intersil HSP50215EVAL CHANNEL 3 CASCADE INPUT IS CHANNEL 4 MODULATOR OUTPUT OUT 1 10 15 gt FROM U1 PAGE 1 vec RSIP 10 1 RZ2 CEPULLUP 2 TO U2 QEPULLUP 2 ACTELEN 2 CSEL 2 2 CSELO 2 FIFOTP 2 MX VEC JP2 GND HEADER 8X2 GND
50. PULLUP U1 13 GND Ground 14 CEPULLUP_1 CHIP ENABLE U1 PULLUP_1 15 GND Ground 16 FIFOTP_1 FIFO TEST POINT U1 JP2 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 GND Ground 2 CSELO_2 CSELO_2 3 GND Ground 4 CSEL1_2 CSEL1_2 5 GND Ground 6 CSEL2 2 CSEL2 2 7 GND Ground 8 Unused Unused 9 GND Ground 10 ACTELEN 2 ACTEL ENABLE FOR U7 11 GND Ground 12 OEPULLUP 2 OUTPUT ENABLE PULLUP U2 13 GND Ground 14 CEPULLUP 2 CHIP ENABLE U2 PULLUP 1 15 GND Ground 16 FIFOTP 2 FIFO TEST POINT U2 JP3 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 GND Ground 2 CSELO 3 CSELO 3 3 GND Ground 4 CSEL1 3 CSEL1 3 5 GND Ground 6 CSEL2 3 CSEL2 3 7 GND Ground 8 Unused Unused 9 GND Ground 10 ACTELEN 3 ACTEL ENABLE FOR U8 11 GND Ground 12 OEPULLUP 3 OUTPUT ENABLE PULLUP U3 13 GND Ground 14 CEPULLUP_3 CHIP ENABLE U3 PULLUP_1 15 GND Ground 16 FIFOTP_3 FIFO TEST POINT U3 JP4 TEST HEADER PIN ASSIGNMENTS PIN SIGNAL DESCRIPTION PIN SIGNAL DESCRIPTION 1 GND Ground 2 CSELO 4 CSELO 4 3 GND Ground 4 CSEL1 4 CSEL1 4 5 GND Ground 6 CSEL2 4 CSEL2 4 7 GND Ground 8 Unused Unused 9 GND Ground 10 ACTELEN 4 ACTEL ENABLE FOR U9 11 GND Ground 12 OEPULLUP 4 OUTPUT ENABLE PULLUP U4 13 GND Ground 14 CEPULLUP 4 CHIP ENABLE U4 PULLUP 1 15 GND Ground 16 FIFOTP 4 FIFO TEST POINT U4 3 19 intersil HSP50215EVAL JP5 TEST HEADER PIN ASSIGNMENTS
51. Prefix Current Filename Enter File Prefix imp extension assumed This field is used for identifying the stimulus file that contains the and Q data for the identified modulator channel See Appendix G Descriptive File List for details on the format of this file type Include in this field the path to the file relative to the directory that the HSP50215 exe file is located Stimulus files send data to both the and Q FIFO s in the HSP50215 Fixed levels A are used r BPSK and QPSK Multiple levels are required for higher order PSK and QAM modulation formats The stimulus file bpskpn writes the following values to the FIFO s 0 707 0 707 0 707 0 707 yielding a vector magnitude of 1 Note If you have not properly identified the stimulus file or the path to that file then the program will not download when you command the software to configure the board and will return you to the DOS prompt at which point you will need to restart the control software and start from scratch on the configuration 3 43 intersil HSP50215EVAL DATA SAMPLES Current Value Current Data Samples Range is 1 65536 Enter New Value Current Value This field is used to identify the number of data samples to be retrieved from the Stimulus file listed in item 7 If a CW signal is desired identify bpskpn as the Stimulus file and select the number of data samples to be 1 If a test pattern is desired select the numbe
52. RFACE submenu item 0 by typing 0 Enter This returns the user to the MAIN MENU You have now configured your board for its first test configuration You may look at the out put with a scope or spectrum analyzer to verify that the board is operating as desired 23 If the output is not as expected review the configura tion of all of the channels to be sure that you have properly selected the stimulus filtering and configu ration 24 When designing a new configurations or new stimulus itis best to begin by editing the example file that most closely matches the desired signal or configuration Learning Your Way Around This Section provides a step by step walk through of some exercises to familiarize the user with the software screens and the techniques used to generate a variety of stimulus and configurations of the HSP50215EVAL Board If the DAC output is routed to a scope or a spectrum analyzer then a visual verification can be made of the configuration changes Note that these exercises assume that the concluding configuration of the previous exercise is the configuration of the board at the start of the next exercise The first exercise configures all channels to ensure success Exercise 1 Generating A CW Tone This exercise will demonstrate the creation of a CW test tone The purpose of this exercise is to illustrate the generation of a signal that is useful in a variety of testing configurations Go to the main men
53. TION FILE 7 COMPUTE REGISTERS 10 EXIT 3 4 8 9 MODULATOR CHANNEL 4 CONFIGURE BOARD TEST COMMAND COMMAND MMAND COMMAND 1 16 FIGURE 1 MENU TREE FOR THE CONTROL STATUS SOFTWARE 3 3 intersil HSP50215EVAL E Configure Board Menu This command accesses a menu called the BOARD INTERFACE MENU The BOARD INTERFACE MENU is used to select among several board configure command options including configure channel 1 configure channel 2 configure channel 3 configure channel 4 or configure all modulator channels D Test Menu This command accesses a menu called the TEST MENU The TEST MENU is used to select among several run options including reset the board write to a location while reset read to a location while reset write to a location while running or read from a location while running For a detailed listing of every Menu screen with selection item definitions refer to Appendix G Descriptive File List Configuration Test Headers Fifteen dual row test headers located on the evaluation circuit board are used to monitor signals and set control pins The pin assignments for each of these headers are found in Appendix D Test Header Pin Assignments Typical Evaluation Configuration Figure 2 identifies the configuration of a typical performance evaluation setup A test PRBS data pattern is created via a stimulus file and used by a modulator to generate a modulated IF s
54. Using SERINADE Designed Filters SERINADE a filter design tool can be used to synthesize a filter for the HSP50215 shaping filters This procedure assumes that the SERINADE imp files are available for import Version 1 1 or higher is recommended File format is consistent with a SERINADE imp file or SIGLAB file Appendix A Circuit Board Layout 72 JP11 i 5 JP6 jpg J3 m JP1 3 14 intersil SERINADE is a trademark of Intersil Corporation SIGLAB a trademark of The Athena Group Inc HSP50215EVAL Appendix B Initial Jumper Settings INITIAL JUMPER SETTINGS CONTINUED LOCATION SETTING JP4 9 10 JP4 11 12 JP4 13 14 The JP4 jumpers set the control signals such as chip enables out put enables and chip select controls for the ACTEL and HSP50215 for Channel 1 JP5 1 2 JP5 3 4 JP5 7 8 JP5 9 10 The JP5 jumpers set the SYNC controls bringing SYNCOUT to the output connector and routing the SYNCOUT of channel 1 HSP50215 to the SYNCIN on all channels HSP50215 s on the board The remaining jumpers add additional output signal resolu tion to the output connector J2
55. aximum Output 1 054336176 0 4dB NBW 1 004 x Fsamp double sided Description Square root of raised cosine filter alpha 0 35 for North American TDMA cellular type signals Frequency Response DC to FOUT 2 of the Shaping FIR Filter 10 20 30 40 70 4 80 FIGURE 9 1513681 FREQUENCY RESPONSE File name RRC2A4X IMP PARAMETER VALUE Taps 48 04x Fsamp IP DS 4 12 3dB BW 0 5 x FSAMP DC Gain 0 595 4 5dB Peak Coef Values 0 610 Maximum Output 1 094 0 78dB NBW 0 996 x double sided Description Square root of raised cosine filter with sharp transition band alpha 0 2 for QAM type signals Frequency Response DC to Fout 2 of the Shaping FIR Filter 10 20 30 JJ 40 50 60 L 70 80 90 2 100 Qo x OG 0t 112 128 144 1 FIGURE 10 RRC2A4X IMP FREQUENCY RESPONSE 3 38 intersil HSP50215EVAL File name GS5T16X IMP PARAMETER VALUE Taps 80 16xFsamp IP DS 16 5 3dB BW 70 25 x Fgamp DC Gain 1 0000 0dB Peak Coef Value 0 7416 Maximum Output 1 0000 0dB
56. co 89 29 ues 58 ams ce 1 66 HSP50215 2 q7 GND16 ul asi Jg REFCLK C6 C25 d qg CASB 02 C5 1 55 i 20 CASO VCC62 61 x NC20 C4 55 Un CAS10 SAMPCK 22 59 2 55 CAS C3 58 ER VCC23 C2 17 55 512 NC57 OUT 557 CAS13 GND56 luni 15 53 1 514 tt 5g CASTS CO 53 55 1 NC28 NC83 15 X NC29 gt NC52 5 2 sz 2 g SYNCOUT 1220922 gt 2 206 2 gt 0 0 1 de cal OF Of sunt ol sol DI oe 09 C9 ss SE 4 sje vu dala aa FROM 5 PAGE 4 CEPULLUP 2 FROM RZ2 99 FROM 011 PAGE 4 L x FROM J9 PAGE 6 FROM J9 PAGE 6 WRRAM2 OERAM 2 CSEL2 2 CSEL1 2 SYMBLCLK 2 CSELO 2 1 2 TO U7 CASZ 2 STAT TO U24 J9 PAGE 6 19191519 apata 210 ca 91 20 90 SINS Pm 8 Bat npes 13 72 14 71 2 13 55 GND70 35 n ACTEL FPGA 67 2 10 67 5 owt 66 55 2 veces I U7 VCC64 63 GND63 62 FPGA 62 51 80 g Fa er 57 Pee e3 56 A22 56 rom 55 54 A20 v 54 44 9 o 2 0 CO 0 00 0 eo el od ol elr olo dale S3 3a 3 9 v v v v
57. ctional Block Diagr m mov ERE Ue apo ea Pede Dea vee e daa elei DR E b 3 1 Control Software Program 4 ls nux ARR ee kake ux dE ERG ead UR EG EE ers 3 3 FIGURE 1 MENU TREE FOR THE CONTROL STATUS 3 3 Configuration Test Headers ore oe Pare ats br d oe RTS as Ba nae DE ER Eque EN 3 4 Typical Evaluation m uh e t e he 3 4 Getting Started Ie Lie RU Eee dk ed top tk te UP o Us kassan hed amin d bite 3 4 Evaluation Circuit Board Configuration and Set 3 4 Requirements for the Control Software Program ehh mes 3 4 Installing the Software Aude edere 3 4 FIGURE 2 TYPICAL MODULATOR PERFORMANCE EVALUATION 3 4 Verifying the Control Software and Board Installation 4 3 5 FIGURE S MAIN MENUJ ates Ur eene rud LT ene eu ege EE rab 3 5 FIGURE 4 BOARD INTERFACE 7 4 3 5 FIG RE 5 TEST SUBMENU Se re ge gear mic pu mi Tees 3 5 Running the Control Software for Evaluation 0
58. e SYNCIN of U1 4 Installing JP5 5 6 routes this sync signal to the output connector JP5 also allows jumpering of additional digital IF output resolution to the output connector J2 Installing JP5 1 2 and 3 4 provides 2 bits of additional resolution on the output connector Power Supply Connections The 5V and 12V are supplied via the ISA interface when the card is installed in a PC When the card is used outside the PC 5V is input via J8 and 12V is input via J7 The 5V can be supplied from any generic 5Vpc 2A AC DC power adapter The evaluation board draws approximately 1 5A at 52MHz on the 5Vpc input The 12V is supplied from the ISA connector J10 and is regulated to 5V with U12 shown on sheet 5 of the schematic If the ISA bus interface is used then jumper J11 must be installed If an external 5Vpc supply is used then jumper J11 must not be installed Any generic 5Vpc 200mA AC DC power adapter can be used for the J7 Vee input The evaluation board draws approximately 100mA at 52MHz on the 5Vpg input Advanced Evaluation Configurations Non ISA PC installed Operation The HSP50215EVAL can be operated external to a PC for laboratory applications with other evaluation boards The ISA interface is disabled by configuring jumpers on the board Remove jumpers JP9 1 2 and 5 6 Install jumpers JP9 3 4 and 7 8 Remove jumper JP6 17 18 and 19 20 Remove jumper JP 11 and provide external power supply voltages 5 0Vpc at J7
59. erly Record the oscillator frequency for future reference Hz 4 Re install the PC chassis cover and power up the computer The circuit board is ready for use Requirements for the Control Software Program In order to properly operate the HSP50215EVAL Control Software Program included in the evaluation kit the PC must meet the following requirements PC XT AT or 100 compatible with a minimum of 640K of RAM DOS Version 3 0 or higher One parallel port with 25 pin connector Installing the Software The instructions that follow will load both the HSP50215EVAL software onto the C drive of the computer If you do not wish to run the software from the C drive consult your computer user s manual for operation from another drive It is good practice to backup original disks prior to installing the software on your computer 1 ___ Insert the HSP50215EVAL distribution disk in Drive and copy the contents of the distribution diskette to the target directory on Drive C Note This must be done in such a way as to retain the file structure of the distribution disk PERSONAL COMPUTER ANALOG IF OUTPUT HSP50215EVAL EVALUATION BOARD DIGITAL IF OUTPUT FIGURE 2 TYPICAL MODULATOR PERFORMANCE EVALUATION CONFIGURATION 3 4 intersil HSP50215EVAL If a FIR filter design software tool is desired then downloading SERINADE from the Intersil Corpora tion website into the target directory is recommend ed The web
60. ers that have changed involve one modulator then the quickest configuration update downloads only the parameters for that modulator The next quickest update is if the Pattern RAM and modulator for that single channel are all that need downloading You will appreciate this as you apply the larger stimulus files like the AWGN files The longest download involves updating the modulator and Pattern RAM files for all channels 3 8 intersil HSP50215EVAL Exercise 4 CW and a Modulated Signal This exercise simulates a CW jammer interferer with a signal of interest The affect of interference is determined by how close in frequency the CW is to the desired signal and what the relative amplitude is to the signal of interest We will use the pre configured channel 1 as the modulated signal and configure channel 2 to be the interfering CW The purpose of this exercise is to introduce the user to simple dual channel operation Go to the main menu Select Item 2 and set the following parameters 8 1 9 6 0 Returns to main menu This will set channel 2 to CW at 3dB lower than the modulated signal level and at half the frequency Select main menu 7 to compute the register values Select main menu 8 to configure the board Select submenu item 2 to configure channel 2 Select submenu item 3 to load both the modulator and Pattern RAM When the submenu reappears the download is complete This particular signal is easier
61. es not support guard times of less than full data bit periods due to that input sample rate To generate guard times with quarter bit resolution the input sample rate must be increased to 4x270833 The channel spacing is 800kHz with one unoccupied channel With the supplied 50MHz oscillator the maximum input sample rate supported by this configuration is 625 000Hz EX02GMSK EXAMPLE CONFIGURATION FILE Channel 1 Channel 2 Channel 3 Channel4 Filter file GS5T16X GS5T16X GS5T16X GS5T16X IP DS 16 5 16 5 16 5 16 5 Center 3200000 4000000 4800000 6400000 Frequency Input 270833 333 270833 333 270833 333 270833 333 Sample Rate Stimulus GMSKPN GMSKPN GMSKPN GMSKPN File PC PC File Name EXO3QPSK Description This is a lower dynamic range QPSK example This filter is a slightly modified version of the 1595 coefficient set The stimulus is a 511 PN sequence on and The channel spacing is 1 25 times the symbol rate With the supplied 50MHz oscillator the maximum input sample rate supported by this configuration is 1 041667MHz EX03QPSK EXAMPLE CONFIGURATION FILE M Ch 11 Ch 12 Ch 13 Ch 14 configuration is 195 312 5Hz apne en Filter file IS95MOD IS95MOD IS95MOD IS95MOD EX01QPSK EXAMPLE CONFIGURATION FILE IP DS 4 12 4 12 4 12 4 12 Channel 1 Channel 2 Channel
62. execution options as shown in Figure 8 This is the same menu that will appear when BOARD INTERFACE MENU items 2 through 5 are selected File Name 1 Configure Channel 1 2 Configure Channel 2 3 Configure Channel 3 4 Configure Channel 4 5 Configure All Channels 0 Main Menu ENTER SELECTION C Intersil Corporation 1997 Version 1 0 FIGURE 7 BOARD INTERFACE SUBMENU Select the desired action from the three choices in 1 Modulator 2 Pattern RAM 3 Both ENTER NEW VALUE 1 FIGURE 8 CONFIGURE CHANNEL 1 SUBMENU the BOARD INTERFACE submenu The MODULA TOR item does an initialization of the designated channel and begins normal operation of that channel The PATTERN RAM menu item allows individual STIMULUS files to be downloaded Selecting item 3 allows both channel and stimulus configuration with one command Selection of an item will return the user to the BOARD INTERFACE submenu Items 2 3 and 4 of the BOARD INTERFACE submenu configure only channel 2 3 and 4 on the board respectively Configure these channels and return to the main BOARD INTERFACE submenu 3 6 intersil HSP50215EVAL 21 Item 5 of the main BOARD INTERFACE submenu does a full initialization and configuration of all four channels on the board Item 5 should be selected whenever the board has been reset After that items 2 3 or 4 can be selected for a faster update 22 Select HARDWARE INTE
63. figuration 3 7 intersil HSP50215EVAL 8 16384 9 48 0 Returns to main menu This configures channel four to be a 351Kbps PSK modulator at 500kHz with a Gaussian White Noise input and with the RF severely attenuated so as to be effectively turned off Select main menu item 6 save configuration file and enter the following file name and path examples exercise Select main menu 7 to compute the register values Select main menu 8 to configure the board Select submenu item 5 to configure all channels Select submenu item 3 to load both the modulator and Pattern RAM When the submenu reappears the download is complete and the scope or spectrum analyzer should show a single CW tone at 500kHz at approximately 0 4Vpp Exercise 2 Adjusting the level of the CW Tone This exercise will demonstrate the technique used in adjusting the output amplitude of the CW test tone via the Gain Control signal of the Digital Upconverter This is but one technique that can be used to set the level noting that scaling the input file can achieve the same result The HSP50215 data sheet notes that care must be taken in setting the signal level at the input to the shaping filter at the input to the interpolation filter at the input to the mixer and at the cascade summer Attention to these points will eliminate the unwanted limiting or roll over The purpose of this exercise is to introduce the user to a technique for setting te
64. guration selections and three command actions The menu tree is illustrated in Figure 1 The 7 configuration submenus are Board Configuration Menu Modulator Channel 1 Configuration Menu Modulator Channel 2 Configuration Menu Modulator Channel 3 Configuration Menu Modulator Channel 4 Configuration Menu Configure Board Menu Test Menu The four command actions are Load Configuration File Save Configuration File Compute Registers Exit A typical operational sequence is A Load Configuration File Executing MAIN MENU item 5 brings up a screen with the current file name and requests the name of the file to be loaded Once the new file name is entered this command loads the configuration setup and returns to the MAIN MENU Screen This command allows the user to select a previously saved configuration file for display review and editing 0 1 2 BOARD MODULATOR CONFIGURATION CHANNEL 1 MODULATOR CHANNEL 2 CONFIGURATION CONFIGURATION 1 1 1 7 16 16 MODULATOR CHANNEL 3 CONFIGURATION CONFIGURATION 1 16 B Edit Configuration File This is done by sequencing through each of the configuration submenus and adjusting the parameters for the desired hardware configuration The BOARD CONFIGURATION MENU is used to select control interface type printer port PRN number FPGA addressing and oscillator frequency The MODULATOR CHANNEL CONFIGURATION MENUS are
65. ignal Noise and other signal impairment stimulus files can be used with additional channels to create a cascaded summed composite IF signal that is routed to a D A converter DAC generating an output analog signal The digitized IF signal is also routed out of the circuit board allowing multiple boards to be cascaded together To check out a complete communication systems the modulator output can be routed to a demodulator whose baseband output is connected to a Bit Error Rate Tester BERT for measuring the Bit Error Rate BER performance Getting Started CHANNEL 1 STIMULUS FILE CHANNEL 1 FILTER FILE CHANNEL 1 STIMULUS FILE CHANNEL 1 FILTER FILE CHANNEL 4 STIMULUS FILE CHANNEL 4 FILTER FILE CONFIGURATION FILE CHANNEL 4 STIMULUS FILE CHANNEL 4 FILTER FILE CONFIGURATION FILE Evaluation Circuit Board Configuration and Set Up 1 ___ Power down the host PC and remove the cover to al low access to the motherboard empty slots 2 Review the jumper configuration of the HSP50215EVAL Board to verify that the jumpers are properly set for the configuration desired Appendices B especially the jumper diagram at the end of the ap pendix D and E will be helpful in this verification 3 Install the HSP50215EVAL into one of the empty ISA slots on the host PC motherboard Make sure that a good connection is made with the motherboard and that the connectors fit in the slots in the rear of the PC chassis prop
66. intersil User s Manual HSP50215EVAL File Number 4463 3 January 1999 DSP Modulator Evaluation Board Evaluation Kit The HSP50215EVAL Kit provides the necessary tools to evaluate the HSP50215 Digital Upconverter integrated circuit and consists of a circuit board and a software program The kit is designed for evaluation of Digital Quadrature Amplitude FM and Shaped FM modulation for IF Communications Applications The circuit board uses baseband and Q data patterns loaded through the 8 bit parallel interface or the ISAbus interface Data is output as either a digital or analog modulated composite IF signal Up to four channels can be included in the composite IF output To facilitate the use of the board during evaluation the kit includes example files for configuration shaping filters and input stimulus Circuit Board The Functional Block Diagram illustrates the major functions of the circuit board The circuit board is a ISAbus form factor with 40 pin I O header connectors for cascade and output signals Baseband test patterns are loaded through the ISAbus or 8 bit parallel interface The external Cascade Input allows expansion of the number of channels in the composite signal The board outputs data through both the RF connector and the 40 pin header Test connectors are provided at key signal and control locations in the circuit Functional Block Diagram Features Multi Channel Composite IF Output with 1
67. ion of your evaluation board When you have completed making your modifications select item 0 and type lt Enter gt to return to the MAIN MENU Select Main Menu item 9 and type Enter to enter the Test Menu The Test Menu is shown in Figure 5 Select Test Menu Item 6 and type Enter to enter the Test Board submenu Ascreen appears that indicates the RAM Address Da ta Bus test results and the HSP50215 data bus test 1 2 3 4 5 6 7 0 results If all the items have passed the test the board and software have been properly installed and you are ready to begin evaluation testing Skip to step 12 If any test failed proceed to step 9 If one of the tests shown on the screen for step 8 did not pass then the board jumper configuration should be reviewed as it is the most likely culprit Interface ISA Base Address Channel 1 FPGA Address Channel 2 FPGA Address Channel 3 FPGA Address Channel 4 FPGA Address Oscillator Freq Main Menu ENTER SELECTION C Intersil Corporation 1997 Version 1 0 FIGURE 4 BOARD INTERFACE SUBMENU File Name 1 2 3 4 5 6 0 Reset Board Write to Location While Reset Read from Location While Reset Write to Location While Running Read from Location While Running Test Board Main Menu ENTER SELECTION 10 11 __ C Intersil Corporation 1997 Version 1 0 FIGURE 5 TEST SUBMENU Next the physical installatio
68. l of one HSP50215 modulation channel on the HSP50215EVAL Input Connector J4 provides access to the control bus of the ACTEL FPGA for channel four All other channels are expected to be not used to prevent bus contention during the control of the channel 1 upconverter via the channel 1 ACTEL FPGA 3 12 intersil ACTEL is a registered trademark of Actel Corporation HSP50215EVAL PC Controller Interface Section ISA Interface The normal installation configuration of the HSP50215EVAL Card is in a PC using a standard ISA slot J10 on sheet 6 of the schematic details the card connector interface to the computer ISA bus JP6 is used to set the card address location in the PC The default card address shown on the schematic is 110000 and should be used unless that address has already been allocated in your PC configuration U21 and RZ7 perform the card decode from the ISA interface and combine with U22 and U23 to generate the Read Write and Address handling necessary for proper ISA interaction with the HSP50215EVAL Jumper JP9 allows for ISA control interface or an 8 bit parallel port interface via connector J9 Set the jumper configuration as shown in the schematic for ISA interface operation U24 provides the ISA bus interface to the HSP50215EVAL 8 bit bus interface which downloads control data to the ACTEL FPGA s on each of the four modulator channels Parallel Interface Configuration To configure the HSP50215EVAL t
69. lt lt FROM 09 PAGE 4 DACCLK X FROM U11 PAGE 4 200 ohm SMA QUT4 15 R28 D J5 14 Ree 7 gt 840h QUT4 13 R26 12 R25 GND 11 525 5 10 R23 GND R31 R6 R22 OUT4 9 3 50Ohm 2 640hm R21 D13 IOUT 2 311012 IOUTB 2 R20 Dii COMPIN Qum 7 D10 COMPOUT 2 QUI R18 5 03 REFOUT 155 X R2 RSET R18 D ARET 8 27 1 QUIS 5 5 1 06 AVSS Z 4 pe 10 55 AEE fi t m Jw p GND QUT4 3 12 aio 5741 01 O 01uFCAP QUIA 2 Ris 147 01 15 00 U5 R30 CLK 16 vec 4 4 DVEE 17 35 0755 Dvss2 GND HIS741 DJ0058 J8 lt GND 0 0058 VEE VEE J7 1 3 30 intersil HSP50215EVAL ICS Continued E Detailed Schemat Appendix 1 4 decoupling caps perActel 1 per side 9 ca 09 610 Cl er 0 01 NP 0 01 NP 0 01 0 01 NP G C1TNP gt o Ld I 1 T EE 2643 c 015 0 01 0 01 0 01 NP 0 01 NP 0 01 NP Ld 5 Ld 1 i T LT og C21 1629 0 01 NP 0 01NP 0 01 NP 0
70. n eo cafe 8 AAA E 2 21312 3888 QEPULLUP 1 Mi CHANNEL 4 HSP50215 MODULATOR E 2535533533395 INPUT VIA pes em ib s 5 C1 0 15 BUS Q ZONE FROM 03 1i orm EELESEELS859585558555 82 _2 2222922020 56605665000 79 000050075 5 NC79 73 m X NC78 77 erie CASZ C15 CASO 5 76 C1 14 6 CASO C14 LB as 71 CAS1 c13 74 3 GND7 NC74 CAS2 g 52 VCC73 75 4 CAS ig CAS3 eor 7 CAS4 11 CAS4 c11 EIS Xi C CASS 69 crs 13 CASS 89 14 GND68 57 era CAS7 15 VCC15 HSP50215 Noss E X GND16 17 64 C16 qg REFCLK C6 55 58 5 C15 CASI 19 Caso 2 1 62 20 ae NC20 u1 0 um CAS10 SAMPCK CASH zx ae 59 C13 23 58 5411 23 c2 37 7 512 55 CAS12 NC57 X 55 CAS13 GND56 zg E NH 27 14 54 CEU 58 CAS15 co NC28 53 X T X zo 29 gt 52 ETX x E s 3 g 8 SYNCOUT X 2 teak unas 5 9 9915992699550 2 20 d 2 ee SS x 8 E di E 3 3 3 lt SYNCIN jaaa jaa FROM JP5 PAGE 4 CEPULLUP_1 FROM RZ1 EE 22 MASTERCLK 1 FROM U11 PAGE 4 lt lt WR x FROM JP9 PAGE 6 FROM J
71. n output calculation and no PRBS pattern is output By lowering the input sample rate again until the PRBS pattern reappears the maximum input sample rate can be determined for your evaluation board oscillator combination Note that a similar process can be used to determine the maximum input rate of each of the example filter files taking care to enter the proper DS and IP values for each filter as noted in Appendix G Descriptive File List Generating User Configurations Now that you understand the basics of controlling this modulator evaluation board you should be able to edit the example configuration and stimulus files to obtain the test figuration you desire Remember that it is best to begin with the files that most closely match the desired configuration Appendix G Descriptive File List has a description of these files 3 11 intersil HSP50215EVAL Detailed Circuit Description The reader should reference the detailed schematics found in Appendix E Detailed Schematics while reading the detailed circuit description Signal Path Modulation Channel 4 Baseband in phase and quadrature I and Q data enters the HSP50215EVAL via the host computer ISA interface sheet 6 and is routed to an ACTEL FPGA U6 U9 on one of the four upconverter channels sheets 1 4 Data enters the HSP50215 Digital UpConverter U1 U2 U3 or U4 from the associated ACTEL FPGA via busses C 15 0 and DUA 9 0 and the WR control
72. n should be checked If the board is properly installed then a verify that no ISAbus card addressing contention exists Steps 9 10 AND 11 are the leading causes of board test fail ure 3 5 intersil HSP50215EVAL Running the Control Software for Evaluation Testing 12 From the MAIN MENU select the first MODULATOR CONFIGURATION MENU item 1 by typing 1 lt En ter gt The MODULATOR CHANNEL 1 CONFIGURA TION MENU will appear It should match the entry found in Figure 6 13 Make any adjustments to the parameters by entering the desired item number for parameter selection and editing each item via the respective parameter entry submenu When editing is complete select item 0 and type lt Enter gt to return to the MAIN MENU File Name Channel 1 5000000 Hz 24300 Hz 1 Carrier Center Freq 2 Input Sample Rate 3 Modulation Type 4 Coef File 5 Interpolation IP 6 Impulse Response Length DS 16 samples 7 Stimulus File STIMULUS QPSKPN 8 9 FILTERS ISA135B 10 Enabled 11 Enabled 12 Internal 13 14 15 Output Format 16 Test Register 0 Main Menu ENTER SELECTION C Intersil Corporation 1997 Version 1 0 FIGURE 6 MODULATOR CHANNEL CONFIGURATION SUB MENU 14 Repeat Steps 12 and 13 for MAIN MENU items 2 15 16 3 and 4 These submenus control Modulator Channels 2 through 4 These submenus are identical to those found under MAI
73. ng the log of the symbol rate converts from C No to Es No The modulation factor converts from Es No to Eb No using the equation 10LOG bits symbol This yields MF 0dB for BPSK MF 3 01dB for QPSK and 4 7788 for 8 PSK An Example Ep No Calculation Data File QPSKPN A 1 0 128ksym sec Noise File GN16K std dev 0 25 400ksamp sec Data filter 15136 DC gain 0 658 NBW 1 004 x FsAMP Noise filter RRC35A4xDC gain 0 5 NBW 0 989 Signal Atten 20 dB 26 256 0 1016 Noise Atten 14 6 dB 48 256 0 1875 Begin by calculating C Ngp 10LOG 1 0x0 658x0 1016 2 2 0 25x0 5x0 1875 2 10LOG 4 4693x109 1 0986x103 6 094dB Continue by calculating Ep No Ep No 6 094 3 01 10LOG 128 000 10LOG 0 989x400000 3 084 51 072 55 973 7 98dB Note that the values for A standard deviation DC gains and noise bandwidths are found in the file headers of the example filter and stimulus files provided When main menu item 7 is executed four configuration files are generated for the various channels These files list the hex values for all of the control registers of the HSP50215 The channel 1 2 3 or 4 is indicated by the file suffix The value of the multiplier for the attenuators is found in Register 17 This value converted to decimal and divided by 256 yields the linear attenuation multiplier value Note that there is an e
74. o operate from a parallel port interface remove jumpers JP6 17 18 and remove jumpers 1 2 and 5 6 from JP9 Install jumpers 3 4 and 7 8 on JP9 Connects the external data bus write signal and the address signals to the appropriate labelled pins on the J9 connector Depending on the length of the cable connected to J9 installation of R13 and 14 as well as C3 and 4 may be desirable to improve the signal quality of the WR and address signals Clocking Jumpered Options Sheet 4 of the schematic contains the jumpers for several clocking configurations JP8 determines the source for the CONNINCLK MASTERCLK and DACCLK clock drivers U11 on the board When JP8 1 2 and 3 4 are installed then the clock source will be either an external source or the on board crystal oscillator and the connector clock is driven by the card These jumpers also route the clock to the output connector J2 When JP8 2 3 is installed the output connector is the source of the clock The configuration shown on the schematic is for internal crystal clock source JP7 determines if the clock source is external or internal The default configuration shown in the schematic is for operation from the internal crystal clock source U10 Termination of the external clock with 50O is done by installing the JP10 jumper Jumper JP5 sets the source for the sync signal Installing jumpers J5 7 8 and 9 10 route the SYNCOUT from Channel 1 to the CASSYNC2 location on J1 and to th
75. ot limit inside the digital upconverter for channel 2 The Gain control can be used to provide sufficient back off The output of the digital upconverter for modulation channel 2 U3 is routed to the cascade input of modulation channel 1 sheet 4 U4 Modulation Channel 1 Sheet 4 of the schematic details the control and access circuitry for modulation channel 1 U4 is the Digital upconverter and U9 is the associated ACTEL FPGA The control software allows Modulation Channel 1 selection of the modulation type QASK bandlimited FM and shaped FM Resampler frequency IF frequency gain control as well as shaping and interpolation filter configuration JP4 and RZ6 provide control and selection for the channel 1 ACTEL FPGA and associated Digital Upconverter U19 and 20 provide the memory storage for data being processed by the ACTEL FPGA Care must be taken to ensure that the cascade input summed with the modulation output of channels 4 through 2 do not limit inside the digital upconverter for channel 1 The Gain control can be used to provide sufficient back off The output of the digital upconverter for modulation channel 1 UA is routed to an output connector J2 and to an DAC U5 found on sheet 5 J2 is the digital output that is the cascaded IF outputs of channels 4 through 1 The DAC output is routed to J5 and provides 500 output at 0 5Vpp Modulation Channel 1 also has an input connector J3 which allows for direct contro
76. r of data samples equal to the length of the test pattern desired and edit a stimulus file to contain the desired data bits starting at location 0 When using one of the AWGN stimulus files identifying a large number of data samples is desirable Use of standard PN leggins such as 27 1 29 1 215 1 will allow a commercial Bit Error Rate Tester to be used on the receive path equipment ITEM 9 OUTPUT ATTENUATION Range is 0 00 to 48 0 more than 48 turns the output off Current Value Current Output Attenuation Setting Enter New Value Current Value This field will control the GAIN CONTROL for the Programmable Upconverter for the channel identified Enter the desired attenuation in dB ITEM 10 OUTPUT Current Value Current Output Enable Setting 0 Disabled 1 Enabled Enter New Value Current Value The field sets the output enable condition for the channel identified ITEM 11 CASCADE INPUT Current Value Current Cascade Input Setting 0 Disabled 1 Enabled Enter New Value Current Value This field is used to set the enable state of the cascade input to the channel identified Remember that channel 4 cascades into channel 3 and likewise channel 3 into channel 2 and channel 2 into channel 1 ITEM 12 SYNC Current Value Current Sync Setting 0 External 1 Internal Enter New Value Current Value This field sets the state of the sync control for the identified channel ITEM 13 SYNC POLARITY Cu
77. rrent Value Current Sync Polarity Setting 0 1 1 L gt H Enter New Value Current Value This field is used to set the Sync polarity for the channel identified ITEM 14 FIFO DEPTH Current Value Current FIFO Depth Setting Range is 1 7 Enter New Value Current Value This field is used to set the and Q FIFO depth on the channel identified ITEM 15 OUTPUT FORMAT Current Value Current Output Format Setting 0 Offset Binary 1 Two s Complement Enter New Value Current Value This field sets the output format of the channel identified ITEM 16 TEST REGISTER Current Value Current Test Register Setting Enter New Value Current Value This field sets the value of Control Register 23 of the channel identified Standard configurations set this field to 0 LOAD CONFIGURATION FILE Current File is Current Configuration File Name Enter New Prefix This field is used to identify a configuration file to be loaded for use or editing See Appendix G Descriptive File List for file format SAVE CONFIGURATION FILE Current File is Current Configuration File Name Enter New Prefix This field is used to save the current configuration as a file Warning If a configuration change has been made and a new file name is not entered the changed configuration will be written over the origi nal file This may destroy example files that are provided with the control software 3 44 intersil HSP50215EV
78. rror introduced due to the 8 bit quantization of the gain control value The error is small for attenuations close to OdB but can be on the order of a tenth of a dB for attenuations greater than 15dB and as much as 1dB at the bottom of the range Exercise 7 PRBS Data This exercise will configure the board to bypass the filter and not upconvert so that the user PRBS data is output This configuration is useful for verifying stimulus files that are short data sequences Go to the main menu Select item and set the following parameters 9 48 O Returns to the main menu This turns channel 1 off Select main menu item 4 and set the following parameters O Returns to the main menu This sets the channel 4 stimulus file to be a 15 bit PRBS The filter was already set to bypass The IF is set to OHZ Select main menu item 7 to compute the register values Select main menu item 8 to configure the board Select submenu item 5 to configure all 4 channels Select sumenu item 3 to load both the modulator and pattern RAM When the submenu reappears the download is complete The output waveform should be the input PRBS data pattern You should note that this configuration can be used to verify the maximum input rate by changing the input sample rate of channel 4 to be fosc 16 Varying the input sample rate will illustrate that with too high of an input sample rate the filter does not have sufficient time to complete a
79. seen on the spectrum analyzer than the scope The CW is set at half the frequency of the modulated signal By turning one of the signals on and off you can convince yourself that the desired combination of signals is present The power of the four channel modulator should now be apparent For signal testing it is possible to generate the signal of interest two adjacent signals and an interferer signal This test configuration is ideal for high signal to noise multi channel applications Exercise 5 A Fourier Series Composite Signal This exercise will demonstrate the use of 3 modulator channels configured as CW tones The fundamental will be set at 124 attenuation the second harmonic at 18dB attenuation and the third harmonic at 24dB attenuation The purpose is to introduce the operator to multiple channel configurations Go to the main menu Select Item 1 and set the following parameters 8 1 9 18 0 Returns to main menu Select Item 2 and set the following parameters 0 Returns to main menu Select Item 3 and set the following parameters 8 1 9 24 0 Returns to main menu Select main menu 7 to compute the register values Select main menu 8 to configure the board Select submenu item 5 to configure all channels Select submenu item 3 to load both the modulator and Pattern RAM When the submenu reappears the download is complete The output is the composite of three CW tones related by harmonics
80. software and start from scratch on the configuration 8 511 9 48 O Returns to main menu This configures channel two to be a 25Kbps PSK modulator at 250kHz but with the RF severely attenuated so as to be effectively turned off The IS136B filter is used here as well as in Channel 1 Select main menu item 3 and set the following parameters 1 750 000Hz 2 75 000Hz 7 Stimulus bpskpn See note below before leaving this item Note If you have not properly identified the stimulus file or the path to that file then the program will not download when you command the software to configure the board and will return you to the DOS prompt at which point you will need to restart the control software and start from scratch on the configuration 8 511 9 48 O Returns to main menu This configures channel three to be a 75Kbps PSK modulator at 750kHz but with the RF severely attenuated so as to be effectively turned off Once again the 5136 filter is used Select Item 4 and set the following parameters 1 500 000Hz 2 501 000Hz 3 QASK 5 6 4 7 Stimulus gn16k See note below before leaving this item o Note If you have not properly identified the stimulus file or the path to that file then the program will not download when you command the software to configure the board and will return you to the DOS prompt at which point you will need to restart the control software and start from scratch on the con
81. st signal levels Go to the main menu Select Item 1 Modulator Channel 1 Configuration and enter the following parameters 9 9 0 Returns to main menu This will reduce the output level by 6dB Select main menu 7 to compute the register values Select main menu 8 to configure the board Select submenu item 1 to configure channel 1 Select submenu item 1 to load the modulator When the submenu reappears the download is complete and the scope or spectrum analyzer should show a single CW tone at 500kHz at with half the amplitude of the signal in Exercise 1 Note that if we had set the value to 48 the channel is effectively turned off Setting the value to 0 is the maximum output level but there is the risk that clipping will occur when other signals are added into the CW tone Exercise 3 Modulating the CW Tone with PN Data This exercise will demonstrate the creation a BPSK signal using a Random PN sequence as a stimulus The BPSK stimulus will write the following values as pairs into the modulator 0 707 0 707 40 707 0 707 This will generate a BPSK signal The purist may wish to edit this file to have the values 1 0 1 0 but the 45 phase offset is not of concern in general The purpose of this exercise is to demonstrate BPSK and provide insight into creating useful test stimulus files as well as to learn techniques for quick test configuration Go to the main menu Select Item 1 and set
82. the following parameters 8 24 9 3 O Returns to main menu This will return the output level to the original setting Select main menu 7 to compute the register values Select main menu 8 to configure the board Select submenu item 1 to configure channel 1 Select submenu item 1 to load the modulator When the submenu reappears the download is complete and the scope or spectrum analyzer should show a filtered modulated signal at an output level of approximately 0 4Vpp There should be 10 IF cycles per baud and the baud rate is 50kHz Notice that it was setting item 8 to 24 that sent PN sequence to the modulator The previous value of 1 held the modulator at CW using an input of either a 0 707 0 707 40 707 0 707 Note that if a particular data pattern is required copying and editing the PN stimulus file for the number of data samples that you desire is a quick way to perform an impulse response or some other useful test pattern such as 1 0 or 1000 Just remember to use the channel configuration menu to only select the number of data samples to match the entries that you have altered in the new file Also selecting a standard PN length 29 1 215 1 allows a commercial Bit Error Rate Tester to be used in conjunction with this modulator in evaluation of the communication link Notice also that the various options for configuring the board are designed to save time during evaluation If the only paramet
83. u Select Item 5 Load Configuration File and enter the following file name and path examples ex01qpsk Enter Select Item 1 Modulator Channel 1 Configuration and enter the following parameters 1 500 000Hz 2 50 000Hz 3 QASK 7 Stimulus bpskpn See note below before leaving this item Note If you have not properly identified the stimulus file or the path to that file then the program will not download when you command the software to configure the board and will return you to the DOS prompt at which point you will need to restart the control software and start from scratch on the configuration 8 1 9 3 0 Returns to main menu This configures channel one input stimulus to be a single bit sampled at 50kHz and applied to a 500kHz QASK modulator with 3dB attenuation The filter has a data span of 16 samples and 16 interpolation phases and is referenced by the filter filename IS136B Notice that it was setting item 8 to 1 that repeatedly sent a single bit to the modulator creating the CW Select main menu item 2 and set the following parameters 1 250 000Hz 2 25 000Hz 3 QASK 7 Stimulus bpskpn See note below before entering this item Note If you have not properly identified the stimulus file or the path to that file then the program will not download when you command the software to configure the board and will return you to the DOS prompt at which point you will need to restart the control

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