PSoC® 4: PSoC 4000 Family Datasheet Programmable System
Contents
1. 1 8Vto 5 5 V PSoC4000 Vop 1pF 0 1uF s Vecp 0 1 uF 1 71V lt Vppio lt Vpp i Vppio 0 1 pF Vss Regulated External Supply In this mode the PSoC 4000 is powered by an external power supply that must be within the range of 1 71 to 1 89 V note that this range needs to include the power supply ripple too In this mode the Vpp and Vccp pins are shorted together and bypassed The internal regulator is disabled in the firmware An example of a bypass scheme follows Vppio is available on the 16 QFN package Figure 8 16 pin QFN Bypass Scheme Example Regulated External Supply Power supply connections when 1 71 lt Vpp lt 1 89 V 1 71 V to 1 89 V PSoC 4000 DD Veep LF 0 1 pF 1 71 V lt Vono lt Voo Vppio 0 1 uF Vss Page 9 of 31 SSS aa F CYPRESS PERFORM Development Support The PSoC 4000 family has a rich set of documentation devel opment tools and online resources to assist you during your development process Visit www cypress com go psoc4 to find out more Documentation A suite of documentation supports the PSoC 4000 family to ensure that you can find answers to your questions quickly This section contains a list of some of the key documents Software User Guide A step by step guide for using PSoC Creator T2. E ak PSoC 4 PSoC 4000 Family CYPRESS PRELIMINARY Datasheet PERFORM XRES Table 7 XRES DC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID77 Vin Input voltage high threshold 0 7 x V CMOS Input VDDD SID78 ViL Input voltage low threshold 0 3 x V CMOS Input VDDD SID79 RpPuLLUP Pull up resistor 3 5 5 6 8 5 kQ SID80 Cin Input capacitance 3 7 pF SID81Pl VuvsxRES Input voltage hysteresis 05 Vpp mV Typical hysteresis is 200 mV for Vpp gt 4 5V Table 8 XRES AC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SiD83FI Tresetwipty Reset pulse width 5 us BID 194 5 TreEsETWAKE _ Wake up time from reset release 3 ms Analog Peripherals Comparator Table 9 Comparator DC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID330 5 lomp4 Block current High Bandwidth mode TBD mA SID33105l lomp2 Block current Low Power mode TBD mA SID33205l VoFESET1 Offset voltage High Bandwidth mode 10 30 mV SID333l5l VoFFSET2 Offset voltage Low Power mode 10 30 V SID334l5l ZcMP DC input impedance of comparator 35 MQ SID338l5l VINP COMP Comparator input range 0 3 6 V Max input voltage is lower of 3 6 V or VoD Table 10 Comparator AC Specifications Guaranteed by Characterization Details Spec ID Parameter Description Min Typ Max Units Conditions SID336l5
3. PERFORM Table 3 DC Specifications continued Details Spec ID Parameter Description Min Typ Max Units Conditions Deep Sleep Mode Vpp 1 8 to 3 6 V Regulator on SID31 Ipp26 C wakeup and WDT on 2 5 pA T 25 C 3 6V SID32 Ipp27 IC wakeup and WDT on TBD pA T 85 C Deep Sleep Mode Vpp 3 6 to 5 5 V Regulator on SID34 Ipp2o IC wakeup and WDT on 2 5 pA T 25 C 5 5V SID35 lpp35 IC wakeup and WDT on 2 5 pA T 25 C 5 5V Deep Sleep Mode Vpp Vccp 1 71 to 1 89 V Regulator bypassed SID37 Ipp32 Pc wakeup and WDT on 2 5 pA T 25 C SID38 Ipp33 I C wakeup and WDT on TBD pA XRES Current SID307 Ipp xR Supply current while XRES asserted 2 5 mA Table 4 AC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID48 Fopu CPU frequency DC 16 MHz 1 71 lt Vpp lt 5 5 SID49Pl TSLEEP Wakeup from Sleep mode 0 HS SID50Pl TpEEPSLEEP Wakeup from Deep Sleep mode 35 HS GPIO Table 5 GPIO DC Specifications referenced to Vppio for 16 Pin QFN Vppio pins Em Details Spec ID Parameter Description Min Typ Max Units Conditions SID57 INS Input voltage high threshold 0 7 x V CMOS Input S ANIME EE E NR RE RR RR SID58 ViL Input voltage low threshold 0 3 x V CMOS Input VDDD SID241 Vi LVTTL input Vppp lt 2 7 V 0 7x V VDDD SID24
4. PERFORM General Description PRELIMINARY PSoC 4 PSoC 4000 Family Datasheet Programmable System on Chip PSoC PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM Cortex M0 CPU It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing The PSoC 4000 product family is the smallest member of the PSoC 4 platform architecture It is a combination of a microcontroller with standard communication and timing peripherals a capacitive touch sensing system CapSense with best in class performance and general purpose analog PSoC 4000 products will be fully upward compatible with members of the PSoC 4 platform for new applica tions and design needs Features 32 bit MCU Subsystem m 16 MHz ARM Cortex M0 CPU m Up to 16 KB of flash with Read Accelerator m Up to 2 KB of SRAM Programmable Analog m Two current DACs IDACs for general purpose or capacitive sensing applications m One low power comparator with internal reference Low Power 1 71 V to 5 5 V operation m Deep Sleep mode with wake up on interrupt and I C address detect Capacitive Sensing m Cypress Capacitive Sigma Delta CSD provides best in class signal to noise ratio SNR and water tolerance m Cypress supplied software component makes capacitive sensing design easy m Automatic hardware tuning SmartSense Serial Communication m
5. External Clock Dx connects to GPIO pin B 4 The Fcpy signal can be divided down to generate synchronous clocks for the analog and digital peripherals There are four clock dividers for the PSoC 4000 each with 16 bit divide capability The 16 bit capability allows flexible generation of fine grained frequency values and is fully supported in PSoC Creator IMO Clock Source The IMO is the primary source of internal clocking in the PSoC 4000 It is trimmed during testing to achieve the specified accuracy The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of 4 MHz The IMO tolerance with Cypress provided calibration settings is 2 24 and 32 MHz ILO Clock Source The ILO is a very low power 40 kHz oscillator which is primarily used to generate clocks for the watchdog timer WDT and peripheral operation in Deep Sleep mode ILO driven counters can be calibrated to the IMO to improve accuracy Cypress provides a software component which does the calibration Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs The watchdog reset is recorded in a Reset Cause register which is firmware readable Reset The PSoC 4000 can be reset from a variety of sources including a software reset Reset events are asynchronous and guarantee reversion t
6. 1 1 1 1 v o CY8C4013LQI 411 16 8 2 1 1 1 1 1 v CY8C4014SXI 411 16 16 2 1 1 1 1 1 v CY8C4014SXI 421 16 16 2 v 1 1 1 1 1 v e CY8C4014LQI 421 16 16 2 v 1 1 1 1 1 v co CY8C4014LQI 412 16 16 2 1 1 1 1 1 v CY8C4014LQI 422 16 16 2 v 1 1 1 1 1 v 5 CY8C4014LQI SLT1 16 16 2 v 1 1 1 1 1 v x CY8C4014LQI SLT2 16 16 2 v 1 1 1 1 1 v Part Numbering Conventions PSoC 4 devices follow the part numbering convention described in the following table All fields are single character alphanumeric 0 1 2 9 AB Z unless stated otherwise The part numbers are of the form CY8CAABCDEF XYZ where the fields are defined as follows Examples 4 PSoC 4 0 4000 Family 1 16 MHz 4 16KB LQ SSOP l Industrial Family Group within Architecture Document Number 001 89638 Rev A CYSC 4 ABCDEF X X X Cypress Prefix Architecture Speed Grade Flash Capacity Package Code Temperature Range Peripheral Set Page 21 of 31 LES E PSoC 4 PSoC 4000 Family NM CYPRESS PRELIMINARY Datasheet PERFORM The Field Values are listed in the following table Field Description Values Meaning
7. 18 System ResoUrces iscir 4 System RESOUNCES iiec tion otn 18 Analog Blocks bh eect race opere 5 Ordering Information eere 21 Fixed Function Digital 5 Part Numbering Conventions essss 21 GPIO wes Q 5 Packaging eese esee esee nnne nnne 23 Special Function Peripherals ssssss 5 Package Outline Drawings eeesss 24 alit c P 6 hiuc e 27 xvi E 9 Document Conventions eee 29 Unregulated External Supply sssse 9 Units of Measure eeens 29 Regulated External Supply sess 9 Revision History Development Support sees 10 Sales Solutions and Legal Information 31 Documentation 000 eee cette centr eeeeeeeetteeeeenaeeeeeneees 10 Worldwide Sales and Design Support 31 eullftemE 10 iier P 31 10 PSoCG Sol tlons 2 recorre 81 a E A 11 Cypress Developer Community OT nn 11 Technical Support seirinin Ol mE 11 direstesies teta E ERR ER eaten 14 Tools Electrical Specifications Absolute Maximum Ratings Device Level Specifications Analog Peripherals Document Number 001 89638
8. CY8C Cypress prefix 4 Architecture 4 PSoC 4 Family 0 4000 Family B CPU speed 1 16 MHz 4 48 MHz C Flash capacity 3 8KB 4 16 KB 5 32 KB 6 64 KB 7 128 KB DE Package code SX SOIC LQ QFN F Temperature range l Industrial XYZ Attributes code 000 999 Code of feature set in specific family Document Number 001 89638 Rev A Page 22 of 31 EE PSoC 4 PSoC 4000 Family P CYPRESS PRELIMINARY Datasheet PERFORM Packaging Table 31 Package List Spec ID Package Description BID 26 QFN 24 24 pin 4 x 4 x 0 6 mm QFN with 0 5 mm pitch BID 33 QFN 16 16 pin 3 x 3 x 0 6 mm QFN with 0 5 mm pitch BID 40 SOIC 16 16 pin 150 Mil SOIC BID 47 SOIC 8 8 pin 150 Mil SOIC Table 32 Package Characteristics Parameter Description Conditions Min Typ Max Units TA Operating ambient temperature 40 25 00 85 C Ty Operating junction temperature 40 100 C TJA Package 0 4 24 pin QFN 38 01 C Watt TJA Package 0 4 16 pin QFN 49 6 C Watt TJA Package 0 4 16 pin SOIC 142 14 C Watt TJA Package 0 4 8 pin SOIC 197 8 C Watt Tuc Package 0 jc 24 pin QFN TBD C Watt Tuc Package 0 c 16 pin QFN Tuc C Watt Tuc Package 0JC 16 pin SOIC Tuc C Watt Tic Package 9 jc 8 pin SOIC Tuc C Watt Table 33 Solder Reflow Peak Temperature Maximum Peak Package Temperature Maximum Time at Peak Temperature Al
9. Conditions SID213 F SWDCLK1 3 3V lt Vpp lt 5 5V 14 MHz SWDCLKs 1 3 CPU clock frequency SID214 F SWDCLK2 1 71 V lt Vpp lt 3 3 V 7 MHz SWDCLKs 1 3 CPU clock frequency sipz15UT r SWDILSETUP T 1 SWDCLK o2 amp T m SID216 0 T SWDI HOLD T 1 f SWDCLK 0 25 T ns SID217U0 T SWDO VALID T 1 f SWDCLK 0 5 T ns SID217All T_ SWDO_HOLD T 1 SWDCLK 1 m ti Internal Main Oscillator Table 25 IMO DC Specifications Guaranteed by Design Spec ID Parameter Description Min Typ Max Units Details Conditions SID218 limot IMO operating current at 48 MHz 7 7 1000 pA SID219 limoz2 IMO operating current at 24 MHz 325 pA Table 26 IMO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID223 FiMoTOL1 Frequency variation at 24 and 2 2V lt Vpp 5 5 V and 32 MHz trimmed 25 C lt Ty lt 85 C SID223A Fimototvecp Frequency variation trimmed 4 All SID226 TsTARTIMO IMO startup time B TBD HS SID228 TJITRMSIMO2 RMS jitter at 24 MHz 145 ps Internal Low Speed Oscillator Table 27 ILO DC Specifications Guaranteed by Design Spec ID Parameter Description Min Typ Max Units Details Conditions Sip231l10 lit 01 ILO operating current 0 3 1 05 yA 1D233170 lit OLEAK ILO leakage current 2 15 nA Table 28 ILO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID234 9l Te RTILO1 ILO startup
10. Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer ass
11. Multi master I C block with the ability to do address matching during Deep Sleep and generate a wake up on match Cypress Semiconductor Corporation Document Number 001 89638 Rev A 198 Champion Court Timing and Pulse Width Modulation m One 16 bit Timer Counter Pulse Width Modulator TCPWM block m Center aligned Edge and Pseudo Random modes m Comparator based triggering of Kill signals for motor drive and other high reliability digital logic applications Up to 20 Programmable GPIO Pins m 24 pin QFN 16 pin SOIC 16 pin QFN and 8 pin SOIC packages m GPIO pins on Ports 0 1 and 2 can be CapSense or have other functions m Drive modes strengths and slew rates are programmable PSoC Creator Design Environment m integrated Development Environment IDE provides schematic design entry and build with analog and digital automatic routing m Applications Programming Interface API component for all fixed function and programmable peripherals Industry Standard Tool Compatibility m After schematic entry development can be done with ARM based industry standard development tools San Jose CA 95134 1709 408 943 2600 Revised February 26 2014 a E PSoC 4 PSoC 4000 Family CYPRESS PRELIMINARY Datasheet To PERFORM Contents Functional Definition eeeeeeeeeereeeeene 4 Digital Peripherals 16 CPU and Memory Subsystem sess 4 iud
12. Power supply input voltage Vccp 1 71 1 89 V Internally unreg Vpp ulated supply SID54 Vppio Vppio domain supply 1 71 Vpp V SID55 CErec External regulator voltage bypass 0 1 uF X5R ceramic or better SID56 CExc Power supply bypass capacitor 1 HF X5R ceramic or better Active Mode Vpp 1 8 to 5 5 V Typical values measured at Vpp 3 3 V SID9 Ipps Execute from flash CPU at 6 MHz x TBD mA SID10 Ippe Execute from flash CPU at 6 MHz ES 2 0 mA T 25 C SID12 Ipps Execute from flash CPU at 12 MHz TBD mA SID13 Ippo Execute from flash CPU at 12 MHz 3 2 mA T 25 C SID16 Ipp44 Execute from flash CPU at 16 MHz s TBD mA SID17 Ipp42 Execute from flash CPU at 16 MHz 4 0 mA T 25 C Sleep Mode Vppp 1 71 to 5 5 V SID25 Ipp20 I C wakeup WDT on 6 MHz 1 1 mA T 25 C SID25A Ipp20A I C wakeup WDT on 12 MHz 1 4 mA T 25 C Note 1 Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability The Maximum Storage Temperature is 150 C in compliance with JEDEC Standard JESD22 A103 High Temperature Storage Life When used below Absolute Maximum conditions but above normal operating conditions the device may not operate to specification Document Number 001 89638 Rev A Page 11 of 31 Se PSoC 4 PSoC 4000 Family CYPRESS PRELIMINARY Datasheet
13. Ratio of counts of finger to noise 5 Ratio Capacitance range of 9 to Guaranteed by characterization 35 pF 0 1 pF sensitivity SID314 IDAC1cRT4 Output current of IDAC1 8 bits in 612 HA high range SID314A IDAC1cnRT2 Output current of IDAC1 8 bits in 306 pA low range SID315 IDAC2cR14 Output current of IDAC2 7 bits in 304 8 HA high range SID315A IDAC2cRT2 Output current of IDAC2 7 bits in 152 4 HA low range SID320 IDACorrset All zeroes input 1 LSB SID321 IDACGAIN Full scale error less offset 10 SID322 IDACyismatcH Mismatch between IDACs 7 LSB SID323 IDACsetg Settling time to 0 5 LSB for 8 bit 10 HS Full scale transition No IDAC external load SID324 IDACsET Settling time to 0 5 LSB for 7 bit 10 us Full scale transition No IDAC external load SID325 CMOD External modulator capacitor 2 2 nF 5 V rating X7R or NPO cap Document Number 001 89638 Rev A Page 15 of 31 LE x PSoC 4 PSoC 4000 Family CYPRESS PRELIMINARY Datasheet PERFORM Digital Peripherals Timer Table 12 Timer DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID115 lTiM1 Block current consumption at 3 MHz 19 pA 16 bit timer SI
14. Rev A Page 2 of 31 ae _ CYPRESS PERFORM PRELIMINARY PSoC 4 PSoC 4000 Family Datasheet Figure 1 Block Diagram PSoC 4000 Cortex MO 16 MHz NVIC IRQMX T AHB Lite System Resources Lite Power Sleep Control Peripherals POR REF PWRSYS Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog Power Modes Active Sleep Deep Sleep PSoC 4000 devices include extensive support for programming testing debugging and tracing both hardware and firmware The ARM Serial Wire Debug SWD interface supports all programming and debug features of the device Complete debug on chip functionality enables full device debugging in the final system using the standard production device It does not require special interfaces debugging pods simulators or emulators Only the standard programming connections are required to fully support debug The PSoC Creator IDE provides fully integrated programming and debug support for the PSoC 4000 devices The SWD interface is fully compatible with industry standard third party tools The PSoC 4000 family provides a level of security not possible with multi chip application solutions or with microcon trollers It has the following advantages m Allows disabling of debug features m Robust flash protection
15. external 125 ns SID135 TerRRESWINT Reset pulse width internal 125 ns SID136 TergnEswExr1 Reset pulse width external 125 ns Pulse Width Modulation PWM Table 16 PWM DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID137 IpwM1 Block current consumption at 3 MHz T 19 pA 16 bit PWM SID138 lpwmM2 Block current consumption at 8 MHz TBD pA 16 bit PWM SID139 lpwmM3 Block current consumption at 12 MHz TBD pA 16 bit PWM Note 6 Guaranteed by characterization Document Number 001 89638 Rev A Page 16 of 31 LES E PSoC 4 PSoC 4000 Family CYPRESS PRELIMINARY Datasheet PERFORM Table 17 PWM AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID140 TPWMFREQ Operating frequency 16 MHz SID141 TPWMPWINT Pulse width internal 125 ns SID142 TPWMEXT Pulse width external 125 ns SID143 TPWMKILLINT Kill pulse width internal 125 ns SID144 TpwMKILLEXT Kill pulse width external 125 ns SID145 TPWMEINT Enable pulse width internal 125 ns SID146 TPWMENEXT Enable pulse width external 125 ns SID147 Tpwmreswint Reset pulse width internal 125 ns SID148 Tpwmreswext Reset pulse width external 125 ns FC Table 18 Fixed I2C DC Specifications Spe
16. m Allows customer proprietary functionality to be implemented in on chip programmable blocks Document Number 001 89638 Rev A Read Accelerator System Interconnect Single Multi Layer AHB PCLK Peripheral Interconnect MMIO SPCIF ROM 4KB SRAM 2KB SRAM Controller Flash 16KB ROM Controller 1x TCPWM 1x SCB 2C IOSS GPIO 4x ports 20 x GPIOs The debug circuits are enabled by default and can only be disabled in firmware If they are not enabled the only way to re enable them is to erase the entire device clear flash protection and reprogram the device with new firmware that enables debugging Additionally all device interfaces can be permanently disabled device security for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences All programming debug and test interfaces are disabled when maximum device security is enabled Therefore PSoC 4000 with device security enabled may not be returned for failure analysis This is a trade off the PSoC 4000 allows the customer to make Page 3 of 31 y E Jf CYPRI ESS Functional Definition CPU and Memory Subsystem CPU The Cortex MO CPU in the PSoC 4000 is part of the 32 bit MCU subsystem which is optimized for low power operation with extensive clock gating Most instructions are
17. protocol IIR infinite impulse response see also FIR ILO internal low speed oscillator see also IMO IMO internal main oscillator see also ILO INL integral nonlinearity see also DNL I O input output see also GPIO DIO SIO USBIO IPOR initial power on reset IPSR interrupt program status register IRQ interrupt request ITM instrumentation trace macrocell LCD liquid crystal display LIN Local Interconnect Network a communications protocol LR link register LUT lookup table LVD low voltage detect see also LVI LVI low voltage interrupt see also HVI LVTTL low voltage transistor transistor logic MAC multiply accumulate MCU microcontroller unit MISO master in slave out NC no connect NMI nonmaskable interrupt NRZ non return to zero NVIC nested vectored interrupt controller NVL nonvolatile latch see also WOL opamp operational amplifier PAL programmable array logic see also PLD Page 27 of 31 LL M au L 2 CYPRESS E PERFORM Table 35 Acronyms Used in this Document continued PRELIMINARY PSoC 4 PSoC 4000 Family Datasheet Table 35 Acronyms Used in this Document continued Document Number 001 89638 Rev A Acronym Description Acronym Description PC program counter SWV single
18. 16 bits in length and the CPU executes a subset of the Thumb 2 instruction set This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex M3 and M4 It includes a nested vectored interrupt controller NVIC block with eight interrupt inputs and also includes a Wakeup Interrupt Controller WIC The WIC can wake the processor from the Deep Sleep mode allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode The CPU also includes a debug interface the serial wire debug SWD interface which is a 2 wire form of JTAG The debug configuration used for PSoC 4000 has four breakpoint address comparators and two watchpoint data comparators Flash The PSoC 4000 device has a flash module with a flash accel erator tightly coupled to the CPU to improve average access times from the flash block The low power flash block is designed to deliver zero wait state WS access time at 16 MHz The flash accelerator delivers 8596 of the single cycle SRAM access performance on average SHAM Two KB of SRAM are provided with zero wait state access at 16 MHz SROM A supervisory ROM that contains boot and configuration routines is provided System Resources Power System The power system is described in detail in the section on Power on page 9 It provides an assurance that voltage levels are as required for each respective mode and either delay
19. 2 Vit LVTTL input Vppp lt 2 7 V 0 3 x V VDDD SID243 Vin LVTTL input Vppp 2 2 7 V 2 0 V SID244 Vit LVTTL input Vppp 2 2 7 V 0 8 V SID59 Vou Output voltage high level Vppp V lon 4 mA at 0 6 3 V Vppp SID60 Vou Output voltage high level Vppp V lon 1 mA at 0 5 1 8 V Vppp SID61 VoL Output voltage low level 7 0 6 V loi 4 mA at 1 8 V Vppp SID62 VoL Output voltage low level x 0 6 V lo 10 mA at Notes 2 Guaranteed by characterization 3 Vi must not exceed Vppp 0 2 V Document Number 001 89638 Rev A Page 12 of 31 EE PSoC 4 PSoC 4000 Family IJ CYPRESS PRELIMINARY Datasheet PERFORM Table 5 GPIO DC Specifications referenced to Vppio for 16 Pin QFN Vppio pins continued ERN A Details Spec ID Parameter Description Min Typ Max Units Conditions SID62A VoL Output voltage low level 0 4 V loL 3 mAat3 V VDDD SID63 RPuLLUP Pull up resistor 3 5 5 6 8 5 kQ SID64 RPULLDOWN Pull down resistor 3 5 5 6 8 5 kQ SID65 lu Input leakage current absolute value 2 nA 25 C Vppp 3 0 V SID66 Cin Input capacitance 3 7 pF siD671 VHYSTTL Input hysteresis LVTTL 15 40 7 mV Vppp 2 2 7 V s D68 VuvscMos Input hysteresis CMOS 0 05 x mV Vpp lt 4 5 V VDDD SID68AM VuvscMossvs Input hysteresis CMOS 200 mV Vpp gt 4 5 V Sipeo l IDIODE Current through protection dio
20. D116 lTiM2 Block current consumption at 8 MHz x TBD pA 16 bit timer SID117 Iri M3 Block current consumption at 16 MHz TBD pA 16 bit timer Table 13 Timer AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID118 TTIMFREQ Operating frequency 16 MHz SID119 TCAPWINT Capture pulse width internal 125 ns SID120 TCAPWEXT Capture pulse width external 125 ns SID121 TTIMRES Timer resolution 65 7 x ns SID122 TTENWIDINT Enable pulse width internal 125 ns SID123 TTENWIDEXT Enable pulse width external 125 ns SID124 Trimreswint Reset pulse width internal 125 ns SID125 TTIMRESEXT Reset pulse width external 125 ns Counter Table 14 Counter DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID126 leTR4 Block current consumption at 3 MHz 19 pA 16 bit Counter SID127 IcrR2 Block current consumption at 8 MHz TBD pA 16 bit Counter SID128 loTR3 Block current consumption at 12 MHz TBD pA 16 bit Counter Table 15 Counter AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID129 TerRFREQ Operating frequency 16 MHz SID130 Tetrewint Capture pulse width internal 125 ns SID131 TcrRPwExr Capture pulse width external 125 ns SID132 TcTRES Counter resolution 65 ns SID133 Tcenwipint Enable pulse width internal 125 ns SID134 TegNwipexr Enable pulse width
21. EC MS 012 PIN 1 ID 4 1 i 4 PACKAGE WEIGHT 0 07gms y2 PART 08 15 STANDARD PKG SZ08 15 LEAD FREE PKG 0 150 3 810 SW8 15 LEAD FREE PKG 0 157 3 987 0 230 5 842 0 244 6 197 Y 5 8 0 189 4 800 0 010 0 264 0 196 4 978 SEATING PLANE 0 016 0 406 me L 061 1 49 0 068 1 727 1 PT J 00040102 1 0 050 1 270 c pou 0 0075 0 190 BSC 0 004 0 102 0 8 0 016 0 406 eh Le e veer ES 0 0098 0 249 0 035 0 889 f 0 0138 0 350 0 01920 487 51 85066 F Page 26 of 31 Document Number 001 89638 Rev A I T c Acronyms Ba Amr CYPRESS PERFORM Table 35 Acronyms Used in this Document PRELIMINARY PSoC 4 PSoC 4000 Family Datasheet Table 35 Acronyms Used in this Document continued Acronym Description abus analog local bus ADC analog to digital converter AG analog global AHB AMBA advanced microcontroller bus archi tecture high performance bus an ARM data transfer bus ALU arithmetic logic unit AMUXBUS analog multiplexer bus API application programming interface APSR application program status register ARMS advanced RISC machine a CPU architectu
22. PIO in addition to their alternate functions listed above The following packages are provided 24 pin QFN 16 pin QFN 16 pin SOIC and 8 pin SOIC Figure 3 24 pin QFN Pinout 2 a o o Kk yr oo 8 oO qd rx a a a a a VDD VSS P0 5 P0 6 P0 7 P1 0 Figure 4 16 Pin QFN Pinout P0 4 VCCD Q e 2 A VDDIO VDD Document Number 001 89638 Rev A Page 7 of 31 YPRESS PRELIMINARY Figure 5 16 Pin SOIC Pinout PSoC 4 PSoC 4000 Family Datasheet 16 SOIC Top View Figure 6 8 Pin SOIC Pinout 8 SOIC Top View Document Number 001 89638 Rev A Page 8 of 31 E c _ 2A SES CYPRESS PERFORM Power The following power system diagrams Figure 7 and Figure 8 show the set of power supply pins as implemented for the PSoC 4000 The system has one regulator in Active mode for the digital circuitry There is no analog regulator the analog circuits run directly from the Vpp input There is a separate regulator for the Deep Sleep mode The supply voltage range is either 1 8 V 5 externally regulated or 1 8 V to 5 5 V unregulated exter nally regulated internally with all functions and circuits operating over that range The Vppjo pin available in the 16 pin QFN package provides a separate voltage domain for the following pins P3 0 P3 1 and P3 2 P3 0 and P3 1 can be I C pins and the chip can thus communicate with an 1 C System running at a different
23. WD CLK 15 P1 3 SDA 11 P1 3 SDA 13 P1 3 SDA I2C Data SWD Data SWD IO SWD IO SWD IO 16 P1 4 UNDO UNDO Underflow Out 17 P1 5 OVFO OVFO Overflow Out 18 P1 6 OVFO U 12 P1 6 OVFO 14 P1 6 OVFO U 7 P1 6 OVFO nOUTO CMPO 90 Sense Comp NDO UNDO nOUTO NDO UNDO Complement of Out Internal Reset nOUTO CMP CMPO 0 nOUTO CMP nOUTO CM OUTO not OUT function during POR must O0 O 0 PO 0 not have load to ground during POR 19 P1 7 MATCH 13 P1 7 MATCH 15 P1 7 MATCH MATCH Match External Clock EXT CLK EXT CLK EXT CLK Out 20 P2 0 16 P2 0 21 P3 0 SDA 14 P3 0 SDA 1 P3 0 SDA 8 P3 0 SDA I2C Data SWD IO SWD IO SWD IO SWD IO SWD IO 22 P3 1 SCL 15 P3 1 SCL 2 P3 1 SCL 1 P3 1 SCL I2C Clock SWD Clock SWD CLK SWD CLK SWD CLK SWD CLK 23 P3 2 16 P3 2 OUTO PWM OUT 0 24 XRES XRES External Reset Document Number 001 89638 Rev A Page 6 of 31 aa PSoC 4 PSoC 4000 Famil a PRELIMINARY Datas Me PERFORM Descriptions of the Pin functions are as follows VDD Power supply for both analog and digital sections VDDIO Where available this pin provides a separate voltage domain see the Power section for details VSS Ground pin VCCD Regulated digital supply 1 8 V 5 Pins belonging to Ports 0 1 and 2 can all be used as CSD sense and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO pins that can be driven by the firmware Pins on Port 3 can be used as G
24. amily Added note stating low power 1 71 V to 5 5 V operation in Features Updated IMO tolerance setting in IMO Clock Source Changed ILO oscillator from 32 kHz to 40 kHz in ILO Clock Source Changed internally regulated voltage range from 2 0 to 5 5 V to 1 8 to 5 5 V Corrected max value of BID46 to 140 Document Number 001 89638 Revision ECN ay 4205791 WKA A 4283569 Updated the description for SID255 Added SID35 in DC Specifications Added BID194 in XRES AC Specifications Added specs for max allowed ripple on power supply in CSD and IDAC Block Specifications Specifications Modified description and conditions for SID223 and SID223A Modified description for SID231 Updated SID237 description and values Updated SID262 description and removed SID256 from Block Specs Updated Ordering Information Added SID338 in Comparator DC Specifications Added SID CSD15 SID CSD16 and SID CSD17 in CSD and IDAC Block Document Number 001 89638 Rev A Page 30 of 31 PSoC 4 PSoC 4000 Family ES CYPRESS PRELIMINARY Datasheet PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at Cypress Locations Products PSoC Solutions Automotive cypress com go automotive psoc cypress com solutions Clocks
25. amp Buffers cypress com go clocks PSoC 1 PSoC 3 PSoC 4 PSoC 5LP Interface cypress com go interface Cypress Developer Community Lighting amp Power Control cypress com go powerpsoc Community Forums Blogs Video Training cypress com go plc Technical Support Memory cypress com go memory PSoC cypress com go psoc cypress com go support Touch Sensing cypress com go touch USB Controllers cypress com go USB Wireless RF cypress com go wireless Cypress Semiconductor Corporation 2013 2014 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation
26. c ID Parameter Description Min Typ Max Units Details Conditions SID149 li2c1 Block current consumption at 100 kHz 10 5 pA SID150 li2c2 Block current consumption at 400 kHz x 135 pA SID152 li2c4 2C enabled in Deep Sleep mode m TBD pA Table 19 Fixed I C AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID153 Fi2c4 Bit rate 400 Kbps Note 7 Guaranteed by characterization Document Number 001 89638 Rev A Page 17 of 31 S ii ER PSoC 4 PSoC 4000 Family CYPRESS PRELIMINARY Datasheet PERFORM Memory Table 20 Flash DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID173 VpE Erase and program voltage 1 71 5 5 V Table 21 Flash AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID174 Tacwemdl Row block write time erase and 20 ms Row block 128 bytes program SID175 Tassos Row erase time 13 ms SID176 TROWPROCRAMS Row program time after erase 7 ms SID178 TBULKERASEHI Bulk erase time 16 KB a TBD ms SID180l Tpevproc l Total device program time TBD seconds S D181M1 FEND Flash endurance 100 K cycles SID182Pl FRET Flash retention Ta lt 55 C 100K 20 years P E cycles SID182A 1 Flash ret
27. de to 7 100 pA Vpp Vss SID69AMI lror GPIO Maximum total source or sink chip 85 mA current Table 6 GPIO AC Specifications Guaranteed by Characterization Details Spec ID Parameter Description Min Typ Max Units Conditions SID70 TRISEF Rise time in fast strong mode 2 12 ns 3 3 V Vppp Cload 25 pF SID71 TFALLF Fall time in fast strong mode 2 12 ns 3 3 V Vppp Cload 25 pF SID72 TRISES Rise time in slow strong mode 10 60 3 3 V Vppp Cload 25 pF SID73 TFALLS Fall time in slow strong mode 10 60 3 3 V Vppp Cload 25 pF SID74 FGPIoUT4 GPIO Four 3 3V lt Vbppp 5 5 V 16 MHz 90 1 096 25 pF Fast strong mode load 60 40 duty cycle SID75 Fepiout2 GPIO Four 1 71 V lt Vppp lt 3 3 V ix 16 MHz 90 1 096 25 pF Fast strong mode load 60 40 duty cycle SID76 F GPIOUT3 GPIO Four 3 3 V lt Vppp 5 5 V 7 MHz 90 1 096 25 pF Slow strong mode load 60 40 duty cycle SID245 FGPIOUT4 GPIO Four 1 71 V lt Vppp x 3 3 V 3 5 MHz 90 10 25 pF Slow strong mode load 60 40 duty cycle SID246 FGPIOIN GPIO input operating frequency 16 MHz 90 10 Vig 1 71 V lt Vppp lt 5 5 V Note 4 Guaranteed by characterization Document Number 001 89638 Rev A Page 13 of 31 _ _ oe M lt A
28. e latest information on the revolutionary easy to use PSoC Creator IDE supported third party compilers programmers debuggers and development kits Page 10 of 31 EE PSoC 4 PSoC 4000 Family ES CYPRESS PRELIMINARY Datasheet PERFORM Electrical Specifications Absolute Maximum Ratings Table 2 Absolute Maximum Ratings Spec ID Parameter Description Min Typ Max Units Ens SID1 Vppp ABS Digital supply relative to Vss 0 5 6 V SID2 Vccp ABS Direct digital core voltage input relative 0 5 1 95 V to Vss SID3 VGPiO ABS GPIO voltage 0 5 mi Vpp 0 5 V SIDA IGPIO_ABS Maximum current per GPIO 25 25 mA SID5 IGPIO injection GPIO injection current Max for Vip gt 0 5 0 5 mA Current injected Vppp and Min for Vij lt Vss per pin BID44 ESD_HBM Electrostatic discharge human body 2200 V model BID45 ESD_CDM Electrostatic discharge charged device 500 V model BID46 LU Pin current for latch up 140 140 mA Device Level Specifications All specifications are valid for 40 C x Ty lt 85 C and T x 100 C except where noted Specifications are valid for 1 71 V to 5 5 V except where noted Table 3 DC Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions SID53 Vpp Power supply input voltage 1 8 5 5 V With regulator enabled SID255 Vpp
29. ention TA lt 85 C 10K 10 years P E cycles System Resources Power on Reset POR Table 22 Power On Reset PRES Spec ID Parameter Description Min Typ Max Units Details Conditions SID185l VRISEIPOR Rising trip voltage 0 80 1 5 V SID186l VEALLIPOR Falling trip voltage 0 75 1 4 V SID187P9 Vipornyst Hysteresis 50 mV Table 23 Brown out Detect BOD for Vccp Spec ID Parameter Description Min Typ Max Units Details Conditions SID190l VFALLPPOR BOD trip voltage in active and 1 48 TBD V sleep modes SID192I7 VFALLDPSLP BOD trip voltage in Deep Sleep 1 14 1 5 V Notes 8 Itcan take as much as 20 milliseconds to write to Flash During this time the device should not be Reset or Flash operations will be interrupted and cannot be relied onto have completed Reset sources include the XRES pin software resets CPU lockup states and privilege violations improper power supply levels and watchdogs Make certain that these are not inadvertently activated 9 Guaranteed by characterization Document Number 001 89638 Rev A Page 18 of 31 ee PSoC 4 PSoC 4000 Family CYPRESS PRELIMINARY Datasheet PERFORM SWD Interface Table 24 SWD Interface Specifications Spec ID Parameter Description Min Typ Max Units Details
30. he software user guide shows you how the PSoC Creator build process works in detail how to use source control with PSoC Creator and much more Component Datasheets The flexibility of PSoC allows the creation of new peripherals components long after the device has gone into production Component data sheets provide all of the information needed to select and use a particular component including a functional description API documentation example code and AC DC specifications Application Notes PSoC application notes discuss a particular application of PSoC in depth examples include brushless DC motor control and on chip filtering Application notes often include example projects in addition to the application note document Document Number 001 89638 Rev A PRELIMINARY PSoC 4 PSoC 4000 Family Datasheet Technical Reference Manual The Technical Reference Manual TRM contains all the technical detail you need to use a PSoC device including a complete description of all PSoC registers The TRM is available in the Documentation section at www cypress com psoc4 Online In addition to print documentation the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world 24 hours a day 7 days a week Tools With industry standard cores programming and debugging interfaces the PSoC 4000 family is part of a development tool ecosystem Visit us at www cypress com go psoccreator for th
31. ion to reading from and writing to an array in memory In addition the block supports an 8 deep FIFO for receive and transmit which by increasing the time given for the CPU to read data greatly reduces the need for clock stretching caused by the CPU not having read data on time Thel C peripheral is compatible with the 12C Standard mode and Fast mode devices as defined in the NXP I C bus specification and user manual UM10204 The I C bus I O is implemented with GPIO in open drain modes Document Number 001 89638 Rev A PRELIMINARY PSoC 4 PSoC 4000 Family Datasheet The PSoC 4000 is not completely compliant with the 2c spec in the following respect m GPIO cells are not overvoltage tolerant and therefore cannot be hot swapped or powered up independently of the rest ofthe c System GPIO The PSoC 4000 has up to 20 GPIOs The GPIO block imple ments the following m Eight drive modes a Analog input mode input and output buffers disabled a Input only a Weak pull up with strong pull down a Strong pull up with weak pull down a Open drain with strong pull down a Open drain with strong pull up a Strong pull up with strong pull down a Weak pull up with weak pull down m Input threshold select CMOS or LVTTL m Individual control of input and output buffer enabling disabling in addition to the drive strength modes m Selectable slew rates for dV dt related noise control to improve EMI The pins are orga
32. l 260 C 30 seconds Table 34 Package Moisture Sensitivity Level MSL IPC JEDEC J STD 020 Package MSL All MSL 3 Document Number 001 89638 Rev A Page 23 of 31 Aes PSoC 4 PSoC 4000 Family L wt 7 CYPRESS PRELIMINARY Datasheet PERFORM Package Outline Drawings Figure 9 24 pin QFN EPAD Sawn Package Outline 4 00 0 10 24 19 19 24 LA PIN S L i 78 S E PIN JT 2 i E 2 i mun zT D Cd uus EE LOT OODdLS 12 ma 0 05 MAX A P 0 400 10 gt JE NOTES 1 588 HATCH IS SOLDERABLE EXPOSED METAL 2 REFERENCE JEDEC 4 VO 248 3 PACKAGE WEIGHT 29 3 mg 4 ALL DIMENSIONS ARE IN MILLIMETERS 001 13937 E The center pad on the QFN package should be connected to ground VSS for best mechanical thermal and electrical performance If not connected to ground it should be electrically floating and not connected to any other signal Note 12 Dimensions of the QFN package drawings are in millimeters Document Number 001 89638 Rev A Page 24 of 31 LR E PSoC 4 PSoC 4000 Family CYPRESS PRELIMINARY Datasheet PERFORM Figure 10 16 pin QFN Package EPAD Sawn IOP VIEW SIDE VIEW BOTTOM VIEW 3 0050 10 4 0 50 0 10 16 13 r i ce PIN 1 ID 1 9 12 EXXXXXEN Elsass PIN 1 DOT E gt dt 3 1 70 0 10 S g
33. l Interface a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug a test protocol Page 28 of 31 X PSoC 4 PSoC 4000 Family ES CYPRESS PRELIMINARY Datasheet Document Conventions Units of Measure Table 36 Units of Measure Symbol Unit of Measure C degrees Celsius dB decibel fF femto farad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz kQ kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz MO mega ohm Msps megasamples per second HA microampere uF microfarad uH microhenry Hs microsecond uV microvolt uW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt Q ohm pF picofarad ppm parts per million ps picosecond S second sps samples per second sqrtHz square root of hertz V volt Document Number 001 89638 Rev A Page 29 of 31 Revision History Orig of Change PRELIMINARY Submission Date 12 20 2013 02 26 2014 PSoC 4 PSoC 4000 Family Datasheet Description of Change Updated Low power Comparators section WKA FF AS CYPRESS PERFORM Description Title PSoC 4 PSoC 4000 Family Datasheet Programmable System on Chip PSoC New datasheet for new device f
34. l Tcomp1 Response Time High Bandwidth mode 50 ns 50 mV overdrive SID337l5 Tcomp2 Response Time Low Power mode 100 ns 50 mV overdrive Page 14 of 31 Note 5 Guaranteed by characterization Document Number 001 89638 Rev A a Fy LR E PSoC 4 PSoC 4000 Family CYPRESS PRELIMINARY Datasheet PERFORM CSD Table 11 CSD and IDAC Block Specifications Details Spec ID Parameter Description Min Typ Max Units Conditions CSD and IDAC Specifications SYS PERZ3 VDD RIPPLE Max allowed ripple on power supply 50 mV VDD gt 2V with ripple DC to 10 MHz 25 C Ta Sensitivity 0 1 pF SYS PER 16 VDD_RIPPLE_1 8 Max allowed ripple on power supply 25 mV VDD gt 1 75V with DC to 10 MHz ripple 25 C T4 Parasitic Capacitance Cp 20 pF Sensitivity 2 0 4 pF SID CSD 15 VREF Voltage reference for CSD and 1 1 1 2 1 3 V Comparator SID CSD 16 IDAC1IDD IDAC1 8 bits block current 1125 HA SID CSD 17 IDAC2IDD IDAC2 7 bits block current 1125 HA SID308 Vcsp Voltage range of operation 1 71 5 5 V 1 8 V 5 or 1 8 V to 5 5 V SID308A VCOMPIDAC Voltage compliance range of IDAC 0 8 Vpp 0 8 V SID309 IDAC1 DNL DNL for 8 bit resolution 1 1 LSB SID310 IDAC1iNL INL for 8 bit resolution 3 3 LSB SID311 IDAC2pwL DNL for 7 bit resolution 1 1 LSB SID312 IDAC2iNL INL for 7 bit resolution 3 3 LSB SID313 SNR
35. nized in logical entities called ports which are 8 bit in width less for Ports 2 and 3 During power on and reset the blocks are forced to the disable state so as not to crowbar any inputs and or cause excess turn on current A multiplexing network known as a high speed I O matrix is used to multiplex between various signals that may connect to an I O pin Data output and pin state registers store respectively the values to be driven on the pins and the states of the pins themselves Every I O pin can generate an interrupt if so enabled and each I O port has an interrupt request IRQ and interrupt service routine ISR vector associated with it 4 for PSoC 4000 Special Function Peripherals CapSense CapSense is supported in the PSoC 4000 through a CSD block that can be connected to up to 16 pins through an analog mux bus via an analog switch pins on Port 3 are not available for CapSense purposes CapSense function can thus be provided on any available pin or group of pins in a system under software control A PSoC Creator component is provided for the CapSense block to make it easy for the user Shield voltage can be driven on another mux bus to provide water tolerance capability Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input Proximity sensing can also be implemented The CapSense block has two IDACs which can be u
36. o a known state The reset cause is recorded ina register which is sticky through reset and allows software to determine the cause of the reset An XRES pin is reserved for external reset on the 24 pin package An internal POR is provided on the 16 pin and 8 pin packages The XRES pin has an internal pull up resistor that is always enabled Voltage Reference The PSoC 4000 reference system generates all internally required references A 1 2 V voltage reference is provided for the comparator The IDACs are based on a 5 reference Page 4 of 31 SSS Br Sa CYPRESS r M PERFORM Analog Blocks Low power Comparators The PSoC 4000 has a low power comparator which uses the built in voltage reference Any one of up to 16 pins can be used as a comparator input and the output of the comparator can be brought out to a pin The selected comparator input is connected to the minus input of the comparator with the plus input always connected to the 1 2 V voltage reference Current DACs The PSoC 4000 has two IDACs which can drive any of up to 16 pins on the chip These IDACs have programmable current ranges Analog Multiplexed Buses The PSoC 4000 has two concentric independent buses that go around the periphery of the chip These buses called amux buses are connected to firmware programmable analog switches that allow the chip s internal resources IDACs comparator to connect to any
37. pin on Ports 0 1 and 2 Fixed Function Digital Timer Counter PWM TCPWM Block The TCPWM block consists of a 16 bit counter with user programmable period length There is a capture register to record the count value at the time of an event which may be an I O event a period register that is used to either stop or auto reload the counter when its count is equal to the period register and compare registers to generate compare value signals that are used as PWM duty cycle outputs The block also provides true and complementary outputs with programmable offset between them to allow use as dead band programmable complementary PWM outputs It also has a Kill input to force outputs to a predetermined state for example this is used in motor drive systems when an over current state is indicated and the PWM driving the FETs needs to be shut off immediately with no time for software intervention Serial Communication Block SCB The PSoC 4000 has a serial communication block which imple ments a multi master 12C interface I C Mode The hardware I C block implements a full multi master and slave interface it is capable of multi master arbitration This block is capable of operating at speeds of up to 400 kbps Fast Mode and has flexible buffering options to reduce interrupt overhead and latency for the CPU It also supports EZI2C that creates a mailbox address range in the memory of the PSoC 4000 and effectively reduces I C commu nicat
38. re ATM automatic thump mode BW bandwidth CAN Controller Area Network a communications protocol CMRR common mode rejection ratio CPU central processing unit CRC cyclic redundancy check an error checking protocol DAC digital to analog converter see also IDAC VDAC DFB digital filter block DIO digital input output GPIO with only digital capabilities no analog See GPIO DMIPS Dhrystone million instructions per second DMA direct memory access see also TD DNL differential nonlinearity see also INL DNU do not use DR port write data registers DSI digital system interconnect DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read only memory EMI electromagnetic interference EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge Document Number 001 89638 Rev A Acronym Description ETM embedded trace macrocell FIR finite impulse response see also IIR FPB flash patch and breakpoint FS full speed GPIO general purpose input output applies to a PSoC pin HVI high voltage interrupt see also LVI LVD IC integrated circuit IDAC current DAC see also DAC VDAC IDE integrated development environment C or IIC Inter Integrated Circuit a communications
39. s mode entry for example on power on reset POR until voltage levels are as required for proper functionality or generates resets for example on brown out detection The PSoC 4000 operates with a single external supply over the range of either 1 8 V 5 externally regulated or 1 8 to 5 5 V internally regulated and has three different power modes transitions between which are managed by the power system The PSoC 4000 provides Active Sleep and Deep Sleep low power modes All subsystems are operational in Active mode The CPU subsystem CPU flash and SRAM is clock gated off in Sleep mode while all peripherals and interrupts are active with instan taneous wake up on a wake up event In Deep Sleep mode the high speed clock and associated circuitry is switched off wake up from this mode takes 35 US Clock System Document Number 001 89638 Rev A PRELIMINARY PSoC 4 PSoC 4000 Family Datasheet The PSoC 4000 clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching In addition the clock System ensures that there are no metastable conditions The clock system for the PSoC 4000 consists of the internal main oscillator IMO and the internal low frequency oscillator ILO and provision for an external clock Figure 2 PSoC 4000 MCU Clocking Architecture IMO Fcpu Divide By 2 4 8
40. sed for general purposes if CapSense is not being used both IDACs are available in that case or if CapSense is used without water tolerance one IDAC is available Page 5 of 31 I T ue L 7 c Pinouts CYPRESS PERFORM PSoC 4 PSoC 4000 Family PRELIMINARY Datasheet The following is the pin list for PSoC 4000 All Port pins support GPIO Ports 0 1 and 2 support CSD CapSense and analog mux bus connections Table 1 PSoC 4000 Pin Descriptions 24 QFN 16 QFN 16 SOIC 8 SOIC Pin Name Pin Name Pin Name Pin Name TCPWM Signals Alternate Functions 1 P0 0 TRINO TRINO Trigger Input O 2 PO 1 TRIN1 1 PO 1 TRIN1 C 3 P0 1 TRIN1 C TRIN1 Trigger CMPO O0 Sense Comp CMPO 0 MPO 0 MPO 0 Input 1 Out 3 PO 2 TRIN2 2 PO 2 TRIN2 4 PO 2 TRIN2 TRIN2 Trigger Input 2 4 P0 3 TRIN3 TRIN3 Trigger Input 3 5 P0 4 TRIN4 3 P0 4 TRIN4 5 P0 4 TRIN4 C 2 P0 4 TRIN4 TRIN4 Trigger CMPO_0 Sense Comp CMPO_O EX CMPO_O EXT MPO_O EXT_ CMPO_O E Input 4 Out External Clock T_CLK _CLK CLK XT_CLK CMOD Cap 6 VCCD 4 VCCD 6 VCCD 3 VCCD 7 VDD 5 VDDIO 7 VDD 4 VDD 8 VSS 6 VDD 8 VSS 5 VSS 9 P0 5 7 VSS 9 P0 5 10 P0 6 8 P0 6 10 P0 6 11 P0 7 12 P1 0 13 P1 1 OUTO 9 P1 1 OUTO 11 P1 1 OUTO 6 P1 1 OUTO OUTO PNM OUT 0 14 P1 2 SCL 10 P1 2 SCL 12 P1 2 SCL I2C SCL SWD Clock SWD CLK SWD CLK S
41. t 4 0 50 0 10 4 9 f 3 O MAR 2 7 0 40 0 10 0 60 MAX DUNS para NOTES RRS HATCH AREA IS SOLDERABLE EXPOSED PA EFERENCE JEDEC 24 ALL DIMENSI ARE ILLIVETE 001 87187 4 PACKAGE WEIGHT See Cypress Package Material Declaration Datasheet PMDD posted on the Cypress web Figure 11 16 pin 150 mil SOIC Package Outline PIN 1 ID 8 H i NDTE 1 DIMENSIONS IN INCHESCMM MAX o 0150 3 8101 2 REFERENCE JEDEC MS 012 015703 9871 3 PACKAGE WEIGHT refer to PMDD spec 001 04308 0 23015 842 0 244 61971 PART amp S1615 STANDARD PKG SZ1615 LEAD FREE PKG 9 16 0 386 9 904 ye x as us 7 SEATING PLANE 001604061 0 06111549 0 068 1 727 DE o004t0 1021 LE 0 05011 2701 0 007510 1901 BSC 0 8 Q01604061 0009810249 0 01380 350 0 004t0 1023 0 0350 8891 0 01280 487 0 009810 2491 51 85068 E Note 13 Dimensions of the QFN package drawings are in inches millimeters Page 25 of 31 Document Number 001 89638 Rev A X7 CYPRESS ee PSoC 4 PSoC 4000 Family PRELIMINARY Datasheet PERFORM Figure 12 8 pin 150 mil SOIC Package Outline 1 DIMENSIONS IN INCHES MM MIN MAX 2 PIN 11D IS OPTIONAL ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3 REFERENCE JED
42. time 2 ms SID236l0I Ti oputy ILO duty cycle 40 50 60 96 SID237 FiLoTRIMA ILO frequency range 20 40 80 kHz Note 10 Guaranteed by characterization Document Number 001 89638 Rev A Page 19 of 31 PSoC 4 PSoC 4000 Family Datasheet PRELIMINARY CYPRESS i Typ Max Units MHz Details Conditions PERFORM Table 29 External Clock Specifications Spec ID Parameter Description Min SiD305 7 ExtClkFreq External clock input frequency 0 SiD306l I ExtCIkDuty Duty cycle measured at Vpp 2 45 55 Table 30 Block Specs Spec ID Parameter Description Min Typ Max Units Details Conditions SID262I111 TCLKSWITCH System clock source switching time 3 4 Periods Note 11 Guaranteed by characterization Document Number 001 89638 Rev A Page 20 of 31 L cx ad PSoC 4 PSoC 4000 Family gy CYPRESS PRELIMINARY Datasheet PERFORM Ordering Information The PSoC 4000 part numbers and features are listed in the following table Features Package g 3 2 o z 9 oO 2 E 2 E 8 a 5 l s8 8 g2 8g2 2i cr z a Slee S z Ex cz lees ics eala cae ME ERE i le Nl oe x u E amp S x ES 9 amp a v ws E qu CY8C4013SXI 400 16 8 2 1 1 v 3 CY8C4013SXI 410 16 8 2 1 1 1 1 1 v CY8C4013SXI 411 16 8 2 1
43. umes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 89638 Rev A Revised February 26 2014 Page 31 of 31 All products and company names mentioned in this document may be the trademarks of their respective holders
44. voltage where Vppio Vpp For example Vpp can be 3 3 V and Vppio can be 1 8 V The PSoC 4000 family allows two distinct modes of power supply operation Unregulated External Supply and Regulated External Supply Unregulated External Supply In this mode the PSoC 4000 is powered by an external power supply that can be anywhere in the range of 1 8 to 5 5 V This range is also designed for battery powered operation For example the chip can be powered from a battery system that starts at 3 5 V and works down to 1 8 V In this mode the internal regulator of the PSoC 4000 supplies the internal logic and the Vecp output of the PSoC 4000 must be bypassed to ground via an external capacitor 0 1 uF X5R ceramic or better Bypass capacitors must be used from Vppp to ground The typical practice for systems in this frequency range is to use a capacitor in the 1 uF range in parallel with a smaller capacitor 0 1 uF for example Note that these are simply rules of thumb and that for critical applications the PCB layout lead induc tance and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing An example of a bypass scheme follows Vppio is available on the 16 QFN package Document Number 001 89638 Rev A PRELIMINARY PSoC 4 PSoC 4000 Family Datasheet Figure 7 16 pin QFN Bypass Scheme Example Unregulated External Supply Power supply connections when 1 8 x Vpp lt 5 5V
45. wire viewer PCB printed circuit board TD transaction descriptor see also DMA PGA programmable gain amplifier THD total harmonic distortion PHUB peripheral hub TIA transimpedance amplifier PHY physical layer TRM technical reference manual PICU port interrupt control unit TTL transistor transistor logic PLA programmable logic array TX transmit PLD programmable logic device see also PAL UART Universal Asynchronous Transmitter Receiver a PLL phase locked loop communications protocol PMDD package material declaration data sheet UDE universal digital block POR power on reset USB Universal Serial Bus PRES precise power on reset USBIO aie PSoC pins used to connect to ep pssudorandom sequence VDAC voltage DAC see also DAC IDAC PS port read data register WDT watchdog timer PSoC Programmable System on Ghip WOL write once latch see also NVL PSRR power supply rejection ratio WRES watchdog timer reset PAM pulsewidth modulator XRES external reset I O pin RAM random access memory XTAL crystal RISC reduced instruction set computing RMS root mean square RTC real time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC CT switched capacitor continuous time SCL 12C serial clock SDA IC serial data S H sample and hold SINAD signal to noise and distortion ratio SIO special input output GPIO with advanced features See GPIO SOC start of conversion SOF start of frame SPI Serial Periphera
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