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DAQ PCI-MIO E Series User Manual

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1. 3 13 Digital I O 3 16 Timing Signal Routing 3 16 Programmable Function Inputs 3 17 Board and RTSI Clocks 3 18 RTSI Triggers 3 18 Chapter 4 Signal Connections I O Connector 4 1 I O Connector Signal Descriptions 4 3 Analog Input Signal Connections 4 11 Types of Signal Sources 4 13 Floating Signal Sources 4 13 Ground Referenced Signal Sources 4 13 Input Configurations
2. 2 1 Board Configuration 2 2 Table of Contents PCI MIO E Series User Manual vi National Instruments Corporation Chapter 3 Hardware Overview Analog Input 3 3 Input Mode 3 3 Input Polarity and Input Range 3 4 Considerations for Selecting Input Ranges 3 7 Dither 3 8 Multichannel Scanning Considerations 3 9 Analog Output 3 11 Analog Output Reference Selection 3 11 Analog Output Polarity Selection 3 11 Analog Output Reglitch Selection 3 12 Analog Trigger
3. xiv Customer Communication xiv Chapter 1 Introduction About the PCI MIO E Series 1 1 What You Need to Get Started 1 2 Software Programming Choices 1 3 National Instruments Application Software 1 3 NI DAQ Driver Software 1 4 Register Level Programming 1 5 Optional Equipment 1 6 Custom Cabling 1 6 Unpacking 1 7 Chapter 2 Installation and Configuration Software Installation 2 1 Hardware Installation
4. 4 41 GPCTR0_GATE Signal 4 42 GPCTR0_OUT Signal 4 42 GPCTR0_UP_DOWN Signal 4 43 GPCTR1_SOURCE Signal 4 43 GPCTR1_GATE Signal 4 44 GPCTR1_OUT Signal 4 45 GPCTR1_UP_DOWN Signal 4 46 FREQ_OUT Signal 4 47 Field Wiring Considerations 4 48 Chapter 5 Calibration Loading Calibration Constants 5 1 Self Calibration 5 2 External Calibration 5 2 Other Considerations 5 3 Appendix A Specifications Appendix B Optional Cable Connector Descri
5. 40 Vrms DC to 1 MHz Glitch energy at midscale transition Magnitude 30 mV Duration 10 s Appendix A Speci cations for PCI MIO 16XE 50 PCI MIO E Series User Manual A 24 National Instruments Corporation Stability Offset temperature coefficient 25 V C Gain temperature coefficient 15 ppm C Onboard calibration reference Level 5 000 V 2 mV actual value stored in EEPROM Temperature coefficient 2 ppm C max Long term stability 15 ppm Digital I O Number of channels 8 input output Compatibility TTL CMOS Digital logic levels Power on state Input High Z Data transfers Programmed I O Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Level Min Max Input low voltage Input high voltage Input low current Input high current 0 V 2 V 0 8 V 5 V 320 A 10 A Output low voltage IOL 24 mA Output high voltage IOH 13 mA 4
6. Short circuit to ground Power on state 0 V External reference input Range 11 V Overvoltage protection 25 V powered on 15 V powered off Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 PCI MIO E Series User Manual A 8 National Instruments Corporation Input impedance 10 k Bandwidth 3 dB 1 MHz Dynamic Characteristics Settling time for full scale step 3 s to 0 5 LSB accuracy Slew rate 20 V s Noise 200 Vrms DC to 1 MHz Glitch energy at midscale transition Magnitude Reglitching disabled 20 mV Reglitching enabled 4 mV Duration 1 5 s Stability Offset temperature coefficient 50 V C Gain temperature coefficient Internal reference 25 ppm C External reference 25 ppm C Onboard calibration reference Level 5 000 V 2 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 15 ppm D
7. 16 bits 1 in 65 536 Maximum sampling rate 20 kS s guaranteed Input signal ranges Input coupling DC Maximum working voltage signal and common mode The common mode signal the average of two signals in a differential pair should remain within 8 V of ground and each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH lt 0 15 gt AISENSE FIFO buffer size 2 048 samples Board Gain Software Selectable Board Range Software Selectable Bipolar Unipolar 1 10 V 0 to 10 V 2 5 V 0 to 5 V 10 1 V 0 to 1 V 100 0 1 V 0 to 0 1 V Appendix A Speci cations for PCI MIO 16XE 50 National Instruments Corporation A 21 PCI MIO E Series User Manual Data transfers DMA interrupts programmed I O DMA modes Scatter gather Configuration memory size 512 words Transfer Characteristics Relative accuracy 0 5 LSB typ 1 LSB max DNL 0 5 LSB typ 1 LSB max No missing codes 16 bits guaranteed Offset err
8. 3 17 Figure 3 12 RTSI Bus Signal Connection 3 19 Figure 4 1 I O Connector Pin Assignment for the PCI MIO E Series Boards 4 2 Figure 4 2 PCI MIO E Series PGIA 4 12 Figure 4 3 Summary of Analog Input Connections 4 14 Figure 4 4 Differential Input Connections for Ground Referenced Signals 4 16 Figure 4 5 Differential Input Connections for Nonreferenced Signals 4 17 Figure 4 6 Single Ended Input Connections for Nonreferenced or Floating Signals 4 20 Figure 4 7 Single Ended Input Connections for Ground Referenced Signals 4 21 Figure 4 8 Analog Output Connections 4 23 Figure 4 9 Digital I O Connections 4 24 Figure 4 10 Timing I O Connections 4 26 Figure 4 11 Typical Posttriggered Acquisition 4 27 Figure 4 12 Typical Pretriggered Acquisition 4 28 Table of Contents National
9. DAC0OUT AO 0 1 Short circuit to ground 5 at 10 5 at 10 5 V s DAC1OUT AO 0 1 Short circuit to ground 5 at 10 5 at 10 5 V s AOGND AO DGND DO VCC DO 0 1 Short circuit to ground 1 A DIO lt 0 7 gt DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 k pu SCANCLK DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu EXTSTROBE DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI0 TRIG1 DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 9 k pu and 10 k pd PFI1 TRIG2 DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI2 CONVERT DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI3 GPCTR1_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI4 GPCTR1_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu GPCTR1_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI5 UPDATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI6 WFTRIG DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI7 STARTSCAN DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI8 GPCTR0_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI9 GPCTR0_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k
10. 200 pA AIGND AO DAC0OUT AO 0 1 Short circuit to ground 5 at 10 5 at 10 20 V s DAC1OUT AO 0 1 Short circuit to ground 5 at 10 5 at 10 20 V s EXTREF AI 10 k 25 15 AOGND AO DGND DO VCC DO 0 1 Short circuit to ground 1A DIO lt 0 7 gt DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 k pu SCANCLK DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu EXTSTROBE DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI0 TRIG1 AI DIO 10 k Vcc 0 5 35 3 5 at Vcc 0 4 5 at 0 4 1 5 9 k pu and 10 k pd PFI1 TRIG2 DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI2 CONVERT DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu Chapter 4 Signal Connections National Instruments Corporation 4 7 PCI MIO E Series User Manual Table 4 2 shows the I O signal summary for the PCI MIO 16XE 10 PFI3 GPCTR1_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI4 GPCTR1_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu GPCTR1_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI5 UPDATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI6 WFTRIG DIO Vcc 0 5 3 5 at Vc
11. 1 of fullscale range Digital Trigger Compatibility TTL Response Rising or falling edge Pulse width 10 ns min Appendix A Speci cations for PCI MIO 16XE 10 National Instruments Corporation A 19 PCI MIO E Series User Manual RTSI Trigger Lines 7 Bus Interface Type Master slave Power Requirement 5 VDC 5 1 5 A Power available at I O connector 4 65 to 5 25 VDC at 1 A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector 68 pin male SCSI II type Environment Operating temperature 0 to 55 C Storage temperature 55 to 150 C Relative humidity 5 to 90 noncondensing National Instruments Corporation A 20 PCI MIO E Series User Manual PCI MIO 16XE 50 Analog Input Input Characteristics Number of channels 16 single ended or 8 differential software selectable Type of ADC Successive approximation Resolution
12. 4 13 Differential Connection Considerations DIFF Input Configuration 4 15 Differential Connections for Ground Referenced Signal Sources 4 16 Differential Connections for Nonreferenced or Floating Signal Sources 4 17 Single Ended Connection Considerations 4 18 Single Ended Connections for Floating Signal Sources RSE Configuration 4 20 Single Ended Connections for Grounded Signal Sources NRSE Configuration 4 20 Common Mode Signal Rejection Considerations 4 21 Analog Output Signal Connections 4 22 Digital I O Signal Connections 4 23 Table of Contents National Instruments Corporation vii PCI MIO E Series User Manual Power Connections 4 25 Timing Connections 4 25 Pro
13. 10 V 1 5 V 0 to 10 V 2 2 5 V 0 to 5 V 5 1 V 0 to 2 V 10 500 mV 0 to 1 V 20 250 mV 0 to 500 mV 50 100 mV 0 to 200 mV 100 50 mV 0 to 100 mV Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 National Instruments Corporation A 3 PCI MIO E Series User Manual Transfer Characteristics Relative accuracy 0 5 LSB typ dithered 1 5 LSB max undithered DNL 0 5 LSB typ 1 LSB max No missing codes 12 bits guaranteed Offset error Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration 2 5 of reading max Gain 1 with gain error adjusted to 0 at gain 1 0 02 of reading max Amplifier Characteristics Input impedance Normal powered on 100 G in parallel with 100 pF Powered off 820 min Overload 820 min Input bias current 200 pA Input offset current 100 pA State PCI MIO 16E 1 PCI MIO 16E 4 Pregain error after calibration Pregain error before calibration Postgain error after calibration Postgain error before calibration
14. 12 V max 2 5 mV max 0 5 mV max 100 mV max 16 V max 4 0 mV max 0 8 mV max 200 mV max Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 PCI MIO E Series User Manual A 4 National Instruments Corporation CMRR all input ranges DC to 60 Hz Dynamic Characteristics Bandwidth Gain CMRR PCI MIO 16E 1 PCI MIO 16E 4 0 5 95 dB 90 dB 1 100 dB 95 dB 2 106 dB 100 dB Board Small Signal 3 dB Large Signal 1 THD PCI MIO 16E 1 PCI MIO 16E 4 1 6 MHz 600 kHz 1 MHz 350 kHz Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 National Instruments Corporation A 5 PCI MIO E Series User Manual Settling time to full scale step System noise LSBrms not including quantization Crosstalk 80 dB DC to 100 kHz Board Gain Accuracy 0 012 0 5 LSB 0 024 1 LSB 0 098 4 LSB PCI MIO 16E 1 0 5 2 S typ 3 S max 1 5 S typ 2 S max 1 5 S typ 2 S max 1 2 S typ 3 S max 1 5 S typ 2 S max 1 3 S typ 1 5 S max 2 to 50 2 S typ 3 S max 1 5 S typ 2 S max 0 9 S typ 1 S max 100 2 S typ 3 S max 1 5 S typ 2 S max 1 S typ 1 5 S max PCI MIO 16E 4 All 4 S typ 8 S max 4 S max 4 S max Board Gain Dither Off Dither On PCI MIO 16E 1 0 5 to 10 20
15. In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there may be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter DAQ Timing Connections The DAQ timing signals are SCANCLK EXTSTROBE TRIG1 TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 11 Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 12 shows a typical pretriggered DAQ sequence The description for each signal shown in these figures is included later in this chapter Figure 4 11 Typical Posttriggered Acquisition 1 3 0 4 2 TRIG1 STARTSCAN CONVERT Scan Counter Chapter 4 Signal Connections PCI MIO E Series User Manual 4 28 National Instruments Corporation Figure 4 12 Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external analog input multiplexers indicating when the input sign
16. The PCI MIO 16XE 50 supplies two channels of analog output voltage at the I O connector The range is fixed at bipolar 10 V Analog Output Reference Selection PCI MIO 16E 1 and PCI MIO 16E 4 You can connect each D A converter DAC to these PCI MIO E Series boards internal reference of 10 V or to the external reference signal connected to the external reference EXTREF pin on the I O connector This signal applied to EXTREF should be within 11 V You do not need to configure both channels for the same mode Analog Output Polarity Selection PCI MIO 16E 1 and PCI MIO 16E 4 You can configure each analog output channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to Vref at the analog output A bipolar configuration has a range of Vref to Vref at the analog output Vref is the voltage reference used by the DACs in the analog output circuitry and can be either the 10 V onboard reference or an externally supplied reference within 11 V You do not need to configure both channels for the same range Chapter 3 Hardware Overview PCI MIO E Series User Manual 3 12 National Instruments Corporation Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two s complement format In two s complement mode data values written to the analog output channel can be either positive or negative If you select unipolar range data is
17. pu Table 4 2 I O Signal Summary PCI MIO 16XE 10 Continued Signal Name Signal Type and Direction Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias Chapter 4 Signal Connections National Instruments Corporation 4 9 PCI MIO E Series User Manual Table 4 3 shows the I O signal summary for the PCI MIO 16XE 50 GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output Note The tolerance on the 50 k pullup and pulldown resistors is very large Actual value may range between 17 k and 100 k Table 4 3 I O Signal Summary PCI MIO 16XE 50 Signal Name Signal Type and Direction Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias ACH lt 0 15 gt AI 20 G in parallel with 100 pF 25 15 3 nA AISENSE AI 20 G in parallel with 100 pF 25 15 3 nA AIGND AO DAC0OUT AO 0 1 Short circuit to ground 5 at 10 5 at 10 2 V s DAC1OUT AO 0 1 Short circuit to ground 5 at 10 5 at 10 2 V s AOGND AO DGND DO
18. 66 67 68 FREQ_OUT GPCTR0_OUT PFI9 GPCTR0_GATE DGND PFI6 WFTRIG PFI5 UPDATE DGND 5 V DGND PFI1 TRIG2 PFI0 TRIG1 DGND DGND 5 V DGND DIO6 DIO1 DGND DIO4 EXTREF1 DAC1OUT DAC0OUT ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND AIGND ACH7 ACH14 AIGND ACH5 ACH12 AISENSE ACH11 AIGND ACH2 ACH9 AIGND ACH0 1 Not available on PCI MIO 16XE 10 or PCI MIO 16XE 50 Appendix B Optional Cable Connector Descriptions National Instruments Corporation B 3 PCI MIO E Series User Manual Figure B 2 shows the pin assignments for the 50 pin MIO connector This connector is available when you use the SH6850 or R6850 cable assemblies with the PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 or PCI MIO 16XE 50 Figure B 2 50 Pin MIO Connector Pin Assignments 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PFI0 TRIG1 SCANCLK 5 V DIO7 DIO6 DIO5 DIO4 DGND EXTREF
19. Bus Interface 8 8 Data 16 AI Control Data 16 AO Control ADC FIFO EEPROM Address Data Control Analog Input Control EEPROM Control DMA Interface MIO Interface DAQ STC Bus Interface Analog Output Control I O Bus Interface MITE Generic Bus Interface PCI Bus Interface IRQ DMA Address 5 Chapter 3 Hardware Overview PCI MIO E Series User Manual 3 4 National Instruments Corporation channel basis for multimode scanning For example you can configure the circuitry to scan 12 channels four differentially configured channels and eight single ended channels Table 3 1 describes the three input configurations For more information about the three types of input configuration refer to the Analog Input Signal Connections section in Chapter 4 Signal Connections which contains diagrams showing the signal paths for the three configurations Input Polarity and Input Range PCI MIO 16E 1 and PCI MIO 16E 4 These boards have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and Vref where Vref is a positive reference voltage Bipolar input means that the input voltage range is between Vref 2 and Vref 2 The PCI MIO 16E 1 and PCI MIO 16E 4 have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 10 V 5 V Table 3 1 Available Input Configurations for the PCI MIO E Series
20. 0 4 V Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 PCI MIO E Series User Manual A 10 National Instruments Corporation Data transfers DMA interrupts programmed I O DMA modes Scatter gather Triggers Analog Trigger Source ACH lt 0 15 gt external trigger PFI0 TRIG1 Level full scale internal 10 V external Slope Positive or negative software selectable Resolution 8 bits 1 in 256 Hysteresis Programmable Bandwidth 3 dB PCI MIO 16E 1 2 MHz internal 7 MHz external PCI MIO 16E 4 650 kHz internal 3 0 MHz external External input PFI0 TRIG1 Impedance 10 k Coupling DC Protection 0 5 to Vcc 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off Digital Trigger Compatibility TTL Response Rising or fa
21. Chapter 4 Signal Connections PCI MIO E Series User Manual 4 4 National Instruments Corporation EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices PFI0 TRIG1 DGND Input Output PFI0 Trigger 1 As an input this is either one of the Programmable Function Inputs PFIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section later in this chapter The hardware analog trigger is explained in the Analog Trigger section in Chapter 2 Analog trigger is available only on the PCI MIO 16E 1 PCI MIO 16E 4 and the PCI MIO 16XE 10 As an output this is the TRIG1 signal In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input Output PFI1 Trigger 2 As an input this is one of the PFIs As an output this is the TRIG2 signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications PFI2 CONVERT DGND Input Output PFI2 Convert As an input this is one of the PFIs As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occu
22. Your PCI MIO E Series board A D converter ADC measures this output voltage when it performs A D conversions You must reference all signals to ground either at the source device or at the board If you have a floating source you should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors see the Differential Connections for Nonreferenced or Floating Signal Sources section later in this chapter If you have a grounded source you should not reference the signal to AIGND You can avoid this reference by using DIFF or NRSE input configurations Instrumentation Amplifier Measured Voltage Vm PGIA Vin Vin Vm Vin Vin Gain Chapter 4 Signal Connections National Instruments Corporation 4 13 PCI MIO E Series User Manual Types of Signal Sources When configuring the input channels and making signal connections you must first determine whether the signal sources are floating or ground referenced The following sections describe these two types of signals Floating Signal Sources A floating signal source is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floa
23. figure 3 14 below low level analog triggering mode figure 3 14 block diagram 3 13 high hysteresis analog triggering mode figure 3 15 inside region analog triggering mode figure 3 15 low hysteresis analog triggering mode figure 3 15 PFIO TRIG1 pin note 3 13 specifications PCI MIO 16E 1 and PCI MIO 16E 4 A 10 PCI MIO 16XE 10 A 18 AOGND signal analog output connections 4 22 to 4 23 description table 4 3 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 9 B bipolar input See input polarity and range bipolar output 3 11 to 3 12 board configuration 2 2 bulletin board support D 1 bus interface specification PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 25 C cable connector optional 50 pin MIO connector pin assignments figure B 3 68 pin MIO connector pin assignments figure B 2 cables See also I O connectors custom cabling 1 6 to 1 7 field wiring considerations 4 48 calibration 5 1 to 5 3 analog output gain error 5 3 external calibration 5 2 to 5 3 loading calibration constants 5 1 to 5 2 self calibration 5 2 charge injection 3 10 clocks board and RTSI 3 18 commonly asked questions See questions about PCI MIO E Series boards common mode signal rejection 4 21 ComponentWorks application software 1 3 configuration See also input configurations board configuration 2 2 questions about P
24. 35 V 0 4 V 1 000 h Appendix A Speci cations for PCI MIO 16XE 50 National Instruments Corporation A 25 PCI MIO E Series User Manual Frequency scaler 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Data transfers DMA interrupts programmed I O DMA modes Scatter gather Triggers Digital Trigger Compatibility TTL Response Rising or falling edge Pulse width 10 ns min RTSI Trigger Lines 7 Bus Interface Type Master slave Power Requirement 5 VDC 5 1 0 A Power available at I O connector 4 65 to 5 25 VDC at 1 A Appendix A Speci cations for PCI MIO 16XE 50 PCI
25. 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output Table 4 3 I O Signal Summary PCI MIO 16XE 50 Continued Signal Name Signal Type and Direction Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias Chapter 4 Signal Connections National Instruments Corporation 4 11 PCI MIO E Series User Manual Analog Input Signal Connections The analog input signals for the PCI MIO E Series boards are ACH lt 0 15 gt AISENSE and AIGND The ACH lt 0 15 gt signals are tied to the 16 analog input channels of your PCI MIO E Series board In single ended mode signals connected to ACH lt 0 15 gt are routed to the positive input of the board PGIA In differential mode signals connected to ACH lt 0 7 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 gt are routed to the negative input of the PGIA Warning Exceeding the differential and common mode input ranges distorts your input signals Exceeding the maximum input voltage rating can damage the PCI MIO E Series board and the computer National Instruments is NOT liable for any damages resulting from such signal connections The maximum input
26. 50 100 0 25 0 4 0 5 0 8 0 5 0 6 0 7 0 9 PCI MIO 16E 4 0 5 to 5 10 to 20 50 100 0 15 0 2 0 35 0 6 0 5 0 5 0 6 0 8 Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 PCI MIO E Series User Manual A 6 National Instruments Corporation Stability Recommended warm up time 15 min Offset temperature coefficient Pregain 5 V C Postgain 240 V C Gain temperature coefficient 20 ppm C Onboard calibration reference Level 5 000 V 2 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 15 ppm Analog Output Output Characteristics Number of channels 2 voltage Resolution 12 bits 1 in 4 096 Max update rate 1 channel 1 MS s 2 channel 600 kS s 1 MS s system dependent Type of DAC Double buffered multiplying FIFO buffer size PCI MIO 16E 1 2 048 S PCI MIO 16E 4 512 S Data transfers DMA int
27. 57 kHz Gain 100 33 kHz Settling time for full scale step Gain 1 2 10 50 s max to 1 LSB Gain 100 75 s max to 1 LSB System noise including quantization noise Gain 1 2 10 0 5 LSB rms Gain 100 0 8 LSB rms bipolar 1 4 LSB rms unipolar Crosstalk 85 dB max DC to 20 kHz Stability Recommended warm up time 15 min Offset temperature coefficient Pregain 1 V C Postgain 12 V C Gain temperature coefficient 5 ppm C Onboard calibration reference Level 5 000 V 2 0 mV actual value stored in EEPROM Temperature coefficient 2 ppm C max Long term stability 15 ppm Analog Output Output Characteristics Number of channels 2 Resolution 12 bits 1 in 4 096 Max update rate 20 kS s Type of DAC Double buffered 1 000 h Appendix A Speci cations for PCI MIO 16XE 50 National Instruments Corporation
28. A 23 PCI MIO E Series User Manual FIFO buffer size None Data transfers DMA interrupts programmed I O DMA modes Scatter gather Transfer Characteristics Relative accuracy INL 0 5 LSB max DNL 1 LSB max Monotonicity 12 bits guaranteed Offset error After calibration 0 5 mV max Before calibration 85 mV max Gain error relative to calibration reference After calibration 0 01 of output max Before calibration 1 of output max Voltage Output Range 10 V Output coupling DC Output impedance 0 1 max Current drive 5 mA Protection Short circuit to ground Power on state 0 V 85 mV Dynamic Characteristics Settling time to 0 5 LSB 0 01 for full scale step 50 s Slew rate 2 V s Noise
29. AISENSE Vcm Selected Channel in NRSE Configuration Common Mode Noise and Ground Potential Ground Referenced Signal Source PGIA Input Multiplexers Chapter 4 Signal Connections PCI MIO E Series User Manual 4 22 National Instruments Corporation Analog Output Signal Connections The analog output signals are DAC0OUT DAC1OUT EXTREF and AOGND EXTREF is not available on the PCI MIO 16XE 10 or PCI MIO 16XE 50 DAC0OUT is the voltage output signal for analog output channel 0 DAC1OUT is the voltage output signal for analog output channel 1 EXTREF is the external reference input for both analog output channels You must configure each analog output channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel If you do not specify an external reference the channel will use the internal reference You cannot use an external analog output reference with the PCI MIO 16XE 10 or PCI MIO 16XE 50 Analog output configuration options are explained in the Analog Output section in Chapter 3 Hardware Overview The following ranges and ratings apply to the EXTREF input Usable input voltage range 11 V peak with respect to AOGND Absolute maximum ratings 15 V peak with respect to AOGND AOGND is the ground reference signal for both analog output channels and the external reference signal Figure 4 8 shows how to ma
30. AO analog output AOGND analog output ground signal ASIC Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions Glossary National Instruments Corporation G 3 PCI MIO E Series User Manual B BIOS basic input output system BIOS functions are the fundamental level of any PC or compatible computer BIOS functions embody the basic operations needed for successful use of the computer s hardware resources bipolar a signal range that includes both positive and negative values for example 5 V to 5 V C C Celsius CalDAC calibration DAC CH channel pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels cm centimeter CMOS complementary metal oxide semiconductor CMRR common mode rejection ratio a measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB CONVERT convert signal counter timer a circuit that counts external pulses or clock pulses timing CTR counter D D A digital to analog DAC digital to analog converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog vol
31. Configuration Description DIFF A channel configured in DIFF mode uses two analog channel input lines One line connects to the positive input of the board programmable gain instrumentation amplifier PGIA and the other connects to the negative input of the PGIA RSE A channel configured in RSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA is internally tied to analog input ground AIGND NRSE A channel configured in NRSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA connects to the analog input sense AISENSE input Chapter 3 Hardware Overview National Instruments Corporation 3 5 PCI MIO E Series User Manual You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely The software programmable gain on these boards increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate The PCI MIO 16E 1 and PCI MIO 16E 4 have gains of 0 5 1 2 5 10 20 50 and 100 and are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 2 shows the overall input range and precision according to the input range configuration and gain used Table 3 2 Actual Range and Measurement Prec
32. Figure 4 30 GPCTR0_GATE Signal Timing in Edge Detection Mode GPCTR0_OUT Signal This signal is available only as an output on the GPCTR0_OUT pin The GPCTR0_OUT signal reflects the terminal count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 31 shows the timing of the GPCTR0_OUT signal Rising edge polarity Falling edge polarity tw tw 10 ns minimum Chapter 4 Signal Connections National Instruments Corporation 4 43 PCI MIO E Series User Manual Figure 4 31 GPCTR0_OUT Signal Timing GPCTR0_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for general use GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input the GPCTR1_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCT
33. MIO 16XE 10 and PCI MIO 16XE 50 3 7 Table 4 1 I O Signal Summary PCI MIO 16E 1 and PCI MIO 16E 4 4 6 Table 4 2 I O Signal Summary PCI MIO 16XE 10 4 7 Table 4 3 I O Signal Summary PCI MIO 16XE 50 4 9 National Instruments Corporation xi PCI MIO E Series User Manual About This Manual This manual describes the electrical and mechanical aspects of each board in the PCI MIO E Series product line and contains information concerning their operation and programming Unless otherwise noted text applies to all boards in the PCI MIO E Series The PCI MIO E Series includes the following boards PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 PCI MIO 16XE 50 The PCI MIO E Series boards are high performance multifunction analog digital and timing I O boards for PCI bus computers Supported functions include analog input analog output digital I O and timing I O Organization of This Manual The PCI MIO E Series User Manual is organized as follows Chapter 1 Introduction describes the PCI MIO E Series boards lists what you need to get started describes the optional software and optional equipment and explains how to unpack your PCI MIO E Series board Chapter 2 Installation and Configuration explains how to inst
34. MIO E Series User Manual A 26 National Instruments Corporation Physical Dimensions not including connectors 17 5 by 9 9 cm 6 9 by 3 9 in I O connector 68 pin male SCSI II type Environment Operating temperature 0 to 55 C Storage temperature 55 to 150 C Relative humidity 5 to 90 noncondensing National Instruments Corporation B 1 PCI MIO E Series User Manual AppendixB Optional Cable Connector Descriptions This appendix describes the connectors on the optional cables for the PCI MIO E Series boards Figure B 1 shows the pin assignments for the 68 pin MIO connector This connector is available when you use the SH6868 or R6868 cable assemblies with the PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 and PCI MIO 16XE 50 Appendix B Optional Cable Connector Descriptions PCI MIO E Series User Manual B 2 National Instruments Corporation Figure B 1 68 Pin MIO Connector Pin Assignments 1 2 3 4 5 6 7 8 9 10 35 36 37 38 39 40 41 42 43 44 11 12 13 14 15 16 17 18 45 46 47 48 49 50 51 52 53 19 20 23 21 22 24 25 26 27 28 29 30 31 32 33 34 54 55 56 57 58 59 60 61 62 63 64 65
35. PCI MIO E Series User Manual Multifunction I O Boards for PCI Bus Computers January 1997 Edition Part Number 320945B 01 Copyright 1995 1997 National Instruments Corporation All Rights Reserved Click here to comment on this document via the National Instruments website at http www natinst com documentation daq support natinst com E mail info natinst com FTP Site ftp natinst com Web Address http www natinst com BBS United States 512 794 5422 BBS United Kingdom 01635 551422 BBS France 01 48 65 15 59 512 418 1111 Tel 512 795 8248 Fax 512 794 5678 Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 09 527 2321 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 5734815 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 520 2635 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 U K 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 Tel 512 794 0100 Internet Support Bulletin Board Support Fax on Demand Support Telephone Support U S International Offices Important Information Warranty The PCI MIO E Series boards are warranted against defects i
36. Timing 4 39 Figure 4 27 UPDATE Output Signal Timing 4 39 Figure 4 28 UISOURCE Signal Timing 4 40 Figure 4 29 GPCTR0_SOURCE Signal Timing 4 41 Figure 4 30 GPCTR0_GATE Signal Timing in Edge Detection Mode 4 42 Figure 4 31 GPCTR0_OUT Signal Timing 4 43 Figure 4 32 GPCTR1_SOURCE Signal Timing 4 44 Figure 4 33 GPCTR1_GATE Signal Timing in Edge Detection Mode 4 45 Figure 4 34 GPCTR1_OUT Signal Timing 4 45 Figure 4 35 GPCTR Timing Summary 4 46 Figure B 1 68 Pin MIO Connector Pin Assignments B 2 Figure B 2 50 Pin MIO Connector Pin Assignments B 3 Tables Table 3 1 Available Input Configurations for the PCI MIO E Series 3 4 Table 3 2 Actual Range and Measurement Precision PCI MIO 16E 1 and PCI MIO 16E 4 3 5 Table 3 3 Actual Range and Measurement Precision PCI
37. Timing Rising edge polarity Falling edge polarity tw tw 10 ns minimum Chapter 4 Signal Connections PCI MIO E Series User Manual 4 32 National Instruments Corporation Figure 4 18 TRIG2 Output Signal Timing STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 11 and 4 12 for the relationship of STARTSCAN to the DAQ sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter starts if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN will be deasserted toff after the last conversion in the scan is initiated This output is set to tri state at startup Figures 4 19 and 4 20 show the input and output timing requirements for the STARTSCAN sign
38. as the reference node for any of channels ACH lt 0 15 gt in NRSE configuration DAC0OUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 DAC1OUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 EXTREF1 A0GND Input External Reference This is the external reference input for the analog output circuitry This pin is not available on the PCI MIO 16XE 10 or PCI MIO 16XE 50 AOGND Analog Output Ground The analog output voltages are referenced to this node All three ground references AIGND AOGND and DGND are connected together on your PCI MIO E Series board DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply All three ground references AIGND AOGND and DGND are connected together on your PCI MIO E Series board DIO lt 0 7 gt DGND Input or Output Digital I O signals DIO6 and 7 can control the up down signal of general purpose counters 0 and 1 respectively 5 V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The fuse is self resetting SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion in the scanning modes when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal
39. gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier Q questions about PCI MIO E Series boards C 1 to C 6 analog input and output C 2 to C 4 general information C 1 to C 2 installation and configuration C 2 timing and digital I O C 4 to C 6 R reference selection analog output 3 11 referenced single ended input RSE See RSE referenced single ended input register level programming 1 5 reglitch selection 3 12 RSE referenced single ended input description table 3 4 recommended configuration figure 4 14 single ended connections for floating signal sources 4 20 RTSI clocks 3 18 RTSI triggers 3 18 to 3 19 overview 3 18 RTSI bus signal connections figure 3 19 specifications PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 25 Index National Instruments Corporation I 9 PCI MIO E Series User Manual S SCANCLK signal description table 4 3 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 timing connections 4 28 settling time 3 9 to 3 10 signal connections analog input 4 11 to 4 12 analog output 4 22 to 4 23 digital I O 4 23 to 4 24 field wiring considerations 4 48 input configurations 4 13 to 4 21 common mode signal rejection 4 21 differential connections DIFF input configuration 4 15 floating signal sources 4 17 to 4 18 ground referenced signal sour
40. interpreted in straight binary format In straight binary mode data values written to the analog output channel range must be positive PCI MIO 16XE 10 You can configure each analog output channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to 10 V at the analog output A bipolar configuration has a range of 10 to 10 V at the analog output You do not need to configure both channels for the same range Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two s complement format In two s complement mode data values written to the analog output channel can be either positive or negative If you select unipolar range data is interpreted in straight binary format In straight binary mode data values written to the analog output channel range must be positive Analog Output Reglitch Selection PCI MIO 16E 1 In normal operation a DAC output will glitch whenever it is updated with a new value The glitch energy differs from code to code and appears as distortion in the frequency spectrum Each analog output of the PCI MIO 16E 1 contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum Notice that this reglitch circuit does not eliminate the glitches it only makes
41. is the slowest most difficult and most accurate Loading Calibration Constants Your PCI MIO E Series board is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the board is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ software determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed Chapter 5 Calibration PCI MIO E Series User Manual 5 2 National Instruments Corporation This method of calibration is not very accurate because it does not take into account the fact that the board measurement and output voltage errors can vary with time and temperature It is better to self calibrate when the board is installed in the environment in which it will be used Self Calibration Your PCI MIO E
42. max Gain 10 V Range 0 to 10 V Range 1 to 10 0 6 LSBrms 0 8 LSBrms 20 0 7 LSBrms 1 1 LSBrms 50 1 1 LSBrms 2 0 LSBrms 100 2 0 LSBrms 3 8 LSBrms Appendix A Speci cations for PCI MIO 16XE 10 National Instruments Corporation A 15 PCI MIO E Series User Manual Stability Recommended warm up time 15 min Offset temperature coefficient Pregain 5 V C Postgain 120 V C Gain temperature coefficient 8 ppm C Onboard calibration reference Level 5 000 V 2 0 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm Analog Output Output Characteristics Number of channels 2 voltage Resolution 16 bits 1 in 65 536 Max update rate 100 kS s Type of DAC Double buffered FIFO buffer size 2 048 S Data transfers DMA interrupts programmed I O DMA modes Scatter gather Transfer Characteristics Relative accuracy INL
43. scan A low to high transition indicates the start of the scan PFI8 GPCTR0_SOURCE DGND Input Output PFI8 Counter 0 Source As an input this is one of the PFIs As an output this is the GPCTR0_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTR0_GATE DGND Input Output PFI9 Counter 0 Gate As an input this is one of the PFIs As an output this is the GPCTR0_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 GPCTR0_OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output 1 EXTREF is not available on the PCI MIO 16XE 10 or the PCI MIO 16XE 50 Signal Name Reference Direction Description Continued Chapter 4 Signal Connections PCI MIO E Series User Manual 4 6 National Instruments Corporation Table 4 1 shows the I O signal summary for the PCI MIO 16E 1 and PCI MIO 16E 4 Table 4 1 I O Signal Summary PCI MIO 16E 1 and PCI MIO 16E 4 Signal Name Signal Type and Direction Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias ACH lt 0 15 gt AI 100 G in parallel with 100 pF 25 15 200 pA AISENSE AISENSE2 AI 100 G in parallel with 100 pF 25 15
44. signal description table 4 5 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 Index PCI MIO E Series User Manual I 8 National Instruments Corporation PFIs programmable function inputs 4 26 to 4 27 overview 4 25 questions about PCI MIO E Series boards C 5 to C 6 signal routing 3 17 timing I O connections 4 26 to 4 27 illustration 4 26 PGIA programmable gain instrumentation amplifier analog input connections 4 12 common mode signal rejection 4 21 differential connections floating signal sources 4 17 to 4 18 ground referenced signal sources 4 16 single ended connections floating signal sources figure 4 20 grounded signal sources figure 4 21 physical specifications PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 26 pin assignments optional cable connector 50 pin MIO connector pin assignments figure B 3 68 pin MIO connector pin assignments figure B 2 PCI MIO 16 E Series boards figure 4 2 polarity input polarity and range 3 4 to 3 7 output polarity selection 3 11 to 3 12 posttriggered data acquisition 4 27 illustration 4 27 power connections 4 25 power requirements PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 25 pretriggered data acquisition 4 27 illustration 4 28 programmable function inputs PFIs See PFIs programmable function inputs programmable
45. signals between several functions on as many as five DAQ boards in your computer The PCI MIO E Series boards can interface to an SCXI system so that you can acquire over 3 000 analog signals from thermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control SCXI is the instrumentation front end for plug in DAQ boards Detailed specifications of the PCI MIO E Series boards are in Appendix A Specifications What You Need to Get Started To set up and use your PCI MIO E Series board you will need the following K One of the following boards PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 PCI MIO 16XE 50 K PCI MIO E Series User Manual K One of the following software packages and documentation ComponentWorks LabVIEW for Macintosh1 LabVIEW for Windows LabWindows CVI for Windows Measure NI DAQ for Macintosh1 NI DAQ for PC Compatibles VirtualBench K Your computer 1 Please note that only the PCI MIO 16XE 50 is currently supported on the Macintosh Please contact National Instruments for information on Macintosh support for the other boards in the PCI MIO E Series Chapter 1 Introduction National Instruments Corporation 1 3 PCI MIO E Series User Manual Software Programming Choices You have several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use National Instrume
46. the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Tables 4 1 4 2 and 4 3 These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 will be in the high impedance state after power on and Table 4 1 shows that there is a 50 k pull up resistor This pull up resistor will set the DIO 0 pin to a logic high when the output is in a high impedance state National Instruments Corporation D 1 PCI MIO E Series User Manual AppendixD Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a Fax on Demand system and e mail support If you have a hardware or software problem first try the electronic support systems If the information available on these systems does not answer your questions we offer fax and telephone support through our technical suppor
47. them more uniform in size Reglitching is normally disabled at startup and your software can independently enable each channel Chapter 3 Hardware Overview National Instruments Corporation 3 13 PCI MIO E Series User Manual Analog Trigger PCI MIO 16E 1 PCI MIO 16E 4 and PCI MIO 16XE 10 In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence the PCI MIO 16E 1 PCI MIO 16E 4 and PCI MIO 16XE 10 also support analog triggering You can configure the analog trigger circuitry to accept either a direct analog input from the PFI0 TRIG1 pin on the I O connector or a postgain signal from the output of the PGIA as shown in Figure 3 5 The trigger level range for the direct analog channel is 10 V in 78 mV steps for the PCI MIO 16E 1 and PCI MIO 16E 4 and 10 V in 4 9 mV steps for the PCI MIO 16XE 10 The range for the post PGIA trigger selection is simply the full scale range of the selected channel and the resolution is that range divided by 256 for the PCI MIO 16E 1 and PCI MIO 16E 4 and divided by 4 096 for the PCI MIO 16XE 10 Note The PFI0 TRIG1 pin is an analog input when configured as an analog trigger Therefore it is susceptible to crosstalk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 1 k source imp
48. 0 5 LSB typ 1 LSB max DNL 1 LSB max Monotonicity 16 bits guaranteed Offset error After calibration 305 V max Before calibration 20 mV max 1 000 h Appendix A Speci cations for PCI MIO 16XE 10 PCI MIO E Series User Manual A 16 National Instruments Corporation Gain error relative to internal reference After calibration 30 5 ppm max Before calibration 2 000 ppm max Voltage Output Range 10 V 0 to 10 V software selectable Output coupling DC Output impedance 0 1 max Current drive 5 mA Protection Short circuit to ground Power on state 0 V 20 mV Dynamic Characteristics Settling time for full scale step 10 s to 1 LSB accuracy Slew rate 5 V s Noise 60 Vrms DC to 1 MHz Stability Offset temperature coefficient 50 V C Gain temperature coefficient 7 5 ppm C O
49. 1 DAC0OUT ACH15 ACH14 ACH13 ACH12 ACH11 ACH10 ACH9 ACH8 AIGND EXTSTROBE AIGND ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 AISENSE DAC1OUT AOGND DIO0 DIO1 DIO2 DIO3 DGND 5 V PFI1 TRIG2 PFI3 GPCTR1_SOURCE GPCTR1_OUT PFI6 WFTRIG GPCTR0_OUT PFI2 CONVERT PFI4 GPCTR1_GATE PFI5 UPDATE PFI7 STARTSCAN FREQ_OUT PFI8 GPCTR0_SOURCE PFI9 GPCTR0_GATE 1 Not available on the PCI MIO 16XE 10 or PCI MIO 16XE 50 National Instruments Corporation C 1 PCI MIO E Series User Manual AppendixC Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of your PCI MIO E Series board General Information 1 What are the PCI MIO E Series boards The PCI MIO E Series boards are switchless and jumperless enhanced MIO boards that use the DAQ STC for timing 2 What is the DAQ STC The DAQ STC is the system timing control application specific integrated circuit ASIC designed by National Instruments and is the backbone of the PCI MIO E Series boards The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into three groups Analog input two 24 bit two 16 bit counters Analog output three 24 bit one 16 bit counters General purpose counter timer functions two 24 bit counters The groups can be configured i
50. 24 bit counter timers for timing I O Because the PCI MIO E Series boards have no DIP switches jumpers or potentiometers they are easily software configured and calibrated The PCI MIO E Series boards are completely switchless and jumperless data acquisition DAQ boards for the PCI bus This feature is made possible by the National Instruments MITE bus interface chip that connects the board to the PCI I O bus The MITE implements the PCI Local Bus Specification so that the interrupts and base memory addresses are all software configured The PCI MIO E Series boards use the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns The DAQ STC makes possible such applications as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate Often with DAQ boards you cannot easily synchronize several measurement functions to a common trigger or timing event The PCI MIO E Series boards have the Real Time System Integration RTSI bus to solve this problem The RTSI bus consists of our RTSI Chapter 1 Introduction PCI MIO E Series User Manual 1 2 National Instruments Corporation bus interface and a ribbon cable to route timing and trigger
51. 4 Signal Connections 10 I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal The PCI MIO 16E 1 board has built in reglitchers which can be software enabled on its analog output channels See the Analog Output Reglitch Selection section in Chapter 3 for more information about reglitching 11 Can I synchronize a one channel analog input data acquisition with a one channel analog output waveform generation on my PCI MIO E Series board Yes One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition To do this follow steps a through d below in addition to the usual steps for data acquisition and waveform generation configuration a Enable the PFI5 line for output as follows If you are using NI DAQ call Select_Signal deviceNumber ND_PFI_5 ND_OUT_UPDATE ND_HIGH_TO_LOW If you are using LabVIEW invoke Route Signal VI with signal name set to PFI5 and signal source set to AO Update b Set up data acquisition timing so that the timing sig
52. 7 PCI MIO 16XE 50 4 9 AIGATE signal 4 36 AIGND signal description table 4 3 differential connections for floating signal sources 4 17 to 4 18 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 9 AISENSE signal description table 4 3 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 7 PCI MIO 16XE 50 4 9 amplifier characteristics PCI MIO 16E 1 and PCI MIO 16E 4 A 3 to A 4 PCI MIO 16XE 10 A 13 to A 14 PCI MIO 16XE 50 A 21 analog input 3 3 to 3 10 dither 3 8 to 3 9 signal acquisition effects figure 3 9 input modes 3 3 to 3 4 input polarity and range 3 4 to 3 7 multiple channel scanning considerations 3 9 to 3 10 questions about PCI MIO E Series boards C 2 to C 4 range selection considerations 3 7 signal connections 4 11 to 4 12 specifications PCI MIO 16E 1 and PCI MIO 16E 4 A 1 to A 6 PCI MIO 16XE 10 A 12 to A 15 PCI MIO 16XE 50 A 20 to A 22 analog output hardware overview 3 11 polarity selection 3 11 to 3 12 questions about PCI MIO E Series boards C 2 to C 4 reference selection 3 11 reglitch selection 3 12 signal connections 4 22 to 4 23 specifications PCI MIO 16E 1 and PCI MIO 16E 4 A 6 to A 8 PCI MIO 16XE 10 A 15 to A 16 PCI MIO 16XE 50 A 22 to A 24 Index PCI MIO E Series User Manual I 2 National Instruments Corporation analog trigger 3 13 to 3 16 above high level analog triggering mode
53. 7 programmable function input connections 4 26 to 4 27 waveform generation timing connections 4 37 to 4 40 UISOURCE signal 4 40 UPDATE signal 4 38 to 4 40 WFTRIG signal 4 37 to 4 38 types of signal sources 4 13 floating 4 13 ground referenced 4 13 single ended connections 4 18 to 4 21 description 4 18 to 4 19 floating signal sources RSE 4 20 grounded signal sources NRSE 4 20 to 4 21 when to use 4 19 SISOURCE signal 4 36 to 4 37 software programming choices National Instruments application software 1 3 NI DAQ driver software 1 4 to 1 5 register level programming 1 5 specifications analog input PCI MIO 16E 1 and PCI MIO 16E 4 A 1 to A 6 PCI MIO 16XE 10 A 12 to A 15 PCI MIO 16XE 50 A 20 to A 22 analog output PCI MIO 16E 1 and PCI MIO 16E 4 A 6 to A 8 PCI MIO 16XE 10 A 15 to A 16 PCI MIO 16XE 50 A 22 to A 24 bus interface PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 25 digital I O PCI MIO 16E 1 and PCI MIO 16E 4 A 8 to A 9 PCI MIO 16XE 10 A 17 PCI MIO 16XE 50 A 24 environment PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 26 physical PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 26 power requirements PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 25 RTSI trigger lines PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 25 timing
54. CI MIO E Series boards C 2 connectors See I O connectors CONVERT signal signal routing 3 17 timing connections 4 34 to 4 35 input timing figure 4 35 output timing figure 4 35 counter timer applications C 4 to C 5 custom cabling 1 6 to 1 7 customer communication xiv D 1 to D 2 D DAC0OUT signal analog output connections 4 22 to 4 23 description table 4 3 Index National Instruments Corporation I 3 PCI MIO E Series User Manual I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 9 DAC1OUT signal analog output connections 4 22 to 4 23 description table 4 3 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 9 DAQ timing connections 4 27 to 4 37 AIGATE signal 4 36 CONVERT signal 4 34 to 4 35 EXTSTROBE signal 4 29 SCANCLK signal 4 28 SISOURCE signal 4 36 to 4 37 STARTSCAN signal 4 32 to 4 34 TRIG1 signal 4 29 to 4 30 TRIG2 signal 4 31 to 4 32 typical posttriggered acquisition figure 4 27 typical pretriggered acquisition figure 4 28 DAQ STC system timing control ASIC C 1 C 4 DGND signal description table 4 3 digital I O connections 4 23 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 9 DIFF differential input mode definition table 3 4 description 4 15 ground referenced signal sources 4 16 nonreference
55. CTR0_OUT PFI9 GPCTR0_GATE DGND PFI6 WFTRIG PFI5 UPDATE DGND 5 V DGND PFI1 TRIG2 PFI0 TRIG1 DGND DGND 5 V DGND DIO6 DIO1 DGND DIO4 EXTREF1 DAC1OUT DAC0OUT ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND AIGND ACH7 ACH14 AIGND ACH5 ACH12 AISENSE ACH11 AIGND ACH2 ACH9 AIGND ACH0 1 Not available on PCI MIO 16XE 10 or PCI MIO 16XE 50 Chapter 4 Signal Connections National Instruments Corporation 4 3 PCI MIO E Series User Manual I O Connector Signal Descriptions Signal Name Reference Direction Description AIGND Analog Input Ground These pins are the reference point for single ended measurements in RSE configuration and the bias current return point for differential measurements All three ground references AIGND AOGND and DGND are connected together on your PCI MIO E Series board ACH lt 0 15 gt AIGND Input Analog Input Channels 0 through 15 Each channel pair ACH lt i i 8 gt i 0 7 can be configured as either one differential input or two single ended inputs AISENSE AIGND Input Analog Input Sense This pin serves
56. E Series User Manual 1 6 National Instruments Corporation Optional Equipment National Instruments offers a variety of products to use with your PCI MIO E Series board including cables connector blocks and other accessories as follows Cables and cable assemblies shielded and ribbon Connector blocks shielded and unshielded 50 and 68 pin screw terminals Real Time System Integration RTSI bus cables SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3 072 channels Low channel count signal conditioning modules boards and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more specific information about these products refer to your National Instruments catalogue or call the office nearest you Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change board interconnections If you want to develop your own cable however the following guidelines may be useful For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source You should route the analog lines separately f
57. Floating Signal Source ACH lt 0 15 gt AIGND Instrumentation Amplifier I O Connector AISENSE Selected Channel in RSE Configuration PGIA Input Multiplexers Chapter 4 Signal Connections National Instruments Corporation 4 21 PCI MIO E Series User Manual Figure 4 7 shows how to connect a grounded signal source to a channel on the PCI MIO E Series board configured for NRSE mode Figure 4 7 Single Ended Input Connections for Ground Referenced Signals Common Mode Signal Rejection Considerations Figures 4 4 and 4 7 show connections for signal sources that are already referenced to some ground point with respect to the PCI MIO E Series board In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the board In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the board The PGIA can reject common mode signals as long as V in and V in input signals are both within 11 V of AIGND The PCI MIO 16XE 50 has the additional restriction that V in V in added to the gain times V in V in must be within 26 V of AIGND At gains of 10 and 100 this is roughly equivalent to restricting the two input voltages to within 8 V of AIGND Vs Vm Measured Voltage ACH lt 0 15 gt AIGND Instrumentation Amplifier I O Connector
58. I is externally inputting the source clock This output is set to tri state at startup Figure 4 29 shows the timing requirements for the GPCTR0_SOURCE signal Figure 4 29 GPCTR0_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR0_SOURCE signal unless you select some external source tp tw tw tp tw 50 ns minimum 23 ns minimum Chapter 4 Signal Connections PCI MIO E Series User Manual 4 42 National Instruments Corporation GPCTR0_GATE Signal Any PFI pin can externally input the GPCTR0_GATE signal which is available as an output on the PFI9 GPCTR0_GATE pin As an input the GPCTR0_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTR0_GATE signal reflects the actual gate signal connected to general purpose counter 0 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup Figure 4 30 shows the timing requirements for the GPCTR0_GATE signal
59. I O PCI MIO 16E 1 and PCI MIO 16E 4 A 9 to A 10 PCI MIO 16XE 10 A 17 to A 18 PCI MIO 16XE 50 A 24 to A 25 triggers PCI MIO 16E 1 and PCI MIO 16E 4 A 10 PCI MIO 16XE 10 A 18 PCI MIO 16XE 50 A 25 stability analog input PCI MIO 16E 1 and PCI MIO 16E 4 A 6 PCI MIO 16XE 10 A 15 Index National Instruments Corporation I 11 PCI MIO E Series User Manual PCI MIO 16XE 50 A 22 analog output PCI MIO 16E 1 and PCI MIO 16E 4 A 8 PCI MIO 16XE 10 A 16 PCI MIO 16XE 50 A 24 STARTSCAN signal 4 32 to 4 34 input timing figure 4 33 output timing figure 4 33 T technical support D 1 to D 2 telephone and fax support D 2 theory of operation See hardware overview timebases board and RTSI clocks 3 18 timing connections 4 25 to 4 47 DAQ timing connections 4 27 to 4 37 AIGATE signal 4 36 CONVERT signal 4 34 to 4 35 EXTSTROBE signal 4 29 SCANCLK signal 4 28 SISOURCE signal 4 36 to 4 37 STARTSCAN signal 4 32 to 4 34 TRIG1 signal 4 29 to 4 30 TRIG2 signal 4 31 to 4 32 typical posttriggered acquisition figure 4 27 typical pretriggered acquisition figure 4 28 exceeding maximum input voltage ratings warning 4 25 general purpose timing signal connections 4 40 to 4 47 FREQ_OUT signal 4 47 GPCTR0_GATE signal 4 42 GPCTR0_OUT signal 4 42 to 4 43 GPCTR0_SOURCE signal 4 41 GPCTR0_UP_DOWN signal 4 43 GPCTR1_GATE signal 4 44 to 4 45 GPCTR1_OUT signal 4 45 GPCTR1_SOURCE signal 4 43 to 4 44 GPC
60. I pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 11 and 4 12 for the relationship of STARTSCAN to the DAQ sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC This is true even if the conversions are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 21 and 4 22 show the input and output timing requirements for the CONVERT signal Chapter 4 Signal Connections National Instruments Corporation 4 35 PCI MIO E Series User Manual Figure 4 21 CONVERT Input Signal Timing Figure 4 22 CONVERT Output Signal Timing The ADC switches to hold mode within 60 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next Separate the CONVERT pulses by at least one conversion period The sample interval counter on the PCI MIO E Series board normally generates the CONVERT signal unless you select some external source The counter is started by the STARTSCAN sign
61. IFF input mode The input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA When you configure a channel for differential input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to eight analog input channels are available You should use differential input connections for any channel that meets any of the following conditions The input signal is low level less than 1 V The leads connecting the signal to the PCI MIO E Series board are greater than 10 ft 3 m The input signal requires a separate ground reference point or return signal The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA Chapter 4 Signal Connections PCI MIO E Series User Manual 4 16 National Instruments Corporation Differential Connections for Ground Referenced Signal Sources Figure 4 4 shows how to connect a ground referenced signal source to a channel on the PCI MIO E Series board configured in DIFF input mode Figure 4 4 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both th
62. Instruments Corporation ix PCI MIO E Series User Manual Figure 4 13 SCANCLK Signal Timing 4 28 Figure 4 14 EXTSTROBE Signal Timing 4 29 Figure 4 15 TRIG1 Input Signal Timing 4 30 Figure 4 16 TRIG1 Output Signal Timing 4 30 Figure 4 17 TRIG2 Input Signal Timing 4 31 Figure 4 18 TRIG2 Output Signal Timing 4 32 Figure 4 19 STARTSCAN Input Signal Timing 4 33 Figure 4 20 STARTSCAN Output Signal Timing 4 33 Figure 4 21 CONVERT Input Signal Timing 4 35 Figure 4 22 CONVERT Output Signal Timing 4 35 Figure 4 23 SISOURCE Signal Timing 4 37 Figure 4 24 WFTRIG Input Signal Timing 4 38 Figure 4 25 WFTRIG Output Signal Timing 4 38 Figure 4 26 UPDATE Input Signal
63. R1_SOURCE monitors the actual clock connected to general purpose counter 1 This is true even if the source clock is being externally generated by another PFI This output is set to tri state at startup Figure 4 32 shows the timing requirements for the GPCTR1_SOURCE signal GPCTR0_SOURCE GPCTR0_OUT GPCTR0_OUT Toggle output on TC Pulse on TC TC Chapter 4 Signal Connections PCI MIO E Series User Manual 4 44 National Instruments Corporation Figure 4 32 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 This is true even if the gate is being externally generated by anot
64. Series board can measure and correct for almost all of its calibration related errors without any external signal connections Your National Instruments software provides a self calibration method This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application Initiate self calibration to minimize the effects of any offset gain and linearity drifts particularly those due to warmup Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration Your PCI MIO E Series board has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using your board at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate your board An external calibration refers to calibrating your board with a kn
65. Series boards lt gt Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit port or signal name for example ACH lt 0 7 gt stands for ACH0 through ACH7 Abbreviations acronyms definitions metric prefixes mnemonics symbols and terms are listed in the Glossary at the end of this manual National Instruments Documentation The PCI MIO E Series User Manual is one piece of the documentation set for your DAQ system You could have any of several types of manuals depending on the hardware and software in your system Use the manuals you have as follows Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software Your SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints Your DAQ hardware documentation This documentation has detailed information about the DAQ hardware that plugs into or is connected to your computer Use this documentation for hardware installation and configuration instructions specification information about your DAQ hardware and application hints Software documentation You may have both
66. TR1_UP_DOWN signal 4 46 to 4 47 programmable function input connections 4 26 to 4 27 questions about PCI MIO E Series boards C 4 to C 6 timing I O connections figure 4 26 waveform generation timing connections 4 37 to 4 40 UISOURCE signal 4 40 UPDATE signal 4 38 to 4 40 WFTRIG signal 4 37 to 4 38 timing I O specifications PCI MIO 16E 1 and PCI MIO 16E 4 A 9 to A 10 PCI MIO 16XE 10 A 17 to A 18 PCI MIO 16XE 50 A 24 to A 25 timing signal routing 3 16 to 3 19 board and RTSI clocks 3 18 CONVERT signal routing figure 3 17 programmable function inputs 3 17 RTSI triggers 3 18 to 3 19 transfer characteristics analog input PCI MIO 16E 1 and PCI MIO 16E 4 A 3 PCI MIO 16XE 10 A 13 PCI MIO 16XE 50 A 21 analog output PCI MIO 16E 1 and PCI MIO 16E 4 A 6 to A 7 PCI MIO 16XE 10 A 15 to A 16 PCI MIO 16XE 50 A 23 TRIG1 signal 4 29 to 4 30 input timing figure 4 30 output timing figure 4 30 TRIG2 signal 4 31 to 4 32 input timing figure 4 31 Index PCI MIO E Series User Manual I 12 National Instruments Corporation output timing figure 4 32 triggers analog 3 13 to 3 16 above high level analog triggering mode figure 3 14 below low level analog triggering mode figure 3 14 block diagram 3 13 high hysteresis analog triggering mode figure 3 15 inside region analog triggering mode figure 3 15 low hysteresis analog triggering mode figure 3 15 PFIO TRIG1 pin note 3 13 RTSI trigge
67. VCC DO 0 1 Short circuit to ground 1A DIO lt 0 7 gt DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 k pu Table 4 2 I O Signal Summary PCI MIO 16XE 10 Continued Signal Name Signal Type and Direction Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias Chapter 4 Signal Connections PCI MIO E Series User Manual 4 10 National Instruments Corporation SCANCLK DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu EXTSTROBE DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI0 TRIG1 DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI1 TRIG2 DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI2 CONVERT DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI3 GPCTR1_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI4 GPCTR1_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu GPCTR1_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI5 UPDATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI6 WFTRIG DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI7 STARTSCAN DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI8 GPCTR0_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI9 GPCTR0_GATE DIO Vcc 0
68. _______________ _______________________________________________________________________________ National Instruments hardware product model __________ Revision _______________________ Configuration ___________________________________________________________________ National Instruments software product ___________________________ Version ____________ Configuration ___________________________________________________________________ The problem is __________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ List any error messages ___________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ The following steps reproduce the problem ____________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ ____________________________________
69. ____________________ Phone ___ __________________________ Fax ___ _________________________________ Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 794 5678 Austin TX 78730 5039 Click here to comment on this document via the National Instruments website at http www natinst com documentation daq National Instruments Corporation G 1 PCI MIO E Series User Manual Glossary Symbols Numbers degrees gt greater than greater than or equal to lt less than less than or equal to per percent plus or minus Prefix Meaning Value p pico 10 12 n nano 10 9 micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 Glossary PCI MIO E Series User Manual G 2 National Instruments Corporation positive of or plus negative of or minus ohms square root of 5 V 5 VDC source signal A A amperes AC alternating current ACH analog input channel signal A D analog to digital ADC analog to digital converter an electronic device often an integrated circuit that converts an analog voltage to a digital number AI analog input AIGATE analog input gate signal AIGND analog input ground signal AISENSE analog input sense signal ANSI American National Standards Institute
70. ___________________________________________ _______________________________________________________________________________ Click here to comment on this document via the National Instruments website at http www natinst com documentation daq PCI MIO E Series Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products PCI MIO E Series board ________________________________________________________ PCI MIO E Series board serial number ____________________________________________ Base memory address of PCI MIO E Series board ___________________________________ Interrupt level of PCI MIO E Series board _________________________________________ Programming choice NI DAQ LabVIEW LabWindows CVI or other __________________ Software version ______________________________________________________________ Other Products Computer make and model ______________________________________________________ Microprocessor _______________________________________________________________ Clock frequency or spee
71. ______________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ If you find errors in the manual please record the page numbers and describe the errors _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ Thank you for your help Name _________________________________________________________________________ Title __________________________________________________________________________ Company _______________________________________________________________________ Address ________________________________________________________________________ ___________________________________________________________
72. action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks LabVIEW NI DAQ RTSI ComponentWorks CVI DAQ STC MITE NI PGIA SCXI and VirtualBench are trademarks of National Instruments Corporation Product and company names listed are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components a
73. address listed below Remember to include your name address and phone number so we can contact you with solutions and suggestions support natinst com Fax and Telephone Support National Instruments has branch offices all over the world Use the list below to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 905 785 0085 905 785 0086 Canada Quebec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 09 527 2321 09 502 2930 France 01 48 14 24 24 01 48 14 24 14 Germany 089 741 31 30 089 714 60 35 Hong Kong 2645 3186 2686 8505 Israel 03 5734815 03 5734816 Italy 02 413091 02 41309215 Japan 03 5472 2970 03 5472 2977 Korea 02 596 7456 02 596 7455 Mexico 5 520 2635 5 520 3282 Netherlands 0348 433466 0348 430673 Norway 32 84 84 00 32 84 86 00 Singapore 2265886 2265887 Spain 91 640 0085 91 640 0533 Sweden 08 730 49 70 08 730 43 70 Switzerland 056 200 51 51 056 200 51 55 Taiwan 02 377 1200 02 737 4644 U K 01635 523545 01635 523154 Fax on Demand Support E Mail Support currently U S only Click here to comment on this document via the National Instruments website at http www natinst com document
74. al tw tw 50 100 ns Chapter 4 Signal Connections National Instruments Corporation 4 33 PCI MIO E Series User Manual Figure 4 19 STARTSCAN Input Signal Timing Figure 4 20 STARTSCAN Output Signal Timing Rising edge polarity Falling edge polarity tw tw 10 ns minimum b Scan in Progress Two Conversions per Scan tw 50 100 ns a Start of Scan toff toff 10 ns minimum Start Pulse CONVERT STARTSCAN STARTSCAN tw Chapter 4 Signal Connections PCI MIO E Series User Manual 4 34 National Instruments Corporation The CONVERT pulses are masked off until the board generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT appears when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN generates a conversion The STARTSCAN pulses should be separated by at least one scan period A counter on your PCI MIO E Series board internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIG1 signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate CONVERT Signal Any PF
75. al Connections PCI MIO E Series User Manual 4 14 National Instruments Corporation Figure 4 3 summarizes the recommended input configuration for both types of signal sources Figure 4 3 Summary of Analog Input Connections Input Differential DIFF Single Ended Ground Referenced RSE Single Ended Nonreferenced NRSE Floating Signal Source Not Connected to Building Ground Grounded Signal Source Examples Ungrounded Thermocouples Signal conditioning with isolated outputs Battery devices Examples Plug in instruments with nonisolated outputs V1 ACH V1 ACH ACH See text for information on bias resistors See text for information on bias resistors R Signal Source Type ACH AIGND V1 ACH AIGND NOT RECOMMENDED ACH Vg V1 Ground loop losses Vg are added to measured signal V1 ACH AISENSE R AIGND V1 ACH AISENSE AIGND AIGND Chapter 4 Signal Connections National Instruments Corporation 4 15 PCI MIO E Series User Manual Differential Connection Considerations DIFF Input Configuration A differential connection is one in which the PCI MIO E Series board analog input signal has its own reference signal or signal return path These connections are available when the selected channel is configured in D
76. al and continues to count down and reload itself until the scan is finished It then reloads itself in preparation for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate Rising edge polarity Falling edge polarity tw tw 10 ns minimum t w t w 50 100 ns minimum Chapter 4 Signal Connections PCI MIO E Series User Manual 4 36 National Instruments Corporation AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in either the level detection or edge detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur In the edge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started AIGATE does not gate off conversions until the beginning of the next
77. al has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 13 shows the timing for the SCANCLK signal Figure 4 13 SCANCLK Signal Timing Don t Care 0 1 2 3 1 0 2 2 2 TRIG1 TRIG2 STARTSCAN CONVERT Scan Counter tw tw 400 to 500 ns td 50 to 100 ns td CONVERT SCANCLK Chapter 4 Signal Connections National Instruments Corporation 4 29 PCI MIO E Series User Manual EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of the EXTSTROBE signal A 10 s and a 1 2 s clock are available for generating a sequence of eight pulses in the hardware strobe mode Figure 4 14 shows the timing for the hardware strobe mode EXTSTROBE signal Figure 4 14 EXTSTROBE Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIG1 signal which is available as an output on the PFI0 TRIG1 pin Refer to Figures 4 11 and 4 12 for the relationship of TRIG1 to the DAQ sequence As an input the TRIG1 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG1 signal starts th
78. all and configure your PCI MIO E Series board Chapter 3 Hardware Overview presents an overview of the hardware functions on your PCI MIO E Series board Chapter 4 Signal Connections describes how to make input and output signal connections to your PCI MIO E Series board via the board I O connector Chapter 5 Calibration discusses the calibration procedures for your PCI MIO E Series board About This Manual PCI MIO E Series User Manual xii National Instruments Corporation Appendix A Specifications lists the specifications of each PCI MIO E Series board Appendix B Optional Cable Connector Descriptions describes the connectors on the optional cables for the PCI MIO E Series boards Appendix C Common Questions contains a list of commonly asked questions and their answers relating to usage and special features of your PCI MIO E Series board Appendix D Customer Communication contains forms you can use to request help from National Instruments or to comment on our products The Glossary contains an alphabetical list and description of terms used in this manual including acronyms abbreviations definitions metric prefixes mnemonics and symbols The Index alphabetically lists topics covered in this manual including the page where you can find the topic Convention
79. and EISA It is achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 MB s PFI Programmable Function Input PFI0 TRIG1 PFI0 trigger 1 PFI1 TRIG2 PFI1 trigger 2 PFI2 CONVERT PFI2 convert PFI3 GPCTR1_SOURCE PFI3 general purpose counter 1 source PFI4 GPCTR1_GATE PFI4 general purpose counter 1 gate Glossary PCI MIO E Series User Manual G 8 National Instruments Corporation PFI5 UPDATE PFI5 update PFI6 WFTRIG PFI6 waveform trigger PFI7 STARTSCAN PFI7 start of scan PFI8 GPCTR0_SOURCE PFI8 general purpose counter 0 source PFI9 GPCTR0_GATE PFI9 general purpose counter 0 gate PGIA Programmable Gain Instrumentation Amplifier port 1 a communications connection on a computer or a remote controller 2 a digital port consisting of four or eight lines of digital input and or output ppm parts per million pu pullup R RAM random access memory rms root mean square RSE referenced single ended mode all measurements are made with respect to a common reference measurement system or a ground Also called a grounded measurement system RTD resistive temperature detector a metallic probe that measures temperature based upon its coefficient of resistivity RTSIbus real time system integration bus the National Instruments timing bus that connects DAQ boards directly by means of connectors on top of the boards for precis
80. application software and NI DAQ software documentation National Instruments application software includes ComponentWorks LabVIEW LabWindows CVI Measure and VirtualBench After you set up your hardware system use either your application software documentation or the NI DAQ documentation to help you write your application If you have a large complicated system it is About This Manual PCI MIO E Series User Manual xiv National Instruments Corporation worthwhile to look through the software documentation before you configure your hardware Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXI Chassis Manual If you are using SCXI read this manual for maintenance information on the chassis and installation instructions Related Documentation The following documents contain information you may find helpful DAQ STC Technical Reference Manual National Instruments Application Note 025 Field Wiring and Noise Considerations for Analog Signals PCI Local Bus Specification Revision 2 0 The following National Instruments manual contains detailed information for the register level programmer PCI MIO E Series Register Level Programmer Manual This manual is available
81. ation daq Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name __________________________________________________________________________ Company _______________________________________________________________________ Address ________________________________________________________________________ _______________________________________________________________________________ Fax ___ ___________________ Phone ___ ________________________________________ Computer brand ________________ Model ________________ Processor___________________ Operating system include version number ____________________________________________ Clock speed ______MHz RAM _____MB Display adapter __________________________ Mouse ___yes ___no Other adapters installed _______________________________________ Hard disk capacity _____MB Brand _____________________________________________ Instruments used __________________________________________________
82. ational Instruments Corporation 4 39 PCI MIO E Series User Manual As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 300 to 350 ns This output is set to tri state at startup Figures 4 26 and 4 27 show the input and output timing requirements for the UPDATE signal Figure 4 26 UPDATE Input Signal Timing Figure 4 27 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The PCI MIO E Series board UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter Rising edge polarity Falling edge polarity tw tw 10 ns minimum t w t w 300 350 ns Chapter 4 Signal Connections PCI MIO E Series User Manual 4 40 National Instruments Corporation D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generati
83. be read or written For example an analog input FIFO stores the results of A D conversions until the data can be read into system memory Programming the DMA controller and servicing interrupts can take several milliseconds in some cases During this time data accumulates in the FIFO for future retrieval With a larger FIFO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored in the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device FREQ_OUT frequency output signal ft feet G GATE gate signal GPCTR general purpose counter GPCTR0_GATE general purpose counter 0 gate signal GPCTR1_GATE general purpose counter 1 gate signal GPCTR0_OUT general purpose counter 0 output signal GPCTR1_OUT general purpose counter 1 output signal GPCTR0_SOURCE general purpose counter 0 clock source signal GPCTR1_SOURCE general purpose counter 1 clock source signal GPCTR0_UP_DOWN general purpose counter 0 up down GPCTR1_UP_DOWN general purpose counter 1 up down Glossary PCI MIO E Series User Manual G 6 National Instruments Corporation H h hour hex hexadecimal Hz hertz I I O input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfac
84. c 0 4 5 at 0 4 1 5 50 k pu PFI7 STARTSCAN DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI8 GPCTR0_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu PFI9 GPCTR0_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 k pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output AI DIO Analog Digital Input Output Note The tolerance on the 50 k pullup and pulldown resistors is very large Actual value may range between 17 k and 100 k Table 4 2 I O Signal Summary PCI MIO 16XE 10 Signal Name Signal Type and Direction Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias ACH lt 0 15 gt AI 100 G in parallel with 100 pF 25 15 1 nA AISENSE AI 100 G in parallel with 100 pF 25 15 1 nA Table 4 1 I O Signal Summary PCI MIO 16E 1 and PCI MIO 16E 4 Continued Signal Name Signal Type and Direction Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias Chapter 4 Signal Connections PCI MIO E Series User Manual 4 8 National Instruments Corporation AIGND AO
85. ces 4 16 nonreferenced signal sources 4 17 to 4 18 recommended configuration figure 4 14 single ended connections 4 18 to 4 21 floating signal sources RSE configuration 4 20 grounded signal sources NRSE configuration 4 20 to 4 21 I O connector 4 1 to 4 10 exceeding maximum ratings warning 4 1 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 to 4 7 PCI MIO 16XE 10 4 7 to 4 9 PCI MIO 16XE 50 4 9 to 4 10 pin assignments figure 4 2 signal descriptions table 4 3 to 4 5 optional cable connector 50 pin MIO connector pin assignments figure B 3 68 pin MIO connector pin assignments figure B 2 power connections 4 25 timing connections 4 25 to 4 47 DAQ timing connections 4 27 to 4 37 AIGATE signal 4 36 CONVERT signal 4 34 to 4 35 EXTSTROBE signal 4 29 SCANCLK signal 4 28 SISOURCE signal 4 36 to 4 37 STARTSCAN signal 4 32 to 4 34 TRIG1 signal 4 29 to 4 30 TRIG2 signal 4 31 to 4 32 typical posttriggered acquisition figure 4 27 typical pretriggered acquisition figure 4 28 general purpose timing signal connections 4 40 to 4 47 FREQ_OUT signal 4 47 GPCTR0_GATE signal 4 42 GPCTR0_OUT signal 4 42 to 4 43 GPCTR0_SOURCE signal 4 41 GPCTR0_UP_DOWN signal 4 43 GPCTR1_GATE signal 4 44 to 4 45 GPCTR1_OUT signal 4 45 GPCTR1_SOURCE signal 4 43 to 4 44 Index PCI MIO E Series User Manual I 10 National Instruments Corporation GPCTR1_UP_DOWN signal 4 46 to 4 4
86. d _______________________________________________________ Type of video board installed ____________________________________________________ Operating system DOS Windows or MacOS ______________________________________ Operating system version _______________________________________________________ Operating system mode _________________________________________________________ Programming language _________________________________________________________ Programming language version __________________________________________________ Other boards in system _________________________________________________________ Base memory address of other boards _____________________________________________ Interrupt level of other boards ___________________________________________________ Click here to comment on this document via the National Instruments website at http www natinst com documentation daq Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title PCI MIO E Series User Manual Edition Date January 1997 Part Number 320945B 01 Please comment on the completeness clarity and organization of the manual _______________________________________________________________________________ _______________________________________________________________________________ _________
87. d or floating signal sources 4 17 to 4 18 recommended configuration figure 4 14 single ended connections 4 18 to 4 19 floating signal sources RSE 4 20 grounded signal sources NRSE 4 20 to 4 21 when to use 4 15 digital I O hardware overview 3 16 questions about PCI MIO E Series boards C 4 to C 6 signal connections 4 23 to 4 24 exceeding maximum input voltage ratings warning 4 23 specifications PCI MIO 16E 1 and PCI MIO 16E 4 A 8 to A 9 PCI MIO 16XE 10 A 17 PCI MIO 16XE 50 A 24 digital trigger specifications PCI MIO 16E 1 and PCI MIO 16E 4 A 10 PCI MIO 16XE 10 A 18 PCI MIO 16XE 50 A 25 DIO lt 0 7 gt signal description table 4 3 digital I O connections 4 23 to 4 24 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 9 dither enabling 3 8 to 3 9 signal acquisition effects figure 3 9 documentation conventions used in manual xii to xiii National Instruments documentation set xiii to xiv Index PCI MIO E Series User Manual I 4 National Instruments Corporation organization of manual ixi to xii related documentation xiv dynamic characteristics analog input PCI MIO 16E 1 and PCI MIO 16E 4 A 4 to A 5 PCI MIO 16XE 10 A 14 PCI MIO 16XE 50 A 22 analog output PCI MIO 16E 1 and PCI MIO 16E 4 A 8 PCI MIO 16XE 10 A 16 PCI MIO 16XE 50 A 23 E EEPROM storage of calibration constants 5 1 e mail support D 2 environment specificat
88. e common mode noise in the signal and the ground potential difference between the signal source and the PCI MIO E Series board ground shown as Vcm in Figure 4 4 Ground Referenced Signal Source Common Mode Noise and Ground Potential Input Multiplexers AISENSE Instrumentation Amplifier Vm Measured Voltage AIGND Vs Vcm I O Connector ACH lt 0 7 gt ACH lt 8 15 gt Selected Channel in DIFF Configuration PGIA Chapter 4 Signal Connections National Instruments Corporation 4 17 PCI MIO E Series User Manual Differential Connections for Nonreferenced or Floating Signal Sources Figure 4 5 shows how to connect a floating signal source to a channel on the PCI MIO E Series board configured in DIFF input mode Figure 4 5 Differential Input Connections for Nonreferenced Signals Figure 4 5 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA will saturate causing erroneous readings You must reference the source to AIGND The easiest way is simply to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as to the negative input of the PGIA without any resistors at all This c
89. e data acquisition sequence for both posttriggered and pretriggered acquisitions The PCI MIO 16E 1 PCI MIO 16E 4 and PCI MIO 16XE 10 support analog triggering on the PFI0 TRIG1 pin See Chapter 3 Hardware Overview for more information on analog triggering t w t w VOH VOL t w 600 ns or 5 s Chapter 4 Signal Connections PCI MIO E Series User Manual 4 30 National Instruments Corporation As an output the TRIG1 signal reflects the action that initiates a DAQ sequence This is true even if the acquisition is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 15 and 4 16 show the input and output timing requirements for the TRIG1 signal Figure 4 15 TRIG1 Input Signal Timing Figure 4 16 TRIG1 Output Signal Timing The board also uses the TRIG1 signal to initiate pretriggered DAQ operations In most pretriggered applications the TRIG1 signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation Rising edge polarity Falling edge polarity tw tw 10 ns minimum tw tw 50 100 ns Chapter 4 Signal Connections National Instruments Corporation 4 31 PCI MIO E Series User Manual TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an outp
90. e industry standard PCI Local Bus Specification Revision 2 0 This allows the PCI system to automatically perform all bus related configurations and requires no user interaction Bus related configuration includes setting the board base memory address and interrupt channel Data acquisition related configuration includes such settings as analog input polarity and range analog input mode and others You can modify these settings through application level software such as NI DAQ ComponentWorks LabVIEW LabWindows CVI and VirtualBench National Instruments Corporation 3 1 PCI MIO E Series User Manual Chapter3 Hardware Overview This chapter presents an overview of the hardware functions on your PCI MIO E Series board Figure 3 1 shows a block diagram for the PCI MIO 16E 1 and PCI MIO 16E 4 Figure 3 1 PCI MIO 16E 1 and PCI MIO 16E 4 Block Diagram Timing PFI Trigger I O Connector 3 RTSI Bus PCI Bus Digital I O 8 12 Bit Sampling A D Converter EEPROM Configuration Memory NI PGIA Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs Dither Circuitry Trigger Analog Trigger Circuitry 2 Trigger Level DACs 6 Calibration DACs DAC0 DAC1 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Re
91. e synchronization of functions S s seconds S samples SCANCLK scan clock signal Glossary National Instruments Corporation G 9 PCI MIO E Series User Manual SCXI Signal Conditioning eXtensions for Instrumentation the National Instruments product line for conditioning low level signals within an external chassis near sensors so only high level signals are sent to DAQ boards in the noisy computer environment SE single ended a term used to describe an analog input that is measured with respect to a common ground settling time the amount of time required for a voltage to reach its final value within specified limits signal conditioning the manipulation of signals to prepare them for digitizing SISOURCE SI counter clock signal SOURCE source signal S s samples per second used to express the rate at which a DAQ board samples an analog signal STARTSCAN start scan signal system noise a measure of the amount of noise seen by an analog circuit or an ADC when the analog inputs are grounded T TC terminal count the ending value of a counter tgh gate hold time tgsu gate setup time tgw gate pulse width tout output delay time THD total harmonic distortion the ratio of the total rms signal due to harmonic distortion to the overall rms signal in dB or percent thermocouple a temperature sensor created by joining two dissimilar metals The junction produces a small voltage as a function o
92. e your PCI MIO 16XE 10 and PCI MIO 16XE 50 analog input circuitry for either a unipolar or bipolar polarity If you mix unipolar and bipolar channels in your scan list and you are using NI DAQ then NI DAQ will load the calibration constants appropriate to the polarity for which analog input channel 0 is configured The software programmable gain on these boards increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate The PCI MIO 16XE 50 has gains of 1 2 10 and 100 and the PCI MIO 16XE 10 has gains of 1 2 5 10 20 50 and 100 These gains are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Chapter 3 Hardware Overview National Instruments Corporation 3 7 PCI MIO E Series User Manual Table 3 3 shows the overall input range and precision according to the input range configuration and gain used Considerations for Selecting Input Ranges Which input polarity and range you select depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For best results match the input range as closely as possible to the expected range of the input signal For example if you are certain the inpu
93. edance if you plan to enable this input via software Figure 3 5 Analog Trigger Block Diagram Analog Input Channels PFI0 TRIG1 PGIA ADC DAQ STC Analog Trigger Circuit Mux Chapter 3 Hardware Overview PCI MIO E Series User Manual 3 14 National Instruments Corporation There are five analog triggering modes available as shown in Figures 3 6 through 3 10 You can set lowValue and highValue independently in software In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue HighValue is unused Figure 3 6 Below Low Level Analog Triggering Mode In above high level analog triggering mode the trigger is generated when the signal value is greater than highValue LowValue is unused Figure 3 7 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue lowValue Trigger highValue Trigger Chapter 3 Hardware Overview National Instruments Corporation 3 15 PCI MIO E Series User Manual Figure 3 8 Inside Region Analog Triggering Mode In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue Figure 3 9 High Hysteresis Analog Triggering Mode In low hysteresis analog triggering mode the trigger is generated when the signa
94. el programming 1 5 unpacking 1 7 PFI0 TRIG1 signal description table 4 4 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 PFI1 TRIG2 signal description table 4 4 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 PFI2 CONVERT signal description table 4 4 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 PFI3 GPCTR1_SOURCE signal description table 4 4 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 PFI4 GPCTR1_GATE signal description table 4 4 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 PFI5 UPDATE signal description table 4 5 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 PFI6 WFTRIG signal description table 4 5 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 PFI7 STARTSCAN signal description table 4 5 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 PFI8 GPCTR0_SOURCE signal description table 4 5 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 PFI9 GPCTR0_GATE
95. en lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other Do not run signal lines through conduits that also contain power lines Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the application note Field Wiring and Noise Consideration for Analog Signals available from National Instruments National Instruments Corporation 5 1 PCI MIO E Series User Manual Chapter5 Calibration This chapter discusses the calibration procedures for your PCI MIO E Series board If you are using the NI DAQ device driver that software includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the PCI MIO E Series boards these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of board calibration is required for all but the most forgiving applications If you do not calibrate your board your signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and described in this chapter The first level is the fastest easiest and least accurate whereas the last level
96. errupts programmed I O DMA modes Scatter gather 1 000 h Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 National Instruments Corporation A 7 PCI MIO E Series User Manual Transfer Characteristics Relative accuracy INL After calibration 0 3 LSB typ 0 5 LSB max Before calibration 4 LSB max DNL After calibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monotonicity 12 bits guaranteed after calibration Offset error After calibration 1 0 mV max Before calibration 200 mV max Gain error relative to internal reference After calibration 0 01 of output max Before calibration 0 5 of output max Gain error relative to external reference 0 to 0 5 of output max not adjustable Voltage Output Ranges 10 V 0 to 10 V EXTREF 0 to EXTREF software selectable Output coupling DC Output impedance 0 1 max Current drive 5 mA max Protection
97. es IOH current output high IOL current output low INL relative accuracy L LSB least significant bit M m meter MB megabytes of memory MIO multifunction I O MITE MXI Interfaces to Everything MSB most significant bit mux multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel Glossary National Instruments Corporation G 7 PCI MIO E Series User Manual N NC normally closed or not connected NI DAQ NI driver software for DAQ hardware noise an undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights CRT displays computers electrical storms welders radio transmitters and internal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send or receive NRSE nonreferenced single ended mode all measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can vary with respect to the measurement system ground O OUT output pin a counter output pin where the counter can generate various TTL pulse waveforms P PCI Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA
98. f the temperature TRIG trigger signal Glossary PCI MIO E Series User Manual G 10 National Instruments Corporation tsc source clock period tsp source pulse width TTL transistor transistor logic U UI update interval UISOURCE update interval counter clock signal unipolar a signal range that is always positive for example 0 to 10 V UPDATE update signal V V volts VDC volts direct current VI virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program VIH volts input high VIL volts input low Vin volts in Vm measured voltage VOH volts output high VOL volts output low Vref reference voltage Vrms volts root mean square Glossary National Instruments Corporation G 11 PCI MIO E Series User Manual W waveform multiple voltage readings taken at a specific sampling rate WFTRIG waveform generation trigger signal National Instruments Corporation I 1 PCI MIO E Series User Manual Index Numbers 5 V signal description 4 3 power connections 4 25 protection provided with PCI MIO E Series C 2 A ACH lt 0 15 gt signal description table 4 3 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4
99. from National Instruments by request You should not need the register level programmer manual if you are using National Instruments driver or application software Using NI DAQ ComponentWorks LabVIEW LabWindows CVI Measure or VirtualBench software is easier than the low level programming described in the register level programmer manual Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix D Customer Communication at the end of this manual National Instruments Corporation 1 1 PCI MIO E Series User Manual Chapter1 Introduction This chapter describes the PCI MIO E Series boards lists what you need to get started describes the optional software and optional equipment and explains how to unpack your PCI MIO E Series board About the PCI MIO E Series Thank you for buying a National Instruments PCI MIO E Series board The PCI MIO E Series boards are completely Plug and Play multifunction analog digital and timing I O boards for PCI bus computers This family of boards features 12 bit and 16 bit ADCs with 16 analog inputs 12 bit and 16 bit DACs with voltage outputs eight lines of TTL compatible digital I O and two
100. gain error before calibration 102 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2 150 ppm of reading max With gain error adjusted to 0 at gain 1 Gain 1 200 ppm of reading max Amplifier Characteristics Input impedance Normal powered on 100 G in parallel with 100 pF Powered off 820 min Overload 820 min Input bias current 1 nA Input offset current 2 nA Appendix A Speci cations for PCI MIO 16XE 10 PCI MIO E Series User Manual A 14 National Instruments Corporation CMRR DC to 60 Hz Dynamic Characteristics Bandwidth 3 dB All gains 255 kHz Settling time for full scale step DC to all gains and ranges System noise including quantization noise Dynamic range 91 7 dB 10 V input with gain 1 to 10 Crosstalk 70 dB max DC to 100 kHz Gain CMRR 1 92 dB 2 97 dB 5 101 dB 10 104 dB 20 105 dB Accuracy 0 00076 0 5 LSB 0 0015 1 LSB 0 0061 4 LSB 40 s max 20 s max 10 s
101. gnal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 to 4 7 PCI MIO 16XE 10 4 7 to 4 9 PCI MIO 16XE 50 4 9 to 4 10 optional cable connector 50 pin MIO connector pin assignments figure B 3 68 pin MIO connector pin assignments figure B 2 pin assignments figure 4 2 RTSI bus signal connections figure 3 19 signal descriptions table 4 3 to 4 5 L LabVIEW application software 1 3 LabWindows CVI application software 1 3 M manual See documentation multiple channel scanning 3 9 to 3 10 N NI DAQ driver software 1 4 to 1 5 C 2 noise avoiding 4 48 NRSE nonreferenced single ended input description table 3 4 differential connections 4 17 to 4 18 recommended configuration figure 4 14 single ended connections NRSE configuration 4 20 to 4 21 P PCI MIO E Series See also hardware overview block diagrams PCI MIO 16E 1 and PCI MIO 16E 4 3 1 PCI MIO 16XE 10 3 2 PCI MIO 16XE 50 3 3 common questions C 1 to C 6 analog input and output C 2 to C 4 general information C 1 to C 2 installation and configuration C 2 timing and digital I O C 4 to C 6 custom cabling 1 6 to 1 7 features 1 1 to 1 2 installation 2 1 to 2 2 Index National Instruments Corporation I 7 PCI MIO E Series User Manual optional equipment 1 6 requirements for getting started 1 2 software programming choices National Instruments application software 1 3 NI DAQ driver software 1 4 to 1 5 register lev
102. grammable Function Input Connections 4 26 DAQ Timing Connections 4 27 SCANCLK Signal 4 28 EXTSTROBE Signal 4 29 TRIG1 Signal 4 29 TRIG2 Signal 4 31 STARTSCAN Signal 4 32 CONVERT Signal 4 34 AIGATE Signal 4 36 SISOURCE Signal 4 36 Waveform Generation Timing Connections 4 37 WFTRIG Signal 4 37 UPDATE Signal 4 38 UISOURCE Signal 4 40 General Purpose Timing Signal Connections 4 40 GPCTR0_SOURCE Signal
103. her PFI This output is set to tri state at startup Figure 4 33 shows the timing requirements for the GPCTR1_GATE signal tp tw tw tp tw 50 ns minimum 23 ns minimum Chapter 4 Signal Connections National Instruments Corporation 4 45 PCI MIO E Series User Manual Figure 4 33 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC board general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 34 shows the timing requirements for the GPCTR1_OUT signal Figure 4 34 GPCTR1_OUT Signal Timing Rising edge polarity Falling edge polarity tw tw 10 ns minimum GPCTR1_SOURCE GPCTR1_OUT Pulse on TC GPCTR1_OUT Toggle output on TC TC Chapter 4 Signal Connections PCI MIO E Series User Manual 4 46 National Instruments Corporation GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 35 s
104. hows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your PCI MIO E Series board Figure 4 35 GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4 35 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges SOURCE V IH VIL V IH V IL t sc t sp t sp t gsu t gh t gw GATE t out OUT V OH V OL sc t t t t t t 50 ns minimum sp 23 ns minimum gsu 10 ns minimum gh 0 ns minimum gw 10 ns minimum out 80 ns maximum Source Clock Period Source Pulse Width Gate Setup Time Gate Hold Time Gate Pulse Width Output Delay Time Chapter 4 Signal Connections National Instruments Corporation 4 47 PCI MIO E Series User Manual The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your PCI MIO E Series board Figure 4 35 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown b
105. igital I O Number of channels 8 input output Compatibility TTL CMOS 1 000 h Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 National Instruments Corporation A 9 PCI MIO E Series User Manual Digital logic levels Power on state Input High Z Data transfers Programmed I O Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scaler 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Level Min Max Input low voltage Input high voltage Input low current Vin 0 V Input high current Vin 5 V 0 0 V 2 0 V 0 8 V 5 0 V 320 A 10 A Output low voltage IOL 24 mA Output high voltage IOH 13 mA 4 35 V
106. iming Signal Routing The DAQ STC provides a very flexible interface for connecting timing signals to other boards or external circuitry Your PCI MIO E Series board uses the RTSI bus to interconnect timing signals between boards and the Programmable Function Input PFI pins on the I O connector to connect the board to external circuitry These connections are designed to enable the PCI MIO E Series board to both control and be controlled by other boards and circuits There are a total of 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing multiplexer for controlling the CONVERT signal is shown in Figure 3 11 Chapter 3 Hardware Overview National Instruments Corporation 3 17 PCI MIO E Series User Manual Figure 3 11 CONVERT Signal Routing This figure shows that CONVERT can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTR0_OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTSI Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs The 10 PFIs are connected to the signa
107. ional Instruments Corporation I 5 PCI MIO E Series User Manual I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 9 PCI MIO 16XE 50 4 10 waveform generation timing connections 4 42 to 4 43 GPCTR0_SOURCE signal 4 41 GPCTR0_UP_DOWN signal 4 43 GPCTR1_GATE signal 4 44 to 4 45 GPCTR1_OUT signal description table 4 4 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 waveform generation timing connections 4 45 GPCTR1_SOURCE signal 4 43 to 4 44 GPCTR1_UP_DOWN signal 4 46 to 4 47 ground referenced signal sources description 4 13 differential connections 4 16 recommended configuration figure 4 14 single ended connections NRSE configuration 4 20 to 4 21 H hardware overview analog input 3 3 to 3 10 dither 3 8 to 3 9 input modes 3 3 to 3 4 input polarity and range 3 4 to 3 7 multiple channel scanning considerations 3 9 to 3 10 range selection considerations 3 7 analog output 3 11 to 3 12 polarity selection 3 11 to 3 12 reference selection 3 11 reglitch selection 3 12 analog trigger 3 13 to 3 16 above high level analog triggering mode figure 3 14 below low level analog triggering mode figure 3 14 block diagram 3 13 high hysteresis analog triggering mode figure 3 15 inside region analog triggering mode figure 3 15 low hysteresis analog triggering mode figure 3 15 PFIO TRIG1 pin note 3 13 b
108. ions PCI MIO 16E 1 and PCI MIO 16E 4 A 11 PCI MIO 16XE 10 A 19 PCI MIO 16XE 50 A 26 environmental noise avoiding 4 48 equipment optional 1 6 EXTREF signal analog output reference selection 3 11 description table 4 3 I O signal summary table 4 6 EXTSTROBE signal description table 4 4 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 8 PCI MIO 16XE 50 4 10 timing connections 4 29 F fax and telephone support D 2 Fax on Demand support D 2 field wiring considerations 4 48 floating signal sources description 4 13 differential connections 4 17 to 4 18 recommended configuration figure 4 14 single ended connections RSE configuration 4 20 FREQ_OUT signal description table 4 5 I O signal summary table PCI MIO 16E 1 and PCI MIO 16E 4 4 7 PCI MIO 16XE 10 4 9 PCI MIO 16XE 50 4 10 waveform generation timing connections 4 47 frequently asked questions See questions about PCI MIO E Series boards FTP support D 1 fuse for 5 V signal C 2 G general purpose timing signal connections 4 40 to 4 47 FREQ_OUT signal 4 47 GPCTR0_GATE signal 4 42 GPCTR0_OUT signal 4 42 to 4 43 GPCTR0_SOURCE signal 4 41 GPCTR0_UP_DOWN signal 4 43 GPCTR1_GATE signal 4 44 to 4 45 GPCTR1_OUT signal 4 45 GPCTR1_SOURCE signal 4 43 to 4 44 GPCTR1_UP_DOWN signal 4 46 to 4 47 glitches 3 12 GPCTR0_GATE signal 4 42 GPCTR0_OUT signal description table 4 5 Index Nat
109. ision PCI MIO 16E 1 and PCI MIO 16E 4 Range Configuration Gain Actual Input Range Precision1 0 to 10 V 1 0 2 0 5 0 10 0 20 0 50 0 100 0 0 to 10 V 0 to 5 V 0 to 2 V 0 to 1 V 0 to 500 mV 0 to 200 mV 0 to 100 mV 2 44 mV 1 22 mV 488 28 V 244 14 V 122 07 V 48 83 V 24 41 V 5 to 5 V 0 5 1 0 2 0 5 0 10 0 20 0 50 0 100 0 10 to 10 V 5 to 5 V 2 5 to 2 5 V 1 to 1 V 500 to 500 mV 250 to 250 mV 100 to 100 mV 50 to 50 mV 4 88 mV 2 44 mV 1 22 mV 488 28 V 244 14 V 122 07 V 48 83 V 24 41 V 1The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings Chapter 3 Hardware Overview PCI MIO E Series User Manual 3 6 National Instruments Corporation PCI MIO 16XE 10 and PCI MIO 16XE 50 These boards have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and Vref where Vref is a positive reference voltage Bipolar input means that the input voltage range is between Vref and Vref The PCI MIO 16XE 10 and PCI MIO 16XE 50 have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 20 V 10 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely Note You can calibrat
110. ke analog output connections and the external reference input connection to your PCI MIO E Series board Chapter 4 Signal Connections National Instruments Corporation 4 23 PCI MIO E Series User Manual Figure 4 8 Analog Output Connections The external reference signal can be either a DC or an AC signal The board multiplies this reference signal by the DAC code divided by the full scale DAC code to generate the output voltage Digital I O Signal Connections The digital I O signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs Warning Exceeding the maximum input voltage ratings which are listed in Tables 4 1 4 2 and 4 3 can damage the PCI MIO E Series board and the computer National Instruments is NOT liable for any damages resulting from such signal connections Channel 0 Channel 1 External Reference Signal Optional Load Load VOUT 0 VOUT 1 DAC1OUT AOGND DAC0OUT EXTREF Analog Output Channels E Series Board Vref Chapter 4 Signal Connections PCI MIO E Series User Manual 4 24 National Instruments Corporation Figure 4 9 shows signal connections for three typical digital I O applications Figure 4 9 Digital I O Connections Figure 4 9 shows DIO lt 0 3 gt configured for digita
111. l input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure Digital output applications include sending TTL signals and driving external devices such as the LED shown in the figure LED 5 V TTL Signal 5 V DIO lt 4 7 gt DIO lt 0 3 gt DGND Switch I O Connector E Series Board Chapter 4 Signal Connections National Instruments Corporation 4 25 PCI MIO E Series User Manual Power Connections Two pins on the I 0 connector supply 5 V from the computer power supply via a self resetting fuse The fuse will reset automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry Power rating 4 65 to 5 25 VDC at 1 A Warning Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the PCI MIO E Series board or any other device Doing so can damage the PCI MIO E Series board and the computer National Instruments is NOT liable for damages resulting from such a connection Timing Connections Warning Exceeding the maximum input voltage ratings which are listed in Tables 4 1 4 2 and 4 3 can damage the PCI MIO E Series board and the computer National Instruments is NOT liable for any da
112. l routing multiplexer for each timing signal and software can select one of the PFIs as the external source for a given timing signal It is important to note that any of the PFIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFI5 UPDATE pin RTSI Trigger lt 0 6 gt PFI lt 0 9 gt CONVERT Sample Interval Counter TC GPCTR0_OUT Chapter 3 Hardware Overview PCI MIO E Series User Manual 3 18 National Instruments Corporation Board and RTSI Clocks Many functions performed by the PCI MIO E Series boards require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector A PCI MIO E Series board can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the board to use the internal timebase you can also program the board to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal This clock source
113. l value is less than lowValue with the hysteresis specified by highValue Figure 3 10 Low Hysteresis Analog Triggering Mode highValue Trigger lowValue highValue Trigger lowValue highValue Trigger lowValue Chapter 3 Hardware Overview PCI MIO E Series User Manual 3 16 National Instruments Corporation The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the analog input analog output and general purpose counter timer sections For example the analog input section can be configured to acquire n scans after the analog input signal crosses a specific threshold As another example the analog output section can be configured to update its outputs whenever the analog input signal crosses a specific threshold Digital I O The PCI MIO E Series boards contain eight lines of digital I O for general purpose use You can individually software configure each line for either input or output At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines T
114. lection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 24 and 4 25 show the input and output timing requirements for the WFTRIG signal tp tw tw tp tw 50 ns minimum 23 ns minimum Chapter 4 Signal Connections PCI MIO E Series User Manual 4 38 National Instruments Corporation Figure 4 24 WFTRIG Input Signal Timing Figure 4 25 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFI5 UPDATE pin As an input the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode Rising edge polarity Falling edge polarity tw tw 10 ns minimum tw tw 50 100 ns Chapter 4 Signal Connections N
115. lling edge Pulse width 10 ns min Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 National Instruments Corporation A 11 PCI MIO E Series User Manual RTSI Trigger Lines Seven Bus Interface Type Master slave Power Requirement 5 VDC 5 PCI MIO 16E 1 1 1 A PCI MIO 16E 4 0 9 A Power available at I O connector 4 65 to 5 25 VDC at 1 A Physical Dimensions not including connectors 17 5 by 10 6 cm 6 9 by 4 2 in I O connector 68 pin male SCSI II type Environment Operating temperature 0 to 55 C Storage temperature 55 to 150 C Relative humidity 5 to 90 noncondensing National Instruments Corporation A 12 PCI MIO E Series User Manual PCI MIO 16XE 10 Analog Input Input Characteristics Number of channels 16 single ended or 8 differential software selectable Type of ADC Successive approximation Resolution 16 bits 1 in 65 536 Max sampling rate 100 kS s g
116. lock diagrams PCI MIO 16E 1 and PCI MIO 16E 4 3 1 PCI MIO 16XE 10 3 2 PCI MIO 16XE 50 3 3 digital I O 3 16 timing signal routing 3 16 to 3 19 board and RTSI clocks 3 18 programmable function inputs 3 17 RTSI triggers 3 18 to 3 19 I input configurations 4 13 to 4 21 available input modes 3 3 to 3 4 DIFF table 3 4 NRSE table 3 4 RSE table 3 4 common mode signal rejection 4 21 differential connections DIFF input configuration 4 15 floating signal sources 4 17 to 4 18 ground referenced signal sources 4 16 nonreferenced signal sources 4 17 to 4 18 Index PCI MIO E Series User Manual I 6 National Instruments Corporation recommended configuration figure 4 14 single ended connections 4 18 to 4 21 floating signal sources RSE configuration 4 20 grounded signal sources NRSE configuration 4 20 to 4 21 input polarity and range 3 4 to 3 7 actual range and measurement precision table PCI MIO 16E 1 and PCI MIO 16E 4 3 5 PCI MIO 16XE 10 and PCI MIO 16XE 50 3 7 mixing bipolar and unipolar channels note 3 6 PCI MIO 16E 1 and PCI MIO 16E 4 3 4 to 3 5 PCI MIO 16XE 10 and PCI MIO 16XE 50 3 5 to 3 6 range selection considerations 3 7 installation See also configuration hardware installation 2 1 to 2 2 questions about PCI MIO E Series boards C 2 software installation 2 1 unpacking the PCI MIO E Series 1 7 I O connectors 4 1 to 4 10 exceeding maximum ratings warning 4 1 I O si
117. mages resulting from such signal connections All external control over the timing of your PCI MIO E Series board is routed through the 10 programmable function inputs labeled PFI0 through PFI9 These signals are explained in detail in the next section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many DAQ waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any DAQ waveform generation and general purpose timing signals The DAQ signals are explained in the DAQ Timing Connections section later in this chapter The waveform generation signals are explained in the Waveform Generation Timing Connections section later in this chapter The general purpose timing signals are explained in the General Purpose Timing Signal Connections section later in this chapter Chapter 4 Signal Connections PCI MIO E Series User Manual 4 26 National Instruments Corporation All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 10 which shows how to connect an external TRIG1 source and an external CONVERT source to two PCI MIO E Series board PFI pins Figure 4 10 Timing I O Connections Programmable Function Input Connections There are a total of 13 internal timing sig
118. modulation is decreased and differential linearity is improved by the addition of the dither When taking DC measurements such as when checking the board calibration you should enable dither and average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable the dither to reduce noise Your software enables and disables the dither circuitry Figure 3 4 illustrates the effect of dither on signal acquisition Figure 3 4a shows a small 4 LSB sine wave acquired with dither off The ADC quantization is clearly visible Figure 3 4b shows what happens when 50 such acquisitions are averaged together quantization is still plainly visible In Figure 3 4c the sine wave is acquired with dither on There is a considerable amount of visible noise But averaging about 50 such acquisitions as shown in Figure 3 4d eliminates both the added noise and the effects of quantization Dither has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of the input signal Chapter 3 Hardware Overview National Instruments Corporation 3 9 PCI MIO E Series User Manual Figure 3 4 Dither You cannot disable dither on the PCI MIO 16XE 10 or PCI MIO 16XE 50 This is because the ADC resolution is so fine
119. mpers should I be aware of when configuring my PCI MIO E Series board The PCI MIO E Series boards are jumperless and switchless 7 Which National Instruments document should I read first to get started using DAQ software Your NI DAQ or application software release notes documentation is always the best starting place 8 What version of NI DAQ must I have to program my PCI MIO E Series board If you are using a PC you must have the NI DAQ for PC version 5 0 or higher Only the PCI MIO 16XE 50 is currently supported on the Macintosh and you must have NI DAQ for Macintosh version 4 8 0 or higher Contact National Instruments for information on Macintosh support for the PCI MIO 16E 1 PCI MIO 16E 4 and PCI MIO 16XE 10 Analog Input and Output 9 I m using my board in differential analog input mode and I have connected a differential input signal but my readings are random and drift rapidly What s wrong Check your ground reference connections Your signal may be referenced to a level that is considered floating with reference to the board ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the board reference There are various methods of achieving this while Appendix C Common Questions National Instruments Corporation C 3 PCI MIO E Series User Manual maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter
120. n materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior n
121. n the Am9513 counter timer and the DAQ STC The DAQ STC based MIO boards have a 20 MHz timebase The Am9513 based MIO boards have a 1 MHz or 5 MHz timebase 15 Will the counter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some of your applications drawn using the CTR VIs will still run However there are many differences in the counters between the PCI MIO E Series and other boards the counter numbers are different timebase selections are different and the DAQ STC counters are 24 bit counters unlike the 16 bit counters on boards without the DAQ STC If you are using the NI DAQ language interface or LabWindows CVI the answer is no the counter timer applications that you wrote previously will not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions will not Appendix C Common Questions National Instruments Corporation C 5 PCI MIO E Series User Manual work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls 16 I m using one of the general purpose counter timers on my PCI MIO E Series board but I do not see the counter timer output on the I O connector What am I doing wrong If you are using the NI DAQ language interface or LabWindows CVI you must configure the output line to output the signal to the I O connec
122. nal for A D conversion comes from PFI5 as follows If you are using NI DAQ call Select_Signal deviceNumber ND_IN_CONVERT ND_PFI_5 ND_HIGH_TO_LOW If you are using LabVIEW invoke AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 Appendix C Common Questions PCI MIO E Series User Manual C 4 National Instruments Corporation c Initiate analog input data acquisition which will start only when the analog output waveform generation starts d Initiate analog output waveform generation Timing and Digital I O 12 What types of triggering can be hardware implemented on my PCI MIO E Series board Digital triggering is hardware supported on every PCI MIO E Series board In addition the PCI MIO 16E 1 PCI MIO 16E 4 and PCI MIO 16XE 10 support analog triggering in hardware 13 What added functionality does the DAQ STC make possible in contrast to the Am9513 The DAQ STC incorporates much more than just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines analog triggering selectable logic level and frequency shift keying The DAQ STC also makes buffered operations possible such as direct up down control single or pulse train generation equivalent time sampling buffered period and buffered semiperiod measurement 14 What is the difference in timebases betwee
123. nals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the board I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin Be careful not to drive a PFI signal externally when it is configured as an output TRIG1 Source DGND PFI0 TRIG1 PFI2 CONVERT CONVERT Source I O Connector E Series Board Chapter 4 Signal Connections National Instruments Corporation 4 27 PCI MIO E Series User Manual As an input you can individually configure each PFI for edge or level detection and for polarity selection as well You can use the polarity selection for any of the 13 timing signals but the edge or level detection will depend upon the particular timing signal being controlled The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode
124. nboard calibration reference Level 5 000 V 2 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm 1 000 h Appendix A Speci cations for PCI MIO 16XE 10 National Instruments Corporation A 17 PCI MIO E Series User Manual Digital I O Number of channels 8 input output Compatibility TTL CMOS Digital logic levels Power on state Input High Z Data transfers Programmed I O Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scaler 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Level Min Max Input low voltage Input high voltage Input low current Vin 0 V Input high current Vin 5 V 0 V 2 V 0 8 V 5 V 320 A 10 A Output low voltage IOUT 24 mA 0 4 V Outp
125. nd testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment National Instruments Corporation v PCI MIO E Series User Manual Table of Contents About This Manual Organization of This Manual xi Conventions Used in This Manual xii National Instruments Documentation xiii Related Documentation
126. ndependently with timing resolutions of 50 ns or 10 s With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate are possible 3 How fast are the PCI MIO E Series boards The last numeral in the name of a PCI MIO E Series board specifies the settling time in microseconds for that particular board For example the PCI MIO 16XE 50 has a 50 s settling time which corresponds to a sampling rate of 20 kS s These sampling rates are aggregate one channel at 20 kS s or two channels at 10 kS s per channel illustrates the relationship Notice however that some Appendix C Common Questions PCI MIO E Series User Manual C 2 National Instruments Corporation PCI MIO E Series boards have settling times that vary with gain and accuracy See Appendix A for exact specifications 4 What type of 5 V protection do the PCI MIO E Series boards have The PCI MIO E Series boards have 5 V lines equipped with a self resetting 1 A fuse Installation and Configuration 5 How do you set the base address for a PCI MIO E Series board The base address of a PCI MIO E Series board is assigned automatically through the PCI bus protocol This assignment is completely transparent to you 6 What ju
127. nductors Electrical coupling is a function of how much the electric field differs between the two conductors Chapter 4 Signal Connections PCI MIO E Series User Manual 4 20 National Instruments Corporation Single Ended Connections for Floating Signal Sources RSE Configuration Figure 4 6 shows how to connect a floating signal source to a channel on the PCI MIO E Series board configured for RSE mode Figure 4 6 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources NRSE Configuration To measure a grounded signal source with a single ended configuration you must configure your PCI MIO E Series board in the NRSE input configuration The signal is then connected to the positive input of the PCI MIO E Series PGIA and the signal local ground reference is connected to the negative input of the PGIA The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the PCI MIO E Series ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by the amplifier If the input circuitry of a PCI MIO E Series board were referenced to ground in this situation as in the RSE input configuration this difference in ground potentials would appear as an error in the measured voltage Vs Vm Measured Voltage
128. nput and AIGND as shown in Figure 4 5 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 k and each of the two resistors is 100 k the resistors load down the source with 200 k and produce a 1 gain error Both inputs of the PGIA require a DC path to ground in order for the PGIA to work If the source is AC coupled capacitively coupled the PGIA needs a resistor between the positive input and AIGND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 k to 1 M In this case you can tie the negative input directly to AIGND If the source has high output impedance you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs you should be aware that there is some gain error from loading down the source Single Ended Connection Considerations A single ended connection is one in which the PCI MIO E Series board analog input signal is referenced to a ground that can be shared with other input signals The input signal is tied to the positive input of the PGIA and the ground is tied to the negative input of the PGIA When eve
129. nts application software NI DAQ or register level programming National Instruments Application Software ComponentWorks contains tools for data acquisition and instrument control built on NI DAQ driver software ComponentWorks provides a higher level programming interface for building virtual instruments through standard OLE controls and DLLs With ComponentWorks you can use all of the configuration tools resource management utilities and interactive control utilities included with NI DAQ LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to NI DAQ software LabWindows CVI features interactive graphics state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition Library is functionally equivalent to the NI DAQ software VirtualBench features virtual instruments that combine DAQ products software and your computer to create a stand alone instrument with the added benefit of the processing display and storage capabilities of your comp
130. ol I O Bus Interface MITE Generic Bus Interface PCI Bus Interface Address 5 Chapter 3 Hardware Overview National Instruments Corporation 3 3 PCI MIO E Series User Manual Figure 3 3 shows a block diagram for the PCI MIO 16XE 50 Figure 3 3 PCI MIO 16XE 50 Block Diagram Analog Input The analog input section of each PCI MIO E Series board is software configurable You can select different analog input configurations through application software designed to control the PCI MIO E Series boards The following sections describe in detail each of the analog input categories Input Mode The PCI MIO E Series boards have three different input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations provide up to 16 channels The DIFF input configuration provides up to eight channels Input modes are programmed on a per Timing PFI Trigger I O Connector 2 2 RTSI Bus PCI Bus Digital I O 8 16 Bit Sampling A D Converter Configuration Memory Programmable Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 4 Calibration DACs DAC0 DAC1 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request
131. on of the UPDATE signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 28 shows the timing requirements for the UISOURCE signal Figure 4 28 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections The general purpose timing signals are GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT GPCTR0_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT tp tw tw tp tw 50 ns minimum 23 ns minimum Chapter 4 Signal Connections National Instruments Corporation 4 41 PCI MIO E Series User Manual GPCTR0_SOURCE Signal Any PFI pin can externally input the GPCTR0_SOURCE signal which is available as an output on the PFI8 GPCTR0_SOURCE pin As an input the GPCTR0_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR0_SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PF
132. onnection works well for DC coupled sources with low source impedance less than 100 Floating Signal Source Input Multiplexers Instrumentation Amplifier Vm Measured Voltage VS I O Connector AIGND Bias Current Return Paths bias resistors see text ACH lt 8 15 gt ACH lt 0 7 gt AISENSE Selected Channel in DIFF Configuration PGIA Chapter 4 Signal Connections PCI MIO E Series User Manual 4 18 National Instruments Corporation However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a differential mode signal instead of a common mode signal and the PGIA does not reject it In this case instead of directly connecting the negative line to AIGND connect it to AIGND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive i
133. or Pregain error after calibration 3 V max Pregain error before calibration 1 mV max Postgain error after calibration 76 V max Postgain error before calibration 4 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2250 ppm of reading max With gain error adjusted to 0 at gain 1 Gain 2 10 100 ppm of reading Gain 100 2250 ppm of reading Amplifier Characteristics Input impedance Normal powered on 7 G in parallel with 100 pF Powered off 820 min Overload 820 min Input bias current 10 nA Input offset current 20 nA CMRR DC to 60 Hz Gain 1 80 dB Gain 2 86 dB Gain 10 100 dB Gain 100 120 dB Appendix A Speci cations for PCI MIO 16XE 50 PCI MIO E Series User Manual A 22 National Instruments Corporation Dynamic Characteristics Bandwidth Gain 1 2 63 kHz Gain 10
134. otice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it E XCEPT AS SPECIFIED HEREIN N ATIONAL I NSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE C USTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF N ATIONAL I NSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER N ATIONAL I NSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any
135. own external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate your board by calling the NI DAQ calibration function Chapter 5 Calibration National Instruments Corporation 5 3 PCI MIO E Series User Manual To externally calibrate your board be sure to use a very accurate external reference The reference should be several times more accurate than the board itself For example to calibrate a 16 bit board the external reference should be at least 0 001 10 ppm accurate Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the analog output gain error when using an external reference In this case it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware See Appendix A Specifications for analog output gain error information National Instruments Corporation A 1 PCI MIO E Series User Manual AppendixA Specifications This appendix lists the specifications of each PCI MIO E Series board These s
136. pecifications are typical at 25 C unless otherwise noted PCI MIO 16E 1 and PCI MIO 16E 4 Analog Input Input Characteristics Number of channels 16 single ended or 8 differential software selectable per channel Type of ADC Successive approximation Resolution 12 bits 1 in 4 096 Maximum sampling rate PCI MIO 16E 1 1 25 MS s multichannel PCI MIO 16E 4 500 kS s single channel 250 kS s multichannel Appendix A Speci cations for PCI MIO 16E 1 and PCI MIO 16E 4 PCI MIO E Series User Manual A 2 National Instruments Corporation Input signal ranges Input coupling DC Maximum working voltage signal and common mode Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH lt 0 15 gt AISENSE FIFO buffer size 512 S Data transfers DMA interrupts programmed I O DMA modes Scatter gather Configuration memory size 512 words Channel Gain Software Selectable Board Range Software Selectable Bipolar Unipolar 0 5
137. ptions Table of Contents PCI MIO E Series User Manual viii National Instruments Corporation Appendix C Common Questions Appendix D Customer Communication Glossary Index Figures Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware 1 5 Figure 3 1 PCI MIO 16E 1 and PCI MIO 16E 4 Block Diagram 3 1 Figure 3 2 PCI MIO 16XE 10 Block Diagram 3 2 Figure 3 3 PCI MIO 16XE 50 Block Diagram 3 3 Figure 3 4 Dither 3 9 Figure 3 5 Analog Trigger Block Diagram 3 13 Figure 3 6 Below Low Level Analog Triggering Mode 3 14 Figure 3 7 Above High Level Analog Triggering Mode 3 14 Figure 3 8 Inside Region Analog Triggering Mode 3 15 Figure 3 9 High Hysteresis Analog Triggering Mode 3 15 Figure 3 10 Low Hysteresis Analog Triggering Mode 3 15 Figure 3 11 CONVERT Signal Routing
138. quest Bus Interface 8 8 DAC FIFO Data 16 AI Control Address Data Control Data 16 Analog Input Control EEPROM Control DMA Interface MIO Interface DAQ STC Bus Interface Analog Output Control I O Bus Interface MITE Generic Bus Interface PCI Bus Interface IRQ DMA AO Control ADC FIFO Address 5 Chapter 3 Hardware Overview PCI MIO E Series User Manual 3 2 National Instruments Corporation Figure 3 2 shows a block diagram for the PCI MIO 16XE 10 Figure 3 2 PCI MIO 16XE 10 Block Diagram Timing PFI Trigger I O Connector 3 2 2 RTSI Bus Digital I O 8 16 Bit Sampling A D Converter Configuration Memory REF Buffer Programmable Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 4 Calibration DACs DAC0 DAC1 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 AI Control IRQ DMA AO Control DAC FIFO Data 16 Trigger Level DACs Analog Trigger Circuitry Data 16 ADC FIFO Trigger PCI Bus EEPROM Address Data Control Data 16 Analog Input Control EEPROM Control DMA Interface MIO Interface DAQ STC Bus Interface Analog Output Contr
139. rge injection where the analog input multiplexer injects a small amount of charge into each signal source when that source is selected If the impedance of the source is not low enough the effect of the charge a voltage error will not have decayed by the time the ADC samples the signal For this reason keep source impedances under 1 k to perform high speed scanning Due to problems with settling times multichannel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as nearly simultaneously as possible The data is much more accurate and channel to channel independent if you acquire data from each channel independently for example 100 points from channel 0 then 100 points from channel 1 then 100 points from channel 2 and so on Chapter 3 Hardware Overview National Instruments Corporation 3 11 PCI MIO E Series User Manual Analog Output PCI MIO 16E 1 and PCI MIO 16E 4 These PCI MIO E Series boards supply two channels of analog output voltage at the I O connector The reference and range for the analog output circuitry is software selectable The reference can be either internal or external whereas the range can be either bipolar or unipolar PCI MIO 16XE 10 The PCI MIO 16XE 10 supplies two channels of analog output voltage at the I O connector The range is software selectable between unipolar 0 to 10 V and bipolar 10 V PCI MIO 16XE 50
140. rom the digital lines When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals The following list gives recommended part numbers for connectors that mate to the I O connector on your PCI MIO E Series board Chapter 1 Introduction National Instruments Corporation 1 7 PCI MIO E Series User Manual Mating connectors and a backshell kit for making custom 68 pin cables are available from National Instruments part number 776832 01 PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 and the PCI MIO 16XE 50 Honda 68 position solder cup female connector part number PCS E68FS Honda backshell part number PCS E68LKPA Unpacking Your PCI MIO E Series board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions Ground yourself via a grounding strap or by holding a grounded object Touch the antistatic package to a metal part of your computer chassis before removing the board from the package Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into yo
141. rring PFI3 GPCTR1_SOURCE DGND Input Output PFI3 Counter 1 Source As an input this is one of the PFIs As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input Output PFI4 Counter 1 Gate As an input this is one of the PFIs As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output This output is from the general purpose counter 1 output Signal Name Reference Direction Description Continued Chapter 4 Signal Connections National Instruments Corporation 4 5 PCI MIO E Series User Manual PFI5 UPDATE DGND Input Output PFI5 Update As an input this is one of the PFIs As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the analog output primary group is being updated PFI6 WFTRIG DGND Input Output PFI6 Waveform Trigger As an input this is one of the PFIs As an output this is the WFTRIG signal In timed analog output sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input Output PFI7 Start of Scan As an input this is one of the PFIs As an output this is the STARTSCAN signal This pin pulses once at the start of each analog input scan in the interval
142. rs 3 18 to 3 19 specifications PCI MIO 16E 1 and PCI MIO 16E 4 A 10 PCI MIO 16XE 10 A 18 PCI MIO 16XE 50 A 25 troubleshooting See questions about PCI MIO E Series boards U UISOURCE signal 4 40 unipolar input See input polarity and range unipolar output 3 11 to 3 12 unpacking the PCI MIO E Series 1 7 UPDATE signal 4 38 to 4 40 input timing figure 4 39 output timing figure 4 39 V VCC signal PCI MIO 16E 1 and PCI MIO 16E 4 4 6 PCI MIO 16XE 10 4 7 PCI MIO 16XE 50 4 9 VirtualBench application software 1 3 voltage output PCI MIO 16E 1 and PCI MIO 16E 4 A 7 to A 8 PCI MIO 16XE 10 A 16 PCI MIO 16XE 50 A 23 W waveform generation timing connections 4 37 to 4 40 UISOURCE signal 4 40 UPDATE signal 4 38 to 4 40 WFTRIG signal 4 37 to 4 38 WFTRIG signal 4 37 to 4 38 input timing figure 4 38 output timing figure 4 38 wiring considerations 4 48
143. ry channel is configured for single ended input up to 16 analog input channels are available Chapter 4 Signal Connections National Instruments Corporation 4 19 PCI MIO E Series User Manual You can use single ended input connections for any input signal that meets the following conditions The input signal is high level greater than 1 V The leads connecting the signal to the PCI MIO E Series board are less than 10 ft 3 m The input signal can share a common reference point with other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions You can software configure the PCI MIO E Series board channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the PCI MIO E Series board provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the PCI MIO E Series board should not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal co
144. s LSBs 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 Chapter 3 Hardware Overview PCI MIO E Series User Manual 3 10 National Instruments Corporation When scanning among channels at various gains the settling times may increase When the PGIA switches to a higher gain the signal on the previous channel may be well outside the new smaller range For instance suppose a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100 the new full scale range is 100 mV if the ADC is in unipolar mode The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range For a 16 bit board to settle within 0 0015 15 ppm or 1 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle within 0 00004 0 4 ppm or 1 400 LSB of the 4 V step It may take as long as 200 s for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called cha
145. s Used in This Manual The following conventions are used in this manual bold Bold text denotes parameters bold italic Bold italic text denotes a note caution or warning italic Italic text denotes emphasis on a specific board in the PCI MIO E Series or on other important information a cross reference or an introduction to a key concept Macintosh Macintosh refers to all Macintosh computers with PCI bus unless otherwise noted monospace Text in this font denotes text or characters that are to be literally input from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions variables file names and extensions and for statements and comments taken from program code NI DAQ NI DAQ refers to the NI DAQ driver software for Macintosh or PC compatible computers unless otherwise noted PC Refers to all PC AT series computers with PCI bus unless otherwise noted About This Manual National Instruments Corporation xiii PCI MIO E Series User Manual SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for National Instruments plug in DAQ boards The indicates that the text following it applies only to specific PCI MIO E
146. scan and conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source Figure 4 23 shows the timing requirements for the SISOURCE signal Chapter 4 Signal Connections National Instruments Corporation 4 37 PCI MIO E Series User Manual Figure 4 23 SISOURCE Signal Timing Waveform Generation Timing Connections The analog group defined for your PCI MIO E Series board is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity se
147. t centers which are staffed by applications engineers Electronic Services National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information call 512 795 6990 You can access these services at United States 512 794 5422 Up to 14 400 baud 8 data bits 1 stop bit no parity United Kingdom 01635 551422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 01 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no parity To access our FTP site log on to our Internet host ftp natinst com as anonymous and use your Internet address such as joesmith anywhere com as your password The support files and documents are located in the support directories Bulletin Board Support FTP Support Click here to comment on this document via the National Instruments website at http www natinst com documentation daq Fax on Demand is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access Fax on Demand from a touch tone telephone at 512 418 1111 You can submit technical support questions to the applications engineering team through e mail at the Internet
148. t consult your computer user manual or technical reference manual for specific instructions and warnings Chapter 2 Installation and Con guration PCI MIO E Series User Manual 2 2 National Instruments Corporation 1 Write down the PCI MIO E Series board serial number in the PCI MIO E Series Hardware and Software Configuration Form in Appendix D Customer Communication of this manual 2 Turn off and unplug your computer 3 Remove the top cover or access port to the I O channel 4 Remove the expansion slot cover on the back panel of the computer 5 Insert the PCI MIO E Series board into a 5 V PCI slot Gently rock the board to ease it into place It may be a tight fit but do not force the board into place 6 If required screw the mounting bracket of the PCI MIO E Series board to the back panel rail of the computer 7 Replace the cover 8 Plug in and turn on your computer The PCI MIO E Series board is installed You are now ready to configure your software Refer to your software documentation for configuration instructions Board Configuration Due to the National Instruments standard architecture for data acquisition and the PCI bus specification the PCI MIO E Series boards are completely software configurable You must perform two types of configuration on the PCI MIO E Series boards bus related and data acquisition related configuration The PCI MIO E Series boards are fully compatible with th
149. t lets multiple devices operate at their peak NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages or National Instruments application software your application uses the NI DAQ driver software as illustrated in Figure 1 1 Chapter 1 Introduction National Instruments Corporation 1 5 PCI MIO E Series User Manual Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware Register Level Programming The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer using NI DAQ or application software to program your National Instruments DAQ hardware is easier than and as flexible as register level programming and can save weeks of development time ComponentWorks LabVIEW LabWindows CVI or VirtualBench Conventional Programming Environment NI DAQ Driver Software DAQ or SCXI Hardware Personal Computer or Workstation Chapter 1 Introduction PCI MIO
150. t signal will not be negative below 0 V unipolar input polarity is best However if the signal is negative or equal to zero you will get inaccurate readings if you use unipolar input polarity Table 3 3 Actual Range and Measurement Precision PCI MIO 16XE 10 and PCI MIO 16XE 50 Range Configuration Gain Actual Input Range Precision1 0 to 10 V 1 0 2 0 5 02 10 0 20 02 50 02 100 0 0 to 10 V 0 to 5 V 0 to 2 V 0 to 1 V 0 to 500 mV 0 to 200 mV 0 to 100 mV 152 59 V 76 29 V 30 52 V 15 26 V 7 63 V 3 05 V 1 53 V 10 to 10 V 1 0 2 0 5 02 10 0 20 02 50 02 100 0 10 to 10 V 5 to 5 V 2 to 2 V 1 to 1 V 500 to 500 mV 200 to 200 mV 100 to 100 mV 305 18 V 152 59 V 61 04 V 30 52 V 15 26 V 6 10 V 3 05 V 1 The value of 1 LSB of the 16 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 16 bit count 2 PCI MIO 16XE 10 only Note See Appendix A Specifications for absolute maximum ratings Chapter 3 Hardware Overview PCI MIO E Series User Manual 3 8 National Instruments Corporation Dither When you enable dither you add approximately 0 5 LSBrms of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of your PCI MIO E Series board as in calibration or spectral analysis In such applications noise
151. tage or current Glossary PCI MIO E Series User Manual G 4 National Instruments Corporation DAC0OUT analog channel 0 output signal DAC1OUT analog channel 1 output signal DAQ data acquisition a system that uses the computer to collect receive and generate electrical signals dB decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts DC direct current DGND digital ground signal DIFF differential mode DIO digital input output DIP dual inline package dithering the addition of Gaussian noise to an analog input signal DMA direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory DNL differential nonlinearity a measure in LSB of the worst case deviation of code widths from their ideal value of 1 LSB DO digital output E EEPROM electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed EXTREF external reference signal EXTSTROBE external strobe signal Glossary National Instruments Corporation G 5 PCI MIO E Series User Manual F FIFO first in first out memory buffer FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can
152. that the ADC and the PGIA inherently produce almost 0 5 LSBrms of noise This is equivalent to having a dither circuit that is always enabled Multichannel Scanning Considerations Most of the PCI MIO E Series boards can scan multichannels at the same maximum rate as their single channel rate however pay careful attention to the settling times for each of the boards The settling time for most of the PCI MIO E Series boards is independent of the selected gain even at the maximum sampling rate The settling time for the very high speed boards is gain dependent which can affect the useful sampling rate for a given gain No extra settling time is necessary between channels as long as the gain is constant and source impedances are low Refer to Appendix A Specifications for a complete listing of settling times for each of the PCI MIO E Series boards 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 LSBs LSBs LSBs LSBs 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 a Dither disabled no averaging b Dither disabled average of 50 acquisitions c Dither enabled no averaging 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 d Dither enabled average of 50 acquisitions LSBs LSBs LSB
153. ting signal source You must tie the ground reference of a floating signal to your PCI MIO E Series board analog input ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the PCI MIO E Series board assuming that the computer is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Input Configurations You can configure your PCI MIO E Series board for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Chapter 4 Sign
154. tor Use the Select_Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are tri stated 17 What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using the NI DAQ language interface or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config CTR Mode Config and CTR Pulse Config advanced level VIs to indicate which function the connected signal will serve Use the Route Signal VI to enable the PFI lines to output internal signals Warning If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the board the computer and the connected equipment Appendix C Common Questions PCI MIO E Series User Manual C 6 National Instruments Corporation 18 What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the board circuitry is not actively driving
155. uaranteed Input signal ranges Input coupling DC Max working voltage Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH lt 0 15 gt AISENSE FIFO buffer size 512 samples Gain Software Selectable Voltage Range Software Selectable Bipolar Unipolar 1 10 V 0 to 10 V 2 5 V 0 to 5 V 5 2 V 0 to 2 V 10 1 V 0 to 1 V 20 0 5 V 0 to 0 5 V 50 0 2 V 0 to 0 2 V 100 0 1 V 0 to 0 1 V Appendix A Speci cations for PCI MIO 16XE 10 National Instruments Corporation A 13 PCI MIO E Series User Manual Data transfers DMA interrupts programmed I O DMA modes Scatter gather Configuration memory size 512 words Transfer Characteristics Relative accuracy 0 75 LSB typ 1 LSB max DNL 0 5 LSB typ 1 LSB max No missing codes 16 bits guaranteed Offset error Pregain error after calibration 3 V max Pregain error before calibration 2 2 mV max Postgain error after calibration 76 V max Post
156. ur computer Never touch the exposed pins of connectors National Instruments Corporation 2 1 PCI MIO E Series User Manual Chapter2 Installation and Configuration This chapter explains how to install and configure your PCI MIO E Series board Software Installation Install your software before you install your PCI MIO E Series board Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence If you are using NI DAQ refer to your NI DAQ release notes Find the installation section for your operating system and follow the instructions given there If you are using LabVIEW LabWindows CVI or other National Instruments application software packages refer to the appropriate release notes After you have installed your application software refer to your NI DAQ release notes and follow the instructions given there for your operating system and application software package If you are a register level programmer refer to the PCI MIO E Series Register Level Programmer Manual and the DAQ STC Technical Reference Manual for software configuration information Hardware Installation You can install a PCI MIO E Series board in any available expansion slot in your computer However to achieve best noise performance leave as much room as possible between the PCI MIO E Series board and other boards and hardware The following are general installation instructions bu
157. ut high voltage IOUT 13 mA 4 35 V Appendix A Speci cations for PCI MIO 16XE 10 PCI MIO E Series User Manual A 18 National Instruments Corporation Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Data transfers DMA interrupts programmed I O DMA modes Scatter gather Triggers Analog Trigger Source ACH lt 0 15 gt PF10 TRIG1 Level fullscale internal 10 V external Slope Positive or negative software selectable Resolution 12 bits 1 in 4 096 Hysteresis Programmable Bandwidth 3 dB 255 kHz internal 4 MHz external External input PFI0 TRIG1 Impedance 10 k Coupling DC Protection 0 5 to Vcc 0 5 V when configured as a digital signal 35 V when configured as an analog signal or disabled 35 V powered off Accuracy
158. ut on the PFI1 TRIG2 pin Refer to Figure 4 12 for the relationship of TRIG2 to the DAQ sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIG1 signal initiates the data acquisition The scan counter indicates the minimum number of scans before TRIG2 can be recognized After the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The board ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the board will acquire a fixed number of scans and the acquisition will stop This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 17 and 4 18 show the input and output timing requirements for the TRIG2 signal Figure 4 17 TRIG2 Input Signal
159. uter VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors Using ComponentWorks LabVIEW LabWindows CVI or VirtualBench software will greatly reduce the development time for your data acquisition and control application Chapter 1 Introduction PCI MIO E Series User Manual 1 4 National Instruments Corporation NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with SCXI or accessory products except for the SCXI 1200 NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI self calibration messaging and acquiring data to extended memory NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments DAQ devices because i
160. voltage ratings are listed in the Protection column of Tables 4 1 to 4 3 In NRSE mode the AISENSE signal is connected internally to the negative input of the PCI MIO E Series board PGIA when their corresponding channels are selected In DIFF and RSE modes this signal is left unconnected AIGND is an analog input common signal that is routed directly to the ground tie point on the PCI MIO E Series boards You can use this signal for a general analog ground tie point to your PCI MIO E Series board if necessary Connection of analog input signals to your PCI MIO E Series board depends on the configuration of the analog input channels you are using and the type of input signal source With the different configurations you can use the PGIA in different ways Figure 4 2 shows a diagram of your PCI MIO E Series board PGIA Chapter 4 Signal Connections PCI MIO E Series User Manual 4 12 National Instruments Corporation Figure 4 2 PCI MIO E Series PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to your PCI MIO E Series board Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the board The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the ground for the board
161. whether local or from the RTSI bus is used directly by the board as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal This timebase is software selectable RTSI Triggers The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any PCI MIO E Series board sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 12 Chapter 3 Hardware Overview National Instruments Corporation 3 19 PCI MIO E Series User Manual Figure 3 12 RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4 for a description of the signals shown in Figure 3 12 RTSI Bus Connector switch RTSI Switch Clock Trigger 7 DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz National Instruments Corporation 4 1 PCI MIO E Series User Manual Chapter4 Signal Connections This chapter describes how to make input and output signal connections to your PCI MIO E Series board via the board I O connector The I O connector for the PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 and PCI MIO 16XE 50 has 68 pins that
162. y tgsu and tgh in Figure 4 35 The gate signal is not required to be held after the active edge of the source signal If you use an internal timebase clock the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the PCI MIO E Series boards Figure 4 35 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ_OUT Signal This signal is available only as an output on the FREQ_OUT pin The PCI MIO E Series board frequency generator outputs the FREQ_OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to tri state at startup Chapter 4 Signal Connections PCI MIO E Series User Manual 4 48 National Instruments Corporation Field Wiring Considerations Environmental noise can seriously affect the accuracy of measurements made with
163. you can connect to 68 pin accessories with the SH6868 shielded cable or the R6868 ribbon cable With the SH6850 shielded cable or R6850 ribbon cable you can connect your board to 50 pin signal conditioning modules and terminal blocks I O Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the PCI MIO E Series boards Refer to Appendix B Optional Cable Connector Descriptions for the pin assignments for the 50 pin connector A signal description follows the connector pinouts Warning Connections that exceed any of the maximum ratings of input or output signals on the PCI MIO E Series boards can damage the PCI MIO E Series board and the computer Maximum input ratings for each signal are given in the Protection column of Tables 4 1 4 2 and 4 3 National Instruments is NOT liable for any damages resulting from such signal connections Chapter 4 Signal Connections PCI MIO E Series User Manual 4 2 National Instruments Corporation Figure 4 1 I O Connector Pin Assignment for the PCI MIO E Series Boards 1 2 3 4 5 6 7 8 9 10 35 36 37 38 39 40 41 42 43 44 11 12 13 14 15 16 17 18 45 46 47 48 49 50 51 52 53 19 20 23 21 22 24 25 26 27 28 29 30 31 32 33 34 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 FREQ_OUT GP
164. your PCI MIO E Series board if you do not take proper care when running signal wires between signal sources and the board The following recommendations apply mainly to analog input signal routing to the board although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions Use differential analog input connections to reject common mode noise Use individually shielded twisted pair wires to connect analog input signals to the board With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference Route signals to the board carefully Keep cabling away from noise sources The most common noise source in a PCI data acquisition system is the video monitor Separate the monitor from the analog signals as much as possible The following recommendations apply for all signal connections to your PCI MIO E Series board Separate PCI MIO E Series board signal lines from high current or high voltage lines These lines can induce currents in or voltages on the PCI MIO E Series board signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling betwe

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