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38K2 Group User`s Manual

1. Rev 2 00 Oct15 2006 page 91 of 99 REJ09B0338 0200 ztENESAS 38K2 Group Function Details Addressing mode APPENDIX 3 6 Machine instructions A BIT A ZP BIT ZP n OP n JOP OP n 7 0 0 gt Ic This instruction shifts either A or M one bit to the right such that bit 7 of the result always is set to 0 and the bit 0 is stored in C 1 46 2 M S A amp A M zz X SesS i Multiplies Accumulator with the memory speci fied by the Zero Page X address mode and stores the high order byte of the result on the Stack and the low order byte in A NOP PC lt PC 1 This instruction adds one to the PC but does no otheroperation ORA When T 0 Note1 AC AVM When T 1 M X M X VM When T 0 this instruction transfers the con tents of A and M to the ALU which performs a bit wise OR and stores the result in A When T 1 this instruction transfers the con tents of M X and the M to the ALU which performs a bit wise OR and stores the result in M X The contents of A remain unchanged but status flags are changed M X represents the contents of memory where is indicated by X This instruction pushes the contents of A to the memory location designated by S and decrements the conten
2. APPENDIX APPENDIX 38K2 Group 3 6 Machine instructions 38K2 Group 3 6 Machine instructions Addressing mode Addressing mode Processor status register Function Details A BIT A ZP ABS X ABS Y IND ZP IND IND X IND Y REL 4 3 n JOP n JOP OP n JOP n JOP n JOP n JOP n JOP n JOP B D xex i This instruction subtracts one from the current contents of X YeY i This instruction subtracts one from the current contents of Y A amp M zz X 1 M zz X A M S lt one s comple ment of Remainder S lt S 1 Divides the 16 bit data in M zz X low order byte and M zz X 1 high order byte by the contents of A The quotient is stored in A and the one s complement of the remainder is pushed onto the stack When T 0 A lt AY M When T 1 M X M X M When T 0 this instruction transfers the con tents of the M and A to the ALU which performs a bit wise Exclusive OR and stores the result in A When T 1 the contents of M X and M are transferred to the ALU which performs a bit wise Exclusive OR and stores the results in M X The contents of A remain unchanged but status flags are changed M X represents the contents of memory where is indicated by X A lt A 1or MeM 1 This instruction adds one to the contents of A or M X X 1 This instruction adds one to the contents o
3. Change of AD conversion register Value of comparison voltage Vref At start of conversion o0oiololololo o o olo 0 First comparison 110101010100000 a Second comparison vi 1 0 0lo0 0 0 0 0 0 a 4 vet Third comparison et 211 0 0 0 0 0 010 a x weet P v NI NI N MN After completion of tenth A result of A D conversion A VREF VREF VREF comparison x1 x2 3 14 5 x6 7 x8 x9 x10 2 eeee 2 4 1024 31 10 A result of the first comparison to the tenth comparison Rev 2 00 Oct15 2006 page 129 of 130 RENESAS REJ09B0338 0200 38K2 Group Figures 168 shows the A D conversion equivalent circuit and ure 169 shows the A D conversion timing chart Vcc Vss About 2 kW Fig HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Built in D A converter Sampling clock Reference clock Fig 168 A D conversion equivalent circuit o JUUUUUUUUUU Chopper amplifier AD conversion register 2 HL AD conversion register 1 AD conversion interrupt request Write signal for AD L control register AD conversion completion bit Sampling clock 61 cycles Fig 169 A D conversion timing chart Rev 2 00 Oct15 2006 page 130 of 130 2tENESAS REJ09B0338 0200 CHAPTER 2 APPLICATION 2 1 I O port 2 2 Interrupt 2 3 Timer 2 4 Serial I O 2 5 USB function 2 6 HUB function 2 7 External bus i
4. State remaining Fig 3 4 41 Structure of EP00 byte number register EP01 byte number register 0 EPO1BYTO address 001 E16 At reset H W BOBYT01 IN Transmit byte number bit Single buffer mode Set the transmitting byte number 0 6 0 Double buffer mode Set the transmitting byte number of buffer 0 OUT Receive byte number bit Single buffer mode The received byte number is automatically set Double buffer mode The received byte number of buffer 0 is automatically set Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 3 4 42 Structure of EP01 byte number register 0 EP02 byte number register 0 EPO2BYTO address 001E16 At reset H W S W BOBYT02 IN Transmit byte number bit Single buffer mode Set the transmitting byte number 0 6 0 Double buffer mode Set the transmitting byte number of buffer 0 OUT Receive byte number bit Single buffer mode The received byte number is automatically set Double buffer mode The received byte number of buffer 0 is automatically set Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function e remaining Fig 3 4 43 Structure of EP02 byte number register 0 Rev 2 00 Oct 15 2006 page 55 of 99 2tENESAS REJ09B0338 0200 APPENDIX
5. EP01REQ BORDY01 BiRDY0O1 ERRO1 EPO2REQ BORDY02 B1RDY02 ERR02 EPO3REQ BORDY03 B1RDY03 ERR03 EP10REQ BRDY10 CTEND10 CTSTS10 BSYDY10 ERR10 EP11REQ BORDY11 Fig 29 USB device interrupt control Rev 2 00 Oct 15 2006 page 31 of 130 7tENESAS REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION USB Register List The USB register list is shown below USB SFR Address Register Name SYMBOL bite bits bid bits bit 001016 USB control register USBCON UCLKCON USBDIFE VREFE VREFCON TRONCON 001116 USB Function Hub enable register USBAE ae z ADIE 001216 USB function address register USBAO USBADDO 6 0 001316 USB HUB address register USBA1 USBADD1 6 0 001416 Frame number register Low FNUML FNUM 7 0 001516 Frame number register High FNUMH FNUM 10 8 001616 USB interrupt source enable register USBICON EP10E EPO1E EPOOE 001716 USB interrupt source register USBIREQ EP10 EP01 EP00 001816 Endpoint index register USBINDEX EPIDX 1 0 001916 Endpoint field register 1 EPXXREG1 001A16 Endpoint field register 2 EPXXREG2 001Bie Endpoint field register 3 EPX
6. Fig 3 4 51 Structure of Timer 1 Rev 2 00 Oct 15 2006 page 58 of 99 2tENESAS REJ09B0338 0200 38K2 Group Timer 2 Timer X b7 b6 b5 b4 b3 b2 b1 bO Timer 2 T2 Address 2216 Timer X TX Address 2516 Set a count value of each timer The value set in this register is written to both each timer and each timer latch at the same time When this register is read out each timer s count value is read out Fig 3 4 52 Structure of Timer 2 Timer X Timer X mode register b7 b6 b5 b4 b3 b2 b1 bO Timer X mode register TM Address 2316 Timer mode Pulse output mode Event counter mode Pulse width measurement mode The function depends on the operating mode of Timer X Refer to Table 2 3 1 Fig 3 4 53 Structure of Timer X mode register Rev 2 00 Oct15 2006 page 59 of 99 2tENESAS REJ09B0338 0200 APPENDIX 3 4 List of registers W Kaku ane mag Rae ee aaa EJEN EARE APPENDIX 38K2 Group 3 4 List of registers Transmit Receive buffer register b7 b6 b5 b4 b3 b2 b1 bO Transmit Receive buffer register TB RB Address 2616 The transmission data is written to or the receive data is read out from this buffer register e At writing A data is written to the transmit buffer register e At reading The contents of the receive buffer register are read out Note The contents of transmit buffer regi
7. USB function Stopped HUB function Stopped External BUS interface Stopped A D converter Stopped Comparator Stopped Rev 2 00 Oct 15 2006 page 96 of 112 RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 13 Standby function 2 Release of stop mode The stop mode is released by a reset input or by the occurrence of an interrupt request Note the differences in the restoration process according to reset input or interrupt request as described below Restoration by reset input The stop mode is released by holding the RESET pin to the L input level during the stop mode Oscillation is started when all ports are in the input state and the stop mode of the main clock Xin Xout is released Oscillation is unstable when restarted For this reason time for stabilizing of oscillation oscillation stabilizing time is required The input of the RESET pin should be held at the L level until oscillation stabilizes When the RESET pin is held at the L level for 16 cycles or more of Xi after the oscillation has stabilized the microcomputer will go to the reset state After the input level of the RESET pin is returned to H the reset state is released in approximately 10 5 to 18 5 cycles of the Xin input Figure 2 13 3 shows the oscillation stabilizing time at restoration by reset input At release of the stop mode by reset input the internal RAM retains its contents previous to the reset However the
8. Output buffer EXB data input lt Input buffer 6 Ports P34 P35 P36 P37 External bus interface enable bit gt 4 A D conversion input oo Analog input pin selection bit Direction register Data bus Port latch 3 Port P2 J Direction register ExCS P34 EWRES ean ExRD P36 External bus interface enable bit Data bus Port latch ExA0 P37 Fig 10 Port block diagram 1 Rev 2 00 Oct 15 2006 page 14 of 130 2RENESAS REJ09B0338 0200 38K2 Group 7 Port P40 Serial I O enable bi Receive enable bit External bus interface enable bi gt Direction register t Data bus gt Port latch ExDreq output p Serial I O input 8 Port P41 External bus interface enable bit gt Serial I O enable bit Receive enable bit Direction register Data bus _ Port latch Serial I O output ExDack 9 Port P42 Serial I O enable bit Serial I O mode selection bit External bus interface enable bit Serial I O synchronous clock selection bit Da Serial I O enable bit External bus
9. State remaining Fig 93 Structure of HUB interrupt source enable register b7 bO fofofofofo HUB interrupt source register HUBIREQ address 002916 Bit symbol Bit name Function At reset H W S W DP1 HUB downstream port 1 This bit is set to 1 when any one of DP1 interrupt 0 interrupt bit source register s bits at least is set to 1 This bit is cleared to 0 by clearing DP1 interrupt source register to 0016 Writing to this bit causes no state change HUB downstream port 1 This bit is set to 1 when any one of DP2 interrupt interrupt bit source register s bits at least is set to 1 This bit is cleared to O by clearing DP2 interrupt source register to 0016 Writing to this bit causes no state change Not used Write 0 when writing 0 is read when reading HUB upstream port remote 0 Remote wakeup being not output wakeup output enable bit 1 Remote wakeup being output This bit change is not for a interrupt source When detecting 2 5 us or more of K signal on a downstream port in Hub suspended state K signal is output on from a upstream port and this bit is simultaneously set to 1 0 can be set by software but 1 cannot be set State remaining Fig 94 Structure of HUB interrupt source register Rev 2 00 Oct 15 2006 page 63 of 130 RENESAS
10. ExDREQ Mch_req Fig 3 1 7 Timing chart 4 Rev 2 00 Oct 15 2006 page 17 of 99 2RENESAS REJ09B0338 0200 38K2 Group Timing chart EXB lt Memory channel mode DMA interface pin function Read and write signals not required mode gt lt Read gt ExDACK DQo to DQ7 twL ACk le L 0 8Vcc 0 2Vcc APPENDIX 3 1 Electrical characteristics ExDREQ Mch_req 0 8Vcc td gab tv ACK D lt Write gt ExDACK DQo to DQ7 twL ACk lt 0 8Vcc 0 2Vcc td ACK Men 0 2Vcc tsu D ACK th ACK D a 0 8Vcc ExDREQ Mch_req 0 2Vcc Fig 3 1 8 Timing chart 5 Rev 2 00 Oct15 2006 page 18 of 99 REJ09B0338 0200 2tENESAS td ACK Men 0 2Vcc APPENDIX 38K2 Group 3 1 Electrical characteristics Timing chart EXB lt Memory channel mode Burst transfer gt lt Read gt saek A AAO SMU twL R twH R 0 8Vcc 0 2Vcc 7L tw cycle DQo to DQ7 i lt gt td R Mdis lt ExDREQ Mch_req lax lt Write gt swak A AA SSN twL W twH W 0 8Vcc 0 2Vcc7r tw cycle DQo to DQ7 td W Mdis ExDREQ Mch_req ee Fig 3 1 9 Timing chart 6 Rev 2 00 Oct 15 2006 page 19 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use
11. State remaining Fig 3 4 57 Structure of HUB interrupt source register b7 bO fofofofofololo HUB downstream port index register HUBINDEX address 002A16 At reset i i i Riw Bit symbol Bit name Function aw Siw DPIDX HUB downstream port index bit 0 HUB downstream port 1 0 o0 1 HUB downstream port 2 i b7 b1 Not used Write 0 when writing 0o 0 is read when reading State remaining Fig 3 4 58 Structure of HUB downstream port index register Rev 2 00 Oct 15 2006 page 61 of 99 7RENESAS REJ09B0338 0200 38K2 Group APPENDIX 3 4 List of registers DP1 interrupt source register DP1REQ address 002B16 Bit symbol Bit name Function At reset H W S W PTDIS1 Downstream port 1 disconnect detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus disconnect state 2 5 us or more of SEO on a downstream port 1 in DSCONN1 1 0 can be set by software but 1 cannot be set 0 PTCON1 Downstream port 1 connect detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus connect state 2 5 us or more of J or K state on a downstream port 1 in DSCONN1 0 0 can be set by software but 1 cannot be set PTER
12. Bit symbol Bit name Function At reset H W S W CTENDE10 Control transfer completion enable bit 0 NAK transmission in the status stage 1 Control transfer completion enabled SIE transmits NULL ACK Valid in PID10 012 At reception of SETUP token This bit is cleared to 0 by the hardware 0 Not used Write 0 when writing 0 is read when reading Fig 77 Structure of EP10 control register 3 EP10 interrupt source register EP10REQ address 001D16 State remaining Bit symbol Bit name Function At reset H W S W BRDY10 USB HUB Endpoint 10 buffer ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer is ready state enabled to be read written on USB HUB Endpoint 10 0 can be set by software but 1 cannot be set 0 0 CTEND10 USB HUB Endpoint 10 control transfer completion interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when control transfer is completed NULL ACK transmission in the status stage on USB HUB Endpoint 10 0 can be set by software but 1 cannot be set CTSTS10 USB HUB Endpoint 10 status stage transition interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to
13. At reset H W S W BOBYT03 IN Transmit byte number bit Single buffer mode Set the transmitting byte number 9 6 0 Double buffer mode Set the transmitting byte number of buffer 0 OUT Receive byte number bit Single buffer mode The received byte number is automatically set Double buffer mode The received byte number of buffer 0 is automatically set Write 0 when writing 0 is read when reading Bit symbol Bit name Function e remaining Fig 70 Structure of EP03 byte number register 0 EP03 byte number register 1 EPO3BYT1 address 001F 16 At reset H W B1BYT03 IN Transmit byte number bit Single buffer mode These bits are invalid 0 6 0 Double buffer mode Set the transmitting byte number of buffer 1 OUT Receive byte number bit Single buffer mode These bits are invalid Double buffer mode The received byte number of buffer 1 is automatically set Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 71 Structure of EP03 byte number register 1 EP03 MAX packet size register EPO3MAX address OFEC16 At reset Bit symbol Bi Function y it name HW MXPS03 Max packet size bit IN These bits are invalid 6 0 OUT Set the maximum packet size b7 Not used Write 0 when writing 0
14. Serial I O output External bus interface funciton input Serial I O control register EXB control register CMOS compatible input level CMOS 3 state output External interrupt input Port P5 pull up control register Interrupt edge selection register Timer X function I O Timer X mode register Note Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction When an input level is at an intermediate poten tial a current will flow from Vcc to Vss through the input stage gate Rev 2 00 Oct15 2006 page 13 of 130 REJ09B0338 0200 RENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION Pull up control bit 4 Ports P30 P32 Direction regis Tt gt Direction register f Y Data bus _ Port latch Data bus gt _ Port latch 2 N 3A Key on wake up input 2 Port P1 5 Port P33 TL External bus interface enable bi External bus interface enable bit 4 m Direction register f al Direction register Data bus _ Port latch Data bus _ Port latch jj ExINT output gt EXB data output
15. aNH ESN L Jaw Bopyoye M yno Bulyesoueb 490 D snq eleq RENESAS 38K2 Group 29A SSA 1NnOX NIX 99 d SSAd Fig 2 Functional block diagram v aAt900dO1d Y Y9v900dO d e6e49ed NVYOSVIG XO014 IWNOILONNS Rev 2 00 Oct15 2006 page 3 of 130 REJ09B0338 0200 38K2 Group PIN DESCRIPTION Table 1 Pin description Pin Name HARDWARE PIN DESCRIPTION Function Function except a port function Vcc Vss Power source e Apply voltage of 3 0 V 5 25 V L version to Vcc and 0 V to Vss VccE Analog power source e Power source pin for ports P1 P3 P4 and analog circuit Connect this pin to Vcc CNVss CNVss e This pin controls the operation mode of the chip Connect this pin to Vss In the flash memory mode this pin becoems VPP power source input pin CNVss2 CNVss2 e This pin controls the operation mode of the chip Connect this pin to Vss VREF Analog reference voltage input e Reference voltage input pin for A D converter DVcc PVcc PVss Analog power source e Power source pin for analog circuit Connect the DVcc and PVcc pins to Vcc and the PVss pin to Vss RESET Reset input e Reset input pin for active L XIN Clock input XOUT Clock output e Input and output pins for the main clock generating cir
16. ccccccecesesceeceeeeeeeeeeeceneeeeeeaeeseeeeeesaeeseeeeeessaeeeseaeees 55 Fig 2 4 24 Connection diagram 0 ccecceceeeceeeeeceeeeeecaeeeeeeeeeceaeeeeeaaeeceaeeeesaaeeseeeeeesaaeseeeeeesiaeeseaeees 56 FIGs 224225 TAM CNAN seso aa EE aa ESAEREN ER 57 Fig 2 4 26 Related registers setting cccecececceeeeeseeceeeeeeseneeeeeeeeeeeseeeseeeeeseeseeaeeeeenenaeeeeeeneneees 57 Fig 2 4 27 Control procedure of master unit essesesssssrsssrisssrsssrsrrssrissstisstinsstnnnstnssnnsnnn nent 58 Fig 2 4 28 Control procedure of slave unit essssssesessssrssrrssrrrsrsrsrissrrissrisssiisssrnssrnnstnnsnn nent 59 Fig 2 4 29 Connection diagram Communication using UART sssssesseesssesssessressrrsssrssrrnses 60 Fig 2 4 30 Timing chart using VART c ee ceeeeeeeeeeee eee eeeeeae eee eeeaaeeeeeeeeaaeeeeeeeaaaeeeeeeeaeeeeeneaaaes 60 Fig 2 4 31 Registers setting related to transmitting side eee rennet 62 Fig 2 4 32 Registers setting related to receiving side 0 eee eeteeeeeeeneeeeeeeeeeaeeeeetenaaeeeeeneaaees 63 Fig 2 4 33 Control procedure of transmitting side ececeeeeeceeeeeeeeeeeeeeeeeaeeseeeeeetiaeeeseeees 64 Fig 2 4 34 Control procedure of receiving Side cceecceceeceeeeeeteceeeeeeeeceeeeeeesaaeeeeeeeeeseaeeeeeaeees 65 Fig 2 4 35 Sequence of setting serial I O control register again eceeeeeeeeeeeeeeeeeeteeees 67 Rev 2 00 Oct 15 2006 page 8 of 14 RENESAS REJ09B0338 0200 38K2 Group List of f
17. 0 control transfer completion disabled on USB function Endpoint 0 0 can be set by software but 1 cannot be set lt Transition to status stage occurrence factor gt At transfer of control write When receiving IN token in data stage OUT At transfer of control read When receiving OUT token in data stage IN At no data transfer Nothing occurs BSRDY00 USB function Endpoint 0 SETUP buffer ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the exclusive buffer for SETUP is ready state enabled to be read on USB function Endpoint 0 0 can be set by software but 1 cannot be set USB function Endpoint 0 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when control transfer error occurs on USB function Endpoint 0 This bit is cleared to 0 by the hardware when receiving SETUP token 0 can be set by software but 1 cannot be set Write 0 when writing 0 is read when reading State remaining Fig 3 4 35 Structure of EP0OO interrupt source register Rev 2 00 Oct15 2006 page 51 of 99 REJ09B0338 0200 2tENESAS 38K2 Group APPENDIX 3 4 List of registers b7 bo fofofofofol EP01 interrupt source register EP01REQ address 001D16 Bit symbol Bit name At rese
18. VI VSS Rev 2 00 Oct15 2006 page 5 of 99 RAM hold voltage REJ09B0338 0200 When clock is stopped 2RENESAS APPENDIX 38K2 Group 3 1 Electrical characteristics L Ver Table 3 1 5 Electrical characteristics 2 Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Typ Power source current f XIN system clock 12 MHz 21 0 Output transistor is isolated Parameter Test conditions o 6 MHz USB reference voltage circuit enabled f XIN 12 MHz 22 5 System clock 8 MHz USB reference voltage circuit enabled f XIN 6 MHz 22 0 System clock 8 MHz USB reference voltage circuit enabled f XIN system clock 6 6 MHz 21 0 USB reference voltage circuit enabled Vcc 3 00 f XIN system clock 6 6 MHz to 4 00 V USB reference voltage circuit disabled Vcc 3 00 f XIN system clock 6 MHz to 3 60 V USB reference voltage circuit disabled Vcc 4 00 f XIN 12 MHz to 5 25V System clock b 8 MHz USB reference voltage circuit enabled Vcc 3 00 f XIN system clock 6 MHz to 4 00 V USB reference voltage circuit disabled Vcc 4 00 USB reference voltage circuit enabled to 5 25 V Low current mode Vcc 3 00 USB reference voltage circuit disabled to5 25V Ta 25 C USB reference voltage circuit disabled Ta 85 C lt Test conditions g
19. When a rise of ExWR is detected an internal memory access sequence which synchronized with a rise of is activated and a data is written in the internal memory within two clocks at a minimum The memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made When the write operation to the end address has been completed the memory address counter is increased but assertion of the next memory channel request is not made and the memory channel operation end interrupt is generated Fig 124 Memory channel receiving operation 1 Rev 2 00 Oct 15 2006 page 84 of 130 2RENESAS REJ09B0338 0200 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION 4 Memory Channel Receiving Operation 2 Burst Mode Memory channel receiving operation 2 is shown bellow Address ExA0 Chip select ExCS DMA acknowledge ExDACK GS l Dack 0 Dack 0 Read ExRD Write EXWR Data DQo to DQ7 l Internal clock LPL LI LT DMA request V ExDREQ TL R LS FL Booo fe 7 PLILI UU UU UTE UT LU Ud mWR 4 detection MWR 7 detection Receive buffer RXBUF Operation enabled Main sequencer Memory channel operation end interrupt Internal memory access Memory address 010016 py 010116 A Counter end Burst end U LL LAL ET LYELL PLL Er Ere Acknowled
20. also set the address signal AO to L If AO is H the memory channel and the CPU channel are activated simultaneously and it might cause some error Rev 2 00 Oct15 2006 page 75 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION P42 ExTC ScLK pin This pin is a port at the initial state The terminal count signal can be set by program If the terminal count signal is set at one bus cycle while a memory channel operation write is being performed the 38K2 group con firms that its bus cycle is the write cycle of the last data and sets the memory channel status bits to 112 and the interrupt is gener ated and the memory channel operation ends even if the memory address counter has not reached the end address The CPU can obtain the last address where the data is written by reading out the value of memory address counter See Figure 126 2tENESAS 38K2 Group EXB Register List The EXB register list is shown below HARDWARE FUNCTIONAL DESCRIPTION Address Register Name SYMBOL EXB SFR bit3 bit1 bito 003016 EXB interrupt source enable register EXBICON TXB_ENB RXB_EMB 003116 EXB interrupt source register EXBIREQ TXB_EMPTY RXB_FULL 003316 EXB index register EXBINDEX 003416 Register window 1 low EXBREG1 INDEX 2 0 LOW_WIN 7 0 003516 Register window 2 high EXBREG2 Fig 107 EXB related registers 1 EXB interrupt source
21. 0 is read when reading Bit symbol Bit name Function State remaining Fig 3 4 63 Structure of DP1 status register b7 bO fofofofofofo DP2 status register DP2STS address 002D16 Bit symbol Bit name Function At reset H W S W D2MINUS D2 signal bit In DSRMOD2 0 a downstream port 2 bus state is In In read using RD signal definite definite In DSRMOD2 1 a downstream port 2 bus state is read using EOF2 signal internal signal D2PLUS D2 signal bit In DSRMOD2 0 a downstream port 2 bus state is In In read using RD signal definite definite In DSRMOD2 1 a downstream port 2 bus state is read using EOF2 signal internal signal Not used Write 0 when writing 0 is read when reading State remaining Fig 3 4 64 Structure of DP2 status register b7 bo ofofofofo EXB interrupt source enable register EXBICON address 003016 Note Bit symbol Bit name Function At reset H W S W RXB_ENB CPU channel receive enable bit 0 Operation disabled Interrupt disabled 0 Operation enabled Receive buffer full interrupt enabled TXB_ENB CPU channel transmit enable bit 0 Operation disabled Interrupt disabled Operation enabled Transmit buffer empty interrupt enabled MC_ENB Memory channel operation
22. 0016 External I O configuration register 0116 Transmit Receive buffer register 0216 Memory channel operation mode register 0316 Memory address counter In In definite definite 0416 End address register Fig 112 Structure of Register window 1 Register window 2 EXBREG2 address 003516 Bit symbol Bit name Function At reset H W HIGH_WIN 7 0 The accessible register using this register window depends on the EXB index register contents as follows Index value 0016 External I O configuration register 0116 Transmit Receive buffer register 0216 Memory channel operation mode register 0316 Memory address counter 0416 End address register definite definite In In Fig 113 Structure of Register window 2 Rev 2 00 Oct15 2006 page 78 of 130 REJ09B0338 0200 2RENESAS 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION Index 0016 External I O configuration register EXBCFGL address 003416 Bit symbol Bit name Function At reset H W EXB_CTR EXB pin control bit Pins P10 to P17 P30 to P34 0 Port 1 EXB function pin 0 INT_CTR 2 0 P33 ExINT pin control bit Selects a signal of P33 ExINT pin ON OFF is programmed by each bit An output logical sum of P33 ExINT pins set for ON are performed and it is out
23. 4 lt d P07 output 4 4 N gt LL 0 register Port POs direction register 1 POs output i D LL 0 regis Port POs 5 0 direction register 1 Port POs re latch AD POs output l T LL 0 regis Port P04 direction register 1 PES HD P04 output if LL 0 regis 3 1 Port POs direction register O Port PO sal EF pon pos F Input reading circuit POs input pete o 0 I D LL 0 regis 2 1 4 Port P02 latch P02 input 4 O O t JD LL 0 register 1 1 a Port PO1 i Y latch P01 input L O O T 1D LL 0 regis O 1 Port POo direction register 0 Port P02 direction register 0 Port P01 direction register 0 k a Port POo latch POo input O O T HD ge P channel transistor for pull up 3x CMOS output buffer Fig 2 2 13 Connection example and port PO block diagram when using key input interrupt Rev 2 00 Oct 15 2006 page 19 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 2 Interrupt 2 Related registers setting Figure 2 2 14 shows the related registers
24. Fig 155 Timing for page read Read Status Register Command This command reads status information When the 7016 com mand code is transferred with the 1st byte the contents of the status register SRD with the 2nd byte and the contents of status register 1 SRD1 with the 3rd byte are read RxD 7016 SRD SRD1 TxD output SRDY BUSY Fig 156 Timing for reading status register Rev 2 00 Oct 15 2006 page 116 of 130 2RENESAS REJ09B0338 0200 38K2 Group Clear Status Register Command This command clears the bits SR3 to SR5 which are set when the status register operation ends in error When the 5016 com mand code is sent with the 1st byte the aforementioned bits are cleared When the clear status register operation ends the SRDY BUSY signal changes from H to L level HARDWARE FUNCTIONAL DESCRIPTION TxD SRDY BUSY Fig 157 Timing for clear status register Page Program Command This command writes the specified page 256 bytes in the flash memory sequentially one byte at a time Execute the page pro gram command as explained here following 1 Transfer the 4116 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and 3rd bytes respectively i As to VA16 to ate PAE A aa hoata 3 From the 4th byte onward as write data Do to D7 for the page 256 bytes specified with addresses As to A23 is
25. Not used Write 0 when writing 0 is read when reading Fig 36 Structure of Frame number register High Rev 2 00 Oct15 2006 page 34 of 130 REJ09B0338 0200 2RENESAS State remaining 38K2 Group bo USB interrupt source enable register USBICON address 001616 HARDWARE FUNCTIONAL DESCRIPTION Bit symbol Bit name Function At reset H W S W EPOOE USB function Endpoint 0 interrup enable bi Interrup Interrupt disab enabl 0 0 EPO1E USB function Endpoint 1 interrup enable bi Interrup Interrupt disab enabl EP02E USB function Endpoint 2 interrup enable bi Interrup Interrupt disab enabl EPO3E USB function Endpoint 3 interrup enable bi Interrup Interrupt disab enabl EP10E USB HUB Endpoint 0 interrupi enable bi Interrup Interrupt disab enabl EP11E USB HUB Endpoint 1 interrup enable bi Interrup Interrupt disab enabl SUSE Suspend interrupt enable bit Interrup Interrupt disab enabl RSME Resume interrupt enable bit Oj OJ OJ Ol oO oj oj o Interrup Interrupt disab enabled Fig 37 Structure of USB interrupt source enable register Rev 2 00 Oct15 2006 page 35 of 130 REJ09B0338 0200 2tENESAS 38K2 Group HARDWARE FUNCT
26. UART control register Address OFE116 b7 bO UARTCON i fal folol Character length selection bit 8 bits Parity enable bit Parity checking disabled Stop bit length selection bit 2 stop bits Baud rate generator Address OFE216 f XiNn Transfer bit rate X 16 X m When bit 0 of the Serial I O control register Address OFE016 is set to 0 a value of m is 1 When bit 0 of the Serial I O control register Address OFE016 is set to 1 a value of m is 4 Fig 2 4 32 Registers setting related to receiving side Rev 2 00 Oct 15 2006 page 63 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Figure 2 4 33 shows a control procedure of the transmitting side and Figure 2 4 34 shows a control procedure of the receiving side RESET x This bit is not used here Set it to O or 1 arbitrarily Initialization SIOCON Address OFEO16 lt 1001x0002 UARTCON Address OFE116 lt 000010002 BRG Address OFE216 lt 39 1 P2 Address 0416 bit4 lt 0 P2D Address 0516 lt xxx1Xxxxe e Port P24 set for communication control eee Y P2 Address 0416 bit4 lt 1 e Communication start e Transmission data write The first byte of a MSIRB vAddress S datal Transmit buffer empty flag is set to O by this writing An interval of 10 ms generated by Timer e Judgment of transferring data from Transmit SIOSTS Address 2716 bit0
27. oF is xA Port P02 O Q o t PULL 0 register Bit 1 1 Port POI Port P01 direction register 0 P01 input latch O 0 KC Jp PULL 0 register Bit 0 1 Port P0o direction register 0 POo input 4 Port POo latch O O Jp Fig 15 Connection example when using key input interrupt and port PO block diagram Rev 2 00 Oct15 2006 page 19 of 130 REJ09B0338 0200 2RENESAS gt 3 P channel transistor for pull up k CMOS outout buffer 38K2 Group TIMERS The 38K2 group has three timers timer X timer 1 and timer 2 The division ratio of each timer or prescaler is given by 1 n 1 where n is the value in the corresponding timer or prescaler latch All timers are down count timers When the timer reaches 0016 an underflow occurs at the next count pulse and the correspond ing timer latch is reloaded into the timer and the count is contin ued When a timer underflows the interrupt request bit corre sponding to that timer is set to 1 bO Timer X mode register TM address 002316 Timer X operating mode bits b1 bO 0 0 Timer mode 0 1 Pulse output mode 1 0 Event counter mode 1 1 Pulse width measurement mode CNTRo active edge switch bit 0 Falling edge active for CNTRo interrupt Count at rising edge in event counter
28. the high order 8 bits becomes 0116 Figure 6 shows the store and the return movement into the stack If there are registers other than those described in Figure 5 the users need to store them with the program Program Counter PC The program counter is a 16 bit counter consisting of two 8 bit registers PCH and PCL It is used to indicate the address of the next instruction to be executed Accumulator Index register X Index register Y Stack pointer Program counter bO N vitelo zic Processor status register PS Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag 2RENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION On going Routine Interrupt request gt Note Execute JSR lt Push return address on stack gt S lt gt n l C A L Push return address on stack M S PS status register on stack S Push contents of processor PCn 6 1 PCL S 1 Interrupt Service Routine g T C Flag is set from 0 to 1 Fetch the jump vector Execute RTS Execute RTI POP return address from stack POP contents of processor status register from stack G jo e A A G G ae POP return address from stack D A v PCH M S
29. 1 it is necessary to write 0 and then write 1 in succession To release the reset it is necessary to set this bit to 0 Bit 4 is the User Area Boot Area Select Bit When this bit is set to 1 Boot ROM area is accessed and CPU rewrite mode in Boot ROM area is available In Boot mode this bit is set to 1 auto matically Reprogramming of this bit must be in a memory other than internal flash memory Figure 148 shows a flowchart for setting releasing CPU rewrite mode Flash memory control register address OFFE16 FMCR Note 1 RY BY status flag 0 Busy being written or erased 1 Ready CPU rewrite mode select bit Note 2 0 Normal mode Software commands invalid 1 CPU rewrite mode Software commands acceptable CPU rewrite mode entry flag 0 Normal mode Software commands invalid 1 CPU rewrite mode Flash memory reset bit Note 3 0 Normal operation 1 Reset User area Boot area select bit Note 4 0 User ROM area accessed 1 Boot ROM area accessed Reserved bits indefinite at read O at write Notes 1 The contents of flash memory control register are XXX00001 just after reset release 2 For this bit to be set to 1 the user needs to write O and then 1 to it in succession If it is not this procedure this bit will not be set to 1 Additionally it is required to ensure that no interrupt will be generated during that interval Use the
30. 32 byte unit b4b3b2b1b0 000 1 0 004016 006016 03C016 03E016 0 Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 97 Structure of EP10 buffer area set register Rev 2 00 Oct15 2006 page 78 of 99 REJ09B0338 0200 2RENESAS APPENDIX 38K2 Group 3 4 List of registers EP11 buffer area set register EP11BUF address OFED16 At reset H W S W BADD11 EP11 beginning address set bit Set the beginning address of EP11 s buffer area 0 4 0 32 byte unit b4b3b2b1b0 004016 006016 Bit symbol Bit name Function 030016 03E016 Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 98 Structure of EP11 buffer area set register Port PO pull up control register b7 b6 b5 b4 b3 b2 bi bO Port PO pull up control register PULLO Address OFF016 B Name Function fraja o POo pul l up control bit E up ns gt No pull i i POo pul l up control bit 1 Pulp up 0 Joio P00 pul l up control bit n a 0 foto 2 rovpuitupconteiot_ 7 patp e foo a Poopurupcomoron fipur forol 5 Poopurup cono 9 puke feol oea e a 0 No pull up 7 POo pul l up control bit 1 Pull up Fig 3 4 99 Structure of Port PO pull up control register Rev 2 00 Oct15 2006 page 79 of 99 2tENESAS REJ09B0338 0200 A
31. Ai or Mi 0 This instruction tests the designated bit i of M or A and takes a branch if the bit is 0 The branch address is specified by a relative ad dress If the bit is 1 next instruction is executed BBS Ai or Mi 1 This instruction tests the designated bit i of the Note 4 M or A and takes a branch if the bit is 1 The branch address is specified by a relative ad dress If the bit is 0 next instruction is executed This instruction takes a branch to the ap pointed address if C is 0 The branch address is specified by a relative address If C is 1 the next instruction is executed This instruction takes a branch to the ap pointed address if C is 1 The branch address is specified by a relative address If C is 0 the next instruction is executed This instruction takes a branch to the ap pointed address when Z is 1 The branch address is specified by a relative address If Z is 0 the next instruction is executed This instruction takes a bit wise logical AND of A and M contents however the contents of A and M are not modified The contents of N V Z are changed but the contents of A M remain unchanged BMI This instruction takes a branch to the ap Note 4 pointed address when N is 1 The branch address is specified by a relative address If N is 0 the next instruction is executed This instruction takes a branch to the ap pointed address if Z is 0 The b
32. Main clock input L pulse width tc CNTR CNTRo input cycle time twH CNTR CNTRo input H pulse width twL CNTR CNTRo input L pulse width twH INT INTo INT1 input H pulse width twL INT INTo INT1 input L pulse width tc SCLk Serial I O clock input cycle time Note tWH SCLKk Serial I O clock input H pulse width Note twL SCLk Serial I O clock input L pulse width Note tsu RxD SCLk Serial I O input set up time th SCLK RxD Serial I O input hold time Note These limits are the rating values in the clock synchronous mode bit 6 of address OFE016 1 In the UART mode bit 6 of address OFE016 0 the rating values are set to one fourth Rev 2 00 Oct15 2006 page 8 of 99 REJ09B0338 0200 2RENESAS 38K2 Group Table 3 1 9 Timing requirements of external bus interface EXB 1 Vcc 4 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter APPENDIX 3 1 Electrical characteristics L Ver Limits Typ tsu S R ExCS setup time for read tsu S W ExCS setup time for write th R S ExCS hold time for read th W S ExCS hold time for write tsu A R ExA0 ExA1 setup time for read tsu A W ExA0 ExA1 setup time for write th R A ExA0 ExA1 hold time for read th W A ExA0 ExA1 hold time for write tsu ACK
33. gt lt P63 LED3 P10 DQo ANo 4 gt lt P62 LEDz2 4 gt P61 LED1 P11 DQ1 AN1 lt lt gt TSE g BE SStseesRAerws G2 OAS Z2Z22Z2222Z 2 Wo gt OW ERRE EER SO aD AaSPrESEAZMWO 5 SCouCcocer 56S qq qaqgQqa a 86 F OU SR a adadad d Rev 2 00 Oct15 2006 page 99 of 99 stENESAS REJ09B0338 0200 REVISION HISTORY 38K2 GROUP USER S MANUAL Rev Date Summary 1 0 2 13 03 First Edition 10 15 06 All pages Package names 64P6U A gt PLQP0064GA A revised Package names 64P6Q A gt PLQP0064KB A revised 38K2 group Standard deleted Fig 137 revised CLOCK GENERATING CIRCUIT No external resistor is needed resistor exists on chip No external resistor is needed depending on conditions Fig 141 Pulled up added NOTE added Fig 144 revised NOTES ON USAGE Power Source Voltage USB Communication added Fig 2 1 3 Do not set bits of If writing to these bits write O added 3 2 deleted 3 3 6 3 USB Communication added Fig 3 5 2 Do not set bits of If writing to these bits write O added 3 6 Package outline revised RENESAS 8 BIT SINGLE CHIP MICROCOMPUTER USER S MANUAL 38K2 Group Publication Data Rev 1 00 Feb 13 2003 Rev 2 00 Oct 15 2006 Published by Sales Strategic Planning Div Renesas Technology Corp 2006 Renesas Technology Corp All rights reserved Printed in Japan
34. ta ScLk TxD tv ScLk TxD 2tENESAS APPENDIX 38K2 Group 3 1 Electrical characteristics Timing chart EXB lt CPU channel mode gt lt Read gt ExA0 ExA1 i DQo to DQ7 lt Write gt tsu A W ExA0 ExA1 EE DQo to DQ7 Fig 3 1 5 Timing chart 2 Rev 2 00 Oct 15 2006 page 15 of 99 2tENESAS REJ09B0338 0200 38K2 Group Timing chart EXB lt Memory channel mode Normal port function gt lt Read gt APPENDIX 3 1 Electrical characteristics ExA0O ExA1 tsu S R lt gt 0 2Vcc 0 8Vcc DQo to DQ7 ExINT Mch_req 0 2Vcc lt lt ta R D 7 td R Mdis 0 2Vcc lt Write gt ExA0O ExA1 tsu A W 0 8Vcc 0 2Vcc DQo to DQ7 ExINT Mch_req Fig 3 1 6 Timing chart 3 Rev 2 00 Oct 15 2006 page 16 of 99 REJ09B0338 0200 2tENESAS 38K2 Group Timing chart EXB lt Memory channel mode DMA interface pin function Read and write signals used together mode gt lt Read gt tsu ACK R ExDACK 0 2Vcc APPENDIX 3 1 Electrical characteristics twL R lt 0 8Vcc XE 0 2Vcc DQo to DQ7 ExDREQ Mch_req lt Write gt tsu ACK W he Nt DQo to DQ7
35. 0 DSPTEN1 Downs ream port 1 enable bit Downstream port 1 disabled Downstream port 1 enabled This bit is cleared when an interrupt of PTDIS1 or PTERR1 is generated DSSUSP1 Downs ream port 1 suspend bit No port suspended Port suspended This bit is cleared when an interrupt of PTDIS1 or PTRSM1 is generated DSDETE1 Downs ream port 1 connect state detection enable bit Connect disconnect state detection disabled PTCON1 and PTDIS1 interrupts disabled Connect disconnect state detection enabled This bit is cleared when an interrupt of PTCON1 PTDIS1 or PTERR1 is generated t DSRSTO1 Downs ream port 1 SEO signal transmit bit Being not output SEO signal being output DSRSMO1 Downs signal t ream port 1 resume ransmit bit Being not output K signal being output When writing 0 a low speed EOP is output and then a transition to being not output occurs DSRMOD1 Downs read m ream port 1 bus state ode control bit Mode where a downstream port 1 bus state is read using RD signal Mode where a downstream port 1 bus state is read using EOF2 signal internal signal DSLSPD1 Downs ream port 1 USB transfer Full speed mode 12MHz Low speed mode 1 5 MHz Fig 97 Structure of DP1 control register b7 bo fofofofofolo DP1 status register DP1STS addr
36. 1 Basic functions and uses Function 1 Control of Event interval Timer X Timer 1 Timer 2 When a certain time by setting a count value to each timer has passed the timer interrupt request occurs lt Use gt Generation of an output signal timing Generation of a wait time Function 2 Control of Cyclic operation Timer X Timer 1 Timer 2 The value of the timer latch is automatically written to the corresponding timer each time the timer underflows and each timer interrupt request occurs in cycles lt Use gt Generation of cyclic interrupts Clock function measurement of 10 ms see Application example 1 Control of a main routine cycle Function 3 Output of Rectangular waveform Timer X The output level of the CNTRo pin is inverted each time the timer underflows in the pulse output mode lt Use gt Piezoelectric buzzer output see Application example 2 Generation of the remote control carrier waveforms Function 4 Count of External pulses Timer X External pulses input to the CNTRo pin are counted as the timer count source in the event counter mode lt Use gt Frequency measurement see Application example 3 Division of external pulses Generation of interrupts due to a cycle using external pulses as the count source count of a reel pulse Function 5 Measurement of External pulse width Timer X The H or L level width of external pulses input to CNTRo pin is measured in the pulse width measurem
37. 7 bits ___ 1 Parity enable bit 0 Parity checking disabled PARE 1 Parity checking enabled 2 Parity selection bit 0 Even parity PARS 1 Odd parity 3 Stop bit length selection bit 0 1 stop bit STPS 1 2 stop bits 4 Nothing is allocated for this bit This is a write disabled bit When this bit is read out the contents are 0 Nothing is allocated for these bits These are write disabled bits When these bits are read out the contents are 1 Fig 3 4 88 Structure of UART control register Rev 2 00 Oct 15 2006 page 75 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers Baud rate generator b7 b6 b5 b4 b3 b2 b1 bO Baud rate generator BRG Address OFE216 EP01 MAX packet size register EP01MAX address OFEC16 At reset H W MXPS01 Max packet size bit IN These bits are invalid 0 6 0 OUT Set the maximum packet size b7 Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 3 4 90 Structure of EP01 MAX packet size register EP02 MAX packet size register EPO2MAX address OFEC16 At reset Bit symbol Bi Function y it name HW MXPS02 Max packet size bit IN These bits are invalid 6 0 OUT Set the maximum packet size b7 Not used Write 0 when writing 0 is read when read
38. F USB difference input 0 Upstream port difference input circuit operation disabled enable bit 1 Upstream port difference input circuit operation enabled USB clock select bit External oscillating clock f XIN PLL circuit output clock fvco 7 USB module operation 0 USB module reset enable bit 1 USB module operation enabled Fig 2 11 2 Structure of USB control register Rev 2 00 Oct 15 2006 page 84 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 11 Frequency synthesizer PLL CPU mode register b7 b6 b5 b4 b3 be b1 b0 CPU mode register ohi CPUM address 3B16 B Nawe Function rset RW b1 b0 Processor mode bits 0 0 Single chip mode gt 0 1 Not available 1 0 Not available 1 1 Not available 2 Stack page selection bit 0 0 page 1 1 page 3 Fix this bit to 1 Fix this bit to O i System clock selection bit 0 Main clock f Xin 2 oio 1 fsyn l System clock division ratio selection bits system clock 8 8 divide mode system clock 4 4 divide mode system clock 2 2 divide mode system clock Through mode The initial value of bit 1 depends on the CNVss level Fig 2 11 3 Structure of CPU mode register PLL control register b7 b6 b5 b4 b3 b2 b1 bO PLL control register PLLCON Address OFF816 B Name Function o Nothing is arranged for these bit These are write disabled bits USB clock division so Divided by 8 fs
39. Fig 126 Memory channel receiving operation 3 Rev 2 00 Oct 15 2006 page 86 of 130 2RENESAS REJ09B0338 0200 38K2 Group 6 Memory Channel Transmitting Operation 1 Cycle Mode Memory channel transmitting operation 1 is shown bellow Address ExAO Chip select ExCS DMA acknowledge ExDACK Read ExRD Write ExWR Data DQo to DQ7 Internal clock o DMA request ExDREQ mRD detection mRD 7 detection Transmission completed Transmit buffer TXBUF FUNCTIONAL HARDWARE DESCRIPTION poy Lu LLL LOLPLyLpL Mch_req j Operation enabled Main sequencer Memory channel operation end interrupt Internal memory access Memory address Counter end Acknowledgment of internal memory access Fig 127 Memory chan 1010016 LI LIL Li 1 Jack f a lt Initial setting gt External I O configuration register Memory channel operation mode register Memory address counter End address register lt Operation start command gt EXB interrupt source enable register gl ack Set as necessary MC_DIR 1 0 Memory channel direction control 102 Transmit mode Burst burst 0 Cycle mode Example 010016 Example 010116 1010216 ae i LLL MC_ENB Memory channel operation enable 1 Operation start In the memory channel transmit mode when the command for enabling operation is
40. Interrupt vector area _ Fig 164 ID code storage addresses Rev 2 00 Oct15 2006 page 121 of 130 REJ09B0338 0200 2tENESAS 38K2 Group Status Register SRD The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error It can be read by writing the read status register command 7016 Also the status register is cleared by writing the clear status register command 5016 Table 14 lists the definition of each status register bit After releas ing the reset the status register becomes 8016 Table 14 Status register SRD SRDO bits SR7 bit7 Status name Sequencer status HARDWARE FUNCTIONAL DESCRIPTION Sequencer status SR7 The sequencer status indicates the operating status of the the flash memory After power on and recover from deep power down mode the se quencer status is set to 1 ready This status bit is set to 0 busy during write or erase operation and is set to 1 upon completion of these operations Erase status SR5 The erase status indicates the operating status of erase operation If an erase error occurs it is set to 1 When the erase status is cleared it is set to 0 Program status SR4 The program status indicates the operating status of write opera tion If a write error occurs it is set to 1 When the program status is cleared it is set
41. Note Condition for acceptance of an interrupt gt Interrupt enable flag is 1 Interrupt disable flag is 0 Fig 6 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator Processor status register Rev 2 00 Oct15 2006 page 8 of 130 2RENESAS REJ09B0338 0200 38K2 Group Processor status register PS The processor status register is an 8 bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation Branch opera tions can be performed by testing the Carry C flag Zero Z flag Overflow V flag or the Negative N flag In decimal mode the Z V N flags are not valid Bit 0 Carry flag C The C flag contains a carry or borrow generated by the arithmetic logic unit ALU immediately after an arithmetic operation It can also be changed by a shift or rotate instruction Bit 1 Zero flag Z The Z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 and cleared if the result is anything other than 0 Bit 2 Interrupt disable flag I The flag disables all interrupts except for the interrupt generated by the BRK instruction Interrupts are disabled when the flag is 1 Bit 3 Decimal mode flag D The D flag
42. Note 4 Vcc 3 00 to 4 00 V System clock frequency Vcc 4 00 to 5 25 V Vcc 3 00 to 4 00 V o frequency Vcc 4 00 to 5 25 V Vcc 3 00 to 4 00 V Notes 1 The total peak output current is the absolute value of the peak currents flowing through all the applicable ports The total average output current is the average value of the absolute value of the currents measured over 100 ms flowing through all the applicable ports 2 The peak output current is the absolute value of the peak current flowing in each port 3 The average output current is the average value of the absolute value of the currents measured over 100 ms 4 The duty of oscillation frequency is 50 6 MHz or 12 MHz is usable Rev 2 00 Oct 15 2006 page 4 of 99 2RENESAS REJ09B0338 0200 38K2 Group 3 1 3 Electrical characteristics L Ver APPENDIX 3 1 Electrical characteristics L Ver Table 3 1 4 Electrical characteristics 1 Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter Test conditions Limits Min Typ H output voltage POo P07 P24 P27 P50 P57 P60 P63 IOH 10 mA Vcc 4 00 to 5 25 V Vcec 2 0 lOH 1 mA Vec 1 0 H output voltage P10 P17 P30 P37 P40 P43 IOH 10 mA VccE 4 00 to 5 25 V VccE 2 0 lOH 1 mA VccE 1 0 H output voltage DO DO D1 D1 D2 D2
43. Setting serial I O control register again Serial 1 0 Set the serial I O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to 0 Clear both the transmit enable bit TE and the receive enable bit RE to 0 l Set the bits 0 to 3 and bit 6 of the serial I O control register Can be set with the LDM instruction at the same time Set both the transmit enable bit TE and the receive enable bit RE or one of them to 1 Fig 2 4 35 Sequence of setting serial I O control register again Rev 2 00 Oct 15 2006 page 67 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 5 Data transmission control with referring to transmit shift register completion flag Serial 1 0 The transmit shift register completion flag changes from 1 to 0 with a delay of 0 5 to 1 5 shift clocks When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register note the delay 6 Transmission control when external clock is selected Serial I O When an external clock is used as the synchronous clock for data transmission set the transmit enable bit to 1 at H of the SCLK input level Also write the transmit data to the transmit buffer register serial I O shift register at H of the SCLK input level 7 Transmit interrupt request when trans
44. The CNVss pin is connected to the internal memory circuit block by a low ohmic resistance since it has the multiplexed function to be a programmable power source pin VPP pin as well To improve the noise reduction connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10 kQ resistance The mask ROM version track of CNVss pin has no operational in terference even if it is connected to Vss pin or Vcc pin via a resistor Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs There are differences in electric characteristics operation margin noise immunity and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufac turing processes When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM ver sion please perform sufficient evaluations for the commercial samples of the Mask ROM version DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc tion 1 Mask ROM Order Confirmation Form 2 Mark Specification Form 3 Data to be written to ROM in EPROM form three identical cop ies or one floppy disk For the mask ROM confirmation and the mark specifications re fer to the Renesas Technology Corp Homepage http www renesas com 2tENESAS 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT FUNCTIONAL DESCRIPTION SUPPLEMENT A D
45. 1 when transition to status stage occurs in CTENDE10 0 control transfer completion disabled on USB HUB Endpoint 10 0 can be set by software but 1 cannot be set lt Transition to status stage occurrence factor gt At transfer of control write When receiving IN token in data stage OUT At transfer of control read When receiving OUT token in data stage IN At no data transfer Nothing occurs BSRDY10 USB HUB Endpoint 10 SETUP buffer ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the exclusive buffer for SETUP is ready state enabled to be read on USB HUB Endpoint 10 0 can be set by software but 1 cannot be set USB HUB Endpoint 10 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when control transfer error occurs on USB HUB Endpoint 10 This bit is cleared to 0 by the hardware when receiving SETUP token 0 can be set by software but 1 cannot be set Not used Write 0 when writing 0 is read when reading Fig 78 Structure of EP10 interrupt source register Rev 2 00 Oct15 2006 page 54 of 130 REJ09B0338 0200 2RENESAS State remaining HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION EP10 byte number register EP10BYT address 001E16 At reset H W B
46. 1 siioni in en A EEEE 14 Port DIOCK diagram 2 aerer E A E E avertertaaid 15 Structure of port I O related registers eessseeesseesseeseiesrieesrsssrresrrnssrnnntnnsstnnsnnnsnnnne 16 Interrupt controlicckss ceive aeaa aa ia N aa aana aa Aaa ia aaa Taada 18 Structure of interrupt related registers cccccceceseeeeeneeeceeeeeeeeeeseeeeeesaeeseeeeeesaaeeeenes 18 Connection example when using key input interrupt and port PO block diagram 19 Structure of timer X mode register cccceeeeeeeeeeeee cesses eceeeeeeaaeeseeeeeeeaeeseeeeeetaeeeeeees 20 Timer block diagr AIM oereide eirinen tiani ie EAAS EEA EE AOSE LAEE ERE 21 Block diagram of clock synchronous serial O sssssssssesssssssissssssssissriresrisssrnsssrnssrnnens 22 Operation of clock synchronous serial I O function 0 ccc eecceteeeeeeseteeeeeessaeeeeeeeeaes 22 Block diagram of UART serial I O eccceeccceceseeeeeeeeeeeeaeeeeeeeeeeaaeeeeeeeeescaeeeseneeesiaeeeteneees 23 Operation of UART serial I O fUNCtION 0 cee eceececeeeeeeeneee cere eeeeaeeseeeeeeaaeeseeeeeeseaaeeeaes 23 Structure of serial I O control registers eccececseeeeeeeeeeeeeeeeeseeeeeseaeeeseaeeeeeeeeeneaeeseaees 25 USB FUNCTION OVEFVIEW 0 0 ccecccccceceteceeceesceeeceseaaeeeecesaaaeeeeeseeaeeeecesesaeeeeeeeaaeesenseseeeeessnaaes 26 USB Function Control Circuit USBFCC block diagram cceeseeeeeeeestteeeeenees 27 USB port external circuit D0 DO USBVrer TrON block di
47. 38K2 Group User s Manual 2tENESAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan REJO9B0338 0200
48. 38K2 Group 3 4 List of registers EP03 byte number register 0 EPO3BYTO address 001E16 At reset H W S W BOBYT03 IN Transmit byte number bit Single buffer mode Set the transmitting byte number 0 6 0 Double buffer mode Set the transmitting byte number of buffer 0 OUT Receive byte number bit Single buffer mode The received byte number is automatically set Double buffer mode The received byte number of buffer 0 is automatically set Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function e remaining Fig 3 4 44 Structure of EP03 byte number register 0 EP10 byte number register EP10BYT address 001E16 At reset H W BBYT10 Transmit receive byte number bit OUT The received byte number is automatically set 0 3 0 IN Set the transmitting byte number b7 b4 Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 3 4 45 Structure of EP10 byte number register b7 bo fofofofolofolo EP11 byte number register EP11BYTO address 001E16 Bit symbol Bit name Function At reset H W BOBYT11 Transmit byte number bit IN Set the transmitting byte number 0 b7 b1 Not used Write 0 when writing 0 is read when reading State remaining Fig 3 4 46 Structure of EP11 byt
49. Bit symbol Bit name Function At reset H W S W PIDO2 1 0 Response PID bit b1 bO 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of over max packet size B1 is set to 1 by the hardware 0 Lt Write 0 when writing 0 is read when reading Fig 57 Structure of EP02 control register 1 Rev 2 00 Oct15 2006 page 45 of 130 REJ09B0338 0200 7tENESAS State remaining 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION b7 bO fofofofofofofo EP02 control register 2 EPO2CON2 address 001B16 Bit symbol Bit name Function At reset H W S W BOVAL02 Buffer 0 enable bit When the selected endpoint is IN writing 1 to this bit makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write 0 Write 0 when writing 0 is read when reading Fig 58 Structure of EP02 control register 2 b7 bO ofofofolofo o EP02 control register 3 EP02CON3 address 001C16 State remaining Bit symbol Bit name At reset Function H W S W B1VAL02 Buffer 1 enable bit When the selected endpoint is IN writing 1 to this bit makes the tra
50. CM5 1 PLLCON 4 3 10 CM5 O34 CM6 O34 Note Set PLLCON 4 3 00 before switching the system clock from XIN to fSYN CM5 gre CM6 agre Note Set PLLCON 4 3 01 before switching the system clock from XIN to fSYN Notes 1 without an allow CM6 O 1 CM6 0O 1 _ _ Set PLLCON 4 3 10 before switching the system clock from XIN f SYN through mode f 6 0 MHz CM7 1 CM6 1 CM5 1 PLLCON 4 3 00 f SYN through mode f b 8 0 MHz CM7 1 CM6 1 CM5 1 PLLCON 4 3 01 HARDWARE FUNCTIONAL DESCRIPTION XIN 4 divide mode f o 1 5 MHz CM7 0 CM6 0 CM5 0 PLLCON 4 3 xx arbitrary XIN through mode f o 1 5 MHz CM7 0 CM6 0 CM5 0 PLLCON 4 3 xx arbitrary CM5 0 1 lt lt Note Set PLLCON 4 3 00 before switching the system clock from XIN to fSYN CM5 O e 3 4 Note Set PLLCON 4 3 01 before switching the system clock from XIN to fSYN Switch the mode by the allows shown between the mode blocks Do not switch between the modes directly 2 Set the USB clock fUsB to 48 MHz when switching the system clock to fSYN Do not change a division ratio of USB clock when using fSYN as the system clock See section PLL CIRCUIT in details for enabling disabling PLL operation and usage notes of fSYN Set the system clock to XIN when entering STOP mode In all modes swit
51. Interrupt disabled interrupt enable bit 1 Interrupt enabled 7 Fix this bit to 0 Fig 2 2 5 Structure of Interrupt control register 2 Interrupt edge selection register b7 b6 b5 b4 b3 b2 bi bO Interrupt edge selection register INTEDGE Address OFF316 B Name Function atresa Riw INTo interrupt edge 0 Falling edge active selection bit 1 Rising edge active Nothing is arranged for this bits This is a write disabled bit l When this bit is read out the contents are 0 l 2 INT1 interrupt edge 0 Falling edge active selection bit 1 Rising edge active a I I Nothing is arranged for these bits These are write disabled bits l When these bits are read out the contents are 0 I o fox I Fig 2 2 6 Structure of Interrupt edge selection register Rev 2 00 Oct 15 2006 page 10 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 2 Interrupt 2 2 3 Interrupt source The 38K2 group permits interrupts of 16 sources These are vector interrupts with a fixed priority system Accordingly when two or more interrupt requests occur during the same sampling the higher priority interrupt is accepted first This priority is determined by hardware but a variety of priority processing can be performed by software using an interrupt enable bit and an interrupt disable flag For interrupt sources vector addresses and interrupt priority refer to Table 2 2 1 Table 2 2 1 Interrupt sou
52. Operation disabled Memory channel operation end enable bit interrupt disabled Operation enabled Memory channel operation end interrupt disabled Not used Write 0 when writing 0 is read when reading State remaining Note Do not set each bit simultaneously Fig 3 4 65 Structure of EXB interrupt source enable register Rev 2 00 Oct 15 2006 page 65 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers EXB interrupt source register EXBIREQ address 003116 Note 1 At reset H W S W RXB_FULL Receive buffer full bit 0 Receive buffer empty 0 0 1 Receive buffer full Note 3 TXB_EMPTY Transmit buffer empty bit 0 Transmit buffer full 0 1 Transmit buffer empty Note 4 MC_STS Memory channel status bits b3b2 0 1 0 0 0 Memory channel operation stopped Note 2 0 1 Memory channel being operating No external access Memory channel being operating External accessing Memory channel operation end Memory channel operation end interrupt generated Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Notes 1 When the the ExA1 pin control bit of external I O configuration register is 1 the external MCU bus can read this register contents by setting the ExA1 pin to H
53. S W CTENDE10 Control transfer completion enable bit 0 NAK transmission in the status stage 1 Control transfer completion enabled SIE transmits NULL ACK Valid in PID10 012 At reception of SETUP token This bit is cleared to 0 by the hardware 0 Write 0 when writing 0 is read when reading Fig 3 4 34 Structure of EP10 control register 3 EPOO interrupt source register EPOOREQ address 001D16 State remaining Bit symbol Bit name At reset Function H W S W BRDY00 USB function Endpoint 0 buffer ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer is ready state enabled to be read written on USB function Endpoint 0 0 can be set by software but 1 cannot be set 0 0 CTENDOO USB function Endpoint 0 control transfer completion interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when control transfer is completed NULL ACK transmission in the status stage on USB function Endpoint 0 0 can be set by software but 1 cannot be set CTSTS00 USB function Endpoint 0 status stage transition interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when transition to status stage occurs in CTENDEOQ00
54. VREF PVcc DVcc USBVREF Input voltage POo P07 P10 P17 P24 P27 P30 P37 P40 P43 P50 P57 P60 P63 Input voltage RESET XIN CNVss2 Input voltage CNVss Mask ROM version Flash memory version All voltages are based on VSS Output transistors are cut off 0 3 to 6 5 0 3 to Vcc 0 3 0 3 to Vcc 0 3 0 3 to Vcc 0 3 0 3 to Vcc 0 3 0 3 to 6 5 Input voltage DO DO D1 D1 D2 D2 Output voltage POo P07 P10 P17 P24 P27 P30 P37 P40 P43 P50 P57 P60 P63 XOUT Output voltage DO DO D1 D1 D2 D2 TrON 0 5 to 3 8 0 3 to Vcc 0 3 0 5 to 3 8 Power dissipation Note Ta 25 C 500 Operating temperature MCU operating 20 to 85 In flash memory mode For flash memory ver sion 2545 Storage temperature 40 to 125 Note The maximum rating value depends on not only the MCU s power dissipation but the heat consumption characteristics of the package Rev 2 00 Oct 15 2006 page 2 of 99 7RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 1 Electrical characteristics L Ver 3 1 2 Recommended operating conditions L Ver Table 3 1 2 Recommended operating conditions Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Typ Power source voltage Vcc System clock 12 MHz 5 00 2 4 8 divide mo
55. buffer register to Transmit shift register Transmit buffer empty flag The second byte of e Transmission data write a transmission data Transmit buffer empty flag is set to 0 by this writing TB RB Address 2616 lt e Judgment of transferring data from Transmit buffer register to Transmit shift register Transmit buffer empty flag SIOSTS Address 2716 bit0 SIOSTS Address 2716 bit2 e Judgment of shift completion of Transmit shift register Transmit shift register shift completion flag P2 Address 0416 bit4 lt 0 Communication completion Fig 2 4 33 Control procedure of transmitting side Rev 2 00 Oct 15 2006 page 64 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O x This bit is not used here Set it to O or 1 arbitrarily Initialization SIOCON Address OFE016 lt 1010x0002 UARTCON Address OFE116 lt 000010002 Address OFE216 lt 39 1 Address 0516 lt XXX0XXXX2 SIOSTS Address 2716 bit1 a e Judgment of completion of receiving Receive buffer full flag 1 e Reception of the first byte data Receive buffer full flag is set to 0 by reading data Read out a reception data from RB Address 2616 e Judgment of an error flag SIOSTS Address 2716 bit6 SIOSTS Address 2716 bit1 J dgment of completion of receiving 4 Receive buffer full flag e Reception of the second
56. instruction set Machine resident 740 family instructions are as follows The FST and SLW instruction cannot be used The STP WIT MUL and DIV instruction can be used The CPU has the 6 registers The register structure is shown in Figure 5 Accumulator A The accumulator is an 8 bit register Data operations such as data transfer etc are executed mainly through the accumulator Index Register X X The index register X is an 8 bit register In the index addressing modes the value of the OPERAND is added to the contents of register X and specifies the real address Index Register Y Y The index register Y is an 8 bit register In partial instruction the value of the OPERAND is added to the contents of register Y and specifies the real address b7 Fig 5 740 Family CPU register structure Rev 2 00 Oct15 2006 page 7 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Stack Pointer S The stack pointer is an 8 bit register used during subroutine calls and interrupts This register indicates start address of stored area stack for storing registers during subroutine calls and interrupts The low order 8 bits of the stack address are determined by the contents of the stack pointer The high order 8 bits of the stack address are determined by the stack page selection bit If the stack page selection bit is O the high order 8 bits becomes 0016 If the stack page selection bit is 1
57. is read when reading e remaining Fig 72 Structure of EP03 MAX packet size register Rev 2 00 Oct15 2006 page 51 of 130 7tENESAS REJ09B0338 0200 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION EP03 buffer area set register EPO3BUF address OFED16 Bit symbol Bit name Function At reset H W S W 4 0 BADDO3 EP03 beginning address set bit Set the beginning address of EP03 s buffer area 32 byte unit b4b3b2b1b0 000 1 0 004016 006016 0 03C016 03E016 0 Write 0 when writing 0 is read when reading Fig 73 Structure of EP03 buffer area set register Rev 2 00 Oct15 2006 page 52 of 130 REJ09B0338 0200 7RENESAS e remaining 38K2 Group 5 Endpoint 10 HARDWARE FUNCTIONAL DESCRIPTION b7 bO fofofofofofolo EP10 stage register EP10STG address 001916 Bit symbol Bit name Function At reset H W S W SETUP10 SETUP packet detection bit This bit is set to 1 at reception of SETUP packet Writing 0 clears this bit if the next SETUP token does not occur Writing 1 causes no state change of the status flags This bit change is not for an interrupt source 1 1 Not used Write 0 when writing 0 is read when reading Fig 74 Structure of EP10 stage register b7 bO
58. it is essential to initialize the index X mode T and the decimal mode D flags because of their effect on calculations Interrupts The contents of the interrupt request bits do not change immedi ately after they have been written After writing to an interrupt request register execute at least one instruction before perform ing a BBC or BBS instruction Decimal Calculations To calculate in decimal notation set the decimal mode flag D to 1 then execute an ADC or SBC instruction After executing an ADC or SBC instruction execute at least one instruction be fore executing a SEC CLC or CLD instruction In decimal mode the values of the negative N overflow V and zero Z flags are invalid Timers e When n 0 to 255 is written to a timer latch the frequency divi sion ratio is 1 n 1 When a count source of timer X is switched stop a count of timer X Multiplication and Division Instructions The index X mode T and the decimal mode D flags do not af fect the MUL and DIV instruction The execution of these instructions does not change the con tents of the processor status register Ports The contents of the port direction registers cannot be read The following cannot be used The data transfer instruction LDA etc The operation instruction when the index X mode flag T is 1 The addressing mode which uses the value of a direction regis ter as an index The bit test
59. product is shipped from Renesas Technology Corp Accordingly make note of the fact that the standard serial I O mode cannot be used if the Boot ROM area is rewritten in parallel I O mode Figure 154 shows the pin connections for the standard serial I O mode In standard serial I O mode serial data I O uses the four serial I O pins SCLK RxD TxD and SRDY BUSY The SCLK pin is the trans fer clock input pin through which an external transfer clock is input The TxD pin is for CMOS output The SRDY BUSY pin out puts L level when ready for reception and H level when reception starts Serial data I O is transferred serially in 8 bit units In standard serial I O mode only the User ROM area shown in Figure 146 can be rewritten The Boot ROM area cannot In standard serial I O mode a 7 byte ID code is used When there is data in the flash memory commands sent from the peripheral unit programmer are not accepted unless the ID code matches Rev 2 00 Oct15 2006 page 112 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Outline Performance Standard Serial I O Mode In standard serial I O mode software commands addresses and data are input and output between the MCU and peripheral units serial programer etc using 4 wire clock synchronized serial I O In reception software commands addresses and program data are synchronized with the rise of the transfer clock that is input to the SCLK pin and are then i
60. s bits at least is set to 1 This bit is cleared to 0 by clearing EP10 interrup source register to 0016 Writing to this bit causes no state change USB HUB Endpoint 1 interrupt bit This bit is set to 1 when any one of EP11 interrup source register s bits at least is set to 1 This bit is cleared to 0 by clearing EP11 interrup source register to 0016 Writing to this bit causes no state change Suspend interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting 3 ms or more of J state using USB clock fuss at 48 MHz 0 can be set by software but 1 cannot be set Resume interrupt bit This bit is set to 1 when the USB bus state changes from J state to K state or SEO in the resume interrupt enable bit 1 It is also 1 in the condition of internal clock stopped This bit is cleared to 0 by clearing the resume interrupt enable bit Writing to this bit causes no state change Fig 38 Structure of USB interrupt source register Rev 2 00 Oct15 2006 page 36 of 130 REJ09B0338 0200 2RENESAS 38K2 Group b7 bO fofofofofol Endpoint index register USBINDEX address 001816 HARDWARE FUNCTIONAL DESCRIPTION Bit symbol Bit name Function At reset H W S W EPIDX 1 0 Endpoint index bit
61. stops at the H level The CPU stops but most of the peripheral units continue operating 1 State in wait mode The continuation of oscillation permits clock supply to the peripheral units Table 2 13 2 shows the state in the wait mode Table 2 13 2 State in wait mode Item State in wait mode Operating Stopped Stopped at H level Retains the state at the WIT instruction execution Oscillation CPU Internal clock I O ports PO P6 Timer Operating Watchdog timer Operating Serial I O Operating USB function Operating HUB function Operating External BUS interface Stopped A D converter Operating Comparator Operating Rev 2 00 Oct15 2006 page 100 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 13 Standby function 2 Release of wait mode The wait mode is released by reset input or by the occurrence of an interrupt request Note the differences in the restoration process according to reset input or interrupt request as described below In the wait mode oscillation is continued so an instruction can be executed immediately after the wait mode is released Restoration by reset input The wait mode is released by holding the input level of the RESET pin at L in the wait mode Upon release of the wait mode all ports are in the input state and supply of the internal clock to the CPU is started To reset the microcomputer the RESET pin should
62. 0 Serial I O and transmit disabled Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I O enable bit is cleared to 0 Serial I O disabled the internal transmission is running in this case since pins TxD RxD SCLK and SRDY function as I O ports the transmission data is not output When data is written to the transmit buffer register in this state data starts to be shifted to the transmit shift register When the serial I O enable bit is set to 1 at this time the data during internally shifting is output to the TxD pin and an operation failure occurs Stop of receive operation Clear the receive enable bit to O receive disabled or clear the serial I O enable bit to O Serial I O disabled Stop of transmit receive operation Clear the transmit enable bit and receive enable bit to 0 simultaneously transmit and receive disabled when data is transmitted and received in the clock synchronous serial I O mode any one of data transmission and reception cannot be stopped Reason In the clock synchronous serial I O mode the same clock is used for transmission and reception If any one of transmission and reception is disabled a bit error occurs because transmission and reception cannot be synchronized In this mode the clock circuit of the transmission circuit also operates for data reception Accordingly the transmission circui
63. 0 bit In double buffer mode set the beginning address of buffer 1 area using a relative value for the beginning address of buffer 0 b1b0 00 8bytes 01 16 bytes 10 64 bytes 1 1 128 bytes 0 DBLB03 Buffer mode select bit Single buffer mode SQCL03 Sequence toggle bit clear bit Toggle bit clear disabled Writing 1 clears the toggle bit and DATAO is used as the next data PID 0 is always read when reading 0 1 Double buffer mode 0 13 ITMD03 Interrupt toggle mode select bit Normal mode Continuous toggle mode valid at Interrupt IN transfer DIRO3 Transfer direction bit OUT Data is received from the host 1 IN Data is transmitted to the host TYP03 Transfer type bit 1 0 b7b6 0 0 Transfer disabled 0 1 Bulk transfer 1 0 Interrupt transfer 1 1 lsochronous transfer Fig 65 Structure of EP03 set register b7 bo fofofofofofo EPO3 control register 1 EPO3CON1 address 001A16 State remaining Bit symbol Bit name Function At reset H W S W PIDO3 Response PID bit 1 0 b1 bO 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of over max packet size B1 is set to 1 by the hardware 0 Write 0 when writing 0 is read when reading Fig 66 Structure of E
64. 00 Oct 15 2006 page 83 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 5 Package outline PLQPO064KB A JEITA Package Code RENESAS Code Previous Code MASS Typ P LQFP64 10x10 0 50 PLQPO064KB A 64P6Q A FP 64K FP 64KV 0 3g Hp NOTE 14 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET 32 by He Reference Dimension in Millimeters Symbol Min Nom Max D 9 9 10 0 10 1 u E 9 9 10 0 10 1 Terminal cross section A2 14 Hp 11 8 12 0 12 2 He 11 8 12 0 12 2 Index mark A N eA _ Ai 0 05 0 1 0 15 bp 0 15 0 20 0 25 br 0 18 sH EE th lt 2 o 0 09 0 145 0 20 d lt gt e o 8 Ay 3 Lh e 05 s gt fox M x 0 08 y 0 08 Detail F Zp 1 25 Ze 1 25 L 0 35 0 5 0 65 Li 1 0 Rev 2 00 Oct 15 2006 page 84 of 99 2RENESAS REJ09B0338 0200 THIS PAGE IS BLANK FOR REASONS OF LAYOUT APPENDIX APPENDIX 38K2 Group 3 6 Machine instructions 38K2
65. 0200 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION ID Code Check Function Use this function in standard serial I O mode When the contents of the flash memory are not blank the ID code sent from the pro grammer is compared with the ID code written in the flash memory to see if they match If the ID codes do not match the commands sent from the programmer are not accepted The ID code consists of 8 bit data and its areas are FFD416 to FFDA16 Write a pro gram which has had the ID code preset at these addresses to the flash memory Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 ID7 FFDB16 ROM cord protect control Interrupt vector area Fig 153 ID code store addresses Rev 2 00 Oct 15 2006 page 110 of 130 7RENESAS REJ09B0338 0200 38K2 Group 2 Parallel I O Mode Parallel I O mode is the mode which parallel output and input soft ware command address and data required for the operations read program erase etc to a built in flash memory Use the ex clusive external equipment flash programmer which supports the 38K2 Group flash memory version Refer to each programmer maker s handling manual for the details of the usage User ROM and Boot ROM Areas In parallel I O mode the user ROM and boot ROM areas shown in Fig ure 146 can be rewritten Both areas of flash memory can be operated on in the same way The boot ROM area is 4 Kbytes in size It is located at addresses F00016 t
66. 1 Low current mode valid in VREFE 1 USB reference voltage circuit operation disabled USB reference voltage circuit operation enabled Upstream port difference input circuit operation disabled Upstream port difference input circuit operation enabled External oscillating clock f XIN PLL circuit output clock fvco USB module reset USB module operation enabled Bit symbol Bit name Function TRONCON TrON output control bit TRONE TrON output enable bit VREFCON USB reference voltage control bit VREFE USB reference voltage enable bit USBDIFE USB difference input enable bit UCLKCON USB clock select bit USBE USB module operation enable bit of of o of of of ofa State remaining Fig 3 4 3 Structure of USB control register b7 bO fofofofofofo USB function HUB enable register USBAE address 001 116 Bit symbol Bit name Function At reset H W ADOE USB function enable bit 0 USB function address register invalidated 0 1 USB function address register validated AD1E USB HUB enable bit 0 USB HUB address register invalidated 1 USB HUB address register validated b7 b2 Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 4 Structure of USB function HUB enable register
67. 2 The memory channel status bits indicate the status of memory channel In MC_ENB 0 these bits are always 002 When the memory channel operation ends these bits are set to 112 and the memory channel operation end interrupt is generated These bits can be read out during operation so that it will show that whether the external MCU bus is accessing or not 3 This bit is cleared to O when reading the transmit receive buffer register in the CPU channel receive enable bit 1 or when the CPU channel receive enable bit is 0 4 This bit is cleared to 0 when writing to the transmit receive buffer register in the CPU channel transmit enable bit 1 or when the CPU channel transmit enable bit is 0 Fig 3 4 66 Structure of EXB interrupt source register b7 bo fofofofofo EXB index register EXBINDEX address 003316 P At reset B I i ii it symbo Bit name Function aw Siw INDEX Index bits The accessible register using the register window 0 2 0 depends on these index bits contents as follows b2b1b0 0 0 External I O configuration register Transmit Receive buffer register Memory channel operation mode register Memory address counter End address register Do not set Do not set 1 1 Do not set Not used Write 0 when writing 0 is read when reading k k iM O OO OOO State remaining
68. 2006 page 13 of 14 7tENESAS REJ09B0338 0200 List of tables 38K2 Group Table 3 1 6 A D Converter characteristics Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted ccceceeesceeceeeeeeceeeeeseeeeeeeeseeeceseeeseeaeeseenseneeeeeeseeseeeeennenaees 7 Table 3 1 7 Timing requirements 1 Vcc 4 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless OUNSHWIS MOLEC ei studecscestsestcnctnegdecace ss teaveesaahaseopecseuuaueeccesanueiecashuneeecesnuainy 8 Table 3 1 8 Timing requirements 2 Vcc 3 00 to 4 00 V Vss 0 V Ta 20 to 85 C unless OINEMWISE noted csc ceed teccenes casas cesaaetpeedeen cua sevesuaddgeanstualpeadanscavessatbalicensautesanaeetanneneess 8 Table 3 1 9 Timing requirements of external bus interface EXB 1 Vcc 4 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted cceceeeeseeeeeeeeeeeseeeeeees 9 Table 3 1 10 Timing requirements of external bus interface EXB 2 Vcc 3 00 to 4 00 V Vss 0 V Ta 20 to 85 C unless otherwise noted cceeeeeeeeeeeeeeeeeeneeee 10 Table 3 1 11 Switching characteristics 1 Vcc 4 00 to 5 25 V Vss 0 V Ta 20 to 85 unless otherwise noted orenera A E EEE 11 Table 3 1 12 Switching characteristics 2 Vcc 3 00 to 4 00 V Vss 0 V Ta 20 to 85 C Unless Otherwise noted ccecececceceeeseeeeeeeeeeeeeeeeeeseeeeeeeeseneeeeeesseneeeeeseeeeeeeseennes 11 Table 3 1 13 Sw
69. 3 2 Notes on use 3 2 1 Notes on input and output ports 1 Modifying output data with bit managing instruction When the port latch of an I O port is modified with the bit managing instruction the value of the unspecified bit may be changed Reason The bit managing instructions are read modify write form instructions for reading and writing data by a byte unit Accordingly when these instructions are executed on a bit of the port latch of an I O port the following is executed to all bits of the port latch As for bit which is set for input port The pin state is read in the CPU and is written to this bit after bit managing As for bit which is set for output port The bit value is read in the CPU and is written to this bit after bit managing Note the following Even when a port which is set as an output port is changed for an input port its port latch holds the output data As for a bit of which is set for an input port its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents 1 Bit managing instructions SEB and CLB instructions Rev 2 00 Oct 15 2006 page 20 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 3 2 2 Termination of unused pins 1 Terminate unused pins I O ports e Set the I O ports for the input mode and connect them to Vcc or Vss through each resistor of 1 kQ to 10 kQ Set the I O
70. AD1 Address 3716 W The read only register in which the A D conversion s results are 2 fox kaci EE 8 bit read gt KAHR ESERIES fof Be lt 10 bit read gt bo age oro Joos oa o oo FPE Ae kA Fig 3 4 79 Structure of AD conversion register 1 AD conversion register 2 b7 b6 b5 b4 b3 b2 bi bO o aan AD conversion register 2 AD2 Address 38 16 O a a re ee The read only register in which the A D conversion s results are lt 10 bit read gt b7 bO o N Nothing is allocated for these bits These are write disabled bits When these bits are read out the contents are 0 Fig 3 4 80 Structure of AD conversion register 2 Rev 2 00 Oct15 2006 page 71 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 bO Watchdog timer control register WDTCON Address 3916 el en STP instruction disable bit 0 STP instruction enabled 1 STP instruction disabled 7 Watchdog timer H count 0 Watchdog timer L underflow source selection bit 1 System clock 16 Fig 3 4 81 Structure of Watchdog timer control register CPU mode register b7 b6 b5 b4 b3 b2 bi b0 CPU mode register BEH CPUM address 3B16 l l B Name Function At reset RW i b1 b0 2 Processor mode bits 0 0 Single chip mode 0 1 Not available Not available Not available Stack page sele
71. APPLICATION 38K2 Group 2 11 Frequency synthesizer PLL Procedure for stop and return of PLL circuit when stop mode Figure 2 11 7 shows the stop procedure of PLL circuit and figure 2 11 8 shows the return procedure of PLL circuit PLL circuit operation enabled Supply PLL circuit output clock fvco as USB clock A X This bit is not used here Set it to O or 1 arbitrarily CPUM address 3B16 lt 11001X002 Select main clock f Xin as a system clock USBCON address 1016 X1XXXXXX2 Select PLL circuit output clock fvco as a USB clock and does not change this setting Disable PLL operation bit7 PLLCON address OFF816 lt OXXXX0002 fvco is fixed to L STP instruction stop mode Stop mode ws ws Note The above setting example assumes the operation when the external oscillating clock is 6 MHz and the internal system clock is fsyn Fig 2 11 7 Related registers setting when stop mode Rev 2 00 Oct 15 2006 page 88 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 11 Frequency synthesizer PLL After recovery from stop mode X This bit is not used here Set it to 0 or 1 arbitrarily PLL operation mode bit6 5 Not multiplied PLLCON OFF bit6 5 00 nee Se a eae sate Change PLL circuit output clock fvco to f XIN USBCON address 1016 lt XOXXXXXX2 Select main clock f X n as a USB clock PLL operation mode bit6 5 Multiplied by 8
72. ATOA OA 95 2 13 39 SLOP MOAS aieoroisaii auai u e ne aE aE aia Aa Aa a a veers 96 213A Will MOOG aa a E aceadbadcfeeatda nae eneedancesdeeliateces 100 2 13 5 Notes On Stand by FUNCTION 0 ccc eee eeeeee eee eeeeeae eee eeeaaaeeeeeeeaaeeeeeeeaaaeeeeeseaaeeeeeneeaas 102 2 14 Flash MOMOLY csin Ea 103 2 VAT OVENI EW aini anaa a Ea EE E A EA E ES 103 214 2 Memory Map acriniria rr E E E EAEE RRA 103 2 143 Related registers cavasan a A E Ai 104 2 144 Parallel VO MOJE rrena a a aa aE 105 2 14 5 Standard serial 1 O MOdC cceeccceceeeeeeeeeeeeeeeeeeeeaaeeeeeeeeceaaesesaeeeseeaeeseaaeeseeaeeseaaeeee 105 2 14 6 CPU rewrite mode oun ceeccecceeeceeenee cence eeeeeeeeeeeeeeseaaeeeaeeeesaaeesdaeeeeeaaeesseneessaeeeseaeeeeaas 106 Rev 2 00 Oct 15 2006 page 2 of 14 RENESAS REJ09B0338 0200 Table of contents 38K2 Group 2 14 7 Flash memory mode application examples ccececececeeeeeeeeeeeeeeeeeeeeeseeeeeeeaeeeeaes 107 2 14 8 Notes on CPU rewrite mode cccceeccceenee cence ee eeaeeeeeeeeceaaeeeeaeeeeeaaeeeeaaeeseeaeeeeiaaeeee 112 CHAPTER 3 APPENDIX 3 1 Electrical characteristics ccccccsseececeeeeeeeeeeeseeeeeeeeeneenseeeeseeeeeeeeeseeeseeeesneeeeeeeseeeeeeensneeeeeennees 2 3 1 1 Absolute maximum ratings 00 0 eeeeee eee eeeeeeeeeeeeeeeeeeeeeaeeeeeeseeeeeeeeeeeeeeeeseeeeeeeeeeeeeaeess 2 3 1 2 Recommended operating conditions L Ver cece eeeeeeeeeeeeeecaeeeeeeeeaeeeeeeeeaeeeeeee 3 3 1 3 Electrical characteristics L
73. BSRDY00 USB function Endpoint 0 SETUP buffer ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the exclusive buffer for SETUP is ready state enabled to be read on USB function Endpoint 0 0 can be set by software but 1 cannot be set USB function Endpoint 0 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when control transfer error occurs on USB function Endpoint 0 This bit is cleared to 0 by the hardware when receiving SETUP token 0 can be set by software but 1 cannot be set Not used Write 0 when writing 0 is read when reading Fig 44 Structure of EPOO interrupt source register Rev 2 00 Oct15 2006 page 39 of 130 REJ09B0338 0200 2RENESAS State remaining 38K2 Group EPOO byte number register EPOOBYT address 001E16 HARDWARE FUNCTIONAL DESCRIPTION Bit symbol Bit name Function At reset H W BBYTOO 3 0 Transmit receive byte number bit OUT The received byte number is automatically set 0 IN Set the transmitting byte number b7 b4 Not used Write 0 when writing 0 is read when reading Fig 45 Structure of EP00 byte number register EPOO buffer area set register EPOOBUF address OFED16 Sta
74. Converter A D conversion is started by setting AD conversion completion bit to 0 During A D conversion internal operations are performed as fol lows 1 After the start of A D conversion AD conversion register goes to 0016 2 The highest order bit of AD conversion register is set to 1 and the comparison voltage Vref is input to the comparator Then Vref is compared with analog input voltage VIN 3 As a result of comparison when Vref lt VIN the highest order bit of AD conversion register becomes 1 When Vref gt VIN the highest order bit becomes 0 Table 16 Relative formula for a reference voltage VREF of A D converter and Vref When n 0 Vref 0 VREF 1024 n Value of A D converter decimal numeral When n 1 to 1023 Vref xn Table 17 Change of AD conversion register during A D conversion By repeating the above operations up to the lowest order bit of the AD conversion register an analog value converts into a digital value A D conversion completes at 122 clock cycles 15 25 us at system clock 8 MHz Through mode after it is started and the result of the conversion is stored into the AD conversion register Concurrently with the completion of A D conversion A D conversion interrupt request occurs so that the AD conversion interrupt request bit is set to 1
75. Corp Homepage USB Device http www renesas com en usb Please refer to them for explanation and application of HUB function Rev 2 00 Oct 15 2006 page 70 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 7 External bus interface EXB 2 7 External bus interface EXB Some application notes are available on the Web site Renesas Technology Corp Homepage USB Device http www renesas com en usb Please refer to them for explanation and application of external bus interface Rev 2 00 Oct 15 2006 page 71 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 8 A D converter 2 8 A D converter This paragraph explains the registers setting method and the notes related to the A D converter 2 8 1 Memory map 003616 AD control register ADCON 003716 AD conversion register 1 AD1 003816 AD conversion register 2 AD2 003D16 Interrupt request register 2 IREQ2 Interrupt control register 2 ICON2 Fig 2 8 1 Memory map of registers related to A D converter 2 8 2 Related registers AD control register b7 b6 b5 b4 b3 b2 bi bO AD control register ADCON Address 3616 B Name Function atreser RW Analog in in selection bits 5261 bO aa eee P1o DQo ANo P11 DQ1 AN1 P12 DQ2 ANe2 P13 DQ3 AN3 P14 DQ4 AN4 P15 DQs ANs P16 DQ6 ANe H P17 DQ7 AN7 3 AD conversion completion bit 0 Conversion in progress 1 1 Conversion completed g IER Fae Fae
76. E E 11 MO O a E E dee deoeie dee biadeeaneh eae 13 O a E T S 17 TIMOL oriei a E EENE E E OEE EEEE NEE 20 Se al lnterfa e 2 sayse sd 2 ceseked ta peck sada inaari aia aaa aiaei adaa aeiiae 22 USB FUNGUON tn aciie ead aaa A A EAE A E ANENE aA 26 HUB FUN CUO Miiceciissccetevtiestetess eencelebbsensdeg gerbes tdee r EE aa EEL EEES 58 External Bus Interface EXB cccccccceeeeeseeececeeeeeaee sees eeeeaae scenes caaaeeeceeeeseaeeseeeeesecaeeeeeeeeee 70 Multichannel RAM isorotan aaa AR E T ageless 89 AID CONVOMMOR aerianas i e a a aa ea aa need Ai da 91 Watchdog TIMOL eiia rer tre epee terete re errr reer tereteecrerrreer tr ner rrr rrr erreee rrrere 93 Reset CinCult nich serait an iden este ele aie eee see ee ee 94 PLL Circuit Frequency Synthesizer cccccececeeeeeeeeeeeeeeeeeeeeeeeeeecaeeeeeeeeseeaeeeeeeeeseeaeeeeeeeeee 95 Clock Generating Circuit prasica asiaa naa aaa aa Eiaa Aaa aa Eaa 97 Flash Memory Mde cocirar a TE RE EE EE A 100 NOTES ON PROGRAMMING sssssssnneennenennenunneunnnnunnnnunnununnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nunne nunnu annan anneanne 126 NOTES ON USAGE Sisia aae a ee sanaa aaa adap ae wast eect te Ea aaa a aaae aa anara oa EEEa ES 128 DATA REQUIRED FOR MASK ORDERS sssnnssenssennnnunnuunrununnunnnnunnnnnnnnnnnnnnnnnnnn nunne nanne nananana 128 FUNCTIONAL DESCRIPTION SUPPLEMENT ccccesecceseeeeeeeeeeeseeeeeseeeesseaeenseeeeneseeseneeneeeeas 129 CHAPTER 2 APPLICATION PAIE UO OU EEEE EEE TE EE EEA
77. EPXXREGS 001E16 Endpoint field register 6 EPXXREG6 001F16 Endpoint field register 7 EPXXREG7 OFE016 Serial I O control register SIOCON OFE116 UART control register UARTCON OFE216 Baud rate generator BRG OFESi6 Reserved Note OFE416 Reserved Note OFE616 Reserved Note OFE716 Reserved Note OFE816 Reserved Note OFE916 Reserved Note OFEAts Reserved Note OFEBis Reserved Note OFED16 Endpoint field register 9 EPXXREG9 OFEE16 Reserved Note OFEF is HARDWARE FUNCTIONAL DESCRIPTION 002016 Prescaler12 PRE12 002116 Timer 1 Tt i y 002216 Timer2 T2 002316 Timer X mode register TM 002416 Prescaler X PREX 002516 Timer X TX 002616 Transmit Receive buffer register TB RB 002A16 HUB down stream port index register HUBINDEX 002B16 HUB port field register 1 DPXREG1 002C16 HUB port field register 2 DPXREG2 002D16 HUB port field register 3 DPXREG3 002E16 _Reserved Note 002F16 _ Reserved Note 003016 EXB interrupt source enable register EXBICON i 0031 16 EXB interrupt source register EXBIREQ 003316 EXB index register EXBINDEX 003416 Register window 1 EXBREG1 003516 Register window 2 EXBREG2 003716 _ AD conversion register 1 AD1 003816 AD conversion register 2 AD2 003A16 _Reserved Note 003B1e CPU mode register CPUM 003C16 Interrupt request r
78. End Erase program Note When one of SR5 to SR4 is set to 1 none of the program erase all blocks and block erase commands is accepted Execute the clear status register command 5016 before executing these commands Fig 165 Full status check flowchart and remedial procedure for errors Rev 2 00 Oct 15 2006 page 124 of 130 7RENESAS REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION Example Circuit Application for Standard Serial O Mode Figure 166 shows a circuit application for the standard serial I O mode Control pins will vary according to a programmer therefore see a programmer manual for more information Clock input SCLK BUSY output SRDY BUSY Data input RxD PD M838K29F8L VPP power source input Notes 1 Control pins and external circuitry will vary according to a programmer For more information see the programmer manual 2 In this example the VPP power supply is supplied from an external source programmer To use the user s power source connect to 4 5 V to 5 25 V Fig 166 Example circuit application for standard serial I O mode Rev 2 00 Oct 15 2006 page 125 of 130 RENESAS REJ09B0338 0200 38K2 Group NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register PS after a reset are undefined except for the interrupt disable flag 1 which is 1 Af ter a reset initialize flags which affect program execution In particular
79. Falling edge count CNTRo interrupt request occurrence Rising edge Pulse width measurement mode 0 Timer X H level width measurement CNTRo interrupt request occurrence Falling edge 4 Rev 2 00 Oct15 2006 page 25 of 112 REJ09B0338 0200 Timer X L level width measurement CNTRo interrupt request occurrence Rising edge RENESAS APPLICATION 38K2 Group 2 3 Timer Interrupt request register 1 b7 b6 b5 b4 b3 b2 bi bO Interrupt request register 1 IREQ1 Address 3C16 B Nare Funcion USB bus reset 0 No interrupt request issued Ta j interrupt request bit 1 Interrupt request issued Of E USB SOF interrupt 0 No interrupt request issued Ol Pa request bit 1 Interrupt request issued I 2 USB device interrupt 0 No interrupt request issued w request bit 1 Interrupt request issued O 3 EXB interrupt o No interrupt request issued o n request bit Interrupt request issued INTo interrupt No interrupt request issued request bit Interrupt request issued Ole Timer X interrupt 0 No interrupt request issued Ol request bit 1 Interrupt request issued I Timer 1 interrupt 0 No interrupt request issued l request bit 1 Interrupt request issued Ol 7 Timer 2 interrupt 0 No interrupt request issued o request bit 1 Interrupt request issued Ta 0 can be set by software but 1 cannot be set Fig 2 3 6 Structure of Interrupt request register 1 Interrupt req
80. Fig 3 4 67 Structure of EXB index register Rev 2 00 Oct15 2006 page 66 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers Register window 1 EXBREG1 address 003416 At reset H W_ S W LOW_WIN The accessible register using this register window In In 7 0 depends on the EXB index register contents as definite definite follows Index value 0016 External I O configuration register 0116 Transmit Receive buffer register 0216 Memory channel operation mode register 0316 Memory address counter 0416 End address register Bit symbol Bit name Function Fig 3 4 68 Structure of Register window 1 Index 0016 External I O configuration register EXBCFGL address 003416 At reset H W S W EXB_CTR_ EXB pin control bit 0 Port 0 Pins P10 to P17 P30 to P34 1 EXB function pin INT_CTR P33 ExINT pin control bit Selects a signal of P33 ExINT pin 2 0 ON OFF is programmed by each bit An output logical sum of P33 ExINT pins set for ON are performed and it is output as an L active signal b3b2b1 0 0 1 RxB_RDY RxBuf ready output 0 1 0 TxB_RDY TxBuf ready output 1 0 0 Mch_req Memory channel request output Others Do not set P43 ExA1 pin control bit 0 Port 1 A1 input used to read status Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Functio
81. Fix Fix this bitto O bit to 0 Fig 2 8 6 Structure of Interrupt control register 2 Rev 2 00 Oct15 2006 page 74 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 8 A D converter 2 8 3 A D converter application examples 1 Conversion of analog input voltage Outline The analog input voltage input from a sensor is converted to digital values Figure 2 8 7 shows a connection diagram and Figure 2 8 8 shows the related registers setting 38K2 Group Fig 2 8 7 Connection diagram Specifications The analog input voltage input from a sensor is converted to digital values P10 DQo ANo pin is used as an analog input pin AD control register address 3616 b7 UY Analog input pin P10 DQo ANo selected A D conversion start AD conversion register 2 address 3816 b7 bO OPI 0e AD conversion register 1 address 3716 b7 bO Read only RR ee A result of A D conversion is stored Note Note After bit 3 of ADCON is set to 1 read out that contents When reading 10 bit data read address 003816 before address 003716 when reading 8 bit data read address 003716 only When reading 10 bit data bits 2 to 6 of address 003816 are O Fig 2 8 8 Related registers setting Rev 2 00 Oct 15 2006 page 75 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 8 A D converter An analog input signal from a sensor is converted to the digital value accordi
82. Group 3 6 Machine instructions 3 6 Machine instructions Addressing mode Addressing mode Processor status register Function Details A BIT A R ZP BIT ZP R ABS ABS X ABS Y IND ZP IND IND X IND Y REL 4 3 n JOP n JOP OP n JOP n JOP n JOP OP n JOP n JOP OP OP B D When T 0 When T 0 this instruction adds the contents 2 6D 4 3 7D 5 3 79 3 61 2 71 2 AsA M C M C and A and stores the results in A and C When T 1 this instruction adds the contents When T 1 of M X M and C and stores the results in M X M X M C M X and C When T 1 the contents of A re main unchanged but the contents of status flags are changed M X represents the contents of memory where is indicated by X When T 0 When T 0 this instruction transfers the con A lt AAM tents of A and M to the ALU which performs a bit wise AND operation and stores the result When T 1 back in A M X M X AM When T 1 this instruction transfers the con tents M X and M to the ALU which performs a bit wise AND operation and stores the results back in M X When T 1 the contents of A re main unchanged but status flags are changed M X represents the contents of memory where is indicated by X This instruction shifts the content of A or M by one bit to the left with bit 0 always being set to 0 and bit 7 of A or M always being contained in C
83. HUB Not used Write 0 when writing 0 is read when reading Fig 3 4 11 Structure of Endpoint index register Rev 2 00 Oct15 2006 page 42 of 99 REJ09B0338 0200 RENESAS State remaining APPENDIX 38K2 Group 3 4 List of registers b7 bo fofofofofofofo EPOO stage register EPOOSTG address 001916 At reset H W S W SETUPOO SETUP packet detection bit This bit is set to 1 at reception of SETUP packet 1 1 Writing 0 to this bit clears this bit if the next SETUP token does not occur Writing 1 to this bit causes no state change of the status flags Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 3 4 12 Structure of EP0OO stage register EP01 set register EP01CFG address 001916 At reset H W S W BSIZ01 Double buffer beginning address set In double buffer mode set the beginning address of 0 1 0 bit buffer 1 area using a relative value for the beginning address of buffer 0 b1b0 0 0 8bytes 01 16 bytes 1 0 64 bytes 1 1 128 bytes DBLB01 Buffer mode select bit 0 Single buffer mode 1 Double buffer mode SQCLO01 Sequence toggle bit clear bit 0 Toggle bit clear disabled 1 Writing 1 clears the toggle bit and DATAO is used as the next data PID 0 is always read wh
84. I O transmission FFE516 FFE416 At completion of serial I O data transmission CNTRo FFE316 FFE216 At detection of either rising or falling edge of CNTRo input Key on wake up FFE116 FFE016 At falling of conjunction of input level for port PO at input mode A D conversion FFDF16 FFDE16 At completion of A D conversion BRK instruction FFDD16 FFDC16 At BRK instruction execution Notes 1 Vector addresses contain interrupt jump destination addresses 2 Reset function in the same way as an interrupt with the highest priority Rev 2 00 Oct15 2006 page 17 of 130 REJ09B0338 0200 2RENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Interrupt disable flag I Interrupt request Fig 13 Interrupt control 0 Interrupt edge selection register INTEDGE address OFF316 INTo interrupt edge selection bit Not used return 0 when read INT1 interrupt edge selection bit Not used return 0 when read 0 Falling edge active 1 Rising edge active b7 bO Interrupt request register 1 Interrupt request register 2 IREQ1 address 003C16 IREQ2 address 003D16 USB bus reset interrupt request bit INT1 interrupt request bit USB SOF interrupt request bit USB HUB interrupt request bit USB device interrupt request bit Serial I O receive interrupt request bit EXB interrupt request bit Serial I O tra
85. PLLCON address OFF816 lt 111010002 USB division mode bit4 3 Divided by 6 Enable PLL operation bit7 Wait for oscillation stabilization When multiplying oscillation by PLL wait for oscillation stabilization Wait approximately 1 ms USBCON address 1016 X1XXXXXX2 Select PLL circuit output clock fvco as a USB clock CPUM address 3B16 lt 11101X002 Select fsyn BMHz as a system clock oN Same setting procedure when hardware reset Note The above setting example assumes the operation when the external oscillating clock is 6 MHz and the internal system clock is fsYn Fig 2 11 8 Related registers setting when recovery from stop mode 2 11 4 Notes on PLL 6 MHz or 12 MHz external oscillator can be connected as an input reference clock f Xin When using the frequency synthesized clock function we recommend using the fastest frequency possible of f X as an input clock reference for the PLL When enabling PLL operation from PLL disabled status disabled when reset set the USB clock select bit of USBCON to 0 f Xin to operate with the main clock f Xw When supplying fvco to the USB block after setting PLL operation enable bit to 1 PLL enabled wait for the oscillation stable time 1 ms or less of PLL to avoid any instability caused by the clock then set USB clock select bit to 1 USB clock When selecting fsyn as an internal system clock fuss must be 48 MHz When se
86. Pulse output mode Timer 2 latch 8 Timer 2 8 p gt Timer 2 interrupt request bit Timer 1 interrupt request bit HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION SERIAL INTERFACE 1 Clock Synchronous Serial I O Mode Serial I O Clock synchronous serial I O mode can be selected by setting the Serial I O can be used as either clock synchronous or asynchro mode selection bit of the serial I O control register bit 6 of ad nous UART serial I O A dedicated timer baud rate generator is dress OFE016 to 1 also provided for baud rate generation For clock synchronous serial I O the transmitter and the receiver must use the same clock If an internal clock is used transfer is started by a write signal to the Trancemit Receive buffer register Data bus Address 002616 Address OFE0is Receive buffer full flag RBF P40 ExDREQ RxD O Receive interrupt request RI Shift clock Clock control circuit P42 ExTC ScLk Serial I O synchronous clock selection bit BRG count source selection bit System clock O 2 Address 0FE216 P stExAvSiov o F Shift clock Transmit shift register shift completion flag TSC Transmit interrupt source selection bit P41 ExDACK TxD Q o Transmit interrupt request TI Transmit buffer empty flag TBE Address 002716 Address 002616 I Data bus Fig 18 Block diagram of clock synchronous serial I O Transfer shift clock
87. REJ09B0338 0200 2RENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION 5 Memory Channel Receiving Operation 3 Burst Mode Terminal Count Memory channel receiving operation 3 is shown bellow Address ExA0 Chip select ExCS DMA acknowledge ExDACK Terminal count ExTC Write ExWR Data DQo to DQ7 Internal clock o E a a DMA request ExDREQ mWR detection mWR detection Receive buffer RxBuf mTC detection TC synchronizing TC end Operation enabled Main sequencer Memory channel operation end interrupt Internal memory access req L I Memory address 010016 010116 010216 Counter end Burst end ILLU IIi aA AU a a aa A Wia a pa lax lax lt lnitial setting gt External I O configuration register Set as necessary Memory channel operation mode register MC_DIR 1 0 Memory channel direction control 012 Receive mode Burst burst 1 Burst mode Memory address counter Example 010016 End address register Example 010716 lt Operation start command gt EXB interrupt source enable register MC_ENB Memory channel operation enable 1 Operation start When a rise of TC is detected negation of the memory channel request which synchronized with a rise of is made When the write operation to the end address has been completed the memory channel operation end interrupt is generated
88. REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION b7 bO fofofofofololo HUB downstream port index register HUBINDEX address 002A16 At reset Bit symbol Bit name Function HW T S W 0 DPIDX HUB downstream port index bit 0 HUB downstream port 1 1 HUB downstream port 2 b7 b1 Not used Write 0 when writing L oio 0 is read when reading State remaining Fig 95 Structure of HUB downstream port index register Rev 2 00 Oct 15 2006 page 64 of 130 7tENESAS REJ09B0338 0200 38K2 Group 1 Downstream port 1 HARDWARE FUNCTIONAL DESCRIPTION DP1 interrupt source register DP1REQ address 002B16 Bit symbol Bit name Function At reset H W S W PTDIS1 Downstream port 1 disconnect detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus disconnect state 2 5 us or more of SEO on a downstream port 1 in DSCONN1 1 0 can be set by software but 1 cannot be set 0 me PTCON1 Downstream port 1 connect detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus connect state 2 5 us or more of J or K state on a downstream port 1 in DSCONN1 0 0 can be set by software but 1 cannot be set PTERR1 Do
89. Software Commands Table 10 lists the software commands After setting the CPU Rewrite Mode Select Bit to 1 write a soft ware command to specify an erase or program operation Each software command is explained below Read Array Command FF 16 The read array mode is entered by writing the command code FF 16 in the first bus cycle When an address to be read is input in one of the bus cycles that follow the contents of the specified ad dress are read out at the data bus Do to D7 The read array mode is retained intact until another command is written Read Status Register Command 7016 When the command code 7016 is written in the first bus cycle the contents of the status register are read out at the data bus Do to D7 by a read in the second bus cycle The status register is explained in the next section Clear Status Register Command 5016 This command is used to clear the bits SR4 and SR5 of the status register after they have been set These bits indicate that opera tion has ended in an error To use this command write the command code 5016 in the first bus cycle Program Command 4016 Program operation starts when the command code 4016 is writ ten in the first bus cycle Then if the address and data to program are written in the 2nd bus cycle the control circuit of flash memory data programming and verification will start a program Whether the write operation is completed can
90. TXBUF Memory channel operation mode register This register sets the operation mode of the memory channel Rev 2 00 Oct15 2006 page 76 of 130 REJ09B0338 0200 END_A 10 8 Tee Not used 0 0 fixed Memory address counter This is a counter to set the beginning address which FIFO ac cesses This register is increased by access from the external MCU bus End address register This register is to set the end address which FIFO accesses 2RENESAS 38K2 Group EXB Related Registers The EXB related registers are shown below FUNCTIONAL DESCRIPTION HARDWARE b7 bo ofofofofo EXB interrupt source enable register EXBICON address 003016 Note P z At reset l Bit symbol Bit name Function aw SW R w RXB_ENB CPU channel receive enable bit 0 Operation disabled Interrupt disabled 0 Joio 1 Operation enabled Receive buffer full interrupt enabled i TXB_ENB CPU channel transmit enable bit 0 Operation disabled Interrupt disabled 0 10 0 1 Operation enabled Transmit buffer empty interrupt enabled l MC_ENB Memory channel operation 0 Operation disabled Memory channel operation end 0 O O enable bit interrupt disabled I 1 Operation enabled Memory channel operation end interrupt disabled i b7 b3 Not used Write 0 when writing JOO 0 is read when reading State remaining Note Do not
91. The minimum instruction execution time ee 0 25 us at 8 MHz system clock System clock Reference frequency to internal circuit except USB function e Memory size ROMo eanet na eTA A E 16 K to 32 K bytes RAM tastes aces iirisissisisegii eenige 1024 to 2048 bytes e Programmable input output ports sessseessessieerreerrnerieerrerrenens 44 e Software pull up resistors SINOU P S ninrinta 16 sources 16 vectors eUSB function Full Speed USB2 0 specification 4 endpoints eUSB HUB function Full Speed USB2 0 specification 2 down ports External bus interface seeseeeeeeeeeereeneens 8 bit X 1 channel PIN CONFIGURATION TOP VIEW HARDWARE DESCRIPTION FEATURES PIN CONFIGURATION TIMES iane ie Aa aiet 8 bit X 3 Watchdog ter ss ticccccussrccsccveceneseeceuteessccuadeesenesseavecs ose 16 bit X 1 e Serial Interface Serial I O eee 8 bit X 1 UART or Clock synchronized A D converter wctcsiccciecictecssalagtecdacsecdenteeiniseasees 10 bit X 8 channels 8 bit reading available s LED direct drive POr ccccscccssccisssevssesnestessestecuecs ott ecscstessectessenseeteess 4 e Clock generating circuit connect to external ceramic resonator or quartz crystal oscillator e Power source voltage L version System clock Internal clock division mode At 12 MHz 2 divide mode o 6 MHZ sessen 4 00 to 5 25 V At 8 MHz Through mode 8 MHZ ee 4 00 to 5 25 V At 6 MHz Through mode 6 MH
92. Transmit mode Do not set 0 Burst bit Cycle mode each byte transfer according to assertion or negation 1 Burst mode continuous transfer till the terminal count Not used Write 0 when writing 0 is read when reading State remaining Fig 117 Index02 low Structure of Memory channel operation mode register Index 0316 Memory address counter MEMADL address 003416 Bit symbol Bit name At reset Function H W S W IM_A 7 0 Register to set the low order address of memory channel operation beginning This contents are increased each time one memory access ends 0 Fig 118 Index03 low Structure of Memory address counter Rev 2 00 Oct15 2006 page 80 of 130 REJ09B0338 0200 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION b7 bO ofofofolo Index 0316 Memory address counter MEMADH address 003516 At reset H W S W IM_A Register to set the high order address of memory 0 10 8 channel operation start This contents are increased each time one memory access ends Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 119 Index03 high Structure of Memory address counter Index 0416 End address register ENDADL
93. Ver icc cccccececcccetneeecceeeeeceebbng eevee aS E RREN AR KRR 5 3 1 4 A D converter characteristics L Ver cccceeeececeeeeeeeneee cee eeeeeaeeseeeeeeeaaaeseeeeeetaaeeneneees 7 3 1 5 Timing requirements L VEP 0 ee ceeeeee eee eeeeee eee eeeeeeeeeeeaeeeeeeseaeeeeeeseeeeeeeeteneaeeeeeeeneaeeees 8 3 1 6 Switching characteristics L Ver ceceececesseeeeeeeececeeeeeeeeeseaaeeeeeeeeseeaeeeseneeseeaeeeenaeeeeaees 11 3 2 Notes OM USC soni siiecceciicc ecb tects ne eee etn eee eee ee 20 3 2 1 Notes on input and output POTTS 2 0 eee eect eee cette eeeeee E NEEE 20 3 2 2 Termination Of UNUSEM PINS riesasta iannis aan anaa aaa aeaaea ad 21 3 2 3 Notes on INterrupts scesa A E 22 3 2 4 Notes OM UME arsson ini ian e E EONA OE OOE OEE OOE ONA 23 3 2 5 Notes of serial Q dsrarismsiienaian oea iae a aa a a aa A aa aa 24 3 26 Notes on USB fUNCUON eier a aa A a a aa aaa 26 3 2 7 Notes on A D Converter arcocrierariirinn ria EANA EANAN NANA AENEA ERNETEN 27 3 2 8 Notes ON watchdog tMar eee ee eeeeeeeeeeeeeeee eee eeeeceeeeeeeeeeeeeesaaeeeeeeeeneeeeeeseeeeaeeeeseeaaaees 27 3 2 9 Notes on TE ET pin wis ddvistnstxsganedain dig iat Sapaltessdcaclnasawtalng Masabes acai ticadasdaytantsoauaenees 27 8 2 10 Notes on Pl es yee eine elves ee Le eed 27 3 2 11 Notes on Stand by FUNCTION eee ee ee eeeee eee teeee eset innein AANA KRENAN AEEA EE 28 3 2 12 Notes on CPU rewrite mode ccccececcceneeeeeeeeeeceeeeeneeeceaaeseeaaeeseeaeeeeaaaeseeae
94. Vss pattern As for a two sided printed circuit board print a VSS pattern on the underside soldering side of the position on the component side where an oscillator is mounted Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring Besides separate this Vss pattern from other Vss patterns An example of Vss patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the Vss line for oscillation from other Vss lines Fig 3 3 10 Vss pattern on the underside of an oscillator 3 3 5 Setup for I O ports Setup I O ports using hardware and software as follows lt Hardware gt e Connect a resistor of 100 Q or more to an I O port in series lt Software gt e As for an input port read data several times by a program for checking whether input levels are equal or not e As for an output port since the output data may reverse because of noise rewrite data to its port latch at fixed periods e Rewrite data to direction registers at fixed periods Note When a direction register is set for input port again at fixed periods a several nanosecond short pulse may be output from this port If this is undesirable connect a capacitor to this port to remove the noise pulse I O port Fig 3 3 11 Setup for I O ports Rev 2 00 Oct 15 2006 page 37 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 3 Countermeasures against noise 3 3 6 Providing of wa
95. X mode register address 2316 b7 bo m ETT afolofe Timer X operating mode Pulse output mode CNTRo active edge selection Output starting at H level Timer X count Stop Clear to 0 when starting count Timer X address 2516 b7 bO xl o _ gt Set division ratio 1 Pieoeael X address 2416 PREX Fig 2 3 15 Related registers setting RESET Initialization x This bit is not used here Set it to O or 1 arbitrarily P5 address 0A16 bitt lt 1 P5D address 0B16 lt XXXxxx1x2 ICON1 address 3E16 bit4 0 Timer X interrupt disabled TM address 2316 lt xxxx10012 CNTRo output stop Piezoelectric buzzer output stop TX address 2516 lt 92 1 Division ratio 1 set to Timer X and Prescaler X PREX address 2416 lt 1 1 Main processing Output unit Processing piezoelectric buzzer request generated during main processing in output unit Piezoelectric buzzer request TM address 2316 bit3 lt 1 TM address 2316 bit3 lt 0 TX address 2516 lt 92 1 Piezoelectric buzzer output start Stop piezoelectric buzzer output Fig 2 3 16 Control procedure Rev 2 00 Oct 15 2006 page 32 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 3 Timer 4 Timer application example 3 Frequency measurement Outline The following two values are compared to judge whether the frequency is within a valid rang
96. a program or erase operation has terminated normally or in error can be verified by reading the status register Figure 147 shows the flash memory control register Bit 0 is the RY BY status flag used exclusively to read the operat ing status of the flash memory During programming and erase operations it is 0 busy Otherwise it is 1 ready This is equivalent to the RY BY pin function in parallel I O mode Bit 1 is the CPU Rewrite Mode Select Bit When this bit is set to 1 the MCU enters CPU rewrite mode Software commands are accepted once the mode is entered In CPU rewrite mode the bO HARDWARE FUNCTIONAL DESCRIPTION CPU becomes unable to access the internal flash memory directly Therefore use the control program in a memory other than inter nal flash memory for write to bit 1 To set this bit to 1 it is necessary to write 0 and then write 1 in succession The bit can be set to 0 by only writing 0 Bit 2 is the CPU Rewrite Mode Entry Flag This flag indicates 1 in CPU rewrite mode so that reading this flag can check whether CPU rewrite mode has been entered or not Bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory This bit is used when exiting CPU rewrite mode and when flash memory access has failed When the CPU Rewrite Mode Select Bit is 1 setting 1 for this bit resets the control circuit To set this bit to
97. address 003416 At reset R w HW SW END_A Register to set the low order address of memory 0 O O 7 0 channel operation end j Bit symbol Bit name Function e remaining Fig 120 Index04 low Structure of End address register b7 bO fofofofofo Index 0416 End address register ENDADH address 003516 Bit symbol Bit name Function At reset H W END_A Register to set the high order address of memory 10 8 channel operation end b7 b3 Not used Write 0 when writing 0 is read when reading e remaining Fig 121 Index04 high Structure of End address register Rev 2 00 Oct 15 2006 page 81 of 130 2RENESAS REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION EXB Operation Timing Diagram 1 CPU Channel Receiving Operation CPU channel receiving operation is shown bellow Address ExA0 Chip select ExCS Read ExRD Write ExWR Data DQo to DQ7 Internal clock LoL Lr p Emp UU Interrupt request ExINT e 1 RxB_RDY a Reryv Receive buffer full bit RXB_FULL Receive buffer RXBUF 0 x Transmit buffer TXBUF CPU channel receive enable bit RXB_ENB Receive buffer read lt Initial setting gt External I O configuration register INT_CTRY 3 1 P33 ExINT pin control 0012 RxB_RDY interrupt lt Operation start gt EXB interrupt source enable re
98. as a system clock the oscillation stabilizing time for approximately 8 000 cycles of the Xin input is reserved at restoration from the stop mode Notes on stand by function In stand by state for low power dissipation do not make input levels of an input port and an I O port undefined Pull up connect the port to Vcc these ports through a resistor When determining a resistance value note the following points e External circuit e Variation of output levels during the ordinary operation When using built in pull up resistor note on varied current values e When setting as an input port Fix its input level e When setting as an output port Prevent current from flowing out to external Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input port and an I O port are undefined This may cause power source current 1 stand by state the stop mode by executing the STP instruction the wait mode by executing the WIT instruction 3 2 12 Notes on CPU rewrite mode 1 2 3 4 5 Operation speed During CPU rewrite mode set the internal clock 1 5 MHz or less using the system clock division ratio selection bits bits 6 and 7 of address 003Bie Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during the CPU rewrite mode Interrupts inhibited against use The in
99. as either input or output CMOS compatible input level CMOS 3 state output structure e A D converter input pins e External bus interface function pins P24 P27 I O port P2 e 4 bit I O port I O direction register allows each pin to be individually programmed as either input or output CMOS compatible input level CMOS 3 state output structure P30 P32 P33 ExINT P34 ExCS P35 ExWR P36 ExRD P37 ExA0 I O port P3 e 8 bit I O port e I O direction register allows each pin to be individually programmed as either input or output CMOS compatible input level CMOS 3 state output structure e External bus interface function pins P40 ExDREQ RxD P41 ExDACK TxD P42 ExTC SCLK P43 ExA1 SRDY I O port P4 e 4 bit I O port e I O direction register allows each pin to be individually programmed as either input or output CMOS compatible input level e CMOS 3 state output structure e Serial I O function pins e External bus interface function pins P50 INTo P51 CNTRo P52 INT1 P53 P57 I O port P5 e 8 bit I O port e I O direction register allows each pin to be individually programmed as either input or output CMOS compatible input level e CMOS 3 state output structure e Interrupt input pin e Timer X funciton pin e Interrupt input pin P60 P63 Rev 2 00 Oct15 2006 page 4 of 130 I O port P6 REJ09B0338 0200 e 4 bit I O port I O direc
100. at the shortest possible distance 20 mm or less from microcomputer pins Rev 2 00 Oct 15 2006 page 21 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 3 2 3 Notes on interrupts 1 Change of relevant register settings When the setting of the following registers or bits is changed the interrupt request bit may be set to 1 When not requiring the interrupt occurrence synchronized with these setting take the following sequence Interrupt edge selection register address OFF316 Timer X mode register address 2316 Set the above listed registers or bits as the following sequence Set the corresponding interrupt enable bit to 0 disabled L Set the interrupt edge select bit active edge switch bit or the interrupt Source select bit to 1 l NOP one or more instructions Set the corresponding interrupt request bit to 0 no interrupt request issued Set the corresponding interrupt enable bit to 1 enabled Fig 3 2 1 Sequence of changing relevant register E Reason When setting the following the interrupt request bit may be set to 1 When setting external interrupt active edge Concerned register Interrupt edge selection register address OFF316 Timer X mode register address 2316 Rev 2 00 Oct 15 2006 page 22 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 2 Check of interrupt request bit When executing the BBC or B
101. b1 bO 0 0 Endpoint 0 0 1 Endpoint 1 1 0 Endpoint 2 1 1 Endpoint 3 0 at Address index bit 0 USB function 1 USB HUB Not used Write 0 when writing 0 is read when reading Fig 39 Structure of Endpoint index register Rev 2 00 Oct15 2006 page 37 of 130 REJ09B0338 0200 2tENESAS State remaining 38K2 Group 1 Endpoint 00 HARDWARE FUNCTIONAL DESCRIPTION b7 bO fofofofofofolo EPOO stage register EPOOSTG address 001916 Bit symbol Bit name Function At reset H W S W SETUPOO SETUP packet detection bit This bit is set to 1 at reception of SETUP packet Writing 0 to this bit clears this bit if the next SETUP token does not occur Writing 1 to this bit causes no state change of the status flags 1 1 Write 0 when writing 0 is read when reading Fig 40 Structure of EPOO stage register b7 bo fofofofofofo EPOO control register 1 EPOOCON1 address 001A16 State remaining Bit symbol Bit name Function At reset H W S W PIDOO 1 0 Response PID bit b1 bO 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of control transfer error B1 is set to 1 by the hardware At reception of SETUP token B1 and b0 are cleared to 0 by the hardwa
102. b3 b2 b1 bO Port Pi direction register PiD i 0 1 2 3 4 5 6 Note Address 0116 0316 0516 0716 0916 OB16 0D16 Port Pio input mode x Port Pio output mode T Port Pi1 input mode x Port Pit output mode Port Piz input mode x 1 Port Piz output mode 0 Port Pis input mode 1 Port Pis output mode a Port Pia input mode Port Pia output mode T Port Pis input mode x Port Pis output mode Port Pis input mode x 1 Port Pis output mode 0 Port Pi7 input mode x 1 Port Piz output mode Since the following ports are not allocated the corrrsponding bits can not be used P20 to P23 e P44 to P47 P64 to P67 Do not set bits of the direction register corresponding to ports P20o P23 bits 0 3 of port P2 direction register address 0516 to output mode 1 If writing to these bits write O Fig 3 4 2 Structure of Port Pi direction register Rev 2 00 Oct 15 2006 page 39 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers USB control register USBCON address 001016 At reset H W S W WKUP Remote wakeup bit Returning to BUS idle state by writing 1 first and 0 then 0 Remote wakeup signal K state output L output mode valid in TRONE 1 H output mode valid in TRONE 1 TTON port output disabled Hi Z state TrON port output enabled Normal mode valid in VREFE
103. be confirmed by reading the status register or the RY BY Status Flag When the program starts the read status register mode is entered automati cally and the contents of the status register is read at the data bus DBo to DB7 The status register bit 7 SR7 is set to O at the same time the write operation starts and is returned to 1 upon completion of the write operation In this case the read status reg ister mode remains active until the read array command FF 16 is written Table 10 List of software commands CPU rewrite mode HARDWARE FUNCTIONAL DESCRIPTION During the program movement The RY BY Status Flag of flash memory control register is set to O When the program com pletes it becomes 1 At program end program results can be checked by reading the status register Write 4016 aa Write address W me Write data Status register read SR7 1 RY BY 1 YES Program completed Fig 149 Program flowchart First bus cycle Program error Second bus cycle Command Cycle number Read array Address X Note 4 Data Do to D7 Address Read status register X SRD Note 1 Clear status register Program WA Note 2 WD Note 2 Erase all blocks X 2016 Block erase Notes 1 SRD Status Register Data 2 WA Write Address WD Write Data 3 BA Block Address to be erased Input the maximum address of each bl
104. bit Operation disabled Receive mode Transmit mode Do not set Burst bit 0 Cycle mode each byte transfer according to assertion or negation 1 Burst mode continuous transfer till the terminal count Not used Write 0 when writing 0 is read when reading 00 01 10 11 State remaining Fig 3 4 71 Index02 low Structure of Memory channel operation mode register Index 0316 Memory address counter MEMADL address 003416 At reset H W S W IM_A Register to set the low order address of memory 0 7 0 channel operation beginning This contents are increased each time one memory access ends Bit symbol Bit name Function Fig 3 4 72 Index03 low Structure of Memory address counter Rev 2 00 Oct 15 2006 page 68 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers Index 0416 End address register ENDADL address 003416 i At reset B i F RW it symbol Bit name unction Hw Siw END_A Register to set the low order address of memory 0 O O 7 0 channel operation end State remaining Fig 3 4 73 Index04 low Structure of End address register Register window 2 EXBREG2 address 003516 At reset H W S W HIGH_WIN The accessible register using this register window In In 7 0 depends on the E
105. bit and an interrupt disable flag as described in detail below Figure 2 2 11 shows an interrupt control diagram Interrupt request bit Interrupt enable bit Interrupt request Interrupt disable flag BRK instruction Reset Fig 2 2 11 Interrupt control diagram The interrupt request bit interrupt enable bit and interrupt disable flag function independently and do not affect each other An interrupt is accepted when all the following conditions are satisfied lnterrupt request bit 4 lnterrupt enable bit 4 lnterrupt disable flag 0 Though the interrupt priority is determined by hardware a variety of priority processing can be performed by software using the above bits and flag Table 2 2 2 shows a list of interrupt control bits according to the interrupt source 1 Interrupt request bits The interrupt request bits are allocated to the interrupt request register 1 address 3Cie and interrupt request register 2 address 3Die The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to 1 The interrupt request bit is held in the 1 state until the interrupt is accepted When the interrupt is accepted this bit is automatically cleared to 0 Each interrupt request bit can be set to 0 but cannot be set to 1 by software 2 Interrupt enable bits The interrupt enable bits are allocated to the interrupt control reg
106. by direct RAM access of the memory channel controller between the external MCU and the 38K2 group s memory multichannel RAM Address LT CS RD WR l o DMA acknowledge lt Data transfer of memory channel When the burst mode is selected with the burst bit of the memory channel operation mode register data transfer can be carried out at the highest speed After the external bus interface detects a rise of external read signal write signal and synchronizes it with the in ternal clock 0 it completes the data transfer between the transmit receive buffer and the multichannel RAM in two clocks However the waiting time of two clocks at a maximum is gener ated to access the multichannel RAM in USB being operating because the USB has priority to access Therefore it is necessary to set up the access interval which fills the following timing with the external MCU bus side In 8 MHz data transfer at about 2 Mbytes second is possible at a maximum When there is access simultaneously from the USB it is about 1 3 Mbytes second In 6 MHz data transfer at about 1 5 Mbytes second is possible at a maximum When there is access simultaneously from the USB it is about 1 Mbytes second Access cycle time from externals 3 clocks or more of Signal delay time Data setup time of external MCU in USB inactive 5 clocks or more of Signal delay time Data setup time of external MCU in USB active Fig 104 Da
107. command decoder and an output selector Acommand decoder generates the follow ing signals to each unit CPU interface part CPU channel read Cch_RD CPU channel write Cch_WR lnternal memory interface part Memory channel read Mch_RD Memory channel write Mch_WR Memory channel terminal count Mch_TC Transmit receive data buffer part Buffer write Buf_WR External I O interface part Status selection stt_sel Output enable ExOE Access to the CPU channel can be controlled only by setup of external signals Access to the memory channel can be controlled by the value of the external I O configuration register and the state mRX_enb mTX_enb signals of the internal memory interface part The output selector has the function which selects from the state of CPU channel TxB_RDY and RxD_RDY and the state of memory channel Mch_req as the signal assigned to P33 ExINT pin and P40 ExDREQ RxD pin Rev 2 00 Oct15 2006 page 73 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION 2 CPU Interface Part The CPU interface part consists of the decoder data selector of the CPU channel the CPU write register and CPU channel con troller Decoder data selector of CPU channel A write operation to the CPU register is performed by generating a write signal for each register with an address decode signal and a write signal A read operation from the CPU register is performed by generat ing an output enable si
108. control program in the area except the built in flash memory for write to this bit 3 This bit is valid when the CPU rewrite mode select bit is 1 Set this bit 3 to 0 subsequently after setting bit 3 to 1 4 Use the control program in the area except the built in flash memory for write to this bit Fig 147 Structure of flash memory control register Rev 2 00 Oct15 2006 page 102 of 130 REJ09B0338 0200 2tENESAS 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION Single chip mode or Boot mode Note 1 y Set CPU mode register Note 2 Transfer CPU rewrite mode control program to memory other than internal flash memory Jump to control program transferred in memory other than internal flash memory Subsequent operations are executed by control program in this memory Set CPU rewrite mode select bit to 1 by writing 0 and then 1 in succession Check CPU rewrite mode entry flag Using software command execute erase program or other operation Execute read array command or reset flash memory by setting flash memory reset bit by writing 1 and then 0 in succession Note 3 Write 0 to CPU rewrite mode select bit Notes 1 When starting the MCU in the single chip mode or memory expansion mode supply 4 5 V to 5 25 V to the CNVss pin until checking the CPU rewrite mode entry flag 2 Set the system clock division ration selection bits of CPU mode register b
109. control register 1 ICON1 Address 3E16 C __Funation ___freet USB bus reset Interrupt disabled interrupt enable bit Interrupt enabled USB aa interrupt Interrupt disabled enable b Interrupt enabled USB coe interrupt Interrupt disabled 0 foto enable b Interrupt enabled EXB interrupt Interrupt disabled enable bit Interrupt enabled INTo interrupt Interrupt disabled enable bit Interrupt enabled Timer X interrupt Interrupt disabled enable bit Interrupt enabled Timer 1 interrupt Interrupt disabled enable bit Interrupt enabled Timer 2 interrupt Interrupt disabled oio enable bit Interrupt enabled Fig 3 4 85 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 bO ol PY TTT TT Interrupt control register 2 ICON2 a 3F16 i et interrupt Interrupt disabled enable bit Interrupt enabled USB HUB interrupt Interrupt disabled l enable bit i Interrupt enabled i 9 Serial I O receive 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 3 Serial I O transmit 0 Interrupt disabled i interrupt enable bit 1 Interrupt enabled 4 CNTR o interrupt 0 Interrupt disabled i enable bit 1 Interrupt enabled i Key on wake up i Interrupt disabled i interrupt enable bit Interrupt enabled A D conversion Interrupt disabled interrupt enable bit Interrupt enabled i 7 Fix this bit to 0 Fig 3 4 86 Structure of Interrupt co
110. cy A D control circuit A D interrupt request i AD conversion register 2 _ Comparator P AD conversion register 1 Channel selector P16 DQ6 ANs O P17 DQ7 AN7 O Fig 134 A D converter block diagram Rev 2 00 Oct15 2006 page 92 of 130 REJ09B0338 0200 address 003816 address 003716 7RENESAS 38K2 Group WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop for example be cause of a software run away The watchdog timer consists of an 8 bit watchdog timer L and an 8 bit watchdog timer H Standard Operation of Watchdog Timer When any data is not written into the watchdog timer control reg ister address 003916 after resetting the watchdog timer is in the stop state The watchdog timer starts to count down by writing an optional value into the watchdog timer control register address 003916 and an internal reset occurs at an underflow of the watch dog timer H Accordingly programming is usually performed so that writing to the watchdog timer control register address 003916 may be started before an underflow When the watchdog timer control reg ister address 003916 is read the values of the high order 6 bits of the watchdog timer H STP instruction disable bit bit 6 and watchdog timer H count source selection bit bit 7 are read Initial Value of Watchdog Timer At reset or writi
111. disabled 1 IN Data is transmitted to the host Not used Write 0 when writing 0 is read when reading Transfer type bite 0 Transfer disabled 1 Interrupt transfer Fig 81 Structure of EP11 set register b7 bo fofofofofofo EP11 control register 1 EP11CON1 address 001A16 State remaining Bit symbol Bit name Function At reset R W H W S W PID11 1 0 Response PID bit b1 bO 0 0 NAK 0 1 Automatic response NAK DATAO DATA1 1 X STALL 0 010 Fig 82 Structure of EP11 control register 1 Write 0 when writing 0 is read when reading 00 b7 bo fofofofofofofo EP11 control register 2 EP11CON2 address 001B16 State remaining Bit symbol Bit name Function At reset H W RW i BOVAL11 Buffer 0 status bit This bit set to 1 shows the transmitting data is in a set state SIE is possible to read 0 0 0 b7 b1 Not used Write 0 when writing 0 is read when reading O O Fig 83 Structure of EP11 control register 2 Rev 2 00 Oct15 2006 page 56 of 130 REJ09B0338 0200 2tENESAS State remaining HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION b7 bO fofofofofofolo EP11 interrupt source register EP11REQ address 001D16 B
112. enable register This register enables disables access from an external bus and an internal interrupt EXB interrupt source register This register indicates the state of CPU channel s transmit receive buffer register and the memory channel The same value can be read out from the external MCU bus by using the buffer status read select signal A1 pin H HIGH_WIN 7 0 0 0 fixed EXB index register Register windows 1 2 The accessible register is switched by treating addresses 003416 and 003516 as a register window depending on the value of EXB index register at address 003316 FR Index 0 Register Name SYMBOL EXB S high bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito INT_CTR 2 0 EXB_CTR 0016 w External I O configu EXBCFGL ration register high EXBCFGH RXBUF TXBUF DAK_CTR 1 0 DRQ_CTR 1 0 At CPU read RXBUF 7 0 At CPU write TXBUF 7 0 jo 0116 ow Transmit Receive buffer register high jo 0216 w Memory channel ope MCHMOD ration mode register high MEMADL MEMADH 0316 ow Memory address counter high ENDADL IM_A 10 8 ENDADH 0416 ow End address register high Fig 108 EXB related registers 2 External I O configuration register This register selects the function of each pin Transmit Receive buffer register This register consists of the receive buffer register RXBUF and the transmit buffer register
113. input sequentially from the smallest address first that page is auto matically written When reception setup for the next 256 bytes ends the SRDY BUSY signal changes from H to L level The result of the page program can be known by reading the status register For more information see the section on the status register data255 SRDY BUSY Fig 158 Timing for page program Rev 2 00 Oct15 2006 page 117 of 130 REJ09B0338 0200 2tENESAS 38K2 Group Erase All Blocks Command This command erases the contents of all blocks Execute the erase all blocks command as explained here following 1 Transfer the A716 command code with the 1st byte 2 Transfer the verify command code D016 with the 2nd byte With the verify command code the erase operation will start and continue for all blocks in the flash memory HARDWARE FUNCTIONAL DESCRIPTION When erase all blocks end the SRDY BUSY signal changes from H to L level The result of the erase operation can be known by reading the status register D016 Fig 159 Timing for erase all blocks Rev 2 00 Oct15 2006 page 118 of 130 REJ09B0338 0200 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION Download Command This command downloads a program to the RAM for execution Execute the download command as explained here following 1 Transfer the FA16 command code with the 1st byte 2 Transfe
114. instruction BBC or BBS etc to a direction register The read modify write instructions ROR CLB or SEB etc to a direction register Use instructions such as LDM and STA etc to set the port direc tion registers A D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low Therefore make sure that f system clock in the middle high speed mode is at least on 500 kHz during an A D conversion Do not execute the STP or WIT instruction during an A D conver sion Rev 2 00 Oct 15 2006 page 126 of 130 REJ09B0338 0200 HARDWARE NOTES ON PROGRAMMING Instruction Execution Time The instruction execution time is obtained by multiplying the fre quency of the internal clock b by the number of cycles needed to execute an instruction However When using the USB function or EXB function an occurrence of one wait due to the multichannel RAM will double an internal clock o cycle 2RENESAS 38K2 Group Definition of A D Conversion Accuracy The A D conversion accuracy is defined below refer to Figure 167 Relative accuracy Zero transition voltage VOT This means an analog input voltage when the actual A D con version output data changes from 0 to 1 Full scale transition voltage VFST This means an analog input voltage when the actual A D con version output data changes from 1023 to 1022 Output data HARDWARE NOT
115. instructions for reading and writing data by a byte unit Accordingly when these instructions are executed on a bit of the port latch of an I O port the following is executed to all bits of the port latch As for a bit which is set for an input port The pin state is read in the CPU and is written to this bit after bit managing e As for a bit which is set for an output port The bit value of the port latch is read in the CPU and is written to this bit after bit managing Note the following e Even when a port which is set as an output port is changed for an input port its port latch holds the output data e As for a bit of the port latch which is set for an input port its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents 1 bit managing instructions SEB and CLB instructions Rev 2 00 Oct 15 2006 page 6 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 1 I O port 2 1 5 Termination of unused pins 1 Terminate unused pins I O ports e Set the I O ports for the input mode and connect them to Vcc or Vss through each resistor of 1 KQ to 10 kQ With regard to ports which can select the built in pull up resistor the built in pull up resistor can be used Set the I O ports for the output mode and open them at L or H e When opening them in the output mode the input mode of the initial status remains until t
116. interface enable bit Direction register Port latch Serial I O clock output Serial I O external clock input ExTC Ce 10 Port P43 Serial I O mode selection bit 7 Serial I O enable bit Srpy output enable bit 1 External bus interface enable bit Da 7 7 i Direction register Serial I O synchronous clock selection bit External bus interface enable bit a Direction register Data bus J gt _ Port latch Serial I O output _ gt ExA1 Fig 11 Port block diagram 2 Rev 2 00 Oct15 2006 page 15 of 130 REJ09B0338 0200 lt External bus interface enable bit HARDWARE FUNCTIONAL DESCRIPTION 11 Ports P50 P52 Pull up 1 gt Direction register Data bus _ Port latch p lt 21 INTo P50 INT1 P52 interrupt input Ge 12 Port P51 mea Direction register Data bus gt _ Port latch se output mode Timer output CNTRo interrupt input 13 Ports P53 P57 Direction register Data bus Port l
117. interrupt occurrence synchronized with these setting take the following sequence Set the corresponding interrupt enable bit to 0 disabled Set the interrupt edge select bit active edge switch bit Set the corresponding interrupt request bit to O after 1 or more instructions have been executed Set the corresponding interrupt enable bit to 1 enabled Interrupt Request Generating Conditions Reset Note 2 FFFD16 FFFC16 At reset USB bus reset FFFB16 FFFA16 At detection of USB bus reset signal 2 5 us interval SEO USB SOF FFF916 FFF816 At detection of USB SOF signal USB device FFF716 FFF616 At detection of resume signal K state or SEO or suspend signal 3 ms interval bus idle or at completion of transaction External bus FFF516 FFF416 At completion of reception or transmission or at completion of DMA transmission INTo FFF316 FFF216 At detection of either rising or falling edge of INTo input Timer X FFF 116 FFFO16 At timer X underflow Timer 1 FFEF 16 FFEE16 At timer 1 underflow Timer 2 FFED16 FFEC16 At timer 2 underflow INT1 FFEB16 FFEA16 At detection of either rising or falling edge of INT1 input USB HUB FFE916 FFE816 At detection of USB HUB downport s state switch Serial I O reception FFE716 FFE616 At completion of serial I O data reception Serial
118. is set to 1 when the buffer 0 is ready state enabled to be read written on USB function Endpoint 2 0 can be set by software but 1 cannot be set 0 0 B1RDY02 USB function Endpoint 2 buffer 1 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued In single buffer mode this bit is invalid This bit is set to 1 when the buffer 1 is ready state enabled to be read written on USB function Endpoint 2 in double buffer mode 0 can be set by software but 1 cannot be set USB function Endpoint 2 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when STALL response occurs on USB function Endpoint 2 0 can be set by software but 1 cannot be set b7 to b3 Not used Write 0 when writing 0 is read when reading Fig 3 4 37 Structure of EP02 interrupt source register Rev 2 00 Oct15 2006 page 52 of 99 REJ09B0338 0200 2tENESAS 38K2 Group APPENDIX 3 4 List of registers b7 bo ofofofofo EPO3 interrupt source register EPO3REQ address 001D16 Bit symbol Bit name Function At reset H W S W BORDY03 USB function Endpoint 3 buffer 0 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer 0 is re
119. mode 1 Rising edge active for CNTRo interrupt Count at falling edge in event counter mode Timer X count stop bit 0 Count start 1 Count stop Not used return 0 when read Fig 16 Structure of timer X mode register Rev 2 00 Oct15 2006 page 20 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Timer 1 and Timer 2 The count source of prescaler 12 is the system clock divided by 16 The output of prescaler 12 is counted by timer 1 and timer 2 and a timer underflow periodically sets the interrupt request bit Timer X Timer X can each select in one of four operating modes by setting the timer X mode register 1 Timer Mode The timer counts the count source selected by timer count source selection bit 2 Pulse Output Mode The timer counts the system clock divided by 16 Whenever the contents of the timer reach 0016 the signal output from the CNTRo pin is inverted If the CNTRo active edge selection bit is 0 output begins at H If it is 1 output starts at L When using a timer in this mode set the corresponding port P51 direction register to output mode 3 Event Counter Mode Operation in event counter mode is the same as in timer mode except that the timer counts signals input through the CNTRo pin When the CNTRo active edge selection bit is 0 the rising edge of the CNTRo pin is counted When the CNTRo active edge selection bit is 1 t
120. of EP01 buffer area set register Rev 2 00 Oct15 2006 page 44 of 130 REJ09B0338 0200 7tENESAS State remaining 38K2 Group 3 Endpoint 02 HARDWARE FUNCTIONAL DESCRIPTION EP02 set register EPO2CFG address 001916 Bit symbol Bit name Function At reset H W S W BSIZ02 1 0 Double buffer beginning address set bit In double buffer mode set the beginning address of buffer 1 area using a relative value for the beginning address of buffer 0 b1b0 0 0 8bytes 01 16 bytes 1 0 64 bytes 1 1 128 bytes 0 DBLB02 Buffer mode select bit 0 Single buffer mode 1 Double buffer mode SQCL02 Sequence toggle bit clear bit 0 Toggle bit clear disabled 1 Writing 1 clears the toggle bit and DATAO is used as the next data PID 0 is always read when reading ITMD02 Interrupt toggle mode select bit 0 Normal mode 1 Continuous toggle mode valid at Interrupt IN transfer DIR02 Transfer direction bit 0 OUT Data is received from the host 1 IN Data is transmitted to the host TYP02 1 0 Transfer type bite b7b6 0 0 Transfer disabled 0 1 Bulk transfer 1 0 Interrupt transfer 1 1 lsochronous transfer Fig 56 Structure of EP02 set register b7 bo fofofofofofo EP02 control register 1 EPO2CON1 address 001A16 State remaining
121. of a e Transmission data write transmission data Transmit buffer empty flag is set to 0 by this writing e Judgment of transferring from Transmit buffer register to Transmit shift register Transmit buffer empty flag e Judgment of shift completion of Transmit shift register Transmit shift register shift completion flag Fig 2 4 17 Control procedure of transmitting side Rev 2 00 Oct 15 2006 page 51 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O RESET x This bit is not used here Set it to 0 or 1 arbitrarily Initialization SIOCON Address OFEO16 lt 1111x11x2 e An interval of 2 ms generated by Timer Y TB RB Address 2616 lt Dummy data e Srpy output Srpy signal is output by writing data to the TB RB Using the Srpy set Transmit enable bit bit4 of the SIOCON to 1 SIOSTS Address 2716 bit Judgment of completion of receiving Receive buffer full flag 1 Read out reception data from e Reception of the first byte data TB RB Address 2616 Receive buffer full flag is set to 0 by reading data SIOSTS Address 2716 bit1 e Judgment of completion of receiving Receive buffer full flag Read out reception data from e Reception of the second byte data TB RB Address 2616 Receive buffer full flag is set to O by reading data Fig 2 4 18 Control procedure of receiving side Rev 2 00 Oct 15
122. of wiring which is connected to clock I O pins as short as possible e Make the length of wiring within 20 mm across the grounding lead of a capacitor which is connected to an oscillator and the Vss pin of a microcomputer as short as possible e Separate the Vss pattern only for oscillation from other Vss patterns Reason If noise enters clock I O pins clock waveforms may be deformed This may cause a program failure or program runaway Also if a potential difference is caused by the noise between the Vss level of a microcomputer and the Vss level of an oscillator the correct clock will not be input in the microcomputer Fig 3 3 3 Wiring for clock I O pins 4 Wiring to CNVss pin Connect the CNVss pin to the Vss pin with the shortest possible wiring Reason The processor mode of a microcomputer is influenced by a potential at the CNVSs pin If a potential difference is caused by the noise between pins CNVss and Vss the processor mode may become unstable This may cause a microcomputer malfunction or a program runaway Fig 3 3 4 Wiring for CNVss pin Rev 2 00 Oct 15 2006 page 33 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 3 Countermeasures against noise 5 Wiring to VPP pin of Flash memory version Connect an approximately 5 kQ resistor to the VPP pin the shortest possible in series and also to the Vss pin When not connecting the resistor make the length of wiring between the VPP pin and the Vss pin
123. output latch is written to and the pin remains floating Table 5 I O ports functions Pin Name Input Output 1 0 Format Non Port Function HARDWARE FUNCTIONAL DESCRIPTION Related SFRs Diagram No POo P07 Port PO P10 P17 Port P1 P24 P27 Port P2 P33 ExINT P34 ExCS P35 ExWR P36 ExRD P37 ExAO Port P3 P40 RxD ExDREQ P41 TxD ExDACK P42 SCLK ExTC P43 SRDY ExA1 P50 INTo P52 INT1 P51 CNTRo P53 P57 Port P5 P60 P63 Input output individual bits CMOS compatible input level CMOS 3 state output Key on wake up Port PO pull up control register CMOS compatible input level CMOS 3 state output Power source is VccE A D conversion input External bus interface funciton I O AD control register EXB control register CMOS compatible input level CMOS 3 state output CMOS compatible input level CMOS 3 state output Power source is VecE External bus interface funciton output EXB control register External bus interface funciton input EXB control register Serial I O input External bus interface funciton output Serial I O control register EXB control register Serial I O output External bus interface funciton input Serial I O control register EXB control register Serial I O 1 0 External bus interface funciton input Serial I O control register EXB control register
124. port D1 D1 USB difference amplifier OFF Full speed port D1 D1 USB difference amplifier ON Low speed port D1 D1 USB difference amplifier ON 0 Downstream port 2 function select bit USB port D2 D2 OFF USB difference amplifier OFF USB exclusive input port D2 D2 USB difference amplifier OFF Full speed port D2 D2 USB difference amplifier ON Low speed port D2 D2 USB difference amplifier ON Write 0 when writing 0 is read when reading Fig 102 Structure of Downstream port control register Rev 2 00 Oct15 2006 page 69 of 130 REJ09B0338 0200 2tENESAS State remaining 38K2 Group EXTERNAL BUS INTERFACE EXB The external bus interface EXB controls the data transfer be tween the external MCU and the 38K2 group s CPU or its HARDWARE FUNCTIONAL DESCRIPTION memory multichannel RAM The external bus interface is shown below 38K2 group CPU channel a type External MCU Memory channel Direct RAM access type ss ee ae bus interface _ i H H USB bus datas Ea perme L EXB Multichannel RAM USB USB host Fig 103 External bus interface CPU channel It is a data transfer course by the interrupt processing between the external MCU and the 38K2 group s CPU Memory channel It is a data transfer course
125. read out from this buffer register At writing A data is written to the transmit buffer register At reading The contents of the receive buffer register are read out Note The contents of transmit buffer register cannot be read out The data cannot be written to the receive buffer reaister Fig 2 4 2 Structure of Transmit Receive buffer register Serial I O status register b7 b6 b5 b4 b3 b2 b1 bO Serial I O status register SIOSTS Address 2716 Name ee n ee Bw Bl buffer empty flag T Buffer full TBE Buffer empty Receive buffer full flag RBF i Buffer empty Buffer full Transmit shift register shift T Transmit shift in progress ae flag TSC 1 Transmit shift completed 3 Overrun error flag OE 0 No error 1 Overrun error Parity error flag PE 7 No error miu Parity error Framing error flag FE A No error Framing error 7 Summing error flag SE 0 U PE U U FE 0 ace 7 Nothing is allocated for this bit er isa T I bit 1 x When this bit is read out the contents are 1 Fig 2 4 3 Structure of Serial I O status register Rev 2 00 Oct15 2006 page 41 of 112 RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Serial I O control register b7 b6 b5 b4 b3 b2 bi bO Serial I O control register SIOCON Address OFE016 B Name Function At esee R WI BRG count source 0 System clock selection bit CSS 1 System clock 4 S
126. register Address OFE016 is set to 0 a value of mis 1 When bit 0 of the Serial I O control register Address OFE016 is set to 1 a value of m is 4 Fig 2 4 31 Registers setting related to transmitting side Rev 2 00 Oct 15 2006 page 62 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Receiving side Serial I O status register Address 2716 b7 bO SIOSTS Receive buffer full flag Confirm completion of receiving 1 byte data with this flag 1 At completing reception 0 At reading out contents of Receive buffer register Overrun error flag 1 When data is ready in Receive shift register while Receive buffer register contains the data Parity error flag 1 When a parity error occurs in enabled parity gt Framing error flag 1 When stop bits cannot be detected at the specified timing gt Summing error flag 1 When any one of the following errors occurs e Overrun error e Parity error e Framing error Serial I O control register Address OFE016 b bO secon i olo o o o BRG count source selection bit f Xin Serial I O synchronous clock selection bit BRG 16 Sroy output enable bit Sroy out disabled Transmit enable bit Transmit disabled gt Receive enable bit Receive enabled gt Serial I O mode selection bit Asynchronous serial I O UART gt Serial I O enable bit Serial I O enabled
127. resistors and capacitors Make sure the USB D D lines do not cross any other wires Keep a large GND area to protect the USB lines Also make sure you use a USB specification compliant connecter for the connec tion USBVREF pin Treatment Noise Elimination Connect a capacitor between the USBVREF pin and the Vss pin The capacitor should have a 2 2 uF capacitor electrolytic capaci tor and a 0 1 uF capacitor ceramic type capacitor connected in parallel eIn Vcc 3 0 to 3 6 V operation connect the USBVREF pin directly to the Vcc pin in order to supply power to the USB port circuit In addition you will need to disable the built in USB reference volt age circuit in this operation set bit 4 of the USB control register to O If you are using the bus powered supply in this condition the DC DC converter must be placed outside the MCU eIn Vcc 4 00 to 5 25 V operation do not connect the external DC DC converter to the USBVREF pin Use the built in USB refer ence voltage circuit Rev 2 00 Oct15 2006 page 128 of 130 REJ09B0338 0200 HARDWARE NOTES ON USAGE DATA REQUIRED FOR MASK ORDERS USB Communication In applications requiring high reliability we recommend providing the system with protective measures such as USB function initial ization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly for example due to external causes such as noise Flash Memory Version
128. set T This instruction stores the contents of A in M The contents of A does not change his instruction resets the oscillation control F F and the oscillation stops Reset or interrupt input is needed to wake up from this mode This instruction stores the contents of X in M The contents of X does not change his instruction stores the contents of Y in M The contents of Y does not change This instruction stores the contents of A in X The contents of A does not change This instruction stores the contents of A in Y The contents of A does not change his instruction tests whether the contents of M are 0 or not and modifies the N and Z his instruction transfers the contents of S in X This instruction stores the contents of X in A his instruction stores the contents of X in S his instruction stores the contents of Y in A he WIT instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped CPU starts its function after the Timer X over flows comes to the terminal count All regis ters or internal memory contents except Timer X will not change during this mode Of course needs VDD Notes 1 The number of cycles n is increased by 3 when T is 1 2 The numbe
129. setting corresponding to Figure 2 2 13 Port PO direction register address 01 16 b0 b7 pop a falala olofo gt Bits corresponding to P07 to POo 0 Input port 1 Output port Port PO pull up control register address OF F016 b7 bO puo dala POo to P03 pull up Interrupt request register 2 address 3D1e6 b0 b7 mea fof gt Key on wake up interrupt request Interrupt control register 2 address 3F 16 b7 bO cone fof at TL gt Key on wake up interrupt Enabled Fig 2 2 14 Registers setting related to key input interrupt corresponding to Figure 2 2 13 Rev 2 00 Oct 15 2006 page 20 of 112 7tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 2 Interrupt 2 2 8 Notes on interrupts 1 Change of relevant register settings When the setting of the following registers or bits is changed the interrupt request bit may be set to 1 When not requiring the interrupt occurrence synchronized with these setting take the following sequence Interrupt edge selection register address OFF316 Timer X mode register address 2316 Set the above listed registers or bits as the following sequence Set the corresponding interrupt enable bit to 0 disabled l Set the interrupt edge select bit active edge switch bit or the interrupt source select bit to 1 NOP One or more instructions Set the corresponding interrupt request bit to 0 no interrupt r
130. setting the related registers as shown in Figure 2 4 26 the slave unit becomes the state where a synchronous clock can be received at any time and the serial I O receive interrupt request bit is set to 1 each time an 8 bit synchronous clock is received In the serial I O receive interrupt processing routine the data to be transmitted next is written to the transmit buffer register after the received data is read out However if no serial I O receive interrupt occurs for a certain time heading adjustment time or more the following processing will be performed 1 The first 1 byte data of the transmission data in the block is written into the transmit buffer register 2 The data to be received next is processed as the first 1 byte of the received data in the block Figure 2 4 28 shows a control procedure of the slave unit using the serial I O receive interrupt and any timer interrupt for heading adjustment Serial I O receive interrupt Timer interrupt processing processing routine routine CLT Note 1 i CLT Note 1 CLD Note 2 Push the register used in the CLD Note 2 Push the register used in Push register to stack interrupt processing routine into Push register to stack the interrupt processing the stack routine into the stack Confirmation of the received byte counter to judge the l Within a block block transfer term Heading adjustment counter 1 transfer term Heading adjustment Read a reception data counte
131. software but 1 cannot be set Write 0 when writing 0 is read when reading Fig 3 4 60 Structure of DP2 interrupt source register Rev 2 00 Oct15 2006 page 63 of 99 REJ09B0338 0200 RENESAS State remaining APPENDIX 38K2 Group 3 4 List of registers DP1 control register DP1CON address 002C16 Bit symbol Bit name Function At reset H W S W DSCONN1 Downs ream port 1 connect bit Disconnect PTCON1 interrupt enabled Connect PTDIS1 interrupt enabled 0 DSPTEN1 Downs ream port 1 enable bit Downstream port 1 disabled Downstream port 1 enabled This bit is cleared when an interrupt of PTDIS1 or PTERR1 is generated DSSUSP1 ream port 1 suspend bit No port suspended Port suspended This bit is cleared when an interrupt of PTDIS1 or PTRSM1 is generated DSDETE1 Downs ream port 1 connect state detection enable bit Connect disconnect state detection disabled PTCON1 and PTDIS1 interrupts disabled Connect disconnect state detection enabled This bit is cleared when an interrupt of PTCON1 PTDIS1 or PTERR1 is generated DSRSTO1 Downs ream port 1 SEO signal transmit bit Being not output SEO signal being output DSRSMO1 Downs signal t ream port 1 resume ransmit bit Being not output K signal being output When w
132. the notes related to the timers 2 3 1 Memory map ONY Ww 002016 002116 002216 002316 002416 002516 Timer X TX 003C16 Interrupt request register 1 IREQ1 003D16 Interrupt request register 2 IREQ2 003E16 Interrupt control register 1 ICON1 003F16 Interrupt control register 2 ICON2 Fig 2 3 1 Memory map of registers related to timers 2 3 2 Related registers Prescaler 12 Prescaler X b7 b6 b5 b4 b3 b2 bi bO Prescaler 12 PRE12 Address 2016 Prescaler X PREX Address 2416 Set a count value of each prescaler eThe value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time When this register is read out the count value of the corres ponding prescaler is read out Fig 2 3 2 Structure of Prescaler 12 Prescaler X Rev 2 00 Oct 15 2006 page 23 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 3 Timer Timer 1 b7 b6 b5 b4 b3 b2 b1 bO Timer 1 T1 Address 2116 Set a count value of timer 1 eThe value set in this register is written to both timer 1 and timer 1 latch at the same time When this register is read out the timer 1 s count value is read out Fig 2 3 3 Structure of Timer 1 Timer 2 Timer X b7 b6 b5 b4 b3 b2 b1 bO Timer 2 T2 Address 2216 Timer X TX Address 2516 Set a count value of each timer ee The value set in this register is written to both each timer a
133. the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different type numbers implement a system evaluation test for each of the products BEFORE USING THIS MANUAL This user s manual consists of the following three chapters Refer to the chapter appropriate to your conditions such as hardware design or software development Chapter 3 also includes necessary information for systems development You must refer to that chapter 1 Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function CHAPTER 2 APPLICATI
134. to O Definition Ready Busy SR6 bit6 Reserved SR5 bit5 Erase status Terminated in error Terminated normally SR4 bit4 Program status Terminated in error Terminated normally Reserved SR2 bit2 Reserved SR1 bit1 Reserved SRO bitO Reserved SRB bit3 Rev 2 00 Oct15 2006 page 122 of 130 REJ09B0338 0200 7RENESAS 38K2 Group Status Register 1 SRD1 The status register 1 indicates the status of serial communica tions results from ID checks and results from check sum comparisons It can be read after the SRD by writing the read sta tus register command 7016 Also status register 1 is cleared by writing the clear status register command 5016 Table 15 lists the definition of each status register 1 bit This regis ter becomes 0016 when power is turned on and the flag status is maintained even after the reset Table 15 Status register 1 SRD1 HARDWARE FUNCTIONAL DESCRIPTION Boot update completed bit SR15 This flag indicates whether the control program was downloaded to the RAM or not using the download function eCheck sum consistency bit SR12 This flag indicates whether the check sum matches or not when a program is downloaded for execution using the download func tion ID check completed bits SR11 and SR10 These flags indicate the result of ID checks Some commands cannot be accept
135. when reading Transfer type bite 0 Transfer disabled 1 Interrupt transfer Fig 3 4 17 Structure of EP11 set register b7 bO fofofofofofo EPOO control register 1 EPOOCON1 address 001A16 e remaining Bit symbol Bit name Function At reset H W S W PIDOO 1 0 Response PID bit b1 bO 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of control transfer error B1 is set to 1 by the hardware At reception of SETUP token B1 and b0 are cleared to 0 by the hardware 0 p Not used Write 0 when writing 0 is read when reading Fig 3 4 18 Structure of EP00 control register 1 Rev 2 00 Oct15 2006 page 45 of 99 REJ09B0338 0200 RENESAS State remaining APPENDIX 38K2 Group 3 4 List of registers b7 bo fofofofofofo EP01 control register 1 EPO1CON1 address 001A16 Bit symbol Bit name Function At reset H W S W PIDO1 Response PID bit b1 bO 0 1 0 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of over max packet size B1 is set to 1 by the hardware Not used Write 0 when writing 0 is read when reading State remaining Fig 3 4 19 Structure of EP01 control register 1 b7 bo fofofofofofo EP0
136. written operation starts main sequencer starts and an internal memory access sequence which synchronized with a rise of is activated A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer TXBUF The memory address counter is simultaneously increased and assertion of the memory channel request is made When the external MCU bus is in the condition of ExCS L and ExA0 L or a fall of ExRD is detected in the condition of ExDACK L negation of the memory channel request which synchronized with a rise of o is made When a rise of ExRD is detected an internal memory access sequence which synchronized with a rise of is activated A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer TXBUF The memory address counter is simultaneously increased and assertion of the memory channel request is made When the read operation from the end address has been completed the transition to the status to wait the memory channel operation end occurs When a rise of ExRD is detected the memory channel operation sequence ends and the memory channel operation end interrupt is generated nel tranmitting operation 1 Rev 2 00 Oct15 2006 page 87 of 130 REJ09B0338 0200 2RENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION 7 Memory Channel Transmitting Operation 2 Burst
137. written to STP instruction disable bit STP instruction Watchdog timer H count source selection bit Reset circuit Internal reset RESET O da gt Fig 135 Block diagram of Watchdog timer Watchdog timer control register WDTCON address 003916 Watchdog timer H for read out of high order 6 bit STP instruction disable bit 0 STP instruction enabled 1 STP instruction disabled Watchdog timer H count source selection bit 0 Watchdog timer L underflow 1 System clock 16 Fig 136 Structure of Watchdog timer control register Rev 2 00 Oct15 2006 page 93 of 130 REJ09B0338 0200 RENESAS 38K2 Group RESET CIRCUIT To reset the microcomputer RESET pin should be held at an L level for 16 cycles or more of XIN Then the RESET pin is returned to an H level the power source voltage should be between 3 0 V and 5 25 V for L version and the oscillation should be stable re HARDWARE FUNCTIONAL DESCRIPTION Power source voltage i set is released After the reset is completed the program starts OV from the address contained in address FFFD16 high order byte and address FFFC16 low order byte Make sure that the reset in put voltage is under 0 6 V for Vcc of 3 0 V L version Internal reset Address lt H Reset input voltage ov Note Reset release voltage Vcc 3 0 V L version i Power source la volta
138. ztENESAS 38K2 Group Addressing mode APPENDIX 3 6 Machine instructions Processor status register ABS ABS X ABS Y IND ZP IND IND X IND Y REL 4 3 JOP n JOP JOP n JOP n OP n JOP n OP n OP B D 4E 6 3 5E 3 ue saved in stack Rev 2 00 Oct15 2006 page 93 of 99 REJ09B0338 0200 ztENESAS APPENDIX APPENDIX 38K2 Group 3 6 Machine instructions 38K2 Group 3 6 Machine instructions Addressing mode Addressing mode Processor status register Symbol Function Details A BIT A ZP BIT ZP 6 4 3 n JOP n JOP OP n V B D SBC When T 0 When T 0 this instruction subtracts the E5 2 Note 1 A lt A M C value of M and the complement of C from A Note 5 and stores the results in A and C When T 1 When T 1 the instruction subtracts the con M X M X M C tents of M and the complement of C from the contents of M X and stores the results in M X and C A remain unchanged but status flag are changed M X represents the contents of memory where is indicated by X Ai or Mi e 1 This instruction sets the designated bit i of A or M CcC lt 1 This instruction sets C This instruction set D his instruction set I his instruction
139. 0 control register 2 0 ececceeeeeeeeeeeeeeeeeeeeeeeaeeeseneeessaeeeseeeeseaees 49 3 4 29 Structure of EP11 control register 2 0 cece cceseeceeee sees eeeeeeeeeeaeeeseneeeseaeeeseeeeeeaes 49 3 4 30 Structure of EPOO control register 3 oo eccceeeeeceeeeeeeeeeeeeeeeeaeeeseeeeeseeeeseeeeesaees 49 3 4 31 Structure of EPO1 control register 3 oo eee cseeeeceeeeeeeeeeeeeeeeeseaeeeeeeeeeseaeeeseaeessaees 50 3 4 32 Structure of EP02 control register 3 oo eee ceceeececeee cess eeeeeeeeseaeeeeeeeeeseaeeeeeaeessaees 50 3 4 33 Structure of EP03 control register 3 oo cece ceeeeceeeeeeeeeeeeeeeeeeeaeeeseeeeeseeeeseaeeseaees 50 3 4 34 Structure of EP10 control register 3 oo ceceeceeeeeeeeeeeeeeeeeeeeeeaeeeseeeeeseaeeeseeeeesaees 51 3 4 35 Structure of EPOO interrupt source register cecccecceeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeteaees 51 3 4 36 Structure of EP01 interrupt source register cece cecceteeeeeeeeeeeeeeeeeeeeseeeseeeeteaees 52 3 4 37 Structure of EP02 interrupt source register ceccceeceeeeeeeeeeeeeeeeeeeeeeeteeeeeeeeeeeaees 52 3 4 38 Structure of EP03 interrupt source register ceecceceeeeeseeeeeeeeeeeeeeeeeseeeeeeeeeseaees 53 3 4 39 Structure of EP10 interrupt source register cece cecseeeeeeeeeeeeeeeeeeeseeeseeeeeeeeeteaees 54 3 4 40 Structure of EP11 interrupt source register cece cee seseeeeeeeeeeeeeeeseeeeeeeeeeeeeeeeeaees 54 3 4 41 Structure of EPOO byte number register 0 cccceeeceeeeeee
140. 016 before executing these commands Fig 151 Full status check flowchart and remedial procedure for errors Rev 2 00 Oct 15 2006 page 108 of 130 7RENESAS REJ09B0338 0200 38K2 Group Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily this MCU incorporates a ROM code protect function for use in parallel I O mode and an ID code check func tion for use in standard serial I O mode ROM Code Protect Function The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control register address FFDB16 in paral lel I O mode Figure 152 shows the ROM code protect control register address FFDB16 This address exists in the User ROM area bO HARDWARE FUNCTIONAL DESCRIPTION If one or both of the pair of ROM Code Protect Bits is set to 0 the ROM code protect is turned on so that the contents of internal flash memory are protected against readout and modification The ROM code protect is implemented in two levels If level 2 is se lected the flash memory is protected even against readout by a shipment inspection LSI tester etc When an attempt is made to select both level 1 and level 2 level 2 is selected by default If both of the two ROM Code Protect Reset Bits are set to 00 the ROM code protect is turned off so that the contents o
141. 0200 Transmit buffer empty flag TBE Transmit shift register shift completion flag TSC Not used returns 1 when read L Character length selection bit CHAS Stop bit length selection bit STPS 2RENESAS HARDWARE FUNCTIONAL DESCRIPTION o Serial I O control register SIOCON address OFE016 BRG count source selection bit CSS 0 System clock 1 System clock 4 Serial I O synchronous clock selection bit SCS 0 BRG output divided by 4 when clock synchronous serial I O is selected BRG output divided by 16 when UART is selected External clock input when clock synchronous serial I O is selected External clock input divided by 16 when UART is selected Srpy output enable bit SRDY 0 P43 pin operates as ordinary I O pin 1 P43 pin operates as Sarpy output pin Transmit interrupt source selection bit TIC 0 Interrupt when transmit buffer has emptied 1 Interrupt when transmit shift operation is completed Transmit enable bit TE 0 Transmit disabled 1 Transmit enabled Receive enable bit RE 0 Receive disabled 1 Receive enabled Serial I O mode selection bit SIOM 0 Asynchronous serial I O UART 1 Clock synchronous serial I O Serial I O enable bit SIOE 0 Serial I O disabled pins P4o P43 operate as ordinary I O pins 1 Serial I O enabled pins P4o P43 can operate as serial I O pins 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION USB FUNCTION 3
142. 1 when the buffer 1 is ready state enabled to be read written on USB function Endpoint 1 in double buffer mode 0 can be set by software but 1 cannot be set USB function Endpoint 1 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when STALL response occurs on USB function Endpoint 1 0 can be set by software but 1 cannot be set Fig 51 Structure of EP01 interrupt source Rev 2 00 Oct15 2006 page 42 of 130 REJ09B0338 0200 Not used Write 0 when writing 0 is read when reading register 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION EP01 byte number register 0 EP01BYTO address 001E16 At reset H W BOBYTO1 IN Transmit byte number bit Single buffer mode Set the transmitting byte number 0 6 0 Double buffer mode Set the transmitting byte number of buffer 0 OUT Receive byte number bit Single buffer mode The received byte number is automatically set Double buffer mode The received byte number of buffer 0 is automatically set Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 52 Structure of EP01 byte number register 0 EP01 byte number register 1 EP01BYT1 address 001F 16 At reset H W BiBYTO1 IN Transmit byte
143. 1 Interrupt request issued O Serial I O transmit 0 No interrupt request issued I 3 OI interrupt request bit 1 Interrupt request issued I 4 CNTRo interrupt 0 No interrupt request issued l request bit 1 Interrupt request issued O 5 Key on wake up 0 No interrupt request issued Ol we interrupt request bit 1 Interrupt request issued I A D conversion 0 No interrupt request issued 7 interrupt request bit 1 Interrupt request issued mas G I Nothing is arranged for this bits This is a write disabled bit 7 When this bit is read out the contents are 0 OQ can be set by software but 1 cannot be set Fig 2 8 5 Structure of Interrupt request register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 bO Ce eee i Interrupt control register 2 ICON2 Address 3F 16 B Name Function _ resa RNW INT1 interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 4 USB HUB interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 2 Serial I O receive 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 4 CNTRo interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 5 Key on wake up Interrupt disabled interrupt enable bit Interrupt enabled 3 Serial I O transmit 0 Interrupt disabled i interrupt enable bit 1 Interrupt enabled i A D conversion Interrupt disabled interrupt enable bit Interrupt enabled 7 Fix this bitto
144. 1 2 to 1 2048 of the internal clock or an external clock Serial output TxD Serial input RxD Write signal to receive transmit buffer register address 002616 RBF 1 TSC 1 Overrun error OE detection The transmit interrupt Tl can be generated either when the transmit buffer register has emptied TBE 1 or after the transmit shift operation has ended TSC 1 by setting the transmit interrupt source selection bit TIC of the serial I O1 control register If data is written to the transmit buffer register when TSC 0 the transmit clock is generated continuously and serial data is output continuously from the TxD pin The receive interrupt RI is set when the receive buffer full flag RBF becomes 1 Fig 19 Operation of clock synchronous serial I O function Rev 2 00 Oct 15 2006 page 22 of 130 2RENESAS REJ09B0338 0200 38K2 Group 2 Asynchronous Serial I O UART Mode Clock asynchronous serial I O mode UART can be selected by setting the serial I O mode selection bit of the serial I O control register to 0 Eight serial data transfer formats can be selected and the transfer formats used by a transmitter and receiver must be identical The transmit and receive shift registers each have a buffer regis HARDWARE FUNCTIONAL DESCRIPTION ter but the two buffers have the same address in memory Since the shift register cannot be written to or read from directly transmit data is written to the
145. 16 BORDY01 BORDY11 032016 B1RDY01 Fig 28 Examples of interrupt source dependant buffer area offset address Rev 2 00 Oct15 2006 page 29 of 130 RENESAS REJ09B0338 0200 38K2 Group USB Interrupt Function HARDWARE FUNCTIONAL DESCRIPTION USB Interrupt Control Circuit USBINTCON has 3 requests and 22 USB device interrupt request sources Each interrupt source register enables the user to easily determine which interrupt has occurred Table 7 shows the list of USB interrupt sources Table 7 USB interrupt sources Interrupt request bit USB interrupt bit IREQ1 Address 003C16 USBIREQ Address 001716 USB bus reset Interrupt source At USB bus reset signal detection After enabling the USB module USBE 1 an interrupt request occurs when 2 5 us SEO state is detected in D0 DO port Equivalent to 120 clock length when fusB 48 MHz At SOF packet receive USB SOF After enabling the USB module USBE 1 an interrupt request occurs when SOF packet is detected in D0 DO port Its occurrence does not depend on frame time or CRC value after SOF packet is transferred Normally SOF packet detection occurs only when fusB 48 MHz USB device EP00 At Endpoint 00 data transfer complete eBuffer ready read write enabled state Control transfer completed Status stage transition SETUP buffer ready read enabled state Control transfer error EP01 At Endpoint 01
146. 2 control register 1 EPO2CON1 address 001A16 Bit symbol Bit name Function At reset H W S W PIDO2 Response PID bit b1 bO 0 1 0 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of over max packet size B1 is set to 1 by the hardware Write 0 when writing 0 is read when reading State remaining Fig 3 4 20 Structure of EP02 control register 1 b7 bo fofofofofofo EPO3 control register 1 EPO3CON1 address 001A16 Bit symbol Bit name Function At reset H W S W PIDO3 Response PID bit b1 bO 0 1 0 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of over max packet size B1 is set to 1 by the hardware Write 0 when writing 0 is read when reading State remaining Fig 3 4 21 Structure of EP03 control register 1 Rev 2 00 Oct 15 2006 page 46 of 99 7tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers b7 bo fofofofofofo EP10 control register 1 EP10CON1 address 001A16 At reset H W S W PID10 1 0 Response PID bit b1 b0 0 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of control transfer error B1 is set to 1 by the hardware At reception of SETUP token B1 and b0 are cleared to 0 by th
147. 2006 page 52 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 2 Output of serial data control of peripheral IC Outline 4 byte data is transmitted and received using the clock synchronous serial I O The CS signal is output to a peripheral IC through port P5s The example for using Serial I O is shown Figure 2 4 19 shows a connection diagram and Figure 2 4 20 shows a timing chart 38K2 group Peripheral IC Example for using Serial I O Fig 2 4 19 Connection diagram Specifications The Serial I O is used clock synchronous serial I O is selected e Synchronous clock frequency 125 kHz f Xin 6 MHz is divided by 48 e Transfer direction LSB first e The Serial I O interrupt is not used e Port P5s is connected to the CS pin L active of the peripheral IC for transmission control the output level of port P5s is controlled by software Fig 2 4 20 Timing chart Rev 2 00 Oct 15 2006 page 53 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Figure 2 4 21 shows registers setting related to Serial I O and Figure 2 4 22 shows a setting of serial I O transmission data Serial I O control register Address OFE016 b7 bO socon 1 1Jo 1 1Jo o o ___ BRG count source selection bit f Xin Serial I O synchronous clock selection bit BRG 4 Sroy output enable bit SRpy output disabled Transmit interrupt source selection bit Transmit shift operat
148. 3 22 shows the control procedure Timer X interrupt Fixed Prescaler X Timer X request bit f XIN 6 MHz 1 16 1 256 1 256 175 ms 0 No interrupt request issued 1 Interrupt request issued Fig 2 3 20 Timers connection and setting of division ratios Rev 2 00 Oct 15 2006 page 36 of 112 7tENESAS REJ09B0338 0200 38K2 Group Timer X mode register address 2316 b7 bo m bhh Timer X operating mode Pulse width measurement mode CNTRo active edge selection H level width measurement Timer X count Stop Clear to 0 when starting count Prescaler X address 2416 b7 bO Timer X address 2516 Set division ratio 1 b7 b0 Interrupt control register 1 address 3E16 b7 bO cor f gt Timer X interrupt Enabled Interrupt request register 1 address 3C16 b7 bO a ol I gt Timer X interrupt request Set to 1 automatically when Timer X underflows Interrupt control register 2 address 3F 16 b7 bO conz j CNTRo interrupt Enabled Interrupt request register 2 address 3D16 b0 b7 ezl fol I er CNTRo interrupt request Set to 1 automatically when H level input came to the end Fig 2 3 21 Related registers setting Rev 2 00 Oct 15 2006 page 37 of 112 2tENESAS REJ09B0338 0200 APPLICATION 2 3 Timer APPLICATION 38K2 Group 2 3 Timer RESET Initialization All interrupts disabled x This bit i
149. 3 Timer 2 3 4 Notes on timer If a value n between 0 and 255 is written to a timer latch the frequency division ratio is 1 n 1 When switching the count source by the timer X count source selection bit the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals Therefore select the timer count source before set the value to the prescaler and the timer Rev 2 00 Oct 15 2006 page 39 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 2 4 Serial I O This paragraph explains the registers setting method and the notes related to the Serial I O 2 4 1 Memory map fw fw 002616 Transmit Receive buffer register TB RB 002716 Serial I O status register SIOSTS ww fw 003D16 Interrupt request register 2 IREQ2 w N 003F16 Interrupt control register 2 ICON2 w Ww OFE016 Serial I O control register SIOCON OFE116 UART control register UARTCON OFE216 Baud rate generator BRG Tw OFF316 Interrupt edge selection register INTEDGE N N T Fig 2 4 1 Memory map of registers related to Serial I O Rev 2 00 Oct15 2006 page 40 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 2 4 2 Related registers Transmit Receive buffer register b7 b6 b5 b4 b3 b2 bi bO Transmit Receive buffer register TB RB Address 2616 The transmission data is written to or the receive data is
150. 38K2 Group 2 2 Interrupt 2 2 Interrupt This paragraph explains the registers setting method and the notes related to the interrupt 2 2 1 Memory map 003C16 Interrupt request register 1 IREQ1 003D16 Interrupt request register 2 IREQ2 003E16 Interrupt control register 1 ICON1 i 003F16 Interrupt control register 2 ICON2 mp aL OFF316 Interrupt edge selection register INTEDGE Fig 2 2 1 Memory map of registers related to interrupt 2 2 2 Related registers Interrupt request register 1 b7 b6 b5 b4 b3 b2 bi bO Interrupt request register 1 IREQ1 Address 3C16 B Name Function At reset RiW USB bus reset 0 No interrupt request issued m l interrupt request bit 1 Interrupt request issued Oi 1 USB SOF interrupt 0 No interrupt request issued Ol request bit 1 Interrupt request issued I 2 USB device interrupt 0 No interrupt request issued request bit 1 Interrupt request issued O 3 EXB interrupt 0 No interrupt request issued Ol request bit 1 Interrupt request issued l 4 INTo interrupt 0 No interrupt request issued l request bit 1 Interrupt request issued O 5 Timer X interrupt 0 No interrupt request issued Ol request bit 1 Interrupt request issued Timer 1 interrupt 0 No interrupt request issued l request bit 1 Interrupt request issued Olx Timer 2 interrupt 0 No interrupt request issued o request bit 1 Interrupt request issued 1 OQ can
151. 6 to FFFF16 are called the special page area The special page addressing mode can be used to specify memory addresses in the special page area Ac cess to this area with only 2 bytes is possible in the special page addressing mode Zero page XXXX16 OFE016 OFFF16 YYYY16 Reserved ROM area 128 bytes FF0016 FFDC16 Interrupt vector area Special page FFFE16 Reserved ROM area FFFF16 2tENESAS 38K2 Group 000016 Port PO PO 000116 Port PO direction register POD 000216 Port P1 P1 000316 Port P1 direction register P1D 000416 Port P2 P2 000516 Port P2 direction register P2D 000616 Port P3 P3 000716 Port P3 direction register P3D 000816 Port P4 P4 000A16 Port P5 P5 000B16 Port P5 direction register P5D 000C16 Port P6 P6 000E16 Reserved Note 000916 Port P4 direction register P4D 000D16 001016 USB control register USBCON 001116 001316 USB HUB address register USBA1 001416 Frame number register Low FNUML 001516 Frame number register High FNUMH 001616 USB interrupt source enable register USBICON 001716 USB interrupt source register USBIREQ 001816 Endpoint index register USBINDEX _ 001916 Endpoint field register 1 EPXXREG1 001A16 Endpoint field register 2 EPXXREG2 e 001B16 Endpoint field register 3 EPXXREG3 001C16 Endpoint field register 4 EPXXREG4 001D16 Endpoint field register 5
152. 8K2 Group HUB FUNCTION The 38K2 Group has a HUB Function Control Circuit HUBFCC that offers easy implementation of USB hub functions signal re peat and bus state detection This circuit is in compliance with USB Specification Version 2 0 Full Speed Low Speed Transfer Modes 12 Mbps 1 5 Mbps equivalent to Version 1 1 The HUBFCC operates with two external down ports and one in ternal down port which is utilized by the USB addresses of the built in peripherals enabling management of a total of three down ports independently A dedicated circuit automatically performs the bus state change detection and error detection needed for the sequence manage ment of the hub repeater circuit data repeat function and down port status management This dedicated control circuit en sures the user easy development of a program or timing design 38K2 Group External down port USB device USB device Fig 87 HUB functions Rev 2 00 Oct15 2006 page 58 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Each down port register can be controlled by USB commands us ing USB addresses for HUB functions or detecting changes in the bus state of down ports The HUBFCC is also equipped with a re mote wakeup signal transfer function for use during global resume as other special signals management The HUBFCC generates an interrupt to the CPU when detecting a down port state change 1 vector 10 sources The flexibility of the indis
153. 8K2 Group Software Commands Table 13 lists software commands In standard serial I O mode erase program and read are controlled by transferring software commands via the RxD pin Software commands are explained Table 13 Software commands Standard serial I O mode Control command 1st byte transfer Page read 2nd byte Address middle 3rd byte Address high HARDWARE FUNCTIONAL DESCRIPTION here below Basically the software commands of the standard se rial I O mode are the same as that of the parallel I O mode but the block erase function is excluded and 4 commands are added ID check download version data output and Boot ROM area output functions 4th byte 5th byte 6th byte Data output to 259th byte When ID is not verified Not acceptable Page program Address middle Address high Data input to 259th byte Not acceptable Erase all blocks D016 Not acceptable Read status register SRD output SRD1 output Acceptable Clear status register Not acceptable ID check function Address low Address middle Address high ID size Acceptable Download function Size low Size high Check sum Data input To required number of times Not acceptable Version data output function Version data output Version data output Version data output Version data output Version data o
154. 8K2 Group is equipped with a USB function control circuit USBFCC that enables effective interfacing with the host PC This circuit is in compliance with USB2 0 s Full Speed Transfer Mode 12 Mbps equivalent to USB1 1 This circuit also supports all four transfer types specified in the standard USB specification The USBFCC has two USB addresses and 6 endpoints enabling separate control of the HUB functions and peripheral functions The USB address for HUB functions is equipped with two end points Each endpoint is fixed to a specified transfer type Endpoint 0 is fixed to Control Transfer and Endpoint 1 is fixed to Interrupt Transfer The USB address for peripheral functions is equipped with four endpoints that can select its transfer type Although Endpoint 0 is fixed to Control Transfer the Endpoints 1 to 3 can be set to Inter rupt Transfer Bulk Transfer or Isochronous Transfer A dedicated circuit automatically performs stage management for Control Transfer and packet management for transactions which are necessary for matching of data transmit receive timing error detection and retry after error This dedicated control circuit en ables the user to develop a program or timing design very easily Each endpoint can be programmed for data transfer conditions so that the endpoints are adaptive for all USB device class transfer systems The data buffer of each endpoint can be assigned to any area in the multi channel RAM This feature o
155. 9 Watchdog timer CPU mode register by be bb bbs be bt bp CPU mode register ihl CPUM address 3B16 BT Nae J Funcion p 1 1 a b1 b a Processor mode bits 0 0 Single chip mode 0 1 Not available 1 1 0 Not available Not available i Stack page selection bit 0 page 1 1 page Fix this bit to 1 Epe i Fix this bit to 0 ae fal System clock selection bit A Main clock f Xin SYN System clock division ratio selection bits lon N o D system clock 8 8 divide mode system clock 4 4 divide mode system clock 2 2 divide mode system clock Through mode PERE mE FTO tou oil h h h h ANAN sece The initial value of bit 1 depends on the CNVss level Fig 2 9 3 Structure of CPU mode register Rev 2 00 Oct15 2006 page 79 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 9 Watchdog timer 2 9 3 Watchdog timer application examples 1 Detection of program runaway Outline If program runaway occurs let the microcomputer reset using the internal timer for detection of program runaway Specifications An underflow of watchdog timer H is judged to be program runaway and the microcomputer is returned to the reset status Before the watchdog timer H underflows 0 is set into bit 7 of the watchdog timer control register at every cycle in a main routine Through mode is used as a system clock division ratio eAn underflow signal of the wa
156. A Fig 2 8 2 Structure of AD control register Rev 2 00 Oct15 2006 page 72 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 8 A D converter AD conversion register 1 b7 b6 b5 b4 b3 b2 bi bO AD conversion register 1 AD1 Address 3716 The read only register in which the AD conversion s results are stored lt 8 bit read gt b7 bO ES Ee Edel lt 10 bit read gt b7 bO sso oo e Fig 2 8 3 Structure of AD conversion register 1 AD conversion register 2 b7 b6 b5 b4 b3 b2 b1 bO o M AD conversion register 2 AD2 Address 38 16 The read only register in which the AD conversion s results are stored lt 10 bit read gt b7 bO o D e Nothing is allocated for these bits These are write disabled bits When these bits are read out the contents are 0 a Fix this bit to O Ge Fig 2 8 4 Structure of AD conversion register 2 Rev 2 00 Oct 15 2006 page 73 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 8 A D converter Interrupt request register 2 b7 b6 b5 b4 b3 b2 bi bO Interrupt request register 2 IREQ2 Address 3D16 B Name Function INT1 interrupt 0 No interrupt request issued Ve l request bit 1 Interrupt request issued O 1 USB HUB interrupt 0 No interrupt request issued olx request bit 1 Interrupt request issued i 2 Serial I O receive 0 No interrupt request issued Ve interrupt request bit
157. ACK R ExDACK setup time for read tsu ACK W ExDACK setup time for write th R ACK ExDACK hold time for read th W ACK ExDACK hold time for write Read H pulse width Read L pulse width Write H pulse width Write L pulse width ExDACK H pulse width twL ACK ExDACK L pulse width tsu D W Data input setup time before write 60 th W D Data input hold time after write 0 tsu D ACK Data input setup time before ExDACK 80 th ACK W Data input hold time after ExDACK 10 tc CPU clock cycle time 166 tw cycle Rev 2 00 Oct15 2006 page 10 of 99 REJ09B0338 0200 Burst mode access cycle time USB function not operating tC 3 30 USB function operating 7tENESAS tC 5 30 APPENDIX 38K2 Group 3 1 Electrical characteristics L Ver 3 1 6 Switching Characteristics L Ver Table 3 1 11 Switching characteristics 1 Vcc 4 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Symbol Parameter Min Typ tWH SCLk Serial I O clock output H pulse width tc SCLK 2 30 twL SCLk Serial I O clock output L pulse width tc SCLK 2 30 td SCLK TxD Serial I O output delay time tv SCLK TxD Serial I O output valid time 30 Serial I O clock output rising time Serial I O clock output falling time CMOS output rising time Note tt CMOS CMO
158. BS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to 0 by using a data transfer instruction execute one or more instructions before executing the BBC or BBS instruction Clear the interrupt request bit to O no interrupt issued NOP one or more instructions J Execute the BBC or BBS instruction Data transfer instruction LDM LDA STA STX and STY instructions Fig 3 2 2 Sequence of check of interrupt request bit E Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to 0 the value of the interrupt request bit before being cleared to 0 is read 3 2 4 Notes on timer if a value n between 0 and 255 is written to a timer latch the frequency division ratio is 1 n 1 When switching the count source by the timer 12 and X count source selection bits the value of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count input signals Therefore select the timer count source before set the value to the prescaler and the timer Rev 2 00 Oct 15 2006 page 23 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 3 2 5 Notes on serial I O 1 Notes when selecting clock synchronous serial I O Serial 1 0 Stop of transmission operation Clear the serial I O enable bit and the transmit enable bit to
159. BYT10 Transmit receive byte number bit OUT The received byte number is automatically set 0 3 0 IN Set the transmitting byte number b7 b4 Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 79 Structure of EP10 byte number register EP10 buffer area set register EP10BUF address OFED16 At reset H W S W BADD10 EP10 beginning address set bit Set the beginning address of EP10 s buffer area 0 4 0 32 byte unit b4b3b2b1b0 000 1 0 004016 006016 Bit symbol Bit name Function 030016 03E016 Not used Write 0 when writing 0 is read when reading e remaining Fig 80 Structure of EP10 buffer area set register Rev 2 00 Oct15 2006 page 55 of 130 RENESAS REJ09B0338 0200 38K2 Group 6 Endpoint 11 HARDWARE FUNCTIONAL DESCRIPTION EP11 set register EP11CFG address 001916 Bit symbol Bit name Function At reset H W b2 b0 Not used Write 0 when writing 0 is read when reading SQCL11 Sequence toggle bit clear bit 0 Toggle bit clear disabled 1 Writing 1 clears the toggle bit and DATAO is used as the next data PID 0 is always read when reading Not used Write 0 when writing 0 is read when reading Transfer direction bit 0 IN transfer
160. Bit symbol Bit name Function State remaining Fig 62 Structure of EP02 byte number register 1 EP02 MAX packet size register EPO2MAX address OFEC16 At reset H W Bit symbol Bit name Function MXPS02 Max packet size bit IN These bits are invalid 6 0 OUT Set the maximum packet size b7 Not used Write 0 when writing 0 is read when reading e remaining Fig 63 Structure of EP02 MAX packet size register Rev 2 00 Oct 15 2006 page 47 of 130 2tENESAS REJ09B0338 0200 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION EP02 buffer area set register EPO2BUF address OFED16 Bit symbol Bit name Function At reset H W S W BADDO2 4 0 EP02 beginning address set bit Set the beginning address of EP02 s buffer area 32 byte unit b4b3b2b1b0 000 1 0 004016 0001 1 006016 111 1 0 03C016 111 1 1 03E016 0 Write 0 when writing 0 is read when reading Fig 64 Structure of EP02 buffer area set register Rev 2 00 Oct15 2006 page 48 of 130 REJ09B0338 0200 7tENESAS State remaining 38K2 Group 4 Endpoint 03 HARDWARE FUNCTIONAL DESCRIPTION EPO3 set register EPO3CFG address 001916 Bit symbol Bit name Function At reset H W S W BSIZ03 Double buffer beginning address set 1
161. Buffer 0 enable bit When the selected endpoint is IN writing 1 to this bit makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 3 4 25 Structure of EP01 control register 2 b7 bO fofofofofofofo EP02 control register 2 EPO2CONZ2 address 001B16 Bit symbol Bit name Function At reset H W S W BOVALO2 Buffer 0 enable bit When the selected endpoint is IN writing 1 to this bit a makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write Not used Write 0 when writing 0 is read when reading State remaining Fig 3 4 26 Structure of EP02 control register 2 b7 bO ofofofolofo o EP03 control register 2 EPO3CON2 address 001B16 Bit symbol Bit name Function At reset H W S W BOVALO3 Buffer 0 enable bit When the selected endpoint is IN writing 1 to this bit makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT wr
162. Control Procedure ccecceeccceeceeeceeeeeeeeeaeeeeeeeeeceaeeeeeaaeecaeeeseaaeeseaeeeseaaeessaneeesaeesseneees 35 Fig 2 3 20 Timers connection and setting of division ratios eee eerie 36 Fig 2 3 21 Related registers setting cceecececceeeceeeeeeee cece eeeeeeeeeeeeeesaaeeseeeeeesaeeseeeeeessaeeeseaeees 37 Fig 2 3 22 Control Procedure cccccceecccecesceceeeeeeeeaeeeeeeeecceaeeeeeaaeecaeeeseaaessseeeseaaeessaneesesaeeseeneees 38 Fig 2 4 1 Memory map of registers related to Serial 1 O eceecceeseeceeeeeeeeeeeeeeeeeettaeeeteneeees 40 Fig 2 4 2 Structure of Transmit Receive buffer register cccccceeseeceeeeeeeeceeeeeeeeeteaeeneneees 41 Fig 2 4 3 Structure of Serial I O status register cccceceeeeseeeeceeeeeeeeseeeeeeeaeeseeeeeetaaeeneeeeens 41 Fig 2 4 4 Structure of Serial I O control register sssssssssssssiessrrsssrssrissrrissrrrssrnsssrnsssrnsstn nens 42 Fig 2 4 5 Structure of UART control register sssssssssssssssriessrsssrrtrsntsrtetrtnnstnssrnnnstnssnnsstn nenn 42 Fig 2 4 6 Structure of Baud rate generator eeceececceceeceeeeeeeeeeeeeeeeeeeeaeeseeeeeesaeeseeeeeeesaeeeneaeees 43 Fig 2 4 7 Structure of Interrupt edge selection register sssesseeseseeessisssessrrissriessrnsssrnssrnnens 43 Fig 2 4 8 Structure of Interrupt request register 2 s sss ssssssrisssisssisrsissrisssriesrrresrrnssrnnssrnsns 44 Fig 2 4 9 Structure of Interrupt control register 2 oo eee ceeseeeeee
163. D and D pins pull down with 0 V via a resistor of 15 kQ 5 2 8 L output voltage POo P07 P24 P27 P50 P57 loL 10 mA Vcc 4 00 to 5 25 V IoL 1mA L output voltage P60 P63 IOL 20 mA Vcc 4 00 to 5 25 V loL 1mA L output voltage P10 P17 P30 P37 P40 P43 IOL 10 mA VccE 4 00 to 5 25 V lol 1 mA VccE 3 00 to 5 25 V L output voltage DO DO D1 D1 D2 D2 D and D pins pull up with 3 6 V via a resistor of 1 5 kQ 5 Hysteresis CNTRo INTo INT1 Hysteresis P10 DQo P17 DQ7 P30 P32 P33 ExINT P34 ExCS P35 ExWR P36 ExRD P37 ExA0 P40 ExDREQ RxD P41 ExDACK TxD P42 ExTC SCLK P43 ExA1 SRDY Hysteresis DO DO D1 D1 D2 D2 Hysteresis RESET H input current POo P07 P24 P27 P50 P57 P60 P63 Vi Vcc Pull ups off H input current P10 P17 P30 P37 P40 P43 Vi VocE H input current RESET CNVss Vi Vcc H input current XIN Vi Vcc L input current POo P07 P24 P27 P50 P57 P60 P63 Vi Vss Pull ups off L input current P10 P17 P30 P37 P40 P43 VI VSS L input current RESET CNVss CNVss2 VI VSS L input current XIN VI VSS L input current P0Oo P07 P50 P52 Pull ups on VI VSS Vcc 4 00 to 5 25 V
164. DPXREG2 002D16 HUB port field register 3 DPXREG3 1 HUB port 1 002B16 DP1 interrupt source register DP1REQ PTCHG1 PTRSM1 PTERR1 PTCON1 PTDIS1 002C16 DP1 control register DP1CON DSLSPD1 DSRMOD1 DSRSMO1 DSRSTO1 DSDETE1 DSSUSP1 DSPTEN1 DSCONN1 002Die DP1 status register DPiSTS D1PLUS DiMINUS 2 HUB port 2 002B16 DP2 interrupt source register DP2REQ PTCHG2 PTRSM2 PTERR2 PTCON2 PTDIS2 002C16 DP2 control register DP2CON DSLSPD2 DSRMOD2 DSRSMO2 DSRSTO2 DSDETE2 DSSUSP2 DSPTEN2 DSCONN2 002D16 DP2 status register DP2STS D2PLUS D2MINUS f f OFF916 Downstream port control register PCON2 1 0 PCONT 1 0 t t Fig 92 HUB related registers Rev 2 00 Oct15 2006 page 62 of 130 7RENESAS REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION HUB Related Registers The HUB related registers are shown below b7 bo fofofofofo HUB interrupt source enable register HUBICON address 002816 At reset H W DP1E HUB downstream port 1 interrupt Interrupt disabled 0 enable bit 1 Interrupt enabled DP2E HUB downstream port 2 interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled b6 b2 Not used Write 0 when writing 0 is read when reading HRWUE HUB upstream port remote 0 Disabled wakeup output enable bit 1 Enabled Bit symbol Bit name Function
165. DWARE 38K2 Group FUNCTIONAL DESCRIPTION EXB Block Diagram The block diagram of external bus interface EXB is shown below The external bus interface EXB consists of 1 External I O interface part 2 CPU interface part 3 Internal memory interface part 4 Transmit Receive data buffer part CPU interface Configuration signal External O Index register configuration register EXB interrupt L CHW source enable register External MCU bus h p3aexcs gt gt GEU channe Decoder data selector TxB_RDY controller RxB_RDY P37 ExA0 gt gt i P36 ExRD i P35 ExWR Memory channel Memory channel control status Internal memory interface Command decoder P41 ExDACK TxD P42 ExTC SCLK P43 ExA1 SRDY mRX_enb Memory channel mTX_enb operation mode register Memory address Memory address 5 counter End address register Memory channel Request acknowledge FIFO_stt controller MRDsel Memory channel transmit buffer control P33 EXINT lt Output selector Multichannel RAM sit_sel N Transmit Receive data buffer P10 DQ0 AN0 9 Memory read data P17 DQ7 AN7 Memory write data Functions as normal ports just after reset Fig 106 Block diagram of external bus interface EXB Rev 2 00 Oct 15 2006 page 72 of 130 2RENESAS REJ09B0338 0200 38K2 Group 1 External I O Interface Part The external I O interface part consists of a
166. EE E E ET E E E 2 AlI Memory Map iden vecivtectece vedeubteevieadeuss eke Ata E E E avin eeewctineed 2 21 2 Related TEGISTONS ii cushes occas r eee E EEEE E IE EE EEEE 3 213 Handling of unused PINS inniinn anaa a Ee ANENE seine 5 2 14 Notes on input and Output PINS iseessreyersesnnkae eaa RNa EE RERNE ESEE 6 2 1 5 Termination of unused PINS 0 ceeeeeeceeeeeeeeeeeeeeeeeecaeeeeeaeeecaeeeseaaeeseeeeesaaeeseeeeeesiaeeseeneees 7 2 2 INLORFUP HE a cede enucatdebesuauedeuiveudadeaeeruudecuanmade 8 2 24 Memory Map asarana Aaa eae enna 8 22212 Rolad rogi toS cassie ccetess roe ch E 8 2 2 3 Interrupt SOUICO eiaa ep a dena eset de ade denver EAEE EA 11 2 24 INFOKTUPE Opera ON sene E Hace euwentonec ees venue et hiedeee iad beeedh eave 12 22 o Merope 11k0 Ieererrereererrer reece rer eererer ce errr rrer eecr rere err ereer centr rrerrerprerer crrtrc reer rrrererer tree 15 2 2 6 INT AMOR Pt ir e E AE EE EE 18 Rev 2 00 Oct15 2006 page 1 of 14 RENESAS REJ09B0338 0200 Table of contents 38K2 Group 2 2 7 Key INPUE interrupt oc scctesccectacdecccsces ccpeccecesdesestencudesecnesUlagenuasesaueecdeeal sevales Seageesszacapesecsnesees 19 2 2 8 Noies Of INLGMUDtS serseri aA evexsadessuvnsseseesseeiieveedxvaieaviessieseds 21 2 3 WAMGK case cs necesncteececcaet E navvanduerd estacce edutncetesyydaceterevvenneeeenduecevarsis 23 22321 MEMORY Map sirce sta va stcet ci vataeden Seve EEE E Cesaasslaavershdutawestasdincceshidiidees 23 2 3 2 Rolad TEQISTOIS cu s
167. EPO3 interrupt source register EPO3REQ address 001D16 State remaining Bit symbol Bit name Function At reset H W S W BORDY03 USB function Endpoint 3 buffer 0 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer 0 is ready state enabled to be read written on USB function Endpoint 3 0 can be set by software but 1 cannot be set 0 0 B1RDY03 USB function Endpoint 3 buffer 1 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued In single buffer mode this bit is invalid This bit is set to 1 when the buffer 1 is ready state enabled to be read written on USB function Endpoint 3 in double buffer mode 0 can be set by software but 1 cannot be set USB function Endpoint 3 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when STALL response occurs on USB function Endpoint 3 0 can be set by software but 1 cannot be set Fig 69 Structure of EP03 interrupt source Rev 2 00 Oct15 2006 page 50 of 130 REJ09B0338 0200 Not used Write 0 when writing 0 is read when reading register 2RENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION EP03 byte number register 0 EPO3BYTO address 001E16
168. ES ON PROGRAMMING Non linearity error This means a deviation from the line between VoT and VFST of a converted value between VOT and VFST Differential non linearity error This means a deviation from the input potential difference re quired to change a converted value between VoT and VEST by 1 LSB of the 1 LSB at the relative accuracy Absolute accuracy This means a deviation from the ideal characteristics between 0 to VREF of actual A D conversion characteristics Full scale transition voltage VFST 1023 1022 Differential non linearity error b a LSB c Non linearity error gt Actual A D conversion characteristics a 1LSB at relative accuracy b Vn 1 Vn c Difference between the ideal Vn and actual Vn j ssf a Ideal line of A D conversion between Vo to Vi022 Zero transition voltage VoT Fig 167 Definition of A D conversion accuracy V1022 VREF Analog voltage Vn Analog input voltage when the output data changes from n to n 1 n 0 to 1022 Vest Vor e 1 LSB at relative accuracy gt oz V VREF e 1 LSB at absolute accuracy gt 027 V Rev 2 00 Oct15 2006 page 127 of 130 2tENESAS REJ09B0338 0200 38K2 Group NOTES ON USAGE Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions the microcomputer does no
169. Group flash memory version 2 The Boot ROM area has had a standard serial I O mode control program stored in it when shipped from the factory This Boot ROM area can be re written in only parallel I O mode Rev 2 00 Oct15 2006 page 100 of 130 REJ09B0338 0200 2RENESAS 38K2 Group 1 CPU Rewrite Mode In CPU rewrite mode the internal flash memory can be operated on read program or erase under control of the Central Process ing Unit CPU In CPU rewrite mode only the User ROM area shown in Figure 146 can be rewritten the Boot ROM area cannot be rewritten Make sure the program and block erase commands are issued for only the User ROM area and each block area The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area In the CPU rewrite mode because the flash memory cannot be read from the CPU the rewrite con trol program must be transferred to internal RAM area to be executed before it can be executed User ROM area 800016 Block 1 32 Kbytes FFFF16 HARDWARE FUNCTIONAL DESCRIPTION Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I O mode beforehand If the control program is written into the Boot ROM area the stan dard serial I O mode becomes unusable See Figure 146 for details about the Boot ROM area Normal microcomputer mode is entered when the microcomputer is reset with p
170. HUB interrupt sources Interrupt request bit IREQ2 Address 003D16 HUBIREQ Address 002916 USB HUB DP1 HARDWARE FUNCTIONAL DESCRIPTION s one interrupt request consist of which can be determined r Table 8 shows the HUB inter HUB interrupt bit Interrupt source At HUB down port 1 state change detected Disconnected state detected Connected state detected Port error state detected Resume signal detected Bus state change detected DP2 DPXREG1 HUBIREQ HUBICON DP1REQ PTDIS1 PTCON1 At HUB down port 2 state change detected Disconnected state detected Connected state detected Port error state detected Resume signal detected Bus state change detected PTERR1 PTRSM1 PTCHG1 DP2REQ PTDIS2 PTCON2 USB HUB One request PTERR2 PTRSM2 PTCHG2 Fig 91 USB HUB interrupt control Rev 2 00 Oct 15 2006 page 61 of 130 2RENESAS REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION HUB Register List The HUB register list is shown below i USB SFR Address Register Name SYMBOL bit 002816 HUB interrupt source enable register HUBICON 002916 HUB interrupt source register HUBIREQ 002A16 HUB downstream port index register HUBINDEX 002B16 HUB port field register 1 DPXREG1 002C16 HUB port field register 2
171. I O enable bit is cleared to 0 Serial I O disabled the internal transmission is running in this case since pins TxD RxD SCLK and SRDY function as I O ports the transmission data is not output When data is written to the transmit buffer register in this state data starts to be shifted to the transmit shift register When the serial I O enable bit is set to 1 at this time the data during internally shifting is output to the TxD pin and an operation failure occurs Only receive operation is stopped Clear the receive enable bit to 0 receive disabled SRDY output of reception side Serial I O When signals are output from the SRDY pin on the reception side by using an external clock in the clock synchronous serial I O mode set all of the receive enable bit the SRDY output enable bit and the transmit enable bit to 1 transmit enabled Setting serial I O control register again Serial 1 0 Set the serial I O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to 0 Clear both the transmit enable bit TE and the receive enable bit RE to 0 l Set the bits 0 to 3 and bit 6 of the serial I O control register L Can be set with the LDM instruction at the same time Set both the transmit enable bit TE and the receive enable bit RE or one of them to 1 Fig 3 2 3 Sequence of
172. IONAL DESCRIPTION USB interrupt source register USBIREQ address 001716 Bit symbol Bit name Function At reset H W S W EP00 USB function Endpoint 0 interrupt bit This bit is set to 1 when any one of EPOO interrup source register s bits at least is set to 1 This bit is cleared to 0 by clearing EPOO interrup source register to 0016 Writing to this bit causes no state change 0 0 USB function Endpoint 1 interrupt bit This bit is set to 1 when any one of EP01 interrup source register s bits at least is set to 1 This bit is cleared to 0 by clearing EP01 interrup source register to 0016 Writing to this bit causes no state change USB function Endpoint 2 interrupt bit This bit is set to 1 when any one of EP02 interrup source register s bits at least is set to 1 This bit is cleared to 0 by clearing EP02 interrup source register to 0016 Writing to this bit causes no state change USB function Endpoint 3 interrupt bit This bit is set to 1 when any one of EPO3 interrup source register s bits at least is set to 1 This bit is cleared to 0 by clearing EPO3 interrup source register to 0016 Writing to this bit causes no state change USB HUB Endpoint 0 interrupt bit This bit is set to 1 when any one of EP10 interrup source register
173. Index X mode flag T Note 2 When using Decimal mode flag D Push registers used in interrupt process routine Processing as out of range when the count value is 256 or more Count value read Count value into Accumulator A stored In range Read value with reference value compared Comparison result to flag Fpulse stored Fpulse 1 TX address 2516 lt 256 1 IREQ1 address 3C16 bits 0 Process judgment result Pop registers RTI Fig 2 3 19 Control procedure Rev 2 00 Oct15 2006 page 35 of 112 REJ09B0338 0200 Counter value initialized Timer X interrupt request bit cleared Pop registers pushed to stack 2RENESAS APPLICATION 38K2 Group 2 3 Timer 5 Timer application example 4 Measurement of FG pulse width for motor Outline The timer X counts the H level width of the pulses input to the P5 CNTRo pin An underflow is detected by the timer X interrupt and an end of the input pulse H level is detected by the CNTRo interrupt Specifications The timer X counts the H level width of the FG pulse input to the P5 CNTRo pin lt Example gt When the clock frequency is 6 MHz the count source is 2 67 us which is obtained by dividing the clock frequency by 16 Measurement can be performed to 175 ms in the range of FFFFi to 000016 Figure 2 3 20 shows the timers connection and setting of division ratio Figure 2 3 21 shows the related registers setting Figure 2
174. K P42 ExTC RxD P40 ExDREQ Busy P43 ExA1 Zm P16 Wwe gt VpP CNVss se gt Y RESET User reset signal Low active 1 When not used set to input mode and pull up or pull down or set to output mode and open 32 It is necessary to apply Vcc to Sctk P42 ExTC pin only when reset is released in the standard serial I O mode Fig 2 14 5 Connection example in standard serial I O mode 1 When control signals are affected to user system circuit 1 Figure 2 14 6 shows an example that the jumper switch cut off the control signals not to supply to the user system circuit in the standard serial I O mode Target board To user system circuit M38K29F8FP HP M38K29F8LFP LHP TxD P41 ExDACK ScLK P42 ExTC RxD P40 ExDREQ Busy P43 ExA1 P16 Vpp CNVss 3 y RESET User reset signal Low active It is necessary to apply Vcc to Sctk P42 ExTC pin only when reset is released in the standard serial I O mode Fig 2 14 6 Connection example in standard serial I O mode 2 Rev 2 00 Oct 15 2006 page 108 of 112 RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory When control signals are affected to user system circuit 2 Figure 2 14 7 shows an example
175. L Ver Table 3 1 7 Timing requirements 1 Vcc 4 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter APPENDIX 3 1 Electrical characteristics L Ver tw RESET Reset input L pulse width tc XIN Main clock input cycle time tWH XIN Main clock input H pulse width tWL XIN Main clock input L pulse width tc CNTR CNTRo input cycle time twH CNTR CNTRo input H pulse width twL CNTR CNTRo input L pulse width twH INT INTo INT1 input H pulse width twL INT INTo INT1 input L pulse width tc SCLk Serial I O clock input cycle time Note tWH SCLK Serial I O clock input H pulse width Note twL SCLk Serial I O clock input L pulse width Note tsu RxD SCLk Serial I O input set up time th SCLK RxD Serial I O input hold time Note These limits are the rating values in the clock synchronous mode bit 6 of address OFE016 1 In the UART mode bit 6 of address OFE016 0 the rating values are set to one fourth Table 3 1 8 Timing Symbol requirements 2 Vcc 3 00 to 4 00 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter tw RESET Reset input L pulse width tC XIN Main clock input cycle time tWH XIN Main clock input H pulse width tWL XIN
176. MISRG Y Fig 2 13 1 Memory map of registers related to standby function 2 13 2 Related registers MISRG b7 b6 b5 b4 b3 b2 bi bO MISRG MISRG address OFFB16 B Name Functions treet RI Oscillation stabilizing time 0 Automatically set 0116 to Timer 1 set after STP instruction FFie to Prescaler 12 released bit 1 Automatically set nothing Nothing is arranged for these bits These are write disabled bits When these bits are read out the contents are indefinite Fig 2 13 2 Structure of MISRG Rev 2 00 Oct 15 2006 page 95 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 13 Standby function 2 13 3 Stop mode The stop mode is set by executing the STP instruction In the stop mode the oscillation of clock Xin Xout stops and the internal clock stops at the H level The CPU stops and peripheral units stop operating As a result power dissipation is reduced 1 State in stop mode Table 2 13 1 shows the state in the stop mode Table 2 13 1 State in stop mode Item State in stop mode Stopped Stopped Stopped at H level Retains the state at the STP instruction execution Oscillation CPU Internal clock I O ports PO P6 Stopped Timers 1 2 X However Timers X can be operated in the event counter mode Stopped Stopped However these can be operated only when an external clock is selected Timer Watchdog timer Serial I O
177. Main processing Fig 2 9 6 Control procedure 2 9 4 Notes on watchdog timer Make sure that the watchdog timer does not underflow while waiting Stop release because the watchdog timer keeps counting during that term When the STP instruction disable bit has been set to 1 it is impossible to switch it to 0 by a program Rev 2 00 Oct 15 2006 page 81 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 10 Reset 2 10 Reset 2 10 1 Connection example of reset IC Power source General purpose 5 Output reset IC 4 Delay capacity 0 1 1 uF Vss 38K2 Group Fig 2 10 1 Example of poweron reset circuit Figure 2 10 2 shows the system example which switches to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt System power source voltage 5 V 3 Vcec2 INT M Vss 38K2 Group 6 Vi anp C4 l M62009L M62009P M62009FP Fig 2 10 2 RAM backup system Rev 2 00 Oct15 2006 page 82 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 10 Reset 2 10 2 Notes on RESET pin Connecting capacitor In case where the RESET signal rise time is long connect a ceramic capacitor or others across the RESET pin and the Vss pin Use a 1000 pF or more capacitor for high frequency use When connecting the capacitor note the following e Make the length of the wiring which is connected to a capacitor as sh
178. Mode Memory channel transmitting operation 2 is shown bellow Address ExA0 Chip select ExCS DMA acknowledge ExDACK Read ExRD Write ExWR Data DQo to DQ7 Internal clock o DMA request ExDREQ mRD detection mRD 7 detection Transmission completed Transmit buffer TXBUF Operation enabled Main sequencer Memory channel operation end interrupt Internal memory access Memory address 010116 Counter end Burst end Ce sd inAnandanans i a disudinency sos ie la of lacs gl lt Initial setting gt External I O configuration register Set as necessary Memory channel operation mode register MC_DIR 1 0 Memory channel direction control 102 Transmit mode Burst burst 1 Burst mode Memory address counter Example 010016 End address register Example 010216 lt Operation start command gt EXB interrupt source enable register MC_ENB Memory channel operation enable 1 Operation start In the memory channel transmit mode when the command for enabling operation is written an internal memory access sequence which synchronized with a rise of is activated A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer TXBUF The memory address counter is simultaneously increased and assertion of the memory channel request is made When a rise o
179. Nothing is allocated for these bits These are write disabled bits ae When these bits are read out the contents are 1 Eiga Rack Fig 2 4 5 Structure of UART control register Rev 2 00 Oct 15 2006 page 42 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator BRG Address OFE216 Fig 2 4 6 Structure of Baud rate generator Interrupt edge selection register b7 b6 b5 b4 b3 b2 bi bO Interrupt edge selection register INTEDGE et OFF316 Function et interrupt edge H Falling edge active selection bit Rising edge active Nothing is arranged for this bits This is a write disabled bit When this bit is read out the contents are 0 Nothing is arranged for this bits This is a write disabled bit When this bit is read out the contents are 0 Fig 2 4 7 Structure of Interrupt edge selection register Rev 2 00 Oct15 2006 page 43 of 112 2RENESAS REJ09B0338 0200 38K2 Group Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 bO Interrupt request register 2 IREQ2 Address 3D16 Name Function At rese INT1 interrupt 0 No interrupt request issued request bit 1 Interrupt request issued USB HUB interrupt 0 No interrupt request issued request bit 1 Interrupt request issued Serial I O receive 0 No interrupt request issued interrupt request bit 1 Interrupt reque
180. ON This chapter describes usage and application examples of peripheral functions based mainly on setting examples of relevant registers CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer such as the electrical characteristics the list of registers 2 Structure of register The figure of each register structure describes its functions contents at reset and attributes as follows Note 2 Bits Bit attributes Note 1 b7 b6 b5 b4 b3 b2 bi bO Contents immediately after reset release CPU mode register CPUM Address 3B 16 Name Function Processor mode bits eae mode Not available Stack page selection bit T 7 page Nothing arranged for these bits These are write disabled bits When these bits are read out the contents are 0 Fix this bit to 0 Main clock X n XourT stop bit He S gperating Internal system clock selection bit Xn Xg selected ERCH E Bit in which nothing is arranged Bit that is not used for control of the corresponding function Note 1 Contents immediately after reset release 0 at reset release 1 at reset release Undefined at reset release Contents determined by option at reset release Note 2 Bit attributes The attributes of control register bits are classified into 3 bytes read only write only and read and write In the figure these attributes are represented as follows
181. P03 control register 1 Rev 2 00 Oct 15 2006 page 49 of 130 7tENESAS REJ09B0338 0200 State remaining 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION b7 bO ofofofolofo o EP03 control register 2 EPO3CON2 address 001B16 Bit symbol Bit name Function At reset H W S W BOVALO3 Buffer 0 enable bit When the selected endpoint is IN writing 1 to this bit makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write 0 Write 0 when writing 0 is read when reading Fig 67 Structure of EP03 control register 2 b7 bO ofofofolofo o EP03 control register 3 EPO3CON3 address 001C16 State remaining Bit symbol Bit name Function At reset H W S W B1VAL03 Buffer 1 enable bit When the selected endpoint is IN writing 1 to this bit makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write In double buffer mode this bit is valid 0 Not used Write 0 when writing 0 is read when reading Fig 68 Structure of EP03 control register 3 b7 bO fofofofofol
182. PLL circuit f XIN or fvco can be selected as an input clock When using as an internal system clock there is restriction on use Refer to the clause of PLL CIR CUIT 2 XIN clock The frequency applied to the XIN pin is used as an internal system clock frequency Rev 2 00 Oct15 2006 page 97 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Oscillation Control 1 Stop mode If the STP instruction is executed the internal clock stops at an H level and the XIN oscillator stops When the oscillation stabi lizing time set after STP instruction released bit is 0 the prescaler 12 is set to FF16 and timer 1 is set to 0116 When the oscillation stabilizing time set after STP instruction released bit is 1 set the sufficient time for oscillation of used oscillator to stabi lize since nothing is set to the prescaler 12 and timer 1 XIN divided by 16 is compulsorily connected to the input of the prescaler 12 Oscillator restarts when an external interrupt includ ing USB resume interrupt is received but the internal clock o remains at H until timer 1 underflows The internal clock is not supplied until timer 1 underflows Because the sufficient time is re quired for the oscillation to stabilize when a ceramic resonator etc is used When the oscillator is restarted by reset apply L level to the RESET pin until the oscillation is stable since a wait time will not be genera
183. PPENDIX 38K2 Group 3 4 List of registers Port P5 pull up control register b7 b6 b5 b4 b3 b2 b1 bO Port P5 pull up control register PULL5 Address OFF216 B Name _ Function 0 No pull up o P50 pul l up control bit 1 Pull up 0 foto Nothing is arranged for this bit This is a write disabled bit O l x When this bit is read out the contents are 0 I x 0 No pull up P52 pul l up control bit 1 Pull up 9 oto Nothing is arranged for these bits These are write disabled I bits When these bits are read out the contents are 0 O Fig 3 4 100 Structure of Port P5 pull up control register Interrupt edge selection register b7 b6 b5 b4 b3 b2 bi bO Interrupt edge selection register INTEDGE Address OFF316 B Name Function Ri INTo interrupt edge 0 Falling edge active selection bit 1 Rising edge active Nothing is arranged for this bits This is a write disabled bit l When this bit is read out the contents are 0 1 2 INT1 interrupt edge 0 Falling edge active selection bit 1 Rising edge active ca I I Nothing is arranged for these bits These are write disabled bits i When these bits are read out the contents are 0 l Fig 3 4 101 Structure of Interrupt edge selection register Rev 2 00 Oct15 2006 page 80 of 99 7tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers PLL control register b7 b6 b5 b4 b3 b2 bi bO PLL control reg
184. R ExDACK setup time for read tsu ACK W ExDACK setup time for write th R ACK ExDACK hold time for read th W ACK ExDACK hold time for write Read H pulse width Read L pulse width Write H pulse width Write L pulse width ExDACK H pulse width twL ACK ExDACK L pulse width tsu D W Data input setup time before write 40 th W D Data input hold time after write 0 Data input setup time before ExDACK tsu D ACK 60 th ACK W Data input hold time after ExDACK 5 CPU clock cycle time tc o 125 Burst mode access cycle time tw cycle USB function not operating tC 3 10 Rev 2 00 Oct15 2006 page 9 of 99 REJ09B0338 0200 USB function operating 2tENESAS tC o 5 10 38K2 Group Table 3 1 10 Timing requirements of external bus interface EXB 2 Vcc 3 00 to 4 00 V Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter APPENDIX 3 1 Electrical characteristics L Ver Limits Typ tsu S R ExCS setup time for read tsu S W ExCS setup time for write th R S ExCS hold time for read th W S ExCS hold time for write tsu A R ExA0 ExA1 setup time for read tsu A W ExA0 ExA1 setup time for write th R A ExA0 ExA1 hold time for read th W A ExA0 ExA1 hold time for write tsu
185. R1 Downstream port 1 port error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when an error occurs on a downstream port 1 0 can be set by software but 1 cannot be set PTRSM1 Downstream port 1 resume interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a resume signal on a downstream port 1 in the condition of HUB suspended or port suspended state 0 can be set by software but 1 cannot be set PTCHG1 Downstream port 1 bus change detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus change of a downstream port 1 in the condition of HUB suspended state It is also 1 in the internal clock halted 0 can be set by software but 1 cannot be set Write 0 when writing 0 is read when reading Fig 3 4 59 Structure of DP1 interrupt source register Rev 2 00 Oct15 2006 page 62 of 99 REJ09B0338 0200 2tENESAS State remaining 38K2 Group APPENDIX 3 4 List of registers DP2 interrupt source register DP2REQ address 002B16 Bit symbol Bit name Function At reset H W S W PTDIS2 Downstream port 2 disconnect detection interrupt bit 0 No interrupt request issued 1 Inter
186. Read enabled Write enabled Read disabled Write disabled 0 write 3 Supplementation For details of software refer to the 740 FAMILY SOFTWARE MANUAL For details of development support tools refer to the Renesas Technology Homepage http www renesas com Table of contents 38K2 Group Table of contents CHAPTER 1 HARDWARE DESCRIPTION ss cccsccce cnet aonni anana aaeain aasien aaaea aaa aa coca ston sec eaaa aannaaien daanan 2 PE URES E E E ce fect rec E EE EE EE AT T 2 PIN CONFIGURATION sce ccccsccesentecc chee cdecccseaccee sates denteedcecauseeed caidet aaae aaaea aaa aaaea 2 FUNC TIONAL IBLOCK os wvcsecocevssersteectccsinecsceeteciute aaaea dian aada cectevesesdecceteteveseieeseedvenisiesecselentevencintves 3 PIN IDES GRUP TON coo cocoa esac sce ween cece auc aaaea ke sete eeme ec ea aeae a eaa Sea ENEE E SEENE 4 PART NUMBERING iiaeeeaeo asar oaa aa aa aa teed a aa aaae aae Eana ei aaa aa aana oiana anaa deanas 5 GROUP EXPANSION uinnissa nesinu aces sacde cece cease Sec annae aaiae aa aana aa aaa iaaa daaa Kaa oada da Eada aiani 6 MEMORY TY DO irrien eE EE S EEE S E E S 6 Memory SIZE sisian a a a a eiaa aar aaaea a DEA a ea aa aaia 6 PACKAGCS acson inn E a EEA E EE AE TE EATE E OEA 6 FUNCTIONAL DESCRIPTION ssssnssnnennnnennnunnnnunnnuunnenunnunnnnnnnnnnnnnnnnnnnnnnnnnnn ennn nnnnnnnnnnnnnnnnnn ennnen nnn nn aes 7 Central Processing Unit CPU rcidorsiienisnaoiiincnii ienaiiino iaaea i iaaa T MenO sr pa bes EE
187. Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office
188. RxB_RDY is normally selected The memory channel request is for an access request signal to the memory channel In a small system a data transfer processing to the internal memory is performed in the interrupt routine According to that situation the 38K2 group has the function automatically to switch an interrupt factor attached on the interrupt pin by program P40 ExDREQ RxD pin This pin is a port at the initial state Which signal can be set by program RxB_RDY receive buffer ready output Mch_req memory channel request output Mch_req of DMAC is normally selected The output method of the memory channel request signal depends on the burst bit BURST of memory channel operation mode register When the burst bit is 0 this signal is periodically output at each 1 byte transfer See Figures 124 and 127 When the burst bit is 1 this signal is continuously output while the memory address counter is counting from the beginning ad dress to the end address See Figures 125 and 128 P41 ExDACK TxD pin This pin is a port at the initial state The DMA acknowledge signal can be set by program The DMA acknowledge signal DACK L is the same state as that of CS L and AO L Access to multichannel RAM is started by a rise of read signal or write signal which is set during this term Note If the DMA acknowledge signal and the chip select signal are simultaneously active DACK L and CS L
189. S Addition Subtraction Multiplication Division Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high order bits of program counter 8 low order bits of program counter 8 high order bits of address 8 low order bits of address FF in Hexadecimal notation Immediate value Zero page address Memory specified by address designation of any ad dressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL in ADH is 8 high order bits and ADL is 8 low or der bits Contents of address indicated by zero page ADL Bit i i 0 to 7 of accumulator Bit i i 0 to 7 of memory Opcode Number of cycles Number of bytes APPENDIX 38K2 Group 3 7 List of instruction code 3 7 List of instruction code JSR ZP IND CLT JSR SP LDX IMM JMP ZP IND WIT 3 byte instruction 2 byte instruction 1 byte instruction Rev 2 00 Oct 15 2006 page 97 of 99 2tENESAS REJ09B0338 0200 38K2 Group 3 8 SFR memory map 000016 Port PO PO 000116 Port PO direction register POD 000216 000316 000416 Port P1 P1 Port P1 di
190. S output falling time Note Notes Pins XouT D0 DO D1 D2 D2 D2 are excluded Table 3 1 12 Switching characteristics 2 Vcc 3 00 to 4 00 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Symbol Parameter 7 Min Typ tWH SCLKk Serial I O clock output H pulse width tc SCLk 2 50 twL SCLk Serial I O clock output L pulse width tc SCLK 2 50 ta SCLK TxD Serial I O output delay time tv SCLK TxD Serial I O output valid time 30 tr SCLKk Serial I O clock output rising time tt SCLKk Serial I O clock output falling time tr CMOS CMOS output rising time Note tt CMOS CMOS output falling time Note Notes Pins XouT D0 DO D1 D2 D2 D2 are excluded Measured output pin CMOS output Fig 3 1 1 Output switching characteristics measurement circuit Rev 2 00 Oct 15 2006 page 11 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 1 Electrical characteristics L Ver Table 3 1 13 Switching characteristics of external bus interface EXB 1 Vcc 4 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter Data output enable time after read Data output disable time after read Data output enable time after ExDACK Data output disable time after ExDACK In cycle mode Mch_req disable output delay time after read ta W Mdis In cycle mode Mch_req
191. Set and clear instructions of each bit of processor status register C O f che zie me omg sra Tiag vios Nio EC SED SET Set instruction S SEI Clear instruction CLC CLI Rev 2 00 Oct15 2006 page 9 of 130 REJ09B0338 0200 CL T C 2tENESAS 38K2 Group CPU Mode Register CPUM 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit The CPU mode register is allocated at address 003B16 HARDWARE FUNCTIONAL DESCRIPTION CPU mode register CPUM address 003B16 Processor mode bits b1 bO 0 0 Single chip mode 0 1 1 0 Not available 1 i Stack page selection bit 0 0 page 1 1 page Not used returns 1 when read Do not write 0 to this bit Not used returns 0 when read Do not write 1 to this bit System clock selection bit 0 Main clock XIN 1 SYN Fig 7 Structure of CPU mode register Rev 2 00 Oct15 2006 page 10 of 130 REJ09B0338 0200 7tENESAS System clock division ratio selection bits b7 b6 0 0 f system clock 8 8 divide mode 0 1 f system clock 4 4 divide mode 1 0 f system clock 2 2 divide mode 1 1 f system clock Through mode 38K2 Group MEMORY Special Function Register SFR Area The Special Function Register area in the zero page contains con trol registers such as I O ports and timers RAM RAM is used for data stor
192. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry CENESAS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is grant
193. U status signal reading Interrupt signal generation Internal bus interface control 2tENESAS 38K2 Group USB Port External Circuit Configuration The operation mode of the USB port driver circuit can be config ured by USB control register address 001016 Figure 25 and Figure 26 show the USB port external circuit block diagram ji VREFCON 0 Hiz Hiz 3 3V output 3 3V output Normal mode Low power model VREFCON USB Reference Voltage Circuit USBVREF status HARDWARE FUNCTIONAL DESCRIPTION USBVREF j UCLKCON USB Module 2 2 uF TRONCON 4 Full gt lt _ lt 4 ba USBE oa e Fig 25 USB port external circuit D0 DO USBVREF TrON block diagram 4 0V lt Vcc lt 5 25V 3 0V to 3 6V Note USBVREF 0 1 uF T TRON TRONCON TRONE UCLKCON Fig 26 USB port external circuit D0 DO USBVREF TrON block diagram 3 0V lt Vcc lt 4 0V Rev 2 00 Oct15 2006 page 28 of 130 REJ09B0338 0200 i gt lt a 4 Full gt T USBE lt lt USBDIFE j lt _ ____ m4 gt USBE Full gt i Note In Vcc 3 0 V to 3 6 V connect this pin to Vcc 2tENESAS 38K2 Group Endpoint Buffer Area Setting The buffer area used i
194. U is used internally to control access with the CPU When receiving an access request from the USB or the EXB the multichannel RAM outputs ONW signal to wait the CPU for one clock and access of the USB or the EXB is performed If the multichannel RAM is outputting ONW signal while the CPU is in the state of reading writing for the RAM area the CPU read cycle or write cycle is extended by 1 period of 0 No wait No wait Except RAM No RD WR lt __ lt 4 _ it _ CPU bus cycle USB REQ Multichannel RAM EXB REQ ONW RAM access right RAM bus cycle RAM RD WR Fig 129 Multichannel RAM timing diagram no wait One wait CPU accessing RAM at the latter part L l L L One wait One wait One wait Prohibiting continuous access of USB having priority of USB EXB 2 cycle wait max for EXB _ j Prior CPU CPU bus cycle Multichannel RAM EXB REQ RAM access right RAM bus cycle RAM RD WR Fig 130 Multichannel RAM timing diagram one wait Rev 2 00 Oct15 2006 page 89 of 130 REJ09B0338 0200 USB EXB simultaneous access gt lt lt gt lt gt lt Prior CPU Prior USB Loo ee Sk T iT Prior CPU USB REQ en Ge y fe qe ee oS y Cd onw e ey ees ee eee GCT Le i T LO NMN LT 2RENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION Multichannel RAM Operation Example The multichannel RAM operation example is shown below This example shows the case
195. U rewrite mode set the internal clock 1 5 MHz or less using the system clock division ratio selection bits bits 6 and 7 of address 003Bie Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during the CPU rewrite mode Interrupts inhibited against use The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data of the flash memory Watchdog timer In case of the watchdog timer has been running already the internal reset generated by watchdog timer underflow does not happen because of watchdog timer is always clearing during program or erase operation Reset Reset is always valid In case of CNVss H when reset is released boot mode is active So the program starts from the address contained in address FFFCis and FFFDie in boot ROM area Rev 2 00 Oct 15 2006 page 112 of 112 7RENESAS REJ09B0338 0200 CHAPTER 3 APPENDIX 3 1 Electrical characteristics 3 2 Notes on use 3 3 Countermeasures against noise 3 4 List of registers 3 5 Package outline 3 6 List of instruction code 3 7 Machine instructions 3 8 SFR memory map 3 9 Pin configurations 38K2 Group 3 1 Electrical characteristics 3 1 1 Absolute maximum ratings Table 3 1 1 Absolute maximum ratings Parameter Conditions APPENDIX 3 1 Electrical characteristics L Ver Ratings Power source voltage Analog power source voltage VcCcE
196. USB function address register USBAO address 001216 At reset Bit symbol Bit name Function nw TSW R iW USBADDO USB function address bit In ADOE 0 this value changes after writing 0 0 10 O 6 0 In ADOE 1 this value changes after completion of SET_ADDRESS control transferring b7 Write 0 when writing O 0 is read when reading Oo e remaining Fig 3 4 5 Structure of USB function address register Rev 2 00 Oct 15 2006 page 40 of 99 7tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers USB HUB address register USBA1 address 001316 At reset H W S W USBADD1 USB HUB address bit In AD1E 0 this value changes after writing 0 0 6 0 In AD1E 1 this value changes after completion of SET_ADDRESS control transferring b7 Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 3 4 6 Structure of USB HUB address register Frame number register Low FNUML address 001416 At reset H W S W FNUM Frame number low bit The frame number is updated at SOF reception In In 7 0 definite definite Bit symbol Bit name Function Fig 3 4 7 Structure of Frame number register Low b7 bO fofofofofo Frame number register High FNUMH address 001516 Bi
197. Wiring to analog input pins e Connect an approximately 100 Q to 1 kQ resistor to an analog signal line which is connected to an analog input pin in series Besides connect the resistor to the microcomputer as close as possible e Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin Besides connect the capacitor to the Vss pin as close as possible Also connect the capacitor across the analog input pin and the Vss pin at equal length Reason Signals which is input in an analog input pin such as an A D converter comparator input pin are usually output signals from sensor The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer the wiring to an analog input pin is longer necessarily This long wiring functions as an antenna which feeds noise into the microcomputer which causes noise to an analog input pin If a capacitor between an analog input pin and the Vss pin is grounded at a position far away from the Vss pin noise on the GND line may enter a microcomputer through the capacitor Note Microcomputer Analog input pin Note The resistor is used for dividing resistance with a thermistor Fig 3 3 7 Analog signal line and a resistor and a capacitor Rev 2 00 Oct 15 2006 page 35 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 3 Countermeasures against noise 3 3 4 Oscillator concerns Take care to prevent an oscill
198. XB index register contents as definite definite follows Index value 0016 External I O configuration register 0116 Transmit Receive buffer register 0216 Memory channel operation mode register 0316 Memory address counter 0416 End address register Bit symbol Bit name Function Fig 3 4 74 Structure of Register window 2 Index 0016 External I O configuration register EXBCFGH address 003516 At reset H W S W DRQ_CTR_ P40 ExDREQ RxD pin control 0 1 0 bit Port Do not set ExDREQ function RxB_RDY RxBuf ready output EXDREQ function Mch_req Memory channel request output DAK_CTR_ P41 ExDACK TxD pin control Specifies P41 ExDACK TxD pin function 1 0 bit Selects which mode requiring read or write signal or not requiring it for use of DMA acknowledge function Bit symbol Bit name Function b3b2 0 0 Port 0 1 Do not set 1 0 ExDACK function DMA acknowledge input Mode for read and write signals used together 1 1 ExDACK function DMA acknowledge input Mode for read and write signals not required P42 ExTC ScLk pin control bit 0 Port 1 ExTC terminal count input Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 75 IndexOO high Structure of External I O configuration register Rev 2 00 Oct 15 2006 pa
199. XREG3 001Ci6 Endpoint field register 4 EPXXREG4 001D16 Endpoint field register 5 EPXXREG5 001E16 Endpoint field register 6 EPXXREG6 001Fis Endpoint field register 7 EPXXREG7 OFEC16 Endpoint field register 8 EPXXREG8 OFED16 Endpoint field register 9 EPXXREG9 1 Endpoint 00 001916 EPOO stage register EPOOSTG SETUPOO 001A16 EP00 control register 1 EPOOCON1 PIDOO 1 0 001Bis EP00 control register 2 EPOOCON2 BVALOO 001Cie EP00 control register 3 EPOOCON3 CTENDE0O 001D16 EPO0O interrupt source register EPOOREQ BSRDY00 CTSTS00 CTENDOO BRDY0O 001E16 EP00 byte number register EPOOBYT BBYTOO 3 0 001F16 OFEC16 OFED16 EPO0O buffer area set register EPOOBUF BADDOO 4 0 T 2 Endpoint 01 001916 set register EPO1CFG TYPO1 1 0 ITMDO1 SQCLO1 DBLBO1 BSIZ01 1 0 001A16 control register 1 EP01CON1 PIDO1 1 0 001Bis control register 2 EP01CON2 BOVALO1 001C16 control register 3 EP01CON3 B1VALO1 001D16 interrupt source register EP01REQ BiRDYO1 BORDYO1 001E16 byte number register 0 EPO1BYTO BOBYT01 6 0 001F16 byte number register 1 EPO1BYT1 B1BYT01 6 0 OFEC16 MAX packet size register EPO1MAX MXPS01 6 0 OFED16 buffer area set register EP01BUF BADD01 4 0 T 3 Endpoint 02 001916 EP02 set register EP02CFG TYP02 1 0 ITMD02 SQCL02 DBLB02 BSIZ02 1 0 001A16 EP02 control re
200. Z 3 00 to 5 25 V e Power dissipation At 5 V power source Voltage eee eeeeeeeeeee 125 mW typ at 8 MHz system clock in through mode At 3 3 V power source voltage esee 30 mW typ at 6 MHz system clock in through mode Operating temperature range eeeeeeeeeeteeeteeeteeees 20 to 85 C e Packages EP soc cinsshacvesscaactvetabaes PLQPO0064GA A 64 pin 14 X 14 mm LQFP a scat seh asec secesttesceess PLQPO064KB A 64 pin 10 X 10 mm LQFP POs gt P07 lt gt P40 ExDREQ RxD lt gt P41 ExDACK TxD gt P42 ExTC Scik lt gt P4s ExA1 Sroy lt gt P30 gt P31 gt P32 lt gt P33 ExINT gt P34 ExCS lt gt P3s ExWR lt gt P36 ExRD gt P37 ExAO0 lt gt P10 DQo ANo 4 gt P11 DQ1 AN1 4 gt M38K27M4L XXXFP HP M38K29F8LFP HP 37 lt gt P52 INT1 36 lt P51 CNTRo 35 lt gt P50 INTo P25 P24 D2 D2 D1 D1 D0 DO TrON USBVREF DVcc PVcc PVss P63 LEDs P62 LED2 P61 LED1 ALN 5 AN4 AN5 AN6 4 DQa 5 DQs P P P CNVss2 gt Package type PLQP0064GA A 64P6U A PLQP0064KB A 64P6Q A Fig 1 Pin configuration of 38K2 group Rev 2 00 Oct15 2006 page 2 of 130 REJ09B0338 0200 2tENESAS HARDWARE FUNCTIONAL BLOCK 0q 434AgSN NOL 8 JaaAU0o X9 0L k YYYY VY
201. _ 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 4 USB SOF interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled USB device interrupt 0 Interrupt disabled 0 oto enable bit 1 Interrupt enabled 3 EXB interrupt 7 Interrupt disabled enable bit Interrupt enabled INTo interrupt Interrupt disabled enable bit Interrupt enabled Timer X interrupt Interrupt disabled enable bit Interrupt enabled 6 Timer 1 interrupt T disabled enable bit 1 Interrupt enabled 7 Timer 2 interrupt 0 Interrupt disabled 0 oto enable bit 1 Interrupt enabled Fig 2 2 4 Structure of Interrupt control register 1 Rev 2 00 Oct 15 2006 page 9 of 112 2RENESAS REJ09B0338 0200 APPLICATION 2 2 Interrupt APPLICATION 38K2 Group 2 2 Interrupt Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 bO lof Td Interrupt control register 2 ICON2 Address 3F 16 B Name Function _ Atreset RiW INT1 interrupt 0 Interrupt disabled l enable bit 1 Interrupt enabled 4 USB HUB interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 9 Serial I O receive 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 3 Serial I O transmit 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 4 CNTRo interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 5 Key on wake up 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled A D conversion _ 0
202. ady state enabled to be read written on USB function Endpoint 3 0 can be set by software but 1 cannot be set 0 0 B1RDY03 USB function Endpoint 3 buffer 1 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued In single buffer mode this bit is invalid This bit is set to 1 when the buffer 1 is ready state enabled to be read written on USB function Endpoint 3 in double buffer mode 0 can be set by software but 1 cannot be set USB function Endpoint 3 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when STALL response occurs on USB function Endpoint 3 0 can be set by software but 1 cannot be set Not used Write 0 when writing 0 is read when reading Fig 3 4 38 Structure of EP03 interrupt source register Rev 2 00 Oct15 2006 page 53 of 99 REJ09B0338 0200 2tENESAS 38K2 Group APPENDIX 3 4 List of registers EP10 interrupt source register EP10REQ address 001D16 Bit symbol Bit name Function At reset H W S W BRDY10 USB HUB Endpoint 10 buffer ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer is ready state enabled to be read written on USB HUB Endpoint 10 0 can be set by softwa
203. age and for stack area of subroutine calls and interrupts ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs In the flash memory version program and erase can be performed in the reserved area RAM area RAM size bytes XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 ROM area ROM size Address Address bytes YYYY16 ZZZZ16 4096 F00016 F08016 8192 E00016 E08016 12288 D00016 D08016 16384 C00016 C08016 20480 B00016 B08016 24576 A00016 A08016 28672 900016 908016 32768 800016 808016 36864 700016 708016 40960 600016 608016 45056 500016 508016 49152 400016 408016 53248 300016 308016 57344 200016 208016 61440 100016 108016 Fig 8 Memory map diagram Rev 2 00 Oct15 2006 page 11 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area The internal RAM and the special function regis ters SFR are allocated to this area The zero page addressing mode can be used to specify memory and register addresses in the zero page area Access to this area with only 2 bytes is possible in the zero page addressing mode Special Page The 256 bytes from addresses FF001
204. agram 4 0V lt Vcc SD eZOV essccisdeuscscwecerdedsnedenisgseonede le seaueluntax E a EE E Ea 28 USB port external circuit D0 DO USBVrer TrON block diagram 3 0V lt Vcc EA ONA E E EEEE N fv cusenideadasiatpaancns lea ENT 28 Example setting of buffer area beginning address sssssssesssresssrsesrisesressrresrressrns 29 Examples of interrupt source dependant buffer area offset address 0 29 USB device interrupt control cece cece ee eeeee cece eeeeeeeeeceeeeeeaeeeeeeeeeeaaeseeeeeeeseaeeeeeaaeeeeaees 31 USB related registers Ac scecvishdisd in anana aa evant 32 Structure of USB Control register cccccesseeeseeeeeeeeeeeeeceaeeeeaaeeseeaeeeeaaeeseeeeeeaaeeseaees 33 Structure of USB function HUB enable register ccceeeeessececeeeeeeeeseeeeeeeteeeeeaees 33 Structure of USB function address register ccccecceeececeeeeeeeeseceeeeeeeeeseeeeeeeeaeeeeaees 34 Structure of USB HUB address register ccccceceeeeeeeeeceeeeeeseeeececeeeeseeeeseeeeeetaeeneaees 34 Structure of Frame number register LOW ccceccceeeseeeeeeeeeeseeeeceeeeeeeaaeeseeeeeeseaaeeeenees 34 Structure of Frame number register High cccceeseeeceeeeeeeeeeeceeeeeeeeeeseeeeeeseaeeeeenees 34 Structure of USB interrupt source enable register cecceeeeeecseeeeeeeeeeeeteeeeeeeeeesees 35 Structure of USB interrupt source register eeeeeeeneeeceeeeeeeeeeeteeeeeesaaeeeeeeeeetiaeeetnes 36 Struc
205. ased 1 oe i 1 CPU rewrite mode 0 Normal mode Software select bit Note 2 commands invalid 1 CPU rewrite mode Software commands acceptable 2 CPU rewrite mode 0 Normal mode Oi X entry flag 1 CPU rewrite mode 3 Flash memory reset 0 Normal operation bit Note 3 1 Reset User area Boot area 0 User ROM area selection bit Note 4 1 Boot ROM area 5 Nothing is arranged for these bits If writing Undefined X Q 6 set 0 When these bits are read out a the contents are undefined Notes 1 The contents of flash memory control register are XXX00001 just after reset release 2 For this bit to be set to 1 the user needs to write 0 and then 1 to it in succession If it is not this procedure this bit will not be set to 1 Additionally it is required to ensure that no interrupt will be generated during that interval Use the control program in the area except the built in flash memory for write to this bit 3 This bit is valid when the CPU rewrite mode select bit is 1 Set this bit 3 to O subsequently after setting bit 3 to 1 4 Use the control program in the area except the built in flash memory for write to this bit Fig 2 14 3 Structure of Flash memory control register Rev 2 00 Oct 15 2006 page 104 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory 2 14 4 Parallel I O mode In the parallel I O mode program era
206. ata normally 8 bits handled as up to 10 bits Because USB uses asynchronous transfers the clock cycle of the USB internal reference clock may change to adjust to the clock phase Therefore the access timing of the USBFCC for the multi channel RAM will change owing to the frequency of internal clock 0 When the USBFCC is operating at 8 MHZ access for a normal Rev 2 00 Oct15 2006 page 26 of 130 REJ09B0338 0200 l External Bus Interface __ Multi ch RAM EXB ulti channe E USB Host z Data transmit ReceiVe path r USB Bus p _ Direct RAM Access Type transfer is performed every 5 to 6 cycles and access for a bit stuff ing transfer is performed in up to 7 cycles If the EXB function is enabled in the above conditions this func tion generates a maximum wait of 1 clock cycle so that the access is performed every 4 to 8 cycles When operating at p 6MHZ a normal access is performed every 4 cycles If the clock phase correction of the reference clock oc curs access is performed every 3 to 5 cycles If bit stuffing occurs at this clock rate the access cycle will be ex tended to up to 6 cycles When the EXB function that generates a maximum 1 wait cycle is used in this condition the access cycle will be 2 min to 7 max cycles 2RENESAS 38K2 Group USB Function Control Circuit USBFCC Block Diagram The following diagram shows the USBFCC block diagram The cir cuit comprises 1 Serial I
207. atch 14 Port P6 Port latch 7tENESAS 38K2 Group Fig 12 Structure of port I O related registers Rev 2 00 Oct15 2006 page 16 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Port PO pull up control register PULLO address OFFO16 POo pull up control bit 0 No pull up 1 Pull up P01 pull up control bit 0 No pull up 1 Pull up P02 pull up control bit 0 No pull up 1 Pull up POs pull up control bit 0 No pull up 1 Pull up P04 pull up control bit 0 No pull up 1 Pull up POs pull up control bit 0 No pull up 1 Pull up POs pull up control bit 0 No pull up 1 Pull up P07 pull up control bit 0 No pull up 1 Pull up Port P5 pull up control register PULL5 address OFF216 P50 pull up control bit 0 No pull up 1 Pull up Nothing is arranged for this bit This is a write disabled bit When this bit is read out the contents are 0 P52 pull up control bit 0 No pull up 1 Pull up Nothing is arranged for these bits These are write disabled bits When these bits are read out the contents are 0 2tENESAS 38K2 Group INTERRUPTS Interrupts occur by sixteen sources four external eleven internal and one software Interrupt Control Each interrupt is controlled by an interrupt request bit an interrupt ena
208. ate remaining 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION DP2 control register DP2CON address 002C16 Bit symbol Bit name Function At reset H W DSCONN2 ream port 2 connect bit Disconnect PTCON2 interrupt enabled Connect PTDIS2 interrupt enabled 0 DSPTEN2 ream port 2 enable bit Downstream port 2 disabled Downstream port 2 enabled This bit is cleared when an interrupt of PTDIS2 or PTERR2 is generated DSSUSP2 ream port 2 suspend bit No port suspended Port suspended This bit is cleared when an interrupt of PTDIS2 or PTRSM2 is generated DSDETE2 Downs ream port 2 connect state detection enable bit Connect state detection disabled PTCON2 and PTDIS2 interrupts disabled Connect state detection enabled This bit is cleared when an interrupt of PTCON2 PTDIS2 or PTERR2 is generated DSRSTO2 Downs transm ream port 2 SEO signal it bit Being not output SEO signal being output DSRSMO2 Downs signal ream port 2 resume transmit bit Being not output K signal being output When writing 0 a low speed EOP is output and then a transition to being not output occurs DSRMOD2 Downs read m ream port 2 bus state ode control bit Mode where a downstream port 2 bus state is read using RD signal Mode where a downstream port 2 bus state is read using EOF2 signal in
209. aticctvcesieeenchi divest actos secee ste xgzesenededesegteoeesesshctacduuasal onescauy neges cateteteetaietees 23 2 3 3 Timer application examples sstessgr kepe aak peanae SERER EN 28 23A Notes ON TIMER arcere Eaa ERA e EAT a deia a ea eiad 39 pA oT A E O E E E E E 40 2 4 Memory Map aeea E A E eee 40 24 2 Related TEQISTSIS oe E ESE E S ie daaieiete 41 2 4 3 Serial I O connection examples cceccceeceeeeeeeeeeeeeeeeeeeaeeeeeeeeesaeeeseaeeeseaeesseaeeseaees 45 2 4 4 Setting of serial I O transfer data format ssssssessssssssressieessrstrisssrinsrinssrrnnsrnnssrnsenn 47 2 4 5 Serial I O application examples ccccccccesceeeeeeeeeeeeeeeeeeeseaeeeseeeeesaeeeseaeeeseeeeseaeeseaees 48 2 4 6 Notes on serial O nindra aa iaai ebat abide ine aan 66 2 5 USB MUN CU OM oaa aaea ee cela ee ee ee ie 69 2 6 HUB function siaaa a fae A a A aA ANA AARAA 70 2 7 External bus interface EXB ccccssssecceeesssseeeeenseseeeeensneeeesenseaeeesesneseeeeseseseeeeeeeseeeeneess 71 28 AD CONVOMCR sodina 72 2g NEm y map a E a ere rerrererertreer ret reccer terre 72 20 2 Peated rogdislorS sccesieucacce tienen ete Reena AEREE RE TAAKAN E ARARE 72 2 8 3 A D converter application examples cccceceececcceeeeeeeeececaeeeeeeeeceaeeeseaeeseeaeeeeeaeeeeaees 75 2 8 4 Notes on A D Converter ecc 2 cecces sentele pace anonn ANNEN ENAERE TEENE 77 2 9 Watchdog tie r ccccceceeecceeeseeeeee een eneeeeeeneneeeee een neeeeeeengneeeeeeegsecee
210. ator that generates clocks for a microcomputer operation from being affected by other signals 1 Keeping oscillator away from large current signal lines Install a microcomputer and especially an oscillator as far as possible from signal lines where a current larger than the tolerance of current value flows Reason In the system using a microcomputer there are signal lines for controlling motors LEDs and thermal heads or others When a large current flows through those signal lines strong noise occurs because of mutual inductance Microcomputer inductance M tw Oh current Fig 3 3 8 Wiring for a large current signal line 2 Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently Also do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise Reason Signal lines where potential levels change frequently such as the CNTR pin signal line may affect other lines at signal rising edge or falling edge If such lines cross over a clock line clock waveforms may be deformed which causes a microcomputer failure or a program runaway Fig 3 3 9 Wiring of RESET pin Rev 2 00 Oct 15 2006 page 36 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 3 Countermeasures against noise 3 Oscillator protection using
211. be executed after every PLP instruction PLP instruction execution S es Sat Fig 3 2 5 Sequence of PLP instruction execution Fig 3 2 6 Stack memory contents after PHP instruction execution 2 BRK instruction Interrupt priority level When the BRK instruction is executed with the following conditions satisfied the interrupt execution is started from the address of interrupt vector which has the highest priority e Interrupt request bit and interrupt enable bit are set to 1 e Interrupt disable flag I is set to 1 to disable interrupt Rev 2 00 Oct 15 2006 page 29 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 3 Decimal calculations Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation set the decimal mode flag D to 1 with the SED instruction After executing the ADC or SBC instruction execute another instruction before executing the SEC CLC or CLD instruction Notes on status flag in decimal mode When decimal mode is selected the values of three of the flags in the status register the N V and Z flags are invalid after a ADC or SBC instruction is executed The carry flag C is set to 1 if a carry is generated as a result of the calculation or is cleared to 0 if a borrow is generated To determine whether a calculation has generated a carry the C flag must be initialized to 0 befor
212. be held at an L level for 16 cycles or more of Xin The reset state is released in approximately 10 5 cycles to 18 5 cycles of the Xin input after the input of the RESET pin is returned to the H level At release of wait mode the internal RAM retains its contents previous to the reset However the previous contents of the CPU register and SFR are not retained Figure 2 13 5 shows the reset input time For more details concerning reset refer to 2 10 Reset gt 4 Wait mode Operating mode Time to hold internal reset state 16 cycles of XIN approximately 10 5 to 18 5 cycles of XIN input i rid gt Execute WIT instruction Fig 2 13 5 Reset input time Rev 2 00 Oct 15 2006 page 101 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 13 Standby function Restoration by interrupt request In the wait mode the occurrence of an interrupt request releases the wait mode and supply of the internal clock to the CPU is started At the same time the interrupt request used for restoration is accepted so the interrupt processing routine is executed However when using an interrupt request for restoration from the wait mode in order to enable the selected interrupt you must execute the STP instruction after setting the following conditions Necessary register setting Interrupt disable flag 0 interrupt enabled Interrupt request bit of interrupt source
213. be set by software but 1 cannot be set Fig 2 2 2 Structure of Interrupt request register 1 Rev 2 00 Oct 15 2006 page 8 of 112 2RENESAS REJ09B0338 0200 38K2 Group Interrupt request register 2 b7 b6 b5 b4 b3 b2 bi bO Interrupt request register 2 IREQ2 Address 3D16 E Name Function INT1 interrupt 0 No interrupt request issued ik j request bit 1 Interrupt request issued O 1 USB HUB interrupt 0 No interrupt request issued Ol request bit 1 Interrupt request issued I 2 Serial I O receive 0 No interrupt request issued interrupt request bit 1 Interrupt request issued l Serial I O transmit 0 No interrupt request issued l 3l OI interrupt request bit 1 Interrupt request issued l 4 CNTRo interrupt 0 No interrupt request issued request bit 1 Interrupt request issued O 5 Key on wake up 0 No interrupt request issued Ol interrupt request bit 1 Interrupt request issued I A D conversion 0 No interrupt request issued interrupt request bit 1 Interrupt request issued O Fares is arranged for this bits This is a write disabled bit l EA When this bit is read out the contents are 0 O x 0 can be set by software but 1 cannot be set Fig 2 2 3 Structure of Interrupt request register 2 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 bO Interrupt control register 1 ICON1 Address 3E16 B Name Function _ Atreser RW USB bus reset _
214. ble bit and the interrupt disable flag except for the software in terrupt set by the BRK instruction An interrupt occurs if the corre sponding interrupt request and enable bits are 1 and the inter rupt disable flag is 0 Interrupt enable bits can be set or cleared by software Interrupt request bits can be cleared by software but cannot be set by software The BRK instruction cannot be disabled with any flag or bit The flag disables all interrupts except the BRK instruction interrupt When several interrupts occur at the same time the interrupts are received according to priority Interrupt Operation By acceptance of an interrupt the following operations are auto matically performed 1 The contents of the program counter and the processor status register are automatically pushed onto the stack 2 The interrupt disable flag is set and the corresponding interrupt request bit is cleared 3 The interrupt jump destination address is read from the vector table into the program counter Table 6 Interrupt vector addresses and priority Vector Addresses Note 1 Interrupt Source Priority High Low HARDWARE FUNCTIONAL DESCRIPTION ENotes on interrupts When setting the followings the interrupt request bit may be set to aa hs When switching external interrupt active edge Related register Interrupt edge selection register address OFF316 Timer X mode register address 002316 When not requiring for the
215. by applying a falling edge to any pin of port PO that have been set to input mode In other words it is generated when AND of input level goes from Port PXx 6 to ports POo P03 L level output PULL 0 register Bit 7 0 xk Port P07 Port P07 direction register 1 at latch P07 output m I 18 HARDWARE FUNCTIONAL DESCRIPTION 1 to 0 An example of using a key input interrupt is shown in Figure 15 where an interrupt request is generated by pressing one of the keys consisted as an active low key matrix which inputs Key input interrupt request PULL 0 register Bit 6 0 Port POs direction register 1 POs output nom od Beas ts PULL 0 register Bit 5 0 1 Port POs Port P05 direction register 1 tC latch POs output I PULL 0 register Bit 4 0 _ Port POs latch Port P04 direction register 1 T lz P04 output aoe I PULL 0 register Bit 3 1 1_ Port POs Port P03 direction register 0 latch POs input tC O 0 Jp Port PO Input reading circuit i PULL 0 register Bit 2 1 Port P02 direction register 0 latch P02 input
216. byte data Read out a reception data from RB Address 2616 Receive buffer full flag is set to 0 by reading data e Judgment of an error flag Processing for error SIOSTS Address 2716 bit6 Fig 2 4 34 Control procedure of receiving side Rev 2 00 Oct15 2006 page 65 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 2 4 6 Notes on serial I O 1 Notes when selecting clock synchronous serial I O Serial 1 O Stop of transmission operation Clear the serial I O enable bit and the transmit enable bit to 0 Serial I O and transmit disabled Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I O enable bit is cleared to 0 Serial I O disabled the internal transmission is running in this case since pins TxD RxD SCLK and SRDY function as I O ports the transmission data is not output When data is written to the transmit buffer register in this state data starts to be shifted to the transmit shift register When the serial I O enable bit is set to 1 at this time the data during internally shifting is output to the TxD pin and an operation failure occurs Stop of receive operation Clear the receive enable bit to 0 receive disabled or clear the serial I O enable bit to 0 Serial I O disabled Stop of transmit receive operation Clear the transmit enable bit and receive enab
217. ccecceeeeeeeceeeeeeeeeeeeeeeeeseaeeeseneeens 69 Fig 103 External bus Interface oo eee cece ceee eee eeeeeeeeeeeseeeeeseesseeeeeeeeaeeeeseseseeaeeeeessneaeseeeseneaes 70 Fig 104 Data transfer timing of memory channel eee eee eeeeee eee eeeeeeeeeeteeeaeeeeeeeeeaeees 70 Fig 105 External bus interface EXB pin ASSIGNMENT eee ee ceeeeee eee eeeeeeeeeeteeeaeeeeeeeeeaees 71 Fig 106 Block diagram of external bus interface EXB ee cece ee eeeeeeeeeeeeeeeeeeeeeeeeeees 72 Fig 107 EXB related registers 1 wescsccccceecsecvecceusnevedentedeceveeeenan eveuelad tects vac deneeesnda EEEE 76 Fig 108 EXB related registers 2 sennasnnenien na 76 Fig 109 Structure of EXB interrupt source enable register ccccsceeeeeeeeeeeeeeeeeeeeeeeteeeees 77 Fig 110 Structure of EXB interrupt source register ccceeeceeeeeeeeeeneeceeeeeeeeeeeeeeeeeeseaeeseeees 77 Fig 111 Structure of EXB index register cccceceeeeeeeseeeceeeeeeeeeeeceeeeeeeeaeeseeeeeesaaaeseeeeeeseaeeneeees 78 Fig 112 Structure of Register Window 1 o eeeccccceeeeeeeceeeeeeeeee cere eeeeaeeseeeeeeeaaaeseneeeesiaaeeseeees 78 Fig 113 Structure of Register WINdOW 2 oo eeeccecccceeeseeeceeeeeeeeeee cere eeeeaeeseeeeeesaaaeseeeeeeeaaeeseeees 78 Fig 114 Index0O0 low Structure of External I O configuration register 0 cceeeeeeee 79 Fig 115 IndexOO high Structure of External I O configuration register 79 Fig 116 Index01 low Structure of Transmit R
218. cceecccecessecseceececeeeeeeeeeceeaeeeeaeeeseeaeeseaaeesseeeseaaesseaes 41 Structure of EP01 control register 1 0 ceceeecceeeeeeeeeeeeececaeeeseeeeseeaeeeseaeeseeaeeeseeaeeeeaees 41 Structure of EP01 control register 2 0 eceeeceecececeeeeeeeeececeeeeseeeeseaeeeseaeeseeeeestaeeneaees 42 Structure of EP01 control register 3 sssssseessssesseseseesrissrirssrrrssrrsssrnsstnnstnnnsennnennnrnnnne 42 Structure of EP01 interrupt source register ce eecceeceeeeeeseeececeeeeeeaeeseeeeeetaeeeeaees 42 Structure of EP01 byte number register O ssssseesssesssssssrsssrrssrrnsernnesrnesrnnsrnnnrnnnennnn 43 Structure of EP01 byte number register ecceceeeeesseeeeeeeeeeeeeeeeeeeeesaaeeseeeeeesaeeeeenes 43 Structure of EP01 MAX packet size register e sseseressreesrrssrrrssrrssrrsrrrsrrresre 43 Structure of EP01 buffer area set register s sessseesesssisssresrrrssrrrssrrsrrnrsrnsrrnnsrne 44 Structure of EP02 set register s seseessseesssesssesssesssrrssrtrsstrnssrnsstnnstrnnnnnnnnnnnnnnntnnnnnnnn 45 Structure of EP02 control register 1 ceeceeeeeeeceeeeeeeeeeeeeeeeeeeaeeseeaeeeseaeeseeeeeseaeeeeaees 45 Structure of EP02 control register 2 0 eccececceececeeeeeeeee cece eeeeeeesecaeeeseaeeseeeeeeeaeeneaees 46 Structure of EP02 control register 3 oo eeceeeeeeeeceeeeeeeeeeeeeeeeeeeeeeseaeeeseaeeseeeeesnaeeneaees 46 Structure of EP02 interrupt source register cecceecceeceeeeeeeeeececeeeeeaeeseeeeeeeeaeeeeaees 46 Struct
219. ceeeeeeeeee 96 Table 2 13 2 State in wait MOC eeecccecececeseceeeeeeeeeeeeeceeeeeeaaeeaeeeseaaeseeaeeesesaesseeeeeesaeeeeeneees 100 Table 2 14 1 Setting of programmers when parallel programming ccccceeseeeeteeeeteeees 105 Table 2 14 2 Connection example to flash programmer when serial programming 4 wires cig heel Mein E Biel ee teeter a ideale alee RA eit 105 Table 2 14 3 Setting condition in serial O mode ce cceecsecceseeeeeeeeceeeeeeeeseeseeeessesaaeess 107 CHAPTER 3 APPENDIX Table 3 1 1 Absolute maximum ratings cece cece ete cece eetne ee eee tana ee eee eaaeeeeeetaaeeeeeeeaeeeeeeeeaeeeeeeeea 2 Table 3 1 2 Recommended operating conditions Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted eeeceeeeeeeeeeeeeeeeeeeaeeeeeeeeeeaeeeseneeeseeeeseeeeee 3 Table 3 1 3 Recommended operating conditions Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted 0 eceecceeeeceseeeeeeeeeeeeeeaeeeeeeeeeeaeeseeneeeesaeeeseaeeeee 4 Table 3 1 4 Electrical characteristics 1 Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise Mote ccceeceeccecceeeeeeceeeeeseeeeeeeenseeeeeeeeseeeeeseesseeeeeeeeseeeeeeeeeneneees 5 Table 3 1 5 Electrical characteristics 2 Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C Unless otherwise Noted ee eee eee eeeeee eee eeeeae eee eeeeeaeeeeeeaaaeeeeeeeaaeeeeeeeaaeeeeeeenaees 6 Rev 2 00 Oct 15
220. ces for accessing the buffer BORDY01 Buffer 0 Ready Interrupt Offset address 00h a When selecting Endpoint 00 b When selecting Single Buffer Mode Memory Memory Offset 02A016 02A016 _ _ 00h BSRDY0O 02A816 BORDY01 BRDYO0O HARDWARE FUNCTIONAL DESCRIPTION Memory OFED16 OFED16 15h 000016 00 Disabled to be used 01 002016 004016 006016 02A016 03E016 Fig 27 Example setting of buffer area beginning address B1RDY01 Buffer 1 Ready Interrupt The offset address varies according to the double buffer begin ning address set bit BSIZ01 Offset address 08h when BSIZ01 00 Offset address 10h when BSIZ01 01 Offset address 40h when BSIZ01 10 Offset address 80h when BSIZ01 11 3 Endpoints 02 and 03 Same as Endpoint 01 4 Endpoint 10 Same as Endpoint 00 5 Endpoint 11 Endpoint 11 has only one interrupt source for accessing the buffer BORDY11 Buffer 0 Ready Interrupt Offset address 00h Notes The selected RAM area must be within addresses 004016 to 03FF16 Make sure the buffer area beginning address is set in agreement with the offset address and the number of transmit receive data bytes This is particularly important when in the double buffer mode or when handling 64 byte data c When selecting Double Buffer Mode d When selecting Endpoint 11 when BSIZ01 11 Memory Memory 02A016 ___ 02A0
221. ching to WAIT mode is possible When it is released the MCU returns to the original mode In WAIT mode the timers can operate Remarks This diagram assumes that the 6 MHz signals are applied to XIN pin Fig 145 State transitions of clock Rev 2 00 Oct15 2006 page 99 of 130 REJ09B0338 0200 2RENESAS 38K2 Group FLASH MEMORY MODE The 38K2 group s flash memory version has an internal new DINOR Divided bit line NOR flash memory that can be rewritten with a single power source when Vcc is 4 5 to 5 25 V and 2 power sources when VCC is 3 0 to 4 5 V For this flash memory three flash memory modes are available in which to read program and erase the parallel I O and standard serial I O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit CPU Summary Table 9 lists the summary of the 38K2 group s flash memory ver sion Table 9 Summary of 38K2 group s flash memory version HARDWARE FUNCTIONAL DESCRIPTION This flash memory version has some blocks on the flash memory as shown in Figure 146 and each block can be erased The flash memory is divided into User ROM area and Boot ROM area In addition to the ordinary User ROM area to store the MCU op eration control program the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I O
222. cleared to 0 by clearing EP10 i source register to 0016 Writing to this bit causes no state change errupt errupt USB HUB Endpoint 1 interrupt bit This bit is set to 1 when any one of EP11 i source register s bits at least is set to 1 This bit is cleared to 0 by clearing EP11 i source register to 0016 Writing to this bit causes no state change errupt errupt Suspend interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting 3 ms or more of J state using USB clock fuss at 48 MHz 0 can be set by software but 1 cannot be set Resume interrupt bit This bit is set to 1 when the USB bus state changes from J state to K state or SEO in the resume interrupt enable bit 1 It is also 1 in the condition of internal clock stopped This bit is cleared to 0 by clearing the resume interrupt enable bit Writing to this bit causes no state change Fig 3 4 10 Structure of USB interrupt source register b7 bo fofofofofo Endpoint index register USBINDEX address 001816 Bit symbol Bit name Function At reset H W S W EPIDX 1 0 Endpoint index bit bo Endpoint 0 Endpoint 1 Endpoint 2 Endpoint 3 0 0 1 1 0 1 0 1 0 Address index bit 0 USB function 1 USB
223. completion flag Confirm completion of transmitting 1 byte data with this flag 1 Transmit shift completed Serial I O control register Address OFEO16 b7 bo secon aaor ee BRG counter source selection bit XIN Serial I O synchronous clock selection bit BRG 4 Transmit enable bit Transmit enabled Receive enable bit Receive disabled Serial I O mode selection bit Clock synchronous serial I O Serial I O enable bit Serial I O enabled Baud rate generator Address OFE216 b7 bo Interrupt edge selection register Address OFF316 b7 bO INTEDGE EpRE0DEN gt INT1 interrupt edge selection bit Falling edge active Fig 2 4 15 Registers setting related to transmitting side Rev 2 00 Oct15 2006 page 49 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Receiving side Serial I O status register Address 2716 b7 b0 Ly Receive buffer full flag Confirm completion of receiving 1 byte data with this flag At completing reception 0 At reading out contents of Receive buffer register Overrun error flag 1 When data is ready in Receive shift register while Receive buffer register contains the data Parity error flag 1 When a parity error occurs in enabled parity Framing error flag 1 When stop bits cannot be detected at the specified timing Summing error flag 1 when any one of the following er
224. ct pin P43 ExA1 SRDY pin to con firm a ready status of the data buffer from an external MCU bus This pin functions as a port just after reset The status read select function can be set by a program Status read select P43 ExA1 SRDY CPU channel Communication with 38K2 group CPU When a read write operation is performed from an external MCU bus in address signal ExA0 H the interrupt is generated and the 38K2 group CPU can confirm its access The 38K2 group CPU judges the interrupt source and it starts a data transmission recep tion with an external MCU bus Memory channel Communication with 38K2 group memory multichannel RAM When a read write operation is performed from an external MCU bus in address signal ExA0 L access to the multichannel RAM is performed Then an address of the multichannel RAM is made by the external bus interface and it is increased at each access completion Consequently FIFO access is performed Even if a read write operation is performed in DACK L instead of ExCS L and ExA0 L FIFO access to the multichannel RAM is performed The beginning address and the end address must be set by the CPU in advance 2tENESAS 38K2 Group P33 ExINT pin Any one of the following signals for this pin can be selected TxB_RDY transmit buffer ready output RxB_RDY receive buffer ready output Mch_req memory channel request output Either TxB_RDY or
225. ction bit z 5 page 1 page Fix this bit to 0 System clock selection bit 0 Main clock f Xin 1 fsyn System clock division ratio selection bits Fix this bit to 1 pe dG system clock 8 8 divide mode system clock 4 4 divide mode system clock 2 2 divide mode system clock Through mode tou ued 2h h h h The initial value of bit 1 depends on the CNVss level Fig 3 4 82 Structure of CPU mode register Rev 2 00 Oct 15 2006 page 72 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers Interrupt request register 1 b7 b6 b5 b4 b3 b2 bi bO Interrupt request register 1 IREQ1 Address 3C16 B Name Fonction USB bus reset 0 No interrupt request issued l OIl interrupt request bit 1 Interrupt request issued I J1 USB SOF interrupt 0 No interrupt request issued Ol 3 request bit 1 Interrupt request issued I 2 USB device interrupt 0 No interrupt request issued ie request bit 1 Interrupt request issued O 3 EXB interrupt 0 No interrupt request issued Ol request bit 1 Interrupt request issued l 4 INTo interrupt 0 No interrupt request issued request bit 1 Interrupt request issued O 5 Timer X interrupt 9 No interrupt request issued Ole request bit Interrupt request issued Timer 1 interrupt v No interrupt request issued o request bit Interrupt request issued Timer 2 interrupt 0 No interrupt request iss
226. ction register i 0 tO 6 oo eeeececeeeeeeseeeeeeeeeeteeeeteneeetaes 3 Fig 2 1 4 Structure of Port PO pull up Control register 0 ccccecececseeeceeeeeeseceeeeeeeeeseeaeeeseeeeeeas 4 Fig 2 1 5 Structure of Port P5 pull up control register c cc cecccecseeeceeeeeececeeeeeeeeeeeaeeeeeeeeeas 4 Fig 2 2 1 Memory map of registers related to interrupt ceceeeceeeeeeeeeeeeeceeeeeeeseeeeeeeaeeeees 8 Fig 2 2 2 Structure of Interrupt request register 1 ceec ce ceeseceeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeseaeeeseeeeteas 8 Fig 2 2 3 Structure of Interrupt request register 2 eecccceeeeceeeeeeeeeeeeeeeeeeeeaeeeeeeeeessaeeeeeeeeteas 9 Fig 2 2 4 Structure of Interrupt control register 1 sesssssssssssiresrsssirssrrrsrrrsrrnsrinsrrnnsrrnssrnessrns 9 Fig 2 2 5 Structure of Interrupt control register 2 s ssssssssssssrisssiissrisssissrisssrinssrresrnnssrnnssrnsnnn 10 Fig 2 2 6 Structure of Interrupt edge selection register cccceeeseeeceeeeeeeeeeeeeeeeeeetaeeteeeees 10 Fig 2 2 7 Interrupt operation GiAGraM ee eccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaaeeeeeeseeeeeeeeesseeaeeeeseneeaees 12 Fig 2 2 8 Changes of stack pointer and program counter upon acceptance of interrupt request oud dia fen teea tephevvas cada tp ada eevils lptaeed aes Paerti aed ive ead i Aides 13 Fig 2 2 9 Time up to execution of interrupt processing routine ceeeeeeeeeeeteeeteeeeeteneeees 14 Fig 2 2 10 Timing chart after acceptanc
227. cture of Flash memory control register cceceeseeeeceeeeeeseceeeeeeeeessaeeneeeees 104 Fig 2 14 4 Rewrite example of built in flash memory in standard serial I O mode 107 Fig 2 14 5 Connection example in standard serial I O mode 1 108 Fig 2 14 6 Connection example in standard serial I O mode 2 ccccceeeeeeeeeeeeeeteeeeeeees 108 Fig 2 14 7 Connection example in standard serial I O mode 3 ccccceseeeeeeereeeetteeeeeeees 109 Fig 2 14 8 Example of rewrite system for built in flash memory in CPU rewrite mode 110 Fig 2 14 9 CPU rewrite mode beginning release flowchart cccsceeeeeeeeseeeeeeeeeeesteeeeeees 111 CHAPTER 3 APPENDIX Fig 3 1 1 Output switching characteristics measurement circuit 20 cece eee eeeeeeeeeeeeeeteeeees 11 Fig 3 1 2 USB output switching characteristics measurement circuit 1 for DO D1 D2 low speed D1 D2 full speed 13 Rev 2 00 Oct 15 2006 page 9 of 14 7tENESAS REJ09B0338 0200 38K2 Group List of figures Fig 3 1 3 SB output switching characteristics measurement circuit 2 for DO D1 D2 full speed D1 D2 low speed 13 Figs S204 Timing Chart T ccteveccaneceedavaae tied avec ERR ET Sea AERE aaaeed Abas 14 Fa s LS TAMING Mart 2 ic costes ieee tees e E RE EEE dling desmasall vanes ddannedetaadindeesdiaaliees 15 POS tO MMOG GHAN cc errr ereererr en erretrer reer pe tern peeererre per err eer Prrererrerr rrr rererrrre
228. cuit Connect a ceramic resonator or a quartz crystal oscillator between the XIN and XOUT pins to set the oscillation frequency lf an external clock is used connect the clock source to the XIN pin and leave the XOUT pin open USBVREF USB reference power source e Power source pin for USB port circuit In Vcc 4 00 to 5 25 V use the built in USB reference voltage circuit In Vcc 3 60 to 4 00 V apply 3 3 V power supply from the external because use of the built in USB reference voltage circuit is prohibited in this voltage range In Vcc 3 00 to 3 60 V connect this pin to Vcc because use of the built in USB reference voltage circuit is prohibited in this voltage range TrON USB reference voltage output e Output pin to pull up DO by 1 5 KQ external resistor DO DO USB upstream VO e USB upstream I O port e USB input level e USB output level output structure Di D1 D2 D2 USB down stream I O USB downstream I O port e USB input level e USB output level output structure POo P07 I O port PO e 8 bit I O port e I O direction register allows each pin to be individually programmed as either input or output CMOS compatible input level CMOS 3 state output structure e Pull up control is enabled e Key input pins key on wake up interrupt P10 DQo ANo P17 DQ7 AN7 I O port P1 e 8 bit I O port e I O direction register allows each pin to be individually programmed
229. d code D016 and the block address in the second bus cycle that follows the block erase erase and erase verify operation starts for the block address of the flash memory to be specified Whether the block erase operation is completed can be confirmed by reading the status register or the RY BY Status Flag of flash memory control register At the same time the block erase opera tion starts the read status register mode is automatically entered so that the contents of the status register can be read out The status register bit 7 SR7 is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation In this case the read status register mode remains active until the read array command FF 16 is writ ten The RY BY Status Flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status reg ister bit 7 After the block erase ends erase results can be checked by read ing the status register For details refer to the section where the status register is detailed Rev 2 00 Oct15 2006 page 106 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Write 2016 2016 D016 Block address 2016 Erase all blocks write D016 Block erase Status register read 1 Erase error YES Erase completed Fig 150 Erase flowchart 2tENESAS 38K2 Group Status Register SRD The status regist
230. data transfer complete Buffer O ready read write enabled state Buffer 1 ready read write enabled state Transfer error EP02 At Endpoint 02 data transfer complete Buffer O ready read write enabled state Buffer 1 ready read write enabled state Transfer error EP03 At Endpoint 03 data transfer complete Buffer O ready read write enabled state Buffer 1 ready read write enabled state Transfer error EP10 At Endpoint 10 data transfer complete Buffer ready read write enabled state Control transfer completed Status stage transition SETUP buffer ready read enabled state Control transfer error EP11 At Endpoin 11 data transfer complete Buffer O ready write enabled state SUS At suspend signal detection After enabling the USB module USBE 1 an interrupt request occurs when 3 ms J state is detected in D0 DO port Equivalent to 144 000 clock length when fusB 48MHz RSM Rev 2 00 Oct15 2006 page 30 of 130 REJ09B0338 0200 At resume signal detection After enabling the USB module USBE 1 and resume interrupt RSME 1 an interrupt request occurs when a bus state change J state to SEO or K state is detected in DO port 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION EPXXREGS5 USBIREQ USBICON EPOOREQ BRDY00 EPOOE TENDOO eae USB device CTSTSOO m interrupt request BSYDY00 ERROO
231. de System clock 8 MHz 5 00 System clock 6 MHz 5 00 Analog power source voltage PVcc DVcc Vcc Parameter Analog power source voltage VCCE Vcc Analog reference voltage VREF Analog reference voltage USBVREF Vcc 3 6 to 4 0 V Vcc 3 0 to 3 6 V Power source voltage Vss Analog power source voltage PVss H input voltage POo P07 P24 P27 P50 P57 0 8Vcc Vcc P60 P63 H input voltage P10 P17 P30 P37 P40 P43 0 8VccE VccE H input voltage RESET Xin CNVss CNVss2 0 8Vcc se H input voltage DO DO D1 D1 D2 D2 20 3 6 L input voltage POo P07 P24 P27 P50 P57 0 0 2Vcc P60 P63 L input voltage P10 P17 P30 P37 P40 P43 0 0 2VCCcE L input voltage RESET XIN CNVss CNVss2 0 0 2Vcc L input voltage DO DO D1 D1 D2 D2 0 8 lt lt S SISS SISIK lt lt II lt lt lt lt Rev 2 00 Oct15 2006 page 3 of 99 2tENESAS REJ09B0338 0200 38K2 Group APPENDIX 3 1 Electrical characteristics L Ver Table 3 1 3 Recommended operating conditions Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter H total peak output current Note 1 POo P07 P24 P27 P50 P57 P60 P63 H total peak output current Note 1 P10 P17 P30 P37 P40 P43 L total peak output curr
232. determines whether additions and subtractions are executed in binary or decimal Binary arithmetic is executed when this flag is 0 decimal arithmetic is executed when it is 1 Decimal correction is automatic in decimal mode Only the ADC and SBC instructions can execute decimal arithmetic HARDWARE FUNCTIONAL DESCRIPTION Bit 4 Break flag B The B flag is used to indicate that the current interrupt was generated by the BRK instruction The BRK flag in the processor status register is always 0 When the BRK instruction is used to generate an interrupt the processor status register is pushed onto the stack with the break flag set to 1 Bit 5 Index X mode flag T When the T flag is O arithmetic operations are performed between accumulator and memory When the T flag is 1 direct arithmetic operations and direct data transfers are enabled between memory locations Bit 6 Overflow flag V The V flag is used during the addition or subtraction of one byte of signed data It is set if the result exceeds 127 to 128 When the BIT instruction is executed bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag Bit 7 Negative flag N The N flag is set if the result of an arithmetic operation or data transfer is negative When the BIT instruction is executed bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag Table 4
233. disable output delay time after write td R Men In cycle mode USB function not operating Mch_req enable output delay time after read USB function operating td W Men In cycle mode USB function not operating Mch_req enable output delay time after write USB function operating Table 3 1 14 Switching characteristics of external bus interface EXB 2 Vcc 3 00 to 4 00 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Typ Parameter Data output enable time after read Data output disable time after read Data output enable time after ExDACK Data output disable time after ExDACK In cycle mode Mch_req disable output delay time after read td W Mdis In cycle mode Mch_req disable output delay time after write td R Men In cycle mode USB function not operating Mch_req enable output delay time after read USB function operating td W Men In cycle mode USB function not operating Mch_req enable output delay time after write USB function operating Rev 2 00 Oct 15 2006 page 12 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 1 Electrical characteristics L Ver Table 3 1 15 Switching characteristics USB ports Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Limits Typ Symbol Parameter tfr D D USB full speed output rising time CL 50 pF tff D D USB full speed output
234. e A value by counting pulses input to P5 1 CNTRo pin with the timer A reference value Specifications The pulse is input to the P5 1 CNTRo pin and counted by the timer X A count value is read out at about 2 ms intervals the timer 1 interrupt interval When the count value is 28 to 40 it is judged that the input pulse is valid Because the timer is a down counter the count value is compared with 227 to 215 Note Note 227 to 215 255 initial value of counter 28 to 255 40 28 to 40 means the number of valid value Figure 2 3 17 shows the judgment method of valid invalid of input pulses Figure 2 3 18 shows the related registers setting Figure 2 3 19 shows the control procedure Input pulse i lt gt 71 4 us or more 71 4 us 50 us or less 14 kHz or less 14 kHz i 20 kHz or more Invalid rie Valid Invalid 71 4 us 50 us 40 counts Fig 2 3 17 Judgment method of valid invalid of input pulses Rev 2 00 Oct 15 2006 page 33 of 112 2tENESAS REJ09B0338 0200 38K2 Group ICON1 IREQ1 APPLICATION Timer X mode register address 2316 bO b7 m I yds fo Ea Timer X operating mode Event counter mode gt CNTRo active edge selection Falling edge count Timer X count Stop Clear to 0 when starting count Prescaler 12 address 2016 b7 bO Timer 1 address 2116 b7 bO 249 Set division ratio 1 Prescaler X address 2416 Timer X addre
235. e each calculation To check for a borrow the C flag must be initialized to 1 before each calculation Set D flag to 1 ADC or SBC instruction NOP instruction SEC CLC or CLD instruction Fig 3 2 7 Status flag at decimal calculations 4 JMP instruction When using the JMP instruction in indirect addressing mode do not specify the last address on a page as an indirect address 5 Multiplication and Division Instructions e The index X mode T and the decimal mode D flags do not affect the MUL and DIV instruction e The execution of these instructions does not change the contents of the processor status register 6 Ports The contents of the port direction registers cannot be read The following cannot be used e The data transfer instruction LDA etc e The operation instruction when the index X mode flag T is 1 e The addressing mode which uses the value of a direction register as an index e The bit test instruction BBC or BBS etc to a direction register e The read modify write instructions ROR CLB or SEB etc to a direction register Use instructions such as LDM and STA etc to set the port direction registers 7 Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction The number of cycles required to execute an instruction is shown in the list of machine instruc
236. e hardware Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 3 4 22 Structure of EP10 control register 1 b7 bo fofofofofofo EP11 control register 1 EP11CON1 address 001A16 Bit symbol Bit name Function At reset H W S W PID11 Response PID bit b1 bO 0 1 0 0 0 NAK 0 1 Automatic response NAK DATAO DATA1 1 X STALL Not used Write 0 when writing 0 is read when reading State remaining Fig 3 4 23 Structure of EP11 control register 1 b7 bO ofolofolofo o EPOO control register 2 EPOOCON2 address 001B16 Bit symbol Bit name Function At reset H W S W BVALOO Buffer enable bit 0 NAK transmission SIE is disabled to read a buffer 0 1 Transmitting receiving data set state SIE is possible to read from write to a buffer At reception of SETUP token This bit is cleared to O by the hardware Write 0 when writing 0 is read when reading e remaining Fig 3 4 24 Structure of EP00 control register 2 Rev 2 00 Oct 15 2006 page 47 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers b7 bo fofofofofofofo EP01 control register 2 EPO01CON2 address 001B16 At reset H W S W BOVALO1
237. e number register 0 Rev 2 00 Oct15 2006 page 56 of 99 2tENESAS REJ09B0338 0200 38K2 Group 3 4 List of registers EP01 byte number register 1 EPO01BYT1 address 001F 16 APPENDIX Bit symbol Bit name Function At reset H W S W B1BYT01 6 0 IN Transmit byte number bit Single buffer mode These bits are invalid Double buffer mode Set the transmitting byte number of buffer 1 0 OUT Receive byte number bit Single buffer mode These bits are invalid Double buffer mode The received byte number of buffer 1 is automatically set Not used Write 0 when writing 0 is read when reading Fig 3 4 47 Structure of EP01 byte number register 1 EP02 byte number register 1 EPO2BYT1 address 001F 16 e remaining Bit symbol Bit name Function At reset H W S W B1iBYT02 6 0 IN Transmit byte number bit Single buffer mode These bits are invalid Double buffer mode Set the transmitting byte number of buffer 1 0 OUT Receive byte number bit Single buffer mode These bits are invalid Double buffer mode The received byte number of buffer 1 is automatically set Not used Write 0 when writing 0 is read when reading Fig 3 4 48 Structure of EP02 byte number register 1 EP03 byte number register 1 EPO3BYT1 address 001F 16 Sta
238. e of External I O configuration register Rev 2 00 Oct15 2006 page 79 of 130 REJ09B0338 0200 RENESAS State remaining 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION Index 0116 Transmit Receive buffer register RXBUF TXBUF address 003416 Bit symbol Bit name At reset Function H W S W RXBUF TXBUF The data received from an external bus is written here at the rise timing of external write signal The data transmitted to an external bus is written here at the timing of internal CPU write or memory write 0 ransmit buffer register TXBUF The receive buffer register RXBUF contents can be read out by reading to this address with the CPU The data which the CPU has written to this address is stored in the However do not perform write operation with the CPU to this address if the memory channel direction control bits of memory channel operation mode register is 102 transmit mode and the memory channel status bits of EXB interrupt source register are 012 or 102 memory channel being operating Fig 116 Index01 low Structure of Transmit Receive buffer register b7 bO fofofofofo Index 0216 Memory channel operation mode register MCHMOD address 003416 Bit symbol Bit name At reset Function H W S W MC_DIR 1 0 Memory channel direction control bit Operation disabled Receive mode
239. e of interrupt request cceecceeeeeeeeeeeeeteteeeteneeees 14 Fig 2 2 11 Interrupt control diagram 0 cece ce eeceeeceeeeeeeeeeeeeeeeeeaeeeeeaeeeeeaaeeseeeeessaeeseeeeeessaeeeseaeees 15 Fig 2 2 12 Example of multiple interrupts ecceeeseeeceeeeeeeeeeeeeeeeeeeeaeeseeeeesaaaeseeeeeetiaaeeneetes 17 Fig 2 2 13 Connection example and port PO block diagram when using key input interrupt PE A ind sires tatiets odode ait etl eich ace Maen 19 Fig 2 2 14 Registers setting related to key input interrupt corresponding to Figure 2 2 13 a E leet d eins weeded di ee ease eee ee ee 20 Fig 2 2 15 Sequence of changing relevant register ccceeeeeeeeeee cesses eeeeeeeeaeeeeeeeeeeeaaeeneneees 21 Fig 2 2 16 Sequence of check of interrupt request Dit cceecceceeeeeeeeeeeseceeeeeeeeesetaeeeeeeeees 22 Fig 2 3 1 Memory map of registers related to timers cceeceeceteee cents eeeeeeeeeaeeeeeeeeeteaeeeteneees 23 Fig 2 3 2 Structure of Prescaler 12 PreSCaler X ccccccscscccccssecceceecesceeeeesseeeeeeeessseeeeesseaaees 23 Fig 2 3 3 Structure vof TIMET A siscesudecsccatdecesaeeneetestecgulitnssscedsasessbudveceasnctaueh ss eagedetsuceteteaisesseaseasaeets 24 Fig 2 3 4 Structure of Timer 2 Timer X o ccececscccccsesseececeeeeeeeeeeeaeeeeeeeaeeeeesseneeeeessstaeeesesenaees 24 Rev 2 00 Oct 15 2006 page 7 of 14 7tENESAS REJ09B0338 0200 List of figures 38K2 Group Fig 2 3 5 Structure of Timer X mode r
240. e on the system board in the standard serial I O mode and the control example in the CPU rewrite mode are described below 1 Control pin connection example on the system board in standard serial I O mode As shown in Figure 2 14 4 in the standard serial I O mode the built in flash memory can be rewritten with the microcomputer mounted on board Connection examples of control pins P40 ExDREQ RxD P41 ExDACK TxD P42 ExTC Scix P43 ExA1 Srpy P16 CNVss and RESET pin in the standard serial I O mode are described below RS 232C Serial programmer Fig 2 14 4 Rewrite example of built in flash memory in standard serial I O mode Table 2 14 3 shows the setting condition in the standard serial I O mode Table 2 14 3 Setting condition in serial I O mode 38K2 Group flash memory version TE Pin name Pin number CNVss VPe Note 7 4 50 to 5 25 V Pie 5 Vcc P42 ExTC Scik 53 Vcc RESET 8 Edge from Vss to Vcc Note CNVss Vere is not Vcc but a voltage when programming Rev 2 00 Oct 15 2006 page 107 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory When control signals are not affected to user system circuit When the control signals in the standard serial I O mode are not used or not affected to the user system circuit they can be connected as shown in Figure 2 14 5 Target board x1 Not used or to user system circuit M38K29F8FP HP M38K29F8LFP LHP TxD P41 ExDACK ScL
241. ead when reading HRWUE HUB upstream port remote 0 Disabled 010 wakeup output enable bit 1 Enabled State remaining Fig 3 4 56 Structure of HUB interrupt source enable register b7 bo fofofofofol HUB interrupt source register HUBIREQ address 002916 Bit symbol Bit name Function At reset H W S W DP1 HUB downstream port 1 This bit is set to 1 when any one of DP1 interrupt 0 interrupt bit source register s bits at least is set to 1 This bit is cleared to 0 by clearing DP1 interrupt source register to 0016 Writing to this bit causes no state change HUB downstream port 1 This bit is set to 1 when any one of DP2 interrupt interrupt bit source register s bits at least is set to 1 This bit is cleared to 0 by clearing DP2 interrupt source register to 0016 Writing to this bit causes no state change Not used Write 0 when writing 0 is read when reading HUB upstream port remote 0 Remote wakeup being not output wakeup output enable bit 1 Remote wakeup being output This bit change is not for a interrupt source When detecting 2 5 us or more of K signal on a downstream port in Hub suspended state K signal is output on from a upstream port and this bit is simultaneously set to 1 0 can be set by software but 1 cannot be set
242. eceeeseeetee 117 159 Timing for erase all DIOCKS ssiccccccescescevsstiecesit esecerve ataa aad a aaaea 118 160 Timing for COWNOAG ecceccceceeeeeeee cece eeeeeeeceeaeeeeeaaeseceeeeeeaaeeseeeeseaaeseseeeeesiaeeeeeeeeseas 119 161 Timing for version information output cc eeeeeeeeeeceteeeeeeeeeeeeeeetaaeeseeeeeeeaaeeeeneee 120 162 Timing for Boot ROM area OUtpUt c ce ececccecceeeeeeeeceeeeeeeeaeeceeeeeeeaaeeeeeeeeesaeeeseneeeeaas 120 163 Timing tor D Ch ek e csissscs Asie eeeccochedecececnid a 121 164 ID code storage addresses 00 eee cece eect eee eeee cette teeaeeeeeeteaeeeeeeeeeaeeeeeeseeeeaeeeeeeneaaees 121 165 Full status check flowchart and remedial procedure for errors s s s 124 166 Example circuit application for standard serial I O mode ccscccceeeesteeeeeeenees 125 167 Definition of A D conversion ACCULACY cecceeeeeeeeneeceeeeeeeeeeeeeeeeeeeaeeseeeeeeeaeeeteneees 127 168 A D conversion equivalent circuit cc ceee ce eeceeeeeeeee cece eeeeeeeeecaeeeeaeeseeieeesaaeeeeneees 130 169 A D Conversion timing Chart ec eee ee cence eee eeeeee eee eeeaaeeeeeeeeaaeeeeeseaaaeeeeeeeaeeeeeseaaas 130 CHAPTER 2 APPLICATION Fig 2 1 1 Memory map of registers related to I O port ceececeeeseceteeeeeeeeececeeeeeeeeeseeeeeeeeeeees 2 Fig 2 1 2 Structure of Port Pi i 0 to 6 ccc ceeceeeeceneeeeeeee scenes eeseaeeeeneeeeseaeeeseeeeescaeeeseeeeeaas 3 Fig 2 1 3 Structure of Port Pi dire
243. eceive buffer register ceesceeeeeeeeeeees 80 Fig 117 Index02 low Structure of Memory channel operation mode register 0 80 Fig 118 Index03 low Structure of Memory address counter ccceeeeeeeseeeeeeeeeeeeteeeteeeeees 80 Fig 119 Index03 high Structure of Memory address counter ccecccceeeeeeeeeeeeeeeteeeeneeees 81 Fig 120 Index04 low Structure of End address register c ccccesceeeeeeeeeeeeeeeeeeeeseteeeeeaeees 81 Fig 121 Index04 high Structure of End address reQiSter c cccccceceeeeeeseeeeeeeeeeeseteeeeeeeeees 81 Fig 122 CPU channel receiving Operation ceececeeceeeeeeeeeeeeeeeeeeeeeeeaeeseeeeeesaeeseeneeetsaeeeneaeees 82 Fig 123 CPU channel tranmitting operation ceeecececeeeeeeeee cece eeeeeeeceeeeeesaaaeseeeeeestaeeseeeens 83 Fig 124 Memory channel receiving Operation 1 oe eceeceeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeseenaeeeeeeeeaeees 84 Fig 125 Memory channel receiving Operation 2 oe eceeeeeeeeceeeeeeeeeeeeeeseeeeeeeeeeeeeaaeeeeneeeaees 85 Fig 126 Memory channel receiving Operation 3 ceccceeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeneeeetaeeeeeneeees 86 Fig 127 Memory channel tranmitting operation 1 cceeseeeeeeeeeeeeeeceeeeeeeeeeteeeeeestaeeeeneeens 87 Fig 128 Memory channel tranmitting Operation 2 ooo ceeee eee eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaaees 88 Fig 129 Multichannel RAM timing diagram NO wait 0 eee ceeeeeeeeeeeeeeeeeaeeeeeteaae
244. ecified with addresses As to A23 will be output se quentially from the smallest address first synchronized with the fall of the clock SRDY BUSY Fig 162 Timing for Boot ROM area output Rev 2 00 Oct 15 2006 page 120 of 130 2tENESAS REJ09B0338 0200 38K2 Group ID Check This command checks the ID code Execute the boot ID check command as explained here following HARDWARE FUNCTIONAL DESCRIPTION 1 Transfer the F516 command code with the 1st byte 2 Transfer addresses Ao to A7 As to A15 and A16 to A23 0016 of the 1st byte of the ID code with the 2nd 3rd and 4th respec tively 3 Transfer the number of data sets of the ID code with the 5th byte 4 Transfer the ID code with the 6th byte onward starting with the 1st byte of the code Fa bee ol woe Osea oY SRDY BUSY Fig 163 Timing for ID check ID Code When the flash memory is not blank the ID code sent from the se rial programmer and the ID code written in the flash memory are compared to see if they match If the codes do not match the command sent from the serial programmer is not accepted An ID code contains 8 bits of data Area is from the 1st byte addresses FFD416 to FFDA16 Write a program into the flash memory which already has the ID code set for these addresses Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 _ ee eee ID3 eC ROM code protect control
245. ectrolytic capacitor and a 0 1 uF capacitor ceramic type capacitor connected in parallel eln Vcc 3 0 to 3 6 V operation connect the USBVrer pin directly to the Vcc pin in order to supply power to the USB port circuit In addition you will need to disable the built in USB reference voltage circuit in this operation set bit 4 of the USB control register to O If you are using the bus powered supply in this condition the DC DC converter must be placed outside the MCU eIn Vcc 4 00 to 5 25 V operation do not connect the external DC DC converter to the USBVrer pin Use the built in USB reference voltage circuit USB Communication ein applications requiring high reliability we recommend providing the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB communication from being terminated unexpectedly for example due to external causes such as noise Rev 2 00 Oct 15 2006 page 26 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 3 2 7 Notes on A D converter 1 Analog input pin Make the signal source impedance for analog input low or equip an analog input pin with an external capacitor of 0 01 uF to 1 uF Further be sure to verify the operation of application products on the user side Reason An analog input pin includes the capacitor for analog voltage comparison Accordingly when signals from signal source with high impedance are inp
246. ed hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but
247. ed without an ID check Data reception time out SR9 This flag indicates when a time out error is generated during data reception If this flag is attached during data reception the re ceived data is discarded and the MCU returns to the command wait state Definition SRD1 bits Status name 4 g SR15 bit7 Boot update completed bit Update completed Not Update SR14 bit6 Reserved SR13 bit5 Reserved SR12 bit4 Checksum match bit Mismatch SR11 bit3 SR10 bit2 ID check completed bits 00 Not verified 01 Verification mismatch 10 Reserved 11 Verified SR9 bit1 Data reception time out Time out Normal operation Reserved SR8 bit0 Rev 2 00 Oct15 2006 page 123 of 130 REJ09B0338 0200 RENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION Full Status Check Results from executed erase and program operations can be known by running a full status check Figure 165 shows a flow chart of the full status check and explains how to remedy errors which occur Read status register Execute the clear status register command 5016 to clear the status register Try performing the operation one more time after confirming that the command is entered correctly Should an erase error occur the block in error cannot be used Should a program error occur the block in error cannot be used
248. edure of Serial I O x This bit is not used here Set it to O or 1 arbitrarily Initialization SIOCON Address OFE016 110110002 Serial I O set UARTCON Address OFE116 bit4 lt 0 Address OFE216 Address 3F16 bit3 Serial I O transmit interrupt Disabled Address 0A16 bit3 Address 0Bis lt xxxx1xxx2 CS signal output port set H level output co y P5 Address 0A16 bit3 lt O CS signal output level to L set bi gt Serial I O transmit interrupt IREQ2 Address 3Die bit8 lt 0 request bit set to 0 TB RB Address 2616 lt transmission Transmission data write l data Start of transmit 1 byte data Judgment of completion of transmitting 1 byte data Use any of RAM area as a counter for counting the number of transmitted bytes Judgment of completion of transmitting the target number of bytes Return the CS signal output level to H when transmission of the target number of bytes is completed P5 Address 0A16 bit3 lt 1 Fig 2 4 23 Control procedure of Serial I O Rev 2 00 Oct 15 2006 page 55 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 3 Cyclic transmission or reception of block data data of specified number of bytes between two microcomputers Outline When the clock synchronous serial I O is used for communication synchronization of the clock and t
249. eeeeaees 82 RENESAS 38K2 Group List of tables List of tables CHAPTER 1 HARDWARE Table 1 Pin GOSCrIPHOM ce cectscteercecsetacceccepetteete epeti ceed ec deladec aeeel laced epettnbedssheleeeessobeliescgepelutnedepenlveresealt 4 Table 2 List of 38K2 group products L Version oo eee eee eeeneeeeeeecaeeeeeeeaeeeeeeeeaaeeeeeteaaaeeeeseeaas 6 Table 3 Push and pop instructions of accumulator or processor status register 4 8 Table 4 Set and clear instructions of each bit of processor status register ceee 9 Table5 I O ports TUNCONS yisssscctidensnarieiiceteett aa e a aa Re e Naa aaa a a eia 13 Table 6 Interrupt vector addresses and priority ssssssssssssssirssesrrssssirnssstinnssntinnnnntnnnnnntnnnnnne 17 Table 7 USB interrupt Sources s sseesssssseessrsssrrssrrnertrnetnnetintrnnstintsttnsstessttnsstnnstnnstunsenu nenun nnt 30 Table 8 HUBintemru pt SOULCES essc SEE EE EE 61 Table 9 Summary of 38K2 group s flash memory version sssssssessssisssisssrsssrrsrrrrsrressrressrns 100 Table 10 List of software commands CPU rewrite mode sssssssesessssrsesssessiserrssrressrrssrens 105 Table 11 Definition of each bit in status register sessessessirssrrsssrrssrrsssrrssrnsrrnsrrnnsrrnssrn 107 Table 12 Description of pin function Standard Serial 1 0 Mode cccccceeseeeeeteeeeeteeeees 113 Table 13 Software commands Standard serial I O mode ceeeeeeeeseeeeeeeeeeeeeeteaeeeteneees 115 Table 14 Statu
250. eeeeeeceeeeeeaeeseeeeeetiaaeeeeeeeees 46 Fig 3 4 20 Structure of EP02 control register 1 ecccceceeceeeeeeeeeeeeeeeeeeceeeeeeeaeeseeeeeeseaaeeneneeess 46 Fig 3 4 21 Structure of EPO3 control register 1 eeceeceeceeeeeeeceeeeeeeeeceeeeesaeeseeeeeeseaeeneeeees 46 Fig 3 4 22 Structure of EP10 control register 1 eeccecseeeeeeeeeeceeeeeeeeeseeeeeeeaeeseeeeeesiaaeeteneeens 47 Fig 3 4 23 Structure of EP11 control register 1 cecceecseeeseeeceeeeeeeeeeseeeeeeeaaeseeeeeesiaaeeneneees 47 Fig 3 4 24 Structure of EPOO control register 2 eeecccecceeesceeeeeeeeeeeeeeceeeeeeeaeeseeeeeeseaeeneeeees 47 Fig 3 4 25 Structure of EPO1 control register 2 ecccceceeeeeeeececeeeeeeeeeeeeeeeeeaeeseceeeesiaaeeneneees 48 Fig 3 4 26 Structure of EP02 control register 2 ccccceceeeeeseeeeeeeeeeeeeeeseeeeeeaeeseeeeeeseaaeeneneeess 48 Rev 2 00 Oct 15 2006 page 10 of 14 RENESAS REJ09B0338 0200 38K2 Group Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Rev 2 00 Oct15 2006 page 11 of 14 REJ09B0338 0200 List of figures 3 4 27 Structure of EPO3 control register 2 oo ceccceeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeseeeeseeeessaees 48 3 4 28 Structure of EP1
251. eeeeeeeeceeeeeeeaeeeeeeeeesaeeeneneees 44 Fig 2 4 10 Serial I O connection examples 1 ccceceececceeeeeeeeeeeeeeeeeeaeeseeeeessaeeseeeeeesiaeeeseneees 45 Fig 2 4 11 Serial I O connection examples 2 eccccececceeeeeeeseeeeeeeeeeeaeeeeeeeeesaeesseneeetiaeeeseaeees 46 Fig 2 4 12 Serial I O transfer data format ccecceecseeeceee cesses seers eeeeaeeseeeeesseaeeseeeeeesnaeeeneeees 47 Fig 2 4 13 Connection diagram 0 ceeeecceeecceeeceeeeeeeaeeeeeeeeeceaeeeeeaaeeseaeeeeeaaeeseeeeseaaaeseeeeeesiaeeseaeees 48 Fo 2414 TMNT enar eina cd ceeded a a E E EE E E AE EEE 48 Fig 2 4 15 Registers setting related to transmitting side oer renee 49 Fig 2 4 16 Registers setting related to receiving side eee eeteeeeeenneeeeeeeeaeeeeeeenaaeeeeeeeaees 50 Fig 2 4 17 Control procedure of transmitting side cceccceeceeeeeeeeeeeeeeeeeeeeeeaeeteeeeeettaeeeteeeees 51 Fig 2 4 18 Control procedure Of receiving side cceecececeeceeeeeteceeeeeeeaeeeeeeeeeteaeeeeeeeeessaeeneeaeees 52 Fig 24 19 Connection CAG FAM 3 22hesnscvendieids deeteeessaavehukiesctdedtens tulianstcaeeiaua TAE Aa aaa Aaa eaaa 53 Fo 2420 Timing CMA unciis iira r e EE EE E E EEEE EE EEAS 53 Fig 2 4 21 Registers setting related to Serial O essssssssssesrisssrssssrsssirsrirssrisssrnssrrnssrnnssrnsns 54 Fig 2 4 22 Setting of serial I O transmission data ceccceeeeeeeee ee eeeeeeeeeeeeeaeeeeeeeeetiaeeeeeeeees 54 Fig 2 4 23 Control procedure of Serial 1 0
252. eeeeeeeeeaeeeeeeeeeeeaeeeeeaeeeeaees 55 3 4 42 Structure of EP01 byte number register O cceeceececeeeeeeeeeeeeeeeeeeeeeeeeeeeeeetaeenenes 55 3 4 43 Structure of EP02 byte number register O cccececceceeeeeeeeeeeeeeeeeeeaeeteeeeeeseaaeeeenes 55 3 4 44 Structure of EP03 byte number register O ceeeecceceeeeeeeneeeeeeeeeeeaeeseeeeeeseaaeeeeees 56 3 4 45 Structure of EP10 byte number register 0 cccceceececeeeeeeeeeeeeeeaeeeseneeeseeeeeeaaeeseaees 56 3 4 46 Structure of EP11 byte number register O 0 0 ceeecceceeeeeeneeeeeeeeeeeeeeseeeeeeseaaeenenes 56 3 4 47 Structure of EP01 byte number register 1 0 ceceececeeeeeeeeeeeeeeeeeeeeeseeeeeetaaeeeeees 57 3 4 48 Structure of EP02 byte number register 1 cceceececeeeeeeeeeeeeeeeeeeeeeteeeeeeseaaeenenes 57 3 4 49 Structure of EP03 byte number register 1 ceceececeeeeeeeneeeeeeeeeeeeeeseeeeeeseaaeeeenes 57 3 4 50 Structure of Prescaler12 Prescaler X wo ccccccccccccccccccececececaeeeseeeeeeesseeeseeeeeeeeeeeeeeeeeees 58 3 4 51 Structure Of Timer M wscititeseecseas iat Arvieeeccovie cs ictaeesiad austeneioneede as ENa TaN aeeai 58 3 4 52 Structure of Timer 2 Timer X cccccccccssscsesccececsececeececececeeeeeceeeceeaeaeaeuauauaeeseeeeeseseeecs 59 3 4 53 Structure of Timer X mode register ceeeeceeseeeeeeeneeeceeeeeeeeeeseeeeesaeeseeeeeessaeeesenes 59 3 4 54 Structure of Transmit Receive buffer register cccceceeeseeeeeeeeeseeeseeeeeesee
253. eeeeeeeeeeeceaeeeeeaaeeceeeeeeeaaeeseaeeeseaaaesseneeessaaesseaeees 99 Fig 146 Block diagram of built in flash Memory cece eee cent eeeeeeeaeeeeeeeaaeeeeeeeeaaeeeeeeeaaas 101 Fig 147 Structure of flash Memory Control reQiSter cceeeeceeeeeeeeeeceeeeeeeeeeeteeeeeeeeaaeeeenees 102 Rev 2 00 Oct 15 2006 page 6 of 14 RENESAS REJ09B0338 0200 38K2 Group Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig List of figures 148 CPU rewrite mode set release flowchart ceeeeeeceeeeeeeenee tener eeeeaaeeeeneeeseaeeteneeeees 103 149 Program TlOWGCMAN iiseccecies shee cevedst arecss dase N SS 105 150 Erase TlOWCMaM miari oraaa a E A e a a ches E a AREE 106 151 Full status check flowchart and remedial procedure for errors s ssssscseses 108 152 Structure of ROM code protect control register ssesssssssssrrsssrnssrrsserrsrresrressres 109 153 ID code Store addresses wiceniesececteecetienetsaeceuhttnnedee cnt ea RN A E ERRER idee 110 154 Pin connection diagram in standard serial I O mode 1 114 155 TIMING for page readin i chant ad 116 156 Timing for reading status register ee eeeeeee eee eeeeeeeeeeeeaeeeeeeeeaaeeeeeseaaeeeeseeaas 116 157 Timing for Clear status register oo cece ee eeeeeeeeeeeeeeaaeeeeeeeaaeeeeeseaaaeeeeeeenaeeeeeseeaas 117 158 Timing for page program ececeeeecececeeeeeeeeeseeeeeeeaeeeeceeeecaaeeeeeeeeseaeseseeees
254. eeeeeees 60 3 4 55 Structure of Serial I O status register ccceeceeeeseeececeeeeeeeeeeeeeeeseaeesecaeeessaeeeeeaees 60 3 4 56 Structure of HUB interrupt source enable regiSter cccceeeeeeeeeseeeeeeeeeeeseeeeenees 61 3 4 57 Structure of HUB interrupt source register ceeeeeeceeeeeeeeeeeeeeeeeeaeeseeeeeeesaaeeeenes 61 3 4 58 Structure of HUB downstream port index register 0 cccceceseeeeeeeeeeeeeeeeeaeeeeenees 61 3 4 59 Structure of DP1 interrupt source register ceceececeeeeeeeeeeeeeeeeeeeeeeseeeeeessaaeenenes 62 3 4 60 Structure of DP2 interrupt source register cccececeeeceeeeeeeeeeeeeeeneeeseeeeeeseaeeeenes 63 3 4 61 Structure of DP1 Control register 0 cccccecceeeeeeeeeeeeeeeeaeeeeeeeeeeeaeeeseeeeeseaeeeeeaaeeeeaees 64 3 4 62 Structure of DP2 Control register cccceeeececeeeeeeeeeeeeeeaeeeeeeeeeeaaeeeseneeessaeeeseaeessaees 64 3 4 63 Structure of DP1 status register ececcccecceeeseeeeeeeceeceaeeeeeeeeeeeeeeeeeaaeeeeeeeeteaeeesaaes 65 3 4 64 Structure of DP2 status register ceeccccecceeceeeeeeeeeeeeeeeeeeaeeeeeeeeesaeeeseeeeesaeeeeeees 65 3 4 65 Structure of EXB interrupt source enable register ccceeceeeeeeeeeeeseeeeeeeseeeeenees 65 3 4 66 Structure of EXB interrupt source register ceecseeeceeeeeeeneeeeeeeeeeeaeeseeeeeeeeaaeeenes 66 3 4 67 Structure of EXB index register cccccecsecceeeeeeeeeeeeeeeeeeceaeeeseaeeeseeeeeeaaeeseeeeeessaaeee
255. eeeeneaaees 89 Fig 130 Multichannel RAM timing diagram one wait 0 cee eeeeeeeeeeeeeeeeeeeeteeeeeeeeeeeeneees 89 Fig 131 Multichannel RAM operation example ccc ceceeeeeeeeeeeceeeeeeeeneeeeeeeeeaeeeeeeeaaeeeeeeeaees 90 Fig 132 Structure of AD Control register cceceeeseeeceee cesses cere eeeaaeeseeeeeeseaaeeeeeeeeteaaeeneneees 91 Fig 133 10 bit A D MOde reading ooo cece ee eeeeee eee eeee eae eeeeeeaaeeeeeeeeaaeeeeeeeaaaeeeeeeeaeeeeeseaaaes 91 Fig 134 A D converter block diagram 0 eee eeeeeee eee eeeeaeeeeeeeeaaeeeeeeeeaaeeeeeeeaaaeeeseeeaeeeeeseaaaes 92 Fig 135 Block diagram of Watchdog tMer esiseinas 93 Fig 136 Structure of Watchdog timer Control register cecceeceeeeeeeeeeeeeceeeeeeeeetetaeeeeeeeeees 93 Fig 13 7 Example of reset circult i ccccseccih eec cl eee iets teed eee ner emcee 94 Fig 138 Reset Segu NCE arrra a d eae ce cQeb tena deceit veteutean cede dauata EREE 94 Fig 139 Block diagram of PLL CirCUit eee eee eene eee eeee E 95 Fig 140 Structure of PLL control register ceceeeesceeceneeeeeeeeeceeeeeeeeaeeseeeeeesaeeseeeeeessaeeeseaeees 96 Fig 141 Ceramic resonator or quartz crystal oscilltor circuit eee eeeeeeeeteeeeeeeeeeeteeeeeeeeees 98 Fig 142 External Clock input CirCUit serasa AAEN EA 98 Fig 143 Structure of MISRGA aiia 98 Fig 144 System clock generating circuit block diagram single chip mode 98 Fig 145 State transitions Of clock eccccccsccseeceec
256. eesaaeeeeaes 28 3 2 13 Notes on programming sre kesenengen Ense tance cues cancer deteann vw dudebia ve deeh EREE R states 29 3 2 14 Notes on flash memory version ccccceeeeeeeeeeeeeceeeeeeeeceeaeeeeaeeeceaeeeseaeeseeeeesiaaeseeaees 31 3 2 15 Electric Characteristic Differences Between Mask ROM and Flash Memory Version MOUS airaa ia as cde ste aa tt neta ea Sedan eats arden accented eee aan 31 3 3 Countermeasures against NOISE cccceeeeeseeeeeeeeeeeeeneeeeneeeeeeeeeeeseeeeeeeeeesneaeseeeeeeeseesenseeeneas 32 3 3 1 Shortest wiring length 22 cece cece ce ceeeeecceeeeeeeeeeeeeeeeeaaeseeeeeeeeaeeeseeeeecaeeeeeaeeeseieeeseaeeesaes 32 3 3 2 Connection of bypass capacitor across Vss line and Vcc liN cceeesteeeeeeereeees 34 3 3 3 Wiring to analog Input PINS 0 eee eee e center eeeee eee EEA AA AaS 35 3 3 4 Oscillator CONnCeINnS s nscieiiie tank aE aaa ia EEA aeai 36 3 3 5 Set p for VO Poltsaren aiie aiaa a ae E niai 37 3 3 6 Providing of watchdog timer function by software c scceceeeeeeeeeeeeeeesecseeeeeeeeees 38 3 4 List Of registers 0 cceceeeec cece settee eens neee cent neeee seen neces eee neeeee eed geeeeeeensneeeeeesaseeeeeeseeseeeeneeneneeeeneees 39 3 5 Package OUUING ssori EEEE E 83 3 6 Machine instructions cccseeeeeceeseeeeeeeeeneeeeeeenneeeeeeeenseeeeeeensneeeeeeeeseceeeeeeseeeeeeeedseeeneeeeeseeteeeees 86 3 7 List Of instruction code cccccceseeee eee ee seen eee eneneeeee ee
257. eeseaeeseeeeeeeaeeeeaees 53 Structure of EP10 control register 1 ccceeecceececeeeeeeeeeceeeeeeeaeeseaeeeseaeeseeeeeenaeeeeaees 53 Structure of EP10 control register 2 0 cecececeeeceeeeceeeeeececeeeeseeeeceaeeeseaeeseeeeesteeeeeees 53 Structure of EP10 control register 3 cceceeeceeeceeeeeeeeeeeeeceeeeseeeeseaeeeseaeeseeeeeeeaeeeeaees 54 Structure of EP10 interrupt source register eceeecceeeceeeeeeseeeceeeeeeeeeeeseeeeeetaeeeeaees 54 Structure of EP10 byte number regQiSter c ccccceeeeeeeeeceeeeeeseeeceeeeeeeaeeseeeeessaeeneaees 55 Structure of EP10 buffer area Set reQiSter ceecceeesseeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeesnaeeeeenes 55 Structure of EP11 set register cccceccccecesseeeeeeeceeeeceeeeeeceeaeeeeaaeeseeaesseaaeesseaeestaaeeeeaes 56 Structure of EP11 control register 1 esssssessseessisesieesrissriresrrssrrsssrnsstnnstnnnstnnnnnnennnne 56 Structure of EP11 control register 2 0 ecceeececececeeeeeeeeeeceeeeseeeeceaeeeeeeeeseeeeeseeaeeeeaees 56 Structure of EP11 interrupt source register essssssssessresrirssrrsssrrsssrnsrrnssnnsrrnsernee 57 Structure of EP11 byte number reQiSter c cccecseeceeeececeeeeeeeeececeeeeeaeeseeaeeeeeaeeeeaees 57 Structure of EP11 buffer area set reQiSter ccceeesceeceeeeeeeeeeseeeeeesaeeseeeeeeseaeeetenes 57 AUB TUNG HON Seic m Ea a E aa A a 58 HUB function control circuit block diagram ssssssssssssrirssssrrrssrsirnssrrirnnnnrinnsnsrinnnnnnnn 59 Bl
258. eesegseeeeeesesaeeeeeseeseeeeeeseeneeeeneees 78 229A Memory MAP eocenie deria e AN ENEE ESANA AEA EEE 78 2 9 2 Related registers iccciecccscccccsecevsecedevetie eeseceneiec ee tuthdeesadeeeeiedeeeceanteeesdeebtec saute iaiia 78 2 9 3 Watchdog timer application examples 0 2 eee ee eeeeeeeeeeeeeeeeeeeteeeaeeeeeteeeaeeeeenenaaees 80 2 9 4 Notes on watchdog timer ceseisirninissnarnsrer tsr inni i 81 2 10 ROSET niea 82 2 10 1 Connection example of reset C n ssssssssssssissssisssrissressristsrisstrnsstnnssinnssrnnstn nsun nnen nnne 82 2 10 2 Notes on RESET pin eae een ener meee ere ae oe eo eee ONE Tene Sen Serene en een rere oe 83 2 11 Frequency synthesizer PLL cccsscccceeeeeeseeseseeeeeeeeeeeseeeeeneeeeeeseeeeeeeeeeesnaeseeeeeeessneseseeeenes 84 2111 Memo Mapep riie a debited J EEEE EIE E RERE 84 211 2 Related rogito S eres an S 84 2 1123 FUNCHO Mall deseri UON saesson aaas E EA 86 2114 NOt6S OM Ph bere cecccecesed cccsetardecccheceatecaseseats ecchecaidessebahiiayeesieasdpectbeanldecssbohigeressdhapecsaendees 89 2 12 Clock generating CIRCUIE ss ssrin napnak aaan aapea 90 A2 MOMOLy MAP recse ENE SERANTES RAES ERA 90 2 122 Related registers ssrimuiciucniir iie er E EE E 90 212 3 Oscillation Control sssrin sinaia aaa E ai lee A 92 2 13 StAMODY TUNCOM ee aaaea a p aa cetic Satceee etc seston sauccecustesdesupesise cessneacevsecnsevencecants 95 2131 Memon Map osica a ee Ae eee ee 95 2 13 2 Related fegiSters arrien iii a E eaten en TAE OOE E
259. egister ccceceeceeeeeeeeeeeeeeeeeeeeeeeceeeeeesaeeeeeeeeetaeeeseeeees 25 Fig 2 3 6 Structure of Interrupt request register 1 0 cece ceeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeetiaeeeteeeens 26 Fig 2 3 7 Structure of Interrupt request register 2 0 cece cece cece cesses eeeeeeeeeeaeeteeeeeetaeeeseeeens 26 Fig 2 3 8 Structure of Interrupt Control register 1 ooo eeceeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeneeeetaeeeseneeens 27 Fig 2 3 9 Structure of Interrupt Control register 2 oo ececeeceeceeeeeeeeeeeeeeeeeeeaeeseeeeeetaeeeteneeens 27 Fig 2 3 10 Timers connection and setting Of division ratios ec eee eeeeee eee eeeeeeeeeeeeeeaees 29 Fig 2 3 11 Related registers setting ccccccccceeececeeeeeee cece eeeeaeeeceaeeeecaaeeseeeeessaeesenneeessaeeeseaeees 29 Fig 2 3 12 Control procedur Gs scrima aanne ieai oa iaaiiai 30 Figs 2 3 13 Peripheral circuit example scesrsissisassiss isei ikk n ESNE NKEA 31 Fig 2 3 14 Timers connection and setting of division ratios essssssssssrsssserrsssrerrsssreerns 31 Fig 2 3 15 Related registers setting ccccceeecceeeeeeeeeeeeeeceaeeeeeeeeeceaeeeeeaaeeseeeeesaaeeseeneestsaeesseaeees 32 Fig 2 38 16 Control procedUre ntis aiaa aeiaai aa ened iaslecsesseecervarssasceaeustiadis 32 Fig 2 3 17 Judgment method of valid invalid of input pulses eerie 33 Fig 2 3 18 Related registers setting ceccceecsceeceeeeeeeeeeeeeeeeeseaeeeceaeeeeeaaeeseeeeeesaeeeeeeeeessaeeeteneees 34 Fig 2 3 19
260. egister 1 address 3C16 gt Timer X interrupt request becomes 1 at 10 ms intervals Interrupt control register 1 address 3E16 b bO 7 AAT gt Timer X interrupt Enabled Fig 2 3 11 Related registers setting Rev 2 00 Oct 15 2006 page 29 of 112 2tENESAS REJ09B0338 0200 38K2 Group RESET Initialization address 2316 lt xxxx1x002 address 3C16 lt XX0XXXXX2 address 3E16 bits lt 1 address 2416 address 2516 lt 30 1 e 125 1 address 2316 bit3 lt 0 Main processing lt Procedure for completion of clock set gt Note 1 address 2316 bit3 lt 1 address 2416 address 2516 lt 30 1 lt 125 1 address 3C16 bits lt 0 address 2316 bit3 lt 0 CLT Note 2 CLD Note 3 Push registers to stack Clock count up 1 100 second to year Pop registers Fig 2 3 12 Control procedure Rev 2 00 Oct15 2006 page 30 of 112 REJ09B0338 0200 APPLICATION 2 3 Timer x This bit is not used here Set it to O or 1 arbitrarily All interrupts disabled Timer X operating mode Timer mode Timer X interrupt request bit cleared Timer X interrupt enabled Division ratio 1 set to Prescaler X and Timer X Timer X count start Interrupts enabled Timer X count stop Timer reset to restart count from 0 second after completion of clock set Timer X count start Note 1 Perform procedure for completion of clock se
261. egister 1 IREQ1 003D16 Interrupt request register 2 IREQ2 003E16 Interrupt control register 1 ICON1 003F 16 Interrupt control register 2 ICON2 OFFO16 Port PO pull up control register PULLO OFF216 Port P5 pull up control register PULL5 OFF316 Interrupt edge selection register INTEDGE _ OFF416 Reserved Note OFF616 Reserved Note OFF716 _ Reserved Note OFF816 _PLL control register PLLCON OFF916 Downstream port control register DPCTL OFFAis Reserved Note OFFBi MISRG o ooo y O OFFD16 Reserved Note OFFE16 _Elash memory control register FMCR OFFF1e Reserved Note Note Do not write any data to these addresses because these areas are reserved Fig 9 Memory map of special function register SFR Rev 2 00 Oct15 2006 page 12 of 130 REJ09B0338 0200 7RENESAS 38K2 Group I O PORTS The I O ports have direction registers which determine the input output direction of each individual pin Each bit in a direction reg ister corresponds to one pin and each pin can be set to be input port or output port When 0 is written to the bit corresponding to a pin that pin be comes an input pin When 1 is written to that bit that pin be comes an output pin If data is read from a pin set to output the value of the port output latch is read not the value of the pin itself Pins set to input are floating If a pin set to input is written to only the port
262. eing executed Figure 2 2 9 shows the time up to execution of interrupt processing routine and Figure 2 2 10 shows the timing chart after acceptance of interrupt request Interrupt request generated Start of interrupt processing Waiting time for Stack push and Main routine post processing 9 Vector fetch Interrupt processing routine 7 to 23 cycles When f Xin 6 MHz system clock 8 MHz through mode 8 MHz 0 875 us to 2 875 us When executing DIV instruction Fig 2 2 9 Time up to execution of interrupt processing routine Waiting time for pipeline Push onto stack Interrupt operation starts post processing Vector fetch 4 4 y _ e FLFLIFLILILI LIL SYNC RD WR Address bus PC S SPS XS 1 SPSXS 2 SPSK BL X BH XAL AH Databus X Notused PCH PCL PSX AL X AH Y SYNC CPU operation code fetch cycle This is an internal signal that cannot be observed from the external unit BL BH Vector address of each interrupt AL AH Jump destination address of each interrupt SPS 0016 or 0116 Fig 2 2 10 Timing chart after acceptance of interrupt request Rev 2 00 Oct 15 2006 page 14 of 112 RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 2 Interrupt 2 2 5 Interrupt control The acceptance of all interrupts excluding the BRK instruction interrupt can be controlled by the interrupt request bit interrupt enable
263. el except when PLL operation mode selection bits are set to 002 Table 2 11 1 shows the example of PLL operation mode selection bits setting Table 2 11 1 PLL operation mode selection bits setting example PLL operation mode f 1 selection bits voo 6 MHz 11 48 MHz 12 MHz 10 48 MHz PLL control register bits 6 5 Furthermore when PLL operation mode selection bits are set to O02 the clock input into PLL is used as fvco which is not multiplied regardless of PLL operation enabled or disabled fuss USB clock Either f Xin main clock or fvco PLL output clock can be selected for fuss by USB clock select bit of USB control register bit6 of USBCON address 001016 and it is supplied to the USB function control circuit When supplying fvco to the USB function control circuit after setting PLL enable bit to 1 enabled and then set USB clock select bit to 1 USB clock Rev 2 00 Oct 15 2006 page 86 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 11 Frequency synthesizer PLL fsvn fuss division clock According to the setting of the USB clock division ratio selection bits bits 4 3 of PLLCON the division clock of fuss is supplied to fsyn fsyn fuss m m value selected by USB clock division ratio selection bits Set the USB clock division ratio selection bits so that fsvy may be set to 6 MHz 8 MHz or 12 MHz When using fsyn as internal system clock set the system clock selec
264. en reading ITMDO1 Interrupt toggle mode select bit 0 Normal mode 1 Continuous toggle mode valid at Interrupt IN transfer DIRO1 Transfer direction bit 0 OUT Data is received from the host 1 IN Data is transmitted to the host TYP01 Transfer type bite b7b6 1 0 0 0 Transfer disabled 0 1 Bulk transfer 1 0 Interrupt transfer 1 1 Isochronous transfer Bit symbol Bit name Function State remaining Fig 3 4 13 Structure of EP01 set register Rev 2 00 Oct 15 2006 page 43 of 99 2tENESAS REJ09B0338 0200 38K2 Group APPENDIX 3 4 List of registers EP02 set register EPO2CFG address 001916 Bit symbol Bit name Function At reset H W S W BSIZ02 1 0 Double buffer beginning address set bit In double buffer mode set the beginning address of buffer 1 area using a relative value for the beginning address of buffer 0 b1b0 00 8 bytes 0 1 16 bytes 1 0 64 bytes 1 1 128 bytes 0 DBLB02 Buffer mode select bit 0 Single buffer mode 1 Double buffer mode SQCL02 Sequence toggle bit clear bit 0 Toggle bit clear disabled 1 Writing 1 clears the toggle bit and DATAO is used as the next data PID 0 is always read when reading ITMD02 Interrupt toggle mode select bit 0 Normal mode 1 Continuous toggle mode valid at Interrupt IN tran
265. enes 66 3 4 68 Structure of Register WINdOW 1 0 cececesceceeeeeeeeceeeeeeeeeeaaeeeeaeeeeeaeeeeaaeeseeeeeeiaaeeeeaes 67 3 4 69 IndexOO low Structure of External I O configuration register cceeee 67 3 4 70 Index01 low Structure of Transmit Receive buffer register ccceeseeeeeees 68 3 4 71 Index02 low Structure of Memory channel operation mode register 68 3 4 72 Index03 low Structure of Memory address COUNTET 0 ccccsececeessteeeeeesssteeeeeess 68 3 4 73 Index04 low Structure of End address register 0 ccecccccessseeeeeeessteeeeeessnteeeeeess 69 3 4 74 Structure of Register WINAdOW 2 cccccceeseeceeeeeeeeceeeeeeeeecaaeeeeaeeeseaeeeeaaeeseeeeesiaaeeeeaes 69 3 4 75 IndexOO high Structure of External I O configuration register cceeee 69 3 4 76 IndexO3 high Structure of Memory address counter ccccecccecesssteeeeeessteeeeeees 70 3 4 77 Index04 high Structure of End address register ccccceccccsseeceeeessteeeeeeestteeeeeess 70 3 4 78 Structure of AD Control register 00 2 ceeecceeeeeeeceeeeeeeeeeceaeeeeeaeeeeeaeeeeeaeeseeeeeessaaeeenes 70 3 4 79 Structure of AD Conversion register 1 ceeecccceeeeeeeeeeceeeeeeeneeeceeeeeeaaeeseeeessnaaeeeenees 71 2tENESAS 38K2 Group Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Rev 2 00 Oct15 2006
266. ent POo P07 P24 P27 P50 P57 Note 1 Note 1 L total peak output current P60 P63 L total peak output current Note 1 P10 P17 P30 P37 P40 P43 H total average output current Note 1 POo P07 P24 P27 P50 P57 P60 P63 H total average output current Note 1 P10 P17 P30 P37 P4o P43 L total average output current Note 1 POo P07 P24 P27 P50 P57 L total average output current Note 1 P60 P63 Note 1 L total average output current P10 P17 P30 P37 P40 P43 H peak output current Note 2 POo P07 P24 P27 P50 P57 P60 P63 H peak output current Note 2 P10 P17 P30 P37 P40 P43 L peak output current Note 2 POo P07 P24 P27 P50 P57 L peak output current Note 2 P60 P63 L peak output current Note 2 P10 P17 P30 P37 P40 P43 H average output current Note 3 POo P07 P24 P27 P50 P57 P60 P63 H average output current Note 3 P10 P17 P30 P37 P40 P43 L average output current Note 3 POo P07 P24 P27 P50 P57 P60 P63 L average output current Note 3 L average output current Note 3 P10 P17 P30 P37 P40 P43 Main clock input oscillation frequency Vcc 4 00 to 5 25 V
267. ent mode lt Use gt Measurement of external pulse frequency measurement of pulse width of FG pulse for a motor see Application example 4 Measurement of external pulse duty when the frequency is fixed FG pulse Pulse used for detecting the motor speed to control the motor speed Rev 2 00 Oct 15 2006 page 28 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 3 Timer 2 Timer application example 1 Clock function measurement of 10 ms Outline The input clock is divided by the timer so that the clock can count up at 10 ms intervals Specifications The clock f Xin 6 MHz is divided by the timer The clock is counted up in the process routine of the timer X interrupt which occurs at 10 ms intervals Figure 2 3 10 shows the timers connection and setting of division ratios Figure 2 3 11 shows the related registers setting Figure 2 3 12 shows the control procedure Dividing by 100 with software Timer X interrupt Fixed Prescaler X Timer X request bit f XIN 6 MHz 1 16 1 30 1 125 10 ms 1 second 0 No interrupt request issued 1 Interrupt request issued Fig 2 3 10 Timers connection and setting of division ratios Timer X mode register address 2316 b7 b0 Ai hl hel Timer X operating mode Timer mode Timer X count Stop Clear to 0 when starting count Prescaler X address 2416 b7 b0 Pe ee Timer X address 2516 Set divisloniratio b7 bo terrupt request r
268. equest issued Set the corresponding interrupt enable bit to 1 enabled Fig 2 2 15 Sequence of changing relevant register E Reason When setting the following the interrupt request bit may be set to 1 When setting external interrupt active edge Concerned register Interrupt edge selection register address 0FF316 Timer X mode register address 2316 Rev 2 00 Oct 15 2006 page 21 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 2 Interrupt 2 Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to O by using a data transfer instruction execute one or more instructions before executing the BBC or BBS instruction Clear the interrupt request bit to O no interrupt issued NOP one or more instructions J Execute the BBC or BBS instruction Data transfer instruction LDM LDA STA STX and STY instructions Fig 2 2 16 Sequence of check of interrupt request bit E Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to 0 the value of the interrupt request bit before being cleared to 0 is read Rev 2 00 Oct 15 2006 page 22 of 112 7tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 3 Timer 2 3 Timer This paragraph explains the registers setting method and
269. equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under ce
270. er 1 Selecting internal clock 2 Selecting external clock 38K2 group Microcomputer 38K2 group Microcomputer 3 Using Srpy signal output function 4 In UART Selecting an external clock 38K2 group Microcomputer 38K2 group Microcomputer Fig 2 4 11 Serial I O connection examples 2 Rev 2 00 Oct 15 2006 page 46 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 2 4 4 Setting of serial I O transfer data format A clock synchronous or clock asynchronous UART can be selected as a data format of Serial I O Figure 2 4 12 shows the serial I O transfer data format 1ST 8DATA 1SP stTALSBX X xX X X X Xs sp 1ST 7DATA 1SP ST LSB 1ST 8DATA 1PAR 1SP ST ALSB MSBX PAR SP 1ST 7DATA 1PAR 1SP stTALSBX XX X X XMsBXPARY sP 1ST 8DATA 2SP TKB X X X X X Xus 28P 1ST 7DATA 2SP stAusBx X X X X XMS asp Serial O 1ST 8DATA 1PAR 2SP st AusB xX _X_X_ gt X_X_X_XXsX pan 2sp 1ST 7DATA 1PAR 2SP st KBX XX X X X Xusan 2sP __ Clock synchronous Serial I O LSB first ST Start bit SP Stop bit PAR Parity bit Fig 2 4 12 Serial I O transfer data format Rev 2 00 Oct 15 2006 page 47 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 2 4 5 Serial I O application examples 1 Communication using clock synchronous serial I O transmit receive Outline 2 byte data is transmitted and received u
271. er PLLCON Address OFF816 ea O Nothing is arranged for these bit These are vanite pies bits O x i I USB clock division pa Divided by 8 fsyn fuss 8 talio seleeion bite Divided by 6 fsvn fuse 6 Divided by 4 fsyn fusB 4 Not selected PLL operation mode ne aedon bits Not multiplied fvco fxin Double fvco fxn X 2 Quadruple fvco fxn X 4 Multiplied by 8 fvco fxin X 8 7 PLL enable bit J T Enabled Fig 2 12 4 Structure of PLL control register Rev 2 00 Oct15 2006 page 91 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 12 Clock generating circuit 2 12 3 Oscillation control Either can be selected as an internal system clock between the following two by system clock selection bit Main clock f Xin fsyn fuss division clock Any one can be selected as an internal clock p among the following four by system clock division ratio selection bits f Xin or fsyn 8 8 divide mode or fsyn 4 4 divide mode or fsyn 2 2 divide mode or fsyn Through mode IN IN ce tS StS a f X f X f X 1 Generation of internal clock f using main clock f X Table 2 12 1 shows the example of internal clock f generation using main clock f Xin Figure 2 12 5 shows the related registers setting Table 2 12 1 Example of internal clock f generation using main clock f Xin System clock division Power source voltage f se dike clack ratio se
272. er in this state data starts to be shifted to the transmit shift register When the serial I O enable bit is set to 1 at this time the data during internally shifting is output to the TxD pin and an operation failure occurs Stop of receive operation Clear the receive enable bit to 0 receive disabled Stop of transmit receive operation Only transmission operation is stopped Clear the transmit enable bit to O transmit disabled Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I O enable bit is cleared to 0 Serial I O disabled the internal transmission is running in this case since pins TxD RxD SCLK and SRDY function as I O ports the transmission data is not output When data is written to the transmit buffer register in this state data starts to be shifted to the transmit shift register When the serial I O enable bit is set to 1 at this time the data during internally shifting is output to the TxD pin and an operation failure occurs Only receive operation is stopped Clear the receive enable bit to 0 receive disabled SRDY output of reception side Serial I O When signals are output from the SRDY pin on the reception side by using an external clock in the clock synchronous serial I O mode set all of the receive enable bit the SRDY output enable bit and the transmit enable bit to 1 transmit enabled
273. er shows the operating status of the flash memory and whether erase operations and programs ended suc cessfully or in error It can be read in the following ways 1 By reading an arbitrary address from the User ROM area after writing the read status register command 7016 2 By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command FF 16 is input Also the status register can be cleared by writing the clear status register command 5016 After reset the status register is set to 8016 Table 11 shows the status register Each bit in this register is ex plained below Sequencer status SR7 The sequencer status indicates the operating status of the flash memory This bit is set to 0 busy during write or erase operation and is set to 1 when these operations ends After power on the sequencer status is set to 1 ready Table 11 Definition of each bit in status register Each bit of SRDO bits Status name Sequencer status HARDWARE FUNCTIONAL DESCRIPTION Erase status SR5 The erase status indicates the operating status of erase operation If an erase error occurs it is set to 1 When the erase status is cleared it is set to O Program status SR4 The program status indicates the operating status of write opera tion When a write error occurs it is set to 1 The p
274. erial I O synchronous In clock synchronous serial I O clock selection bit SCS 0 BRG output divided by 4 1 External clock input e In UART 7 BRG output divided by 16 External clock input divided by 16 Srpy output enable bit ra P43 pin operates as ordinary I O pin SRDY P43 pin operates as Sarpy output pin Transmit interrupt o Interrupt when transmit buffer has emptied source selection bit TIC Interrupt when transmit shift operation is completed 4 Transmit enable bit TE 0 Transmit disabled 1 Transmit enabled 5 Receive enable bit RE T Receive disabled Receive enabled Serial I O mode selection bit 0 Clock asynchronous UART serial I O SIOM 1 Clock synchronous serial I O 7 Serial I O enable bit 0 Serial I O disabled SIOE pins P40 to P43 operate as ordinary I O pins 1 Serial I O enabled pins P40 to P43 operate as serial I O pins Fig 2 4 4 Structure of Serial I O control register UART control register b7 b6 b5 b4 b3 b2 bi bO ee UART control register UARTCON Address OFE1 16 Nae Function Arrest RW et length selection bit O 8 bits CHAS 1 7 bits Parity hal bit 0 Parity checking disabled PARE 1 Parity checking enabled je ssc bit 0 Even parity PARS 1 Odd parity 4 Nothing is allocated for this bit This is a write disabled bit When this bit is read out the contents are 0 Stop length selection bit nE 1 stop bit STPS 2 stop bits 5
275. erved Note Reserved Note Reserved Note OFEAt6 Reserved Note OFEBi6 OFECi6 OFEDi6 Reserved Note Endpoint field register 9 EPXXREGQ OFEE16 OFEF 16 Note Rev 2 00 Oct 15 2006 page 98 of 99 REJ09B0338 0200 Reserved Note Reserved Note 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002Bi6 002Ci16 002Di6 002E16 002F 16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F 16 OFFO16 OFF 116 OFF216 OFF316 OFF 416 OFF5i16 OFF616 OFF716 OFF816 OFF916 OFFAi6 OFFDi6 OFFE16 OFFFie Prescaler 12 PRE12 Timer 1 T1 Timer 2 T2 Timer X mode register TM Prescaler X PREX Timer X TX Transmit Receive buffer register TB RB Serial I O status register SIOSTS HUB interrupt source enable register HUBICON HUB interrupt source register HUBIREQ HUB down stream port index register HUBINDEX HUB port field register 1 DPXREG1 HUB port field register 2 DPXREG2 HUB port field register 3 DPXREG3 Reserved Note Reserved Note EXB interrupt source enable register EXBICON EXB interrupt source register EXBIREQ Reserved Note EXB index register EXBINDEX Register window 1 EXBREG1 Register window 2 EXBREG2 AD control register ADCON AD conversion register 1 AD1 AD c
276. eseeeeeteeeeeeeeeseereeeeeaeeeeenees 77 3 4 93 Structure of EPOO buffer area Set register cececceceeeeeeeeeeeeeeeeeeeeeeeseeeeeessaeeeeees 77 3 4 94 Structure of EP01 buffer area set register cccccecesceeeeeeeeeeeeeeeeeeeseeeeeessaeenenes 77 3 4 95 Structure of EP02 buffer area Set register ceececcecseeeeeeneeeeeeeeeeeeeeeseeeeeessaaeenenes 78 3 4 96 Structure of EP03 buffer area Set register cceccccececeeeeeeeeeeeeeeeeeseeseeeeeessaaeeeenes 78 3 4 97 Structure of EP10 buffer area Set register ceccccececeeeeeneeeeeeeeeeeeeeteeeeeessaaeenenes 78 3 4 98 Structure of EP11 buffer area set register ccececceceeeeeeneeeeeeeeeeeeeeeseeeeeestaaeeeenes 79 3 4 99 Structure of Port PO pull up control register ccecseeeeeeeeeeeeeeseeeseeeeeeeeeeeeeeaees 79 3 4 100 Structure of Port P5 pull up control register ccceccceeseeeseeeeeeeeeeeseeeeeeseeeeeeeees 80 3 4 101 Structure of Interrupt edge selection register cecceesseeeeeeeeeeteeeeeeeeeeesaeeeeenes 80 3 4 102 Structure of PLL Control register ccececceeeceeeeeeeeeeeceeeeeeeeeseeaeeeeaaeesecaeeesaaeeeeaees 81 3 4 103 Structure of Downstream port control register ccceeeeeeeeeeeeeeneeeeeteeeeeeeeeeees 81 3 4 104 Structure Of MISRG 0 0 eee e cence eeeeeeeeeeeeeeeaaeeeeeeeeeceaeesseeeeesaeesseaaeeseeeeeseaaeenanes 82 3 4 105 Structure of Flash memory control reQiSter cccccccseeeeeeeeseceeeeeeeeseeeeesene
277. ess 002D16 State remaining Bit symbol Bit name Function At reset H W S W RIW D1MINUS D1 signal bit In DSRMOD1 0 a downstream port 1 bus state is read using RD signal In DSRMOD1 1 a downstream port 1 bus state is read using EOF2 signal internal signal In definite In definite O x D1PLUS D1 signal bit In DSRMOD1 0 a downstream port 1 bus state is read using RD signal In DSRMOD1 1 a downstream port 1 bus state is read using EOF2 signal internal signal In definite In definite OX Not used Write 0 when writing 0 is read when reading O O Fig 98 Structure of DP1 status register Rev 2 00 Oct15 2006 page 66 of 130 REJ09B0338 0200 2RENESAS i State remaining 38K2 Group 2 Downstream port 2 HARDWARE FUNCTIONAL DESCRIPTION DP2 interrupt source register DP2REQ address 002B16 Bit symbol Bit name Function At reset H W S W PTDIS2 Downstream port 2 disconnect detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus disconnect state 2 5 us or more of SEO on a downstream port 2 in DSCONN2 1 0 can be set by software but 1 cannot be set 0 PTCON2 Downstream port 2 connec
278. et register EP10BUF BADD10 4 0 T T 6 Endpoint 11 001916 EP11 set register EP11CFG SQCL11 001A16 EP11 control register 1 EP11CON1 PID11 1 0 001B16 EP11 control register 2 EP11CON2 BOVAL11 001Ci6 001D16 EP11 interrupt source register EP11REQ BORDY11 001E16 EP11 byte number register EP11BYTO BOBYT11 O01F 1s OFECi6 OFED16 EP11 buffer area set register EP11BUF BADD11 4 0 T T T Fig 30 USB related registers Rev 2 00 Oct 15 2006 page 32 of 130 2RENESAS REJ09B0338 0200 38K2 Group USB Related Registers The USB related registers are shown below bo HARDWARE FUNCTIONAL DESCRIPTION USB control register USBCON address 001016 Bit symbol Bit name Function At reset H W S W WKUP Remote wakeup bit Returning to BUS idle state by writing 1 first and then 0 Remote wakeup signal K state output 0 TRONCON TrON output control bit L output mode valid in TRONE 1 H output mode valid in TRONE 1 TRONE TrON output enable bit TON port output disabled Hi Z state TON port output enabled VREFCON USB reference voltage control bit Normal mode valid in VREFE 1 Low current mode valid in VREFE 1 VREFE USB reference voltage enable bit USB reference voltage ci
279. f ExRD is detected an internal memory access sequence which synchronized with a rise of is activated A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer TXBUF The memory address counter is simultaneously increased When the read operation from the end address has been completed the detection circuit of external read signal ExRD operation is enabled and negation of the memory channel request which synchronized with the following o is made When a rise of ExRD is detected the memory channel operation sequence ends and the memory channel operation end interrupt is generated Fig 128 Memory channel tranmitting operation 2 Rev 2 00 Oct 15 2006 page 88 of 130 2RENESAS REJ09B0338 0200 38K2 Group MULTICHANNEL RAM The 38K2 group has the built in multichannel RAM including the small logic circuit RAM I F instead of ordinary RAM The multichannel RAM has the USB channel and the EXB channel in addition to the CPU channel The multichannel RAM controls access from CPU USB and EXB synchronizing control with The USB transfer rate is about 1 5 Mbytes second Access to the multichannel RAM is performed at every about 5 3 clocks in 8 MHz or at every about 4 clocks in o 6 MHz The USB s access has priority to the EXB s No wait ONW H HARDWARE FUNCTIONAL DESCRIPTION The one wait function ONW function of 38000 series CP
280. f X YY This instruction adds one to the contents of Y If addressing mode is ABS PCL lt ADL PCH amp ADH If addressing mode is IND PCL amp M ADu ADL PCH amp M ADH ADL 1 If addressing mode is ZP IND PCL lt M 00 ADL PCH lt M 00 ADL 1 This instruction jumps to the address desig nated by the following three addressing modes Absolute Indirect Absolute Zero Page Indirect Absolute M S PCH lt S 1 M S amp PCL S lt S 1 After executing the above if addressing mode is ABS PCL lt ADL PCH amp ADH if addressing mode is SP PCL lt ADL PCH amp FF If addressing mode is ZP IND PCL lt M 00 ADL PCH lt M 00 ADL 1 This instruction stores the contents of the PC in the stack then jumps to the address desig nated by the following addressing modes Absolute Special Page Zero Page Indirect Absolute When T 0 A amp M When T 1 M X M When T 0 this instruction transfers the con tents of M to A When T 1 this instruction transfers the con tents of M to M X The contents of A remain unchanged but status flags are changed M X represents the contents of memory where is indicated by X This instruction loads the immediate value in M This instruction loads the contents of M in X Rev 2 00 Oct15 2006 page 90 of 99 REJ09B0338 0200 This instruction loads the contents of M in Y ztENESAS
281. f conversion result can be performed by selecting the reading procedure of the AD conversion registers 1 2 after A D conversion is completed in Figure 133 The 8 bit reading inclined to MSB is performed when reading the AD converter register 1 after A D conversion is started or reset and when the AD converter register 1 is read after reading the AD converter register 2 the 8 bit reading inclined to LSB is per formed AD Control Register ADCON 003616 The AD control register controls the A D conversion process Bits 0 to 2 select a specific analog input pin Bit 3 signals the comple tion of an A D conversion The value of this bit remains at 0 during an A D conversion and changes to 1 when an A D con version ends Writing 0 to this bit starts the A D conversion Comparison Voltage Generator The comparison voltage generator divides the voltage between VREF and AVSs into 1024 and that outputs the comparison volt age The A D converter successively compares the comparison voltage Vref in each mode dividing the VREF voltage see below with the input voltage e 10 bit reading VREF Vref 4o94 X N n 0 1023 8 bit reading Vref VREF x 0 2 re 256 n n 0 255 Channel Selector The channel selector selects one of the input ports P17 AN7 P10 ANo Rev 2 00 Oct15 2006 page 91 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Comparator and Control Circuit The comparator and cont
282. f internal flash memory can be read out or modified Once the ROM code protect is turned on the contents of the ROM Code Protect Reset Bits cannot be modified in parallel I O mode Use the serial I O or CPU rewrite mode to rewrite the contents of the ROM Code Pro tect Reset Bits ROM code protect control register address FFDBie ROMCP Reserved bits 1 at read write ROM code protect level 2 set bits ROMCP2 Notes 1 2 b3b2 0 0 Protect enabled 0 1 Protect enabled 1 0 Protect enabled 1 1 Protect disabled ROM code protect reset bits Note 3 b5b4 0 0 Protect removed 0 1 Protect set bits effective 1 0 Protect set bits effective 1 1 Protect set bits effective ROM code protect level 1 set bits ROMCP1 Note 1 b7b6 0 0 Protect enabled 0 1 Protect enabled 1 0 Protect enabled 1 1 Protect disabled Notes 1 When ROM code protect is turned on the internal flash memory is protected against readout or modification in parallel I O mode 2 When ROM code protect level 2 is turned on ROM code readout by a shipment inspection LSI tester etc also is inhibited 3 The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2 However since these bits cannot be modified in parallel I O mode they need to be rewritten in serial I O mode or CPU rewrite mode Fig 152 Structure of ROM code protect control register Rev 2 00 Oct15 2006 page 109 of 130 REJ09B0338
283. f serial I O data Valid when serial I O is selected transmission transmission CNTRo 14 FFE31i6 FFE216 At detection of either rising or External interrupt falling edge of CNTRo input active edge selectable Key on wake up 15 FFE116 FFEO16 At falling of conjunction of input External interrupt level for port PO at input mode active edge selectable A D conversion 16 FFDF16 FFDE16 At completion of A D conversion BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Non maskable software interrupt Notes 1 Vector addresses contain interrupt jump destination addresses 2 Reset function in the same way as an interrupt with the highest priority Rev 2 00 Oct15 2006 page 11 of 112 REJ09B0338 0200 2tENESAS APPLICATION 38K2 Group 2 2 Interrupt 2 2 4 Interrupt operation When an interrupt request is accepted the contents of the following registers just before acceptance of the interrupt requests is automatically pushed onto the stack area in the order of and High order contents of program counter PCx Low order contents of program counter PC Contents of processor status register PS After the contents of the above registers are pushed onto the stack area the accepted interrupt vector address enters the program counter and consequently the interrupt processing routine is executed When the RTI instruction is executed at the end of the interrupt processing routine the contents of the above registers p
284. ffers highly efficient memory usage by avoiding re buffering and enabling simple data modifica tion The transmit receive data is directly transferred to the data buffer via the control circuit direct RAM access type without disturbing the CPU operation This mechanism enables the CPU to transfer data smoothly with no drop in performance In addition to this buffer function a double buffer setting will keep a re buffering stall at a minimum and increase the overall data throughput max 64 bytes X 2 channels As other special signals control the endpoints have detection functions for the USB bus reset signal resume signal suspend signal and SOF signal and also have a remote wake up signal transmit function When completing data transfer or receiving a special signal the endpoint generates the corresponding interrupt to the CPU 3 vec tors 24 factors With all this essential yet comprehensive built in hardware your system using the 38K2 group will be ready for any USB applica tion that comes its way 38K2 Group MCU Built in Peripheral Functions D Gas 2 QO T E Ww Fig 23 USB function overview USB Data Transfer The USB specification promises 12 Mbps data transfer in the full speed mode that is equivalent to 1 5 M bytes per second of data transactions However in USB data transfer bit stuffing may be executed de pending on the bit patterns of the transfer data possibly resulting in 1 byte d
285. fofofofofofo EP10 control register 1 EP10CON1 address 001A16 State remaining Bit symbol Bit name Function At reset H W S W PID10 1 0 Response PID bit b1 bO 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of control transfer error B1 is set to 1 by the hardware At reception of SETUP token B1 and b0 are cleared to 0 by the hardware 0 pe Not used Write 0 when writing 0 is read when reading Fig 75 Structure of EP10 control register 1 State remaining b7 bo fofofofofo ofo EP10 control register 2 EP10CON2 address 001B16 Bit symbol Bit name Function At reset H W S W BVAL10 Buffer enable bit 0 NAK transmission SIE is disabled to read a buffer 1 Transmitting receiving data set state SIE is possible to read from write to a buffer Valid in PID10 012 At reception of SETUP token This bit is cleared to 0 by the hardware 0 Not used Write 0 when writing 0 is read when reading Fig 76 Structure of EP10 control register 2 Rev 2 00 Oct15 2006 page 53 of 130 REJ09B0338 0200 7tENESAS e remaining 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION b7 bO ofofofofofofo EP10 control register 3 EP10CONS3 address 001C16
286. from the receive shift register to the receive buffer reg ister and the receive buffer full flag is set A write to the serial I O status register clears all the error flags OE PE FE and SE bit 3 to bit 6 respectively Writing 0 to the serial I O enable bit SIOE bit 7 of the serial I O control register also clears all the status flags including the error flags All bits of the serial I O status register are initialized to 0 at reset but if the transmit enable bit bit 4 of the serial I O control register has been set to 1 the transmit shift register shift completion flag bit 2 and the transmit buffer empty flag bit 0 become 1 Transmit Buffer Receive Buffer Register TB RB 002616 The transmit buffer register and the receive buffer register are lo cated at the same address The transmit buffer register is write only and the receive buffer register is read only If a character bit length is 7 bits the MSB of data stored in the receive buffer regis ter is 0 Baud Rate Generator BRG OFE216 The baud rate generator determines the baud rate for serial trans fer The baud rate generator divides the frequency of the count source by 1 n 1 where n is the value written to the baud rate genera tor Notes on serial I O When setting the transmit enable bit to 1 the serial I O transmit interrupt request bit is automatically set to 1 When not requiring the interrupt occurre
287. g 43 Structure of EPOO control register 3 EPOO interrupt source register EPOOREQ address 001D16 State remaining Bit symbol Bit name Function At reset H W S W BRDY00 USB function Endpoint 0 buffer ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer is ready state enabled to be read written on USB function Endpoint 0 0 can be set by software but 1 cannot be set 0 0 CTENDOO USB function Endpoint 0 control transfer completion interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when control transfer is completed NULL ACK transmission in the status stage on USB function Endpoint 0 0 can be set by software but 1 cannot be set CTSTSOO USB function Endpoint 0 status stage transition interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when transition to status stage occurs in CTENDEO0 0 control transfer completion disabled on USB function Endpoint 0 0 can be set by software but 1 cannot be set lt Transition to status stage occurrence factor gt At transfer of control write When receiving IN token in data stage OUT At transfer of control read When receiving OUT token in data stage IN At no data transfer Nothing occurs
288. ge 69 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers b7 bO fofofofofol Index 0316 Memory address counter MEMADH address 003516 At reset H W S W IM_A Register to set the high order address of memory 0 10 8 channel operation start This contents are increased each time one memory access ends Write 0 when writing 0 is read when reading Bit symbol Bit name Function e remaining Fig 3 4 76 Index03 high Structure of Memory address counter b7 bO ofolofolo Index 0416 End address register ENDADH address 003516 Bit symbol Bit name Function At reset H W S W END_A Register to set the high order address of memory 10 8 channel operation end b7 b3 Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 77 Index04 high Structure of End address register AD control register b7 b6 b5 b4 b3 b2 b1 bO ae AD control register ADCON Address 3616 P10 DQo ANo P11 DQ1 AN1 P12 DQ2 ANe2 P13 DQ3 AN3 P14 DQ4 AN4 P15 DQ5 AN5 P16 DQ6 AN6 P17 DQ7 AN7 Fig 3 4 78 Structure of AD control register Rev 2 00 Oct15 2006 page 70 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers AD conversion register 1 b7 b6 b5 b4 b3 b2 bi bO AD conversion register 1
289. ge detection circuit Fig 137 Example of reset circuit 3 X2 X2 X X FEFC X FFEFD X ADHD Reset address from the vector table Xin 10 5 to 18 5 clock cycles Fig 138 Reset sequence Notes 1 The frequency relation of f Xin and f 0 is f Xin 8 f 0 2 The question marks indicate an undefined state that depends on the previous state Rev 2 00 Oct 15 2006 page 94 of 130 2RENESAS REJ09B0338 0200 38K2 Group PLL CIRCUIT FREQUENCY SYNTHESIZER The PLL circuit generates fvco PLL output clock which is re quired for fusB USB clock and fSYN fUsB division clock from f XIN external input reference clock Figure 139 shows the PLL circuit block diagram It is possible to input 6 or 12 MHz clock from the externals as a standard clock input When using the USB function set the PLL operation mode selection bit so that fvco may be set to 48 MHz The PLL circuit operates by setting the PLL operation enable bit to 1 When supplying fvco to the USB block wait for the oscillation stable time 1ms or less of PLL before selecting fvco with the USB clock selection bit According to the setting of the USB clock division ratio selection bit the division clock of fUSB is supplied to fSYN When using this clock as system clock set the USB clock division ratio selection bit so that it may be set to 6 MHz 8 MHz or 12 MHz However using it only when fusB is 48MHz is recommended address OF F816 add
290. gister 1 EP02CON1 PIDO2 1 0 001Bis EP02 control register 2 EP02CON2 BOVALO2 001Ci6 EP02 control register 3 EP02CON3 B1VALO2 001D16 EP02 interrupt source register EP02REQ BiRDY02 BORDY02 001E16 EP02 byte number register 0 EPO2BYTO BOBYT02 6 0 001Fis EP02 byte number register 1 EPO2BYT1 B1BYT02 6 0 OFEC16 EP02 MAX packet size register EPO2MAX MXPS02 6 0 OFED16 EP02 buffer area set register EPO2BUF BADDO2 4 0 T 4 Endpoint 03 001916 EPOS set register EPO3CFG TYPO3 1 0 ITMDO3 SQCLO3 DBLB03 BSIZ03 1 0 001A16 EP03 control register 1 EP03CON1 PIDO3 1 0 001B16 EP03 control register 2 EPO3CON2 BOVALO3 001Ci6 EP03 control register 3 EP03CON3 B1VAL03 001D16 EP03 interrupt source register EPO3REQ B1RDY03 BORDY03 001E16 EP03 byte number register 0 EPO3BYTO BOBYT03 6 0 001F16 EP03 byte number register 1 EPO3BYT1 B1BYT03 6 0 OFECis EP03 MAX packet size register EPO3MAX MXPS03 6 0 OFED16 EP03 buffer area set register EPO3BUF BADD03 4 0 T 5 Endpoint 10 001916 EP10 set register EP10STG SETUP10 001A16 EP10 control register 1 EP10CON1 PID10 1 0 001B16 EP10 control register 2 EP10CON2 BVAL10 001Cis EP10 control register 3 EP10CON3 CTENDE10 001D16 EP10 interrupt source register EP10REQ BSRDY10 CTSTS10 CTEND10 BRDY10 001E16 EP10 byte number register EP10BYT BBYT10 3 0 OO1F 1s OFECi6 OFED16 EP10 buffer area s
291. gister RXB_ENB CPU channel receive enable 1 Receive buffer full interrupt enabled Writing the command for enabling operation makes RXB_RDY assertion and the P33 ExINT pin goes to L If the CPU channel receive enable bit RXB_ENB is 0 both the receive buffer full bit RXB_FULL and the receive buffer ready signal RxB_RDY to an external are inactive When a write operation is performed from an external MCU bus in the condition of ExCS L and WxA0 H it will result in as follows The data is written into the receive buffer RXBUF Negation of the receive buffer ready signal RxB_RDY to an external is made The RXB_FULL interrupt is generated When the CPU reads out the receive buffer RXBUF with an interrupt processing program the receive buffer full bit RXB_FULL is cleared to 0 Fig 122 CPU channel receiving operation Rev 2 00 Oct 15 2006 page 82 of 130 2RENESAS REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION 2 CPU Channel Transmitting Operation CPU channel transmitting operation is shown bellow Address ExA0 Chip select ExCS Read ExRD Write EXWR Data DQo to DQ7 Internal clock 6 Lm Interrupt request ExINT TxB_RDY Transmit buffer empty bit TXB_EMPTY Receive buffer RXBUF Transmit buffer TXBUF CPU channel transmit enable bit TXB_ENB Transmit data write lt lnitial setting gt External I O configura
292. gment of internal memory access lt Initial setting gt External I O configuration register Memory channel operation mode register Memory address counter End address register lt Operation start command gt EXB interrupt source enable register Jack of lack ay Set as necessary MC_DIR 1 0 Memory channel direction control 012 Receive mode Burst burst 1 Burst mode Example 010016 Example 010216 MC_ENB Memory channel operation enable 1 Operation start In the memory channel receive mode when the command for enabling operation is written assertion of the memory channel request which synchronized with a rise of o is made When a rise of ExWR is detected an internal memory access sequence which synchronized with a rise of is activated and a data is written in the internal memory within two clocks at a minimum The memory address counter is increased simultaneously at the former data write completion When the memory address counter reaches the end address the detection circuit of external write signal ExWR operation is enabled and negation of the memory channel request which synchronized with the following is made When the write operation to the end address has been completed the memory address counter is increased and the memory channel operation end interrupt is generated Fig 125 Memory channel receiving operation 2 Rev 2 00 Oct15 2006 page 85 of 130
293. gnal of the internal data bus with an module select signal and a read signal and generating a select signal for each register with an address decode signal CPU write register There are three CPU write registers as follows EXB interrupt source enable register Index register External I O configuration register The EXB interrupt source register is a read only register A status signal of the CPU channel controller and a status signal of the memory channel controller in the internal memory interface part are generated CPU channel controller The CPU channel controller generates the following signals using bits 0 and 1 RXB_ENB TXB_ENB of EXB interrupt source en able register Memory channel transmitting buffer control signal MRD_sel generated in the internal memory interface part CPU channel command signal Cch_RD Cch_WR generated in the external I O interface part Signals RxB_RDY RxB_full and TxB_RDY TxB_empty gener ated with read write signals from the CPU channel 2tENESAS 38K2 Group 3 Internal Memory Interface Part The internal memory interface part consists of the CPU register and the memory channel controller CPU register The CPU register consists of the follows Memory channel operation mode register Memory address counter End address register The CPU can set the beginning address into the memory address counter when the memory channel operation enable bit MC_ENB of EXB interrupt source enab
294. he SWDT contents do not change after interrupt processing lt The interrupt processing routine gt e Decrements the SWDT contents by 1 at each interrupt processing e Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles at the fixed interrupt processing count e Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less Interrupt processing routine SWDT SWDT 1 Interrupt processing Main processing Return Interrupt processing Main routine routine errors errors Fig 3 3 12 Watchdog timer by software Rev 2 00 Oct 15 2006 page 38 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers 3 4 List of registers Port Pi b7 b6 b5 b4 b3 b2 bi bO Port Pi Pi i 0 1 2 3 4 5 6 Note Address 0016 0216 0416 0616 0816 OA16 OCi6 Bp Name J Futon Reo RW oper O gee a ele Write ae EE e In input mode i ee Read Value of pins KIGE Bai aide pee KERE Kage Note Since the following ports are not allocated the corrrsponding bits can not be used e P20 to P23 e P44 to P47 e P64 to P67 Fig 3 4 1 Structure of Port Pi Port Pi direction register b7 b6 b5 b4
295. he data between the transmitting and receiving sides may be lost because of noise included in the synchronous clock It is necessary to correct that constantly using heading adjustment This heading adjustment is carried out by using the interval between blocks in this example Figure 2 4 24 shows a connection diagram Scik RxD TxD Master unit Fig 2 4 24 Connection diagram Specifications e The serial I O is used clock synchronous serial I O is selected e Synchronous clock frequency 125 kHz f Xin 6 MHz is divided by 48 e Byte cycle 488 us e Number of bytes for transmission or reception 8 byte block e Block transfer cycle 16 ms e Block transfer term 3 5 ms e Interval between blocks 12 5 ms e Heading adjustment time 8 ms Limitations of specifications e Reading of the reception data and setting of the next transmission data must be completed within the time obtained from byte cycle time for transferring 1 byte data in this example the time taken from generating of the serial I O receive interrupt request to input of the next synchronous clock is 431 us Heading adjustment time lt interval between blocks must be satisfied Rev 2 00 Oct 15 2006 page 56 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O The communication is performed according to the timing shown in Figure 2 4 25 In the slave unit when a synchronous clock is not input wi
296. he falling edge of the CNTRo pin is counted 4 Pulse Width Measurement Mode If the CNTRo active edge selection bit is 0 the timer counts the system clock divided by 16 while the CNTRo pin is at H If the CNTRo active edge selection bit is 1 the timer counts it while the CNTRo pin is at L The count can be stopped by setting 1 to the timer X count stop bit in any mode The corresponding interrupt request bit is set each time a timer underflows 2tENESAS 38K2 Group Divider System clock HARDWARE FUNCTIONAL DESCRIPTION Prescaler X latch 8 1 16 P51 CNTRO CNTRo active Timer X latch 8 Pulse width Timer mode measurement Pulse output mo mo Prescaler X 8 Timer X 8 edge selection bit Event Timer x count stop bit g counter Timer X interrupt request bit CNTRO interrupt CNTRO active q edge selection bt 2 Q Toggle So request bit Port P51 direction register Port P51 latch Pulse output mode Divider T flip flop R 4 o Prescaler 12 latch 8 Timer 1 latch 8 System clock 1 16 Fig 17 Timer block diagram Rev 2 00 Oct15 2006 page 21 of 130 REJ09B0338 0200 Prescaler 12 8 Timer 1 8 RENESAS Timer X latch write
297. he mode of the ports is switched over to the output mode by the program after reset Thus the potential at these pins is undefined and the power source current may increase in the input mode With regard to an effects on the system thoroughly perform system evaluation on the user side e Since the direction register setup may be changed because of a program runaway or noise set direction registers by program periodically to increase the reliability of program 2 Termination remarks I O ports Do not open in the input mode Reason The power source current may increase depending on the first stage circuit e An effect due to noise may be easily produced as compared with proper termination shown in 1 I O ports When setting for the input mode do not connect to Vcc or Vss directly Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between a port and Vcc or Vss I O ports When setting for the input mode do not connect multiple ports in a lump to Vcc or Vss through a resistor Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between ports e At the termination of unused pins perform wiring at the shortest possible distance 20 mm or less from microcomputer pins Rev 2 00 Oct 15 2006 page 7 of 112 2RENESAS REJ09B0338 0200 APPLICATION
298. hen recovery from stop mode ee eeeeeeeeeeeeeeeeees 89 Fig 2 12 1 Memory map of registers related to clock generating circuit 0 eeeeeeeee 90 Fig 2 12 2 Structure of USB Control register cccececceceeeeeeeeeeeeeeeeeeeaeeceeeeeeeaaaeseeeeeesiaaeeeeeees 90 Fig 2 12 3 Structure of CPU mode register eccccecesceceeee cesses eeceeeeeeaaeeeeeeesseaeeeeeeeeettaeeeeeaeees 91 Fig 2 12 4 Structure of PLL Control register cccceceecececeeeeeeeee seer eeeaeeceeeeeeeaaeseeeeeeseaaeeneneees 91 Fig 2 12 5 Related registers setting ccccceeccceceeeeeeeeeeeeceaeeeeeeeeeceaeeeeeeaeeseaeeeesaaeeseeeeeesaeesseneees 92 Fig 2 12 6 Related registers setting cccccecesceceeceeeeeeee cece eeeeeeeeeeaeeeeeaaeeseeeessaeeeseeeeessaeeeseaeees 94 Fig 2 13 1 Memory map of registers related to standby function c ceeeeeeeeeeeeetteeteeneeees 95 Fig 2 13 22Structure Of MISRG sessist sne anientar a oaiae aaa a a aaa a aatia 95 Fig 2 13 3 Oscillation stabilizing time at restoration by reset input ss esesesesseeeesrssrsss 97 Fig 2 13 4 Execution sequence example at restoration by occurrence of INTo interrupt request E A T E E T E E E A E E E 99 Fig 2 129 Reset IMPUt IMO secre E 101 Fig 2 14 1 Memory map of flash memory version for 38K2 Group cceseeeeeeeeeesteeeeeeees 103 Fig 2 14 2 Memory map of registers related to flash Memory c ccceeeeesteeseeeeeeetteeeeeees 104 Fig 2 14 3 Stru
299. hrough FFFF 16 Make sure program and block erase opera tions are always performed within this address range Access to any location outside this address range is prohibited In the Boot ROM area an erase block operation is applied to only one 4 Kbyte block The boot ROM area has had a standard serial I O mode control pro gram stored in it when shipped from the Mitsubishi factory There fore using the device in standard serial I O mode you must perform program and block erase in the user ROM area Rev 2 00 Oct 15 2006 page 111 of 130 RENESAS REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION 38K2 Group 3 Standard Serial I O Mode The standard serial I O mode inputs and outputs the software commands addresses and data needed to operate read pro gram erase etc the internal flash memory This I O is clock synchronized serial This mode requires a purpose specific pe ripheral unit The standard serial I O mode is different from the parallel I O mode in that the CPU controls flash memory rewrite uses the CPU rewrite mode rewrite data input and so forth The standard serial I O mode is started by connecting H to the P16 CE pin and H to the P42 SCLk pin and H to the CNVss VPP pin apply 4 5 V to 5 25 V to Vpp from an external source and re leasing the reset operation In the ordinary microcomputer mode set CNVss pin to L level This control program is written in the Boot ROM area when the
300. ics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics tENESAS C 7 D me on lt D D 38K2 Group User s Manual RENESAS 8 BIT SINGLE CHIP MICROCOMPUTER 740 FAMILY 38000 SERIES All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http Awww renesas com Renesas Electronics www renesas com Rev 2 00 2006 1 0 10 11 12 13 Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document Renesas shall have no liabili
301. ide mode system clock Through mode f f f f 2 Select main clock f Xin as USB clock b7 bo USB control register jo ELT USBCON address 1016 0 Main clock f XIN 3 Enable PLL circuit and generating PLL output clock fvco 48 MHz and fsyn b7 bO SULT Tells PLLGON address OF F815 Divided by 8 fsyN fusB 8 Divided by 6 fSYN fusB 6 Divided by 4 fsYn fusB 4 Not selected Not multiplied fvco fXIN Double fvco fXIN X 2 Quadruple fvco fXIN X 4 Multiplied by 8 fvco fxINn X 8 PLL enabled 4 Select PLL output clock fvco as USB clock b7 bO ELLI USBcon address 101 1 fvco 5 Select fsyn as system clock b7 bO LOLLI Crum adress 38 0 1 SYN Fig 2 12 6 Related registers setting Note When selecting fsyn as an internal system clock refer to 2 11 Frequency synthesizer PLL for details concerning how to generate fuss USB clock from f Xin and the notes on PLL circuit Rev 2 00 Oct 15 2006 page 94 of 112 zRENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 13 Standby function 2 13 Standby function The 38K2 group is provided with standby functions to stop the CPU by software and put the CPU into the low power operation The following two types of standby functions are available Stop mode using STP instruction Wait mode using WIT instruction 2 13 1 Memory map iL Y OFFB16 MISRG
302. igures Fig 2 8 1 Memory map of registers related to A D converter ccctceeeeeeeeeeeteeeeeetteeeeeeeees 72 Fig 2 8 2 Structure of AD Control register ecececceeeeeeeeeeeeeeeeeeeeeeeeeeeaeeseeeeeesaaeeseeeeeesaeeeneneees 72 Fig 2 8 3 Structure of AD Conversion register 1 eeececeeeceeeeeeeceeeeeeeeeeeseeeeeeeeaeeseeeeeeeiaeeneeees 73 Fig 2 8 4 Structure of AD conversion register 2 eeeececeeeeeeeeeeceeeeeeeeeeeceeeeeeeaeeeeeeeeettaeeeeneeens 73 Fig 2 8 5 Structure of Interrupt request register 2 cececeeeeeeeeeeeeeeeeeceeeeeeeeaeeeeeeeeeteaeeeeeeees 74 Fig 2 8 6 Structure of Interrupt control register 2 oo eecceceeeeceeeeeeeeeeeeeeeeeaeeeeeeeeetiaeeeneeeens 74 Fig 2 8 7 Connection GIAQFAM eccececcecceeeeeeeeeeeeeaaeeeeeeeeceaaeeeeaeee sage seeaaeeseeaeeseaaeeseeeeeesaaesseneees 75 Fig 2 8 8 Related registers setting c ccccecceeeeeeceeeeeeeeeeceeeeeeeaaeeeeeeeeesaaeeseeeeessaaaeseeeeeetiaaeeseaeees 75 Fig 2 8 9 Control procedure for 8 Dit read oi eeececceeeeceeceeeeeeeeeeeeeeeeeeaaeeseeeeesseaeeseeeeeesaeeeseaeees 76 Fig 2 8 10 Control procedure for 10 bit read ou eee eeceececeteeeeeneeeceeeeeeeeaeeseeeeeeseaeeseeeeeesiaaeeneneees 76 Fig 2 9 1 Memory map of registers related to watchdog timer ccecccccseeeeeeeeeeettteeeeeeeees 78 Fig 2 9 2 Structure of Watchdog timer Control register ccceceeeeeeteceeeeeeeeeeteeeeeesetaeeteeeees 78 Fig 2 9 3 Structure of CPU mode
303. ilt in flash memory in CPU rewrite mode Rev 2 00 Oct 15 2006 page 110 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory Single chip mode or boot mode Note 1 Set CPU mode register Note 2 Transfer CPU rewrite mode control program to built in RAM Jump to transferred control program on RAM The following operations are controlled by the control program on this RAM Set 1 to CPU rewrite mode select bit by writing O and then 1 in succession Check CPU rewrite mode entry flag Using software command execute erase program or other operation Execute read command or set flash memory reset bit by writing O and then 1 in succession Note 3 Set 0 to CPU rewrite mode select bit Notes 1 When MCU starts in the single chip mode it is necessary to apply 4 50 to 5 25 V to dhe CNVss pin until confirming of the CPU rewrite mode entry flag Set bits 6 and 7 system clock division ratio selection bits of the CPU mode register address 003Bie Before releasing the CPU rewrite mode after completing erase or program operation always be sure to execute the read array command or reset the flash memory Fig 2 14 9 CPU rewrite mode beginning release flowchart Rev 2 00 Oct 15 2006 page 111 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory 2 14 8 Notes on CPU rewrite mode 1 2 3 4 5 Operation speed During CP
304. in 6 MHz is divided by 624 Communication control using port P24 The output level of port P24 is controlled by software e 2 byte data is transferred from the transmitting side to the receiving side at intervals of 10 ms generated by the timer Fig 2 4 30 Timing chart using UART Rev 2 00 Oct 15 2006 page 60 of 112 2RENESAS REJ09B0338 0200 38K2 Group APPLICATION 2 4 Serial I O Table 2 4 1 shows setting examples of the baud rate generator BRG values and transfer bit rate values Figure 2 4 31 shows registers setting related to the transmitting side Figure 2 4 32 shows registers setting related to the receiving side Table 2 4 1 Setting examples of Baud rate generator values and transfer bit rate values Transfer bit rate BRG count source At XIN 6 MHz At f XIN 8 MHz bps Note 3 Note 1 BRG setting value Note 2 BRG setting value Note 2 600 f Xin 4 155 207 1200 f X n 4 77 103 2400 f Xin 155 207 4800 f Xin 77 103 9600 f Xin 38 51 14400 f Xin 25 34 19200 f Xin 19 25 38400 f Xin 9 12 57600 f Xin 8 Notes 1 Select the BRG count source with bit O of the serial I O control register Address OFE016 2 These are setting values with small errors 3 Equation of transfer bit rate Transfer bit rate bps f XIN BRG setting value 1 X 16 X m m When bit 0 of the serial I O control register Address OFE016 is set to 0 a
305. ing e remaining Fig 3 4 91 Structure of EP02 MAX packet size register Rev 2 00 Oct 15 2006 page 76 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers EP03 MAX packet size register EPO3MAX address OFEC16 At reset H W Bit symbol Bit name Function MXPS03 Max packet size bit IN These bits are invalid 6 0 OUT Set the maximum packet size b7 Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 92 Structure of EP03 MAX packet size register EPOO buffer area set register EPOOBUF address OFED16 At reset H W S W BADDOO EP00 beginning address set bit Set the beginning address of EP00 s buffer area 0 4 0 32 byte unit b4b3b2b1b0 0001 0 004016 0001 1 006016 Bit symbol Bit name Function 111 1 0 03C016 1111 1 03E016 Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 93 Structure of EP00 buffer area set register EP01 buffer area set register EPO1BUF address OFED16 At reset H W S W BADDO1 EP01 beginning address set bit Set the beginning address of EP01 s buffer area 0 4 0 32 byte unit b4b3b2b1b0 000 1 0 004016 006016 Bit symbol Bit name Function 03C016 03E016 Not used Write 0 when writing 0 is read when readi
306. ing completion gt Transmit enable bit Transmit enabled _ Receive enable bit Receive disabled gt Serial I O mode selection bit Clock synchronous serial I O gt Serial I O enable bit Serial I O enabled Baud rate generator Address OFE216 b7 bO Interrupt control register 2 Address 3F16 b7 bO gt Serial I O transmit interrupt enable bit Interrupt disabled Interrupt request register 2 Address 3D16 b7 bO Rea gt Serial I O transmit interrupt request bit Confirm completion of transmitting 1 byte data by one unit 1 Transmit shift completion Fig 2 4 21 Registers setting related to Serial I O Transmit Receive buffer register Address 2616 b7 bO TB RB Set a transmission data OoOo Confirm that transmission of the previous data is completed bit 3 of the Interrupt request register 2 is 1 before writing data Fig 2 4 22 Setting of serial I O transmission data Rev 2 00 Oct 15 2006 page 54 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O When the registers are set as shown in Fig 2 4 21 the Serial I O can transmit 1 byte data by writing data to the transmit buffer register Thus after setting the CS signal to L write the transmission data to the transmit buffer register by each 1 byte and return the CS signal to H when the target number of bytes has been transmitted Figure 2 4 23 shows a control proc
307. ins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after
308. interrupt 0 Interrupt disabled 0 foto enable bit Interrupt enabled EXB interrupt 0 Interrupt disabled enable bit Interrupt enabled 4 INTo interrupt i Interrupt disabled enable bit 1 Interrupt enabled Timer X interrupt i Interrupt disabled enable bit Interrupt enabled Timer 1 interrupt Interrupt disabled enable bit Interrupt enabled Timer 2 interrupt Interrupt disabled enable bit i Interrupt enabled Fig 2 3 8 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 bi bO ol TTT ETT Interrupt control register 2 ICON2 T a 3F 16 l Name Function fAtreset RiW i Beare _ interrupt 0 Interrupt disabled i enable bit Interrupt enabled USB HUB interrupt Interrupt disabled i enable bit J Interrupt enabled 9 Serial I O receive 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 3 Serial I O transmit 0 Interrupt disabled i interrupt enable bit 1 Interrupt enabled i 4 CNTRo interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled i 5 Key on wake up 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 7 Fix this bit to 0 A D conversion _ 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled a Fig 2 3 9 Structure of Interrupt control register 2 Rev 2 00 Oct15 2006 page 27 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 3 Timer 2 3 3 Timer application examples
309. ions At reset RIW Oscillation stabilizing time 0 Automatically set 0116 to Timer 1 set after STP instruction FFie to Prescaler 12 released bit 1 Automatically set nothing Nothing is arranged for these bits These are write disabled bits When these bits are read out the contents are indefinite Fig 3 4 104 Structure of MISRG Flash memory control register b7 b6 b5 b4 b3 b2 b1 bO Flash memory control register FMCR address 0FFE16 Note 1 P _Nane Funcions atresei A RY BY status flag 0 Busy being written or 1 O x erased 1 Ready l 1 CPU rewrite mode 0 Normal mode Software select bit Note 2 commands invalid 1 CPU rewrite mode Software commands acceptable 2 CPU rewrite mode 0 Normal mode Oi X enn flag 1 CPU rewrite mode Flash memory reset 0 Normal operation bit Note 3 1 Reset User area Boot area 0 User ROM area selection bit Note 4 1 Boot ROM area 5 Nothing is arranged for these bits If writing 6 set 0 When these bits are read out E the contents are undefined wand o Notes 1 The contents of flash memory control register are XXX00001 just after reset release 2 For this bit to be set to 1 the user needs to write 0 and then 1 to it in succession If it is not this procedure this bit will not be set to 1 Additionally it is required to ensure that no interrupt will be generated during that inter
310. is necessary not only to take measures as follows but to evaluate before actual use 3 3 1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer The shorter the total wiring length by mm unit the less the possibility of noise insertion into a microcomputer 1 Package Select the smallest possible package to make the total wiring length short Reason The wiring length depends on a microcomputer package Use of a small package for example QFP and not DIP makes the total wiring length short to reduce influence of noise Fig 3 3 1 Selection of packages 2 Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible Especially connect a capacitor across the RESET pin and the Vss pin with the shortest possible wiring within 20mm Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions If noise having a shorter pulse width than the standard is input to the RESET pin the reset is released before the internal state of the microcomputer is completely initialized This may cause a program runaway Reset Reset circuit circuit Vss Vss Fig 3 3 2 Wiring for the RESET pin Rev 2 00 Oct 15 2006 page 32 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 3 Countermeasures against noise 3 Wiring for clock input output pins e Make the length
311. ist of registers Bit symbol Bit name Function At reset H W S W EP00 USB function Endpoint 0 interrupt bit This bit is set to 1 when any one of EPOO in source register s bits at least is set to 1 This bit is cleared to 0 by clearing EPOO in source register to 0016 Writing to this bit causes no state change errupt errupt 0 0 USB function Endpoint 1 interrupt bit This bit is set to 1 when any one of EP01 i source register s bits at least is set to 1 This bit is cleared to 0 by clearing EP01 i source register to 0016 Writing to this bit causes no state change errupt errupt USB function Endpoint 2 interrupt bit This bit is set to 1 when any one of EP02 i source register s bits at least is set to 1 This bit is cleared to 0 by clearing EP02 i source register to 0016 Writing to this bit causes no state change errupt errupt USB function Endpoint 3 interrupt bit This bit is set to 1 when any one of EPO3 i source register s bits at least is set to 1 This bit is cleared to 0 by clearing EP03 i source register to 0016 Writing to this bit causes no state change errupt errupt USB HUB Endpoint 0 interrupt bit This bit is set to 1 when any one of EP10 i source register s bits at least is set to 1 This bit is
312. ister PLLCON Address OFF816 nai b4 b3 USB clock division q 9 Divided by 8 fsvn fuse 8 ratio selection bits 6 4 Divided by 6 fsvn fuse 6 1 0 Divided by 4 fsyn fuss 4 1 1 Not selected b6 b5 0 0 Not multiplied fvco fxin 0 1 Double fvco fxn X 2 10 PO fvco fxin X 4 PLL operation mode selection bits Downstream port control register DPCTL address OFF916 At reset H W S W PCON1 Downstream port 1 function 0 1 0 select bit USB port D1 D1 OFF USB difference amplifier OFF USB exclusive input port D1 D1 USB difference amplifier OFF Full speed port D1 D1 USB difference amplifier ON Low speed port D1 D1 USB difference amplifier ON Bit symbol Bit name Function Downstream port 2 function select bit 0 0 USB port D2 D2 OFF USB difference amplifier OFF 0 1 USB exclusive input port D2 D2 USB difference amplifier OFF 1 0 Full speed port D2 D2 USB difference amplifier ON 1 1 Low speed port D2 D2 USB difference amplifier ON Not used Write 0 when writing 0 is read when reading State remaining Fig 3 4 103 Structure of Downstream port control register Rev 2 00 Oct 15 2006 page 81 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers MISRG b7 b6 b5 b4 b3 b2 bi bO MISRG MISRG address OFFB16 B Name Funct
313. ister 1 address 003E16 and the interrupt control register 2 address 3Fie The interrupt enable bits control the acceptance of the corresponding interrupt request When an interrupt enable bit is 0 the corresponding interrupt request is disabled If an interrupt request occurs when this bit is 0 the corresponding interrupt request bit is set to 1 but the interrupt is not accepted In this case unless the interrupt request bit is set to 0 by software the interrupt request bit remains in the 1 state When an interrupt enable bit is 1 the corresponding interrupt is enabled If an interrupt request occurs when this bit is 1 the interrupt is accepted when interrupt disable flag O Each interrupt enable bit can be set to 0 or 1 by software Rev 2 00 Oct 15 2006 page 15 of 112 2tENESAS REJ09B0338 0200 38K2 Group 3 Interrupt disable flag APPLICATION 2 2 Interrupt The interrupt disable flag is allocated to bit 2 of the processor status register The interrupt disable flag controls the acceptance of interrupt request except BRK instruction When this flag is 1 the acceptance of interrupt requests is disabled When the flag is 0 the acceptance of interrupt requests is enabled This flag is set to 1 with the SEI instruction and is set to 0 with the CLI instruction When a main routine branches to an interrupt processing routine this flag is automa
314. it symbol Bit name Function At reset H W S W BORDY11 USB HUB Endpoint 1 buffer 0 0 No interrupt request issued 0 0 ready interrupt bit 1 Interrupt request issued This bit is set to 1 when the buffer is ready state enabled to be read written on USB HUB Endpoint 1 0 can be set by software but 1 cannot be set Not used Write 0 when writing 0 is read when reading State remaining Fig 84 Structure of EP11 interrupt source register b7 bo fofofofofofofo EP11 byte number register EP11BYTO address 001E16 Bit symbol Bit name Function At reset H W BOBYT11 Transmit byte number bit IN Set the transmitting byte number 0 b7 b1 Not used Write 0 when writing 0 is read when reading State remaining Fig 85 Structure of EP11 byte number register EP11 buffer area set register EP11BUF address OFED16 At reset H W S W BADD11 EP11 beginning address set bit Set the beginning address of EP11 s buffer area 0 4 0 32 byte unit b4b3b2b1b0 0001 0 004016 006016 Bit symbol Bit name Function 030016 03E016 Not used Write 0 when writing 0 is read when reading e remaining Fig 86 Structure of EP11 buffer area set register Rev 2 00 Oct15 2006 page 57 of 130 RENESAS REJ09B0338 0200 3
315. itching characteristics of external bus interface EXB 1 Vcc 4 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted ccceeeeeeeees 12 Table 3 1 14 Switching characteristics of external bus interface EXB 2 Vcc 3 00 to 4 00 V Vss 0 V Ta 20 to 85 C unless otherwise noted cccceeeenes 12 Table 3 1 15 Switching characteristics USB ports Vcc 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted cccecccccesssceeeeeseeceeeescsneeeeesseseeeeessseeeeeess 13 Rev 2 00 Oct15 2006 page 14 of 14 RENESAS REJ09B0338 0200 THIS PAGE IS BLANK FOR REASONS OF LAYOUT CHAPTER 1 HARDWARE DESCRIPTION FEATURES PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USAGE DATA REQUIRED FOR MASK ORDERS FUNCTIONAL DESCRIPTION SUPPLEMENT 38K2 Group DESCRIPTION The 38K2 group is the 8 bit microcomputer based on the 740 fam ily core technology The 38K2 group has the USB function an 8 bit bus interface a Serial Interface three 8 bit timers and an 8 channel 10 bit A D converter which are available for the PC peripheral I O device The various microcomputers in the 38K2 group include variations of internal memory size and packaging For details refer to the section on part numbering FEATURES e Basic machine language instructions cece eee eeeeeeee 71 e
316. ite ExwWR Data DQo to DQ7 ja Internal clock LO M E M M m M m m LA Ba DMA request _ j i j ExDREQ et J j 5 fich reg MWR 4 detection mWR 7 detection Receive buffer RXBUF Operation enabled Main sequencer Memory channel operation end interrupt Internal memory access Memory address 010016 Counter end In mananan Acknowledgment of i ack i i l D internal memory access i i i d i lt Initial setting gt External I O configuration register Set as necessary Memory channel operation mode register MC_DIR 1 0 Memory channel direction control 012 Receive mode Burst burst 0 Cycle mode Memory address counter Example 010016 End address register Example 010116 lt Operation start command gt EXB interrupt source enable register MC_ENB Memory channel operation enable 1 Operation start In the memory channel receive mode when the command for enabling operation is written operation starts main sequencer starts and assertion of the memory channel request which synchronized with a rise of o is made When the external MCU bus is in the condition of ExCS L and ExA0 L or a fall of ExWR is detected in the condition of ExDACK L negation of the memory channel request which synchronized with a rise of o is made
317. iting 1 to this bit makes data reception possible SIE is possible to write Not used Write 0 when writing 0 is read when reading State remaining Fig 3 4 27 Structure of EP03 control register 2 Rev 2 00 Oct 15 2006 page 48 of 99 7tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers b7 bO fofofofofo ofo EP10 control register 2 EP10CON2 address 001B16 Bit symbol Bit name Function At reset H W S W BVAL10 Buffer enable bit 0 NAK transmission SIE is disabled to read a buffer 0 1 Transmitting receiving data set state SIE is possible to read from write to a buffer Valid in PID10 012 At reception of SETUP token This bit is cleared to O by the hardware Write 0 when writing 0 is read when reading e remaining Fig 3 4 28 Structure of EP10 control register 2 b7 bO ofofofolofo o EP11 control register 2 EP11CON2 address 001B16 Bit symbol Bit name Function At reset H W S W BOVAL11 Buffer 0 status bit This bit set to 1 shows the transmitting data is in a set 0 JOO state SIE is possible to read i b7 b1 Not used Write 0 when writing O O 0 is read when reading I Riw State remaining Fig 3 4 29 Structure of EP11 control regi
318. its 6 and 7 at address 003B16 3 Before exiting the CPU rewrite mode after completing erase or program operation always be sure to execute the read array command or reset the flash memory Fig 148 CPU rewrite mode set release flowchart Rev 2 00 Oct 15 2006 page 103 of 130 RENESAS REJ09B0338 0200 38K2 Group Notes on CPU Rewrite Mode Take the notes described below when rewriting the flash memory in CPU rewrite mode Operation speed During CPU rewrite mode set the internal clock to 1 5 MHz or less using the system clock division ratio selection bits bits 6 and 7 of address 003B16 lnstructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode lnterrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory Watchdog timer If the watchdog timer has been already activated internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase Reset Reset is always valid The MCU is activated using the boot mode at release of reset in the condition of CNVss H so that the pro gram will begin at the address which is stored in addresses FFFC16 and FFFD16 of the boot ROM area Rev 2 00 Oct 15 2006 page 104 of 130 7RENESAS REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION 38K2 Group
319. ize Flash memory S Z wiesisececcscceetsecdseverestessascressecnseeevedt ceaesees 32 Kbytes Mask ROM size eeeseieieiirirrirrierieiieinrierinrierierees 16 Kbytes RAM size v2 ciccccshesdsesscssncesdegicedeeassdascasiestepeiseazcans 1024 to 2048 bytes Memory Expansion Plan ROM size bytes HARDWARE GROUP EXPANSION Packages PLQP0064GA A ssec 0 8 mm pitch plastic molded LQFP PLQPO0064KB A isee 0 5 mm pitch plastic molded LQFP TOODOM avcscceccscctctstiecsccsees 0 65 mm pitch metal seal PIGGY BACK QD Mass Production a M38K29F8L a woe QM 38K27M4 LID peer 512 1 024 RAM size bytes Fig 4 Memory expansion plan Currently products are listed below Table 2 List of 38K2 group products L version ROM size bytes ROM size for User in Peni Slee BYtES Product As of October 2006 Package Remarks M38K27M4L XXXFP M38K27M4L XXXHP 16384 16254 1024 PLQP0064GA A PLOQP0064KB A Mask ROM version M38K29F8LFP 32768 M38K29F8LHP 32638 2048 PLQP0064GA A PLQP0064KB A Flash memory version M38K29RFS 2048 Rev 2 00 Oct15 2006 page 6 of 130 REJ09B0338 0200 100D0M 2tENESAS 38K2 Group FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT CPU The 38K2 group uses the standard 740 family instruction set Re fer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the
320. le bit to 0 simultaneously transmit and receive disabled when data is transmitted and received in the clock synchronous serial I O mode any one of data transmission and reception cannot be stopped Reason In the clock synchronous serial I O mode the same clock is used for transmission and reception If any one of transmission and reception is disabled a bit error occurs because transmission and reception cannot be synchronized In this mode the clock circuit of the transmission circuit also operates for data reception Accordingly the transmission circuit does not stop by clearing only the transmit enable bit to 0 transmit disabled Also the transmission circuit is not initialized by clearing the serial I O enable bit to 0 Serial I O disabled refer to 1 Rev 2 00 Oct 15 2006 page 66 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 2 3 4 Notes when selecting clock asynchronous serial I O Serial 1 0 Stop of transmission operation Clear the transmit enable bit to 0 transmit disabled Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I O enable bit is cleared to 0 Serial I O disabled the internal transmission is running in this case since pins TxD RxD SCLK and SRDY function as I O ports the transmission data is not output When data is written to the transmit buffer regist
321. le register is 0 When this bit is 1 the write operation from the CPU is invalid and each access from the external bus causes count up operation Memory channel controller The CPU register consists of the follows Main sequencer Internal memory request signal generating circuit External memory channel request signal generating circuit Address end detection circuit Terminal end input processing circuit 4 Transmit Receive Data Buffer Part The transmit receive data buffer part consists of the 8 bit transmit buffer register TXBUF and the 8 bit receive buffer register RXBUF Both CPU channel and memory channel use the same transmit buffer register receive buffer register to transfer a data to an exter nal MCU bus Rev 2 00 Oct15 2006 page 74 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION 5 External Pin The external bus interface has the following pins to connect with an external MCU bus Chip Select sassen P34 ExCS C7 Xe 0 lt srisiusisicsrisisniiiisisrins P37 ExA0 D ai aer AET hiveneceuctinsteneaey P10 DQo ANo to P17 DQ7 AN7 P36 ExRD repareert P35 ExWR RET P33 ExINT It also has the following pins to connect with an external DMAC Each pin can be programmed for an ordinary port function or a DMA interface pin function DMA request aiseee P40 ExDREQ RxD DMA acknowledgment P41 ExDACK TxD Terminal count ee P42 ExTC SCLK It also has the status read sele
322. lecting fsyn as an internal system clock change the system clock selection bit to main clock f Xin before executing STP instruction It is because the following are needed for the low power consumption fuss must be stopped by disabling PLL operation in Stop mode The taimer 1 for waiting oscillation stabilization when returning from Stop mode will require the input count source Rev 2 00 Oct 15 2006 page 89 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 12 Clock generating circuit 2 12 Clock generating circuit This paragraph explains the registers setting method and the notes related to the clock generating circuit 2 12 1 Memory map 001016 USB control register USBCON 003B16 CPU mode register CPUM OFF816 PLL control register PLLCON Fig 2 12 1 Memory map of registers related to clock generating circuit 2 12 2 Related registers USB control register b7 b6 b5 b4 b3 b2 bi bO USB control register USBCON Address 1016 I l B Name Function i A 0 Returning to BUS idle state by writing 1 first R keup bit 0 Emoe WE RUP and then 0 Remote wakeup signal K state output 1 TrON output control bit z L output mode valid in TRONE 1 D H output mode valid in TRONE 1 E TrON D enable bit p TrON port output disabled Hi Z state TTON port output enabled a reference voltage Normal mode valid in VREFE 1 control bi
323. lection bits Vcc V 0 75 MHz 1 5 MHz 3 MHz 3 00 to 5 25 4 00 to 5 25 CPU mode register CPUM address 3B16 0 Main clock f XIN b7 b6 00 01 10 11 system clock system clock system clock 8 8 divide mode 4 4 divide mode 2 f f f 2 divide mode f system clock Through mode Fig 2 12 5 Related registers setting Rev 2 00 Oct15 2006 page 92 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 12 Clock generating circuit 2 Generation of internal clock f using fsyn fuss division clock Table 2 12 2 shows the example of internal clock f generation using fsyn Figure 2 12 6 shows the related registers setting Table 2 12 2 Example of internal clock f generation using fsyn fuss USB clock division f System clock division 6 Power source voltage ratio selection bits So ratio selection bits Vcc V 00 0 75 MHz 11 00 z 01 8 MHz 10 11 4 00 to 5 25 00 10 1 PLL control register bits 4 3 2 CPU mode register bits 7 6 Rev 2 00 Oct 15 2006 page 93 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 12 Clock generating circuit 1 Select main clock f Xin as system clock and set clock division mode CPU mode register CPUM address 3B16 0 Main clock f XiN b7 b6 system clock 8 8 divide mode system clock 4 4 divide mode system clock 2 2 div
324. level for 20 cycles or longer clocks of p XIN Clock input XOUT Clock output Connect a ceramic or crystal resonator between the XIN and XOUT pins When entering an externally drived clock enter it from XIN and leave XOUT open USBVREF USB reference voltage input Connect this pin to Vcc when not using TrON USB reference voltage output Leave this pin open when not using DO D0 USB upstream input Input L level when not using D1 D1 USB downstream input Input L level when not using D2 D2 USB downstream input Input L level when not using POo to P07 Input port PO Input L or H level or keep open Pio to P15 Input port P1 Input L or H level or keep open P16 Input port P1 Input L or H level or keep open Input H level only at release of reset P17 Input port P1 Input L or H level or keep open P20 to P24 Input port P2 Input L or H level or keep open P30 to P37 Input port P3 Input L or H level or keep open P40 RxD input This is a serial data input pin P41 TxD output This is a serial data output pin P42 SCLK input This is a serial clock input pin Input H level only at release of reset P43 BUSY output This is a BUSY output pin P50 to P57 Input port P5 Inpu
325. ll up control register PULL5 Address OFF216 B Name f _ Function r No pull up g P5o pul l up control bit Pull up e Nothing is arranged for this bit This is a write disabled bit When this bit is read out the contents are 0 Nothing is arranged for these bits These are write disabled bits When these bits are read out the contents are 0 Fig 2 1 5 Structure of Port P5 pull up control register Rev 2 00 Oct 15 2006 page 4 of 112 2RENESAS REJ09B0338 0200 APPLICATION 2 1 I O port 38K2 Group APPLICATION 2 1 I O port 2 1 3 Handling of unused pins Table 2 1 1 Handling of unused pins Pins Ports name Handling PO P1 P2 P3 P4 Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kQ P5 P6 to 10 kQ Set to the output mode and open at L or H level VREF Connect to Vss GND Xout Open only when using an external clock USBVrer Connect to Vcc TrON Open DO DO Connect each to Vss through a resistor of 1 KQ to 10 kQ Di D1 D2 D2 Rev 2 00 Oct 15 2006 page 5 of 112 RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 1 I O port 2 1 4 Notes on input and output pins 1 Modifying output data with bit managing instruction When the port latch of an I O port is modified with the bit managing instruction the value of the unspecified bit may be changed Reason The bit managing instructions are read modify write form
326. ministration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications You should use the products described herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measure
327. mit enable bit is set Serial 1 0 When the transmit interrupt is used set the transmit interrupt enable bit to transmit enabled as shown in the following sequence Set the interrupt enable bit to 0 disabled with CLB instruction Prepare serial I O for transmission reception Set the interrupt request bit to 0 with CLB instruction after 1 or more instruction has been executed Set the interrupt enable bit to 1 enabled Reason When the transmission enable bit is set to 1 the transmit buffer empty flag and transmit shift register completion flag are set to 1 The interrupt request is generated and the transmission interrupt bit is set regardless of which of the two timings listed below is selected as the timing for the transmission interrupt to be generated e Transmit buffer empty flag is set to 1 e Transmit shift register completion flag is set to 1 Rev 2 00 Oct 15 2006 page 68 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 5 USB function 2 5 USB function Some application notes are available on the Web site Renesas Technology Corp Homepage USB Device http www renesas com en usb Please refer to them for explanation and application of USB function Rev 2 00 Oct 15 2006 page 69 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 6 HUB function 2 6 HUB function Some application notes are available on the Web site Renesas Technology
328. modes This Boot ROM area has had a standard serial I O mode control program stored in it when shipped from the factory However the user can write a rewrite control program in this area that suits the user s application sys tem This Boot ROM area can be rewritten in only parallel I O mode Power source voltage Vcc Specifications 3 00 5 25 V L version Program and erase in 4 00 to 5 25 V of Vcc 3 00 4 00 V L version Program and erase in 3 00 to 5 25 V of Vcc Program Erase VPP voltage VPP 4 50 5 25 V Flash memory mode 3 modes Flash memory can be manipulated as follows CPU rewrite mode Manipulated by the Central Processing Unit CPU Parallel I O mode Manipulated using an external programmer Note 1 Standard serial I O mode Manipulated using an external programmer Note 1 Erase block division User ROM area 1 block 32 Kbytes Boot ROM area 1 block 4 Kbytes Note 2 Program method Byte program Erase method Batch erasing Program Erase control method Program Erase control by software command Number of commands 6 commands Number of program Erase times 100 times Data retention period 10 years ROM code protection Available in parallel I O mode and standard serial I O mode Notes 1 In the parallel I O mode or the standard serial I O mode use the exclusive external equipment flash programmer which supports the 38K2
329. monitor input Vcc Note 2 1 Voc PVcc DVcc Note 2 14 21 22 GND GND Note 1 7 Vss PVss Note 1 11 20 Notes 1 When connecting a serial programmer first connect both GNDs to the same GND level 2 Vcc power of MFW 1 is supplied from a target board Power consumption of MFW 1 is Max 200 mA when serial programming Therefore when the current capacity of target borad is short connect AC adapter and supply power source to MFW 1 Rev 2 00 Oct 15 2006 page 105 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory 2 14 6 CPU rewrite mode In the CPU rewrite mode issuing software commands through the Central Processing Unit CPU can rewrite the built in flash memory Accordingly the contents of the built in flash memory can be rewritten with the microcomputer itself mounted on board without using the programmer Store the rewrite control program to the built in flash memory in advance The built in flash memory cannot be read in the CPU rewrite mode Accordingly after transferring the rewrite control program to the internal RAM execute it on the RAM The following commands can be used in the CPU rewrite mode read array read status register clear status register program erase all block and block erase For details concerning each command refer to CHAPTER 1 Flash memory mode CPU rewrite mode 1 CPU rewrite mode beginning release procedures Operation procedure in the CPU rewrite mode fo
330. n State remaining Fig 3 4 69 Index00 low Structure of External I O configuration register Rev 2 00 Oct 15 2006 page 67 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers Index 0116 Transmit Receive buffer register RXBUF TXBUF address 003416 At reset H W S W RXBUF The data received from an external bus is written here 0 TXBUF at the rise timing of external write signal The data transmitted to an external bus is written here at the timing of internal CPU write or memory write Bit symbol Bit name Function The receive buffer register RXBUF contents can be read out by reading to this address with the CPU The data which the CPU has written to this address is stored in the transmit buffer register TXBUF However do not perform write operation with the CPU to this address if the memory channel direction control bits of memory channel operation mode register is 102 transmit mode and the memory channel status bits of EXB interrupt source register are 012 or 102 memory channel being operating Fig 3 4 70 Index01 low Structure of Transmit Receive buffer register b7 bo fofofofofo Index 0216 Memory channel operation mode register MCHMOD address 003416 Bit symbol Bit name Function At reset H W S W MC_DIR Memory channel direction b1b0 0 1 0 control
331. n At reset H W S W B1VAL02 Buffer 1 enable bit When the selected endpoint is IN writing 1 to this bit O 5 makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write In double buffer mode this bit is valid Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 32 Structure of EP02 control register 3 b7 bO fofofofofofofo EPO3 control register 3 EPO3CON3 address 001C16 Bit symbol Bit name Function At reset H W S W B1VAL03 Buffer 1 enable bit When the selected endpoint is IN writing 1 to this bit 0 makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write In double buffer mode this bit is valid Write 0 when writing 0 is read when reading e remaining Fig 3 4 33 Structure of EP03 control register 3 Rev 2 00 Oct 15 2006 page 50 of 99 2RENESAS REJ09B0338 0200 38K2 Group APPENDIX 3 4 List of registers b7 bo fofofofofofofo EP10 control register 3 EP10CONS3 address 001C16 Bit symbol Bit name Function At reset H W
332. n V is 1 The branch address is specified by a relative address When V is 0 the next instruction is executed Ai or Mi lt 0 This instruction clears the designated bit i of A or M This instruction clears C This instruction clears D CLI This instruction clears I CLT This instruction clears T CLV This instruction clears V CMP Note 3 When T 0 this instruction subtracts the con tents of M from the contents of A The result is not stored and the contents of A or M are not modified When T 1 the CMP subtracts the contents of M from the contents of M X The result is not stored and the contents of X M and A are not modified M X represents the contents of memory where is indicated by X This instruction takes the one s complement of the contents of M and stores the result in M This instruction subtracts the contents of M from the contents of X The result is not stored and the contents of X and M are not modified This instruction subtracts the contents of M from the contents of Y The result is not stored and the contents of Y and M are not modified Rev 2 00 Oct15 2006 page 88 of 99 REJ09B0338 0200 This instruction subtracts 1 from the contents of Aor M ztENESAS Rev 2 00 Oct15 2006 page 89 of 99 REJ09B0338 0200 ztENESAS
333. n data transfer can be assigned to any area of the multi channel RAM for each endpoint Buffer area beginning address The buffer area configuration register address OFED16 defines the beginning address of the buffer area every 32 bytes for each Endpoint However the only RAM area is configurable 00h Address 000016 01h Address 002016 Not configurable 02h Address 004016 to 1Fh Address 03E016 Configurable interrupt source dependant buffer area offset address An offset value is added to the beginning address of each source which is specified by the interrupt source register address 001D16 for each endpoint This section describes in detail the beginning address specified by the buffer area set register as offset address 00h according to each endpoint 1 Endpoint 00 Endpoint 00 has two kinds of interrupt sources for accessing the buffer The respective address offsets are BSRDYOO SETUP Buffer Ready Interrupt Offset address 00h BRDYOO OUT or IN Buffer Ready Interrupt Offset address 08h 2 Endpoint 01 The buffer area offset address for each interrupt source for of End point 01 varies according to the contents of the EP01 set register address 001916 eIn single buffer mode DBLBO1 O Endpoint 01 has only one interrupt source for accessing the buffer BORDY01 Buffer 0 Ready Interrupt Offset address 00h eIn double buffer mode DBLBO1 1 Endpoint 01 has two kinds of interrupt sour
334. n neeeeeensneeeeeeenseceeeeeeeseeeeeeeesneeeeeeeeseeeennenes 97 3 8 SFR Memory Mapsen ieaoo aa sic aN Aaaa aN aaa N aaa aaaea aaaea 98 3 9 Pin configuration S eisenii AAEREN AE 99 Rev 2 00 Oct15 2006 page 3 of 14 7tENESAS REJ09B0338 0200 38K2 Group List of figures List of figures CHAPTER 1 HARDWARE Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig ONOoaRWBD PONNAONNMN HHH a eer eer HH Oo oFWNHHTOCOOANDAKRWN CO Fig 26 Fig 27 Fig 28 Fig 29 Fig 30 Fig 31 Fig 32 Fig 33 Fig 34 Fig 35 Fig 36 Fig 37 Fig 38 Fig 39 Fig 40 Fig 41 Fig 42 Fig 43 Rev 2 00 Oct 15 2006 REJ09B0338 0200 Pin configuration Of 38K2 group cceseceeeeceeeceeeeceeeeceeaeeeeeeeesesaeeeseaeeseaeeeseaaeseeeeeeeeaeeseaes 2 Functional block diagram siiras ansia aai iaaiiai 3 Part TUIMIDG RING serioena E E EE ATE ENO 5 Memory expansion Pla sersreni n R Gioia ase 6 740 Family CPU register Structure ssssiscreaiisssiunnniuanannaindna kaniinia a aaia 7 Register push and pop at interrupt generation and subroutine Call c eee 8 Structure Of CPU mode register cceececceeeeeeeeeeeeeeaeeeeeneeecaaeeeeeaaeeseaeeeesaaeeseeeeesenaaeeenes 10 NIG MOLY map diagram sessione ei EERE cad cvs EEA EE E 11 Memory map of special function register SFR ssssssesssssssssrsssrsssrssrrrssrrsrriesrrresrns 12 Port block diagrami
335. n reading Fig 49 Structure of EP01 control register 2 b7 bO ofofofolofo o EP01 control register 3 EP01CON3 address 001C16 State remaining Bit symbol Bit name Function At reset H W S W B1VAL01 Buffer 1 enable bit When the selected endpoint is IN writing 1 to this bit makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write In double buffer mode this bit is valid 0 Fig 50 Structure of EP01 control register 3 Not used Write 0 when writing 0 is read when reading b7 bO ofofofofo EP01 interrupt source register EP01REQ address 001D16 State remaining Bit symbol Bit name At reset Function H W S W BORDY01 USB function Endpoint 1 buffer 0 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer 0 is ready state enabled to be read written on USB function Endpoint 1 0 can be set by software but 1 cannot be set 0 0 B1RDY01 USB function Endpoint 1 buffer 1 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued In single buffer mode this bit is invalid This bit is set to
336. nce synchronized with the transmission enalbed take the following sequence Set the serial I O transmit interrupt enable bit to 0 disabled Set the transmit enable bit to 1 Set the serial I O transmit interrupt request bit to 0 after 1 or more instructions have been executed Set the serial I O transmit interrupt enable bit to 1 enabled Rev 2 00 Oct 15 2006 page 24 of 130 2tENESAS REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION 38K2 Group 50 Serial I O status register SIOSTS address 002716 0 Buffer full 1 Buffer empty Receive buffer full flag RBF 0 Buffer empty 1 Buffer full 0 Transmit shift in progress 1 Transmit shift completed Overrun error flag OE 0 No error 1 Overrun error Parity error flag PE 0 No error 1 Parity error Framing error flag FE 0 No error 1 Framing error Summing error flag SE U FE U FE 0 OE U PE E 0 1 OE U PE 1 b0 UART control register UARTCON address OFE116 0 8 bits 1 7 bits Parity enable bit PARE 0 Parity checking disabled 1 Parity checking enabled Parity selection bit PARS 0 Even parity 1 Odd parity 0 1 stop bit 1 2 stop bits Not used return 0 when read This is a write disabled bit Not used return 1 when read Fig 22 Structure of serial I O control registers Rev 2 00 Oct15 2006 page 25 of 130 REJ09B0338
337. nction address bit In ADOE 0 this value changes after writing In ADOE 1 this value changes after completion of SET_ADDRESS control transferring 0 0 b7 Not used Write 0 when writing 0 is read when reading Fig 33 Structure of USB function address register USB HUB address register USBA1 address 001316 State remaining Bit symbol Bit name Function At reset H W S W USBADD1 6 0 USB HUB address bit In AD1E 0 this value changes after writing In AD1E 1 this value changes after completion of SET_ADDRESS control transferring 0 0 b7 Not used Write 0 when writing 0 is read when reading Fig 34 Structure of USB HUB address register Frame number register Low FNUML address 001416 State remaining Bit symbol Bit name Function At reset H W S W FNUM 7 0 Frame number low bit The frame number is updated at SOF reception In In definite definite Fig 35 Structure of Frame number register Low b7 bO fofofofofo Frame number register High FNUMH address 001516 Bit symbol Bit name Function At reset H W S W t FNUM 10 8 Frame number high bit The frame number is updated at SOF reception In In definite definite b7 b3
338. nd each timer latch at the same time 1 Jele When this register is read out each timer s count value is read m Engg RAG ele EARE EERE ee Fig 2 3 4 Structure of Timer 2 Timer X Rev 2 00 Oct 15 2006 page 24 of 112 2RENESAS REJ09B0338 0200 38K2 Group Timer X mode register b7 b6 b5 b4 b3 b2 b1 bO APPLICATION 2 3 Timer Timer X mode register TM Address 2316 Timer mode Pulse output mode Event counter mode Pulse width measurement mode The function depends on the operating mode of Timer X Refer to Table 2 3 1 Nothing is arranged for these bits These are write disabled bits When these bits are read out the contents are 0 Fig 2 3 5 Structure of Timer X mode register Table 2 3 1 CNTRo active edge selection bit function Timer X operation modes Timer mode Q CNTRo active edge selection bit bits 2 of address 2316 contents CNTRo interrupt request occurrence Falling edge No influence to timer count 4 CNTRo interrupt request occurrence Rising edge No influence to timer count Pulse output mode Q Pulse output start Beginning at H level CNTRo interrupt request occurrence Falling edge 4 Pulse output start Beginning at L level CNTRo interrupt request occurrence Rising edge Event counter mode 0 Timer X Rising edge count CNTRo interrupt request occurrence Falling edge 4 Timer X
339. ng State remaining Fig 3 4 94 Structure of EP01 buffer area set register Rev 2 00 Oct 15 2006 page 77 of 99 2RENESAS REJ09B0338 0200 38K2 Group EP02 buffer area set register EPO2BUF address OFED16 APPENDIX 3 4 List of registers Bit symbol Bit name Function At reset H W S W BADD02 4 0 EP02 beginning address set bit Set the beginning address of EP02 s buffer area 32 byte unit b4b3b2b1b0 004016 006016 0 03C016 1 03E016 0 rosie Write 0 when writing 0 is read when reading Fig 3 4 95 Structure of EP02 buffer area set register EPO3 buffer area set register EPO3BUF address OFED16 State remaining Bit symbol Bit name Function At reset H W S W BADDO3 4 0 EP08 beginning address set bit Set the beginning address of EP03 s buffer area 32 byte unit b4b3b2b1b0 000 1 0 004016 006016 03C016 03E016 0 Not used Write 0 when writing 0 is read when reading Fig 3 4 96 Structure of EP03 buffer area set register EP10 buffer area set register EP10BUF address OFED16 State remaining Bit symbol Bit name Function At reset H W S W BADD10 4 0 EP10 beginning address set bit Set the beginning address of EP10 s buffer area
340. ng to the related registers setting shown by Figure 2 8 8 Figure 2 8 9 shows the control procedure for 8 bit read and Figure 2 8 10 shows the control procedure for 10 bit read X This bit is not used here Set it to O or 1 arbitrarily ADCON address 3616 XXXX00002 P10 DQo ANo pin selected as analog input pin A D conversion start Judgment of A D conversion completion Read out of conversion result Fig 2 8 9 Control procedure for 8 bit read X This bit is not used here Set it to 0 or 1 arbitrarily P10 DQo ANo pin selected as analog input pin ADCON address 3616 lt XXXX00002 A D conversion start ADCON address 3616 bit3 Judgment of A D conversion completion 1 Read out AD2 address 3816 Read out of high order digit b9 b8 of conversion result Read out AD1 address 3716 Read out of low order digit b7 b0 of conversion result Vv N LNG Fig 2 8 10 Control procedure for 10 bit read Rev 2 00 Oct 15 2006 page 76 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 8 A D converter 2 8 4 Notes on A D converter 1 Analog input pin Make the signal source impedance for analog input low or equip an analog input pin with an external capacitor of 0 01 uF to 1 uF Further be sure to verify the operation of application products on the user side Reason An analog input pin includes the capacitor for analog voltage comparison Acc
341. ng to the watchdog timer control register address 003916 each watchdog timer H and L is set to FF 16 FF16 is set when watchdog timer control register is y written to System clock 1 169 Watchdog timer L 8 HARDWARE FUNCTIONAL DESCRIPTION Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register address 003916 per mits selecting a watchdog timer H count source When this bit is set to 0 the count source becomes the underflow signal of watchdog timer L The detection time is set to 131 072 ms at sys tem clock 8 MHz frequency When this bit is set to 1 the count source becomes the system clock divided by 16 The detection time in this case is set to 512 us at system clock 8 MHz frequency This bit is cleared to O after resetting Operation of STP instruction disable bit Bit 6 of the watchdog timer control register address 003916 per mits disabling the STP instruction when the watchdog timer is in operation When this bit is O the STP instruction is enabled When this bit is 1 the STP instruction is disabled Once the STP instruction is executed an internal reset occurs When this bit is set to 1 it cannot be rewritten to 0 by program This bit is cleared to 0 after resetting Data bus FF16 is set when tpn watchdog timer 9 Q control register is 4 Watchdog timer H 8
342. nput to the MCU via the RxD pin In transmission the read data and status are synchronized with the fall of the transfer clock and output from the TxD pin The TxD pin is for CMOS output Transfer is in 8 bit units with LSB first When busy such as during transmission reception erasing or program execution the SRDY BUSY pin is H level Accordingly always start the next transfer after the SRDY BUSY pin is L level Also data and status registers in a memory can be read after in putting software commands Status such as the operating state of the flash memory or whether a program or erase operation ended successfully or not can be checked by reading the status register Here following explains software commands status registers etc 7RENESAS 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION Table 12 Description of pin function Standard Serial I O Mode Pin name Vcc Vss Signal name Power supply Function Apply 3 00 to 5 25 V L version to the Vcc pin and 0 V to the Vss pin VccE Power supply Connect this pin to Vcc CNVss VPP Connect this pin to VPP VPP 4 50 to 5 25 V CNVss2 CNVss2 Connect this pin to Vss VREF Analog reference voltage Connect this pin to Vcc when not using DVcc PVcc Analog power supply Connect this pin to Vcc PVss Analog power supply Connect this pin to Vss RESET Reset input To reset input L
343. nsmit interrupt request bit INTo interrupt request bit CNTRo interrupt request bit Timer X interrupt request bit Key on wake up interrupt request bit Timer 1 interrupt request bit A D conversion interrupt request bit Timer 2 interrupt request bit Nothing is arranged for this bit This is a an write disabled bit When this bit is read 0 can be set by software but 1 out the contents are 0 cannot be set 0 No interrupt request issued 1 Interrupt request issued bO Interrupt control register 1 Interrupt control register 2 ICON1 address 003E16 ICON2 address 003F16 USB bus reset interrupt enable bit INT1 interrupt enable bit USB SOF interrupt enable bit USB HUB interrupt enable bit USB device interrupt enable bit Serial I O receive interrupt enable bit EXB interrupt enable bit Serial I O transmit interrupt enable bit INTo interrupt enable bit CNTRo interrupt enable bit Timer X interrupt enable bit Key on wake up interrupt enable bit Timer 1 interrupt enable bit A D conversion interrupt enable bit Timer 2 interrupt enable bit Fix this bit to 0 0 can be set by software but 1 0 Interrupts disabled cannot be set 1 Interrupts enabled Fig 14 Structure of interrupt related registers Rev 2 00 Oct 15 2006 page 18 of 130 2RENESAS REJ09B0338 0200 38K2 Group Key Input Interrupt Key on Wake Up A Key on wake up interrupt request is generated
344. nsmit receive buffer register in the CPU channel receive enable bit 1 or when the CPU channel receive enable bit is 0 4 This bit is cleared to 0 when writing to the transmit receive buffer register in the CPU channel transmit enable bit 1 or when the CPU channel transmit enable bit is 0 Fig 110 Structure of EXB interrupt source Rev 2 00 Oct15 2006 page 77 of 130 REJ09B0338 0200 register RENESAS 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION b7 bo fofofofofo EXB index register EXBINDEX address 003316 Bit name Function At reset H W S W i Bit symbol INDEX 2 0 Index bits The accessible register using the register window depends on these index bits contents as follows b2b1b0 0 0 External I O configuration register Transmit Receive buffer register Memory channel operation mode register Memory address counter End address register Do not set Do not set 1 1 Do not set a a a 34000000 0 Write 0 when writing 0 is read when reading Fig 111 Structure of EXB index register Register window 1 EXBREG1 address 003416 State remaining Bit symbol Bit name Function At reset H W LOW_WIN 7 0 The accessible register using this register window depends on the EXB index register contents as follows Index value
345. nsmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write In double buffer mode this bit is valid 0 Not used Write 0 when writing 0 is read when reading Fig 59 Structure of EP02 control register 3 b7 bO fofofofofo EP02 interrupt source register EPO2REQ address 001D16 State remaining Bit symbol Bit name Function At reset H W S W BORDY02 USB function Endpoint 2 buffer 0 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer 0 is ready state enabled to be read written on USB function Endpoint 2 0 can be set by software but 1 cannot be set 0 0 B1RDY02 USB function Endpoint 2 buffer 1 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued In single buffer mode this bit is invalid This bit is set to 1 when the buffer 1 is ready state enabled to be read written on USB function Endpoint 2 in double buffer mode 0 can be set by software but 1 cannot be set USB function Endpoint 2 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when STALL response occurs on USB functi
346. nterface EXB 2 8 A D converter 2 9 Watchdog timer 2 10 Reset 2 11 Frequency synthesizer PLL 2 12 Clock generating circuit 2 13 Standby function 2 14 Flash memory APPLICATION 38K2 Group 2 1 I O port 2 1 I O port This paragraph explains the registers setting method and the notes related to the I O ports 2 1 1 Memory map 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 Port P direction register PED OFFO16 Port PO pull up control register PULLO OFF216 Port P5 pull up control register PULLS Fig 2 1 1 Memory map of registers related to I O port Rev 2 00 Oct15 2006 page 2 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 1 I O port 2 1 2 Related registers Port Pi b7 b6 b5 b4 b3 b2 b1 bO Port Pi Pi i 0 1 2 3 4 5 6 Note Address 0016 0216 0416 0616 0816 OA16 OC168 B Name Function e O ree Write e In input mode Read Value of pins Note Since the following ports are not allocated the corrrsponding bits can not be used e P20 to P23 e P44 to P47 e P64 to P67 Fig 2 1 2 Structure of Port Pi i 0 to 6 pot of of of of of of ofa of of of of of of of off Port Pi direction register b7 b6 b5 b4 b3 b2 bi bO Port Pi direction register PiD i 0 1 2 3 4 5 6 Note Address 0116 0316 0516 0716 0916 0B16 0D16 0 Port Pio input mode 1 Port Pio outpu
347. nterface Engine SIE Device Control Unit DCU Internal Memory Interface MIF CPU Interface CIF 2 3 4 n A U aH USB Function Control Circuit DCU control DCU status L MIF control O a HARDWARE FUNCTIONAL DESCRIPTION EAN control L eee status USB Transceiver Transmit Receive data Multi Channel RAM Fig 24 USB Function Control Circuit USBFCC block diagram 1 Serial Interface Engine SIE The SIE performs the following USB lower layer protocols pack ets transactions Sampling of receive data and clock generation of transmit clock Serial to parallel conversion of transmit receive data NRZI Non Return Zero Invert encode decode Bit stuffing unstuffing SYNC Synchronization Pattern detection EOP End of Packet detection USB address detection endpoint detection CRC Cyclic Redundancy Check generation and checking 2 Device Control Unit DCU The DCU manages the following USB upper layer protocols ad dress endpoint and control transfer sequence Status control for each endpoint Control transfer sequence control Memory interface status control Rev 2 00 Oct15 2006 page 27 of 130 REJ09B0338 0200 3 Memory Interface MIF The MIF controls the flow of data transfer between the SIE and the multi channel RAM under the management of the DCU 4 CPU Interface CIF The CIF performs the following functions Mode setting via registers DCU control signal generation DC
348. ntrol register 2 Rev 2 00 Oct15 2006 page 74 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers Serial I O control register b7 b6 b5 b4 b3 b2 bi bO Serial I O control register SIOCON Address OFE016 B Name Function At esee RW BRG count source System clock selection bit CSS System clock 4 1 Serial I O synchronous af clock synchronous serial O clock selection bit SCS 0 BRG output divided by 4 1 External clock input e In UART BRG output divided by 16 External clock input divided by 16 Sry output enable bit H P43 pin operates as ordinary I O pin SRDY P43 pin operates as Srpy output pin Transmit interrupt Interrupt when transmit buffer has emptied source selection bit TIC Interrupt when transmit shift operation is completed Transmit enable bit TE p Transmit disabled Transmit enabled Receive enable bit RE D Receive disabled Receive enabled Serial I O mode selection bit A Clock asynchronous UART serial I O SIOM Clock synchronous serial I O 7 Serial I O enable bit 0 Serial I O disabled pins P40 to P43 operate as ordinary I O pins 1 Serial I O enabled pins P40 to P43 operate as serial I O pins Fig 3 4 87 Structure of Serial I O control register UART control register b7 b6 b5 b4 b3 b2 bi bO UART control register UARTCON Address OFE1 16 pt Name Function atvoset RW Character length selection bit 8 bits Race CHAS
349. number bit Single buffer mode These bits are invalid 0 6 0 Double buffer mode Set the transmitting byte number of buffer 1 OUT Receive byte number bit Single buffer mode These bits are invalid Double buffer mode The received byte number of buffer 1 is automatically set Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 53 Structure of EP01 byte number register 1 EP01 MAX packet size register EPO1MAX address OFEC16 At reset H W Bit symbol Bit name Function MXPS01 Max packet size bit IN These bits are invalid 6 0 OUT Set the maximum packet size b7 Not used Write 0 when writing 0 is read when reading e remaining Fig 54 Structure of EP01 MAX packet size register Rev 2 00 Oct 15 2006 page 43 of 130 7tENESAS REJ09B0338 0200 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION EP01 buffer area set register EPO1BUF address OFED16 Bit symbol Bit name Function At reset H W S W BADDO1 4 0 EP01 beginning address set bit Set the beginning address of EP01 s buffer area 32 byte unit b4b3b2b1b0 000 1 0 004016 0001 1 006016 111 1 0 03C016 111 1 1 03E016 0 Write 0 when writing 0 is read when reading Fig 55 Structure
350. o 0 0 Joio Fig 2 4 9 Structure of Interrupt control register 2 Rev 2 00 Oct 15 2006 page 44 of 112 RENESAS REJ09B0338 0200 APPLICATION 2 4 Serial I O APPLICATION 38K2 Group 2 4 Serial I O 2 4 3 Serial I O connection examples 1 Control of peripheral IC equipped with CS pin Figure 2 4 10 shows connection examples of a peripheral IC equipped with the CS pin There are connection examples using a clock synchronous serial I O mode 1 Only transmission 2 Transmission and reception Using the RxD pin as an I O port Port CS Scik CLK TxD DATA 38K2 group Peripheral IC 38K2 group Peripheral IC OSD controller etc E PROM etc 3 Transmission and reception 4 Connection of plural IC When connecting RxD with TxD When connecting IN with OUT in peripheral IC Peripheral IC 1 38K2 group Peripheral Ic 2 38K2 group E PROM etc CS CLK 1 Select an N channel open drain output for TxD pin output control IN x2 Use the OUT pin of peripheral IC which is an N channel open drain output and becomes high impedance during receiving data OUT Peripheral IC 2 Notes Port means an output port controlled by software Fig 2 4 10 Serial I O connection examples 1 Rev 2 00 Oct 15 2006 page 45 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 2 Connection with microcomputer Figure 2 4 11 shows connection examples with another microcomput
351. ock 4 X denotes a given address in the User ROM area Rev 2 00 Oct15 2006 page 105 of 130 RENESAS REJ09B0338 0200 BA Note 3 D016 38K2 Group Erase All Blocks Command 2016 2016 By writing the command code 2016 in the first bus cycle and the confirmation command code 2016 in the second bus cycle that follows the operation of erase all blocks erase and erase verify starts Whether the erase all blocks command is terminated can be con firmed by reading the status register or the RY BY Status Flag of flash memory control register When the erase all blocks operation starts the read status register mode is entered automatically and the contents of the status register can be read out at the data bus Do to D7 The status register bit 7 SR7 is set to O at the same time the erase operation starts and is returned to 1 upon comple tion of the erase operation In this case the read status register mode remains active until the read array command FF 16 is writ ten The RY BY Status Flag is O during erase operation and 1 when the erase operation is completed as is the status register bit 7 After the erase all blocks end erase results can be checked by reading the status register For details refer to the section where the status register is detailed Block Erase Command 2016 D016 By writing the command code 2016 in the first bus cycle and the confirmation comman
352. ock diagram of USB down port peripheral circuits D1 D1 neeese 60 Block diagram of USB down port peripheral circuits D2 D2 Lasses 60 USB HUB interrupt Control ctecisic tie hence aai ia 61 HUB related registers cccccceceeeeeeeeeceneeeeeeneeceeaeeeeeaaeeesaeeeeeaaeseeeeesesaeseeeeeesteaeeseneaeeenaees 62 Structure of HUB interrupt source enable register ccceceeeeeeeeeeeeeeeteeeeeeeeseeeeeaees 63 Structure of HUB interrupt source register eee cceeee sete eeeeeee cee eeeeeeeeeeeeeetaeeteaees 63 Structure of HUB downstream port index register cceeeeeeeeeseeeeeeeseeeeeeeeeeeeeeeeees 64 page 5 of 14 7tENESAS List of figures 38K2 Group Fig 96 Structure of DP1 interrupt source register c cece cece eeeeeeeeeeeeeeeaeeeeeeeeessaeeeteaeees 65 Fig 97 Structure of DP1 Control register cceceeeeeeeceeeeeeeeeeeceeeeeeeeaeeseeeeessaaaeseeeeeesiaaeeneneees 66 Fig 98 Structure of DP1 status reQiSter eee eceeeseeececeeeeeeeeceeeeeeeaeeeeaeeeeaaeeeeceeeeeiaaeeneeeees 66 Fig 99 Structure of DP2 interrupt source register ecceeeeeeeeeeeeeeeeeeceeeeeeeeeaeeeeeeeeessaeeeteaeees 67 Fig 100 Structure of DP2 Control register eeceececeeceee cesses eceeeeeeeaaeeseeeeessaaeeseeneeessaeeeneaeees 68 Fig 101 Structure of DP2 status register eee eeesceeceneeeeeeeeeeeeeeeeeeaeeeeeeeeeeaaeeeeeeeeesaeeeteneeess 68 Fig 102 Structure of Downstream port control register
353. on Endpoint 2 0 can be set by software but 1 cannot be set Fig 60 Structure of EP02 interrupt source Rev 2 00 Oct15 2006 page 46 of 130 REJ09B0338 0200 b7 to b3 Not used Write 0 when writing 0 is read when reading register 2RENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION EP02 byte number register 0 EPO2BYTO address 001E16 At reset H W BOBYTO2 IN Transmit byte number bit Single buffer mode Set the transmitting byte number 0 6 0 Double buffer mode Set the transmitting byte number of buffer 0 OUT Receive byte number bit Single buffer mode The received byte number is automatically set Double buffer mode The received byte number of buffer 0 is automatically set Write 0 when writing 0 is read when reading Bit symbol Bit name Function State remaining Fig 61 Structure of EP02 byte number register 0 EP02 byte number register 1 EPO2BYT1 address 001F 16 At reset H W B1BYT02 IN Transmit byte number bit Single buffer mode These bits are invalid 0 6 0 Double buffer mode Set the transmitting byte number of buffer 1 OUT Receive byte number bit Single buffer mode These bits are invalid Double buffer mode The received byte number of buffer 1 is automatically set Not used Write 0 when writing 0 is read when reading
354. on USB HUB Endpoint 10 This bit is cleared to 0 by the hardware when receiving SETUP token 0 can be set by software but 1 cannot be set Not used Write 0 when writing 0 is read when reading Fig 3 4 39 Structure of EP10 interrupt source register b7 bo fofofofofofolo EP11 interrupt source register EP11REQ address 001D16 State remaining Bit symbol Bit name Function At reset H W S W BORDY11 USB HUB Endpoint 1 buffer 0 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer is ready state enabled to be read written on USB HUB Endpoint 1 0 can be set by software but 1 cannot be set 0 0 Not used Write 0 when writing 0 is read when reading Fig 3 4 40 Structure of EP11 interrupt source register Rev 2 00 Oct15 2006 page 54 of 99 REJ09B0338 0200 2tENESAS State remaining APPENDIX 38K2 Group 3 4 List of registers EPO0O byte number register EPOOBYT address 001E16 At reset H W S W BBYT0O Transmit receive byte number bit OUT The received byte number is automatically set 0 3 0 IN Set the transmitting byte number b7 b4 Not used Write 0 when writing 0 is read when reading Bit symbol Bit name Function
355. onous transfer Fig 3 4 15 Structure of EP03 set register Rev 2 00 Oct15 2006 page 44 of 99 REJ09B0338 0200 2RENESAS e remaining 38K2 Group APPENDIX 3 4 List of registers b7 bo fofofofofofofo EP10 stage register EP10STG address 001916 Bit symbol Bit name Function At reset H W S W SETUP10 SETUP packet detection bit This bit is set to 1 at reception of SETUP packet Writing 0 clears this bit if the next SETUP token does not occur Writing 1 causes no state change of the status flags This bit change is not for an interrupt source 1 1 Write 0 when writing 0 is read when reading 0 0 Fig 3 4 16 Structure of EP10 stage register EP11 set register EP11CFG address 001916 State remaining Bit symbol Bit name Function At reset H W S W b2 b0 Not used Write 0 when writing 0 is read when reading SQCL11 Sequence toggle bit clear bit 0 Toggle bit clear disabled as the next data PID 0 is always read when reading 1 Writing 1 clears the toggle bit and DATAO is used Not used Write 0 when writing 0 is read when reading Transfer direction bit 0 IN transfer disabled 1 IN Data is transmitted to the host Not used Write 0 when writing 0 is read
356. onversion register 2 AD2 Watchdog timer control register WDTCON Reserved Note CPU mode register CPUM Interrupt request register 1 IREQ1 Interrupt request register 2 IREQ2 Interrupt control register 1 ICON1 Interrupt control register 2 ICON2 Port PO pull up control register PULLO Reserved Note Port P5 pull up control register PULLS Interrupt edge selection register INTEDGE Reserved Note Reserved Note Reserved Note PLL control register PLLCON Downstream port control register DPCTL Reserved Note Reserved Note Flash memory control register FMCR Reserved Note Do not write any data to these addresses because these areas are reserved 2tENESAS APPENDIX 3 8 SFR memory map APPENDIX 38K2 Group 3 9 Pin configurations 3 9 Pin configurations oO ERE Zo2 oO oo Nurr OR OHO t MAT SHR o O OOOO O L0 LO LO LO O O O ONAN Ooadaaadakbaadaaaaanada ff JRAKRRRARRRRHE st ca a i 0 POs gt gt P25 P07 gt gt P24 P40 ExDREQ RxD D2 P41 ExDACK TxD lt gt D2 P42 ExTC ScLk lt gt gt Di P43 ExA1 Srpy lt 4 Di1 P30 gt D0 P31 lt gt M388K27M4L XXXFP HP lt gt D0 P32 4 gt gt TrON P33 ExINT lt gt M38K29F8LFP HP USBVREF P34 ExCS lt lt gt DVcc PVcc P3s ExWR lt gt 60 P3e ExRD lt gt PVss P37 ExAO0 lt
357. ordingly when signals from signal source with high impedance are input to an analog input pin charge and discharge noise generates This may cause the A D conversion precision to be worse 2 Clock frequency during A D conversion The comparator consists of a capacity coupling and a charge of the capacity will be lost if the clock frequency is too low Thus make sure the following during an A D conversion f XIN is 500 kHz or more e Do not execute the STP instruction Rev 2 00 Oct 15 2006 page 77 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 9 Watchdog timer 2 9 Watchdog timer This paragraph explains the registers setting method and the notes related to the watchdog timer 2 9 1 Memory map 003916 003B16 Fig 2 9 1 Memory map of registers related to watchdog timer 2 9 2 Related registers Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 bO Watchdog timer control register WDTCON Address 3916 B Name Funcion g Watchdog timer H for read out of high order 6 bits STP instruction disable bit 0 STP instruction enabled 1 STP instruction disabled Watchdog timer H count 0 Watchdog timer L underflow source selection bit 1 System clock 16 gt PECECECE o of of of of of of of of of x x x x x xls Fig 2 9 2 Structure of Watchdog timer control register Rev 2 00 Oct15 2006 page 78 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2
358. ort 2 SEO signal transmit bit Being not output SEO signal being output DSRSMO2 Downs signal ream port 2 resume transmit bit Being not output K signal being output When writing 0 a low speed EOP is output and then a transition to being not output occurs DSRMOD2 Downs read m ream port 2 bus state ode control bit Mode where a downstream port 2 bus state is read using RD signal Mode where a downstream port 2 bus state is read using EOF2 signal internal signal DSLSPD2 Downs ream port 2 USB transfer speed select bit Full speed mode 12MHz Low speed mode 1 5 MHz Fig 3 4 62 Structure of DP2 control register Rev 2 00 Oct 15 2006 page 64 of 99 REJ09B0338 0200 2RENESAS State remaining APPENDIX 38K2 Group 3 4 List of registers b7 bO fofofofofofo DP1 status register DP1STS address 002D16 At reset H W S W DIMINUS D1 signal bit In DSRMOD1 0 a downstream port 1 bus state is n In read using RD signal definite definite In DSRMOD1 1 a downstream port 1 bus state is read using EOF2 signal internal signal D1PLUS D1 signal bit In DSRMOD1 0 a downstream port 1 bus state is n In read using RD signal definite definite In DSRMOD1 1 a downstream port 1 bus state is read using EOF2 signal internal signal Write 0 when writing
359. ort as possible e Be sure to verify the operation of application products on the user side Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin it may cause a microcomputer failure Rev 2 00 Oct 15 2006 page 83 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 11 Frequency synthesizer PLL 2 11 Frequency synthesizer PLL This paragraph explains the registers setting method and the notes related to the frequency synthesizer PLL circuit 2 11 1 Memory map 001016 USB control register USBCON 003B16 CPU mode register CPUM OFF816 PLL control register PLLCON Fig 2 11 1 Memory map of registers related to PLL 2 11 2 Related registers USB control register b7 b6 b5 b4 b3 b2 bi bO USB control register USBCON Address 1016 B nme Funcion 0 Returning to BUS idle state by writing 1 first Remote wakeup bit 0 p and then 0 Remote wakeup signal K state output 1 TrON output control bit z L output mode valid in TRONE 1 H output mode valid in TRONE 1 E TrON D enable bit p TrON port output disabled Hi Z state TTON port output enabled a reference voltage Normal mode valid in VREFE 1 control bit 1 Low current mode valid in VREFE 1 4 USB reference voltage 7 USB reference voltage circuit operation disabled enable bit USB reference voltage circuit operation enabled
360. own port control block consisting of the circuits listed below performs down port controls under supervision of the HUB re peater state operation Down port sequencer circuit Down port state change detect circuit Rev 2 00 Oct 15 2006 page 59 of 130 RENESAS REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION USB Down port Peripheral Circuit Setting The USB down port peripheral circuits can be set with the down stream port control register address OFF916 Figures 89 and 90 show the circuit block diagrams 4 PCON11 qt PCON10 Full Speed 4 PCON11 JDD PCON11 J gt PCON10 PCON10 HUB Module Y PCON11 J gt PCON10 Full gt gt PCON11 i y PCON10 Low PCON11 qt PCON10 Fig 89 Block diagram of USB down port peripheral circuits D1 D1 PCON21 PCON20 PCON21 2 PCON21 Jy PCON20 PCON20 HUB Module n PCON21 J gt PCON20 Full gt gt PCON21 A PCON20 Low PCON21 qt PCON20 Fig 90 Block diagram of USB down port peripheral circuits D2 D2 Rev 2 00 Oct 15 2006 page 60 of 130 2tENESAS REJ09B0338 0200 38K2 Group HUB Interrupt Function The HUB function control circuit ha ing of 10 interrupt sources each through the interrupt source registe rupt sources Table 8
361. page 12 of 14 REJ09B0338 0200 List of figures 3 4 80 Structure of AD Conversion register 2 ececcceseeceeeeesceeeeeeeeeeceneeeeeaaeeseeeeessnaeeseeees 71 3 4 81 Structure of Watchdog timer Control register cccceeeeeeeeseceeeeeeeeeceeaeeesaeeeeeaees 72 3 4 82 Structure of CPU mode register 0 ccceccceeeeeeeeeeeeeeeeeecaeeeeeaeeeseaeeeeeaaeeseeeeeeeaeeesenes 72 3 4 83 Structure of Interrupt request register 1 00 cece e cee eceeeeeeeeee sees eeeeeeeeseeeeeeeeeesaees 73 3 4 84 Structure of Interrupt request register 2 02 cee eeeeeceeeeeeeeeeeeeeeeaeeeeeneeeteaeeeseeeeeeaees 73 3 4 85 Structure of Interrupt Control register 1 e eee eeeeeeeceeeeeeeeeeeeeeeeeeaeeseeeeeessaeeetenes 74 3 4 86 Structure of Interrupt Control register 2 ou eecceceeeeceeeeeeeneeeeeteeeeeaeeseeeeeettaeeeeenes 74 3 4 87 Structure of Serial I O Control register c cccecceeeeececeeeeeeeeeeeseneeeesaaeeseeeeeeenaeeeeenees 75 3 4 88 Structure of UART Control register cececcecceeeeeeeeeeeeeeeeeeeeeseaeeeeeaaeessneessaaeeeenees 75 3 4 89 Structure of Baud rate generator eeeececcceeceeeeeeceeeeeeeeaeeeeeeeeeeeaeeeseneeesseeeseaeeseaees 76 3 4 90 Structure of EP01 MAX packet size register ccccceeeeseeeeeteeeeeeeeeteeeeeettaeeeeeeees 76 3 4 91 Structure of EP02 MAX packet size register cccceceeeeeeeeeneeeeeeeeeseeeeeeeeaeeteenes 76 3 4 92 Structure of EPO03 MAX packet size register ccceecee
362. pensable yet wide ranging HUBFCC structure and an external interrupt function and I O ports imple mented in the standard features of this MCU enable the power supply management essential for USB HUB functions and also al low users to easily and effortlessly configure their optimum system Up port USB host 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION HUB Function Control Circuit Block Diagram The HUB function control circuit as show in the diagram below consists of the following blocks 1 HUB repeater block 2 Down port control block 3 CPU interface block CIF HUB Function Control Circuit USB transceiver USB down port 1 USB Down port 2 transceiver transceiver Di D2 D2 Fig 88 HUB function control circuit block diagram 1 HUB repeater block 3 CPU interface block CIF The HUB repeater block consisting of the circuits listed below The CPU interface block performs the following processes processes the HUB repeater function sequence The HUB re Control of repeater down port states through registers peater is ready for operation after enabling the USB module Generates interrupt signal USBE 1 Controls internal bus interface Repeater circuit detects SOP EOP signal Frame time circuit synchronizes to SOF signal and manages frames in 1 ms Receiver circuit manages up port states Transmitter circuit controls up port outputs 2 Down port control block The d
363. ports for the output mode and open them at L or H e When opening them in the output mode the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset Thus the potential at these pins is undefined and the power source current may increase in the input mode With regard to an effects on the system thoroughly perform system evaluation on the user side e Since the direction register setup may be changed because of a program runaway or noise set direction registers by program periodically to increase the reliability of program 2 Termination remarks I O ports Do not open in the input mode Reason The power source current may increase depending on the first stage circuit e An effect due to noise may be easily produced as compared with proper termination shown on the above I O ports When setting for the input mode do not connect to Vcc or Vss directly Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between a port and Vcc or Vss I O ports When setting for the input mode do not connect multiple ports in a lump to Vcc or Vss through a resistor Reason If the direction register setup changes for the output mode because of a program runaway or noise a short circuit may occur between ports e At the termination of unused pins perform wiring
364. previous contents of the CPU register and SFR are not retained For more details concerning reset refer to 2 10 Reset Oscillation 16 cycles or Stop mode stabilizing time more of Xin Operating mode t Time to hold internal reset state approximately 10 5 to 18 5 cycles of Xin input o vy Execute Stop instruction Fig 2 13 3 Oscillation stabilizing time at restoration by reset input Rev 2 00 Oct15 2006 page 97 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 13 Standby function Restoration by interrupt request The occurrence of an interrupt request in the stop mode releases the stop mode As a result oscillation is resumed The interrupts available for restoration are INTo INT CNTRo Serial I O using an external clock eTimer X using an external event count Key input key on wake up USB function resume However when using any of these interrupt requests for restoration from the stop mode in order to enable the selected interrupt you must execute the STP instruction after setting the following conditions Necessary register setting Interrupt disable flag 0 interrupt enabled Timer 1 interrupt enable bit 0 interrupt disabled Interrupt request bit of interrupt source to be used for restoration 0 no interrupt request issued Interrupt enable bit of interrupt source to be used for restoration 1 interr
365. put as an L active signal b3b2b1 0 0 1 RxB_RDY RxBuf ready output 0 1 0 TxB_RDY TxBuf ready output 1 0 0 Mch_req Memory channel request output Others Do not set P43 ExA1 pin control bit 0 Port 1 A1 input used to read status Fig 114 Not used Write 0 when writing 0 is read when reading IndexOO low Structure of External I O configuration register Index 0016 External I O configuration register EXBCFGH address 003516 State remaining Bit symbol Bit name Function At reset H W S W DRQ_CTR 1 0 P40 ExDREQ RxD pin control bit Port Do not set ExDREQ function RxB_RDY RxBuf ready output ExDREQ function Mch_req Memory channel request output 0 DAK_CTR 1 0 P41 ExDACK TXD pin control bit Specifies P41 ExDACK TxD pin function Selects which mode requiring read or write signal or not requiring it for use of DMA acknowledge function b3b2 0 0 Port 0 1 Do not set 1 0 ExDACK function DMA acknowledge input Mode for read and write signals used together 1 1 ExDACK function DMA acknowledge input Mode for read and write signals not required P42 ExTC ScLk pin control bit 0 Port 1 ExTC terminal count input Not used Write 0 when writing 0 is read when reading Fig 115 IndexOO high Structur
366. r 0 Y Write the first transmission A received byte counter 1 data first byte in a block A received byte counter lt 0 A received byte counter gt 8 A gisters Pop registers which is Write a transmission data Write dummy data FF16 pushed to stack Heading Initial adjustment lt value counter Note 3 Pop registers Pop registers which is pushed to stack Notes 1 When using the Index X mode flag T 2 When using the Decimal mode flag D 3 In this example set the value which is equal to the heading adjustment time divided by the timer interrupt cycle as the initial value of the heading adjustment counter For example When the heading adjustment time is 8 ms and the timer interrupt cycle is 1 ms set 8 as the initial value Fig 2 4 28 Control procedure of slave unit Rev 2 00 Oct 15 2006 page 59 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O 4 Communication transmit receive using asynchronous serial I O UART Outline 2 byte data is transmitted and received using the asynchronous serial I O Port P24 is used for communication control Figure 2 4 29 shows a connection diagram and Figure 2 4 30 shows a timing chart Transmitting side Receiving side 38K2 group 38K2 group Fig 2 4 29 Connection diagram Communication using UART Specifications The Serial I O is used UART is selected e Transfer bit rate 9600 bps f X
367. r of cycles n is increased by 2 when T is 1 3 The number of cycles n is increased by 1 when T is 1 4 The number of cycles n is increased by 2 when branching has occurred 5 N V and Z flags are invalid in decimal operation mode Rev 2 00 Oct 15 2006 page 94 of 99 RENESAS Rev 2 00 Oct 15 2006 page 95 of 99 RENESAS REJ09B0338 0200 REJ09B0338 0200 38K2 Group Symbol Contents APPENDIX 3 6 Machine instructions Contents IMP IMM A BIT A BIT A R ZP BIT ZP BIT ZP R ZP X ZP Y ABS ABS X ABS Y IND ZP IND IND X IND Y REL SP Rev 2 00 Oct15 2006 page 96 of 107 REJ09B0338 0200 Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X modified arithmetic mode flag Overflow flag Negative flag M ADh ADL M 00 ADL Ai Mi OP n 7tENESA
368. r register LOW ccccccccesceeeeeeeeeeeeeeeeeeeeeseaeeeeeeeeessaeeeeeaeees 41 Fig 3 4 8 Structure of Frame number register High sss sssssesssssssssssrsssrssssrssrissrrnssrrnssrnsssrnssennns 41 Fig 3 4 9 Structure of USB interrupt source enable register s sseesseeeseseressriesrrresrrnssrnssss 41 Fig 3 4 10 Structure of USB interrupt source register essssesssissssesssieeriessrisssrnssinnssrnnsnnns 42 Fig 3 4 11 Structure of Endpoint index register cccccccecscceesseeeeeeeeeeeeeeeeeeeeessaeeeeeeeeetsaeeseeaeees 42 Fig 3 4 12 Structure of EPOO stage register eccecseeececeeeeeeeee cece eeeaeeseceeeeeaaeseeeeeetiaeeneneeess 43 Fig 3 4 13 Structure of EPO1 Set register ec eeesceeceeeeeeeeeeceeeeeeeaaeeeeeeeeseaaeeeeeeeeetaeeeteneees 43 Fig 3 4 14 Structure of EPO2 Set register cecceeceeeeceeeeeeeeeeeeeeeeeeseaeeseeeeeeeaeeseeeeeeeaeeeneetes 44 Fig 3 4 15 Structure of EPO3 Set register ccceceeeseeeceeeeeeeeeeeeeeeeeeeeaeeseeeeeesaeeseeeeeesiaeeeseeeens 44 Fig 3 4 16 Structure of EP10 stage register ccceeescceceseeeeeeee cece eeeeaeeeeeeeessaaeeeeeeeeesiaaeeteneees 45 Fig 3 4 17 Structure of EP11 Set register eececeeceseeceeeeeeeeeeeeeeeeeeeeaeeseeeeeesaaeeseeeeeetiaeeeneneeess 45 Fig 3 4 18 Structure of EPOO control register 1 eeccceeceeeeeeeeeeceeeeeeeeeeeeeeeaeeseeeeeeseaaeeneeeees 45 Fig 3 4 19 Structure of EPO1 control register 1 eccececeeeeeeeeeceee
369. r the built in flash memory is described below As for the control example refer to 2 14 7 2 Control example in the CPU rewrite mode Beginning procedure Apply 4 50 to 5 25 V to the CNVss Vrp pin at selecting boot ROM area Release reset Set bits 6 and 7 main clock division ratio selection bits of the CPU mode register After CPU rewrite mode control program is transferred to internal RAM jump to this control program on RAM The following operations are controlled by this control program Apply 4 50 to 5 25 to the CNVss Vep pin in single chip mode Set 1 to the CPU rewrite mode select bit bit 1 of address OFFEie Read the CPU rewrite mode entry flag bit 2 of address OFFEi to confirm that the CPU rewrite mode is set to 1 Flash memory operations are executed by using software commands Note The following procedures are also necessary e Control for data which is input from the external serial I O etc and to be programmed to the flash memory e Initial setting for ports etc e Writing to the watchdog timer Release procedure Execute the read command or set the flash memory reset bit bit 3 of address OFFE e Set the CPU rewrite mode select bit bit 0 of address OFFE e to 0 Rev 2 00 Oct 15 2006 page 106 of 112 RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory 2 14 7 Flash memory mode application examples The control pin processing exampl
370. r the program size with the 2nd and 3rd bytes 3 Transfer the check sum with the 4th byte The check sum is added to all data sent with the 5th byte onward 4 The program to execute is sent with the 5th byte onward When all data has been transmitted if the check sum matches the downloaded program is executed The size of the program will vary according to the internal RAM _Co ere rar low high sum data Program data SRDY BUSY Fig 160 Timing for download Rev 2 00 Oct 15 2006 page 119 of 130 2tENESAS REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION Version Information Output Command 1 Transfer the FB16 command code with the 1st byte This command outputs the version information of the control pro 2 The version information will be output from the 2nd byte on gram stored in the Boot ROM area Execute the version ward information output command as explained here following This data is composed of 8 ASCII code characters Fig 161 Timing for version information output Boot ROM Area Output Command 1 Transfer the FC16 command code with the 1st byte This command reads the control program stored in the Boot ROM 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and area in page 256 bytes unit Execute the Boot ROM area output 3rd bytes respectively command as explained here following 3 From the 4th byte onward data Do to D7 for the page 256 bytes sp
371. ranch address is specified by a relative address If Z is 1 the next instruction is executed Rev 2 00 Oct15 2006 page 86 of 99 ztENESAS Rev 2 00 Oct 15 2006 page 87 of 99 ztENESAS REJ09B0338 0200 REJ09B0338 0200 APPENDIX APPENDIX 38K2 Group 3 6 Machine instructions 38K2 Group 3 6 Machine instructions Addressing mode Addressing mode Processor status register Symbol Function Details A BIT A ZP 4 3 n JOP n JOP B D BPL Note 4 This instruction takes a branch to the ap pointed address if N is 0 The branch address is specified by a relative address If N is 1 the next instruction is executed PC lt PC offset This instruction branches to the appointed ad dress The branch address is specified by a relative address Be1 PC lt PC 2 M S PCH S lt S 1 M S PCL S lt S 1 M S PS lt S 1 Ic 1 PCL amp ADL PCH amp ADH When the BRK instruction is executed the CPU pushes the current PC contents onto the stack The BADRS designated in the interrupt vector table is stored into the PC BVC V 0 Note 4 This instruction takes a branch to the ap pointed address if V is 0 The branch address is specified by a relative address If V is 1 the next instruction is executed This instruction takes a branch to the ap pointed address whe
372. rces vector addresses and priority of 38K2 group interrupt Source Priorit Vector Addresses Note 1 Interrupt Request Sanne y High Low Generating Conditions Reset Note 2 1 FFFD16 FFFC16 At reset Non maskable USB bus reset 2 FFFB16 FFFA16 At detection of USB bus reset Valid when USB is selected signal 2 5 us interval SEO USB SOF 3 FFF916 FFF816 At detection of USB SOF signal Valid when USB is selected USB device 4 FFF716 FFF616 At detection of resume signal K Valid when USB is selected state or SEO or suspend signal 3 ms interval bus idle or at completion of transaction External bus 5 FFF516 FFF416 At completion of reception or Valid when external bus is selected transmission or at completion of DMA transmission INTo 6 FFF316 FFF216 At detection of either rising or External interrupt falling edge of INTo input active edge selectable Timer X 7 FFF116 FFFO16 At timer X underflow Timer 1 8 FFEF16 FFEE16 At timer 1 underflow STP release timer underflow Timer 2 9 FFED16 FFEC16 At timer 2 underflow INT1 10 FFEBi6 FFEA16 At detection of either rising or External interrupt falling edge of INT1 input active edge selectable USB HUB 11 FFE916 FFE816 At detection of status change of Valid when USB HUB is selected USB HUB down ports Serial I O 12 FFE716 FFE616 At completion of serial I O data Valid when serial I O is selected reception reception Serial I O 13 FFE516 FFE416 At completion o
373. rcuit operation disabled USB reference voltage circuit operation enabled USBDIFE USB difference input enable bit Upstream port difference input circuit operation disabled Upstream port difference input circuit operation enabled UCLKCON USB clock select bit External oscillating clock f XIN PLL circuit output clock fvco USBE USB module operation enable bit Olu a oja of of of oJ USB module reset USB module operation enabled Fig 31 Structure of USB control register b7 bO fofofofofofo USB function HUB enable register USBAE address 001116 State remaining Bit symbol Bit name Function At reset H W ADOE USB function enable bit 0 USB function address register invalidated 1 USB function address register validated 0 AD1E USB HUB enable bit 0 USB HUB address register invalidated 1 USB HUB address register validated b7 b2 Not used Write 0 when writing 0 is read when reading Fig 32 Structure of USB function HUB enable register Rev 2 00 Oct15 2006 page 33 of 130 REJ09B0338 0200 2RENESAS e remaining 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION USB function address register USBAO address 001216 Bit symbol Bit name Function At reset H W S W USBADDO 6 0 USB fu
374. re 0 Write 0 when writing 0 is read when reading Fig 41 Structure of EP00 control register 1 b7 bO ofofofolofo o EPOO control register 2 EPOOCON2 address 001B16 State remaining Bit symbol Bit name Function At reset H W S W BVALOO Buffer enable bit 0 NAK transmission SIE is disabled to read a buffer 1 Transmitting receiving data set state SIE is possible to read from write to a buffer At reception of SETUP token This bit is cleared to 0 by the hardware 0 Not used Write 0 when writing 0 is read when reading Fig 42 Structure of EP0O control register 2 Rev 2 00 Oct15 2006 page 38 of 130 REJ09B0338 0200 2tENESAS State remaining 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION b7 bo fofofofofofofo EPOO control register 3 EPOOCONS address 001C16 Bit symbol Bit name Function At reset H W S W CTENDE0O Control transfer completion enable bit 0 NAK transmission in the status stage 1 Control transfer completion enabled SIE transmits NULL ACK valid in PIDOO 012 At reception of SETUP token This bit is cleared to O by the hardware 0 Not used Write 0 when writing 0 is read when reading Fi
375. re but 1 cannot be set 0 0 CTEND10 USB HUB Endpoint 10 control transfer completion interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when control transfer is completed NULL ACK transmission in the status stage on USB HUB Endpoint 10 0 can be set by software but 1 cannot be set CTSTS10 USB HUB Endpoint 10 status stage transition interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when transition to status stage occurs in CTENDE10 0 control transfer completion disabled on USB HUB Endpoint 10 0 can be set by software but 1 cannot be set lt Transition to status stage occurrence factor gt At transfer of control write When receiving IN token in data stage OUT At transfer of control read When receiving OUT token in data stage IN At no data transfer Nothing occurs BSRDY10 USB HUB Endpoint 10 SETUP buffer ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the exclusive buffer for SETUP is ready state enabled to be read on USB HUB Endpoint 10 0 can be set by software but 1 cannot be set USB HUB Endpoint 10 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when control transfer error occurs
376. rection register P1D Port P2 P2 000516 000616 000716 Port P2 direction register P2D Port P3 P3 Port P3 direction register P3D 000816 Port P4 P4 000916 000A16 Port P4 direction register P4D Port P5 P5 000B16 Port P5 direction register P5D 000C16 000D16 000E16 Port P6 P6 Port P6 direction register P6D Reserved Note OOOF 16 Reserved Note 001016 001116 USB control register USBCON USB function Hub enable register USBAE 001216 USB function address register USBAO 001316 001416 001516 USB HUB address register USBA1 Frame number register Low FNUML Frame number register High FNUMH 001616 001716 001816 USB interrupt source enable register USBICON USB interrupt source register USBIREQ Endpoint index register USBINDEX 001916 Endpoint field register 1 EPXXREG1 001At16 001B16 Endpoint field register 2 EPXXREG2 Endpoint field register 3 EPXXREG3 001Ci6 Endpoint field register 4 EPXXREG4 001D16 001E16 001F16 Endpoint field register 5 EPXXREG5 Endpoint field register 6 EPXXREG6 Endpoint field register 7 EPXXREG7 OFEO16 Serial I O control register SIOCON OFE116 OFE216 UART control register UARTCON Baud rate generator BRG OFE3i6 Reserved Note OFE416 OFESi16 OFE616 Reserved Note Reserved Note Reserved Note OFE716 OFE816 OFE916 Res
377. register ceeccceeeceeceeeeeeeeeeeceeeeeesaaeeseeeeeesaaeeseeneeessaeeeseaeees 79 Fig 2 9 4 Watchdog timer connection and division ratio setting eeeeeeeeeeeeeteteeeeeteeees 80 Fig 2 9 5 Related registers setting ccccccccecceeseeeeeeeeeeeeeeceaeeeeeaeeeceaeeeesaaeeseeeeesaaaesseeeeesiaeeseaeees 81 Fig 2 9 6 Control PrOCCCUIG niseni a aaa aaa iaaa 81 Fig 2 10 1 Example of poweron reset circuit sssssssssesssrreeessrrnesrennneernnnnnntnnnnennnnnnnntennneennnnnnna 82 Fig 2 10 2 RAM backup SYStOM cc ececeeeeeeeeeeeeeeeeeeeeeeeeeeeaaaeeeeeeeaaeeeeseeaaaeeeeeeeaaeeeeseeenaeeeeeseaaes 82 Fig 2 11 1 Memory map of registers related to PLL cece ee eeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeaeees 84 Fig 2 11 2 Structure of USB Control register cceceececeeeeeeeseeeeeeeeeeeeaeeseeeeeesaaaeseeeeeeteaeeseneees 84 Fig 2 11 3 Structure of CPU mode register eccceceseececeeeeeeeeeeeceeeeeeeaeeeeeeeeesaaeeeeeeeeetsaeeeeeaeees 85 Fig 2 11 4 Structure of PLL Control register ceeecececeeeeeeeeeeeceeeeeaeeseeeeeeaaaeseceeeetiaeeneeeeens 85 Fig 2 11 5 Block diagram for frequency synthesizer circuit ccccceeeeeeeeeeeceeeeeeeeeteeeteeeees 86 Fig 2 11 6 Related registers setting when hardware reset ccsseceeeeeeeeteeeeeeeesetaeeteeeeees 87 Fig 2 11 7 Related registers setting when stop Mode ceeececceeeee cette eceeeeeeteaeeeeeeeeettaeeeteneees 88 Fig 2 11 8 Related registers setting w
378. registers shown in Figure 2 4 26 the master unit starts transmission or reception of 1 byte data by writing transmission data to the transmit buffer register To perform the communication in the timing shown in Figure 2 4 25 take the timing into account and write transmission data Additionally read out the reception data when the serial I O transmit interrupt request bit is set to 1 or before the next transmission data is written to the transmit buffer register Figure 2 4 27 shows a control procedure of the master unit using timer interrupts Interrupt processing routine executed every 488 us CLT Note 1 Note 1 When using the Index X mode flag T pe e aA tack Note 2 When using the Decimal mode flag D US Teg sien TO S Push the register used in the interrupt processing routine into the stack Within a block transfer term Generation of a certain block interval y using a timer or other functions Y b Read a reception data Count a block interval counter eCheck the block interval counter and determine to start a block transfer Complete to transfer a Start a block transfer N Write a transmission data Write the first transmission data first byte in a block Pop registers Pop registers which is pushed to stack Fig 2 4 27 Control procedure of master unit Rev 2 00 Oct 15 2006 page 58 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Control in the slave unit After
379. rerr reer re tr errr 16 Figs 3 1 7 THM Chart 4 secticeutvecctehlate E EEEE E 17 FIGs Si te Timing ohart 5 aeniea erai aaa aK ee RE e a 18 Fig S219 Timing chart 6 eiorcnrarosaiiiinte irita EEOAE AAEE EAA 19 Fig 3 2 1 Sequence of changing relevant register ss ssssssrisssirssissrrtrretsissrrnnsrnnssrnsssrnsnn 22 Fig 3 2 2 Sequence of check of interrupt request Dit sssssssssssssissseerressriessrrssrrnssrnnssrnsns 23 Fig 3 2 3 Sequence of setting serial I O control register again s ssssessseessessressriesrrrssrrnsns 25 Fig 3 2 4 Initialization of processor status register e sssssssesssisssressissrisssrissrrnssinnssrnsstnnnnt 29 Fig 3 2 5 Sequence of PLP instruction execution s sssssssssssrssssrrsrrsrsrssrrsssriessrrssrrnssrnnssrnsnnn 29 Fig 3 2 6 Stack memory contents after PHP instruction execution esssssssseseerrreren 29 Fig 3 2 7 Status flag at decimal calculations cccecececeeeeeeeeeeeeeeeeeaeeceeeeeesaaaeseeeeeeeaaeeteeees 30 Fig 3 3 1 Selection Of PACKAGES kiroressinsnsanan ner ra a a a aaa 32 Fig 3 3 2 Wiring for the RESET pin s ctcccssscsersedovig asceseredesdutcsoatetadiete alulnecaebiivecoatondouternsaees 32 Fig 3 3 3 Wiring for clock I O PINS oe cece ceccceeeeeeeceeeeeeeeeeecaeeeeeaeeeceaeeeesaaeeseeeeesaaaeseeeeeetiaaeeneaeees 33 Fig 3 3 4 Wiring for CNVss Dit susning eea aana E aa EA aS 33 Fig 3 3 5 Wiring for the Ver pin of the flash memory version ssssssesessseesrreerressrsss
380. ress 001016 Fig 139 Block diagram of PLL circuit Rev 2 00 Oct 15 2006 page 95 of 130 RENESAS REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION Division circuit 38K2 Group Fig 140 Structure of PLL control register Rev 2 00 Oct15 2006 page 96 of 130 REJ09B0338 0200 HARDWARE FUNCTIONAL DESCRIPTION PLL control register PLLCON address OF F816 Not used return 0 when read USB clock division ratio selection bits b4b3 0 0 Divided by 8 fsYN fusB 8 0 1 Divided by 6 fsYN fusB 6 1 0 Divided by 4 fSYN fusB 4 1 1 Not selected PLL operation mode selection bits b6b5 0 0 Not multiplied fvco fxIN 0 1 Double fvco fXIN X 2 1 0 Quadruple fvco fXIN X 4 1 1 Multiplied by 8 fvco fXIN X 8 PLL Enable Bit 0 Disabled 1 Enabled 7tENESAS 38K2 Group CLOCK GENERATING CIRCUIT An oscillation circuit can be formed by connecting a resonator be tween XIN and XOUT Use the circuit constants in accordance with the resonator manufacturer s recommended values No external resistor is needed between XIN and XOUT since a feed back resis tor exists on chip An external feed back resistor may be needed depending on conditions Frequency Control Either fSYN or f XIN can be selected as an internal system clock Furthermore the frequency of internal clock can be selected by the system clock division ratio selection bit 1 fSYN clock fsYN clock is generated by the
381. rising time CL 50 pF tir D D USB low speed output rising time CL 200 to 600 pF Ta 0 to 85 C CL 250 to 600 pF Ta 20 to 85 C CL 200 to 600 pF Ta 20 to 85 C tif D D USB low speed output falling time CL 200 to 600 pF Ta 0 to 85 C CL 250 to 600 pF Ta 20 to 85 C CL 200 to 600 pF Ta 20 to 85 C tfrfm D D USB full speed ports rising falling ratio tfr D D tff D D tirfm D D USB low speed ports rising falling ratio tir D D tff D D Vers D D USB output signal cross over voltage TrON Measured output pin RL 1 5 kQ RL 27Q CL Measured output pin OVW RL 15 kQ RL 15 kQ USB port output USB port output Fig 3 1 2 USB output switching characteristics measurement cir Fig 3 1 3 USB output switching characteristics measurement cir cuit 1 for DO D1 D2 low speed D1 D2 full speed cuit 2 for D0 D1 D2 full speed D1 D2 low speed Rev 2 00 Oct 15 2006 page 13 of 99 2tENESAS REJ09B0338 0200 38K2 Group INTo INT4 Serial I O RxD at receive TxD at transmit Fig 3 1 4 Timing chart 1 Rev 2 00 Oct15 2006 page 14 of 99 REJ09B0338 0200 APPENDIX 3 1 Electrical characteristics twH INT twL INT BV oor 0 2Vcc tw RESET tc ScLk tr twL SCLk twH SCLk 0 8VccE tsu RxXD ScLk th ScLk RxD SOHN RRRRRRE EE PSRRRRRRRORRR RR 0 8VccE Q XXXXXX
382. riting 0 a low speed EOP is output and then a transition to being not output occurs DSRMOD1 Downs read m ream port 1 bus state ode control bit Mode where a downstream port 1 bus state is read using RD signal Mode where a downstream port 1 bus state is read using EOF2 signal internal signal DSLSPD1 Downs ream port 1 USB transfer Full speed mode 12MHz Low speed mode 1 5 MHz Fig 3 4 61 Structure of DP1 control register DP2 control register DP2CON address 002C16 State remaining Bit symbol Bit name Function At reset H W S W DSCONN2 Downs ream port 2 connect bit Disconnect PTCON2 interrupt enabled Connect PTDIS2 interrupt enabled 0 DSPTEN2 Downs ream port 2 enable bit Downstream port 2 disabled Downstream port 2 enabled This bit is cleared when an interrupt of PTDIS2 or PTERR2 is generated DSSUSP2 Downs ream port 2 suspend bit No port suspended Port suspended This bit is cleared when an interrupt of PTDIS2 or PTRSM2 is generated DSDETE2 Downs ream port 2 connect state detection enable bit Connect state detection disabled PTCON2 and PTDIS2 interrupts disabled Connect state detection enabled This bit is cleared when an interrupt of PTCON2 PTDIS2 or PTERR2 is generated DSRSTO2 Downs ream p
383. rogram status is set to O when it is cleared If 1 is written for any of the SR5 and SR4 bits the program erase all blocks and block erase commands are not accepted Before executing these commands execute the clear status regis ter command 5016 and clear the status register Definition Ready Busy Reserved Erase status Terminated in error Terminated normally Program status Terminated in error Terminated normally Reserved Reserved Reserved Reserved Rev 2 00 Oct15 2006 page 107 of 130 REJ09B0338 0200 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION Full Status Check By performing full status check it is possible to know the execu tion results of erase and program operations Figure 151 shows a full status check flowchart and the action to be taken when each error occurs Read status register Command Execute the clear status register command 5016 T to clear the status register Try performing the operation one more time after confirming that the command is entered correctly Erase error should an erase error occur the block in error cannot be used Program error Should a program error occur the block in error cannot be used End block erase program Note When one of SR5 and SR4 is set to 1 none of the program erase all blocks and block erase commands is accepted Execute the clear status register command 5
384. rol circuit compares an analog input volt age with the comparison voltage and then stores the result in the AD conversion registers 1 2 When an A D conversion is com pleted the control circuit sets the AD conversion completion bit and the AD interrupt request bit to 1 Note that because the comparator consists of a capacitor cou pling set f system clock to 500 kHz or more during an A D conversion AD control register ADCON address 003616 Analog input pin selection bits 0 0 0 P10 DQo0 ANo 1 P11 DQ1 AN1 P12 DQ2 AN2 P13 DQ3 AN3 P14 DQ4 AN4 P15 DQs ANs5 P16 DQ6 ANe 1 1 P17 DQ7 AN7 AD conversion completion bit 0 Conversion in progress 1 Conversion completed Not used indefinite at read These bits are write disabled bits Fig 132 Structure of AD control register 10 bit reading Read address 003816 before 003716 b7 bO 0 b9 b8 b7 bO b7 b6 b5 b4 b3 b2 b1 b0 Note Bits 2 to 7 of address 003816 become 0 at reading 8 bit reading Read only address 003716 address 003816 address 003716 b7 0 oofba o7 bs 5 aoa address 003716 Fig 133 10 bit 8 bit reading 2tENESAS 38K2 Group Data bus HARDWARE FUNCTIONAL DESCRIPTION A D control register bO address 003616 P10 DQo ANo O P11 DQ1 AN1 O P12 DQ2 AN2 O P13 DQ3 AN3 O P14 DQ4 AN4 O gt P15 DQs ANs O gt
385. rom the host 1 IN Data is transmitted to the host TYP0O1 1 0 Transfer type bite b7b6 0 0 Transfer disabled 0 1 Bulk transfer 1 0 Interrupt transfer 1 1 lsochronous transfer Fig 47 Structure of EP01 set register b7 bo fofofofofofo EP01 control register 1 EPO1CON1 address 001A16 e remaining Bit symbol Bit name Function At reset H W S W PIDO1 1 0 Response PID bit b1 bO 0 0 NAK 0 1 Automatic response ACK NAK DATAO DATA1 1 X STALL At occurrence of over max packet size B1 is set to 1 by the hardware 0 Write 0 when writing 0 is read when reading Fig 48 Structure of EP01 control register 1 Rev 2 00 Oct15 2006 page 41 of 13 REJ09B0338 0200 0 7tENESAS State remaining 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION b7 bo fofofofofofofo EP01 control register 2 EP01CON2 address 001B16 Bit symbol Bit name Function At reset H W S W BOVALO1 Buffer 0 enable bit When the selected endpoint is IN writing 1 to this bit makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write 0 Write 0 when writing 0 is read whe
386. rors occurs e Overrun error e Parity error e Framing error Serial I O control register Address OFEO16 b7 bO siooon 1 sits af Serial I O synchronous clock selection bit External clock Srov output enable bit Srov output enabled Transmit enable bit Transmit enabled Set this bit to 1 using Srov output Receive enable bit Receive enabled Serial I O mode selection bit Clock synchronous serial I O Serial I O enable bit Serial I O enabled Fig 2 4 16 Registers setting related to receiving side Rev 2 00 Oct 15 2006 page 50 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Figure 2 4 17 shows a control procedure of the transmitting side and Figure 2 4 18 shows a control procedure of the receiving side RESET x This bit is not used here Set it to O or 1 arbitrarily Initialization Address OFE016 lt 1101xx002 Address OFE216 lt 12 1 INTEDGE Address OFF316 bit2 lt 0 IREQ2 Address 3D16 bit0 Detection of INT1 falling edge IREQ2 Address 3D16 bit0 lt 0 TB RB Address 2616 lt The first byte of a Transmission data write transmission data Transmit buffer empty flag is set to 0 by this writing SIOSTS Address 2716 bit0 e Judgment of transferring from Transmit buffer register to Transmit shift register 1 Transmit buffer empty flag TB RB Address 2616 lt The second byte
387. rrupt request Concurrently with the push operation the jump destination address the beginning address of the interrupt processing routine of the occurring interrupt stored in the vector address is set in the program counter then the interrupt processing routine is executed After the interrupt processing routine is started the corresponding interrupt request bit is automatically cleared to 0 The interrupt disable flag is set to 1 so that multiple interrupts are disabled Accordingly for executing the interrupt processing routine it is necessary to set the jump destination address in the vector area corresponding to each interrupt Stack area Program counter PCL Program counter low order PCH Program counter high order Interrupt disable flag 0 S Stack pointer S S Interrupt request is accepted Program counter Stack area PCL Vector address Interrupt disable flag 1 PCH from Interrupt vector area s Stack pointer Processor status register S S 3 Program counter low order Program counter high order Fig 2 2 8 Changes of stack pointer and program counter upon acceptance of interrupt request Rev 2 00 Oct 15 2006 page 13 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 2 Interrupt 2 Timing after acceptance of interrupt request The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently b
388. rsion except that the flash memory is built in and some of the SFR area differ from that of the mask ROM version refer to 2 14 2 Memory map In the flash memory version the built in flash memory can be programmed or erased by using the following three modes e CPU rewrite mode e Parallel I O mode e Standard serial I O mode 2 14 2 Memory map 38K2 group flash memory version has 32 Kbytes of built in flash memory Figure 2 14 1 shows the memory map of the flash memory version 000016 SFR area 004016 Internal RAM area 2 Kbyte 083F 16 User ROM area 084016 Not used 800016 OFE016 SFR area OFFF16 100016 Not used 32 Kbytes 800016 Reserved ROM area 808016 Built in flash memory area 32 Kbytes FFFF16 FFFFIG Boot ROM area F00016 4 Kbytes FFFF16 Note Access to boot ROM area Pararell I O mode Read Write avilable CPU rewrite mode Read only available Standard serial mode Read only available Fig 2 14 1 Memory map of flash memory version for 38K2 Group Rev 2 00 Oct 15 2006 page 103 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory 2 14 3 Related registers Address Fig 2 14 2 Memory map of registers related to flash memory Flash memory control register b7 b6 b5 b4 b3 b2 b1 b0 Flash memory control register FMCR address 0OFFE16 Note 1 Poem flag 0 Busy a written or O x er
389. rtain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electron
390. rupt request issued This bit is set to 1 when detecting a bus disconnect state 2 5 us or more of SEO on a downstream port 2 in DSCONN2 1 0 can be set by software but 1 cannot be set 0 PTCON2 Downstream port 2 connect detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus connect state 2 5 us or more of J or K state on a downstream port 2 in DSCONN2 0 0 can be set by software but 1 cannot be set PTERR2 Downstream port 2 port error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when an error occurs on a downstream port 2 0 can be set by software but 1 cannot be set PTRSM2 Downstream port 2 resume interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a resume signal on a downstream port 2 in the condition of HUB suspended or port suspended state 0 can be set by software but 1 cannot be set PTCHG2 Downstream port 2 bus change detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus change of a downstream port 2 in the condition of HUB suspended state It is also 1 in the internal clock halted 0 can be set by
391. s Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input p
392. s not used here Set it to 0 or 1 arbitrarily address 2316 lt xxxx10112 Timer X operating mode Pulse width measurement mode address 2416 256 1 Measure H level of pulses input from CNTRo pin address 2516 256 1 Set division ratio so that Timer X interrupt will occur at address 3C16 bits 0 175 ms intervals address 3E16 bitS 1 Timer X interrupt request bit cleared address fe bit4 0 Timer X interrupt enabled address 3F16 bit4 lt 1 CNTRo interrupt request bit cleared CNTRo interrupt enabled address 2316 bit3 lt 0 Timer X count start Interrupts enabled y Tha N Timer X interrupt process routine Process errors Error occurs CNTRo interrupt process routine CLT Note 1 Note 1 When using Index X mode flag T CLD Note 2 Note 2 When using Decimal mode flag D Push registers to stack Push registers used in interrupt process routine A lt PREX Read the count value and store it to RAM Low order 8 bit result of lt Inverted A pulse width measurement A lt TX High order 8 bit result of lt Inverted A pulse width measurement PREX address 2416 256 1 Division ratio set so that Timer X interrupt will occur at TX address 2516 256 1 175 ms intervals Pop registers Pop registers pushed to stack Fig 2 3 22 Control procedure Rev 2 00 Oct 15 2006 page 38 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2
393. s register SRD ecccccccceeeeseceeeeeeeeeeeeecaeeeeeeaeeeeaeeeeeaaeseseeeseeaeeeeeeeeessaeeneeaeees 122 Table 15 Status register 1 SRD1 e cece cece ceceeeeeeeeeeeeeeeeeeeaeeeceeeeeeaaeeeeeeeeesaeeeseeeeessaeeeseneees 123 Table 16 Relative formula for a reference voltage VREF of A D converter and Vref 129 Table 17 Change of AD conversion register during A D conversion 0 cceeeeeeeteeeees 129 CHAPTER 2 APPLICATION Table 2 1 1 Handling of unused PINS 20 cet eeeeeceeeceeteeeeeeceaaeeeeaeeeceaaeseeaaeeseeaeeseaaeeseceeetaaeeneaes 5 Table 2 2 1 Interrupt sources vector addresses and priority of 38K2 group 11 Table 2 2 2 List of interrupt bits according to interrupt SOUICE eee eee eeneeeeeeteteeeeeeettteeeeees 16 Table 2 3 1 CNTRo active edge Selection bit FUNCTION 0 0 cccecsseeeeeeesneeeeeesesteeeeessnteeeeness 25 Table 2 4 1 Setting examples of Baud rate generator values and transfer bit rate values 61 Table 2 11 1 PLL operation mode selection bits setting example cccceeeeeeeteeeeetteeteees 86 Table 2 11 2 USB clock division ratio selection bits setting example 0 ccceeeeeesteeeeees 87 Table 2 12 1 Example of internal clock f f generation using main clock f Xin esses 92 Table 2 12 2 Example of internal clock f f generation using fSYN eeeeeeeeeeeteeeeeeeeeeeee 93 Table 2 13 1 State in Stop MOE eeecccececeececeeeeeeeeeaeeeeeeeeeeeaaeeeeeeeeseaaeeeeeeeeseaeesseaeese
394. se to the built in flash memory can be performed by a flash programmer MFW 1 The memory area of program erase is from OF0001s to OFFFFis boot ROM area or from 0800016 to OFFFFis user ROM area Be especially careful when erasing if the memory area is not set correctly the products will be damaged eternally Table 2 14 1 shows the setting of programmers when programming in the parallel I O mode MFW 1 provided by Sunny Giken Inc http Awww sunnygiken co jp english index html Table 2 14 1 Setting of programmers when parallel programming Products Parallel adapter Boot ROM area User ROM area Saan AT SHEE wee OF00016 to OFFFF 0800016 to OFFFF M38K29F8FP LEP MFW S19 ee a e 6 2 14 5 Standard serial I O mode Table 2 14 2 shows a pin connection example 4 wires between the programmer MFW 1 and the microcomputer when programming in the standard serial I O mode MFW 1 provided by Sunny Giken Inc http Awww sunnygiken co jp english index html Table 2 14 2 Connection example to flash programmer when serial programming 4 wires MFW 1 38K2 Group flash memory version Function Signal name MFW 1 side connector Pin name Pin number Line number Transfer clock input CLK 3 P42 ExTC Sc1ik 53 Serial data input RxD 10 P40 ExDREQ RxD 51 Serial data output TxD 4 P4 ExDACK TxD 52 Transmit Receive enable output BUSY 2 P43 ExA1 Sroy 54 Vee input CNVss 1 CNVss 7 Reset input RESET 8 RESET 8 Target board power source
395. set each bit simultaneously Fig 109 Structure of EXB interrupt source enable register EXB interrupt source register EXBIREQ address 003116 Note 1 Bit symbol Bit name Function At reset H W S W Receive buffer full bit 0 Receive buffer empty 1 Receive buffer full 0 0 Note 3 Transmit buffer empty bit 0 Transmit buffer full 1 Transmit buffer empty 0 Note 4 Memory channel status bits b3b2 00 O41 Memory channel operation stopped Memory channel being operating No external access Memory channel being operating External accessing Memory channel operation end Memory channel operation end interrupt generated 0 Write 0 when writing 0 is read when reading regis 2 The memory channel status bits indicate the status of memory channel In MC_ENB 0 these bits are a State remaining Notes 1 When the the ExA1 pin control bit of external I O configuration register is 1 the external MCU bus can read this er contents by setting the ExA1 pin to H ways 002 When the memory channel operation ends these bits are set to 112 and the memory channel operation end interrupt is generated These bits can be read out during operation so that it will show that whether the external MCU bus is accessing or not 3 This bit is cleared to O when reading the tra
396. setting serial I O control register again Rev 2 00 Oct 15 2006 page 25 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 5 6 7 Data transmission control with referring to transmit shift register completion flag Serial I O The transmit shift register completion flag changes from 1 to 0 with a delay of 0 5 to 1 5 shift clocks When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register note the delay Transmission control when external clock is selected Serial I O When an external clock is used as the synchronous clock for data transmission set the transmit enable bit to 1 at H of the SCLK input level Also write the transmit data to the transmit buffer register serial I O shift register at H of the SCLK input level Transmit interrupt request when transmit enable bit is set Serial I O When the transmit interrupt is used set the transmit interrupt enable bit to transmit enabled as shown in the following sequence Set the interrupt enable bit to 0 disabled with CLB instruction Prepare serial I O for transmission reception Set the interrupt request bit to 0 with CLB instruction after 1 or more instruction has been executed Set the interrupt enable bit to 1 enabled Reason When the transmission enable bit is set to 1 the transmit buffer empty flag and transmit
397. sfer DIR02 Transfer direction bit 0 OUT Data is received from the host 1 IN Data is transmitted to the host TYP02 1 0 Transfer type bite b7b6 0 0 Transfer disabled 0 1 Bulk transfer 1 0 Interrupt transfer 1 1 lsochronous transfer Fig 3 4 14 Structure of EP02 set register EPO3 set register EPO3CFG address 001916 e remaining Bit symbol Bit name Function At reset H W S W BSIZ03 1 0 Double buffer beginning address set bit In double buffer mode set the beginning address of buffer 1 area using a relative value for the beginning address of buffer 0 b1b0 00 8 bytes 01 16 bytes 10 64 bytes 1 1 128 bytes 0 DBLBO3 Buffer mode select bit Single buffer mode Double buffer mode SQCLO3 Sequence toggle bit clear bit Toggle bit clear disabled Writing 1 clears the toggle bit and DATAO is used as the next data PID 0 is always read when reading 0 1x 0 1i ITMD03 Interrupt toggle mode select bit 0 Normal mode 1 Continuous toggle mode valid at Interrupt IN transfer DIRO3 Transfer direction bit 0 OUT Data is received from the host 1 IN Data is transmitted to the host TYP03 1 0 Transfer type bit b7b6 0 0 Transfer disabled 0 1 Bulk transfer 1 0 Interrupt transfer 1 1 lsochr
398. shift register completion flag are set to 1 The interrupt request is generated and the transmission interrupt bit is set regardless of which of the two timings listed below is selected as the timing for the transmission interrupt to be generated e Transmit buffer empty flag is set to 1 e Transmit shift register completion flag is set to 1 3 2 6 Notes on USB function 1 2 3 Port pins D0 DO D1 D1 D2 D2 treatment The USB specification requires a driver impedance 28 to 44 Q In order to meet the USB specification impedance requirements connect a resistor 27 W recommended in series to the USB port pins In addition in order to reduce the ringing and control the falling rising timing and a crossover point connect a capacitor between the USB port pins and the Vss pin if necessary The values and structure of those peripheral elements depend on the impedance characteristics and the layout of the printed circuit board Accordingly evaluate your system and observe waveforms before actual use and decide use of elements and the values of resistors and capacitors Make sure the USB D D lines do not cross any other wires Keep a large GND area to protect the USB lines Also make sure you use a USB specification compliant connecter for the connection USBVrer pin treatment Noise Elimination Connect a capacitor between the USBVrer pin and the Vss pin The capacitor should have a 2 2 uF capacitor el
399. sing the clock synchronous serial I O The Savy signal is used for communication control Figure 2 4 13 shows a connection diagram and Figure 2 4 14 shows a timing chart Figure 2 4 15 shows a registers setting related to the transmitting side and Figure 2 4 16 shows registers setting related to the receiving side Transmitting side Receiving side P52 INT1 Scik TxD RxD 38K2 group 38K2 group Fig 2 4 13 Connection diagram Specifications The Serial I O is used clock synchronous serial I O is selected e Synchronous clock frequency 125 kHz f Xin 6 MHz is divided by 48 e The Sarpy receivable signal is used e The receiving side outputs the Srov signal at intervals of 2 ms generated by timer and 2 byte data is transferred from the transmitting side to the receiving side Sroy ed _ TALL gee Scik TxD l i XD DK lt 4 2 ms gt Fig 2 4 14 Timing chart Rev 2 00 Oct 15 2006 page 48 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Transmitting side Serial I O status register Address 2716 b7 bO SIOSTS Transmit buffer empty flag e Confirm that the data has been transferred from Transmit buffer register to Transmit shift register e When this flag is 1 it is possible to write the next transmission data in to Transmit buffer register Transmit shift register shift
400. sing the fastest frequency possible of f X as an input clock reference for the PLL When enabling PLL operation from PLL disabled status disabled when reset set the USB clock select bit of USBCON to 0 f Xin to operate with the main clock f Xi When supplying fvco to the USB block after setting PLL operation enable bit to 1 PLL enabled wait for the oscillation stable time 1 ms or less of PLL to avoid any instability caused by the clock then set USB clock select bit to 1 USB clock When selecting fsyn as an internal system clock fuss must be 48 MHz When selecting fsyn as an internal system clock change the system clock selection bit to main clock f Xin before executing STP instruction It is because the following are needed for the low power consumption fuss must be stopped by disabling PLL operation in Stop mode The taimer 1 for waiting oscillation stabilization when returning from Stop mode will require the input count source Rev 2 00 Oct 15 2006 page 27 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 3 2 11 Notes on stand by function 1 2 Notes on using stop mode Register setting Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the stop mode set them again respectively When the oscillation stabilizing time set after STP instruction released bit is O Clock restoration When the main clock side is set
401. ss 2516 b7 bO 255 Set 255 just before counting pulses After a certain time has passed the number of input pulses is decreased from this value Interrupt control register 1 address 3E16 ay eT gt Timer X interrupt Disabled gt Timer 1 interrupt Enabled Interrupt request register 1 address 3C16 b7 bO gt Judge Timer X interrupt request bit 1 of this bit when reading the count value indicates the 256 or more pulses input in the condition of Timer X 255 Fig 2 3 18 Related registers setting Rev 2 00 Oct15 2006 page 34 of 112 2RENESAS REJ09B0338 0200 2 3 Timer 38K2 Group Initialization SEI address 2316 lt xxxx11102 address 2016 3 1 address 2116 lt 250 1 address 2416 1 1 address 2516 lt 256 1 address 3E16 bit6 lt 1 address 2316 bit3 0 Timer 1 interrupt process routine CLT Note 1 CLD Note 2 Push registers to stack IREQ1 address 3C16 bit5 A lt TX address 2516 214 lt A lt 228 gt Out of range Fpulse APPLICATION 2 3 Timer x This bit is not used here Set it to 0 or 1 arbitrary All interrupts disabled Timer X operating mode Event counter mode Count a falling edge of pulses input from CNTRo pin Division ratio set so that Timer 1 interrupt will occur at 2 ms intervals Timer 1 interrupt enabled Timer X count start Interrupts enabled Note 1 When using
402. sss 34 Fig 3 3 6 Bypass capacitor across the Vss line and the Voc line ssssscsesssessreresesssss 34 Fig 3 3 7 Analog signal line and a resistor and a capacitor sssseessesrirssesrrrssererrssnreerss 35 Fig 3 3 8 Wiring for a large current signal line sssseeesssseesssrnesessnneeennnnnssrennneennnnnnnenenneennnnnnne 36 Fig 3 3 9 Wiring of RESET pin cdecssescicccoseenitasemesucacastieald odeasesuitinladisradtusanssaid nannescidosseccaisonucdes 36 Fig 3 3 10 Vss pattern on the underside of an oscillator sssssesssseessseeesisssessrresrrssrrnssrnssns 37 Figs 3 3 11 Setup for 1 0 POrts x siciesisccisect saree Aviceeeeens detddantes aa a e a A a a 37 Fig 3 3 12 Watchdog timer by software oc eeeececceteee cence cent eeeeeeeeeeeeeeeeaaeeseeeesseaeeseeneeessaeeeneneees 38 Fig 3 4 1 Structure of Port Pl istvccsmiii caine vic ee eel nectniedeniienien 39 Fig 3 4 2 Structure of Port Pi direction register cccceceeeeeeeeeeeeeeeeeeeeeeeeeeeaeeseeeeeesiaeeneeeees 39 Fig 3 4 3 Structure of USB Control reQisSte ro eeceeceeeeeeee cesses eeeeeeeeeeaeeseeeeessaaeeeeeeeeessaeeeseaeees 40 Fig 3 4 4 Structure of USB function HUB enable register ccccceseeeeeeeeteeeeeeeeeeeeeeeeeeeees 40 Fig 3 4 5 Structure of USB function address reQister eee eee eeeeeeeeeeeseeeneetsaeeeneeeaaes 40 Fig 3 4 6 Structure of USB HUB address register ccccceseeeeeeee sees eeeeeeeeeeaeeeeeeeeeteaeeeeeneees 41 Fig 3 4 7 Structure of Frame numbe
403. st issued O 0_ 2 x x ae CNTRo interrupt 0 No interrupt request issued request bit 1 Interrupt request issued Key on wake up 0 No interrupt request issued interrupt request bit 1 Interrupt request issued A D conversion 0 No interrupt request issued interrupt request bit 1 Interrupt request issued Nothing is arranged for this bits This is a write disabled bit 7 When this bit is read out the contents are 0 0 can be set by software but 1 cannot be set 3 Serial I O transmit 0 No interrupt request issued interrupt request bit 1 Interrupt request issued sm ee O_ x x x x x Fig 2 4 8 Structure of Interrupt request register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 bi bO lol dd Interrupt control register 2 ICON2 Address 3F 16 IB Name Function Atresa Riw l INT1 interrupt 0 Interrupt disabled l enable bit 1 Interrupt enabled i J1 USB HUB interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled i 2 Serial I O receive 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 3 Serial I O transmit 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled 4 CNTRo interrupt 0 Interrupt disabled enable bit 1 Interrupt enabled 5 Key on wake up 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled A D conversion _ 0 Interrupt disabled interrupt enable bit 1 Interrupt enabled Fix this bit t
404. ster 2 b7 bO fofofofofofofo EPOO control register 3 EPOOCONS address 001C16 Bit symbol Bit name Function At reset H W S W CTENDEOO Control transfer completion 0 NAK transmission in the status stage 0 enable bit 1 Control transfer completion enabled SIE transmits NULL ACK valid in PIDOO 012 At reception of SETUP token This bit is cleared to 0 by the hardware Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 30 Structure of EP00 control register 3 Rev 2 00 Oct 15 2006 page 49 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers b7 bO ofofofolofo o EP01 control register 3 EPO1CONS address 001C16 Bit symbol Bit name Function At reset H W S W B1VAL01 Buffer 1 enable bit When the selected endpoint is IN writing 1 to this bit O makes the transmitting data a set state SIE is possible to read When the selected endpoint is OUT writing 1 to this bit makes data reception possible SIE is possible to write In double buffer mode this bit is valid Write 0 when writing 0 is read when reading e remaining Fig 3 4 31 Structure of EP01 control register 3 b7 bo fofofofofofo o EP02 control register 3 EPO2CONS3 address 001C16 Bit symbol Bit name Functio
405. ster cannot be read out The data cannot be written to the receive buffer reaister Fig 3 4 54 Structure of Transmit Receive buffer register Serial I O status register b7 b6 b5 b4 b3 b2 bi bO Serial I O status register SIOSTS Address 2716 T _fuse oT buffer empty flag A Buffer full Buffer empty n buffer full flag RBF 0 Buffer empty 1 Buffer full 2 Transmit shift register shift 3 Transmit shift in progress x I flag TSC Transmit shift completed Sa ENGE ONEIN error Parity error flag PE A No error Parity error Framing error flag FE be No error 0 fox Framing error Summing error flag SE OE U PE U FE 0 Eg OE U PE U FE 1 7 Nothing is allocated for this bit This is a write disabled bit Eg When this bit is read out the contents are 1 Fig 3 4 55 Structure of Serial I O status register Rev 2 00 Oct15 2006 page 60 of 99 2tENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers b7 bo fofofofofo HUB interrupt source enable register HUBICON address 002816 At reset Bit symbol Bit name Function HW S W RW DP1E HUB downstream port 1 interrupt O Interrupt disabled 0 JOO enable bit 1 Interrupt enabled DP2E HUB downstream port 2 interrupt 0 Interrupt disabled O iO enable bit 1 Interrupt enabled f b6 b2 Not used Write 0 when writing 0 0 i i L 0 is r
406. stop mode by INTo interrupt rising edge selected Stop mode Oscillation stabilizing time lt o XIN oS INTo pin o la FFie 512 counts Prescaler 12 counter Timer 1 counter INTo interrupt request bit Peripheral device operating Stopped Operating CPU Operating Stopped Operating A A A Execute STP INTo interrupt signal 512 counts down by instruction input INTo interrupt prescaler 12 request occurs Start supplying internal Oscillation start clock p to CPU Prescaler 12 count start Accept INTo interrupt request Note f Xin 16 is input as the prescaler 12 count source Fig 2 13 4 Execution sequence example at restoration by occurrence of INTo interrupt request 3 Notes on using stop mode Register setting Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the stop mode set them again respectively When the oscillation stabilizing time set after STP instruction released bit is O Clock restoration When the main clock side is set as a system clock the oscillation stabilizing time for approximately 8 000 cycles of the Xin input is reserved at restoration from the stop mode Rev 2 00 Oct 15 2006 page 99 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 13 Standby function 2 13 4 Wait mode The wait mode is set by execution of the WIT instruction In the wait mode oscillation continues but the internal clock
407. t Function H W S W BORDY01 USB function Endpoint 1 buffer 0 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when the buffer O is ready state enabled to be read written on USB function Endpoint 1 0 can be set by software but 1 cannot be set 0 0 B1RDY01 USB function Endpoint 1 buffer 1 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued In single buffer mode this bit is invalid This bit is set to 1 when the buffer 1 is ready state enabled to be read written on USB function Endpoint 1 in double buffer mode 0 can be set by software but 1 cannot be set USB function Endpoint 1 error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when STALL response occurs on USB function Endpoint 1 0 can be set by software but 1 cannot be set Not used Write 0 when writing 0 is read when reading Fig 3 4 36 Structure of EP01 interrupt source register b7 bO fofofofofol EP02 interrupt source register EPO2REQ address 001D16 Bit symbol Bit name Function At reset H W S W BORDY02 USB function Endpoint 2 buffer 0 ready interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit
408. t L or H level or keep open P60 to P63 Input port P6 Rev 2 00 Oct15 2006 page 113 of 130 REJ09B0338 0200 Input L or H level or keep open 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION aq P51 CNTRo 37 P52 INT1 35 P50 INTo 38 4 P53 P06 P07 P40 ExDREQ RxD P41 ExDACK TxD P42 ExTC ScLkK P43 ExA1 SRDY P30 P31 P32 P33 ExINT P34 ExCS P35 EXWR P36 ExRD P37 ExA0 P10 DQo ANo P11 DQ1 AN1 M38K29F8LFP HP USBVREF DVcc PVcc PVss P63 LEDs3 P62 LED2 P61 LED1 O EBREBEERBEREREBE CNVss gt RESET Vcc CNVss2 gt 2 DQ2 AN2 gt 3 DQ3 AN3 L2 4 DQ4 AN4 5 DQ5 ANs gt 6 DQe6 ANs 1 7 DQ7 AN7 lt gt VccE P P P P P P Vss Mode setup method Signal Value Connect to oscillator circuit CNVss 4 5 to 5 25 V SCLK Vcc Note 2 RESET Vss Vcc CE Vcc Note 2 Notes 1 Connect to Vcc in the case of Vcc 4 5 V to 5 25 V Connect to VPP 4 5 V to 5 25 V in the case of Vcc 3 0 V to 4 5 V 2 Supply Vcc at releasimg Reset Package outline PLQPO0064GA A PLQPO064KB A Fig 154 Pin connection diagram in standard serial I O mode Rev 2 00 Oct 15 2006 page 114 of 130 2RENESAS REJ09B0338 0200 3
409. t Notes 1 Operating in single chip mode Clock input from XIN pin XOUT oscillator stopped fUSB 48 MHz All USB difference input circuits enabled Leaving I O pins open Operating functions PLL circuit CPU Timers 2 Operating in single chip mode with Wait mode Clock input from XIN pin XOUT oscillator stopped fUSB 48 MHz All USB difference input circuits enabled Leaving I O pins open Operating functions PLL circuit Timers USB receiving Disabled functions CPU 3 Operating in single chip mode with Stop mode Oscillation stopped All USB difference input circuits disabled Leaving I O pins open Rev 2 00 Oct 15 2006 page 6 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 1 Electrical characteristics L Ver 3 1 4 A D converter characteristics L Ver Table 3 1 6 A D Converter characteristics VCC 3 00 to 5 25 V Vss 0 V Ta 20 to 85 C unless otherwise noted Parameter Test conditions Resolution Linearity error Ta 25 C Differential nonlinear error Ta 25 C Zero transition voltage Voc VREF 5 12 V Full scale transition voltage Vcc VREF 5 12 V Conversion time RLADDER Ladder resistor IVREF Reference power source input current A D converter operating VREF 5 0 V A D converter not operating VREF 5 0 V I AD A D port input current Rev 2 00 Oct 15 2006 page 7 of 99 2tENESAS REJ09B0338 0200 38K2 Group 3 1 5 Timing Requirements
410. t Tl can be generated to occur when either the TI source selection bit TIC of the serial 1 01 control register The receive interrupt RI is set when the RBF flag becomes 1 4 After data is written to the transmit buffer register when TSC 1 0 5 to 3 Fig 21 Operation of UART serial I O function Rev 2 00 Oct15 2006 page 23 of 130 REJ09B0338 0200 Error flag detection occurs at the same time that the RBF flag becomes 1 at 1st stop bit during reception BE or TSC flag becomes 1 depending on the setting of the transmit interrupt 1 5 cycles of the data shift cycle is necessary until changing to TSC 0 2RENESAS 38K2 Group Serial I O Control Register SIOCON OFE016 The serial I O control register contains eight control bits for the se rial I O function UART Control Register UARTCON OFE116 The UART control register consists of four control bits bits 0 to 3 which are valid when asynchronous serial I O is selected and set the data format of an data transfer Serial I O Status Register SIOSTS 002716 The read only serial I O status register consists of seven flags bits 0 to 6 which indicate the operating status of the serial I O function and various errors Three of the flags bits 4 to 6 are valid only in UART mode The receive buffer full flag bit 1 is cleared to 0 when the receive buffer is read If there is an error it is detected at the same time that data is transferred
411. t detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus connect state 2 5 us or more of J or K state on a downstream port 2 in DSCONN2 0 0 can be set by software but 1 cannot be set PTERR2 Downstream port 2 port error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when an error occurs on a downstream port 2 0 can be set by software but 1 cannot be set PTRSM2 Downstream port 2 resume interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a resume signal on a downstream port 2 in the condition of HUB suspended or port suspended state 0 can be set by software but 1 cannot be set tPTCHG2 Downstream port 2 bus change detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus change of a downstream port 2 in the condition of HUB suspended state It is also 1 in the internal clock halted 0 can be set by software but 1 cannot be set Write 0 when writing 0 is read when reading Fig 99 Structure of DP2 interrupt source register Rev 2 00 Oct15 2006 page 67 of 130 REJ09B0338 0200 2RENESAS St
412. t 1 Low current mode valid in VREFE 1 4 USB reference voltage 7 USB reference voltage circuit operation disabled enable bit USB reference voltage circuit operation enabled F USB difference input 0 Upstream port difference input circuit operation disabled enable bit 1 Upstream port difference input circuit operation enabled USB clock select bit External oscillating clock f XIN PLL circuit output clock fvco 7 USB module operation 0 USB module reset enable bit 1 USB module operation enabled Fig 2 12 2 Structure of USB control register Rev 2 00 Oct 15 2006 page 90 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 12 Clock generating circuit CPU mode register b7 b6 b5 b4 b3 be b1 b0 CPU mode register ohi CPUM address 3B16 B Nawe Function rset RW b1 b0 Processor mode bits 0 0 Single chip mode 0 1 Not available 1 0 Not available 1 1 Not available 2 Stack page selection bit H 0 page 1 page Fix this bit to 1 1 Fix this bit to 0 i System clock selection bit ie Main clock f X n ca fsyn System clock division ratio selection bits O system clock 8 8 divide mode system clock 4 4 divide mode system clock 2 2 divide mode system clock Through mode The initial value of bit 1 depends on the CNVss level Fig 2 12 3 Structure of CPU mode register PLL control register b7 b6 b5 b4 b3 b2 bi bO PLL control regist
413. t does not stop by clearing only the transmit enable bit to 0 transmit disabled Also the transmission circuit is not initialized by clearing the serial I O enable bit to 0 Serial I O disabled refer to 1 Rev 2 00 Oct 15 2006 page 24 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 2 3 4 Notes when selecting clock asynchronous serial I O Serial 1 0 Stop of transmission operation Clear the transmit enable bit to O transmit disabled Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I O enable bit is cleared to 0 Serial I O disabled the internal transmission is running in this case since pins TxD RxD SCLK and SRDY function as I O ports the transmission data is not output When data is written to the transmit buffer register in this state data starts to be shifted to the transmit shift register When the serial I O enable bit is set to 1 at this time the data during internally shifting is output to the TxD pin and an operation failure occurs Stop of receive operation Clear the receive enable bit to 0 receive disabled Stop of transmit receive operation Only transmission operation is stopped Clear the transmit enable bit to O transmit disabled Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial
414. t mode 0 Port Pi1 input mode 1 Port Pi1 output mode 0 Port Piz input mode 1 Port Piz output mode y Port Pis input mode RIWI RAKE eG Rage p x 1 Port Pis output mode eee 0 Port Pia input mode x 1 Port Pia output mode 0 Port Pis input mode 1 Port Pis output mode 0 Port Pis input mode 1 Port Pis output mode 0 Port Piz input mode 1 Port Piz output mode Note Since the following ports are not allocated the corrrsponding bits can not be used e P20 to P23 e P44 to P47 e P64 to P67 Do not set bits of the direction register corresponding to ports P20 P23 bits 0 3 of port P2 direction register address 0516 to output mode 1 If writing to these bits write 0 Fig 2 1 3 Structure of Port Pi direction register i 0 to 6 Rev 2 00 Oct 15 2006 page 3 of 112 2tENESAS REJ09B0338 0200 38K2 Group Port PO pull up control register b7 b6 b5 b4 b3 b2 b1 b0 Port PO pull up control register PULLO Address OFF016 Name Function 0 No pull up POo pul l up control bit 1 Pull up 2 fio 1 Po puitapcontorst fipur ojo 2 Poopurumconribt tipat foto 2 Foepuitunconsaist patie ofo a Pooputup conoi fipa 9 foo 5 Poopurupcomoron fap 0 feol i eee Tie e 2 foto 7 POo pul l up control bit Fig 2 1 4 Structure of Port PO pull up control register Port P5 pull up control register b7 b6 b5 b4 b3 b2 bi bO Port P5 pu
415. t only when completing clock set Note 2 When using Index X mode flag T Note 3 When using Decimal mode flag D Push registers used in interrupt process routine Judgment whether clock stops Clock counted up Pop registers pushed to stack 2tENESAS APPLICATION 38K2 Group 2 3 Timer 3 Timer application example 2 Piezoelectric buzzer output Outline The rectangular waveform output function of the timer is applied for a piezoelectric buzzer output Specifications The rectangular waveform dividing the clock f Xin 6 MHz into about 2 kHz 2038 Hz is output from the P51 CNTRo pin The level of the P5 1 CNTRo pin is fixed to H while a piezoelectric buzzer output stops Figure 2 3 13 shows a peripheral circuit example and Figure 2 3 14 shows the timers connection and setting of division ratios Figures 2 3 15 shows the related registers setting and Figure 2 3 16 shows the control procedure The H level is output while a piezoelectric buzzer output stops CNTRo output P51 CNTRo 245 a 245 us Set a division ratio so that the underflow output period of the timer X can be 245 us 38K2 Group Fig 2 3 13 Peripheral circuit example Fixed Prescaler X Timer X Fixed f XIN 6 MHz 1 16 1 92 fe gt CNTRo Fig 2 3 14 Timers connection and setting of division ratios Rev 2 00 Oct 15 2006 page 31 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 3 Timer Timer
416. t operate normally and may perform unstable operation In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation Handling of Power Source Pin In order to avoid a latch up occurrence connect a capacitor suit able for high frequencies as bypass capacitor between power source pin Vcc pin and GND pin Vss pin Besides connect the capacitor to as close as possible For bypass capacitor which should not be located too far from the pins to be connected a ce ramic or electrolytic capacitor of 1 0 uF is recommended USB Port Pins D0 DO D1 D1 D2 D2 Treatment The USB specification requires a driver impedance 28 to 44 Q In order to meet the USB specification impedance requirements connect a resistor 27 Q recommended in series to the USB port pins In addition in order to reduce the ringing and control the falling rising timing and a crossover point connect a capacitor between the USB port pins and the Vss pin if necessary The values and structure of those peripheral elements depend on the impedance characteristics and the layout of the printed circuit board Accordingly evaluate your system and observe waveforms before actual use and decide use of elements and the values of
417. t symbol Bit name Function At reset H W S W FNUM Frame number high bit The frame number is updated at SOF reception In In 10 8 definite definite b7 b3 Not used Write 0 when writing 0 is read when reading e remaining Fig 3 4 8 Structure of Frame number register High bo USB interrupt source enable register USBICON address 001616 At reset H W S W errupt disabled 0 0 errupt enabled errupt disabled 0 0 errupt enabled errupt disabled errupt enabled errupt disabled errupt enabled errupt disabled errupt enabled errupt disabled errupt enabled errupt disabled errupt enabled errupt disabled errupt enabled Bit symbol Bit name Function EPOOE USB function Endpoint 0 interrupt enable bit EPO1E USB function Endpoint 1 interrupt enable bit EP02E USB function Endpoint 2 interrupt enable bit EPO3E USB function Endpoint 3 interrupt enable bit EP10E USB HUB Endpoint 0 interrupt enable bit EP11E USB HUB Endpoint 1 interrupt enable bit SUSE Suspend interrupt enable bit RSME Resume interrupt enable bit Gja gl oc o oO ol ol oo Fig 3 4 9 Structure of USB interrupt source enable register Rev 2 00 Oct 15 2006 page 41 of 99 2tENESAS REJ09B0338 0200 38K2 Group USB interrupt source register USBIREQ address 001716 APPENDIX 3 4 L
418. ta transfer timing of memory channel Rev 2 00 Oct15 2006 page 70 of 130 REJ09B0338 0200 2tENESAS 38K2 Group EXB Pin Assignment The external bus interface EXB pins are shown bellow The 38K2 group can transmit receive a data to from an external MCU using the following signals Control input signal 4 ExCS ExA0 ExRD ExWR Data input output pin 8 DQo to DQ7 Interrupt output signal 1 ExINT Additionally the DMA interface signal and the buffer status read select signal of 38K2 group can be set up per one by the program Control input signal 3 ExTC ExDACK ExRD ExA1 Interrupt output signal 1 ExDREQ External pins External chip select External address External read External write p External data 4 gt External interrupt lt _ _ DMA request 4 Terminal count gt DMA acknowledge Status read select Functions as normal ports just after reset 38K2 group External bus interface EXB P34 ExCS L P37 ExA0 address P36 ExRD L P35 ExWR L P10 DQ0 ANo P17 DQ7 AN7 data P33 ExINT L P40 ExDREQ RxD L P42 ExTC ScLK L P41 ExDACK TxD L P43 ExA1 SRDY H Fig 105 External bus interface EXB pin assignment Rev 2 00 Oct15 2006 page 71 of 130 REJ09B0338 0200 2RENESAS HARDWARE FUNCTIONAL DESCRIPTION Multichannel RAM HAR
419. tchdog timer L is supplied as the count source of watchdog timer H Figure 2 9 4 shows a watchdog timer connection and division ratio setting Figure 2 9 5 shows the related registers setting Figure 2 9 6 shows the control procedure Fixed Watchdog timer L Watchdog timer H XIN 6 MHz gt 1 16 1 256 H Internal reset STP instruction disable bit STP instruction Fig 2 9 4 Watchdog timer connection and division ratio setting Rev 2 00 Oct 15 2006 page 80 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 9 Watchdog timer CPU mode register address 3B16 bo b7 ceum ili lololi folol gt Processor mode Single chip mode gt System clock Main clock gt System clock division ratio f system clock Through mode Watchdog timer control register address 3916 b7 bo worcon Lolo h gt Watchdog timer H for read out of high order 6 bits gt Enable STP instruction gt Watchdog timer H count source Watchdog timer L underflow Fig 2 9 5 Related registers setting Initialization SEI All interrupts disabled CLT CLD Processor mode Single chip mode CPUM address 3B16 lt 11001X002 Main clock f XiN Operating Through mode selected as main clock division ratio CLI Interrupts enabled Watchdog timer L underflow selected as Watchdog WDTCON address 3916 bit7 bit6 lt 002 timer H count source STP instruction enabled
420. tchdog timer function by software If a microcomputer runs away because of noise or others it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation This is equal to or more effective than program runaway detection by a hardware watchdog timer The following shows an example of a watchdog timer provided by software In the following example to reset a microcomputer to normal operation the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine This example assumes that interrupt processing is repeated multiple times in a single main routine processing lt The main routine gt e Assigns a single byte of RAM to a software watchdog timer SWDT and writes the initial value N in the SWDT once at each execution of the main routine The initial value N should satisfy the following condition N 1 gt Counts of interrupt processing executed in each main routine As the main routine execution cycle may change because of an interrupt processing or others the initial value N should have a margin e Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set e Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case If t
421. te remaining Bit symbol Bit name Function At reset H W S W BADDOO 4 0 EP00 beginning address set bit Set the beginning address of EPO0 s buffer area 0 32 byte unit b4b3b2b1b0 000 1 0 004016 006016 03C016 03E016 Write 0 when writing 0 is read when reading Fig 46 Structure of EPOO buffer area set register Rev 2 00 Oct15 2006 page 40 of 130 REJ09B0338 0200 7tENESAS State remaining 38K2 Group 2 Endpoint 01 HARDWARE FUNCTIONAL DESCRIPTION EP01 set register EP01CFG address 001916 Bit symbol Bit name Function At reset H W S W BSIZ01 1 0 Double buffer beginning address set bit In double buffer mode set the beginning address of buffer 1 area using a relative value for the beginning address of buffer 0 b1b0 00 8 bytes 01 16 bytes 10 64 bytes 1 1 128 bytes 0 DBLBO1 Buffer mode select bit 0 Single buffer mode 1 Double buffer mode SQCLO01 Sequence toggle bit clear bit 0 Toggle bit clear disabled 1 Writing 1 clears the toggle bit and DATAO is used as the next data PID 0 is always read when reading ITMDO1 Interrupt toggle mode select bit 0 Normal mode 1 Continuous toggle mode valid at Interrupt IN transfer DIRO1 Transfer direction bit 0 OUT Data is received f
422. te remaining Bit symbol Bit name Function At reset H W B1BYT03 6 0 IN Transmit byte number bit Single buffer mode These bits are invalid Double buffer mode Set the transmitting byte number of buffer 1 0 OUT Receive byte number bit Single buffer mode These bits are invalid is automatically set Double buffer mode The received byte number of buffer 1 Write 0 when writing 0 is read when reading Fig 3 4 49 Structure of EP03 byte number register 1 Rev 2 00 Oct15 2006 page 57 of 99 REJ09B0338 0200 2tENESAS State remaining APPENDIX 38K2 Group 3 4 List of registers Prescaler 12 Prescaler X b7 b6 b5 b4 b3 b2 b1 bO Prescaler 12 PRE12 Address 2016 Prescaler X PREX Address 2416 Beane ooo looo uton paw Set a count value of each prescaler The value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time When this register is read out the count value of the corres ponding prescaler is read out Fig 3 4 50 Structure of Prescaler12 Prescaler X Timer 1 b7 b6 b5 b4 b3 b2 b1 bO Timer 1 T1 Address 2116 Set a count value of timer 1 The value set in this register is written to both timer 1 and timer 1 latch at the same time When this register is read out the timer 1 s count value is read out
423. ted automatically 2 Wait mode If the WIT instruction is executed the internal clock stops at an H level but the oscillator does not stop The internal clock 6 re starts at reset or when an interrupt is received Since the oscillator does not stop normal operation can be started immediately after the clock is restarted To ensure that the interrupts will be received to release the STP or WIT state their interrupt enable bits must be set to 1 before ex ecuting of the STP or WIT instruction When releasing the STP state the prescaler 12 and timer 1 will start counting the clock XIN divided by 16 Accordingly set the timer 1 interrupt enable bit to O before executing the STP instruc tion HNote When using the oscillation stabilizing time set after STP instruction released bit set to 1 evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION MISRG XIN XOUT MISRG address OFFBi6 Rd Note Oscillation stabilizing time set after STP instruction released bit 0 Automatically set 0116 to Timer 1 FF16 to Prescaler 12 1 Automatically set nothing Not used indefinite at read Jo Jo Note Insert a damping resistor if required 7 The resistance will vary depending on the oscillator Fig 143 Struc
424. ternal signal DSLSPD2 Downs ream port 2 USB transfer speed select bit Full speed mode 12MHz Low speed mode 1 5 MHz Fig 100 Structure of DP2 control register b7 bO ofofofolofo DP2 status register DP2STS address 002D16 State remaining Bit symbol Bit name Function At reset H W S W D2MINUS D2 signal bit In DSRMOD2 0 a downstream port 2 bus state is read using RD signal In DSRMOD2 1 a downstream port 2 bus state is read using EOF2 signal internal signal In definite In definite D2PLUS D2 si gnal bit In DSRMOD2 0 a downstream port 2 bus state is read using RD signal In DSRMOD2 1 a downstream port 2 bus state is read using EOF2 signal internal signal In definite In definite Not us ed Write 0 when writing 0 is read when reading Fig 101 Structure of DP2 status register Rev 2 00 Oct15 2006 page 68 of 130 REJ09B0338 0200 2RENESAS State remaining 38K2 Group HARDWARE FUNCTIONAL DESCRIPTION Downstream port control register DPCTL address OFF916 Bit symbol Bit name Function At reset H W S W PCON1 1 0 Downstream port 1 function select bit USB port D1 D1 OFF USB difference amplifier OFF USB exclusive input
425. terrupts cannot be used during the CPU rewrite mode because they refer to the internal data of the flash memory Watchdog timer In case of the watchdog timer has been running already the internal reset generated by watchdog timer underflow does not happen because of watchdog timer is always clearing during program or erase operation Reset Reset is always valid In case of CNVss H when reset is released boot mode is active So the program starts from the address contained in address FFFC1s and FFFDie in boot ROM area Rev 2 00 Oct 15 2006 page 28 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 3 2 13 Notes on programming 1 Processor status register Initializing of processor status register Flags which affect program execution must be initialized after a reset In particular it is essential to initialize the T and D flags because they have an important effect on calculations Reason After a reset the contents of the processor status register PS are undefined except for the flag which is 1 Reset Initializing of flags Main program Fig 3 2 4 Initialization of processor status register How to reference the processor status register To reference the contents of the processor status register PS execute the PHP instruction once then read the contents of S 1 If necessary execute the PLP instruction to return the PS to its original status A NOP instruction should
426. that an external MCU uses the 38K2 group as a peripheral LSI USB controller The following explains that the external MCU reads out the data which is received via the USB The data which is received via the USB is written into the multi channel RAM Receive completion is propagated to the CPU The external bus interface is activated owing to the CPU 1 The external bus interface sets the data which is read from the multichannel RAM into the internal data buffer 2 The external MCU reads out the data bus buffer of the exter nal bus interface 3 The above operation is repeated by the number of the re ceived bytes After that the data transfer is completed USB bus USB host 2 S T E g 4 uw FIFO read of received data Fail FIFO write of received data by External bus interface i H by USB Fig 131 Multichannel RAM operation example Rev 2 00 Oct15 2006 page 90 of 130 2tENESAS REJ09B0338 0200 38K2 Group A D CONVERTER The functional blocks of the A D converter are described below AD Conversion Register 1 2 AD1 AD2 003716 003816 The AD conversion register is a read only register that stores the result of an A D conversion When reading this register during an A D conversion the previous conversion result is read Bit 7 of the AD conversion register 2 must be set to 0 Not only 10 bit reading but also only high order 8 bit reading o
427. that the analog switch 74HC4066 cut off the control signals not to supply to the user system circuit in the standard serial I O mode Target board 74HC4066 Ta To user system circuit M38K29F8FP HP M38K29F8LFP LHP TxD P41 ExDACk SCLK P42 ExTC RxD P40 ExDREQ Busy P43 ExA1 P16 VpP CNVss 455 RESET User reset signal Low active It is necessary to apply Vcc to Scik P42 ExTC pin only when reset is released in the standard serial I O mode Fig 2 14 7 Connection example in standard serial I O mode 3 Rev 2 00 Oct 15 2006 page 109 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory 2 Control example in CPU rewrite mode In this example data is received by using serial I O and the data is programmed to the built in flash memory in the CPU rewrite mode Figure 2 14 8 shows an example of the reprogramming system for the built in flash memory in the CPU rewrite mode Figure 2 14 9 shows the CPU rewrite mode beginning release flowchart M38K29F8FP HP M38K29F8LFP LHP P16 CE Clock input SCLK BUSY output Srpy Busy Data input RxD Data output lt __ TxD Vpp power source input Note 1 User reset signal Note 1 Apply 4 50 to 5 25 V to the Ver power source Fig 2 14 8 Example of rewrite system for bu
428. the shortest possible Note Even when a circuit which included an approximately 5 kQ resistor is used in the Mask ROM version the microcomputer operates correctly Reason The VPP pin of the flash memory version is the power source input pin for the built in flash memory When programming in the built in flash memory the impedance of the VPP pin is low to allow the electric current for writing flow into the flash memory Because of this noise can enter easily If noise enters the VPP pin abnormal instruction codes or data are read from the built in flash memory which may cause a program runaway Approximately 5kQ CNVss VpP b In the shortest distance Fig 3 3 5 Wiring for the VPP pin of the flash memory version 3 3 2 Connection of bypass capacitor across Vss line and Vcc line Connect an approximately 0 1 uF bypass capacitor across the Vss line and the Vcc line as follows e Connect a bypass capacitor across the Vss pin and the Vcc pin at equal length e Connect a bypass capacitor across the Vss pin and the Vcc pin with the shortest possible wiring e Use lines with a larger diameter than other signal lines for Vss line and Vcc line e Connect the power source wiring via a bypass capacitor to the Vss pin and the Vcc pin Fig 3 3 6 Bypass capacitor across the Vss line and the Vcc line Rev 2 00 Oct 15 2006 page 34 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 3 Countermeasures against noise 3 3 3
429. thin a certain time heading adjustment time the next clock input is processed as the beginning heading of a block When a clock is input again after one block 8 byte is received the clock is ignored Figure 2 4 26 shows related registers setting Do D1 D2 ae D7 ee Do I Byte cycle net Block transfer term Interval between blocks i gt Block transfer cycle gt Heading adjustment time gt 4 Processing for heading adjustment Fig 2 4 25 Timing chart Master unit Slave unit Serial I O control register Address OFE016 oe I O control Eae Address OFE016 bO b7 siocon 1 a i f fofofo SIOCON PEEELEET BRG count source f XIN Be Not affected by external clock Synchronous clock BRG 4 Synchronous clock External clock Sroy output disabled Srov output disabled Transmit interrupt source Not use the serial I O transmit interrupt Transmit shift operating completion Transmit enabled Transmit enabled Receive enabled Receive enabled gt Clock synchronous serial I O gt Clock synchronous serial I O ___ Serial I O enabled Serial 1 0 enabled Both of units Baud rate generator oe OFE216 b7 BRG Set division ratio 1 Fig 2 4 26 Related registers setting Rev 2 00 Oct 15 2006 page 57 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Control procedure Control in the master unit After setting the related
430. tically set to 1 so that multiple interrupts are disabled To use multiple interrupts set this flag to O with the CLI instruction within the interrupt processing routine Figure 2 2 12 shows an example of multiple interrupts Table 2 2 2 List of interrupt bits according to interrupt source Interrupt enable bit Interrupt source Interrupt request bit Address Bit Address Bit USB bus reset 003E16 003C16 bO USB SOF 003E16 003C16 b1 USB device 003E16 003C16 b2 External bus 003E16 003C16 b3 INTo 003E16 003C16 b4 Timer X 003E16 003C16 b5 Timer 1 003E16 003C16 b6 Timer 2 003 E16 003C16 b7 INT 003Fi6 003Di6 bO USB HUB 003Fi6 003Di6 b1 Serial I O receive 003Fi6 003Di6 b2 Serial I O transmit 003Fi6 003Di6 b3 CNTRo 003Fi6 003Di6 b4 Key on wake up 003F 16 003Di16 b5 A D converter 003F16 003D16 b6 Rev 2 00 Oct15 2006 page 16 of 112 REJ09B0338 0200 7RENESAS APPLICATION 38K2 Group 2 2 Interrupt Interrupt request Nesting Main routine l 1 Ci 0 C2 0 Interrupt request 1 Interrupt 1 Interrupt Multiple interrupt request 2 Interrupt disable flag Interrupt enable bit of interrupt 1 Interrupt enable bit of interrupt 2 Set automatically L Set by software Fig 2 2 12 Example of multiple interrup
431. tion bit of CPU mode register bit 5 of CPUM address 003Bie to 1 fsyn Table 2 11 2 shows the example of USB clock division ratio selection bits setting Table 2 11 2 USB clock division ratio selection bits setting example USB clock division f Ise ratio selection bits ila 00 6 MHz 48 MHz 01 8 MHz 10 12 MHz PLL control register bit4 3 Setting for starting up PLL circuit when hardware reset Figure 2 11 6 shows the example of related registers setting X This bit is not used here Set it to O or 1 arbitrarily CPUM address 3B16 lt 11001X002 Select main clock f X n as a system clock USBCON address 1016 XOXXXXXXz2 Select main clock f Xin as a USB clock PLL operation mode bit6 5 Multiplied by 8 PLLCON address OFF816 111010002 USB division mode bit4 3 Divided by 6 Enable PLL operation bit7 Wait for oscillation stabilization When multiplying oscillation by PLL wait for oscillation stabilization Wait approximately 1 ms USBCON address 1016 lt X1XXXXXX2 Select PLL circuit output clock fvco as a USB clock CPUM address 3B16 lt 11101X002 Select fsyN as a system clock Note The above setting example assumes the operation when the external oscillating clock is 6 MHz and the internal system clock is fsyn Fig 2 11 6 Related registers setting when hardware reset Rev 2 00 Oct 15 2006 page 87 of 112 2RENESAS REJ09B0338 0200
432. tion register INT_CTR 3 1 P33 ExINT pin control 0102 TxB_RDY interrupt lt Operation start gt EXB interrupt source enable register TXB_ENB CPU channel transmit enable 1 Transmit buffer empty interrupt enabled Writing the command for enabling operation generates TXB_EMPTY interrupt If the CPU channel transmit enable bit TXB_ENB is 0 both the transmit buffer empty bit TXB_EMPTY and the transmit buffer ready signal TxB_RDY to an external are inactive When the CPU writes the data into the transmit buffer TXBUF with an interrupt processing program the transmit buffer empty bit TXB_EMPTY is cleared to 0 and assertion of the transmit buffer ready signal TxB_RDY to an external is made When a read operation is performed from an external MCU bus in the condition of ExCS L and ExA0 H it will result in as follows The contents of the transmit buffer TXBUF is read out The transmit buffer empty bit TXB_EMPTY is set to 1 Negation of the transmit buffer ready signal TxB_RDY to an external is made Fig 123 CPU channel tranmitting operation Rev 2 00 Oct 15 2006 page 83 of 130 RENESAS REJ09B0338 0200 HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION 3 Memory Channel Receiving Operation 1 Cycle Mode Memory channel receiving operation 1 is shown bellow Address ExA0 Chip select ExCS DMA acknowledge ExDACK Read ExRD Wr
433. tion register allows each pin to be individually programmed as either input or output CMOS compatible input levele CMOS 3 state output structure Output large current for LED drive is enabled 7tENESAS 38K2 Group PART NUMBERING Product M38K2 7M 4 L XXX FP Package type FP PLQP0064GA A package HP PLQPO064KB A package ROM number Omitted in the flash memory version Omitted in the flash memory version L L version ROM PROM size 1 4096 bytes 8192 bytes 12288 bytes 16384 bytes 20480 bytes 24576 bytes 36864 bytes 40960 bytes 45056 bytes 49152 bytes 53248 bytes 57344 bytes HARDWARE PART NUMBERING Fig 3 Part numbering Rev 2 00 Oct15 2006 page 5 of 130 REJ09B0338 0200 9 A B C D E F 28672 bytes 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas they cannot be used as a user s ROM area However they can be programmed or erased in the flash memory version so that users can use them 61440 bytes Memory type M Mask ROM version F Flash memory version RAM size 192 bytes 256 bytes 384 bytes 512 bytes 640 bytes 768 bytes 896 bytes 1024 bytes 1536 bytes 2048 bytes OONDORWN O 2tENESAS 38K2 Group GROUP EXPANSION Mitsubishi plans to expand the 38K2 group as follows Memory Type Support for mask ROM and flash memory versions Memory S
434. tions The frequency of the internal clock fis half of the Xin frequency in high speed mode Rev 2 00 Oct 15 2006 page 30 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 2 Notes on use 3 2 14 Notes on flash memory version The CNVss pin is connected to the internal memory circuit block by a low ohmic resistance since it has the multiplexed function to be a programmable power source pin Vee pin as well To improve the noise reduction connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10 kQ resistance The mask ROM version track of CNVss pin has no operational interference even if it is connected to Vss pin or Vcc pin via a resistor 3 2 15 Electric Characteristic Differences Between Mask ROM and Flash Memory Version MCUs There are differences in electric characteristics operation margin noise immunity and noise radiation between Mask ROM and Flash Memory version MCUs due to the difference in the manufacturing processes When manufacturing an application system with the Flash Memory version and then switching to use of the Mask ROM version please perform sufficient evaluations for the commercial samples of the Mask ROM version Rev 2 00 Oct 15 2006 page 31 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 3 Countermeasures against noise 3 3 Countermeasures against noise Countermeasures against noise are described below The following countermeasures are effective against noise in theory however it
435. to be used for restoration 0 no interrupt request issued Interrupt enable bit of interrupt source to be used for restoration 1 interrupts enabled For more details concerning interrupts refer to 2 2 Interrupts 2 13 5 Notes on stand by function In stand by state for low power dissipation do not make input levels of an input port and an I O port undefined Pull up connect the port to Vcc these ports through a resistor When determining a resistance value note the following points e External circuit e Variation of output levels during the ordinary operation When using built in pull up resistor note on varied current values e When setting as an input port Fix its input level e When setting as an output port Prevent current from flowing out to external Reason The potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input port and an I O port are undefined This may cause power source current 1 stand by state the stop mode by executing the STP instruction the wait mode by executing the WIT instruction Rev 2 00 Oct 15 2006 page 102 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 14 Flash memory 2 14 Flash memory This paragraph explains the registers setting method and the notes related to the flash memory version 2 14 1 Overview The functions of the flash memory version are similar to those of the mask ROM ve
436. transmit buffer and receive data is read from the receive buffer The transmit buffer can also hold the next data to be transmitted and the receive buffer register can hold a character while the next character is being received Data bus Address 002616 OE Receive buffer register Character length selection bit 7 P4o ExDREQ RxD O Serial 1 01 control register Address OFE016 Receive buffer full flag RBF Receive interrupt request RI Receive shift register SP detector Serial I O synchronous clock selection bit mj feH P42 ExTC ScLk O 1 16 UART control register Address OFE116 Clock control circuit BRG count source selection bit Frequency division ratio 1 System clock O Address OFE216 Baud rate generator n 1 ST SP PA generator P41 ExDACK TxD O lt Character length selection bit Fig 20 Block diagram of UART serial I O Transmit or receive clock Transmit buffer write signal Serial output TxD Transmit shift register Transmit buffer register Address 002616 Transmit shift register shift completion flag TSC Transmit interrupt source selection bit a ween interrupt request TI Transmit buffer empty flag TBE Serial I O status register Address 002716 tH 7 o 8 data bits 1 _ 1 or 0 parity bit Receive buffer read signal 1 or 2 stop bit s SerialinputixD N STX DY XK n Notes 1 2 The transmit interrup
437. ts Rev 2 00 Oct 15 2006 page 17 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 2 Interrupt 2 2 6 INT interrupt The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin INTo INT 1 Active edge selection INTo and INT can be selected from either a falling edge or rising edge detection as an active edge by the interrupt edge selection register In the O state the falling edge of the corresponding pin is detected In the 1 state the rising edge of the corresponding pin is detected Rev 2 00 Oct 15 2006 page 18 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 2 Interrupt 2 2 7 Key input interrupt A key input interrupt request is generated by applying L level to any port PO pin that has been set to the input mode In other words it is generated when AND of the input level goes from 1 to 0 1 Connection example when Key input interrupt is used When using the Key input interrupt compose an active low key matrix which inputs to port PO Figure 2 2 13 shows a connection example and the port PO block diagram when using a key input interrupt In the connection example in Figure 2 2 13 a key input interrupt request is generated by pressing one of the keys corresponding to ports PQo to POs Port PXx L level output PU LL 0 register Port P07 Key input interrupt request Bit 7 0 direction register 1 oF a Port P07 atc
438. ts of S by one This instruction pushes the contents of PS to the memory location designated by S and dec rements the contents of S by one This instruction increments S by one and stores the contents of the memory designated by Sin A This instruction increments S by one and stores the contents of the memory location designated by S in PS This instruction shifts either A or M one bit left through C C is stored in bit 0 and bit 7 is stored in C This instruction shifts either A or M one bit right through C C is stored in bit 7 and bit 0 is stored in C This instruction rotates 4 bits of the M content to the right S lt S 1 PS M S S S 1 PCL amp M S SesS 1 PCH amp M S This instruction increments S by one and stores the contents of the memory location designated by S in PS S is again incremented by one and stores the contents of the memory location designated by S in PCL S is again incremented by one and stores the contents of memory location designated by S in PCH S lt S 1 PCL amp M S SesS 1 PCH amp M S PC PC 1 Rev 2 00 Oct15 2006 page 92 of 99 REJ09B0338 0200 This instruction increments S by one and stores the contents of the memory location designated by S in PCL S is again incremented by one and the contents of the memory location is stored in PCH PC is incremented by 1
439. ture of Endpoint index register ccceceecececeeeeeeeeececeeeeeeeeseceeeeseaeeseeeeeeeeaeeeeaees 37 Structure of EPOO stage register ccccccseceeeeeececeeeeeeeeeceeaeeeseneeseaeeeseaeeseeeeeesaeeeeaes 38 Structure of EPOO control register 1 ceeceeeceeececeeeeeeeeeceeeeeeeeeeeseeaeeeseaeeseeaeeestaeeeeaees 38 Structure of EPOO control register 2 0 eeceeeceeeceeeeeeeeeeececeeeeseeeeseaeeeseaeeseeeeeeseaeeeeaees 38 Structure of EPOO control register 3 oo ce ceeeceeececeeeeeeeeececeeeeeeeeesecaeeeeeaeeseeeeseeaeeeeaees 39 page 4 of 14 RENESAS 38K2 Group Fig 44 Fig 45 Fig 46 Fig 47 Fig 48 Fig 49 Fig 50 Fig 51 Fig 52 Fig 53 Fig 54 Fig 55 Fig 56 Fig 57 Fig 58 Fig 59 Fig 60 Fig 61 Fig 62 Fig 63 Fig 64 Fig 65 Fig 66 Fig 67 Fig 68 Fig 69 Fig 70 Fig 71 Fig 72 Fig 73 Fig 74 Fig 75 Fig 76 Fig 77 Fig 78 Fig 79 Fig 80 Fig 81 Fig 82 Fig 83 Fig 84 Fig 85 Fig 86 Fig 87 Fig 88 Fig 89 Fig 90 Fig 91 Fig 92 Fig 93 Fig 94 Fig 95 Rev 2 00 Oct 15 2006 REJ09B0338 0200 List of figures Structure of EPOO interrupt source register ceeeeceececeeeeseeeececeeeeeeaeeseeeeeeeaeeeeaees 39 Structure of EPOO byte number reQiSter c ccccceeeeseeceeeeeeeeeeeceeeeeeeeeeseeeeeseaeeneaees 40 Structure of EPOO buffer area Set reQiSter ccecceeesceeceeeeeeeeeeeeeeeeeeeaeeseeeeeesaeeetenes 40 Structure of EPO1 set register ccc
440. ture of MISRG and the oscillation drive capacity setting Use the value recommended by the maker of the oscillator Also if the oscillator manufacturer s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on chip insert a feedback resistor between Xin and XouT following the instruction Fig 141 Ceramic resonator or quartz crystal oscilltor circuit External oscillation circuit Fig 142 External clock input circuit p fVC0 USB clock selection bit USB clock division ration selection bits o fsyn o System clock selection bit ee Prescaler 12 Timer 1 Reset or STP FFi6 0116 instruction System clock division ration selection bits Timing 9 internal clock Reset STP instruction WIT STP instruction p instruction Reset Interrupt disable flag Interrupt request 1 Fig 144 System clock generating circuit block diagram single chip mode Rev 2 00 Oct 15 2006 page 98 of 130 2tENESAS REJ09B0338 0200 38K2 Group XIN 8 divide mode f 0 75 MHz CM7 0 CM6 0 CM5 0 PLLCON 4 3 00 XIN 2 divide mode f 3 0 MHz CM7 1 CM6 0 CM5 0 PLLCON 4 3 xx arbitrary Note to fSYN f SYN 2 divide mode f 6 0 MHz CM7 1 CM6 0
441. ty for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this doc
442. ued Lo lois request bit 1 Interrupt request issued E 0 can be set by software but 1 cannot be set Fig 3 4 83 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 bi bO Interrupt request register 2 IREQ2 Address 3D16 E Name Function INT1 interrupt 0 No interrupt request issued l j request bit 1 Interrupt request issued O 1 USB HUB interrupt 0 No interrupt request issued Ol request bit 1 Interrupt request issued I 2 Serial I O receive 0 No interrupt request issued ol interrupt request bit 1 Interrupt request issued I 3 Serial I O transmit 0 No interrupt request issued Ol ie interrupt request bit 1 Interrupt request issued I CNTRo interrupt 0 No interrupt request issued l 4 Ol request bit 1 Interrupt request issued I 5 Key on wake up _ 9 No interrupt request issued o interrupt request bit Interrupt request issued A D conversion D No interrupt request issued o interrupt request bit Interrupt request issued Nothing is arranged for this bits This is a write disabled bit 7 When this bit is read out the contents are 0 OQ can be set by software but 1 cannot be set Fig 3 4 84 Structure of Interrupt request register 2 Rev 2 00 Oct 15 2006 page 73 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 4 List of registers Interrupt control register 1 b7 b6 b5 b4 b3 b2 bi bO Interrupt
443. uest register 2 b7 b6 b5 b4 b3 b2 bi bO Interrupt request register 2 IREQ2 Address 3D16 B Name Funcion INT1 interrupt 0 No interrupt request issued Le request bit 1 Interrupt request issued oF 4 USB HUB interrupt 0 No interrupt request issued o n request bit 1 Interrupt request issued I 2 Serial I O receive 0 No interrupt request issued re interrupt request bit 1 Interrupt request issued O 3 Serial I O transmit 9 No interrupt request issued oi 4 interrupt request bit Interrupt request issued l CNTRo interrupt n No interrupt request issued l re Olx quest bit Interrupt request issued I g Key on wake up i No interrupt request issued o x interrupt request bit Interrupt request issued A D conversion o No interrupt request issued interrupt request bit Interrupt request issued Nothing is arranged for this bits This is a write disabled bit When this bit is read out the contents are 0 0 can be set by software but 1 cannot be set Fig 2 3 7 Structure of Interrupt request register 2 Rev 2 00 Oct15 2006 page 26 of 112 RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 3 Timer Interrupt control register 1 b7 b6 b5 b4 b3 b2 bi b0 Interrupt control register 1 ICON1 a 3E16 Name Function _ Atreset iW om bus reset Interrupt disabled interrupt enable bit TE enabled USB SOF interrupt 0 Interrupt disabled enable bit Interrupt enabled D USB device
444. ulling CNVss pin low In this case the CPU starts operating using the control program in the User ROM area When the microcomputer is reset by pulling the P16 CE pin high the CNVss pin high the CPU starts operating using the control program in the Boot ROM area This mode is called the Boot mode Block Address Block addresses refer to the maximum address of each block These addresses are used in the block erase command Boot ROM area FFFFi6 heres Notes 1 The Boot ROM area can be rewritten in only parallel I O mode Access to any other areas is inhibited 2 To specify a block use the maximum address in the block Fig 146 Block diagram of built in flash memory Rev 2 00 Oct15 2006 page 101 of 130 REJ09B0338 0200 2RENESAS 38K2 Group Outline Performance CPU Rewrite Mode CPU rewrite mode is usable in the single chip or Boot mode The only User ROM area can be rewritten in CPU rewrite mode In CPU rewrite mode the CPU erases programs and reads the in ternal flash memory as instructed by software commands This rewrite control program must be transferred to a memory such as the internal RAM before it can be executed The MCU enters CPU rewrite mode by applying 4 50 V to 5 25 V to the CNVss pin and setting 1 to the CPU Rewrite Mode Select Bit bit 1 of address OFFE16 Software commands are accepted once the mode is entered Use software commands to control program and erase operations Whether
445. ument When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision ad
446. upts enabled For more details concerning interrupts refer to 2 2 Interrupts Oscillation is unstable when restarted For this reason time for stabilizing of oscillation oscillation stabilizing time is required For restoration by an interrupt request waiting time prior to supplying internal clock to the CPU is automatically generated by Prescaler 12 and Timer 1 This waiting time is reserved as the oscillation stabilizing time on the system clock side The supply of internal clock to the CPU is started at the Timer 1 underflow Figure 2 13 4 shows an execution sequence example at restoration by the occurrence of an INTo interrupt request 1 If the STP instruction is executed when the oscillation stabilizing time set after STP instruction released bit is O FFie and 01 16 are automatically set in the Prescaler 12 counter latch and Timer 1 counter latch respectively When the oscillation stabilizing time set after STP instruction released bit is 1 nothing is automatically set to either Prescaler 12 or Timer 1 For this reason any suitable value can be set to Prescaler 12 and Timer 1 for the oscillation stabilizing time 2 Immediately after the oscillation is started the count source is supplied to the prescaler 12 so that a count operation is started Rev 2 00 Oct 15 2006 page 98 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 13 Standby function When restoring microcomputer from
447. ure of EP02 byte number register O ceeceeesseeeeeeeeeeeeeeeeeeeeeseaeeseeeeeestaeeeeenes 47 Structure of EP02 byte number register 1 ecceeceeesceeeeeeeeeeeeeeeeeeeeeeaeeseeeeeeseaeeseenes 47 Structure of EP02 MAX packet size register ccceceeceeeeeeeeeeeceeeeeeeaeeteeeeeeseaaeeeenes 47 Structure of EP02 buffer area Set reQiSter ccecceeesseeceeeeeeeeeeseeeeeeeaeeseeeeeesiaeeeeenes 48 Structure of EPO3 set register cccccescccccecseeeeeeeeeceeeeeeeeeceeaeeeeaaeeseeaeseeaaeesseeeesiaaeeneaes 49 Structure of EPO3 control register 1 eeceeeeceeceeeeeeeeeeececeeeeseeeeseeaeeeseaeeseeeeeetaeeeeaees 49 Structure of EPO3 control register 2 0 ceeeeecececeeeeeeeee cece eeeeeeeseaeeeseaeeseeeeeseaeeeeaees 50 Structure of EPO3 control register 3 ceceeeceeececeeeeeeeeeceeeeeseaeececaeeeseaeeseeaeeeetaeeeeaees 50 Structure of EP03 interrupt source register 0 cececceeececeeeeeeeeeceeeeeeeeeeseeeeeetaeeneaees 50 Structure of EPO3 byte number register O eeeeceeeesceeceneeeeeeeeeseeeeeesaeeseeeeeesaeeetenes 51 Structure of EPO3 byte number register 1 ceeceeesceeceeeeeeeeeeeeeeeeeeeaeeeeeeeeessaeeeeenes 51 Structure of EP03 MAX packet size register cceeeeceeeeeeeeeeeseeeeeeeeaeeseeeeeeseaaeetenes 51 Structure of EPO3 buffer area Set reQiSter cceccesseeceeeeeeeeeeseeeeeesaeeeeeeeeesiaeeeeenes 52 Structure of EP10 stage register cccccccececeeeececeeeeeeeeeceeaeeeseaeeseae
448. ushed onto the stack area are restored to the respective registers in the order of and and the microcomputer resumes the processing executed just before acceptance of the interrupts Figure 2 2 7 shows an interrupt operation diagram Executing routine Accepting interrupt request Suspended Interrupt occurs Contents of program counter high order are pushed onto stack operation Contents of program counter low order are pushed onto stack Resume processin P E Contents of processor status register are pushed onto stack Interrupt processing routine RTI instruction Contents of processor status register are popped from stack Contents of program counter low order are popped from stack Contents of program counter high order are popped from stack Operation commanded by software OoOo Internal operation performed automatically Fig 2 2 7 Interrupt operation diagram Rev 2 00 Oct 15 2006 page 12 of 112 2tENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 2 Interrupt 1 Processing upon acceptance of interrupt request Upon acceptance of an interrupt request the following operations are automatically performed The processing being executed is stopped The contents of the program counter and the processor status register are pushed onto the stack area Figure 2 2 8 shows the changes of the stack pointer and the program counter upon acceptance of an inte
449. ut to an analog input pin charge and discharge noise generates This may cause the A D conversion precision to be worse 2 Clock frequency during A D conversion The comparator consists of a capacity coupling and a charge of the capacity will be lost if the clock frequency is too low Thus make sure the following during an A D conversion f XIN is 500 kHz or more e Do not execute the STP instruction 3 2 8 Notes on watchdog timer Make sure that the watchdog timer does not underflow while waiting Stop release because the watchdog timer keeps counting during that term When the STP instruction disable bit has been set to 1 it is impossible to switch it to O by a program 3 2 9 Notes on RESET pin Connecting capacitor In case where the RESET signal rise time is long connect a ceramic capacitor or others across the RESET pin and the Vss pin Use a 1000 pF or more capacitor for high frequency use When connecting the capacitor note the following e Make the length of the wiring which is connected to a capacitor as short as possible e Be sure to verify the operation of application products on the user side Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin it may cause a microcomputer failure 3 2 10 Notes on PLL 6 MHz or 12 MHz external oscillator can be connected as an input reference clock f Xin When using the frequency synthesized clock function we recommend u
450. utput Version data output to 9th byte Acceptable Boot ROM area output function Address middle Address high Data output Data output Data output Data output to 259th byte Not acceptable Notes1 Shading indicates transfer from the internal flash memory microcomputer to a programmer All other data is transferred from a programmer to the in ternal flash memory microcomputer 2 SRD refers to status register data SRD1 refers to status register 1 data All commands can be accepted when the flash memory is totally blank Address low is Ao to A7 Address middle is As to A15 Address high is A16 to A23 Address high A16 to A23 are always 0016 A Rev 2 00 Oct15 2006 page 115 of 130 REJ09B0338 0200 2tENESAS HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION The contents of software commands are explained as follows 1 Transfer the FF16 command code with the 1st byte 2 Transfer addresses As to A15 and A16 to A23 with the 2nd and Page Read Command 3rd bytes respectively This command reads the specified page 256 bytes in the flash 3 From the 4th byte onward data Do to D7 for the page 256 memory sequentially one byte at a time Execute the page read bytes specified with addresses As to A23 will be output se command as explained here following quentially from the smallest address first synchronized with the fall of the clock As to A16 to
451. val Use the control program in the area except the built in flash memory for write to this bit 3 This bit is valid when the CPU rewrite mode select bit is 1 Set this bit 3 to 0 subsequently after setting bit 3 to 1 4 Use the control program in the area except the built in flash memory for write to this bit Fig 3 4 105 Structure of Flash memory control register Rev 2 00 Oct 15 2006 page 82 of 99 2RENESAS REJ09B0338 0200 APPENDIX 38K2 Group 3 5 Package outline 3 5 Package outline PLQP0064GA A JEITA Package Code RENESAS Code Previous Code MASS Typ P LQFP64 14x14 0 80 PLQP0064GA A 64P6U A 0 7g NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET b1 OI T Reference Dimension in Millimeters Terminal cross section Symbol Min Nom Max D 13 9 14 0 14 1 E 13 9 14 0 14 1 A2 1 4 Hp 15 8 16 0 16 2 He 15 8 16 0 16 2 A 17 At 0 0 1 0 2 _ lt 2 bp 0 32 0 37 0 42 l b 0 35 a j 4 c 0 09 0 145 0 20 iai L c 0 125 oe e 0 8 e 0 8 Detail F x 026 y 0 10 Zp 1 Ze 1 0 L 0 3 0 5 0 7 Li 1 0 Rev 2
452. value of m is 1 When bit 0 of the serial I O control register Address OFE016 is set to 1 a value of m is 4 Rev 2 00 Oct 15 2006 page 61 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 4 Serial I O Transmitting side Serial I O status register Address 2716 b7 bO SIOSTS leas Transmit buffer empty flag Confirm that the data has been transferred from Transmit buffer register to Transmit shift register e When this flag is 1 it is possible to write the next transmission data in to Transmit buffer register Transmit shift register shift completion flag Confirm completion of transmitting 1 byte data with this flag 1 Transmit shift completed Serial I O control register Address OFEO1e bO b7 siocon 1 ofoja ofofo BRG count source selection bit f Xin Serial I O synchronous clock selection bit BRG 16 Srov output enable bit Srov out disabled Transmit enable bit Transmit enabled Receive enable bit Receive disabled Serial I O mode selection bit Asynchronous serial I O UART Serial I O enable bit Serial I O enabled UART control register Address OFE116 b7 bO uartcon 1 olol Es Character length selection bit 8 bits Parity enable bit Parity checking disabled Stop bit length selection bit 2 stop bits Baud rate generator Address OFE216 b7 bO f Xin Transfer bit rate X 16 Xm When bit 0 of the Serial I O control
453. wnstream port 1 port error interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when an error occurs on a downstream port 1 0 can be set by software but 1 cannot be set PTRSM1 Downstream port 1 resume interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a resume signal on a downstream port 1 in the condition of HUB suspended or port suspended state 0 can be set by software but 1 cannot be set tPTCHG1 Downstream port 1 bus change detection interrupt bit 0 No interrupt request issued 1 Interrupt request issued This bit is set to 1 when detecting a bus change of a downstream port 1 in the condition of HUB suspended state It is also 1 in the internal clock halted 0 can be set by software but 1 cannot be set Not used Write 0 when writing 0 is read when reading Fig 96 Structure of DP1 interrupt source register Rev 2 00 Oct15 2006 page 65 of 130 REJ09B0338 0200 2RENESAS State remaining HARDWARE 38K2 Group FUNCTIONAL DESCRIPTION DP1 control register DP1CON address 002C16 At reset Bit symbol Bit name Function H W DSCONN1 Downs ream port 1 connect bit Disconnect PTCON1 interrupt enabled Connect PTDIS1 interrupt enabled
454. yn fusB 8 rato Selecon DIIS Divided by 6 fsyn fusa 6 Divided by 4 fsyn fusB 4 Not selected PLL operation mode selection bits Not multiplied fvco fxin Double fvco fxin X 2 Quadruple fvco fxn X 4 11 Multiplied by 8 fvco fxin X 8 7 PLL enable bit 0 Disabled 1 Enabled Fig 2 11 4 Structure of PLL control register I I Rev 2 00 Oct 15 2006 page 85 of 112 2RENESAS REJ09B0338 0200 APPLICATION 38K2 Group 2 11 Frequency synthesizer PLL 2 11 3 Functional description The frequency synthesizer generates the 48 MHz clock which is multiples of the external input reference f Xin and is needed for operating USB function When using the USB function set PLL enable bit of PLL control register PLLCON address OFF8ie to 1 enabled to send the 48 MHz PLL output clock fvco into USB function control unit Figure 2 11 5 shows the block diagram for the frequency synthesizer circuit Division circuit address OFF816 address 001016 Fig 2 11 5 Block diagram for frequency synthesizer circuit fvco PLL output clock fvco is generated by multiplying PLL input clock according to the contents of PLL operation mode selection bits bits 6 5 of PLLCON where fvco f Xin X n n value selected by PLL operation mode selection bits Set PLL operation mode selection bits so that fvco may be set to 48 MHz While the PLL enable bit is 0 disabled fvco retains L lev

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