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SECTION 12 ELECTRICAL AND THERMAL CHARACTERISTICS

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1. y y y 38 SNI BKA all ja SEE NOTE 1 Figure 12 5 Bus Arbitration Timing M68060 USER S MANUAL 1 For illustrative purposes a bus mastership hand over is shown after a locked bus cycle sequence which adds one extra clock period between the bus mastership hand over that would not occur for a bus mastership hand over after a non locked bus cycle 2 Address and attributes refer to the following signals EEE A31 A0 SIZ1 SIZO R W TT1 TTO TM2 TM0 TLN1 TLNO UPA1 UPAO CIOUT BS3 BS0 MOTOROLA Electrical and Thermal Characteristics N A A A BCLK sat ee ee CURE a 2 a a one oe ADDRESS amp H n pa ATTRIBUTES oa ry y g Te T 3 3 Te i ryt D31 D0 OUT WRITE f B OFE gt 7 gt e a BTT OUT gt lt gt SEE NOTE 1 TEE HI y pe y y NOTES 1 For illustrative purposes a bus mastership hand over is shown after a locked bus cycle sequence which adds one extra clock period between the bus mastership hand over that would not occur for a bus mastership hand over after a non locked bus cycle 2 Address and attributes refer to the fol
2. S MANUAL MOTOROLA Electrical and Thermal Characteristics 12 5 CLOCK INPUT SPECIFICATIONS Vcc 3 3 Voc 5 Num Characteristic 40 MHz pole 98 Mhz Unit Min Max Min Max Min Max Frequency of Operation 04 40 04 50 04 66 67 MHz 1 CLK Cycle Time 25 20 15 ns 2 CLK Rise Time 2 2 2 ns 3 CLK Fall Time 2 2 2 ns 4 CLK Duty Cycle Measured at 1 5 V 45 55 45 55 45 55 4a CLK Pulse Width High Measured at 1 5 V 11 25 13 75 9 11 6 75 8 25 ns 4b2 CLK Pulse Width Low Measured at 1 5 V 11 25 13 75 9 11 6 75 8 25 ns 55 CLKEN Input Setup 8 7 5 ns 56 CLKEN Input Hold 2 _ 2 2 ns NOTES 1 40 MHz available only for the MC68EC060 2 Specification value at maximum frequency of operation 3 CLK may be stopped LOW to conserve power 4 Minimum frequency is periodically sampled and not 100 tested CLK BCLK Figure 12 1 Clock Input Timing Diagram MOTOROLA M68060 USER S MANUAL 12 3 Electrical and Thermal Characteristics 12 6 OUTPUT AC TIMING SPECIFICATIONS Vcc 3 3 Voc 5 40 MHz 50 MHz 66 MHz Pad Pad Pad Pad Pad Pad Num Characteristic Starts Starts Starts Starts Starts Starts Unit at 5 5 V3 atVoc at5 5V3 atVoc at5 5V3 at Vec Min Max Min Max Min Max Min Max Min Ma
3. TT1 Invalid Hold 2 2 2 ns 45e BCLK to SNOOP Invalid Hold 2 2 2 ns 46 TS Valid to BCLK Setup 12 10 7 ns 47 BCLK to TS Invalid Hold 2 2 2 ns 49 MC68060 yt ce Bus Waste rship 3 3 3 ng 51 RSTI Valid to BCLK 3 2 1 ns 52 BCLK to RSTI Invalid hold 2 2 2 ns 53 Mode Select Setup to BCLK RSTI Asserted 12 10 7 ns 54 e to Mode Selects Invalid RSTI Assert 2 2 2 ag 64 CLA Valid to BCLK Setup 12 10 7 ns 65 BCLK to CLA Invalid Hold 2 2 2 ns NOTES 1 BCLK is not a pin signal name It is a virtual bus clock derived from the combination of CLK and CLKEN A BCLK rising edge coincides with a CLK in which CLKEN is asserted A BCLK falling edge is insignificant When a reference to BCLK is used to describe input timing it means that the specific input is recognized only on rising CLK edges in which CLKEN is asserted A timing reference to CLK means that the input is recognized at any rising CLK edge in cluding those edges in which CLKEN is negated 2 40 MHz available only for the MC68ECO060 12 6 M68060 USER S MANUAL MOTOROLA Electrical and Thermal Characteristics DRIVE TO 2 4 V CLK 1 5 V DRIVE TO A lt A 0 5 V B m VALID OUTPUTS 1 oren DRIVETO gt gt 2 4 V INPUTS 2 DRIVETO gt 0 5 V NOTES 1 This output timing is applicable to all parameters specified
4. not a pin signal name It is a virtual bus clock derived from the combination of CLK and CLKEN A BCLK rising edge coincides with a CLK in which CLKEN is asserted A BCLK falling edge is insignificant When a reference to BCLK is used to describe output timing it means that the specific output transitions only on rising CLK edges in which CLKEN is asserted A timing reference to CLK means that the output may transition off the rising CLK edge including those rising edges in which CLKEN is negated 5 When the processor drives these signals from a three stated condition use spec 11a or 40a Use the Pad Starts at 12 4 M68060 USER S MANUAL MOTOROLA Electrical and Thermal Characteristics Vec column or Pad Starts at 5 5 column as applicable Once these signals are driven subsequent transitions are defined by spec 11 or 40 The Pad Starts at 5 5 column is deleted from specs 11 and 40 since the processor drives up to the Vcc level only BR is never three stated by the processor and therefore spec 40a does not apply for BR 6 Pad Starts at 5 5 does not apply since these signals are always driven MOTOROLA M68060 USER S MANUAL 12 5 Electrical and Thermal Characteristics 12 7 INPUT AC TIMING SPECIFICATIONS Vec 3 3 Voc 5 Num Characteristic 40 MHz oe
5. ome Unit Min Max Min Max Min Max 15 Data In Valid to BCLK Setup 3 2 1 ns 16 BCLK to Data In Invalid Hold 2 2 2 ns 17 ead Followed by Write o Bt eee i ae ed ee I Se 22a TA Valid to BCLK Setup 12 10 7 ns 22b TEA Valid to BCLK Setup 12 10 7 ns 22c TCI Valid to BCLK Setup 12 10 7 ns 22d TB Valid to BCLK Setup 12 10 7 ns 22e TRA Valid to BCLK Setup 12 10 7 ns 23 RRT to TA TEA TCI TBI TRA Invalid 2 2 2 ne 24 AVEC Valid to BCLK Setup 12 10 7 ns 25 BCLK to AVEC Invalid Hold 2 2 2 ns 41a IBB Valid to BCLK Setup 12 10 7 ns 41b IBG Valid to BCLK Setup 12 10 7 ns 41c CDIS MDIS Valid to BCLK Setup 12 10 7 ns 41d IPL Valid to CLK Setup 3 2 1 ns 41e BTT Valid to BCLK Setup 12 _ 10 7 ns 41f BGR Valid to BCLK Setup 12 10 7 ns 42a BCLK to BB Invalid Hold 2 2 2 ns 42b BCLK to BG Invalid Hold 2 2 2 ns 42c BCLK to CDIS MDIS Invalid Hold 2 2 2 ns 42d CLK to IPLx Invalid Hold 2 7 2 2 ns 42e BCLK to BTT Invalid Hold 2 2 2 ns 42f BCLK to BGR Invalid Hold 2 2 2 ns 44a Address Valid to BCLK Setup 3 2 1 ns 44c TT1 Valid to BCLK Setup 12 10 7 ns 44e ISNOOP Valid to BCLK Setup 12 10 7 ns 45a BCLK to Address Invalid Hold 2 2 2 ns 45c BCLK to
6. 1 BCLK to BTT Valid 3 19 3 18 3 15 4 3 13 5 3 11 8 3 10 4 ns 62 BCLK to BTT Invalid Output Hold 3 3 3 3 3 3 ns 63 BCLK to BTT High Impedance 15 15 12 12 10 10 ns NOTES 1 40 MHz available only for the MC68EC060 2 Output timing is measured at the pin The specifications assume a capacitive load of 50 pF However a maximum load of 130 pF may be used at each pin Characterization data shows that at 130 pF loads output propagation delays are as follows 40 MHz Pad at Vcc multiply by prop delay by 1 4 40 MHz Pad at 5 5 multiply prop delay by 1 6 50 MHz Pad at Vcc multiply prop delay by 1 4 50 MHz Pad at 5 5 multiply prop delay by 1 6 66 MHz Pad at Voc multiply prop delay by 1 3 66 MHz pad at 5 5 multiply prop delay by 1 4 Exceeding the 130 pF limit on any pin might affect long term reliability and Motorola does not guarantee proper operation 3 When interfacing the processor to a system designed for 5 volt operation the Pad Starts at 5 5 column must be used when it is possible that the pin is at 5 5 volts when the processor begins to drive Once a pin is driven by the processor and is not three stated the Pad Starts at Vcc column may be used If the processor is in a system designed for 3 3 volt operation use the Pad Starts at Vcc column always This note not applicable to specs 11 11a 40 and 40a Refer to note 5 for these specs 4 BCLK is
7. 4 5 3 5 4 5 3 9 4 9 W Normal Mode Vec 3 465 V TA 0 C LPSTOP Mode CLK Running 300 300 300 300 300 300 300 mW Vec 3 465 V Ta 0 C 30 30 30 30 30 30 30 W LPSTOP Mode CLK Stopped Low i NOTES 1 Power dissipation values are preliminary and will likely be replaced with lower values upon further testing 2 Power dissipation assumes no DC load 3 Power dissipation figures are not applicable to the debug pipe control mode MOTOROLA M68060 USER S MANUAL 12 1 Electrical and Thermal Characteristics 12 4 DC ELECTRICAL SPECIFICATIONS Vec 3 3 Vpe 5 Characteristic Symbol Min Max Unit Input High Voltage VIH 2 5 5 V Input Low Voltage VIL GND 0 8 V Undershoot _ 0 8 V Overshoot 0 8 V Input Leakage Current AVEC CLK TT1 BG CDIS MDIS IPLx RSTI SNOOP CLKEN liL IIH 50 20 pA Hi Z Off State Leakage Current An BB CIOUT Dn LOCK LOCKE TDO ITSI 50 20 uA TIP SAS BTT BSx TMx TLNx TS TTx UPAx Signal Low Input Current Vi 0 8 V TMS TDI TRST liL 1 1 0 18 mA Signal eren VIH 2 0 V IH 0 94 0 16 MA Output High Voltage IOH 16 mA VOH 2 4 V Output Low Voltage IOL 16 mA VOL 0 5 V Capacitance Vin 0 V f 1 MHz CLK Only Cin 20 pF Capacitance Vin 0 V f 1 MHZ All Inputs Except CLK Cin 20 pF Capacitance is periodically sampled and not 100 tested 12 2 M68060 USER
8. SECTION 12 ELECTRICAL AND THERMAL CHARACTERISTICS The following paragraphs provide information on the maximum rating and thermal charac teristics for the MC68060 This section is subject to change For the most recent specifica tions contact the AESOP electronic bulletin board at 800 843 3451 or 512 891 3650 refer to C 5 4 AESOP Electronic Bulletin Board for connection information 12 1 MAXIMUM RATINGS Characteristic Symbol Value Unit This device contains protective circuitry againstdamageduetohighstaticvoltages Supply Voltage Voc 0 3 to 4 0 V or electrical fields however it is advised Input Voltage Vin 0 5 to Vcc 4 V that normal precautions be taken to avoid 7 F z application of any voltages higher that Maximum Operating Junction Temperature Ty 110 C maximum rated voltages to this high Minimum Operating Ambient Temperature Ta 0 C impedance circuit Reliability of operation Storage Temperature Range Ta 55 to 150 C is enhanced if unused inputs are tied to an stg appropriate logic voltage level e g either GND or Veo 12 2 THERMAL CHARACTERISTICS Description Symbol Value Unit Thermal Resistance Junction to Case PGA BIC 2 5 C W Thermal Resistance Junction to Case GQFP ajc 2 0 C W 12 3 POWER DISSIPATION Conditions MC68EC060 MC68LC060 MC68060 Unit 40 MHz 50 MHz 66 MHz 50 MHz 66 MHz 50 MHz 66 MHz Vec 3 465 V TA 0 C an oi 3 1 3 5
9. lowing signals TENES A31 A0 SIZ1 SIZO R W TT1 TTO TM2 TM0 TLN1 TLNO UPA1 UPAO CIOUT BS3 BS0 Figure 12 6 Bus Arbitration Timing Continued MOTOROLA M68060 USER S MANUAL 12 11 Electrical and Thermal Characteristics CLK BCLK ADDRESS amp ATTRIBUTES a T A3 A2 the zy O 1 gt aa NOTE Address and attributes refer to the following signals A31 A0 SIZ1 SIZO RW TT1 TTO TM2 TMO TLN1 TLNO UPA1 UPAO 12 12 Figure 12 7 CLA Timing M68060 USER S MANUAL MOTOROLA MOTOROLA Electrical and Thermal Characteristics CLK BCLK CLKEN A31 A0 TT1 IN SNOOP a SO oy Figure 12 8 Snoop Timing M68060 USER S MANUAL 12 13 Electrical and Thermal Characteristics PST4 PSTO 12 14 Figure 12 9 Other Signals Timing M68060 USER S MANUAL MOTOROLA
10. relative to the rising edge of the clock 2 This input timing is applicable to all parameters specified relative to the rising edge of the clock LEGEND A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification Figure 12 2 Drive Levels and Test Points for AC Specifications MOTOROLA M68060 USER S MANUAL 12 7 Electrical and Thermal Characteristics CLK BCLK D15 D0 in IPL2 IPLO Figure 12 3 12 8 1 a a eel O os ley ee ce PEC MODE SELECTS REGISTERED ON PREVIOUS BCLK EDGE Reset Configuration Timing M68060 USER S MANUAL MOTOROLA MOTOROLA Electrical and Thermal Characteristics CLK ADDRESS amp ATTRIBUTES o 5 D31 D0 in READ D31 D0 out WRITE o D gt ep gt I J a gt ZH 4m ds D lt m Ol 25 gt PRECONDITIONED DATA OR WRITE DATA FROM PREVIOUS BUS CYCLE USING EXTRA DATA WRITE HOLD MODE NOTE Address and attributes refer to the following signals A31 A0 SIZ1 SIZO RAW TT1 TTO TM2 TMO TLN1 TLNO UPA1 UPAO CIOUT BS3 BSO Figure 12 4 Read Write Timing M68060 USER S MANUAL 12 9 Electrical and Thermal Characteristics CLK BCLK ADDRESS amp ATTRIBUTES ih oq a D31 D0 OUT WRITE 12 10 k l w lyf 0 y y anit
11. x Min Max ESERE RATSEL Ta X xX 115 TTx UPAx BSx Valid signal pre 3 17 3 126 3 99 ns driven POLKI to Aadress SN TOCE three statej BCLK or CLK to Output Invalid _ _ _ _ _ _ 12 Output Hold 3 3 3 3 3 3 ns 13 BCLK to TS Valid 3 19 3 18 3 14 4 3 12 3 3 10 9 3 9 5 ns 14 BCLK to TIP Valid 3 19 3 18 3 15 4 3 1854 3 11 8 3 10 4 ns 18 BCLK to Data Out Valid 3 19 3 18 3 13 5 3 713 5 3 10 4 3 10 4 ns 19 HN to Data Out Invalid Output 3 3 3 3 z 3 3 SN He 21 BCLK to Data Out High Impedance 15 15 12 M 12 10 10 ns ESERE ANY SER Tie S x xX 38 TMx Tix UPAx BSx High Imped 15 15 pat 12 10 10 ns ance CLK to BB TIP 39 High Impedance 15 lt 15 w 12 12 10 10 ns BCLK to BR BB Valid Signal Pre 408 riven Sig Ar wy 3 126 3 99 ns BCLK to BB Valid signal from 40a lise cai ON 3 19 a Pts 3 154 3 135 3 11 8 3 10 4 ns 508 CLK to IPEND PSTx RSTO Valid 3 18 3 13 5 3 10 4 ns 57 BCLK to SAS Valid 3 19 3 18 3 15 4 3 113 5 3 111 8 3 10 4 ns 58 BCLK to SAS Invalid Output Hold 3 3 3 3 3 3 ns 59 BCLK to SAS High Impedance 15 15 12 12 10 10 ns 60 BCLK to TS Invalid Output Hold 3 3 3 3 3 3 ns 6

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