L4 Introduction and L4 API
Contents
1. PALcode amp C rudimentary 3 Potts Winwood UNSW completed SMP Version 2e 3 UNSW pistachio port Potts amp Winwood in progress gt StrongARM gt L4Ka hazelnut kernel 3 PowerPC pistachio LeVasser Karlsruhe partially complete gt A 64 pistachio Skoglund Karlsruhe partially complete gt SPARC planned UNSW cse UNSW COMP3231 2002 S1 W12 P2 L4 Implementation Example MIPS HISTORY gt Written by Kevin Elphinstone UNSW PhD student 1995 7 gt First 64 bit version of L4 gt Used in OS research projects at UNSW since 1996 gt Used in teaching at UNSW since 1997 3 New VM management multiple page size shared page tables new PT structure by Szmajda calypso not yet released cse UNSW COMP3231 2002 S1 W12 P3 L4 Implementation Example MIPS HISTORY gt Written by Kevin Elphinstone UNSW PhD student 1995 7 gt First 64 bit version of L4 gt Used in OS research projects at UNSW since 1996 gt Used in teaching at UNSW since 1997 3 New VM management multiple page size shared page tables new PT structure by Szmajda calypso not yet released STATISTICS KERNEL VERSION 79 gt 6k lines assembler source S gt 5k lines C source c gt 1 7k lines C and assembler header files h gt 80kB kernel text and static data gt 1MB kernel data mostly TCBs and page tables gt kernel footprint could be reduced to 200kB gt fast details later cse UN2. a page in the receiver s address space which will receive a mapping Hotspot address is also taken modulo send fpage size 3 Uniquely determines a page in the send fpage which will be mapped e In other words the smaller foage is mapped to from the larger one so that 3 it is aligned according to its size and gt it contains the hot spot cse UNSW COMP3231 2002 S1 W12 P46 Fpage Mapping Examples s 10 At b 5 h 2 x 2 offset rr ES E a b 0 h 2 x 24 offset cse UNSW COMP3231 2002 S1 W12 P47 Formal Fpage Mapping Rules e Sender specifies fpage as b s foage lb x 2 b 1 x 2 e Sender specifies hotspot h e Receiver specifies foage as b s foage fb x 25 Y 1 x 2 s s mapping is b x 2 gt b x 2 hot spot specification is not needed s lt s mapping Is b x 2 gt D163 8 hfst 1 5 9 s sender s fpage is aligned around hot spot s gt s mapping is bjs h s 1 5 0 6 gt b x 2 receiver s fpage is aligned around hot spot e Note Only h mod max 2 2 is relevant cse UNSW COMP3231 2002 S1 W12 P48 Fpage Notes e Page fault IPC manufactured by kernel specifies whole address space for receiver b 0 s 64 e Present MIPS implementation only uses smallest hardware page size s 12 but that is transparent to user 3 Changed in next release e Present MIPS implementation does not support granting 3 Changed in next release e An attempt to map over an existing ma
3. chief 3 chief can forward the message transparently Depth of hierarchy is limited 16 on MIPS Note Clans amp chiefs will be replaced by a better model cse UNSW COMP3231 2002 S1 W12 P11 INTER CLAN IPC O N TR f mi 2 k 2 Ne A cse UNSW COMP3231 2002 S1 W12 P12 Page Faults and Pagers e L4 maintains kernel page tables containing mappings explicitly established by user threads via IPC e On a page fault the kernel invokes the thread s pager by sending an IPC message to the pager on the faulter s behalf catching the pager s reply and continue the faulter Pager s is expected to send a mapping for the missing page ager page fault QA Qs L4 cse UNSW COMP3231 2002 S1 W12 P13 Exceptions and Excepters L4 MIPS EXCEPTION HANDLING Totally analogous to page faults e Each thread has an excepter e f a thread triggers an exception the kernel invokes the thread s excepter by sending an IPC message to the pager on the faulter s behalf catching the pager s reply and continue the faulter e The excepter may chose not to reply leaving the excepting thread blocked forever cse UNSW COMP3231 2002 S1 W12 P14 L4 1x86 EXCEPTION HANDLING Virtualisation of hardware e A thread installs its own interrupt vector using kernel emulated processor features The kernel handles some exceptions internally TLB miss system call cse UNSW COM
4. 2 Timeouts e IPC timeouts can be specified between 1s and 19h e page fault timeouts can be specified between 4us 1ms and 256s e actual timeout resolution is more coarse ims timeout resolution on MIPS e Data structure 14 types h 14 timeout t L4 IPC TIMEOUT e Utilities time h void 14 mips_encode_timeout dword_t msecs byte_t mant byte_t exp byte_t round dword_t 14 mips decode timeout byte_t mant byte_t exp cse UNSW COMP3231 2002 S1 W12 P43 Specification of Mappings e Source and destination specified as fpages e Sender specifies a set of foages which are to be mapped granted to the receiver e Receiver specifies the receive window gt kernel will not map outside this window cse UNSW COMP3231 2002 S1 W12 P44 Specification of Mappings e Source and destination specified as fpages e Sender specifies a set of foages which are to be mapped granted to the receiver e Receiver specifies the receive window gt kernel will not map outside this window FPAGE REPRESENTATION MIPS base 4096 5 Pal 8 T e Data structure 14 types h 14_fpage_t e MIPS kernel presently only supports 4kB pages e Bigger send fpages are handled by mapping individual pages cse UNSW COMP3231 2002 S1 W12 P44 Fpage Mapping e Send and receive fpages may be of different size gt page fault receive fpage covers full address space gt there may be several send fpage but only one receive fpage gt
5. 8 Address Spaces Address spaces are recursively constructed from mappings into other address spaces e A magic initial address space co maps physical memory e each address space pager can map portions of its own address Space into another cooperating address space cse UNSW COMP3231 2002 S1 W12 P9 Address Spaces Address spaces are recursively constructed from mappings into other address spaces e A magic initial address space co maps physical memory e each address space pager can map portions of its own address Space into another cooperating address space DONE WITH THREE MAPPING PRIMITIVES Map a page to receiver sender retains page Grant a page to receiver sender loses page Flush undoes a Map removes page from receiver cse UNSW COMP3231 2002 S1 W12 P9 Granting userA ot user X f J Y map std pager cse UNSW COMP3231 2002 S1 W12 P10 Clans amp Chiefs Clans amp Chiefs are a security mechanism for e task control define ownership of tasks gt a task creating another task becomes the chief of that task gt the set of tasks created by a chief is that chief s clan gt task can be killed only directly by its chief indirectly when its chief is killed e communication control restrict the flow of messages gt intra clan messages are delivered directly 3 inter clan messages are redirected to
6. P3231 2002 S1 W12 P15 Preemptions and Preempters e Basic idea 3 treat a preemptions like a page fault i e a time faults gt have a preempter as a time fault handler gt preempter is invoked via IPC e Model is at present not matured and preemipers are not implemented in any L4 version cse UNSW COMP3231 2002 S1 W12 P16 Interrupts and Interrupt Handlers e Each hardware interrupt is modelled as a virtual hardware thread e At most one user level interrupt handler thread is associated with each hardware interrupt e If an interrupt occurs the kernel generates an IPC from the interrupt thread to the interrupt handler e The interrupt handler is in general part of a device driver gt It will need access to device registers 3 Done via a special mapping protocol of the root pager Kernel handles some interrupts internally e g timer cse UNSW COMP3231 2002 S1 W12 P17 Device Interfaces e Devices are controlled via special device registers typically status register to obtain device status control register to send commands to device status and control registers are at the same address data register s to pass data command parameters e Number of registers is normally small data and parameter buffers are passed in memory address specified in data registers e Device registers are either memory mapped or accessed via O instructions e Devices access only physical memory i e bypass the MMU c
7. SW COMP3231 2002 S1 W12 P3 Main L4 Abstractions threads execution abstraction and UIDs tasks address spaces and resources IPC message based communication incl VM mappings flexpages VM page abstraction superpages clans and chiefs task hierarchy for arbitrary security models pagers excepters preempters interrupt handlers exceptions e Mostly strict separation of 3 mechanisms provided by kernel and gt policy implemented by user level servers e Minimality achieved by orthogonality of mechanisms cse UNSW COMP3231 2002 S1 W12 P4 L4 Threads e A thread is the basic active entity execution and scheduling e Threads communicate via message passing IPC e Each thread has 3 a register set IP SP user visible registers processor state gt an associated task address space 3 a page fault handler pager this is a thread which receives page faults via IPC gt an exception handler dependent on architecture this is a thread which receives exceptions via IPC gt preempters not implemented tread which receives preemption messages gt scheduling parameters priority time slice cse UNSW COMP3231 2002 S1 W12 P5 Tasks e A task essentially provides an address space plus a clan boundary e An active task contains one or more active threads e The number of threads in a task Is fixed 128 on R4k 3 The full set of 128 threads is created with the task gt all but one are inactive 1 e
8. The L4 Microkernel gt Developed and implemented on ix86 by Jochen Liedtke GMD Germany 1992 95 Version 2 gt Successor of Eumel 1979 and L3 1987 3 Ongoing development by Liedtke at IBM Watson Research Center 1997 99 Uni Karlsruhe 1999 L4Ka Version X 2 3 Implementations at Dresden Uni of Technology and UNSW cse UNSW COMP3231 2002 S1 W12 P1 The L4 Microkernel gt Developed and implemented on ix86 by Jochen Liedtke GMD Germany 1992 95 Version 2 gt Successor of Eumel 1979 and L3 1987 3 Ongoing development by Liedtke at IBM Watson Research Center 1997 99 Uni Karlsruhe 1999 L4Ka Version X 2 3 Implementations at Dresden Uni of Technology and UNSW FEATURES gt system calls Version 2 gt recursive address spaces gt user level page fault handlers gt user level device drivers user level scheduling gt real time capable sort of cse UNSW COMP3231 2002 S1 W12 P1 qe L4 Implementations gt Liedtke s kernel 100 assembler Versions 1 X 3 Hohmut Dresden called Fiasco C Version 2e Dannowski L4Ka hazelnut kernel C Version X 3 L4Ka Team pistachio kernel C portable Version X 2 gt MIPS R4x00 3 Elphinstone UNSW 64 bit assembler amp C Version 2e 3 Calypso kernel by Chris Szmajda VM management 3 UNSW pistachio port Potts amp Winwood in progress 3 Alpha gt Schonberg Dresden 96 64 bit
9. ceives message 3 parent replies by deceiving send pretending to be oo It s a matter of convention cse UNSW COMP3231 2002 S1 W12 P69 References AH98 Alan Au and Gernot Heiser L4 User Manual School Comp Sci amp Engin University NSW Sydney 2052 Australia Jan 1998 UNSW CSE TR 9801 Latest version available from http www cse unsw edu au disy L4 EHL97 Kevin Elphinstone Gernot Heiser and Jochen Liedtke L4 Reference Manual MIPS R4x00 School Comp Sci amp Engin University NSW Sydney 2052 Australia Dec 1997 UNSW CSE TR 9709 Latest version available from http www cse unsw edu au disy L4 cse UNSW COMP3231 2002 S1 W12 P70
10. d in registers e remainder possibly empty is passed as a by value string Operation will not block longer than indicated by timeout e can be 0 or oo cse UNSW COMP3231 2002 S1 W12 P29 Example Receive Call int 4_mips_ipc_receive I4 threadid t src ID of sender const void rcv_msg msg descriptor I4 ipc reg msg t rcv reg initial part of msg 14_timeout_t timeout timeout spec 14_msgdope_t result result code e Will only accept message from specified sender e result contains result code and description of received message i e in line vs out of line data cse UNSW COMP3231 2002 S1 W12 P30 L4 IPC Messages TWO KINDS OF MESSAGE PARAMETERS snd_reg or rcv_reg in register short part of message first 8 words on MIPS R4k snd_msg or rcv_msg in memory long part of message cse UNSW COMP3231 2002 S1 W12 P31 L4 IPC Messages TWO KINDS OF MESSAGE PARAMETERS snd_reg or rcv_reg in register short part of message first 8 words on MIPS R4k snd_msg or rcv_msg in memory long part of message MESSAGES CONTAIN 3 KINDS OF DATA by value in line data directly in registers or message buffer by value string out of line data message buffer contains pointer to data by reference fpages describing mappings cse UNSW COMP3231 2002 S1 W12 P31 Register message format e Registers s0 s7 on MIPS R4k contain some possibly zero 2 word foage descrip
11. eate an active one e Task is active iff it has a valid pager e task_new deletes an active or inactive task and creates a new one with task same number but different version hence different ID e New task can be gt active syscall parameters specify start address stack pointer pager exception handler scheduling priority initially runs single thread Ithread 0 gt inactive does not consume any resources can optionally be donated to new chief cse UNSW COMP3231 2002 S1 W12 P52 Details of task_new Operation e Donation of inactive tasks allows passing of creation right e Deleting an inactive task does not affect version number e Deleting a task implicitly deletes all tasks in its clan or subclans e Only a task s chief can execute a task new syscall for it e Exception MIPS Anyone can call task new for a task which has never been active 3 Means of allocating task creation rights at system startup cse UNSW COMP3231 2002 S1 W12 P53 Thread Manipulation Ithread ex regs e Task has a fixed number 128 of threads initially all but one inactive e Thread is activated by supplying a valid IP and SP gt Thread inherits pager excepter from activating thread e Ithread ex regs sets new and returns previous values for instruction pointer IP stack pointer SP exception handler pager e Supplying invalid value 1 to any of those retains original setting Can be used for performing a user
12. ence Manual EHL97 defines the L4 ABI gt making maximal use of registers gt assembler interface gt very architecture specific e 1ib14 provides a C API 3 still somewhat architecture specific e g size of register message gt interface is defined in header files in http cs9242 include L4 include 14 gt documented in Unix man pages http cs9242 man L4 man man2 e Usage is explained in the L4 User Manual AH98 cse UNSW COMP3231 2002 S1 W12 P24 L4 System Calls O ipe gt Message passing combining send and receive fpage unmap gt Revoke mappings id_nearest gt Determination own and target TID 4 task new gt Create delete task address space lthread ex regs 3 Create manipulate thread thread switch gt Explicit time slice donation D thread schedule gt Setting enquiring scheduling parameters cse UNSW COMP3231 2002 S1 W12 P25 IPC System Call Overview Variants of syscall accessible via separate C bindings CLIENT FUNCTIONS gt send send a message blocking to a specific thread receive closed receive from specific sender includes sleeping if specify invalid sender 3 wait open receive from any thread incl interrupt gt call send amp wait for reply usual RPC operation gt reply and wait send amp wait for any message typical server operation gt send deceiving like send but substitut
13. foage may need to be mapped at different addresses in sender and receiver e g on page fault cse UNSW COMP3231 2002 S1 W12 P45 Fpage Mapping e Send and receive fpages may be of different size gt page fault receive fpage covers full address space gt there may be several send fpage but only one receive fpage 3 foage may need to be mapped at different addresses in sender and receiver e g on page fault e Need ability to specify where an fpage gets mapped e Send fpage is accompanied with a hotspot address send base gt Determines mapping address if receive fpage is big enough cse UNSW COMP3231 2002 S1 W12 P45 Fpage Mapping e Send and receive fpages may be of different size gt page fault receive fpage covers full address space gt there may be several send foage but only one receive fpage 3 foage may need to be mapped at different addresses in sender and receiver e g on page fault e Need ability to specify where an fpage gets mapped e Send fpage is accompanied with a hotspot address send base gt Determines mapping address if receive fpage is big enough SEND FPAGE INFORMATION w1 snd fpage 62 wg wO snd base a w write permission bit unset fpage will be mapped read only g grant bit set gt fpage will be granted cse UNSW COMP3231 2002 S1 W12 P45 Fpage Mapping Rules e Rules for disambiguating foage mapping Hotspot address is taken modulo receive fpage size 3 Uniquely determines
14. ill happily destroy running tasks threads if requested to do so gt gt lt is up to the user code i e OS server to manage them properly cse UNSW COMP3231 2002 S1 W12 P57 L4 Scheduling e Every L4 thread has a timeslice length and a priority e These are 3 inherited from parent gt changeable via thread schedule e L4 implements hard priorities gt scheduler will always select highest priority runable thread gt within priority scheduler uses round robin cse UNSW COMP3231 2002 S1 W12 P58 User level scheduling in L4 Two ways to control scheduling e Can use controller thread with high MCP gt uses thread schedule to manipulate other threads 3 controlled threads run with zero MCP e Can use user level scheduler thread running at highest priority gt L4 will always schedule this scheduler thread gt Scheduler thread uses thread switch to give a time slice to some thread e Preempters unimplemented would be used to inform scheduler of premptions Obvioulsy combinations of these are possible cse UNSW COMP3231 2002 S1 W12 P59 The Root Pager oy go Is the initial address space gy contains a mapping for each available frame of physical memory oo IS also a pager and chief for original servers tasks contained in boot image and marked as automatically run gy maps any frame writable to the first task requesting it and ignores any further requests for the same frame Pages can be reques
15. in the send message descriptor and gt register data starts with a valid foage descriptor gt Fpage processing stops if invalid foage descriptor found gt Fpages are only recognised in register part of message MIPS gt all data is copied to receive incl foage descriptors e Out of line data strings 3 described by dopes immediately after in line data cse UNSW COMP3231 2002 S1 W12 P35 Message format Logical snd_msg msg hdr fpages 0 in line string string string cse UNSW COMP3231 2002 S1 W12 P36 Message format Physical registers fpages in line part 1 snd_msg msg hdr in line part 2 string dopes gt string string string cse UNSW COMP3231 2002 S1 W12 P37 Message header format DATA STRUCTURE L4 TYPES H L4_MSGHDR_T fpage res w0 receive fpage describes how to map any incoming fpages w1 message size dope specifies the total buffer space available words size of buffer in words total for foages and in line data strings number of string dopes w2 message send dope buffer space used on sending e buffer size used words and string dopes used strings must be less than or equal specifications of message size dope e Note specified buffer message size is in addition to registers cse UNSW COMP3231 2002 S1 W12 P38 String dope format DATA STRUCTURE L4 TYPES H L4_STRDOPE_T w3 TCV string 6s rcv st
16. ing sender ID gt reply deceiving and wait similar cse UNSW COMP3231 2002 S1 W12 P26 C BINDINGS FOR CHIEFS e Support transparent forwarding by chief chief send identical to send deceiving chief wait like wait but returns intended destination chief receive like receive but returns intended destination chief call like call substitutes sender amp returns intended destination chief_reply_and_wait like reply_deceiving_and_wait returns intended destination cse UNSW COMP3231 2002 S1 W12 P27 Deceiving IPC CLANS amp CHIEFS MECHANISM Supported by deceiving e If deceit bit is set by sender L4 will deliver the message with sender specified virtual sender ID e The receiver is alerted by the deceit bit e Deceiving only works if direction preserving real sender must be along the redirection chain from the virtual sender to the receiver i e x message goes out of clan amp virtual sender ID is within clan or x message goes to subclan amp virtual sender ID is outside clan e Supports transparent inter clan IPC interception cse UNSW COMP3231 2002 S1 W12 P28 Example Send Call int 4_mips_ipc_send l4_threadid_t dest ID of dest thread const void snd_msg msg descriptor I4 ipc reg msg t snd reg initial part of msg 14 timeout t timeout timeout spec 14_msgdope t result result code Message is divided into two paris e initial part snd_reg 64 bytes on R4k is passe
17. level thread switch exchanging registers of running thread with saved ones gt saving thread s context by supplying only invalid parameters e Call terminates any pending or ongoing IPC e Note A thread cannot be deleted only blocked cse UNSW COMP3231 2002 S1 W12 P54 Release CPU thread_switch The calling thread voluntarily releases the CPU e May specify another thread to continue immediately time slice donation gt Destination thread gets remaining time slice for free gt Normal scheduling taken at expiry e May yield CPU by not specifying valid destination thread gt Remaining time thread is forfeit gt Normal scheduling action taken immediately possibly re scheduling caller thread cse UNSW COMP3231 2002 S1 W12 P55 Scheduling Parameters thread_schedule e Allows setting inquiring the priority and timeslice length of a thread e Also returns thread state running IPC ing dead gt Partially implemented on MIPS e Scheduling parameters can only be changed for a thread running at a lower priority than the caller s maximum controlled priority MCP e If setting priority cannot exceed caller s MCP e MCP is task attribute specified in task create system call child MCP cannot exceed parent s cse UNSW COMP3231 2002 S1 W12 P56 Task and thread management e Management of task and thread IDs is left to user level code e 4Stask create and lthread_ex_regs system calls w
18. ny time gt Note only tasks in os clan can IPC directly to oo e Device mappings within RAM are used for DMA able memory e Present MIPS o does not check whether address really refers to a device e Cacheability attribute is passed on when mapping to subtasks gt supports device drivers not directly in cs clan cse UNSW COMP3231 2002 S1 W12 P63 Bootstrap MIPS Specific Boot image header L4 Initial server other stuff On boot Load image into RAM L4 bootstrap starts oo as first task in kernel mode oo Starts all initial servers as user tasks registering as their pager exception handler and chief Initial servers are marked as such in boot image set up by DIT downloadable image tool cse UNSW COMP3231 2002 S1 W12 P64 OS Startup Code Register itself for all free interrupts Grab all memory from oo without interfering with other initial tasks Set up data structures for memory management gt reserved space for own tables 3 free lists frame table page tables for client memory Grab all inactive tasks Start device drivers maybe separate initial server tasks gt Drivers map device pages Start other server threads if multi server implementation Set up data structures for services TCBs file system Set up task management O Start up initial user task s Possibly donate tasks to subtasks cse UNSW COMP3231 2002 S1 W12 P65 De
19. p parameter buffer write device registers or queue request if device busy gt reply to user if asynchronous cse UNSW COMP3231 2002 S1 W12 P20 L4 device driver e Top half must be fast to avoid missing interrupis gt runs at high priority gt generally runs with interrupts disabled does minimal amount of work 3 longer tasks left to to top half copying buffers replying to user e Concurrency control required between top and bottom half e Top half must not be blocked by bottom half cse UNSW COMP3231 2002 S1 W12 P21 r devices tty SCSI E E Sr Ser ey cse UNSW L4 Based OS Design Client client excpt syscall sub handler handler system L4 pager r ooo ES SS e SS E COMP3231 2002 S1 W12 P22 OS Structure e OS server is chief of client processes e Client s system calls are library stubs performing RPC to OS server e OS may consist of many server threads in same or separate tasks e OS server may redirect client requests to other servers gt within OS server task gt outside OS server task e Clans amp chiefs mechanism gt prevents direct client access to separate servers tasks gt supports easy redirection of system call RPC cse UNSW COMP3231 2002 S1 W12 P23 The L4 Interface e The L4 Refer
20. pping is silently ignored except if the mappings only differ in the write permission This is a bug in al present L4 implementations gt Changed in next release cse UNSW COMP3231 2002 S1 W12 P49 Revoke Mappings fpage_unmap e Unmaps pages directly or indirectly mapped from caller s address space e Unmapping may be gt partial revert to read only remap or 3 complete pages vanish from other address spaces flush e The fpage argument defines a region in the caller s address space e All pages within that region which are mapped into other address Spaces will be remapped or flushed e Mappings in the caller s address space are 3 unaffected other or 3 also unmapped all cse UNSW COMP3231 2002 S1 W12 P50 Obtain Thread IDs id_nearest System Call e Returns the ID of the thread which would really receive a message sent to a specified destination thread e Also returns a type field indicating the direction of the IPC with respect to the clan boundary e f destination is inside own clan returns destination thread ID type same outside own clan returns own chief s ID type outer in subclan of own clan returns ID of chief within own clan of subclan type inner nil returns own thread ID cse UNSW COMP3231 2002 S1 W12 P51 Task Creation and Deletion task_new e System has fixed number of tasks initially all inactive e Inactive task is essentially a capability to cr
21. ring SIZE 64 N snd StriNg 64 snd string S Ze 64 w0 size in bytes of string to be sent w1 address of string to be sent w2 size in bytes of buffer for string to be received w3 address of buffer for string to be received O a cse UNSW COMP3231 2002 S1 W12 P39 IPC Result Status MESSAGE DOPE returns status word 0 32 words str CC words size in words of in line data received e in addition to registers str number of strings received e in buffers pointed to by string dopes e dopes contained in message header cc condition code cse UNSW COMP3231 2002 S1 W12 P40 IPC Result Condition Code CONDITION CODE FORMAT Cia ijra ec error code ec 0 IPC failed gt result codes in manual gt frequent reason Cut message receivers buffer was too small not enough strings etc gt Note this value is also delivered as C return value m map bit m 1 gt fpages were received Other bits are for clans and chiefs consult the manual cse UNSW COMP3231 2002 S1 W12 P41 IPC Timeout Specifications e An IPC operation specifies 4 timeout values M er receive timeout is m 41 us Ms es send timeout is m 4 us pr receive page fault timeout is 4 us ps send page fault timeout is 4 s us gt e 0 or p 0 mean oso i e no timeout gt m 0 amp e gt 0 mean 0 i e never block 3 p 15 means O i e fail on page fault cse UNSW COMP3231 2002 S1 W12 P4
22. se UNSW COMP3231 2002 S1 W12 P18 Device Driver e Interface between hardware device controller and OS e Processes OS device requests and controls device by writing to data amp command registers e Monitors device by reading status amp data registers and handling device interrupts e Transfers data between OS buffers and device cse UNSW COMP3231 2002 S1 W12 P19 L4 device driver e Runs at user level e Has mappings for device registers MIPS and physical memory e Typically consists of top half and bottom half cse UNSW COMP3231 2002 S1 W12 P20 L4 device driver e Runs at user level e Has mappings for device registers MIPS and physical memory e Typically consists of top half and bottom half TOP HALF HANDLER processes device interrupts gt receive L4 interrupt IPC gt check success status register gt make data available copying or mapping 3 initiate next request if one 3 notify reply to user IPC cse UNSW COMP3231 2002 S1 W12 P20 L4 device driver e Runs at user level e Has mappings for device registers MIPS and physical memory e Typically consists of top half and bottom half TOP HALF HANDLER processes device interrupts gt receive L4 interrupt IPC gt check success status register gt make data available copying or mapping 3 initiate next request if one 3 notify reply to user IPC BOTTOM HALF HANDLER processes user requests 3 initiate I O set u
23. ted implicitly by touching or explicitly by RPC according to paging protocol 3 First job of OS personality is to request all available frames gt Server has then control over memory Some special pages are used for kernel information page and memory mapping devices On MIPS o runs in kernel space for no good reason cse UNSW COMP3231 2002 S1 W12 P60 Kernel information page e Lives in kernel reserved space e Mapped by oo upon requesting a particular invalid page address 3 on MIPS e Mapped read only to anyone requesting it at any time e Contains information about L4 and machine gt L4 version etc gt size of physical memory gt size and address of L4 reserved memory gt millisecond real time clock gt address of DIT header page MIPS cse UNSW COMP3231 2002 S1 W12 P61 DIT header page MIPS e Lives in kernel reserved space e Address is contained in kernel info page e Mapped read only to anyone requesting it at any time e Contains for each file in the boot image 3 name gt size and location in physical memory 3 entrypoint address zero if not executable image 3 flag indicating whether it s to be started by oo cse UNSW COMP3231 2002 S1 W12 P62 Devices MIPS e Are memory mapped to addresses outside RAM range e Device pages are mapped upon requesting a particular invalid page with page address as second parameter e Mapped writable and uncacheable to anyone requesting it at a
24. they do nothing and consume no resources gt further threads can be activated via a system call lthread_ex_regs gt Model will change in future versions e Upon system initialisation the full set of tasks 2048 on R4k is created but in an nactive state e A task has a chief parent owner gt Chiefs will vanish in future versions cse UNSW COMP3231 2002 S1 W12 P6 IPC e Message passing IPC provides communication between threads e All IPC is gt synchronous i e blocking and gt unbuffered This is key to high IPC performance e IPC requires an agreement between sender and receiver i e receiver must be expecting IPC must provide buffers etc gt supports in line and out of line by value data gt supports map and grant VM operations for by reference data e Blocking can be limited by timeouts Note the interaction between IPC and threads e threads need efficient IPC to talk e blocking IPC needs low cost threads to be efficient cse UNSW COMP3231 2002 S1 W12 P7 Flexpages e Describe virtual memory regions for use in mapping operations e Generalisation of pages by abstracting over page size e Usually called fpages PROPERTIES gt size 2 gt hardware page size 3 aligned to 2 gt kernel should try to map whole fpage as a single super page 3 partially populated foages an fpage refers to all mapped pages within the region designated by it cse UNSW COMP3231 2002 S1 W12 P
25. tors followed by data foage descriptors by value data presence of fpages is indicated by the m bit in snd_msg or rcv_msg fpage processing stops if invalid foage descriptor found remainder or all of register data is simply copied e Size is specified in 14 ipc h 14_ipc_reg_msg_t cse UNSW COMP3231 2002 S1 W12 P32 Send message descriptor format FORMAT OF snd msg PARAMETER gt snd msg 4 message descriptor address 0 short message no memory data 0 address of message descriptor m mapping bit 0 by value send operation no mappings 0 by reference mapping send operation 3 beginning of message string contains foage descriptors 3 d deceiving bit lie about sender turned on automatically by using deceiving send binding cse UNSW COMP3231 2002 S1 W12 P33 Receive message descriptor format MIPS FORMAT OF msg rcv PARAMETER m mapping bit m Q rec msg 0 receive register data only no mappings rec msgz 0 message descriptor address gt first 8 words of message are in registers gt rest as specified in message buffer 3 may accept mappings if receive foage option is used m 1 fpage receive operation gt rcv msg is not a pointer contains the foage describing the mapping window COMP3231 2002 S1 W12 P34 cse UNSW Memory message format foage descriptors by value data string dopes e Fpages are expected only if 3 the m bit is set
26. vice drivers e maps device registers device mapping from oo e maps uncached RAM device mapping from ao e sets up interrupt handler thread for device e initialises device by writing to device registers e process user requests and device interrupts cse UNSW COMP3231 2002 S1 W12 P66 Implication of server architecture OS Is just a user level L4 task OS can be interrupted amp unscheduled gt gt Need concurrency control on all OS data structures cse UNSW COMP3231 2002 S1 W12 P67 What to run first OS always gt handles a client request or gt waits for a client request Q Where does it get the clients from cse UNSW COMP3231 2002 51 W12 P68 What to run first OS always gt handles a client request or gt waits for a client request Q Where does it get the clients from A define your own startup convention e g e OS starts up first non initial server executable in boot image e First non executable item in boot image contains list of initial client tasks e OS looks for program of a certain name in boot image cse UNSW COMP3231 2002 S1 W12 P68 Where s the OS How does a client know where to send syscall RPCs First action of new task could be an open receive parent sends message thereby disclosing its identity gt hide in startup code crt0 Client could send all system call RPCs to oo 3 clans 4 chiefs mechanism ensures that parent re
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