AVM16 Manual V2.0 - W-IE-NE
Contents
1. With Preamble of channel beyond q_threshold with Pileup Verbose Mode Pulse Integral Code Block Verbose Mode Entry Code Block Verbose Mode Single Pulse Code Block Pulse Integral Decoding 0x20 Verbose Mode Pileup Pulse Code Block Pulse Integral Decoding 0x20 of Pileup Pulse Finally the sum of all individual EVBLN shall agree with the d_length FIFO byte count read out Rarely Pulse Integral Decoding can be transmitted before the Verbose Pulse Code Block is ready W IE NE R Plein amp Baus GmbH 29 www wiener d com Industrie elektronik WIENER M F elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 4 4 3 Raw Data Frame While the Verbose Data Frame is changing the data frame format globally as described in the last paragraph the Raw Data Frame can be masked out by the cha_raw register individually Hence in principal all channels can be read out in raw data frame mode or only a subset of them In this way a DAQ expert can switch on and off simply a channel of his her choice for monitoring purposes during run time This eases control of bigger readout systems from time to time without halting it This switching is possible within compressed or verbose running DAQ systems If selected cha_raw register the whole raw data record expands in its decoding structure 4 3 1 maybe localized directly after the last not selected channel block or either behind the data frame header For example to check f2. Werk f r e Industrie elektronik WIENER fe Ad Plein amp Baus Elektronik M Regelungs A Phoenix Mecano Company W IE NE R AVM16 AVX16 16 channel ADC 160 MHz with features extraction User s Manual V2 0 W IE NE R Plein amp Baus GmbH 1 www wiener d com Board Rev 1 3 Firmware Rev 2 1 November 11 2011 General Remarks The only purpose of this manual is a description of the product It must not be interpreted as a declaration of conformity for this product including the product and software W Ie Ne R revises this product and manual without notice Differences between the description in manual and the product are possible W Ie Ne R excludes completely any liability for loss of profits loss of business loss of use or data interrupt of business or for indirect special incidental or consequential damages of any kind even if W Ie Ne R has been advises of the possibility of such damages arising from any defect or error in this manual or product Any use of the product which may influence health of human beings requires the express written permission of W Ie Ne R Products mentioned in this manual are mentioned for identification purposes only Product names appearing in this manual may or may not be registered trademarks or copyrights of their respective companies No part of this product including the product and the software may be reproduced transmitted transcribed stored in a retrieval sy
3. If baseline upsets or trips from the detector side may occur from time to time these can be tackled safely by the VME readout software only in verbose mode If they can be completely ruled out compressed mode can be selected for highest trigger rates W IE NE R Plein amp Baus GmbH 7 www wiener d com Industrie elektronik WIENER M F elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik Data from within the boundaries of the window control called search window are transferred to the extended Waveform Feature Extraction section or if raw data is additionally requested to the readout FIFO The Waveform Feature Extraction continuously searches in this window for physical pulses in a kind of pipeline algorithm If found a detailed list of parameters is extracted Figure 3 shows such a list in case of a pile up event Those extracted values are made completely available via VME in verbose readout mode or in raw mode for any selected channel An important parameter for further calculations is the self extrapolated pulse start time Pz left dashed line For a detailed generation see 1 2 8 Finally when input pulses are bigger than a preset size their pulse integrals Pq are calculated precisely during run time The integration can be installed in two ways Within an individually fixed time window after Pz or in a window starting at Pz but with a floating end In the latter case the integration stops wh
4. with internal 160MHz clock and external NIM trigger Additionally every activated channel can be installed as internal trigger source or ed featured trigger The current channel baseline and noise are frequently recalculated They are only updated within the pulse free time periods Extended data transfer cycles via VME allow for up to 64 bit block moves MBLT An additional hardware byte swapper can be activated to ease readout transfer for little endian machines INTEL while default is big endian Freescale Motorola Further extensions like VME Renaissance 2eVME 2eSST are physically possible as well as the optional VXS readout Both are physically connected for possible customized implementations in the future further firmware upgrades possible Further hardware extensions may not be ruled out and may be proven on valued costumer request In this way a readout system with 480 BGO channel and of two multi wire proportional chambers MWPC has been designed As used within current backplane xTCA physics extensions W IE NE R Plein amp Baus GmbH 5 www wiener d com Nuklear elektronik WIENER fay Cd Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 1 2 Functional description 1 2 1 Block diagram The AVM16 AVX16 modules contain four quad channel ADC blocks a VME VXS control part and a clock and synchronization system see figure 1 XC3S1000 Data Bus P1 VME BUS
5. detector with a minimum useful rise time of 20 25ns and fall times lower than 3ps It extracts all times amplitudes and integrals of physical interest for any CR RC or Gaussian shaped pulses from a detector The feature extraction even works up to a pile up factor of two or more which means even searches for the inter pulse minimum and a following maximum are possible Due to a complex on board triggering architecture up to 16 modules can be synchronized within one VME crate via daisy chaining on the frontpanel bus on the crate level while other crates can be point to point connected via the P2 backplane connector to form trees of synchronized crates The synchronization between the modules is done via modern multipoint transceivers compliant to the TIA EIA 899 M LVDS standard on the front or backplane buses with flat cables to be terminated on both sides internal jumpers are foreseen for the frontpanel bus Overall trigger synchronization is guaranteed by high resolution system timers and a wide timestamp register An overall busy logic is working on single eventbase filling a multi event buffer FIFO as long as one or more modules flag for an internal readout FIFO overflow The finally achievable trigger rate depends strongly on the analyzed window size the verbosity level of the transmitted data raw verbose compressed and the chosen VME transaction strategy For laboratory purposes one AVM16 AVX16 can be simply used as single master SM
6. if a corresponding new manual version exists if needed Then the following instruction shows up how an hardware expert may reconfigure the board to the new firmware version with the new mcs file downloaded together with an existing XILINX JTAG download cable and the existing IMPACT boundary scan software Else generally W IE NE R updates the boards firmware on costumer request gt ISE iMPACT 0 61xd Boundary Scan File Edit View Operations Output Debug Window Help 030 8 GH aT AW IMPACT Flows O amp X Right click device to select operations a Boundary Scan fSF BER SystemACE basa Create PROM File PROM File Formatter WebTalk Data TOi xcf32p xcSvlxS t xc3s1500 xc3s1500 xc3s1500 xc3s1500 bypass bypass bypass bypass bypass bypass Figure 12 The AVM 16 AVX 16 FPGA in the JTAG Boundary Chain How to program the PROM 1 Connect the Plattform Cable USB to the dedicated JTAG pins 2 Execute the impact exe It can be done from run dialog box or ISE program 3 In the iMPACT program run the Boundary Scan and then initialize chain from toolbox A chain with 6 devices has to be appeared Figure 12 4 Right click on the xcf32p for a Assign New Configuration File e g AVMI6 v 2 1 mcs b Set Programming Properties The following property values must be checked b1 Venfy b2 Design Specific Erase Before Programming b3 Load FPGA b4 During Configuratio
7. should be 0 negative logic The base address is divided in two parts The gross range is set with SW1 6 5 and can be 0x0000000 0x40000000 0x80000000 or 0xC0000000 The fine range is set with SW 4 1 and can be from 0x000000 to 0x1E0000 with 0x20000 steps The real base address is the sum of the two ranges For example if only the switch 1 is set to off the selected address range will be 0x00020000 to 0x0003FFFC The entire address range of the card is 0x20000 or 128kB Of these ranges the first kB 0x000 to 0x7FC is determined for module registers and the rest 0x800 to OXIFFFC is determined for the block data transferred from the FIFO This means with any addressed read from this range the data will be removed from the top of the data FIFO and transferred to the VME backplane A re read of the last FIFO word or FIFO block is not possible BLT MBLT can be done either with or without auto address increment with blocks from 1 256 without a release of the data bus by the master W IE NE R Plein amp Baus GmbH 17 www wiener d com WIENER fay Cd Nuklear elektronik Plein amp Baus Elektronik A Phoenix Mecano Company ue 3 2 VME registers Offset Name Write Read 0x000 ident ersion mero prete pintas Renate 0x014 dlength Data length for block transfer as Byte offset_dac 4 baseline offset for all ADC inputs NT ee ee TU ioi pet peon Like Master Reset local trigger level 12 Bit s
8. the interrupt ta recognition These 4 bits are written in bit 31 28 of ta so that it is possible to map data to a specific module see data format mod_type 0x00C Module Type and Module Status LM Local Master Trigger amp controls frontpanel bus LM GW Gateway Master Links to Remote Master via P2 RM Remote Master Linked to a GW module via P2 SLV Slave Synchronized via frontpanel bus by LM RM SLV GW Gateway Slave SLV links to RM via P2 lag Synchronization reset done lag Frontpanel clock failure applies not to SM lag Remote clock failure on VME P2 W IE NE R Plein amp Baus GmbH 19 www wiener d com state dlength W IE NE WIENER Plein amp Baus Elektronik Werk fiir Industrie elektronik Nuklear elektronik Cd A Phoenix Mecano Company Regelungs technik lag Frontpanel clock ready applies not to SM lag Remote clock ready lag LM Setup Busy wait until SLV are sync lag General Clock Failure bit4 OR bit5 lag LM Timeout during sync setup lag LM Timeout caused by RM lag Trigger Time Parity Failure during broadcast 0x010 General Status Register mi qms Meaning Ti T T 7 un 8 FFULL FIFO Full Flags overflow of the 128k readout FIFO FERROR Data valid Data are ready in readout FIFO If his bit is set an interrupt is triggered in case the programmed interrupt level is not zero
9. values are restored by reset or by writing 0 A zero as parameter is not valid and will be ignored W IE NE R Plein amp Baus GmbH 23 www wiener d com Industrie elektronik WIENER M a elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik iw_start 0x118 Start of the supplementary integral window within the search window The time unit is the ADC sample rate 6 25 ns The value must be bigger or equal to 4 in order for the 4 values leading the window to be present for calculating the informational search window start pedestal iw_length 0x11C Length of the integral window in units of the ADC clock The end of the integral window plus 4 should not overcome the end of the search window The time unit is the ADC sample rate 6 25 ns sw_start 0x120 Start of the search window for the range of internal trigger time search The range is 512 to 511 times 12 5 ns 6 4 us Positive values mean halved number of presamples before trigger time and negative values mean halved number of postsamples after trigger time sw_length 0x124 Length of the search window The time corresponds to the value plus 1 times 12 5 ns The maximum value is 511 i e 6 4 us Summary of constraints to be respected IW_START gt 4 IW START IW LENGTH 4 lt SW LENGTH sw intlength 0x128 Integral length of pulse integrals in ADC sample rate units 6 25 ns After a reset the value is set to maximum 0x03FF by
10. via the error flags retrievable within the AVM16 AVX16 masters VME mode registers As long they are o k no sync failure occurred The implemented trigger scheme reduces tremendously the amount of external synchronization logic required for readout of the AVM16 AVX16 with no extra cost for the user 7 The small trigger delays between modules of a crate and modules between crates are not recovered by the local or remote masters within the current firmware version W IE NE R Plein amp Baus GmbH 12 www wiener d com 13 Technical Specification Bus standard No of channels Sampling speed Resolution Input voltage range Input offset DAC Full bandwidth Anti aliasing filter Default input coupling Noise Buffer length Clock Trigger options Feature extraction Readout mode Integration time window System timer resolution Self Test Configuration Base address Addressing mode Power requirements W IE NE R Plein amp Baus GmbH Industrie elektronik WIENER M a elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik VME64 VXS 16 LEMO connectors 160 MHz 12 bit 1 0 V individual amplitude offsets 12 bit 141MHz user defined AC 280 kHz user defined 50Q terminated customizations possible DC Gain 0 8 LSB RMS 2048 samples 12 8 us selectable 1024 max Internal clock 160 MHz External front panel connector M LVDS LVPECL User defined VME P
11. word with size and units depending on a decoding part in between both sections This is mixed up also with identification due to the output sequence The endianness of the readout interface must be checked first before a correct decoding is possible can be changed by bit 4 of com ids register 4 1 Event Data Frames Events are additionally kept in blocked event data frames with a frame header see table 4 Euer EVBLN 17 0 Length of event block EVBLN in bytes 12B 17kB TTSP 31 0 Trigger timestamp in units of 1 5625 ns 640MHz EVN 31 0 Event number reset to zero by SRST EVBLN 4 3 Data Words compressed verbose raw Table 5 Event Data Frame structure with three word Frame Header 4 2 Data Preamble In general the data words preamble or word header is itself coded in the following way oce us uor ur vo o o cs crj co Table 6 Data Preamble for localization of events U 3 0 Card address To be programmed via register com ids 19 16 C 3 0 Channel address Generated automatically 4 3 Data Decoding 4 3 1 Raw Data Decoding Word 21 0 21 12 11 0 cue o oma D 11 0 ADC raw data if OXFFF means overflow if 0x000 means underflow The Raw Data record repeats sw length times until it stops with code Z 0 W IE NE R Plein amp Baus GmbH 26 www wiener d com eae e Industrie elektronik WIENER M elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs te
12. 2 pins External NIM standard LEMO connector Internal trigger sampled leading edge Software trigger Amplitude Time of arrival Charge integrals Pile up count of two or more Compressed only charge and time for the main pulse Verbosity full set of extracted parameters Raw all samples plus full set of extracted parameters relative to trigger time or to pulse arrival time integral threshold individual for every channel programmable relative pulse integral window 1 5625 ns Internal pulse generator with programmable amplitude Remote via VME Local via JTAG connector A 31 16 selectable by 6 dip switch from 0x0002 up to OxCO1E A32 D32 BLT MBLT VME 32 5V 8A VME 64 5V 2 5A 3 3V 5 5A 13 www wiener d com Werk f r Cd Industrie elektronik WIENER Plein amp Baus Elektronik Nuklear elektronik A Phoenix Mecano Company Regelungs technik 2 Technical Description 2 1 Frontpanel Layout and Connector Description W ie Ne R AVM16 Pin No Row z Rowa Row b Rowc Row d Status 01 UD UD 5VDC UD UD O O LEDs 02 GND UD GND UD UD Data Ack 03 UD UD RETRY UD 04 GND UD A24 UD UD 0 05 UD UD A25 UD UD 06 GND UD A26 UD UD 9 1 e 07 UD UD A27 UD UD 2 08 GND UD A28 UD UD b d 68988 09 UD UD A29 UD UD 3 99999 10 GND UD A30 UD UD 00
13. 5ns and is broadcast throughout the system in the same way as described for the Internal Trigger in 1 2 5 External NIM source is only selectable for mastered boards The same rules are valid for the Software Trigger generated in situ to the generated software call and can be used for diagnostic purposes software baseline and noise monitoring With any accepted trigger the event number is increased by one resettable via VME 1 2 7 Window Control Either installed and non inhibited trigger is distributed to all channels of an AVM16 AVX16 module The trigger time is then used by the channels Window Control to set the time boundaries for Feature Extraction means scanning transmission of the dual ported RAMs Those boundaries are under full user control by four VME registers see figure 5 e SW START Search Window Start Also known as trigger latency when positive means presamples when negative refers to a postsample start range 6 4us e SW LENGTH Search Window Length Transmitted size if raw data output is chosen max 1kS 6 4us e IW Start Integral Window Start For exclusion of early integration much before trigger e IW Length Integral Window Length To additionally reduce maximum integration length SW_LENGTH ange SW_START Event trigger IW_START IW_LENGTH ix Integral range Figure 5 Data window for feature extraction The ntegral Window is only a sub part of the Search Window Addit
14. 900 11 UD UD A31 UD UD 00000 12 GND UD GND UD UD 4 00000 00000 13 UD UD 5 VDC UD UD 00000 5 00000 14 GND UD DI6 UD UD EI 15 UD UD D17 UD UD 6 COO 16 GND UD D18 UD UD II 17 UD UD D19 UD UD 00000 7 e 99999 18 GND UD D20 UD UD 19 UD UD D21 UD UD d 999606 20 GND UD D22 UD UD 8 Inp uts 60000 00000 21 UD UD D23 UD UD 00000 9 00000 22 GND UD GND UD UD EI 23 UD UD D24 UD UD 10 LIE 24 GND UD D25 UD UD Oe Coe 25 UD UD D26 UD UD 14 332 00000 26 GND UD D27 UD UD 27 UD UD D28 UD UD 42 O 28 GND BP BUSYN D29 GND UD LU 29 UD BP TRGN D30 BP TRG P UD 13 30 GND BP DATA N D31 BP DATA P UD 31 UD BP START N GND BP START P GND GND BP 40MHz N VDC BP 40MHz P VPC Figure 7 P2 VME Backplane Connector and pinout definition for M LVDS bus External Re m trigger TRG SYNC Flat cable Pin LeftRow Pin Right Row g ed connector 1 FC TRG P FC TRG N BUSY 3 FC 40MHz P FC 40MHz N 5 FC START P 6 FC START N 7 FC DATAP 8 FC DATAN amp 9 GND 10 FC_BUSY_OC Figure 8 The AVM 16 AVX 16 Front Panel Layout W IE NE R Plein amp Baus GmbH 14 Table 2 Flat Cable Connector pinout definition for M LVDS bus www wiener d com lerk f r ES WIENER A Phoenix Mecano Company luklear slektronik elungs technik Plein amp Baus Elektronik 2 2 DIP Switch and Jumper Position Figure 9 shows the user key locations fo
15. Frontpanel Layout and Connector Description eeeee eese esee ette ee eee tn enne eee ennu 14 2 2 DIP Switch and Jumper Position sossssesonssensonnnennsnsnsonsnsnsnnnnnnonsnsnnnnnnensnnsnssnnnnnnnnsnnnns 16 2 3 Analog IMP m 17 3 DESCRIPTION OF VME INTERFACE uuzsuuusssseennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 18 KBRBAUEDDITSIU DL M 18 KAWA ANI ND gana La a a J EA 19 3 3 Technical Description of VME Registers ccsscccssssssccssscsscsccscscecssssscscsssceeesesesssssssees 20 3 3 1 Virtex5 Control FPGA Registers esses eren eene enne enne nnns 20 3 3 2 Spartan3 ADC FPGA Registers nennen nennen nene gaga rennes 23 3 3 3 Spartan3 Individual Channel Registers sese 26 3 3 4 Virtex5 Data FIFO Readout Register eene nennen nennen 26 dap duel um 27 EMBOZSMITIrBULrV eno 27 4 2 Data UT Vl M 27 AMO TIEWPr lium nasao eeaane 27 4 3 1 Raw Data D coding cene hr Heri ree edente EUH Eee e E EA NGE Fa dde sd dre espada 27 4 3 2 Pulse Integral Decoding sssssssssssssseseeen eene nnne 28 4 3 3 Verbose Feature Extraction Data Decoding sssssssssssseeeeeeee nennen 28
16. The number of bytes in dlength register shall be read out DVAL will be reset and another interrupt i be generated asynchronously as soon as a event is transferred to the readout FIFO lost meaning Firmware Version 2 1 Local Busy This bit is set shortly when a trigger is accepted blocking further trigger until all the data is transferred internally to the readout FIFO It is set also when no data can be transferred from the Spartan FIFO System Busy Sum of LBUSY of the whole system Level Trigger Source Indicates which ADC channel fired the last level trigger FIFO Error If event size too big and FIFO stucks This may be generally ruled out by design 0x014 This register indicates how many bytes of data are ready for VME readout e g BLT MBLT in the FIFO 128kB reserve in total The dlength count includes only complete event frames Hence read out is fully asynchronous from data transfer as long as no FIFO overflow occurs Data is packed into a special event frame format as described for the data range register R Plein amp Baus GmbH 20 www wiener d com jtag esr jtag data tp dac offset dac 4 Plein amp Baus Elektronik Nuklear elektronik WIENER fay Cd A Phoenix Mecano Company Regelungs technik 0x030 JTAG control status Register Biene Ta e i mr ers put to the fee mo dene 2 ren sme Clock muse be zero when AG CIK is wee
17. W IE NE R Plein amp Baus GmbH 3 www wiener d com Industrie elektronik WIENER M elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 4A Data RrAm esas asas ass aaa aa nan TING DIGUNG GS ENE EEO EE NEE a aa ag Nana 29 441 Compressed Data Frame nennen ee I is ae einsehen 29 4 4 2 Verbose Data Frame ccnnnssssssssssssnenennnnsnnnnnsnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenennnnnnnnnnn 30 44 3 Raw Data Brame anana Baga Tag t remonte eter edel a nes ernennen 31 4 5 Example of Data Cnm c 32 5 PROM FILE FORMATTING usususuasnsaa sans aaa ann a ann aha dann 33 W IE NE R Plein amp Baus GmbH 4 www wiener d com Industrie elektronik WIENER M a elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 1 General Description 1 1 Overview The AVM16 AVX16 is a l unit wide VME64x VXS module which allows for compact readout of physics experiments with very high channel count 16 per unit while reducing the amount of transferred data to be stored and interpreted to a minimum Hence the AVM16 AVX16 series allows for much higher trigger rates than raw data sampling with traditional FADCs This is made possible by extensive use of local data compression power for each channel on board The implemented FPGA algorithm called feature extraction is capable to analyze any unipolar shaped physical signal coming from a scintillating plastic crystal a gaseous or silicon
18. XC3S1000 XC5VLX50T FIFO 4 3k FIFO 43k XC3S1000 P2 VME BUS XC3S1000 Trigger Connection to another Crate External Trigger Input External Trigger Bus Figure 1 AVM16 AVX16 Block Diagram Each of the ADC channel is equipped with a symmetrizing amplifier anti aliasing filter and an individual 12 bit Analog to Digital converter running at 160 MS s After conversion the digital data is passed to 4 FPGA circuits providing buffers for data retention and a feature extraction logic One Spartan 3 FPGA from Xilinx is used for a block of four channels keeping a history of 2048 samples for each channel in its internal registers W IE NE R Plein amp Baus GmbH 6 www wiener d com Nuklear elektronik WIENER fay Cd Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik Feature extraction algorithms are used to calculate important parameters of the input pulses such as amplitude time integrals and many others which allows to minimize the readout data volume and thus increasing the readout speed The user may still choose to read a full set of samples recorded in the buffer or to read only a subset of those samples within the specified time boundaries being in relation to the trigger After an internal or external trigger request the stored and or extracted data is passed to a control VIRTEX 5 FPGA chip via four local data buses and then transferred over a VME bus or a VXS backplane P2P conn
19. all ADC FPGA in order to start the analysis The next trigger is then only possible when all data have been transmitted to VIRTEX 5 With this bit a trigger is fired when the value of an ADC input that is not inhibited by cha inh overcomes the value in trig level register The corresponding ADC FPGA sends the trigger time to VIRTEX 5 which forwards it to all ADC FPGA in order to start the read out If zero means full compression Only pairs Pz Pg If one means verbose mode Additionally the pairs of values for minima and maxima are transmitted Full data is output to channels of cha raw register The polarity of the ADC data can be changed here By default ADC data are inverted to analyse negative pulses When this bit is set ADC data are not inverted to analyse positive pulses Also the RAW data are inverted Single Gradient In the computation of the rise time only two points with Ax 1l are considered Normally Ax can also be 2 or 4 if the corresponding y values lay between and of the maximal value with this bit the test signal can be st enabled with this bit the analogue ADC power supply can statically enabled Otherwise it is only enabl when bit 0 ENA is set 22 www wiener d com Nuklear elektronik WIENER fay Cd Plein amp Baus Elektronik A Phoenix Mecano Company VER act 0x104 Action register Bit Name Write single shot 1 S
20. anew measurement q threshold 16 0x280 to 0x2BC Write Only Individual threshold levels for pulse integral recognition within the Feature Extraction If a value is zero the integral of the corresponding is something like the sum of all signals also noise over the integral window and hence is not of special interest Instead a positive value with the meaning of a minimum detection energy makes sense 3 3 4 Virtex5 Data FIFO Readout Register data range 0x400 to Ox1FFFC event data frames stored in the VIRTEX 5 FIFO can be read out through this address independently from which address in this range is read so that also an incremental block transfer is possible Single transfers as well as block transfers BLT and MBLT are allowed In MBLT a trailing empty word is filled up with a zero word If the FIFO is empty gt FFFFFFFF is output A second read of data contents is not possible by FIFO definition For the kind of data format see following chapter W IE NE R Plein amp Baus GmbH 25 www wiener d com Werk f r N 4 SEA WIENER Plein amp Baus Elektronik A A Phoenix Mecano Company Exc 4 Data Format The AVM16 AVX16 data format is quite complex due to the high compression factor realized The whole event data format is structured in 32 bit words of 4 Bytes where the 32 bits may be subdivided into a preamble part for localization on the most significant section of the word and a data part on the least significant section of the
21. ch mean values are stored in a pipeline register Only if all of these values are within 1 this common value becomes the new current pedestal or baseline value In periods free of trigger and pulses the AVM16 AVX16 Noise Extraction Feature maximum peak to peak delta values are stored in individual noise registers The maximum noise value is currently limited to a value of 31 It is reset to zero by its VME noise register read 1 2 4 Trigger Feature Extraction For every activated channel the AVM16 AVX16 Trigger Feature Extraction steadily integrates four consecutive samples and stores the results in a pipeline As soon as the value rises above a certain value Pi a pulse tagging mechanism takes place For samples with distances of one two or four samples the delta values will be calculated Normally when a pulse peaks the pulse drops again For a certain time after the tagged maximum Pa only those delta values between 4 and of Pa will be used for linear extrapolation of the different pulse start times to the current baseline From all of these times the earliest becomes the pulse start or arrival time Pz with an internal resolution of Y clock period 1 5625 ns and tagged by the A method which has won see figure 4 Triggerlevel Pz Figure 4 Graphical representation of the generation of the pulse start time Pz by the AVM16 AVX16 Trigger Feature Extraction 1 2 5 Internal Trigger Independently of the Trigger Feature Extraction
22. chnik 4 3 2 Pulse Integral Decoding wordt cote ajo rro Pulse Integral in ADC units Negative values are only possible if q threshold of the corresponding channel is zero else it is always positive see 83 3 3 and may overflow during baseline upsets or signal excitations e g trips see also OVF variable in 4 3 3 4 3 3 Verbose Feature Extraction Data Decoding The following table 6 gives an overview over the coding structure of the Feature Extraction Data seem Tip ofofo comm nne fesasoe also eoi mem nme AA Verbose Mode Single Pulse Code Block i esee T Pop o cm ementi Guess rp o foli i m peces teen coaeroae ifr o eje ome erii zPEHHCEBDD ra 5 Code 0x36 afaj o jaja esoo a a 0 o p o cmo pinnes afo php mo freon ofi mn 3 fin Code 0x33 ole array iain ove or mo Jere masepak pini dio io a se Integral Code Block caeron 1 1 o fifi esei Code 0x37 fafa o fafafa base_line_start at search window start ode 0x20 Pulse Integral Decoding see 4 3 2 conero i ie Tr mmo nn Table 7 Addressed and sequenced decoding structure of Feature Extraction Data 3 Code 0x34 Code 0x35 5 Code 0x36 lt g 7 ua 5 a 1 N slae W IE NE R Plein amp Baus GmbH 27 www wiener d com Industrie elektronik WISNER M 5 elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs techn
23. d TDO Data Output of the last JTAG device ENABLE drives signal to the JTAG Connector the connector must be free 9 auTO CLK Jone clock cycle is generated rising and falling edge With bit 8 set TDI TMS and TCK on JTAG connector are driven from FPGA Otherwise these signals are high impedance in order for an external programming tool to be able to connect By means of this register it is possible to enable a program to gain full control over the JTAG chain For programming of the firmware by experts or the manufacturer the JTAG configuration connector with little imprint of the pins has to be used see figure 6 0x034 This register has two functions 0 With the read function the user gets the shift register for TDO In order not to have to read jtag csr after each output the TDO bit is moved to a write register with each cycle so that the last 32 TDO bits e g Device ID can be read out in chain TCK shift B With the write function a number of TCK Clocks with TMS 0 is returned The value is used in svf Files as RUNTEST n TCK In this way it is possible to insert pauses after commands 0x01C With bit 3 in act register it is possible to generate a test pulse through a DAC The height of the test pulse is set by means of this tp dac register Since the DAC has only 8 bits only bits 11 4 are relevant 0x020 When no signal is connected the ADC mean output value is about 0x800 i e a sig
24. dditionally LM Driving VME P2 Back Panel BP synchronization bus used for inter crate synchronization RM Remote Master Synchronized via BP from a Gate Way GW module Driving the local crates FC synchronization bus SLV Slave Synchronization done by LM or RM FC synchronization bus passive high impedance SLV_GW Slave Gateway Synchronization done by LM Driving BP synchronization bus Table 1 AVM16 AVX16 Module Mode Nomenclature W IE NE R Plein amp Baus GmbH 11 www wiener d com WIENER Cd Nuklear elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik The flat cables transfer differential M LVDS signals They have to be terminated on both ends by jumpers situated at the frontpanel and at the backpanel piggy connectors The synchronization takes place automatically after power up or a system reset SRST Within some milliseconds the mastered synchronizing FPGA controllers LM RM perform a full check of the functionality of the adapted flat cables e g listening to correct transfer of the clock and trigger signals and re initialize the system timers and timestamp registers The implemented Trigger and Clock Synchronization shall guarantee for full clock and event number synchronization and for broadcast delivery of the correct event timestamps during a completely asynchronous VME readout The current states of the synchronization are to be monitored
25. default see 1 2 7 aclk shift 0x12C The ADC clock must have a fixed phase to the FPGA clock in order to correctly transmit ADC data For test purposes it is possible to change the phase e g in order to determine whether the default phase is set correctly The default phase is 0 Execute a step Step executed Upper or lower limit reached overflow t 0 4 8 12 1 5 9 13 2 6 10 14 Reset number of steps to 0 160 steps in one or the other direction correspond to 180 Ib test 4 0x130 to 0x13C Every one of the 4 SPARTAN 3 FPGA has a data test register for testing the local data bus These registers should be writeable with any 16 bit value and it should be possible to read this value back After a MRST values 0x1230 to 0x1233 are preset for the 4 FPGA W IE NE R Plein amp Baus GmbH 24 www wiener d com Industrie elektronik WIENER M a elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 3 3 3 Spartan3 Individual Channel Registers base_line 16 0x200 to 0x23C Read Only The ADC mean values for all channels are continuously updated and can be monitored by these addresses see 81 2 3 noise_level 16 0x240 to 0x27C Read Only The peak noise amplitude is computed for each channel individually by subtracting the minimum value from the maximum value outside of pulses since the last read see 1 2 3 An individual read call resets the noise level for
26. ection fabric In multichannel systems where a common time base is required global clock and synchronization signals are provided either via the front panel connector or via user defined pins on the VME P2 connector The clocking and synchronization circuitry allows for choosing of the correct clock source especially for bigger data acquisition systems 1 2 2 AVMI6 AVX16 Feature Extraction FEATURE EXTRACTION 2 5 lt 12 BIT 1 WINDOW LOCAL pee CONTROL z BUS 7 data WAVEFORM trigger FEATURE 9 timing EXTRACTION PEDESTAL N EXTRACTION A j Ee Y NOISE PP Figure 2 Feature extraction FPGA The following description of the Feature Extraction applies to every channel in the same manner When no trigger occurs while the AVM16 AVX16 is running the current baseline pedestal and the current peak to peak noise value is regularly recalculated and updated These values can be read out any time via VME for longtime monitoring purposes The further Waveform Feature Extraction then strongly relies on the freshest recalculated baseline value Data coming from ADC converters are continuously stored in ring buffers dual ported RAM synchronous to the global clock keeping a record of the last 2048 samples Only 1024 of these samples can be selected from the window control for output to the Spartan local interface FIFO
27. ether the end of integral window is reached first or the pulse amplitude has fallen back to 1 32 of its maximum before Only the pairs Pz Pq are transmitted to the central FIFO in compressed readout mode If pileup events occur the process repeats for every peak trigger PO Pi Pz Pa PPi PPz PPa time 0 PPq 5 Figure 3 Feature extraction parameters P0 window beginning Pi first value greater the channels individual integral threshold Pz pulse start time calculated from slope crossing the pedestal value Pa signal amplitude Pq signal integral charge j Pileup Number in case of j 1 the brackets were suppressed in figure 3 PPi j minimum value before pileup PPz j pileup pulse start time calculated from slope crossing the current pedestal value PPi j PPa j pileup pulse amplitude Pe j pileup integral starting from PPi j relative to the common baseline f pileup occurs the integral Pq is only calculated until PPi j time else when 1 32 of Pa is reached else when the integer window end comes before W IE NE R Plein amp Baus GmbH 8 www wiener d com WIENER fay Cd Nuklear elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 1 2 3 Pedestal and Noise Extraction In periods free of trigger and pulses the AVM16 AVX16 Pedestal Extraction Feature steadily calculates the mean of 32 consecutive samples for every channel Eight su
28. for every channel an internal leading edge discriminator sampling is implemented for fast trigger decision on a one board level Single or Local Master see 1 2 8 The common threshold is programmable via VME trigger level register Only the first Spartan3 FPGA trigger from all activated channels becomes the event trigger referenced to from the local Virtex5 FPGA If several trigger appear at the same time the trigger channel with the smallest channel number is chosen The event trigger location can be readout via the VME state register The event trigger is broadcast back to all 16 window controls see 1 2 7 Additionally the event timestamp is broadcast in bigger system with more than one card or crate see 1 2 8 but only one card in the system is installable with this featured internal trigger LM in the current hardware and firmware version non inhibited controlled via the VME cha_inh register controlled via the channel selective VME q_threshold register controlled via the VME anal_ctrl register W IE NE R Plein amp Baus GmbH 9 www wiener d com Industrie elektronik WIENER M a elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 1 2 6 External NIM and Software Trigger External NIM trigger from the terminated frontpanel TRG LEMO connector can be accepted for fast trigger timestamp generation on base of the internal 640MHZ clock reference The timestamp has a resolution of 1 562
29. hat the nomenclature has changed a bit from the new manual version V2 0 to help for a better understanding A cross check is given by the following tabular New Nomenclature Old Nomenclature baseline or baseline at start end of integral window mean level preceding trailing q_threshold trigger time in integral window minimum time first value above q_threshold in integral window minimum level pulse peaking time maximum time pulse peak amplitude maximum level single pulse 1 first pileup pulse 2 second The variable declarations as given by figure 3 Pz Pi Pa PPz j PPi j Pg Pe j etc are those since start of the AVM16 AVX16 project even if ordinates and abscissas had been a bit mixed up To disentangle this the times are called within the code data tables The pileup count has changed form two max to more than two with the newest firmware version s Everyone should feel free to use an own nomenclature in the DAQ software for data processing W IE NE R Plein amp Baus GmbH 31 www wiener d com ES e Industrie elektronik WIENER M f elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 5 PROM File Formatting In the case a new firmware version exists distributed by W IE NE R directly or is made remotely available via the W IE NE R Download File Server the expert user may check first whether it fits to the corresponding board version and
30. ignal analysing control 0x130 1b test 4 r w test register for the local bus to 4 SPARTAN 0x13C 0x200 base line 16 auto base line 12 bit 0x23C 0x240 noise level 16 peak to peak noise level 0x27C 5 Bit 0x280 threshold 16 q threshold for trigger Ox2BC decision in the integral indow amp data block gen 0x0800 data range data single or block OxlFFFC transfer W IE NE R Plein amp Baus GmbH 18 www wiener d com WIENER Cd Nuklear elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs techni 3 3 Technical Description of VME Registers 3 3 1 Virtex5 Control FPGA Registers ident 0x000 Board Id Contains firmware version number Bit Value Meaning 7 0 0x70 Module Id V1 1 common baseline no NIM Trigger 0x71 Module Id V1 2 wrong baseline byte swap 0x72 Module Id V1 3 actual Design Firmware Version here 2 1 new Sync System Reserved Serial 0x004 User serial number This number can be programmed by the user and is saved in the FPGA PROM Read and write access possible com ids 0x008 In this register there are three identifiers for communication Bit Meaning 2 0 Interrupt Request Level 1 to 6 an interrupt is issued if data are available A 0 disables the interrupt Little endian Big endian default terrupt Vector It is transmitted on Interrupt knowledge in order to identify
31. ik OVF Overflow bit To additionally flag for overflow and underflow events AX 1 0 AX bin decoding Smallest Pz PPz j was achieved with bin value 1 2 4 Units and types All times are in units of the system timer 1 5625 ns 640MHz Respectively Pz with signed 14 bit all time types are of signed 16 bit Negative values count times before the event trigger All other value units are in ADC bits Types are of signed 16 bit The sign refers to the orientation over or under the current baseline Code Sequence The preferred sequence within the data blocks while output 1s as given in the order indicated by the counter number left of the bordered boxes 4 4 Data Frames 4 4 1 Compressed Data Frame Compressed mode is the most sparse data mode and should only be used if the overall ground and channel baseline stability has been proven as well as rare electrical upsets trips discharges can be ruled out or tackled by another external system In this case the Compressed Data Frame has a simple Pz Pq structure starting with the lowest channel number containing data above threshold maybe sparse of some channels to the highest channel containing data above threshold First Event Block Length First Trigger Timestamp First Event Number Preamble first channel beyond q threshold Pulse Start Time Decoding 0x36 Preamble first channel beyond q threshold Pulse Integral Decoding 0x20 e e e Preamble last channel beyond q_thresho
32. ionally the SW INTLENGTH variable limits the maximum width for the pulse integral extraction after Pz PPz j in case of a pile up event It can be used with big success for nearly Gaussian shaped pulses where tailored integral measurements cause no additional failures W IE NE R Plein amp Baus GmbH 10 www wiener d com WIENER fay Cd Nuklear elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 1 2 8 Trigger and Clock Synchronization Making extensive use of the frontpanel and backpanel synchronization connectors of the AVM16 AVX16 eases dramatically the final installation of a multi module or multi crate setup The following figure 6 shows then how the trigger scheme follows a simple top down structure 69009900 end LVDS Front Dus mmm Trigger Signal NIM 90000000000 20000000 00000000 100 LVDS Front Bus Ed meme Figure 6 Trigger and Synchronization Scheme for bigger experiments To simplify the routing of the different possible clock and trigger sources in such a common synchronization scheme with flat cables the following nomenclature was introduced to help how to preset the modules VME mode registers SM Single Master Standalone module triggered by software external NIM or internal Frontpanel Connector FC synchronization bus passive high impedance LM Local Master Like SM Driving FC synchronization bus Local Master Gateway Like LM but a
33. ld Pulse Start Time Decoding 0x36 Preamble last channel beyond q_threshold Pulse Integral Decoding 0x20 Second Event Block Length Second Trigger Timestamp Second Event Number In case of pile up further PPz j Pe j j 1 N couples with same channel number directly follow Finally the sum of all individual EVBLN shall agree with the d length FIFO byte count read out W IE NE R Plein amp Baus GmbH 28 www wiener d com Industrie elektronik WIENER M a elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 4 4 2 Verbose Data Frame Verbose mode allows to tackle for electrical upsets during run time To do this the baseline mean values four samples before the integral window and four samples after the integral window are output quite early in the Verbose Data Frame by the Verbose Mode Pulse Integral Code Block First Event Block Length First Trigger Timestamp First Event Number With Preamble of first channel beyond q_threshold Verbose Mode Pulse Integral Code Block Verbose Mode Entry Code Block Verbose Mode Single Pulse Code Block Pulse Integral Decoding 0x20 With Preamble of last channel beyond q_threshold Verbose Mode Pulse Integral Code Block Verbose Mode Entry Code Block Verbose Mode Single Pulse Code Block Pulse Integral Decoding 0x20 Second Event Block Length Second Trigger Timestamp Second Event Number In case of pile up further code blocks and pulse integrals are transmitted
34. n PROM is Slave clocked externally c Program After this the AVM16 AVX16 is ready for powering up in a W IE NE R VME64 VXS Crate W IE NE R Plein amp Baus GmbH 32 www wiener d com
35. nal in one polarity can use only half of the measurement range By means of an offset value for a DAC it is possible to reduce this ADC mean value until Zero For this purpose there are 4 12 bit DACS with 4 channels respectively The DAC AD5324 has the following SPI register assignments W IE NE R Plein amp Baus GmbH 21 www wiener d com WIENER Plein amp Baus Elektronik Nuklear elektronik Industrie elektronik A Phoenix Mecano Company Regelungs technik PE Ks DAC Function WO 12 kit offset one unit corresponds to about one ADC unit i e when the value here is increased by 0x100 the ADC mean value when no signal is present should decrease more or less by the same value Fer this bit is 0 all 4 channels are updated This Fe is always set to 0 internally alude 30 bas not power not power down this bit is set internally to 1 this bit is set internally to 1 15 14 A1 AO0 DAC channel group number 0 to 3 for offset dac 0 4 to 7 for offset dac 1 and so on 3 3 2 Spartan3 ADC FPGA Registers The read back of these registers occurs from a shadow register in VIRTEX 5 er 0x100 Control Mode Register dos LEVTRIG is W IE NE R Plein amp Baus GmbH ER neral enable If this bit is not set AVM16 is in ERES ground state All data is deleted Enables the trigger input from the front connector LVDS The trigger time is determined in VIRTEX 5 and sent to
36. or the Feature Extraction working properly during run time the full Verbose Data Frame is automatically added behind e e With Preamble of a channel beyond q_threshold Raw Data Record Verbose Mode Pulse Integral Code Block Verbose Mode Entry Code Block Verbose Mode Single Pulse Code Block Pulse Integral Decoding 0x20 And in case of a pileup event with pileup factor of two e e With Preamble of a channel beyond q_threshold with Pileup Raw Data Record Verbose Mode Pulse Integral Code Block Verbose Mode Entry Code Block Verbose Mode Single Pulse Code Block Pulse Integral Decoding 0x20 Verbose Mode Pileup Pulse Code Block Pulse Integral Decoding 0x20 Finally the sum of all individual EVBLN shall agree with the d_length FIFO byte count read out W IE NE R Plein amp Baus GmbH 30 www wiener d com m e WIENER A _ AM Nuklear Plein amp Baus Elektronik A Phoenix Mecano Company Exp 4 5 Example of Data Readout To give a practical example for a typical AVM16 AVX16 data frame the location identifier is set to zero com ids 19 16 zero and only the first three channels were non inhibited cha inh 0xFFFS8 and set to raw mode cha raw 0x0007 at a trigger point in which all three channels see a pileup event at the same time see figure 11 Extracted Data Meaning Same data if they were on ch 1 Same data if they were on ch 2 10 Channel Figure 11 Possible example of data output This is an older example but shows t
37. r jumpers and connectors SOIN31 1ndu 3 3 5 8 E S x S Q iS g S S 3 N a AI er S d uv y E o n Ja S b Adi d ES P 2 gt Ben iz m Eel E oO amp pm E aa eubis WIN BUH E JeBBu BuJ9 X3 a WIENER Cd Nuklear elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 2 3 Analog Input The default input AC filter provides an effective cut off for background low frequency noise and mains pick up It is optimized for use in a typical QDC readout chain generating negatively shaped unipolar pulses of 2 volts dynamics 12bit DACs allow to shift the baselines individually into the upper region to use the full dynamical range 12 bit The symmetrizing amplifier provides a differential input for the 12 bit ADC reducing PCB noise pickup The anti aliasing filter allows for precise input bandwidth control An on board pulse generator provides a fast test pulse of programmable size to all channels for diagnostic purposes COMMON LEVEL L1 C4 H 100nF C5 10uF 1206 Q 3 3VA BSLA gt NP A My THS4521 v TEST PULSE 510 Figure 10 Input symmetrizing amplifier and anti aliasing filter R5 R7 C2 Resistors values the location of the test pulse and the values and locations of capacitors may depend on AVM16 version or be customized Customization by manufacturer Dynamic range of the inpu
38. stem or translated into any language in any form by any means without the express written permission of W Ie Ne R W IE NE R Plein amp Baus GmbH 2 www wiener d com Industrie elektronik WIGNGR M a elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Table of contents 1 GENERAL DESCRIPTION sasa sana ata ana nain na aga aa aa pa ah a AN aa aa aa baa naa na Anna 5 1 1 OAT a E E E E 5 1 2 Functional description eesseeseesseeseeesoeseeesoeesoesoeesoeeseesoeeseesceesoeseoesoeesoseeoesoeesorsooeeessoeeeesseoeeesss 6 1 2 1 Block diagram teret m e e ete DR KG SEIEN e I ER qos ner 6 1 2 2 AVMI6 AVX16 Feature Extraction nennen enne enne 7 1 2 3 Pedestal and NO1seEKtractioni ss eag gaeng pas KUE pa E NGE SINGA EE NE NGA EHE GED EA NGA ba Eeee 9 1 2 4 Trigger Feature Extraction iret ah peng aa aka bagan kag Papa asd cece aaa ga babi a naban 9 1 2 5 Internal Trigger een nenne ERE aa sa DAB KG ga aa aan 9 1 2 6 External NIM and Software Trigger enne nnns 10 1 2 7 Window Control ak apana ae ag a aan a nie Ka Tag gagang a gang ena b panang ea aana bapan 10 1 2 8 Trigger and Clock Synchronization ssesesesee een e aane nenen w anana aana n anana nennen 11 1 3 Technical Specification ssousssossssossssnnsssnnssnnnsnnnnsnnnssnnnssnnnssnnnsnnnnsnnnnsnnsnsnnnsssnnnsnnsnnnnnnsnssnnne 13 2 TECHNICAL DESCRIPTION 2222444444040000000000RR Rn nnnn nnn nnn nnn nnn nnn nnn nnn nnn nnn 14 2 1
39. ts and the bandwidth of the anti aliasing filters as well as DC coupling can be easily adapted on customer request Due to the unipolar input circuitry positive pulses can be sampled only with halve of range and resolution 11 bit In this case the overall sampling polarity for positive feature extraction analysis can be switched via the VME control register x The 0603 SMD 500 input termination is capable to sustain only a maximum power of 63mW and 50V peak voltage W IE NE R Plein amp Baus GmbH 16 www wiener d com Industrie elektronik WISNER M 5 elektronik Plein amp Baus Elektronik A Phoenix Mecano Company Regelungs technik 3 Description of VME Interface 3 1 VME addressing AVM16 AVX16 reacts to read and write accesses with following Address Modifiers AM gt 0F A32 supervisory block transfer BLT gt 0B A32 non privileged block transfer BLT gt 0D A32 supervisory data access gt 09 A32 non privileged data access gt 0C A32 supervisory 64 bit block transfer MBLT gt 08 A32 non privileged 64 bit block transfer MBLT Table 3 AVM16 AVX16 Address Modifiers The base address is set by means of a 6 fold DIP Switch SW1 according to following table Base Address 0x80000000 0x40000000 0x00100000 0x00080000 0x00040000 0x00020000 Table 4 Base Address Settings A switch in the on position means that the corresponding address bit
40. ynchronous Reset for all timers so that all FPGA have the same time reference 2 TRIGGER Software Trigger 3 TPULSE Generates a fast test pulse on all 16 channels Bits 3 1 are only relevant for modules in Single Master SM or Local Master LM mode see mod_type register Those signals will be sent to all allocated Slave Modules in the synchronization scheme A software triggered pulse is generated when bits 2 and 3 were synchronously set cha_inh 0x108 The corresponding channel to each bit 0 bis 15 which is set is inhibited means removed from readout trigger and feature extraction cha_raw 0x10C If the corresponding channel to each bit is set all ADC raw data samples that are within the search window are transmitted together with all available data from the feature extraction including start point value pairs integrals trig_level 0x110 This value is the common trigger level when LEVTRIG in cr register is activated relative to internally regularly updated baseline of every channel anal_ctrl 0x114 Here it is possible to parametrize the pulse analysis Integral based detection this value times 4 indicates how high should the integral be in order for a pulse to be detected In case of a pile up the integral is computed on the basis of the last minimum value number of clock units after the last maximum start time point from where a new pulse even a ile up can be detected The default
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