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AXM-D Series and AXM

1. 4 MODEL 5025 288 TERMINATION PANEL SCHEMATIC Sess ARE TIED TO J1 METAL HOUSING A PIN 68 2 2 5 J1 ss 5 8 n 12 al H 2 MET 3 40 86 36 PLACE MODEL SERIAL TBI LABEL HERE gt 1 200000000000000000002000000020000 t1 88 ooooooooooooooooooooooooooooooooQ n Y SIDE VIEW lt 180 34 zx TOP VIEW NOTE 123 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 DIMENSIONS AREIN INCHES 1 MILLIMETERS 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 TERMINATION 2 HHHH MARKINGS 68 58 FRONT VIEW 4501 920 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com
2. AXM 004 30 LVDS 8 Channels AXM EDK 30 LVTTL 8 Channels CE Differential I O are provided on the AXM D02 and AXM D03 models through the Field I O Connector refer to Table 2 1 and 2 2 Field I O points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage Differential channels to the FPGA are buffered using EIA RS485 RS422 line transceivers The transceivers are considered failsafe as a open or short circuit on the I O will not damage the board Field input lines are not terminated External 120 Ohm resistors are recommended on all receivers Signals received are converted from the required EIA RS485 RS422 voltages to the LVTTL levels required by the FPGA Likewise LVTTL signals are converted to the EIA RS485 RS422 voltages for data output transmission The direction control of the differential channels is independently controlled Digital field I O are provided on the 003 model through the Field Connector refer to Table 2 2 Field points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops Ignoring this effect may cause operation errors and with extreme abuse possible circuit dama
3. COMMON Differential Ch28 Differential Ch29 COMMON 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 50 51 52 53 54 55 56 57 58 59 61 62 63 64 65 67 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board AXM D04 Front I O The AXM D04 module has 30 Low Voltage Differential Signaling LVDS channels The data direction of the differential channels numbered 0 to 29 are independently controlled via the Differential Direction Registers The pinout is shown in Table 2 3 Table 2 3 AXM D04 Board Field I O Pin Connections Pin Description Pin Pin Description LVOSCh a CVS Ch lVDSCh k O CVS Ch 6 3 lVDSCh amp 8 36 C Sere 9 O Sero LVDSCh LVDSChi e 16 6056 O i7 LVDSCh4 O 18 LVDSChi5 LVDSChM i9 LVDSChi 5556 22 LVDSChi8 O COMMON 23 COMMON 1705 2 24 LVDSCh2 O LVDSCm2 25 CLS Chet 5556124 26 CLS Chee DSCs 27 LVDS Chea 5550 28 LVDSCh24 O 1705 5 29 0505 O LVDSCh26c 30 LVDSCh26 705 3i 057 O 1705 32 LVDSCh28 O Ker O gt Od OF BY BH 5 5 BY BY BR BY RY BY CO Go Co Go CO N
4. careful consideration should be given to air filtering Remove power from the system before installing board cables termination panels and field wiring The AXM EDK and AXM D Series boards cannot stand alone and must be mated with a compatible Acromag PMC module The default configuration of the control register bits at power up is described in section 3 The front panel connector provides the field I O interface connections For the AXM D series it is a SCSI 3 68 pin female connector AMP 5787394 7 or equivalent employing latch blocks and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to Acromag termination panel 5025 288 from the front panel via round shielded cable Model 5028 432 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 7 The AXM EDK board has two front connectors The first is a double row 14 pin 2mm header male for JTAG programming This is the standard Xilinx JTAG Header The other I O interface is a double row 34 pin 0 1 header male A standard floppy drive cable can be used to connect to the interface Note neither cables are available from Acromag The 002 module has 30 differential I O channels The data 002 Front I O direction of the differential channels numbered 0 to 29 are independently controlled via the Differential Direction R
5. 46 Channels AXM EDK Bi directional LVTTL LVTTL VO signals are independently direction controlled Reset Power Up Condition All Digital Channels Default to Input LVTTL I O Characteristics Due to the direct connections from the Field to the FPGA all I O characteristics for LVTTL are determined by the FPGA Refer to the FPGA documentation for 3 3V signaling for further information Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 26 AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board APPENDIX CABLE MODEL 5028 432 SCSI 3 to Round Shielded TERMINATION PANEL MODEL 5025 288 Type Round shielded cable 68 wires SCSI 3 male connector at both ends The cable length is 2 meters 6 56 feet This shielded cable is recommended for all I O applications both digital I O and precision analog I O Application Used to connect Model 5025 288 termination panel to the board Length Standard length is 2 meters 6 56 feet Consult factory for other lengths It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 68 conductors 28 AWG on 0 050 inch centers permits mass termination for IDC connectors foil braided shield inside a PVC jacket Connectors SCSI 3 68 pin male connector with backshell Keying The SCSI 3 connector has a D Shell Schematic and Physical Attributes See Drawing 4501 919 Electrical
6. On BY Go Po CO NI Od BK Go N O CO CO NI O O1 A Gd N O CY CO C1 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com hitp www acromag com 1 0 AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board AXM EDK Front I O The AXM EDK has a standard 34 pin double row 0 1 header for front The I O are LVTTL compatible These pin connections can emulate the 30 differential channels on the 002 and AXM D04 models and the 22 differential channels on the 003 model using LVTTL signaling Refer to the Differential I O Register section for further information Front I O connections are listed in Table 2 4a The AXM EDK front I O also includes the standard Xilinx 14 pin 2mm JTAG header This header can be used to directly program the FPGA or to interface with the FPGA debug software ChipScope The pin connections are shown in table 2 4b In addition the AXM EDK contains 16 auxiliary pins that are routed to two 8 pin SIP patterns on the board Note that these are not front panel I O connections Due to height restrictions SIP sockets are not installed This allows for full end user customization These pins correspond to the 16 channels of Digital I O on the AXM D03 module Refer to the Digital I O Register section for further information The connections are listed in table 2 4C Refer to drawing 4502 056 located at the end of this manual for pin loca
7. See the PMC base board for further information The JTAG interface is powered by 3 3V Eight Channels in each model can be configured to generate interrupts INTERRUPT LOGIC for Change Of State COS and input level polarity match conditions The interrupt is released via a write to the corresponding bit of the Interrupt Status Clear register The channels enabled for interrupt in the example design are Differential Channels 8 to 15 on the 002 and 003 LVDS Channels 8 to 15 on the AXM D04 and LVTTL Channels 8 15 on the AXM EDK Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 20 AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board AXM EDK and AXM D series of ion I O modul hed e an D series of extension modules are attache CONNECTION to the PMC base board via a high speed 150 pin header The connector provides power to the extension board and multiple logic connections to the base board Note that any PMC base board with a re configurable FPGA will require the pin definitions provided in the EDK to properly operate the AXM EDK and AXM D series boards Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series and AXM EDK User s Manual Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for re
8. 32 bit data transfers INPUT OUTPUT with the lower ordered bits corresponding to the lower numbered channels REGISTERS for the register of interest All input output channels are configured as inputs following a power on or software reset Data bits 16 through 31 are not used and will return 0 when read Data bits 0 through 15 on the AXM D02 and AXM D04 modules are not used and will read back the last data value written to them Digital Direction Control Register Read Write Base Addr 8010H The data direction input or output of the digital channels is selected via this register at the carrier base address 8010H This includes the sixteen CMOS Channels on the 003 and the sixteen auxiliary LVTTL I O on the AXM EDK module The direction of each channel is controlled by its corresponding data bit The register mapping is the same as the Digital I O Register Data bits 16 through 31 are not used and will return 0 when read Data bits 0 through 15 on the 002 and AXM D04 modules are not used and will read back the last data value written to them Independent channel direction control is provided for each digital channel Setting a bit low configures the corresponding channel data direction for input Setting the control bit high configures the corresponding channel data direction for output The default power up state of these registers is logic low Thus all channels are configured as inputs following system reset or power u
9. Acromag Qi AXM D Series and AXM EDK Digital I O Mezzanine Modules USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A Copyright 2010 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 796 C10H012 2 AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board TABLE OF IMPORTANT SAFETY CONSIDERATIONS CONTENTS You must consider the possible negative effects of power wiring component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Information The information of this manual KEY FEATUBRES eri ener nere tits od evans 4 may change without notice SIGNAL INTERFACE PRODUCTS 5 Acromag makes no warranty ENGINEERING DESIGN KIT 5 of any kind with regard to this BOARD CONTROL 5 material including but not limited to the implied 2 0 PREPARATION FOR USE warranties of merchantability AN NSSS OF UNPACKING AND 1 6 purpose Further Acromag assumes no responsibility fo
10. BEZEL 4 THE SCSI CONNECTOR CAN BE FURTHER SECURED TO THE BOARD WITH 2 ADDITIONAL SCREWS D 5 CONNECT THE COMBINED AXM amp PMC MODULE TO THE CARRIER PER THE MANUFACTURE S INSTRUCTIONS PMC MODULE NYLON STANDOFF x2 CONNECTOR pe YW COMPONENT SIDE OF PMC MODULE D AXM MECHANICAL ASSEMBLY 4502 6055 NYLON SCREWS x2 GROUND SHIELD ON CABLE CONNECTS TO P1 amp P2 SHIELDED BACKSHELL 4 H gt cH 1 P2 P 9 e7 66 66 H gt ot a 2 METERS g a po 78 72 INCHES 4 0 0 0 INCHES 1 60 60 9 E TOP VIEW 57 57 56 56 E SS S 53 53 52 52 51 51 50 50 49 49 2 2 3 2 S 47 47 46 46 C 45 45 5 5 PIN 34 HR PIN 68 PIN 25754 PIN 68 38 38 E x 37 28 36 zi 88 32 32 BB T 31 31 BB 98 30 30 E HE E BB 88 28 28 BB oo M M T T E PIN 1 35 PIN 1 Pia PIN 35 2 22 21 21 i FRONT VIEW i i MODEL 5028 432 SCSI 3 68 PIN CABLE ASS
11. DK N A No active components Channel Configuration 30 002 or 22 AXM D04 Bi directional EIA 485 422 differential signals are independently direction controlled e 1 5 V Min 3 3V Max Differential Driver Output Voltage with 540 load e 3V Max Common Mode Output Voltage e 0 2 Min to 0 05 Max Differential Input Threshold Voltage 7 lt lt 12 e 15mV Typical Input Hysteresis e 96KQ Minimum Input Resistance The receiver contains a fail safe feature that results in a logic high output state if the inputs are unconnected floating or shorted e Driver Input to Output Delay 27ns Typical 40ns Maximum e Receiver Input to Output Delay 33ns Typical 60ns Maximum Termination Resistors Termination resistor are not provided External 120 Ohm termination resistors for EIA RS485 422 differential receivers are recommended SPECIFICATIONS Reliability Prediction DIFFERENTIAL I O EIA 485 422 Differential I O Electrical Characteristics Differential Propagation Delay Termination Resistors Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 24 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board DIGITAL I O CMOS Digital I O DC Electrical Characteristics Digital Propagation Delay LVDS I O LVDS I O Electrical Characteristics LVDS Propagation Delay Maximum Data Rate Termination Resistors CMOS Channel Configuration 16 C
12. EMBLY SHIELDED 5 4 4 2 2 m l 4501 191 SCHEMATIC Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 30 AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 12345678 9101112 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
13. FF CHANNEL 29 P1 DIRECTION CONTROL re DIFF CHANNEL 29 a 100 Ohms 10K r LVTTL I O A TO FPGA 30 LVDS INPUT OUTPUT DIFF CHANNEL 0 CHANNELS 2 DIRECTION CONTROL re DIFF CHANNEL 0 gt 100 Ohms 10 m3 AXM D 4 BLOCK DIAGRAM 4502 051C EDK MODULE JTAG PIN FUNTIONS PIN FUNCTION PIN FUNCTION 1 GND 2 3 3V 3 GND 4 TMS 5 GND 6 TCK 7 GND 8 TDO 9 GND 10 TDI ee 11 GND 12 NC FRONT AREA 13 GND 14 NC AXM EDK 1 0 LOCATION DRAWING 4502 055 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 29 FLAT HEAD 2 56 OPTIONAL FLAT HEAD 2 56 NYLON SCREWS x2 NYLON SCREWS x2 ASSEMBLY PROCEDURE CMC BEZEL 1 INSERT CMC BEZEL OVER AXM MODULE A USE TWO BEZEL SCREWS TO SECURE IF NECESSARY THE PORTION OF THE AXM MODULE COVERED BY THE CMC BEZEL IS OUTLINED 2 CAREFULLY ALIGN THE CONNECTORS ON THE PMC MODULE AND THE AXM MODULE PUSH CONEONENT SE QF AM MODULE TOGETHER B STACKING HEIGHT IS 8 mm l po CONNECTOR 3 SECURE THE AXM MODULE WITH NYLON CMC BEZEL eo STANDOFFS 2 AND WITH 4 SCREWS C SCREWS x2 TIGHTEN ALL SCREWS rm AREA COVERED BY CMC
14. However an example design for each module is included in the Engineering Design Kit of the PMC base board Furthermore the AXM EDK is included with the Engineering Design Kit of the PMC base board to allow for programming via the JTAG interface Refer to the PMC base board s manual for further information on the available Engineering Design Kit Acromag does not provide board control software specifically for the BOARD CONTROL AXM EDK and 0 series boards However the AXM EDK and each SOFTWARE AXM D module can be accessed via the control software for the base PMC module These products sold separately facilitate the product interface in the following operating systems Windows DLL VxWorks and QNX Refer to the PMC base board s manual for further information Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 6 AXM D Series and AXM EDK User s Manual 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Wy CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS WARNING This board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature BOARD CONFIGURATION Default Hardware Conf
15. Specifications 30 VAC per UL and CSA SCSI 3 connector spec s 1 Amp maximum at 50 energized SCSI 3 connector spec s Operating Temperature 30 C to 80 C Storage Temperature 40 C to 85 C Shipping Weight 1 0 pound 0 5Kg packed Type Termination Panel For 68 Pin SCSI 3 Cable Connection Application To connect field I O signals to the board Termination Panel Acromag Part 4001 066 The 5025 288 termination panel facilitates the connection of up to 68 field I O signals and connects to the board connectors only via a round shielded cable Model 5028 432 Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 68 correspond to field I O pins 1 68 on the board Each board has its own unique pin assignments Refer to the board manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 920 Field Wiring 68 position terminal blocks with screw clamps Wire range 12 to 26 AWG Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 0 pounds 0 5kg packaged Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series and AXM EDK User s Manual Dig
16. ed bits corresponding to the lower numbered channels for the register of interest All input output channels are configured as inputs following a power on or software reset Data bits 30 and 31 are not used and will return 0 when read Data bits 0 through 7 in the 003 module will read back the last data values written to those bits Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 1 D DIFFERENTIAL Differential Direction Control Register Read Write INPUT OUTPUT Base Addr 8008H REGISTERS The data direction input or output of the differential channels is selected via this register at the carrier base address 8008H This includes the direction of all 30 differential channels on the 002 22 differential channels on the 003 30 LVDS channels on the AXM D04 and 30 general purpose LVTTL channels on the AXM EDK The direction of each channel is controlled by its corresponding data bit Data bit use varies depending on the module selected The bit mapping corresponds to the Differential EDK I O Register Independent channel direction control is provided for each differential channel Setting a bit low configures the corresponding channel data direction for input Setting the control bit high configures the corresponding channel data direction for output The default power up state of th
17. egister The pinout is shown in Table 2 1 Table 2 1 AXM D02 Board Pin Description Pin Pin Description Field VO Pin Connections EON Differential Ches 8 Diferential Che Differential 9 Diferential Ch7 COMMON a COMMON Differential Ch4 Differential Ch4 gt OF OF O1 OF1 OT BY BH 5 BY 5 BY BR BY RY BY Co Go N BY Go PO o CO NI Od BY Go N O 0 NI A Gd N O CY CO O1 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com hitp www acromag com 8 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 003 Front I O Table 2 2 AXM D03 Board Field Pin Connections DIFFERENTIAL CHANNELS ARE NUMBERED 8 to 29 THERE ARE NO DIFFERENTIAL CHANNELS 0 to 7 ON THIS MODULE The 003 module has 22 differential I O channels and 16 digital CMOS channels The data direction of the differential channels numbered 8 to 29 and digital channels numbered 0 to 15 are independently controlled via the Differential and Digital Direction Registers The pinout is shown in Table 2 2 SCSI 3 68 Pin Female Connector i Pin oa 8 Ee i i i i 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 i Differential Ch18 COMMON i Differential Ch25 Differential Ch27 Differential Ch26 Differential Ch27 Differential Ch28 Differential Ch29
18. ese registers is logic low Thus all channels are configured as inputs following system reset or power up Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Data bits 30 and 31 are not used and will return 0 when read Data bits 0 through 7 in the 003 module will read back the last data values written to those bits Digital Input Output Registers Read Write DIGITAL Base Addr 800CH INPUT OUTPUT Digital CMOS input output channels may be individually accessed via REGISTERS this register at the carrier base address 800CH This includes the sixteen CMOS Channels on the 003 and the sixteen auxiliary LVTTL I O on the AXM EDK module Channel input signal levels are determined by reading this register Likewise channel output signal levels are set by writing to this register The data bits are mapped according to the following table Note that the data direction input or output must first be set via the Digital Direction register at base address plus 8010H Model Digital I O Register Mapping 05 D14 03 D12 Dt 00 09 D8 AXM EDK AUX 15 AUX 14 AUX 13 AUX 12 AUX 11 AUX 10 AUX 9 AUX 8 FL o bt 50 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 6 AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board DIGITAL Channel read write operations use 8 bit 16 bit or
19. ge Digital input output signals to the FPGA are buffered using a dual voltage digital transceiver Signals received are converted from 5V CMOS to LVTTL as required by the FPGA Likewise LVTTL signals are converted to 5V CMOS voltages for data output transmission The direction control of the digital channels is independently controlled Each field line has a 10K pullup resistor to 5V Output operation is considered Fail safe That is the Digital Input Output signals are always configured as inputs following a power up or software reset This is done for safety reasons to ensure reliable control under all conditions Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 1 LVDS INPUT OUTPUT LVDS I O on the AXM D04 are provided through the Field I O Connector LOGIC refer to Table 2 3 Field I O points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage LVDS channels 0 31 to the FPGA are buffered using multidrop LVDS line drivers and receivers The drivers and receivers are standard LVDS signaling characteristics TIA EIA 644 with double the current for multipoint applications Field inputs to these receive
20. gh i e a 1 in the differential input channel data register Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Further the Interrupt Polarity Register will have no effect if the Change of State COS interrupt type is configured by the Interrupt Type Configuration Register The Interrupt Polarity register at the base address offset 801CH is used to control differential channels 8 through 15 as mapped in the Interrupt Enable Register For example channel 8 is controlled via data bit 0 Bits 8 to 15 are not used and will always read as 0 All bits are set to 0 following a reset which means that the inputs will cause interrupts when they are logic low provided they are enabled for interrupt on level Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 8 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 4 0 THEORY OF OPERATION DIFFERENTIAL INPUT OUTPUT LOGIC CMOS DIGITAL INPUT OUTPUT LOGIC This section contains information regarding the hardware of the board A description of the basic functionality of the circuitry used on the board is also provided Note that each section does not necessarily apply to every model Refer to table below to determine the appropriate sections MODEL Type Interrupts E AXM D02 30 30 Differential 8 Channels 22 EUM amp 003 16 CMOS Digital 8 Channels
21. hannels 002 of Bi directional CMOS Transceivers Direction controlled as pairs of channels Reset Power Up Condition All Digital Channels Default to Input e Digital l O DC Electrical Characteristics e Vou 3 8V minimum e 0 55V maximum lou 32 lou 32 0 e 3 5V minimum e Vy 1 5V maximum e Driver Receiver Input to Output Delay 4ns Typical Pull up Resistors 10K pull up resistors to 5 are installed on each CMOS line Channel Configuration 30 Channels AXM D04 Bi directional LVDS signals are independently direction controlled e 247m V Min 454mV Max LVDS Driver Output Voltage with 50Q load e 1 37 V Max Common Mode Output Voltage e 50 mV Min to 50mV Max LVDS Input Threshold Voltage e Interface with either standard LVDS TIA EIA 644 or M LVDS TIA EIA 899 for Multipoint Data Interchange e Driver Propagation Delay Time 2 7ns Maximum e Driver Output Signal Transition Time 1 0ns Maximum e Receiver Propagation Delay Time 4 5ns Maximum e Receiver Output Signal Transition Time 1 5ns Maximum e Maximum Data Rate 150MHz 4 Meters shielded cable at 25 Termination Resistors Non removable 100Q termination resistors are in place for each of the differential channels Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board 2 D Channel Configuration
22. ht possible interrupting channels A 0 bit selects interrupt on level An interrupt will be generated when the input channel level specified by the Interrupt Polarity Register occurs i e Low or High level transition interrupt A 1 bit means the interrupt will occur when a Change Of State COS occurs at the corresponding input channel i e any state transition low to high or high to low The Interrupt Type Configuration register at base address 8018H is used to control channels 8 through 15 as mapped in the Interrupt Enable Register For example channel 8 is controlled via data bit 0 Bits 8 to 15 are not used and will always read as 0 All bits are set to 0 following a reset which means that if enabled the inputs will cause interrupts for the levels specified by the Interrupt Polarity Register Channel read or write operations use 8 bit 16 bit or 32 bit data transfers Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register Interrupt Polarity Register Read Write Base Addr 801C The Interrupt Polarity Register determines the level that will cause a channel interrupt to occur for each of the channels enabled for level interrupts 0 bit specifies that an interrupt will occur when the corresponding input channel is low i e a 0 in the differential input channel data register A 1 bit means that an interrupt will occur when the input channel is hi
23. iguration Front Panel Field I O Connector Digital I O Mezzanine Board Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the system boards plus the installed Acromag board within the voltage tolerances specified Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air
24. ital Mezzanine Board 27 TO FRONT VO BASEBOARD INTERFACE P3 DIFF CHANNEL 29 DIFF DIRECTION CONTROL TERMINATION RESISTOR 10 DIER CHANNEL 29 NOT PROVIDED LVTTL VO TO FPGA 30 RS485 RS422 DIFFERENTAL INPUT OUTPUT DIFF CHANNEL 0 CHANNELS DIFF DIRECTION CONTROL iy 10K TERMINATION RESISTOR DIFF CHANNEL 0 NOT PROVIDED AXM D02 BLOCK DIAGRAM 4502 051A FRONT INTERFACE DIFF CHANNEL 29 EM DIRECTION CONTROL Pes q 2 DIFF CHANNEL 29 TERMINATION RESISTOR NOT PROVIDED 10K 22 RS485 422 p DIFFERENTIAL INPUTIOUTPUT DIFF CHANNEL 8 e DIRECTION CONTROL TO FPGA TERMINATION RESISTOR DIFF CHANNEL 8 NOT PROVIDED bong Z5 Y DIG CHANNEL 15 DIRECTION CONTROL 10K DIG CHANNEL 15 lt gt lt gt 10K 16 CMOS P DIG CHANNEL 0 DIGITAL e Y DIRECTION CONTROL INPUT OUTPUT 45V gt CHANNELS a DIG CHANNEL 0 10 gt AXM D 3 BLOCK DIAGRAM 4502 051B Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 28 AXM D Series and AXM EDK User s Manual Digital I O Mezzanine Board CONNECTOR FRONT I O TO PMC INTERFACE BASEBOARD P2 DI
25. m Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 22 AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 6 0 Single AXM Board SPECIFICATIONS Height 11 5 mm 0 453 in Stacking Height 8 0 mm Wes Depth 31 0 mm 1 220 in PHYSICAL Width 74 0 mm 2 913 in Board Thickness 0 8 mm 0 031 in Unit Weight Including all A EU Kon 1 n 2 0 mounting hardware 003 1 39302 0 0395Kg 004 1 3902 0 0394Kg Connectors e AXN D Front Field 68 pin SCSI 3 female receptacle male header AMP 5787394 7 or equivalent e AXM EDK Front Field I O 14 2mm double row male header standard Xilinx JTAG header 34 pin 0 1 double row header Table 6 1 Power Requirements for Example Power Requirements Design 002 460 900 700m 004 162 330 AXM EDK Not Used 002 Not Used 003 80mA Vasy AMD PA CSS AXM D04 Not Used 1 AXM EDK Not Used Power source is the base board Current draw is for AXM module only 2 With 7 of I O as inputs 1 2 as outputs and at 25 C 3 The AXM EDK has no components that draw power It is simply a pass though board 4 Floating or shorted will have higher current draw Operating Temperature 40 C to 85 Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 150 C Non Isolated Logic and field co
26. mmons have a direct electrical connection ENVIRONMENTAL Radiated Field Immunity Complies with EN61000 4 3 3V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 with no register upsets Conducted R F Immunity CRFI Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with no register upsets Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 23 Electromagnetic Interference Immunity EMI No register upsets occur under the influence of EMI from switching solenoids commutator motors and drill motors Surge Immunity Not required for signal I O per European Norm EN50082 1 Electric Fast Transient EFT Immunity Complies with EN61000 4 4 Level 2 0 5KV at field I O terminals and European Norm EN50082 1 Electrostatic Discharge ESD Immunity Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge Level 2 4KV enclosure port contact discharge Level 1 2KV I O terminals contact discharge and European Norm EN50082 1 Radiated Emissions Meets or exceeds European Norm EN50081 1 for class B equipment Shielded cable with I O connections in shielded enclosure are required to meet compliance Mean Time Between Failure MIL HDBK 217F Notice 2 at 25 C 002 3 559 276 Hours 003 3 921 522 Hours 004 6 534 197 Hours AXM E
27. nd Software Reset Register Read Write Base Addr 8000H RESET REGISTER This read write register is used the issue a software reset view and clear pending interrupts and to identify the attached AXM module It may also provide other functions that are defined by the base board Writing a 1 to bit 31 of this register will cause a software reset effecting both the PMC base board and all of the AXM series registers Bits 15 to 13 are used for AXM identification code Bits 0 to 7 or this register reflect the status of each of the Differential I O channels 8 to 15 A Read of this bit reflects the interrupt pending status Read of a 1 indicates that an interrupt is pending for the corresponding differential channel Write of a logic 1 to this bit will release the corresponding differential channel s pending interrupt Writing 0 to a bit location has no effect a pending interrupt will remain pending o Differential Channel 8 interrupt Pendng Glear 6 Differential Channel 14 Interrupt PendingiClear AXM Identification bits Read Only 15 13 oor oor 37 Reset Note that if no at module is the register will still read 001 Itis up to the end user to differentiate if no mezzanine module is attached 2 All other 3 bit values are reserved for future use 3 Bitfunction is defined by the base PMC Module This register can be written with either 8 bit 16 bit or 32 bi
28. p Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers DIFFERENTIAL Interrupt Enable Register Read Write INTERRUPT Base Addr 8014H REGISTERS The Interrupt Enable Register provides a map bit for each differential channel from 8 to 15 A 0 bit will prevent the corresponding input channel from generating an external interrupt A 1 bit will allow the corresponding channel to generate an interrupt The Interrupt Enable register at the base address offset 8014H is used to control channels 8 through 15 via data bits O to 7 Bits 8 to 15 are not used and will always read as 0 All channel interrupts are disabled set to 0 following a power on or software reset Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Additional steps may be required to enable interrupts Refer to the PMC base module s User s Manual for further information Interrupt Register Mapping D7 Ds a D3 Di _ Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 1 7 DIFFERENTIAL Interrupt Type COS or H L Configuration Register INTERRUPT Read Write Base Addr 8018 REGISTERS The Interrupt Type Configuration Register determines the type of input channel transition that will generate an interrupt for each of the eig
29. p www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 3 6 0 SPECIFICATIONS TABLE OF CONTENTS PHYSICAL 22 ENVIRONMENTAL ecce 22 DIFFERENTIAL 23 DIGITAL INPUT OUTPUT eeenennnnnnttnnnt 24 LVDS 24 LVTTL 25 APPENDIX CABLE MODEL 5028 432 26 TERMINATION PANEL MODEL 5025 288 26 DRAWINGS 4502 051A AXM D02 BLOCK DIAGRAM 27 4502 051B AXM D03 BLOCK DIAGRAM 27 4502 051 AXM D04 BLOCK DIAGRAM 28 4502 056 AXM EDK I O LOCATION DRAWING 28 4502 055 AXM MECHANICAL ASSEMBLV 29 4501 919 CABLE 5028 432 SHIELDED 29 4501 920 TERMINATION PANEL 5025 288 30 Trademarks are the property of their respective owners Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 4 AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 1 0 GENERAL INFORMATION Table 1 1 AXM D Series and AXM EDK Models KEY FEATURES The AXM D series of daughter boards offer numerous digital options for Front I O to Acromag s line of re configurable PMC modules The 003 provides 22 differential amp 16 CMOS input o
30. pair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Acromag s application engineers can also be contacted directly for technical assistance via telephone or email Contact information is located at the bottom of this page When needed complete repair services are also available Digital I O Mezzanine Board 2 1 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP www acromag co
31. r CARD CAGE CONSIDERATIONS 6 any errors that may appear in BOARD CONFIGURATION 6 this manual makes no Default Hardware Configuration 6 commitment to update or Front Panel l O e 6 keep current the information Non Isolation Considerations 12 contained in this manual No part of this manual may be 3 0 PROGRAMMING INFORMATION copied or reproduced in any form without the prior written MEMORY MAP eese 12 consent of Acromag Inc Board Status and Reset Register 13 Differential I O Registers 14 Digital Input Output Registers 15 Differential Interrupt 16 4 0 THEORY OF OPERATION DIFFERENTIAL INPUT OUTPUT LOGIC 18 DIGITAL INPUT OUTPUT LOGIC 18 LVDS INPUT OUTPUT LOGIC 19 LVTTL DIRECT INTERFACE eee 19 JTAG INTERFACE eere eene 19 INTERRUPT LOGIC 19 BASE BOARD CONNECTION 20 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSITANCE 21 PRELIMINARY SERVICE PROCEDURE 21 WHERE TO GET 21 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com htt
32. rd provides the standard Xilinx JTAG interface to allow direct programming of the FPGA and an interface with ChipScope Programmable Change of State Level Interrupts Example code provides interrupts that are software programmable for any bit Change Of State or level on 8 channels e Example Design The example VHDL design provided in the base board EDK includes control of all and eight Change Of State interrupts Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board D The AXM D models I O is accessed via a 68 pin SCSI front panel SIGNAL INTERFACE connector PRODUCTS Cables and a termination panel are available to interface with these boards Cable Model 5028 432 A 2 meter round 68 conductor shielded cable with a See the Appendix for male SCSI 3 connector at both ends and 34 twisted pairs This cable is further information on these used for connecting the board to Model 5025 288 termination panels products For optimum performance use the shortest possible length of shielded cable Termination Panel Model 5025 288 DIN rail mountable panel provides 68 screw terminals for universal field I O termination Connects to Acromag board via SCSI 3 to twisted pair cable described above ENGINEERING DESIGN Acromag does not provide an engineering design kit specifically for the KIT AXM D modules
33. round loops caused by multiple ground connections Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 2 AXM D Series and AXM EDK User s Manual 3 0 PROGRAMMING INFORMATION AXM EDK amp AXM D GENERIC MEMORY MAP Table 3 2 Memory Map 1 This address space is not defined for this module This space may be used on the base PMC Module Refer to the base PMC module User s Manual for further information 2 These registers have bits that are reserved for the base PMC module See the register definition later in this manual for further details 3 The bits used in these registers varies for each model Refer to the register descriptions in the following pages for specific module mapping 4 The board will return 0 for all addresses that are Not Used Digital I O Mezzanine Board This Section provides the specific information necessary to program and operate the boards These models are daughter cards intended only for use on specific Acromag PMC modules As such only a small portion of I O memory space is currently reserved for operation of the daughter card The remaining memory space is defined in the base boards User s Manual The generic memory space address map for the board is shown in Table 3 2 The actual bit mapping in the individual registers varies by the mezzanine module and are detailed in the register descriptions later in this manual Note that the ba
34. rs include a 100 ohm termination resistor Signals received are converted from the LVDS voltages to the LVTTL levels required by the FPGA Likewise LVTTL signals are converted to the TIA EIA 644 LVDS voltages for data output transmission The direction control of the LVDS channels is independently controlled The AXM EDK has a total of 46 30 General Purpose and 16 auxiliary channels of LVTTL These I O provide a direct connection through the mezzanine connector to the adjoining FPGA There no intermediate buffers on the I O As such care must be taken to limit overshoot to 3 6V and to prevent ESD or the FPGA on the PMC base board may be damaged The I O on the AXM EDK are mapped to simulate the various types of I O that can be found on the AXM D series modules Therefore the same registers can be used to simulate the Field on the AXM EDK The 30 general purpose map to the 30 differential I O on the 002 the 22 differential on the 003 and 30 LVDS I O on the AXM DO4 The 16 auxiliary map to the 16 differential signal on the AXM DOS Note that regardless of which AXM D module is being emulated the AXM EDK are all 3 3V LVTTL The AXM EDK model has a front field I O Xilinx JTAG header It readily JTAG INTERFACE connects to any compatible Xilinx programming system such as the MULTIPro Tool or Parallel Cable programming system In general the JTAG interface pins connect only to the Xilinx FPGA
35. se address from the base PMC module in memory space must be added to the addresses shown to properly access the board registers Register accesses as 32 16 and 8 bits in memory space are permitted Base D15 Base Addr DOO Addr Board Status Register and Software Reset 29 0 Differential amp EDK I O Register Direction Register 5 Differential amp EDK Channels 29 0 800F 15 0 Digital I O Register 800C 8013 Direction Register Digital Channels 15 0 Interrupt Enable Differential Ch 15 8 Interrupt Type Differential Ch 15 8 Interrupt Polarity Differential Ch 15 8 Not Used 8010 8014 8017 Not Used 801B Not Used 801F Not Used 8018 801 8023 8020 8027 Not Used 8024 802B Not Used 8028 602 02C Reserved for base Module 1FFFFF FFFFC Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 1 3 This memory map reflects byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses BOARD STATUS AND Board Status a
36. t data transfers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 4 AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board DIFFERENTIAL Differential amp EDK Input Output Registers Read Write INPUT OUTPUT Base Addr 8004H REGISTERS AXM D differential channels and the AXM EDK LVTTL channels may be individually accessed via this register at the carrier base address 8004H This includes all 30 differential channels on the AXM DO2 22 differential channels on the 003 30 LVDS channels on the AXM D04 and 30 general purpose LVTTL channels on the AXM EDK Each channel is controlled by its corresponding data bit as shown in the register mapping table below Channel input signal levels are determined by reading this register Likewise channel output signal levels are set by writing to this register Note that the data direction input or output must first be set via the Differential Direction register at base address plus 8008H Mods Differential VO Register Mapping D30 o 08 D26 55 oa n2 D DH 50 Div 56 Di bis biz Dii Dio D D D6 D5 D4 DB D2 Di DO Diff Channels 0 7 are not used in this module DifChamelsO Zarnotusediniismodue Channel read write operations use 8 bit 16 bit or 32 bit data transfers with the lower order
37. tions on the AXM EDK Table 24a AXM EDK Board Field VO Pin Connections Pin Description Pin Pin Description Pin COMMON V Chame 5 lVIILChame3 6 ViTLChamel4 7 iVi Chanels 8 VL Chanels 9 LVTTL Channel 310 lVITLChame i8 2 LVTTL Channel i9 22 lVITLChame20 28 LVTTL Chamel 24 lVITLChame22 25 LVITLOhannd28 26 lVITLChame 24 27 LVITLOhannd25 28 Table 2 4b AXM EDK Board Field JTAG Pin Connections PinDescripion Pin PinDescripion Pin COMMON _ 37 5 COMMON 7 COMMON o Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com AXM D Series AXM EDK User s Manual Digital I O Mezzanine Board 1 1 AXM EDK Front I O Auxiliary LVTTL I O Pin Connections SIP Table 2 4c AXM EDK SIP 1 51 SIP 2 S2 Auxiliary Pin Connections Pin Description Pin Description Pin AUX Channel 8 AUX Channel 9 AUX Channel 10 AUX Channel 11 AUX Channel 12 5 6 8 6 AUX Channel 14 AUXChame7 8 AUXChannel15 8 The board is non isolated since there is electrical continuity between the Non Isolation logic and field I O grounds As such the field I O connections are not Considerations isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and g
38. utput channels on the Front for compatible Acromag PMC modules The data direction input output for each channel can be independently controlled Eight change of state interrupt channels are provided on the least significant eight differential channels The AXM EDK board sold with the PMC base boards Engineering Design Kit provides the standard Xilinx JTAG header as well as direct connections to the Xilinx FPGA These general purpose LVTTL Low Voltage TTL I O points allow the user to emulate AXM D modules while using ChipScope OPERATING Front I O MODEL Front Type Conector auci un AXM AXM D02 30 30 Differential 68 685051 ETSI to REGEM o o AXM D04 30 LVDS 68 68565 40 C to 85 C to 85 C Std JTAG amp o o AXM EDK JTAG amp LVTTL 34 0 1 Header 49 C to 85 C Multifunction Modules Various modules allows users to select the Front required for their application e Differential Input Output Channels Differential RS485 RS422 can be configured for input or output with independent direction control e Digital Input Output Channels Interface with 5V compliant input output CMOS channels which can be configured as input or output with independent direction control e LVDS Input Output Channels Low voltage differential signaling can be configured for input or output with independent direction control e Xilinx JTAG Interface The EDK boa

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