STM8S103xx STM8S105xx
Contents
1. 1 2 4 kHz beep di Reset block ai Tai Mhz K gt Clock controller Reset qx Reset lt RC int 16 MHz Detector POR BON 4 RC int 128 kHz Clock to peripherals and core KE Window WDG STM8 CORE KE 5 gt Independent WDG Single wire Up to 8 Kbytes debug interf Debug SWIM p y lt gt program Flash Bd 2 Q 400 Kis lt 7 Pc lt gt s 1 Kbytes i RAM ke S 8 Mbit s Sei L gt 2 Boot ROM D o LIN master L 2 Y 16 bit advanced control KD SPI emul USART timer TIM1 Up to 7 CAPCOM s gt 16 bit general purpose aed channels timer TIM2 8 bit basic timer Up to 7 channels 10 bit ADC TIM4 extended features Beeper 5 gt r gt AWU timer 9 56 Product overview STM8S103xx STM8S105xx 4 4 1 10 56 Product overview The following section intends to give an overview of the basic features of the STM88103 105 access line functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RMOO16 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiencv and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 802. Bottom view 42 ME Table 22 32 lead very thin fine pitch quad flat no lead package mechanical data mm inches Dim Min Typ Max Min Typ Max A 0 80 0 90 1 00 0 0315 0 0354 0 0394 Al 0 0 02 0 05 0 0008 0 0020 A3 0 20 0 0079 b 0 18 0 25 0 30 0 0071 0 0098 0 0118 D 4 85 5 00 5 15 0 1909 0 1969 0 2028 D2 3 20 3 45 3 70 0 1260 0 1457 E 4 85 5 00 5 15 0 1909 0 1969 0 2028 E2 3 20 3 45 3 70 0 1260 0 1358 0 1457 e 0 50 0 0197 L 0 30 0 40 0 50 0 0118 0 0157 0 0197 ddd 0 08 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits 1 TBD to be determined d STM8S103xx STM8S105xx Package characteristics 8 1 3 TSSOP package mechanical data Figure 34 TSSOP 20 pin 4 40 mm body 0 65 mm pitch A A Cr e TSSOP20 M Table 23 TSSOP 20 pin 4 40 mm body 0 65 mm pitch mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 2 0 0472 Al 0 05 0 15 0 002 0 0059 A2 0 8 1 1 05 0 0315 0 0394 0 0413 b 0 19 0 3 0 0075 0 0118 CP 0 1 0 0039 c 0 09 0 2 0 0035 0 0079 6 4 6 5 6 6 0 252 0 2559 0 2598 6 2 6 4 6 6 0 2441 0 252 0 2598 E1 4 3 4 4 4 5 0 1693 0 1732 0 1772 e 0 65 0 0256 L 0 45 0 6 0 75 0 0177 0 0236 0 0295 L1 1 0 0394 a 0 8 0 8 1
3. x o tr E 5 z ES d DONT OOo 999 OG ere o6 2229 23 EE OOR LL wen a 00 oq DH SEER FONG Oo ole A OOOO020o000004uvu D unn nununnun 1 1 MANrTODARONM st CO zt CO CO CO CO CN QV QU ANA NAN AN e N D e N B 8 N e 8 2 3 E o E 2 wa re t 3 op e st T Ze ES GER RER ER EE TA GES JARE BOER ree o gt 5 gt 9a me ZZ sto gt a o2 gt 28 Og o 93d 6NIV 084 ONIV LOON LANI LBd LNIV ZOON LLL 28d CNIV EOON WIL Cad ENIV HLA HANI vAd vNIV SAd SNIV 9Ad ONIV Zad ZNIV VSSA vada HS high sink capability 22 56 STM8S103xx STM8S105xx Pinouts and pin description 4 Figure 7 STM8S105 LQFP VQFN 32 pin pinout NRST OSCIN PA1 OSCOUT PA2 Vss VCAP Von Vppio AIN12 PF4 L1 o Joo ROND 1 9 10111213141516 x oc m z E ES 8 aTa 5 N l Haz mar Q 52890 9 EKOOO O9 INI m l Il lN No zc rp2z2czzc SSEELETE a4zzoemooocov ESJLLLLL RoW st CO Oe e ANANANAA con e De Die De De 3231 30292827 26 25 e 24 VDDA Vssa N5 PB5 N4 PB4 N3 PB3 N2 PB2 N1 PB1 NO PBO I2C SCL A TIM1 ETR AI TIM1 NCC3 A TIM1 NCC2 A TIM1_NCC1 A I2C SDA A PC7 SPI_MISO PC6 SPI MOSI PC5 SPI_SCK PC4 HS TIM1_CC4
4. 14 4 8 Auto wake upcounter 15 4 9 EE EE EE E a H 15 4 10 TIM1 16 bit advanced control timer 15 4 11 TIM2 16 bit general purpose timer 15 4 12 TIM4 8 bitbasictimer 15 4 13 Analog digital converter ADC 17 4 14 Communication interfaces 17 4314 1 USART IKI AAA eae 18 4 14 2 LINUART 2 23 4 ii aea a sh aa 18 4 14 3 SPI iu k EE A B tat 19 AMA EG EE 20 5 Pinouts and pin description 21 5 1 Package pinouts 21 5 2 Pin description 25 5 2 1 Alternate functionremapping 30 6 Option Bytes aaa EE ra Dd 31 2 56 DI STM8S103xx STM8S105xx Contents 7 10 11 Electrical characteristics 35 7 1 Parameter conditions 35 7 1 1 Minimum and maximum values 35 7 1 2 Typical values IA eee 35 7 1 3 Typical curves IIIA Re ee ee ee Re a EE dk eee 35 7 1 4 Loading capacitor 0 ka dieni eren 35 7 1 5 Pin input voltage 36 7 2 Absolute maximum ratings 36 7 3 Operating conditions
5. 38 7 3 1 VO port pin characteristics 39 7 3 2 Reset pin characteristics 44 Package characteristics 46 8 1 Package mechanical data 47 8 1 1 LQFP package mechanical data 47 8 1 2 QFN package mechanical data 50 8 1 3 TSSOP package mechanical data 51 Ordering information 52 STM8 development tools 53 10 1 Emulation and in circuit debugging tools 53 10 2 Software e EE 54 10 2 1 STMB8toolset ini KUA eee d 54 10 2 2 Candassemblytoolchains 54 10 3 Programming tools 54 Revision history 55 3 56 List of tables STM8S103xx STM8S105xx List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 4 56 Device SUMMarV iss Bee b de dee aei arsa EE bos aes Mee a a Y 1 STM8S103 105 access line features 7 STM8 TIM timer feature compar
6. 128 kHz Low Speed Internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS 13 56 Product overview STM8S103xx STM8S105xx 4 6 4 7 14 56 and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Available frequencies are 8 MHz 4 MHz or 1 MHz Power management For efficent power management the application can be put in one four different low power modes Vou can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode in this mode the CPU is stopped but peripherals are kept running The wake up is performed bv an internal or external interrupt or reset e Fastactive halt mode in this mode the CPU and peripheral clocks are stopped An internal wake up is generated at programmable intervals bv the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is more than in slow active halt mode but the wake up time is faster Wake up is triggered bv the in
7. 973 STM8S103xx STM8S105xx Access line STM8S 8 bit MCU up to 32 Kbytes Flash 10 bit ADC timers USART SPI 1 C Features Core m Max fcopy up to 16 MHz m Advanced STM8 core with Harvard architecture and 3 stage pipeline m Extended instruction set Memories m Program memory Up to 32 Kbytes Flash data retention 20 years at 85 C after 1 kcycles m RAM Up to 2 Kbytes Clock reset and supply management m 3 0 to 5 5 V operating voltage m Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal 16 MHz RC Internal low power 128 kHz RC m Clock security system with clock monitor m Power management Low power modes Wait Active halt Halt Switch off peripheral clocks individually m Permanently active low consumption power on and power down reset Interrupt management m Nested interrupt controller with 32 interrupts m Up to 37 external interrupts on 6 vectors Timers W 2x 16 bit general purpose timers with 2 3 CAPCOM channels IC OC or PWM m Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization m 8 bit basic timer with 8 bit prescaler Auto wake up timer m 2 watchdog timers Window watchdog and independent watchdog June 2008 Preliminary Data LQFP44 10x10 VFQFN32 5x5 LQFP32 7x7 TSSOP20 Communications interfaces m U
8. X Port E1 IEC clock 40 36 PEO CLK CCO vo xxx losi x x Port Eo dE SES TIM1_BKIN 41 37 25 PDO TIM3_CC2 1 O X X X HS OS3 X X Port DO Timer 3 channel 2 DARA CLK_CCO AFR2 42 38 26 PD1 SWIM vol x x x Hs Oo4 x x Port D1 SWIM data interface 43 39 27 PD2 TIM3_CC1 1 O X X X HS OS3 X X Port D2 Timer 3 channel 1 Ce 44 40 28 JPD3 TIM2 CC2 VO X X X HS OS X X Port D3 Timer 2 channel2 PE 45 41 29 PDA TIM2_CC1 BEE jo x x x luslos x X Port D4 Timer 2 channel 1 PEEP output P AFR7 46 42 30 PD5 LINUART_TX vol X X X O1 X X Port Ds HNUART data transmit 47 43 31 PDG LINUART BN I O X X X O1 x X Port De LINUART data receive 48 44 32 PD7 TLI VO X X X O1 X X Port D7 Top level interrupt 1 In the open drain output column T defines a true open drain VO P buffer and protection diode to Vpp are not implemented ky 27 56 Pinouts and pin description STM8S103xx STM8S105xx Table 6 Pin description for STM8S103 MCUs Pin number input output Alternate i function gt 9 2 9 Default alternate after aig Pin name EI o gt x 3r L N EI g E ET 5 function remap gg S 37 ala c2 4 0 sS g E c ola ts option 29 5 5 565 lt bit L H c e x S l 1 3 INRST VO X Reset 2 4 PA1
9. X Port E7 Analog input 9 25 23 17 PE5 SPI_NSS volx x x lot x x Port Es SES Timer 1 channel 1 PC1 TIM1_CC1 26 24 18 LINUART_CK VO X X X HS O3 X X Port C1 LINUART synchronous clock 27 25 19 PC2 TIM1_CC2 VO X X X HS O3 X X Port C2 Timer 1 channel 2 28 26 20 PC3 TIM1_CC3 VO X X X IHS O3 X X Port C3 Timer 1 channel 3 29 21 PC4 TIM1_CC4 1 O X X X HS O3 1 X X Port C4 Timer 1 channel 4 30 27 22 PC5 SPI_SCK 1 O X X X OS X X Port C5 SPI clock 311281 Vssio 2 S 1 O ground 32 29 Vppio 2 S VO power supply 33 s0 23 PCe SPL mosi vo l x x x o3 X x Port ce SP master out slave in SPI master in 34 31 24 PC7 SPI MISO O X X X O3 X X Port C7 slave out 35 32 PGO VO O1 Port GO 36 33 PG1 1 O X X O1 X X Port G1 37 PES TIM1_BKIN O X X X O1 X X Port E3 LL 38 34 JPE2 C SDA VO X X X O1 TO X Port E2 I C data 26 56 DI STM8S103xx STM8S105xx Pinouts and pin description Table 5 Pin description for STM8S105 MCUs continued Pin number Input Output M z ER Alternate o x i ois Pin name 8 gt gt E f ge Default alternate function after Q Q Q Falls gt aanu 5 function remap SG ala 5S35EESS A Ss option bit Al 3 2 IE EK x l 39 35 JPE1 I C SCL O X X X O1 T
10. X X HS OS X X Port D7 Timer 1 channel 4 1 In the open drain output column T defines a true open drain I O P buffer and protection diode to Vpp are not implemented ky 29 56 Pinouts and pin description STM8S103xx STM8S105xx 5 2 1 30 56 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of 8 AFR alternate function remap option bits Refer to Section 6 Option bytes on page 29 When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see GPIO section of the family reference manual RM0016 STM8S103xx STM8S105xx Option bytes 6 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the address shown in Table 7 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode exce
11. 12 00 0 4724 E1 10 00 0 3937 e 0 80 0 0315 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 0 0177 0 0236 0 0295 L1 1 00 0 0394 1 Values in inches are converted from mm and rounded to 4 decimal digits ky STM8S103xx STM8S105xx Package characteristics Figure 32 32 pin low profile quad flat package 7 x 7 D D1 Table 21 32 pin low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 60 0 0630 Al 0 05 0 15 0 0020 0 0059 A2 1 35 1 40 1 45 0 0531 0 0551 0 0571 b 0 30 0 37 0 45 0 0118 0 0146 0 0177 C 0 09 0 20 0 0035 0 0079 D 9 00 0 3543 D1 7 00 0 2756 E 9 00 0 3543 E1 7 00 0 2756 e 0 80 0 0315 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 0 0177 0 0236 0 0295 L1 1 00 0 0394 1 Values in inches are converted from mm and rounded to 4 decimal digits Ky 49 56 Package characteristics STM8S103xx STM8S105xx 8 1 2 50 56 QFN package mechanical data Figure 33 32 lead very thin fine pitch quad flat no lead package 5 x 5 Seating plane C
12. 125 C 1 75 1 25 0 75 o a 10 15 20 25 lo mA Figure 20 Typ Vo 8 Vpp 3 3 V high sink Figure 21 Typ VoL Vpp 5 0 V high sink ports ports 1 5 kika 1 5 Ue 25 C a 25 C 1 25 85 C 1 25 85 C 125 C 125 C 1 1 0 75 075 gt 0 5 0 5 0 25 0 25 A OF OF 0 2 4 6 8 10 12 14 0 5 10 15 20 25 lo mA lo mA 42 56 STM8S103xx STM8S105xx Electrical characteristics Figure 22 Typ Vpp z Vou Vpp 3 3 V standard ports Figure 23 Typ Vpp 7 Vou Vpp 5 0 V standard ports 5 40 C 25 C 1 75 85 C 1 5 125 C 1 25 3 gt 0 75 0 5 0 25 oF 0 1 2 3 4 5 6 7 lou MA 40 C 25C 1 75 85 C 1 5 125 C gt 1 25 3 gt 1 8 gt 0 75 0 5 p 0 25 OF 0 2 4 6 8 10 12 lon MA Figure 24 Typ Vpp Vou Vpp 3 3 V high sink ports Figure 25 Typ Vpp 3 Vou Vpp 5 0 V high sink ports 40 C 5 40 C 25 C 25C 1 75 85 C 173 85 C 1 5 125 C 15 125 C 1 25 1 25 q i 8 gt 0 75 0 75 0
13. 5 0 5 0 25 0 25 0 OF 0 2 4 6 8 10 12 14 0 5 10 15 20 25 lo mA lon mA ki 43 56 Electrical characteristics STM8S103xx STM8S105xx 7 3 2 44 56 Reset pin characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 18 NRST pin characteristics Symbol Parameter Conditions Min b Max Unit ViL NRST NRST Input low level voltage 2 Vss TBD ViH NRST NRST Input high level voltage 2 TBD Vpp V VOL NAST NRST Output low level voltage 2 lo TBD mA TBD RPU NAST NRST Pull up resistor 9 30 40 60 kQ VENRST NRST Input filtered pulse TBD ns VNF NRST NRST Input not filtered pulse TBD us 1 TBD to be determined 2 Data based on characterization results not tested in production 3 The Rpy pull up equivalent resistor is based on a resistive transistor 4 Data guaranteed by design not tested in production Figure 26 Typical NRST Vu and Vum vs Vpp 4 temperatures A 40 C 250C 54 85 C 125 C 4 gt E 2 O01 ZZ 1 0 T T T T T r 2 5 3 3 5 4 4 5 5 5 5 Von V d STM8S103xx STM8S105xx Electrical characteristics Figure 27 Typical NRST pull up resistance Rpu Vs Vpp 4 temperatures 60 40 C m 25 C E 55 85 C B 125 C o 50 2 S Zm e e g 45 E 3 40 D
14. F4 Analog input 12 9 PAS TIM2 CC3 O X X X O1 X X Port A3 Timer 2 channel3 a 10 9 PA4 VO O3 Port A4 111101 PA5 O X X X O3 X X Port A5 12 11 PA6 VO X X X O3 X X Port A6 13 12 9 Vppa S Analog power supply 14 13 10 Vssa S Analog ground 15 14 PB7 AIN7 O X X X O1 X X Port B7 Analog input 7 Ky 25 56 Pinouts and pin description STM8S103xx STM8S105xx Table 5 Pin description for STM8S105 MCUs continued Pin number Input Output c z A Alternate Q x i ois Pin name 2 D gt E f ge Default alternate function after Q Q Q FEB S Si aa 5 function remap S6586 3 25 5809 option bit 1 2J 2 sir s x ui 16 15 PB6 AIN6 O X X X O1 X X Port B6 Analog input 6 I C SDA 17 16 11 PB5 AIN5 OJXIXI X O1 X X Port B5 Analog input 5 AFR6 PC_SCL 18 17 12 PB4 AIN4 VO X X X O1 X X Port B4 Analog input 4 AFR6 19 18 13 JPB3 AIN3 O X X X O1 X X Port B3 Analog input 3 um 20 19 14 PB2 AIN2 O X X X O1 X X Port B2 Analog input oa 21 20 15 PB1 AIN1 O X X X O1 X X Port B1 Analog input 1 TIM NGO AFR5 22 21 16 PBO AINO volxixix O1 X X Port BO Analog input O ea 23 PE7 AIN8 VO X X X O1 X Port E7 Analog input 8 24 22 PEG AIN9 VO X X X O1 X
15. Negative injection disturbs the analog performance of the device 4 When several inputs are submitted to a current injection the maximum Zl piv is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with lin Pi maximum current injection on four I O port pins of the device Table 12 Thermal characteristics Storage temperature range 65 to 150 Maximum junction temperature 150 K 37 56 Electrical characteristics STM8S103xx STM8S105xx 7 3 38 56 Operating conditions Table 13 General operating conditions Symbol Parameter Conditions Min Max Unit fopu Internal CPU clock frequency 0 16 MHz Vpp Vpp 1o Standard operating voltage 3 0 5 5 V LQFP48 TBD Power dissipation at S TBD Pp Ta 85 C for suffix 6 LQFP32 TBD mW or TAS 125 C for suffix 3 VFQFN32 TBD TSSOP20 TBD Ambient temperature for 6 Maximum power dissipation 40 85 C R suffix version Low power dissipation 40 105 e A i MT Ambient temperature for 3 Maximum power dissipation 40 125 C suffix version Low power dissipation 2 40 TBD C 6 suffix version 40 105 C Tj Junction temperature range 3 suffix version 40 TBD C 1 TBD to be determined 2 In low power dissipation state Ta can be extended to this range as long as Ty does not exceed T max Figure 12 fcpumax versus Vpp fo
16. OSCIN vo x X X 01 X X Port A1 Resonator crystal in 3 5 PAZ OSCOUT vo x x Lx lot x X PortA2 eo crystal 4 6 Vas S Digital ground 5 7 VCAP 1 8 V regulator capacitor 6 8 Vpp S Digital power supply SPI 7 9 IPA3 TIM2 CC3 SPI NSS lO X X X IHSIOSI X X Port A3 Timer 2 channel 3 master sla ve select 8 PF4 1 O X X X O1 X X Port F4 9 JPB7 1 O X X X O1 X X Port B7 10 PB6 1 O X X X O1 X X Port B6 11 10 PB5 I2C SDA VO X X X O1 TO X Port B5 PC data 12 11 PBA I2C SCL 1 O X X X O1 TO X Port B4 I2C clock 13 PB3 TIM1_ETR o x x X HS O3 X X Port B3 SE SR 14 PB2 TIMI_NCC3 vol x X x IHslos X X Port ga Timer 1 inverted channel 3 Analog input 1 15 PB1 AIN1 TIM1_NCC2 lO X X X HS O3 X X Port B1 Timer 1 inverted channel 2 Analog input 0 16 PBO AINO TIM1_NCC1 1 O X X X HS O3 X X Port BO Timer 1 inverted channel 1 SPI master slave 17 PE5 SPI_NSS VO X X X IHSIOSI X X Port E5 select 18 PCI TIM1 CC1 vo x x x IHslosl X X PortCi pene cane 19 PCZ TIM1_CC2 vo x x x uslos X X Port c2 ee PC3 TLI TIM1 CC3 Top level interrupt USART 20112 VOI X X X HS O3 X X Port C3 Ti USART_CK r a channel clock 28 56 ky STM8S103xx STM8S105xx Pinouts and pin description Table 6 Pi
17. Values in inches are converted from mm and rounded to 4 decimal digits 51 56 Ordering information STM8S103xx STM8S105xx 9 52 56 Ordering information Figure 35 STM8S103 105 access line ordering information scheme Example Product class STM8 microcontroller Family type S Standard Sub family type 105 intermediate peripheral set 103 small peripheral set Pin count F 20 pins K 32 pins S 44 pins C 48 pins R 64 pins Program memory size 2 4 Kbytes 3 8 Kbytes 4 16 Kbytes 6 32 Kbytes Package type P TSSOP U VFQFPN T LQFP Temperature range 6 40 C to 85 C Package pitch no character 0 5 mm B 0 65 mm C 0 8 mm Packing no character tray or tube TR tape and reel STM8 S 103 F 3 P 6 M B For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you d STM8S103xx STM8S105xx STM8 development tools 10 10 1 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation svstem supported bv a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STMS8 is to be supported by a comp
18. Vpp 4temperatures 40 Typical pull up resistance Rpu vs Vpp 4temperatures 40 Typical pull up current lp vs Vpp 4temperatures 40 Typ VOL VDD 3 3 V standard ports 42 Typ VOL VDD 5 0 V standard ports 42 Typ VOL VDD 3 3 V true open drain ports 42 Typ VOL VDD 5 0 V true open drain ports 42 Typ VOL VDD 3 8 V high sink ports 42 Typ VOL VDD 5 0 V high sink ports 42 Typ VDD VOH VDD 3 3 V standard ports 43 Typ VDD VOH VDD 5 0 V standard ports 43 Typ VDD VOH VDD 3 3 V high sink ports 43 Typ VDD VOH VDD 5 0 V high sinkportis 43 Typical NRST Vj and Vip vs Vpp 4temperatures 44 Typical NRST pull up resistance Rpu vs Vpp 4 temperatures 45 Typical NRST pull up current lou VS Vpp 4 temperatures 45 Recommended reset pin protection 45 48 pin low profile quad flat package 7 X 7 47 44 pin low profile quad flat package 10
19. Vpp 5 0 V 1000 mV lio 20 mA Vpp 5 0 V TBD 1 Data based on characterization results not tested in production Table 17 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 4 pins sunk lio 10 MA Vpp 3 3 V 10000 Vo Output low level with 8 pins sunk lio 10 MA Vpp 5 0 V 800 mV Output low level with 4 pins sunk lio 20 mA Vpp 5 0 V 1500 Output high level with 4 pins sourced lio 10 mA Vpp 3 3 V 2 10 Vou Output high level with 8 pins sourced lio 10 mA Vpp 5 0 V 4 0 V Output high level with 4 pins sourced lio 20 mA Vpp 5 0 V 3 30 1 Data based on characterization results not tested in production 4 41 56 Electrical characteristics STM8S103xx STM8S105xx Figure 16 Typ Vo Vpp 3 3 V standard Figure 17 Typ Vo Vpp 5 0 V standard ports ports 1 5 40 C 1 5 396 250C m 25 C 1 25 85 C 1 25 85 C 125 C 125 C 1 075 FE 0 5 A 0 25 og 7 0 2 4 6 8 10 12 lo mA lo mA Figure 18 Typ Vo Vpp 3 3 V true open drain ports Figure 19 Typ Vo Vpp 5 0 V true open drain ports 40 C 25C 85 C 15 125 C Vo V Vo V 40 C m 25 C 85 C 1 5
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21. instructions Architecture and registers e Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data transfer between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers STM8S103xx STM8S105xx Product overview 4 2 4 3 4 4 Single wire interface module SWIM and debug module DM The single wire interface module and debug module and permit non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memo
22. ke C 35 30 2 5 3 3 5 4 4 5 5 5 5 6 Voo VI Figure 28 ra 3 5 o 5 2 60 40 C D o 5 25C 85 C 20 125 C 0 T T T T T 0 1 2 3 4 5 6 Voo V The reset network shown in Figure 29 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vu max level specified in Table 14 Otherwise the reset is not taken into account internally Figure 29 Recommended reset pin protection External reset circuit NRST y Internal reset Filter 0 01uF STM8 45 56 Package characteristics STM8S103xx STM8S105xx 8 46 56 Package characteristics In order to meet environmental requirements ST offers these devices in ECOPACK packages These packages have a lead free second level interconnect The category of second level interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com STM8S103xx STM8S105xx Package characteristics 8 1 8 1 1 Package mechanical data LQFP package mechanical data Figure 30 48 pin low profile quad flat package 7 x 7 Table 19 48 pi
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24. to 1 Mbit s fcpu 16 and capable of following any standard baud rate regardless of the input frequency e Separate enable bits for transmitter and receiver e 2receiver wakeup modes A Address bit MSB Idle line interrupt e Transmission error detection with interrupt generation e Parity control LIN master capability e Emission Generates 13 bit synch break frame e Reception Detects 11 bit break frame Synchronous communication e Full duplex synchronous transfers e SPI master operation e 8 bit data communication e Max speed 1 Mbit s at 16 MHz fcpu 16 LINUART Main features e LIN master slave rev 2 1 compliant e Auto svnchronization in LIN slave mode e High precision baud rate generator e 1 Mbit full duplex SCI LIN master e Emission Generates 13 bit synch break frame e Reception Detects 11 bit break frame STM8S103xx STM8S105xx Product overview Note 4 14 3 LIN slave e Autonomous header handling one single interrupt per valid message header e Automatic baud rate synchronization maximum tolerated initial clock deviation 15 Yo e Synch delimiter checking e 11 bit LIN synch break detection break detection always active e Parity check on the LIN identifier field e LIN error management e Hotplugging support Asynchronous communication UART mode Full duplex asynchronous communications NRZ standard format mark space Independently programmable transmit and receive baud
25. x 10 48 32 pin low profile quad flat package 7 X 7 49 32 lead very thin fine pitch quad flat no lead package 5x5 50 TSSOP 20 pin 4 40 mm body 0 65 mmpitch 51 STM88103 105 access line ordering information scheme 52 5 56 Introduction STM8S103xx STM8S105xx 6 56 Introduction This datasheet contains the description of the STM8S103 105 access line features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual PM0051 e For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e Forinformation on the STM8 core please refer to the STM8 CPU programming manual PMOO44 STM8S103xx STM8S105xx Description 2 Description The STM85S103 105 access line 8 bit microcontrollers offer from 8 Kbytes up to 32 Kbytes of program memory All devices of the STM8S103 105 access line provide the following benefits Reduced system cost A High system integrat
26. 2_CC1 SPI_SCK Voo Ea 13 PC4 HS AIN2 TIM1_CC4 CLK_CCO SPI_NSS TIM2_CC3 HS PA3 ig 121 PCS HSVTLITIM1 CC3 USART CK DC SDA PB5 C 10 11174 PB4 EC SCL HS high sink capability d STM8S103xx STM8S105xx Pinouts and pin description 5 2 Pin description Table 4 Legend abbreviations Type l input O output S power supply Level Input CM CMOS Output HS High sink Output speed O1 Slow up to 2 MHz O2 Fast up to 10 MHz O3 Fast slow programmability with slow as default state after reset OA Fast slow programmability with fast as default state after reset Port and control Input float floating wpu weak pull up configurado Output T true open drain OD open drain PP push pull Reset state is shown in bold Table 5 Pin description for STM8S105 MCUs Pin number Input Output S z g A Alternate gigg Pininame 8 gt 5 P g g Default alternate function after 2 SE se qo ue S g S 3 E G 35 B l 1 1 1 NRST VO X Reset 2 2 2 PA1 OSCIN vo X x O1 X X Port A1 GEN 3 3 3 JPA2 OSCOUT yo X X X Lola X Port az Resonator crystal 4 4 Vssio 1 S 1 O ground 51514 Wee S Digital ground 6 6 5 VCAP S 1 8 V regulator capacitor 71716 Vpp S Digital power supply 8 8 7 Vppio 1 S 1 O power supply 8 PF4 AIN12 VO X X O1 X X Port
27. 4 temperatures 6 z 40 C 5 m 25 C 85 C 4 125 C gt sd e 2 1 0 7 7 7 7 7 2 5 3 3 5 4 4 5 5 5 5 6 Vop V Figure 14 Typical pull up resistance Rpy VS Vpp 4 temperatures 60 55 E o lt 50 Ai o B R R R S 2 S 45 e 5 40 PG eet 40 C i 25C a 35 85 C 125 C w o Figure 15 Typical pull up current ly vs Vpp 4 temperatures 140 120 100 co o o o Pull Up current HAJ B o N o Voo VI Note The pull up is a pure resistor slope goes through 0 d STM8S103xx STM8S105xx Electrical characteristics Table 15 Output driving current standard ports Symbol Parameter Conditions Min Max Unit Output low level with 4 pins sunk lio 4 MA Vpp 3 3 V 1000 VoL Output low level with 8 pins sunk lo 10 mA Vpp 5 0 V 2000 id Output high level with 4 pins sourced ljg 4 mA Vpp 3 3 V 2 10 You Output high level with 8 pins sourced lig 10 mA Vpp 5 0 V 2 8 Ni 1 Data based on characterization results not tested in production Table 16 Output driving current true open drain ports Svmbol Parameter Conditions Min Max Unit lio 10 MA Vpp 3 3 V 1500 VoL Output low level with 2 pins sunk lio 10 mA
28. M2 TRGO STM8S103 End of conversion EOC interrupt ADC extended features STM88103 105 access line products contain a 10 bit successive approximation A D converter with the following features Upto 10 STM8S105x or 7 STM8S103x multiplexed input channels Single continuous and buffered continuous conversion on a selected channel Scan mode for single and continuous conversion of a sequence of channels A Analog watchdog capability with programmable upper and lower thresholds internal reference voltage on channel AIN7 STM8S103 only A Analog watchdog interrupt Communication interfaces The following communication interfaces are implemented USART STM8S105 no USART STM8S103 full feature UART single wire mode LIN2 1 master capability LINUART STM8S105 LIN2 1 master slave capability full feature UART synchronous mode SPI master mode Smartcard mode IrDA mode STM88103 No LINUART SPI full and half duplex 8 Mbit s PC up to 400 Kbit s 17 56 Product overview STM8S103xx STM8S105xx 4 14 1 4 14 2 18 56 USART Main features 1 Mbit s full duplex SCI LIN master capable SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder Single wire half duplex mode Asynchronous communication UART mode e Full duplex communication NRZ standard format mark space e Programmable transmit and receive baud rates up
29. NCC3 port B1 alternate function TIM1_NCC2 port BO alternate function TIM1 NCC1 AFRA Alternate function remapping option 4 0 Port D7 alternate function TLI 1 Port D7 alternate function TIM1 CC4 AFRS3 Alternate function remapping option 3 0 Port DO alternate function TIM3 CC2 1 Port DO alternate function TIM1 BKIN AFR2 Alternate function remapping option 2 0 Port DO alternate function TIM3 CC2 1 Port DO alternate function CLK CCO Note AFR2 option has priority over AFR3 if both are activated OPT2 cont d 32 56 AFR1 Alternate function remapping option 1 0 Port A3 alternate function TIM2_CC3 port D2 alternate function TIM3 CC1 1 Port A3 alternate function TIM3_CC1 port D2 alternate function TIM2 CC3 AFRO Alternate function remapping option O 0 Port D3 alternate function TIM2 CC2 1 Port D3 alternate function ADC ETR d STM8S103xx STM8S105xx Option bytes d Table 8 Option byte description continued Option byte no Description LSI_EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG_HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware OPT3 WWDG HW Window watchdog activation 0 WWDG window watchdog activated bv software 1 WWDG window watchdog activated bv hardware W
30. P Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontrollers Flash memory STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www cosmic software com e Raisonance C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www raisonance com e ST7 STM8 assembler linker Free assembly toolchain included in the ST7 STM8 toolset which allows you to assemble and link your application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third p
31. PC3 HS TIM1_CC3 PC2 HS TIM1_CC2 PC1 HS TIM1_CC1 LINUART_CK PES SPI NSS HS high sink capability 23 56 Pinouts and pin description STM8S103xx STM8S105xx 24 56 Figure 8 STM8S103 LQFP VQFN 32 pin pinout id 9 tr El o BO fa Da saz o BAR X x woo o BOEKE 2 CHETAN ehe JA FER ko e zz EXSESSSE HDZZNONHNNDH IxzxLLLLI Eed o oe e DOOOOOONO aara ri ria 323130292827 26 25 NRST Cie 240 PC7 HS SPI_MISO OSCIN PA1 22 230 PC6 HS SPI_MOSI OSCOUT PA2 g3 221 PC5 HS SPI_SCK TIM2_CC1 Vss CH 210 PC4 HS AIN2 TIM1_CC4 VCAP OS 200 PC3 HS TIM1 CC3 TLI USART CK Vpp 26 190 PC2 HS TIM1_CC2 SPI_NSS TIM2_CC3 HS PA3 CH 180 PC1 HS TIM1 CC1 PF4 Q8 170 PES HS SPI NSS 9 10111213141516 T Q 10 st OO QN FO n cn M M M M M M BA 6 B BA BR TAJACONDO QO ITII OO ss OEOES AEREE F RT l 598 F 4 4 2 2 HS high sink capability Figure 9 TSSOP20 pinout USART TX AIN5 PD5 Z 1e 20 PD4 HS TIM2 CC1 BEEP USART CK USART RX AING PD6 J 2 19 PD3 HS AIN4 TIM2_CC2 ADC_ETR NRST rH 3 18 PD2 HS AIN3 TIM2_CC3 OSCIN PA1 E 4 1714 PDT HS SWIM OSCOUT PA2 5 tek PC7 HS SPI MISO Vss 46 15 PC6 HS SPI_MOSI VCAP E 7 14 PC5 HS TIM
32. R1 Alternate function remapping option 1 0 TBD 1 TBD AFRO Alternate function remapping option O 0 TBD 1 TBD OPT2 34 56 d STM8S103xx STM8S105xx Electrical characteristics 7 7 1 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at TA 25 C and TA Tamar given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 X Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 0 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 X Typical curves Unless otherwise specified all typical curves are g
33. SART or LINUART with clock output for synchronous operation smartcard mode IrDA mode LIN master mode m SPI synchronous serial interface up to 8 Mbit s m C interface up to 400 Kbit s Analog to digital converter ADC m 10 bit 1 LSB ADC with up to 10 multiplexed channels scan mode and analog watchdog VOs m Up to 38 I Os on a 48 pin package including 9 high sink outputs m Highly robust UO design immune against current injection Table 1 Device summary Reference Root part number STM8S103xx STM88103K3 STM8S105C6 STM8S105C4 STM8S105xx STM8S105K6 STM8S105K4 STM8S105S6 STM8S105S4 Rev 2 1 56 This is preliminary information on a new product now in development or undergoing evaluation Details are subject to change without notice www st com Contents STM8S103xx STM8S105xx Contents 1 IRMOGUCTION WEE 6 2 DES EE 7 3 Block diagram 8 4 Product overview sic atin ie ce EE ER eee ace RT ere meee eee 10 4 1 Central processing unit STM8 10 4 2 Single wire interface module SWIM and debug module DM 11 4 3 Interrupt controller 11 4 4 Flash program memory 11 4 5 Clockcontroller 13 4 6 Power management 14 4 7 Watchdog timers
34. TIM2_CC1 BEEP PE1 2C SCL PE2 2C SDA HS TIM3_CC2 HS TIM3_CC1 HS SWIM PEO CLK_CCO HS TIM2 PD6 LINUART_RX PD4 PD3 PD2 PD1 PDO H PE3 TIM1_BKIN e gt O PD7 TLI I HNJOONRON o 10 O11 O12 R N R e2 A Ru R R R GA R N B rd R CH C2 C2 Co u Ki w Oo H Vppio 2 O PC4 HS TIM1_CC4 131415 1617 18192021 222324 U N oO AIN6 PB6 AIN5 PB5 AIN4 PB4 TIM1_ETR AIN3 PB3 AIN8 PE AIN9 PE TIM1_NCC3 AIN2 PB2 TIM1_NCC2 AIN1 PB1 TIM1_NCC1 AINO PBO PG1 PGO PC7 SPI MISO PC6 SPI MOSI Vssio 2 PC5 SPI SCK PC3 HS TIM1 CC3 PC2 HS TIM1_CC2 PC1 HS TIM1_CC1 LINUART_CK PEB SPI NSS HS high sink capability 4 21 56 STM8S103xx STM8S105xx Pinouts and pin description LQFP 44 pin pinout Figure 6 vas Ozl 2ad O JOS 92 4 3d 0 099 419 03d O AUS LWIL ZOO EWIL SH oaa CI WIMS SH Lad O 00 ZWIL L99 EWIL SH zaa O 413 OOV ZOO eNIL SH Qd D d33g L99 ZWIL SH vad O XL LHVANIT SQA CI KU LYVNNIT 9dd O YOO LALLITUZQd O
35. WDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wake up unit clock 0 LSI clock source selected for AWU OPT4 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler 00 Reserved 01 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPTS HSECNT 7 0 HSE crystal oscillator stabilization time This configures the stabilisation time to 0 16 256 4096 HSE cycles OPT6 Reserved OPT7 Reserved BL 7 0 Bootloader option byte This option is checked by the boot ROM code after reset Depending on OPTBL content of addresses 487Eh 487Fh and 8000h reset vector the CPU jumps to the bootloader or to the reset vector Refer to STM8S bootloader manual for more details 33 56 Option bytes STM8S103xx STM8S105xx Table 9 STM8S103x alternate function remapping bits Option byte no Description AFR7Alternate function remapping option 7 0 TBD 1 TBD AFR6 Alternate function remapping option 6 0 TBD 1 TBD AFR5 Alternate function remapping option 5 0 TBD 1 Reserved AFR4 Alternate function remapping option 4 0 TBD 1 TBD AFR3 Alternate function remapping option 3 0 TBD 1 TBD AFR2 Alternate function remapping option 2 0 TBD 1 TBD AF
36. arty tool developers already supplying programmers for the STM8 family STM8S103xx STM8S105xx Revision history 11 Revision history Table 24 Document revision history Date Revision Changes 05 Jun 2008 1 Initial release Corrected number of high sink outputs to 9 in Os on page 1 23 Jun 2008 2 Updated part numbers in Table 2 STM8S103 105 access line features on page 7 55 56 STM8S103xx STM8S105xx Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered
37. cation to modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 3 The size of the UBC is programmable through the UBC option byte Table 8 in increments of 1 page by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory Up to 32 Kbytes minus UBC e User specific boot code UBC Configurable up to 32 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area lt protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 3 Flash memory organization STM8S105 Programmable area from 0 5 Kbytes UBC area 2 first pages up to 32 Kbytes Remains write protected during IAP 1 page steps Up to 32 Kbytes Flash G program memory Program memory area Write access possible for IAP STM8S103xx STM8S105xx Product overview 4 5 Figure 4 Flash memory organisation STM8S103 Programmable area from 128 bytes UBC area 2 first pages up to 8 Kbytes Remains write protected during IAP 1 page steps Up to 8 Kbytes Flash TJ program memorv Program memorv area Write access possibl
38. d flat no lead package mechanical data 50 TSSOP 20 pin 4 40 mm body 0 65 mm pitch mechanical data 51 Document revision history 55 STM8S103xx STM8S105xx List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 STM88105 access line block diagram 8 STM8S103 access line block diagram 9 Flash memory organization STM8S105 s sasa saka aa kka aaa a 12 Flash memory organisation STM8S103 13 LOFP 48 pir PINOUT EE EE me bawak ali vd li d EO eR ED es 21 LQFP 44 pin pinout 22 STM88105 LQFP VQFN 32 pin pinout 23 STM8S103 LQFP VQFN 32 pin pinout 24 ToSOP20PNOU ss e xax ds Phe eer a e VUE ac ae A 24 Pin loading conditions lss as s RI das n 35 Pin input volta a s 14 a EE 36 i pijmax versus VID rapra de dif i dat EE ce Ee a SC 38 Typical Vi and Vip vs
39. during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 53 56 STM8 development tools STM8S103xx STM8S105xx 10 2 10 2 1 10 2 2 10 3 54 56 Software tools STM8 development tools are supported by a complete free software package from STMi croelectronics that includes ST visual develop STVD IDE and the ST visual programmer STVP software interface STVD provides seamless integration of the cosmic C compiler for STM8 which is available in a free version that outputs up to 16 Kbytes of code STMS toolset STMS toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST visual develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST visual programmer STV
40. e for IAP Read out protection ROP The read out protection blocks reading and writing the Flash program memorv in debug mode Once the read out protection is activated anv attempt to toggle its status triggers a global erase of the program and data memorv Even if no protection can be considered as totallv unbreakable the feature provides a verv high level of protection for a general purpose microcontroller Clock controller The clock controller distributes the system clock fyASTER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources 4 different clock sources can be used to drive the master clock 1 16 MHz High Speed External crystal HSE Up to 16 MHz High Speed user external clock HSE user ext 16 MHz High Speed Internal RC oscillator HSI
41. endent WDG STM8S103K3 32 282 28 7 10 7 8 1K comm smartcard ADC extended features mode IrdA mode and single wire mode 1 9 high sink outputs 2 8high sink outputs ky 7 56 Block diagram STM8S103xx STM8S105xx 3 Figure 1 Block diagram STM8S105 access line block diagram 8 56 SPI emul Up to 10 channels 400 Kbit s lt gt PC 10 Mbit s lt SPI 10 bit ADC extended features 1 2 4 kHz beep Beeper tery gy Address and data bus i Reset block XTAL 1 16 MHz Clock controller Reset a Reset RC int 16 MHz Detector POR BOR RC int 128 kHz Clock to peripherals and core lt gt Window WDG STM8 CORE 5 gt Independent WDG Single wire debug interf gt Debug SWIM Up to 32 Kbytes lt gt program Master slave Blah autosynchro lt I LINUART LIN master extended features Up to 2 Kbytes RAM Boot ROM 16 bit advanced control timer TIM1 16 bit general purpose timers TIM2 TIM3 8 bit basic timer TIM4 AWU timer 5 LN 5 Up to 9 CAPCOM channels d STM8S103xx STM8S105xx Block diagram 4 Figure 2 STM8S103 access line block diagram
42. ion level with internal clock oscillators watchdog and brown out reset Performance and robustness 16 MHz CPU clock frequency Robust I O independent watchdogs with separate clock source Clock security system Short development cycles A Applications scalability across a common family product architecture with compatible pinout memory map and and modular peripherals Full documentation and a wide choice of development tools Product longevity Advanced core and peripherals made in a state of the art technology Afamily of products for applications with 3 0 V to 5 5 V operating supply Table 2 STM8S103 105 access line features 2 o gt Q 82 ol D o c o c o El El EG pe E 2 f 5 a H a 5 EA 2 2 0 E 2 gt Device 89 03 2 s2 8 Peripheral set Sei ol O 5 oz E D 9 o2 z E Ela AR EE lt 3 O o tc s la sl E ela o Al e z E b 4 u STM8S105C6 48 38 37 9 12 10 32K 2K LINUART extended STM8S105C4 aa 38 37 9 12 10 16K 2 Ee STM8S10586 44 34 31 8 11 9 32K 2K Somm smartcara Multipurpose timer TIM1 STM8S105S4 44 340 31 8 11 9 16K 2K mode AA mode PWM timer TIM2 STM8S105K6 32 25 23 8 11 7 32K 2K Ewe TE 8 bit timer TIM4 STM8S105K4 32 25 23 8 11 7 16K 2K timer TIM3 USART with full Window WDG features synchronous Indep
43. ison 16 Legend abbreviations 25 Pin description for STM8S105 MCUS 25 Pin description for STM8S103 MCUS 28 Option b tes cea tee OR AR ee EE ee ERE E er ER ede ee 31 Option byte description 32 STM88103x alternate function remappingbits 34 Voltage characteristics 00 36 Current characteristics 37 Thermal characteristics 37 General operating conditions 38 VO static characteristics 39 Output driving current standard ports 41 Output driving current true open drain ports 41 Output driving current high sink ports 41 NRST pin characteristics 44 48 pin low profile quad flat package mechanical data 47 44 pin low profile quad flat package mechanical data 48 32 pin low profile quad flat package mechanical data 49 32 lead very thin fine pitch qua
44. iven only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10 Figure 10 Pin loading conditions STMS PIN 50pF 35 56 Electrical characteristics STM8S103xx STM8S105xx 7 1 5 7 2 36 56 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11 Figure 11 Pin input voltage STM8 PIN E Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 10 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including Vppa and Vopio 0 3 6 5 Vi Input voltage on true open drain pins PE1 PE2 2 Vss 0 3 6 5 V Input voltage on any other pin Vss 0 3 Vpp 0 3 IVppx Vss Variations between different power pins 50 IVssx Vss Variations between all the different ground pins 50 i 1 All power Vpp Vppio VDDA and ground Vss Vssio Vssa pins must always be connected to the external power supply 2 linj PIN must never be exceeded This is implicitly insured if Vjy maximum is re
45. lete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STM8 tool line includes the full featured STice emulation system offering a complete range of emulation and in circuit debugging features on a platform that is designed for versatilitv and cost effectiveness In addition STM8 application development is supported bv a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows vou to order exactiv what vou need to meet vour development requirements and to adapt vour emulation svstem to support existing and future ST microcontrollers STice kev features Occurrence and time profiling and code coverage new features Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 K records Read write on the fly of memory
46. n description for STM8S103 MCUs continued Pin number Input Sen ES Alternate SS function fa 9 2 2 9 Default alternate after Q g Pin name 2 o 2 S 3r l u A Ec E ET S function remap O JA s3292 9 ala s e 2 9 s SI lt lt ee ss option o 9 89 o mc bit GIF tT I gt w Con Analog input 2 l PC4 AIN2 TIM1 4 yao TIM EE vol x x x uslos X X Port C4 Timer 1 channel OU Sie CLK_CCO 4 clock output 22 14 PC5 TIM2_CC1 SPL_SCK_1 O X X X HS O3 X X Port cs Mer 2 channel ent clock 23 15 PC6 SPI_MOSI vol x x x IHslos X x Port ce SP master out slave in SPI master in 24 16 PC7 SPI MISO VO X X X HS O3 X X Port C7 slave out Con 25 PDO TIM1_BKIN CLK_CCO o x X X pelen X X Port po mer 1 break figurable input clock output 26 17 PD1 SWIM vol x x x IHsloal X X Port D1 JSWIM data interface Analog input 3 27 18 JPD2 AIN3 TIM2 CC3 VO X X X HS OS X X Port D2 Timer 2 channel 3 Analog input 4 ADC 28 19 EE VO X X X HS O3 X X Port D3 Timer 2 channel jexternal 2 trigger USART PD4 TIM2_CC1 BEEP Timer 2 channel clock 29 20 USART_CK VO X X X HS O3 X X Port D4 BEEP output USART 30 1 PD5 AIN5 USART_TX O X X X O1 X X Port D5 Analog input 5 data transmit USART 31 2 PD6 AING USART_RX VO X X X O1 X X Port D6 Analog input 6 data receive Top level interrupt 32 PD7 TLI TIM1_CC4 VO X
47. n low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 60 0 0630 Al 0 05 0 15 0 0020 0 0059 A2 1 35 1 40 1 45 0 0531 0 0551 0 0571 0 17 0 22 0 27 0 0067 0 0087 0 0106 C 0 09 0 20 0 0035 0 0079 D 9 00 0 3543 D1 7 00 0 2756 E 9 00 0 3543 E1 7 00 0 2756 e 0 50 0 0197 q 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 0 0177 0 0236 0 0295 L1 1 00 0 0394 1 Values in inches are converted from mm and rounded to 4 decimal digits 47 56 Package characteristics STM8S103xx STM8S105xx 48 56 Figure 31 44 pin low profile quad flat package 10 x 10 A gt WA lt ARARARARR A Tu Lit 3 5 L a h Table 20 44 pin low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 60 0 0630 Al 0 05 0 15 0 0020 0 0059 A2 1 35 1 40 1 45 0 0531 0 0551 0 0571 b 0 30 0 37 0 45 0 0118 0 0146 0 0177 C 0 09 0 20 0 0035 0 0079 D 12 00 0 4724 D1 10 00 0 3937 E
48. oad AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 Timers with 3 or 2 individually configurable capture compare channels PWM mode Interrupt sources 2 or 3 x input capture output compare 1 x overflow update TIMA 8 bit basic timer e 8 bitautoreload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update 15 56 Product overview STM8S103xx STM8S105xx Table 3 STMA TIM timer feature comparison Counter Timer Counting CAPCOM Complem Ext synchr Timer size Prescaler dm x mode channels outputs trigger onization bits ne chaining TIM1 16 Any integer from 1 to 65536 Up down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No T es TIMS 16 Any power of 2 from 1 to 32768 Up 2 0 No TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No 16 56 A STM8S103xx STM8S105xx Product overview 4 13 4 14 Analog digital converter ADC STM88103 105 access line products contain a 10 bit successive approximation A D converter with up to 10 multiplexed input channels and the following general features _ Input voltage range 0 to Vppa Dedicated voltage reference VREF pins available on 80 and 64 pin devices Conversion time 14 clock cycles Single and continuous conversion modes External trigger input Trigger from TIM1 TRGO STM88105 or TI
49. pt the ROP and UBC options that can only be toggled in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UMO470 for information on SWIM programming procedures Table 7 Option bytes Option Option bit Factor Option p p gt aciory Addr hame byte default no 7 6 5 4 3 2 1 0 setting 4800h Read out OPTO ROP 7 0 00h protection ROP 4801h User boot OPTI UBC 7 0 00h code UBC 4802h NOPTI NUBC 7 0 FFh 4803h Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFRI AFRO 00h function 4804h remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh AFR 4805h Watchdog OPT3 Reserved LSI IWDG WWDG WWDG 00h option _EN _HW HW _HALT 4806h NOPT3 Reserved NLSI NIWDG_ NWWDG NWWG FFh _EN HW HW _HALT 4807h Clock option OPT4 Reserved EXT CKAWU PRS PRS 00h CLK SEL C1 Co 4808h NOPT4 Reserved NEXT NCKAWUS NPR NPR FFh CLK EL SC1 SCO 4809h HSE clock OPT5 HSECNT 7 0 00h startup 480Ah NOPT5 NHSECNTIT 0 FFh 480Bh Reserved OPT6 Reserved 00h 480Ch NOPT6 Reserved FFh 480Dh Flash wait OPT7 Reserved Wait state 00h states 480Eh NOPT7 Reserved Nwait state FFh 487Eh Bootloader OPTBL BL 7 0 00h 487Fh NOPTBL NBL 7 0 FFh ky 31 56 Option bytes STM8S103xx STM8S105xx Table 8 Option byte description Op
50. pu MHz FUNCTIONALITY NOT GUARANTEED IN THIS AREA 16 SUPPLY VOLTAGE V d STM8S103xx STM8S105xx Electrical characteristics 7 3 1 I O port pin characteristics General characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 14 VO static characteristics Symbol Parameter Conditions Min Typ Max Unit V Input low level 0 3 V TBD V voltage Input high level Vpp 5 0 V VIH voltage 0 7 x Vpp Vpp 0 3 V V Vhys Hysteresis 700 mV Rou Pull up resistor Vpp 5 V Vin Vss 30 45 60 kQ Fast I Os 20 3 ge te te Rise and fall time Load 50 pF R IF 10 90 Standard and high sink I Os 425 3 ns Load 50 pF Input leakage lika current VssSViNSVpp x1 3 HA analog and digital Analog input sy 8 liko ana leakage current VssSVINSVDD 260 nA Leakage rrent in Injection current 4 mA x19 HA kin adjacent VOO 1 TBD to be determined 2 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 3 Data based on characterization results not tested in production K 39 56 Electrical characteristics STM8S103xx STM8S105xx 40 56 Figure 13 Typical Vu and Vu vs Vpp
51. rates up to 500 Kbit s Programmable data word length 8 or 9 bits Low power standby mode 2 receiver wake up modes A Address bit MSB ldle line Muting function for multiprocessor configurations Overrun noise and frame error detection 6 interrupt sources Tx Rx parity control In STM8S105 the LINUAHT also supports IrDA mode Smartcard mode and synchronous communication SPI master mode SPI Maximum speed 8 Mbit s fmasTER 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on 2 lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin 19 56 Product overview STM8S103xx STM8S105xx 4 14 4 20 56 I C PC master features Clock generation Start and stop generation EC slave features Programmable EC address detection Stop bit detection Generation and detection of 7 bit 10 bit addressing and general call Supports different communication speeds Standard speed up to 100 kHz Fast speed up to 400 kHz STM8S103xx STM8S105xx Pinouts and pin description 5 5 1 Figure 5 Package pinouts Pinouts and pin description LQFP 48 pin pinout NRST OSCIN PA1 OSCOUT PA2 Vssio 1 Vss VCAP Von VDDIO 1 TIM2 CC3 PA3 PA4 PAS PA6 CC2 ADC_ETR PD5 LINUART TK HS
52. rocessor malfunctions due to hardware or software failures ky STM8S103xx STM8S105xx Product overview 4 8 4 9 4 10 4 11 4 12 It is clocked by the 128 kHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wake up counter e Used for auto wake up from active halt mode e Clock source internal 128 kHz internal low frequency RC oscillator or external clock Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e A independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output Synchronization module to control the timer with external signal Break input to force the timer outputs into a defined state 3 complementary outputs with adjustable dead time Encoder mode Interrupt sources x input capture output compare 1 x overflow update 1 x break TIM2 16 bit general purpose timer 16 bit autorel
53. ry programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R Wto RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e 2advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on 6 vectors including TLI Trap and reset interrupts Flash program memory e Upto 32 Kbytes of program single voltage Flash memory e User option byte area 11 56 Product overview STM8S103xx STM8S105xx 12 56 Write protection WP Write protection of Flash is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS Memory Access Security System MASS is always enabled and protects the main Flash program memory and option bytes To perform In Application Programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the appli
54. spected If Vin maximum cannot be respected the injection current must be limited externally to the linj pin value A positive injection is induced by Viu Vpp while a negative injection is induced by Vins Vss Por true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected d STM8S103xx STM8S105xx Electrical characteristics Table 11 Current characteristics Symbol Ratings Max IVDD Total current into Vpp power lines source 60 Ivss Total current out of Vss ground lines sink 1 60 m Output current sunk by any I O and control pin 20 Output current source by any I Os and control pin 20 Injected current on NRST pin 4 lINs PIN AS Injected current on OSCIN pin 4 Injected current on any other pin 4 ZIiNJ PIN Total injected current sum of all VO and control pins 4 20 Unit mA 1 All power Vpp Vppio Vppa and ground Vss Vssjo Vssa pins must always be connected to the external supply 2 linj PIN Must never be exceeded This is implicitly insured if Vin maximum is respected If Vin maximum cannot be respected the injection current must be limited externally to the linj Pin Value A positive injection is induced by Vin Vpp while a negative injection is induced by Viy Vss For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected
55. ternal AWU interrupt external interrupt or reset e Slow active halt mode this mode is the same as fast active halt except that the main voltage regulator is powered off so the wake up time is slower e Halt mode in this mode the microcontroller uses the least power CPU and peripheral clocks are stopped the main voltage regulator is powered off Wake up is triggered by external interrupt or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications The WDG timer activity is controlled by option bytes Once activated the watchdog can not be disabled by the user program without reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower then the one stored in the window register Independent watchdog timer The independent watchdog peripheral can be used to resolve p
56. tion byte no Description ROP 7 0 Memory readout protection ROP AAh Enable readout protection write access via SWIM protocol SE Note Refer to the family reference manual RM0016 section on Flash memory readout protection for details UBC 7 0 User boot code area For STM8S105 page size 128 bytes 00h no UBC no write protection O1h Page 0 and 1 defined as UBC memory write protected 02h to FFh Pages 2 to 255 defined as UBC memory write protected OPT1 For STM8S103 page size 64 bytes 00h no UBC no write protection O1h Page 0 and 1 defined as UBC memory write protected 02h to 7Fh Pages 2 to 127 defined as UBC memory write protected Note Refer to the family reference manual RM0016 section on Flash write protection for more details Note This remapping applies to STM8S105 For STM8S103 alternate function remapping refer to Table 9 on page 34 AFR7Alternate function remapping option 7 0 Port D4 alternate function TIM2_CC1 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 Port B5 alternate function AIN5 port B4 alternate function AIN4 1 Port B5 alternate function IC SDA port B4 alternate function EG SOL AFRS Alternate function remapping option 5 0 Port B3 alternate function AIN3 port B2 alternate function AIN2 port B1 alternate function AIN1 port BO alternate function AINO OPT2 1 Port B3 alternate function TIM1_ETR port B2 alternate function TIM1
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