MICRONAS
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1. SPGS0025 2 P100V1E Fig 2 1 PQFP100 Plastic Quad Flat Pack 100 Pin Weight approx 1 61 g Micronas March 31 2003 6251 608 2Al 9 CDC1607F E ADVANCE INFORMATION 2 2 Pin Assignment Pin Functions Pin Pin Pin Functions Bus LCD Port Port Basic No No Basic Port Port LCD Bus Mode Mode Special Out Special In Function Function Special In Special Out Mode Mode SEG7 3 GWRQ U7 3 91 90 U4 0 CAN2 RX WP7 SEG4 0 ADB8 SEG7 2 GRDQ U7 2 92 89 U4 1 CAN2 TX SEG4 1 ADB9 SEG7 1 U7 1 93 88 U4 2 UART2 RX SEG4 2 ADB10 SEG7 0 U7 0 94 87 U4 3 UART2 TX SEG4 3 ADB11 UVSS 95 86 U4 4 UARTO RX WP8 SEG4 4 ADB12 UVDD 96 85 U4 5 UARTO TX SEG4 5 ADB13 ADB7 SEG3 7 T2 OUT U3 7 97 84 U4 6 CC2 IN CC1 OUT SEG4 6 ADB14 ADB6 SEG3 6 CC1 OUT U3 6 98 83 U4 7 CC1 IN SEG4 7 ADB15 ADB5 SEG3 5 SPI1 CLK OUT SPI1 CLK IN U3 5 99 82 U5 0 CCO IN CO1 SEG5 0 ADB4 SEG3 4 TO OUT WPO U3 4 100 81 U5 1 INT TEST IN CCO OUT SEG5 1 ADB3 SEG3 3 CC2 OUT U3 3 1 80 U5 2 LCD CLK IN AM PWM SEG5 2 ADB2 SEG3 2 DIGIT OUT DIGIT IN U3 2 2 79 U5 3 LCD SYNC IN AM OUT SEG5 3 ADB1 SEG3 1 CO1 SPI1 D IN U3 1 3 78 U5 4 IRQ UART1 TX SEG5 4 ADBO SEGS3 0 SPI1 D OUT U3 0 4 77 U5 5 ABORTQ co2. including Slope Level Selection Patch Module 10 ROM locations 5 ROM loca 10 ROM locations 5 ROM loca 6 ROM locations tions tions Boot System allows in system downloading of allows in system downloading of code and data into RAM via serial code and data into RAM via serial link link Analog Reset Alarm Combined Input for Regulator Input Supervision Clock and Supply v Supervision 10 bit ADC charge 9 channels 5 channels selectable as digital input balance type ADC Reference VREF Pin Comparators PO6COMP with 1 2 AVDD reference LCD Internal processing of all analog voltages for the LCD driver 4 4Z0910090 NOLLVINHOHNI 3ONVAGV SeUOJOIIN IV2 809 LS29 002 LE YVEN Table 1 1 CDC16xxF Family Feature List continued 256 byte object RAM each 256 byte object 256 byte object RAM each 256 byte object This Docu ment Item CDC1605F E CDC1607F E CDC1631F E CDC1605F C CDC1607F C CDC1641F C CDC1652F C CDC1672F C EMU MCM Flash MASK ROM EMU MCM Flash Mask ROM Mask ROM Mask ROM Communication DMA 1 DMA Channel for serving the 1 DMA Channel for serving the 1 DMA Channel for serving the Graphics Bus interface Graphics Bus interface Graphics Bus interface UART 3 UARTO UART1 and UART2 1 UARTO 3 UARTO UART1 and UART2 1 UARTO 3 UARTO UART1 and UART2 Synchronous Serial 2 SPIO and SPI1 1 SPIO 2 SPIO and SPI1 1 SPIO 2 SPIO and SPI1 Peripheral Interfaces Full CAN m
3. 8 Data Sheet History 1 Advance Information CDC1607F E Automotive Control ler Specification Feb 17 2003 6251 608 1Al First release of the advance information Originally created for the HW version CDC1607F E1 2 Advance Information CDC1607F E Automotive Control ler Specification March 31 2003 6251 608 2Al Second release of the advance information Originally created for the HW version CDC1607F E2 Micronas GimbH Hans Bunte Strasse 19 D 79108 Freiburg Germany P O Box 840 D 79008 Freiburg Germany Tel 49 761 517 0 Fax 49 761 517 2174 E mail docservice micronas com Internet www micronas com Printed in Germany Order No 6251 608 2Al All information and data contained in this data sheet are without any commitment are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability Any new issue of this data sheet invalidates previous issues Product availability and delivery are exclusively subject to our respective order confirmation form the same applies to orders based on development samples deliv ered By this publication Micronas GmbH does not assume responsibil ity for patent infringements or other rights of third parties which may result from its use Further Micronas GmbH reserves the right to revise this publication and to make changes to its content at any time without obligation to notify any person or entity of such revisions
4. MHz 5 When the ERM is active this time value is decreased by 0 121 fXTAL e g 15 125 ns at 8 MHz 6 Measured with external clock Add 170 WA at 4 MHz 200 uA at 10 MHz for operation on typical quartz with SR3 XTAL 0 Oscillator RUN mode 14 March 31 2003 6251 608 2Al Micronas ADVANCE INFORMATION CDC1607F E 3 0 4 Recommended Crystal Characteristics Table 3 4 UVss HVss1 HVss2 AVss 0V 4 5V lt Vpp AVpp UVpp lt 5 5 V 4 75 V lt HVpp1 HVpp2 lt 5 25 V TCASE 40 C to 105 C Symbol Parameter Min Typ Max Unit Test Conditions fp Parallel Resonance Frequency 4 12 MHz C 12 pF R4 Series Resonance Res for 50 ms Oscillation Start Up time QC 12 pF 380 Ohm START UP fp 4 MHz 320 RUN fp 6 MHz 230 Ohm START UP 160 RUN fp 8 MHz 150 Ohm START UP 95 RUN fp 10 MHz 100 Ohm START UP 60 RUN Cext External Oscillation Capaci 18 pF tances for C 12 pF connected to VSS Micronas March 31 2003 6251 608 2Al 15 CDC1607F E ADVANCE INFORMATION 4 CPU RAM ROM and Banking MCM Alternative Native PQFP1 physadd Bat Boot e VEMM log addr _ _ log addr Reserved 001800 Reserved FE ERS ee l 091309 CAN2 RAM se CAN1 RAM 091500 CANO RAM 001C00 CAN Regs 001D00 Ext I O NEM VO Reg1 001F00 l O RegO 002000 Sector0 0 0 0 0 0 0 0 0 0 0 0 0 S S S ee Bank0 upper 8 KB 004000
5. Temperature 45 125 C Pmax Maximum Power Dissipation 0 8 W 1 This condition represents the worst case load with regard to the intended application Stresses beyond those listed in the Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only Functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions Characteristics of this specification is not implied Exposure to absolute maximum ratings conditions for extended periods may affect device reliability 12 March 31 2003 6251 608 2Al Micronas ADVANCE INFORMATION CDC1607F E 3 0 2 Recommended Operating Conditions Table 3 2 UVSS HVSS1 HVSS2 AVSS 0 V Symbol Parameter Pin Name Min Typ 1 Max Unit Vpp Supply Voltage VDD 4 5 5 5 5 V Port Supply Voltage UVDD Analog Supply Voltage AVDD HVpp SM Supply Voltage 1 HVDD1 4 75 5 5 25 V SM Supply Voltage 2 HVDD2 AVpp Voltage Difference between VDD VDD AVDD 0 2 0 2 V and AVDD resp UVDD UVDD dAVpp AVDD Ripple Peak to Peak AVDD 200 mV fXTAL XTAL Clock Frequency XTAL1 4 12 MHz XTAL Clock Frequency XTAL1 4 10 MHz using ERM Tj Junction Temperature 40 110 C Vii Low Input Voltage U Ports 0 51 Vpp V H Ports PO Ports TEST Vin High Input Voltage U Ports 0 86 Vpp V H Ports PO Port
6. changes To ensure compatible option settings in this IC and mask ROM derivatives when run with the same ROM code it is recommended to always read locations OOFFAOh through OOFFC3h directly after reset Please note that the non programmable locations OOFFB8h through OOFFBFh may not be compatible within this IC and the mask ROM derivative Micronas March 31 2003 6251 608 2Al 19 CDC1607F E ADVANCE INFORMATION 7 Differences This chapter describes differences of this document to pre decessor document CDC1607F E Automotive Controller Specification Feb 17 2003 6251 606 1Al Section Description 1 Introduction Table 1 1 CDC16xxF Family Feature List on page 3 Name and features of Example E Family changed into CDC1631F E Multiplier 8 by 8 bit added Fig 1 1 Block diagram of CDC1605F E CDC1607F E on page 8 Multiplier 8 by 8 bit added 2 External Components Value of C at RESETQ changed from 47 u to 47 n value of C at VREF changed from 10 u to 10 n and text added 3 Core Logic Table 5 1 Control byte source on page 17 Updated minimized 4 CPU RAM ROM and Bank ing Fig 4 1 Address Map on page 16 Layout format corrected 5 Differences New Chapter 20 March 31 2003 6251 608 2Al Micronas ADVANCE INFORMATION CDC1607F E Micronas March 31 2003 6251 608 2Al 21 CDC1607F E ADVANCE INFORMATION
7. function to the host system requirements clock signal selection for most of the peripheral modules from fosc to fosc 2 7 plus some internal sig nals see table in Chapter Hardware Options of document CDC16xxF E Automotive Controller Family User Manual interrupt source selection for interrupt inputs 5 6 7 13 14 and 15 Special Out signal selection for some U and H ports Rx Tx polarity selection for SPI and UART modules U port Port Slow Mode selection Hardware Option setting requires two steps 1 selection is done by programming dedicated address locations with the desired options code 2 activation is done by a read access to these dedi cated address locations at least once after each reset Address locations OOFFB8h through OOFFBFh do not allow random setting Their respective Hardware Options are hard wired and can only be altered by changing a production mask for this IC By default the Port Slow Option is set for all U Ports with the excep tion of U1 0 to U1 3 Port Fast Option is set The Watchdog and Clock Monitor are activated via soft ware by default Future mask ROM derivatives of this IC will not require but will tolerate activation of option settings by read accesses as the ROM as well as the options will be hard wired Instead the manufacturer will automati cally process the setting of the dedicated address locations as given in the ROM code file to set the required mask
8. 1 X normal Emula mode tor mode 1 Flash mode TSTROM TestROM Table 5 4 FLASH FLASH EEPROM Table 5 5 IROM Internal ROM Tables 5 4 and 5 5 Table 5 4 TSTROM and IROM usage in mask ROM parts TSTROM IROM selected program storage between Bus mode and normal mode 1 1 internal ROM EBTRI Emulator Data Bus Tristate Table 5 3 0 internal TestROM x 0 external via Multifunction pins in Bus mode Micronas March 31 2003 6251 608 2Al 17 CDC1607F E ADVANCE INFORMATION Table 5 5 FLASH and IROM usage in FLASH and EMU parts FLASH IROM selected program storage 1 1 internal FLASH EEPROM resp Emulator Bus 0 internal BOOT ROM x 0 external via Multifunction pins in Bus mode IRAM Internal RAM r w1 Enable internal RAM r wO Disable internal RAM ICPU Internal CPU r w1 Enable internal CPU r wO Disable internal CPU Table 5 6 Some commonly used settings for address location OOFFF3h A copy is automatically transferred to the CR during IC start up Code TEST Operation Mode Pin FFh 0 Stand alone with internal ROM or Flash ABh 1 External program storage connected to multifunction pins in Bus mode DFh 0 Emulator mode CPGA177 package 18 March 31 2003 6251 608 2Al Micronas ADVANCE INFORMATION CDC1607F E 6 Hardware Options 6 1 Functional Description Hardware Options are available in several areas to adapt the IC
9. ADVANCE INFORMATION CDC1607F E Automotive Controller Specification Edition March 31 2003 2 MICRONAS 6251 608 2Al CDC1607F E ADVANCE INFORMATION Contents Page Section Title 3 1 Introduction 3 1 1 Features 7 1 2 Abbreviations 9 2 Package and Pins 9 2 1 Package Outline Dimensions 10 2 2 Pin Assignment 11 2 3 External Components 12 3 Electrical Characteristics 16 4 CPU RAM ROM and Banking 17 5 Core Logic 17 5 1 Control Register CR 19 6 Hardware Options 19 6 1 Functional Description 20 7 Differences 22 8 Data Sheet History 2 March 31 2003 6251 608 2Al Micronas SeUOJOIIN IV2 809 LS29 002 Le YVEN 1 Introduction Release Note Revision bars indicate significant changes to the previous edition The IC is a single chip controller for use in automotive applications The CPU on the chip is an upgrade of the 65C02 with 16 bit internal data and 24 bit address bus The chip consists of timer counters an interrupt controller a multichannel A D converter a stepper motor and LCD driver CAN interfaces and PWM outputs This document provides MCM Flash hardware specific information General information on operating the IC can be found in the document CDC16xxF E Auto motive Controller Family User Manual 6251 606 2Al 1 1 Features Table 1 1 CDC16xxF Family Feature List This Docu ment Item CDC1605F E CDC1607
10. C not connected 43 H3 3 SMD2 DBT SMA2 H0 1 39 leave vacant 42 H34 SMDT DBO SMA2 SMA COMP H0 0 40 41 H3 5 SMD1 Fig 2 2 Pin Assignment for PQFP100 Package 10 March 31 2003 6251 608 2Al Micronas ADVANCE INFORMATION CDC1607F E 2 3 External Components C 100 nto 150n 5V N EVDD 0 to 1 5 V L i 2 C System EVSS 0 to 1 2 Ground C 100 nto 150 n c 45V 2 ik i System c Ground 5 V Analog 5V 4 7k 47 n Anal Reset I nalog q Ground System l Ground Fig 2 3 Recommended external supply and quartz connection for low electromagnetic interference EMI To provide effective decoupling and to improve EMC behav ior the small decoupling capacitors must be located as close to the supply pins as possible The self inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self resonant fre quency of the decoupling network A frequency too low will reduce decoupling effectiveness increase RF emissions and may affect device operation adversely XTAL1 and XTAL2 quartz connections are especially sensi tive to capacitive coupling from other PC board signals It is strongly recommended to place quartz and oscillation capac itors as close to the pins as possible and to shield the XTAL1 and XTAL2 traces from other sign
11. F E CDC1631F E CDC1605F C CDC1607F C CDC1641F C CDC1652F C CDC1672F C EMU MCM Flash MASK ROM EMU MCM Flash Mask ROM Mask ROM Mask ROM Core CPU 16 bit 65C816 featuring software compatibility with its 8 bit NMOS and CMOS 6500 series predecessors CPU Active Operation FAST SLOW and DEEP SLOW FAST and SLOW Modes Power Saving Modes WAKE and IDLE CPU Inactive EMI Reduction Mode selectable in FAST mode Oscillators 4 MHz to 12 MHz Quartz RC 4 MHz to 12 MHz Quartz RAM 6 KB 2KB 6 KB 2 75 KB 4 KB 6 KB ROM ROMIess 256 KB Flash 64 KB ROMless 256 KB Flash 90 KB 128 KB 216 KB external pro bottom boot external pro bottom boot gram storage configuration gram storage configuration with up to internal 2 KB with up to internal 2 KB 16 MB internal Boot ROM 16 MB internal Boot ROM 2 KB Boot 2 KB Boot ROM ROM NOILVAYOANI 3ONVAGV 4 4Z0910090 IV2 809 LS29 002 LE YVEN SEeUOJOI N Table 1 1 CDC16xxF Family Feature List continued This Docu ment Item CDC1605F E CDC1607F E CDC1631F E CDC1605F C CDC1607F C CDC1641F C CDC1652F C CDC1672F C EMU MCM Flash MASK ROM EMU MCM Flash Mask ROM Mask ROM Mask ROM Multiplier 8 by 8 bit v Digital Watchdog v Central Clock Divider v Interrupt Controller 16 inputs 16 priority levels expanding NMI Port Interrupts including 4 inputs Slope Selection Port Wake Up Inputs v
12. Port output operable in Power Saving put Mode Timers amp Counters 16 bit free running CCCO with 3CAPCOM counters with Capture Compare modules 16 bit timers 1 TO 8 bit timers 2 T1 and T2 Real Time Clock Deliver v ing Hours Minutes and Seconds Miscellaneous Scalable layout in CAN v v RAM and ROM Various randomly select Most options SW programmable Mask pro Most options SW programmable able HW options copy from user program storage grammed copy from user program storage Core Bond Out v Supply Voltage 4 5 V to 5 5 V Temperature Range Tease 40 to 105C Tamb 40 to 85C Package Type Ceramic Plastic 100QFP Ceramic Plastic 100QFP 177PGA 0 65mm pitch 177PGA 0 65mm pitch Bonded Pins 176 100 176 100 4 4Z0910090 NOILWAYOANI H3ONVAGV SeUOJOIIN IV2 809 LS29 002 LE yey 1 2 Abbreviations AM CAN CAPCOM CPU DMA ERM IR LCD PO6COMP PINT PSM PWM RTC SM SPI TO T1 T2 UART Audio Module Controller Area Network Module Capture Compare Module Central Processing Unit Direct Memory Access Module EMI Reduction Module Interrupt Controller Liquid Crystal Display Module P0 6 Alarm Comparator Port Interrupt Module Power Saving Module 8 Bit Pulse Width Modulator Module Real time Clock Stepper Motor Control Module Serial Synchronous Peripheral Interface 16 Bit Timer 0 8 Bit Timers 1 and 2 Universal As
13. Sector 1 8KB 006000 Sector 2 8KB 008000 Sector 3 Boot ROM 010000 Sector 4 SB The device contains a 256 KB Flash 256 KB EEPROM of the AMD Am29F200BT type ESTER RER ALLER Flash bottom boot configuration This device exhibits FFFF 018000 EEPROM electrical byte program and sector erase functions Refer to the AMD data sheet for details 020000 Sector 5 64 KB 028000 030000 Sector 6 64 KB 08800 XP OSFFFF 040000 Sector 0 040000 lower 8 KB Bank 4 he a SIS eth A ent kas Git nt hs ws We SRL INTER tN a 041FFF 042000 mirrored Flash 1 EEPROM i CEREEER S oS cote oo ons CL a Rd See ed RR p E NER EE ERR Fig 4 1 Address Map 16 March 31 2003 6251 608 2Al Micronas ADVANCE INFORMATION CDC1607F E 5 Core Logic 5 1 Control Register CR The Control Register CR serves to configure the ways by which certain system resources are accessed during opera tion The main purpose is to obtain a variable system config uration during IC test Upon each HIGH transition on the RESETQ pin internal hardware reads data from the address location OOFFF3h and stores it to the CR The state of the TEST and ESTOPCLK pins at this timepoint specifies which program storage source is accessed for this read Table 5 1 Control byte source TEST Control byte source 0 or NC internal BOOT ROM standard for stand alone operation 1 external via mul
14. als by embedding them in a VSS trace The RESETQ pin adjacent to XTAL2 should be supplied with a 47 nF capacitor to prevent fast RESETQ transients from being coupled into XTAL2 to prevent XTAL2 from coupling into RESETQ and to guarantee a time constant of gt 200 us sufficient for proper Wake Reset functionality Micronas March 31 2003 6251 608 2Al 11 CDC1607F E ADVANCE INFORMATION 3 Electrical Characteristics 3 0 1 Absolute Maximum Ratings Table 3 1 UVss HVss1 HVss gt AVss 0V Symbol Parameter Pin Name Min Max Unit Vsup Core Supply Voltage VDD 0 3 6 0 V Port Supply Voltage UVDD Analog Supply Voltage AVDD SM Supply Voltage 1 HVDD1 SM Supply Voltage 2 HVDD2 AVDD Voltage Difference between VDD and VDD AVDD 0 5 0 5 V AVDD resp UVDD UVDD Isup Core Supply Current VDD VSS 100 100 mA Port Supply Current UVDD UVSS lAsup Analog Supply Current AVDD AVSS 20 20 mA IHsup SM Supply Current HVDD1 HVSS1 380 380 mA Q T 105C Duty Factor 0 71 HVDD2 HVSS2 Vin Input Voltage U Ports UVss 0 5 UVpp 0 7 V XTAL RESETQ TEST PO Ports UVss 0 5 AV ppt0 7 V VREF H Ports HVss 0 5 HVppt0 7 V lin Input Current all Inputs 0 2 mA lo Output Current U Ports 5 5 mA H Ports 60 60 mA toshsl Duration of Short Circuit in Port SLOW U Ports except indefinite S Mode to UVSS or UVDD U3 2 in DP Mode Tj Junction Temperature under Bias 45 115 C Ts Storage
15. m 60 C W Junction to Ambient Supply Currents CMOS levels on all Inputs no Loads on Outputs difference between any two VDDs within 0 2 V IpprF VDD FAST Mode Supply VDD 60 mA Flash Read 9 Current 80 Flash Write Erase 9 Ipps VDD SLOW Mode Supply VDD 1 8 mA all Modules OFF 9 Current Ippp VDD DEEP SLOW Mode VDD 1 5 all Modules OFF 9 Supply Current Ippi VDD IDLE Mode Supply VDD 50 75 uA fagi 4 MHz 9 Current 60 90 HA fyta 10 MHz 70 100 uA internal RC oscill Ippw VDD WAKE Mode Supply VDD 30 50 uA Current Ulppa UVDD Active Supply Cur UVDD 0 3 mA no Output Activity rent LCD Module ON Alppa AVDD Active Supply Cur AVDD 0 2 0 4 mA ADC ON ERM OFF rent 1 2 mA ERM ON fyta_ 8 4MHz Alppq Quiescent Supply Current AVDD 1 10 uA ADC and ERM OFF Ulppg UVDD 1 10 uA no Output Activity LCD Module OFF Elppq EVDD1 1 10 uA no Output Activity LCD EVDD2 Module OFF Hippa Sum of all 1 20 uA no Output Activity HVDD1 SM Module OFF HVDD2 1 Typical values describe typical behavior at room temperature 25 C unless otherwise noted with typical Recommended Operating Conditions applied derived from device characterization not 100 tested 2 Value may be exceeded with unusual Hardware Option setting Design value only the actually observable hysteresis may be lower due to system activity and related supply noise 4 When the ERM is active this time value is increased by 0 121 fXTAL e g 15 125 ns at 8
16. o SEG5 5 SEG6 7 CANO TX MULTI TEST IN U6 7 5 76 U5 6 PINT3 WP6 PWM2 SEG5 6 SEG6 6 PINT1 OUT CANO RX WP1 U6 6 6 75 U5 7 PINT3 UART1 RX PINTO OUT SEG5 7 SEG6 5 Ti OUT SPIO D IN U6 5 7 100 91 90 81 74 U2 0 GDO SEG2 0 ADBi16 SEG6 4 SPIO D OUT U6 4 8 73 U2 1 GD1 SEG2 1 ADB17 TEST 9 72 U2 2 GD2 SEG2 2 ADB18 RESETQ 10 71 U2 3 GD3 SEG2 3 ADB19 XTAL2 11 70 U2 4 GD4 SEG2 4 ADB20 XTAL1 12 69 U2 5 GD5 SEG2 5 ADB21 VSS 13 68 U2 6 GD6 SEG2 6 ADB22 VDD 14 67 U2 7 GD7 SEG2 7 ADB23 SEG6 3 SPIO CLK OUT SPIO CLK IN U6 3 15 66 AVSS SEG6 2 T1 OUT PINT2 IN WP5 U6 2 16 65 AVDD SEG6 1 LCD CLK OUT PINT1 IN WP4 U6 1 17 64 VREF SEG6 0 LCD SYNC OUT PINTO IN WP3 U6 0 18 63 PO 1 PO 1 digital input WEQ SEG1 7 CAN1 TX U1 7 19 62 P0 2 PO 2 digital input CEQ SEG1 6 CAN1 RX WP2 U1 6 20 61 P0 3 P0 3 digital input ITSTOUT SEG1 5 LCD CLK OUT UT 5 21 31 20171 50 60 P0 4 PO 4 digital input HWQ SEG1 4 LCD SYNC OUT U1 4 22 59 P0 5 PO 5 digital input PH2 BP3 U1 3 23 58 P0 6 P0 6 Compar inp OEQ BP2 U1 2 24 57 P0 7 BE BP1 U1 1 25 56 P0 8 RDY BPO ITSTOUT U1 0 26 55 P0 9 STOPCLK SMB1 H1 5 27 54 H2 0 SMC COMP SMC2 VPQ SMB1 H1 4 28 53 H2 1 SMC2 VPA SMB2 H1 3 29 52 H2 2 SMC1 VDA SMB2 SMB COMP H1 2 30 51 H2 3 SMC1 DB7 SME1 PWM2 H1 1 31 50 H2 4 WP9 PWMO DB6 SME1 PWMO H1 0 32 49 H2 5 Pol PWM4 HVDD1 33 48 HVSS2 HVSS1 34 47 HVDD2 DB5 SME2 H0 5 35 46 H3 0 PWM1 DB4 SME2 SME COMP H0 4 36 45 H3 1 PWM3 DB3 SMA1 H0 3 37 44 H3 2 SMD COMP SMD2 DB2 SMA1 H0 2 38 N
17. odules V2 0B 3 CANO CAN1 and CAN2 with 1 CANO with 3 CANO CAN1 and CAN2 with 1 CANO with 2 CANO and CAN1 with 256 byte object RAM each LCANOO009 puts LCANOOOF RAM LCANO0009 RAM LCANOOOF LCANO009 DIGITbus 1 master module 1 master module 1 master module Input amp Output Universal Ports select up to 52 I O or 48 LCD segment lines 2192 segments able as 4 1 mux LCD in groups of two configurable as I O or LCD Segment Backplane lines or Digital I O Ports Universal Port Slew Rate HW preselectable Stepper Motor Control 5 Modules 24 dl dt controlled ports Modules with High Cur rent Ports 8 bit PWM Modules 5 Modules PWMO PWM1 3 Modules 5 Modules PWMO PWM1 2 Modules 5 Modules PWMO PWM1 PWM2 PWM3 and PWM4 PWMO PWM1 PWM2 PWM3 and PWM4 PWMO PWM1 PWM2 PWM3 and PWM4 PWM2 Audio Module with auto v decay SW selectable Clock out 2 NOLLVINHOHNI 3ONVAGV 4 4Z0910090 IV2 809 LS29 002 LE yey SeUOJOI N Table 1 1 CDC16xxF Family Feature List continued during system start up according to user specifica tion during system start up This Docu ment Item CDC1605F E CDC1607F E CDC1631F E CDC1605F C CDC1607F C CDC1641F C CDC1652F C CDC1672F C EMU MCM Flash MASK ROM EMU MCM Flash Mask ROM Mask ROM Mask ROM Polling Flash Timer Out 1 High Current
18. or changes No part of this publication may be reproduced photocopied stored on a retrieval system or transmitted without the express written consent of Micronas GmbH 22 March 31 2003 6251 608 2Al Micronas
19. s TEST RV Reset Active Input Voltage RESETQ 0 9 V WRV Reset Active Input Voltage during RESETQ 0 6 V Power Saving Modes and Wake Reset RVim Reset Inactive and Alarm Active RESETQ 1 6 2 1 V Input Voltage RVin Reset Inactive and Alarm Inactive RESETQ 2 9 V Input Voltage WRVin Reset Inactive during Power Sav RESETQ UVpp V ing Modes 0 4V VREFi ADC Reference Input Voltage VREF 2 56 AVpp V POV PO ADC Input Port Input Voltage PO Ports 0 VREFi V Clock Input from External Generator XVii Clock Input Low Voltage XTAL1 0 2 Vpp V XVin Clock Input High Voltage XTAL1 0 8 Vpp V DXTAL Clock Input High to Low Ratio XTAL1 0 45 0 55 1 Typical values describe typical behavior at room temperature 25 C unless otherwise noted with typical Recommended Operating Conditions applied derived from device characterization not 100 tested Micronas March 31 2003 6251 608 2Al 13 CDC1607F E ADVANCE INFORMATION 3 0 3 Characteristics differing from Characteristics described in document CDC16xxF E Automotive Con troller Family User Manual Table 3 3 UVss HVss1 HV sso AVss 0V 45V lt Vpp AVpp UVpp lt 5 5 V 4 75 V lt HVpp1 HVpp2 lt 5 25 V TCASE 40 C to 105 fXTAL 10 MHz Symbol Parameter Pin Name Min Typ Max Unit Test Conditions Package R nje Thermal Resistance from 25 C W Junction to Case R nja Thermal Resistance fro
20. tifunction pins in Bus mode for test purposes only The system will thus start up according to the configuration defined in address location OOFFF3h automatically copied to register CR CR Control Register 7 6 5 4 3 2 1 0 r w RESLNGITSTTOG x MFM TSTROM IROM IRAM ICPU ROM r w RESLNGITSTTOG EBTRI MFM FLASH IROM IRAM ICPU Emu Value of OOFFF3h Res RESLNG Reset Pulse Length r w1 Pulse length is 4095 FxtAL r wO Pulse length is 16 Fytar This bit specifies the length of the reset pulse which is output at pin RESETQ following an internal reset If pin TEST is 1 the first reset after power on is short The following resets are as programmed by RESLNG If pin TEST is 0 all resets are long TSTTOG TEST Pin Toggle Tables 5 2 and 5 3 This bit is used for test purposes only If TSTTOG is true in IC active mode pin TEST can toggle the multifunction pins MFM Multifunction Pin Mode Tables 5 2 and 5 3 Table 5 2 TSTTOG and MFM usage in mask ROM parts TSTTOG MFM TEST pin Multifunction Pins 0 0 X Bus mode 1 0 0 Bus mode 1 normal mode x 1 X normal mode Table 5 3 TSTTOG EBTRI and MFM usage in Flash and EMU parts TST EBT MFM TEST Multi Emula TOG RI pin function tor Bus Pins Pins 0 x 0 X Bus Flash mode mode 1 x 0 0 Bus Flash mode mode 1 normal mode X 0
21. ynchronous Receiver Transmitter NOLLVINHOHNI 3ONVAGV 4 4Z0910090 CDC1607F E RESETQ NE Reset Alarm Watchdog Clock RC Oscillator m L xmi Lo XTAL2 VREF AVDD AVSS iR 9 5 a o mm 6 5 a I 6 5 EE a I 9 N 6 5 O o i e 6 5 o a I 1 j HVDD1 HVSS1 HVDD2 HVSS2 Power Saving Module Audio Module Multiplier 8 by 8 bit 10 Bit ADC Stepper Motor Control 8 Bit PWM 2 8 Bit PWM 0 8 Bit PWM 4 8 Bit PWM 1 8 Bit PWM 3 Patch Module 65C816 CPU 16 Inputs Interrupt Controller 6k RAM ROMless or 256kFlash Boot ROM LCD Control CAN 1 DMA Logic 8 Bit Timer 1 g 8 Bit Timer 2 CAPCOM 1 west E CAPCOM 2 E 16 Bit Timer 0 DIGITbus UART 0 B8 UART 2 Han Clock Out 0 NH Clock Out 1 ic CAPCOM 0 K UART 1 ADVANCE INFORMATION CAN 0 der ic Scalable within wide limits Fig 1 1 Block diagram of CDC1605F E CDC1607F E March 31 2003 6251 608 2Al Micronas ADVANCE INFORMATION CDC1607F E 2 Package and Pins 2 1 Package Outline Dimensions 29 x 0 65 18 85 80 51 ae HERARRARAARARARAANARARARARARAR 4 8 gj f 50 ET zm NN E N n 10 E 8 100 wey E 31 E Y PUTAS DOG
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