An0030 - Eurotech
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1. Reducing the cable length can allows users to reduce possible interference to the TFT LCD digital signals EurolecH 10 J4 TFT Digital Interface signal description The digital TFT interface signals are described in the following table SIGNAL NAME Dot Clock FP_HSYNC FP_VSYNC ENA_DISP VDD ENABLE DATA ENABLE BACKLIGHT ENABLE RED 5 0 GREEN 5 0 BLUE 5 0 GND Description Pixel Port Clock Dot Clock is the pixel dot clock output It clocks the pixel data Flat Panel Horizontal Sync Flat Panel Horizontal Sync establishes the line rate and horizontal Retrace interval for a TFT display Flat Panel Vertical Sync Flat Panel Vertical Sync establishes the screen refresh rate and vertical retrace interval for a TFT display Display Enable Display Enable indicates the active display portion of a scan line This is a data valid signal This is a useful signal which allow you to control the switching on off of the lamps Graphics Red Pixel Data Bus This bus drives graphics pixel data synchronous to the Dot Clock output Graphics Green Pixel Data Bus This bus drives graphics pixel data synchronous to the Dot Clock output Graphics Blue Pixel Data Bus This bus drives graphics pixel data synchronous to the Dot Clock output Ground Table 4 EurolecH Application Note Electrical Characteristics TTL 8mA Vumax 3 3V TTL 8mA Vmax 3 3V TTL 8mA Vumax 3 3V TTL 8mA Vmax 3 3V TTL 82. J7 J9 KB SPK WD IDE DOM VGA Ethernet Figure 1 Connectors layout The following table shows the J4 connector type and its matching models Connector Reference Connector Type J4 Used Connector Hirose DF13 40DP 1 25V J4 Corresponding connector Hirose DF13 40DS 1 25C Table 2 J4 mating connectors For futher information about connectors electrical mecanical please refer to the Hirose website http www hirose com referring to the DF13 connector family EurolecH Application Note 9 J4 TFT Digital Interface Pin Out The following table describes the signals of the J4 TFT Digital Interface connector PIN SIGNAL SIGNAL PIN FUNCTION 1 GND Dot Clock 2 3 GND RED5 MSB 4 5 Data Enable RED4 6 7 RED3 RED2 8 9 RED1 REDO LSB 10 11 BLUE5 MSB VDD Enable 12 13 BLUE4 BLUE3 14 LCD TFT 15 BLUE2 BLUE1 16 17 BLUEO LSB GREEN5 MSB 18 19 Back Light enable GREEN4 20 21 GREEN3 GREEN2 22 23 GREEN1 GREENO LSB 24 25 FP_VSYNC FP_HSYNC 26 27 GND_USB USBDP 28 Tee 29 USBDN VDD_USB 30 31 PC_BEEP VDD_CODEC 32 33 SDATA_OUT RSTDRV 34 35 SDATA_IN SYNC ggg CE CODEC 37 GND1_CODEC AC97_CLK 38 39 GND2 CODEC BITCLK 40 Table 3 J4 TFT Digital Interface connector pinout For further information about the physical layout of the J4 connector please refer to the Figure 1 layout This information is intended to help the user properly build the cable used to connect the Digital interface of the CPU 1432 with the TFT LCD panel selected
3. using the CPU 1432 TFT digital interface The goal is to help users properly connect TFT LCD panels to the CPU 1432 TFT Digital Interface Overview The CPU 1432 allows you to connect various models of LCD TFT panels via its J4 connector The following table shows the supported LCD TFT video resolutions Resolution 640x480 640x480 800x600 800x600 1024x768 1024x768 Table 1 Simultaneous Refresh Rate Colours Hz 8bpp 256 colours 60 16bpp 64K colours 60 8bpp 256 colours 60 16bpp 64K colours 60 8bpp 256 colours 60 16bpp 64K colours 60 LCD TFT video resolutions This list is not meant to be a complete list of all the possible supported TFT video For further info about other new supported LCD TFT flat panels please contact the Eurotech Customer Support Service 8 Application Note J4 TFT Digital Interface Connector The TFT digital interface is accessible via the J4 connector which is a 20x2 pitch 1 25mm SMT connector J4 J5 LCD TFT USB Parallel Floppy Audio CODEC Serial1 Serial2 O 1 39 L 39 1 A By O m o0 og oaj 1 NS zf Geode Gx1 Hi J15 Processor ao Slim sa Floppy Disk ogy agja 5 J3 as PCI BUS ae A Jt J2 RHEE ISA BUS NS Geode apla 8 J8 og o CS5530A a oja Cc D Ke Ae a J11 Companion a8 e Auxiliary C aa mm Power FO 1 2
4. EmbeddedDNA Eurolech THE COMPLETE EMBEDDED PC SOLUTION CPU 1432 TFT Digital Interface Rev 1 0 Sep 2003 COPYRIGHT 1994 2005 Eurotech S p A All Rights Reserved Application Note ABOUT THIS MANUAL This application note contains information about the TFT Digital Interface installed on the CPU 1432 EurolecH THE COMPLETE EMBEDDED PC SOLUTION Via J Linussio 1 33020 AMARO UD ITALY Phone 39 0433 485 411 Fax 39 0433 485 499 web _ http www eurotech it e mail mailto sales eurotech it NOTICE Although all the information contained herein has been carefully verified Eurotech S p A assumes no responsibility for errors that might appear in this document or for damage to property or persons resulting from an improper use of this manual and of the related software Eurotech S p A reserves the right to change the contents and form of this document as well as the features and specifications of its products at any time without notice Trademarks and registered trademarks appearing in this document are the property of their respective owners EurolecH Application Note Conventions The following table lists conventions used throughout this guide Icon Notice Type Description Important features or Information note instructions potential damage to a program system or device or potential personal injury Warning Information to alert you to EurolecH This page is intentiona
5. IOS setup but the contents are the same lt Horizontal gt Hsync Display period Note Figure 3 Timing Diagram Horizontal Mode EurolecH Application Note 15 lt Vertical gt Vsyne Display period Note Figure 4 Timing Diagram Vertical Mode The previous figures may be useful to graphically verify if the entered BIOS parameters match the TFT timing diagram Regarding the timing the following relationships should be ensured Horizontal Sync Period th Display Period thd Front Porch thf Pulse Width thp Back Porch thb Vertical Sync Period tv Display Period tvd Front Porch tvf Pulse Width tvp Back Porch tvb Practically referring to Table 6 and to Table 7 the results are Horizontal Sync 800 640 16 96 48 Vertical Sync 525 480 12 31 2 EurolecH 16 Application Note Chapter 3 Connecting the TFT LCD to the CPU 1432 This section contaisn a brief checklist of the actions to perform before connecting a TFT LCD to the CPU 1432 Q Download all information about the TFT LCD module and its inverter selected QO Verify that the resolution of the TFT panel is compatible with and suppported by the resolution shown in Table 1 of this Application note Q Read carefully the TFT LCD datasheet in particular the Electrical Characteristics that must be compatible with the electrical interface of the CPU 1432 TFT LCD interface referred to in Table 4 O Co
6. MA Vmax 3 3V TTL 8mA Vumax 3 3V TTL 8MA Vumax 3 3V TTL 8mA Vumax 3 3V TTL 8mA Vumax 3 3V TTL 8mA Vmax 3 3V Ground Signal Description Electrical Characteristics Application Note 11 Chapter 2 BIOS Setup To enable the TFT Digital Interface functionality the user should properly configure the BIOS settings This section illustrates the BIOS settings the user is allowed to modify for properly controlling the LCD TFT For further information on how to use the BIOS functionality please refer to the CPU 1432 user manual CPU 1432 BIOS Menu After entering BIOS setup by pressing the F2 Key during the boot time select the Flat Panel menu using cursors You will be prompted to the following menu General Devices Communications ATAPI Units Advanced Flat Panel PCI Legacy PCI Advanced Power Management Error Handling Quit custom 640x480 25 Figure 2 BIOS setup Flat Panel section EurolecH 12 Application Note CPU 1432 BIOS Flat Panel parameters Here a brief description of each field the user is allowed to modify from the BIOS setup program and its default value T Default Field Description Value Type Disabled Disabled Custom Custom parameters Hitachi 800x600 38MHz Disabled LG 800x600 38MHz NEC 800x600 38MHz Sharp 800x600 40MHz Bese uel 640x90 Select the proper graphical 800x600 Pocalition 640x480 1024x768 Dot Clock MHz Dot Clock Frequency in MHz 0 HS
7. e following instructions are an example showing how to define the values to enter into the Flat Panel BIOS setup according to the timing characteristics in Table 6 EurolecH 14 Application Note BIOS Field BIOS Value Notes Type Custom We would enter custom parameters Resolution 640x480 Obtained from the TFT LCD Data Sheet this is a characteristic Dot Clock MHz 25 Referring Table 6 CLK 1 Tc Typical value The reported value 25 175MHz is approximated to 25Mhz Referring Table 6 HSync Front Porch thf Typical value The HSync FP 2 reported value 16CLK So the value you ve to enter the BIOS is 2 to obtain 16 2x8 Referring Table 6 HSync Pulse width thp Typical value The HSync AT 12 reported value 96CLK The value you ve to enter the BIOS is 12 to obtain 96 12 x 8 Referring Table 6 HSync Pulse Back porch thb Typical value HSync BP 6 The reported value 48CLK The value you ve to enter the BIOS is 6 to obtain 48 6 x 8 Referring Table 6 VSync Front Porch tvf Typical value The VSync FP 12 reported value 12CLK Referring Table 6 VSync Pulse width tvp Typical value The VSync AT 2 reported value 2 H Vesna BE z Referring Table 6 VSync Back Porch thb Typical value The reported value 31CLK Table 7 Flat Panel BIOS parameters Timings Diagrams The followings images show a graphical mode to represent timing data The information is not represented in the same graphical order shown into the Flat Panel B
8. lly left blank Table of Contents CONVENTIONS seen a AS EARST AARTS TATA E O caus R OA EE EA VOA A tints 3 Table of Comte nt civcciccccs ceesscecees scitecececiets ceeactcneesceie a a a a eeeteneaesneietd crentee 5 Chapter 1 CPU 1432 TFT Digital Interface 000 2 cccesseeeeeeeeeeeeeeneneeeeeeeeeeeeseeesesesaeseeeseaeseseseanseseseenseeeseeaes 7 TET Digital Interface OVEMViOw 22 05 es sensi reaa aa ae eean di ete ee che a dee eee ee teh tee ee 7 J4 TFT Digital Interface Connector eea E E A AE AEAEE A EAEE 8 J4 TFT Digital Interface Pin Out vs 2 coci seca neeice denian ei kanei Eria i iaai i E iaeia 9 J4 TFT Digital Interface signal description aeiseeeeerieeeirreseerrsanrinneeennastenndstennnatinneattanaatenastennaatnansanan nanna 10 Chapter2 LOL e ETET E T 11 CPU 1432 BIOS MOM iit nite ead A eh A a ee ee 11 CPU 1432 BIOS Flat Panel parameters ccccececeeeeeeeecaeeeeeeeeeceneaeaeeeeeeeeeeseccaeaeeeeeeesesecsaaeeseeeseeeeenaeas 12 Defining CPU 1432 BIOS parameters 00 0 ccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeceeeeeeeseeeaeeeseeeaeeeseeeaeeesseneaeeeseneeeeseeaees 12 TIMINGS DIAGrAIMS v 32 E A od eee ecetevad tevin Ree eee ee ee eae ae 14 Chapter 3 Connecting the TFT LCD to the CPU 1432 cccccesssnteeeeseeneeeeseeneeeeseeneeenseeneeeeaseeneeensesenenees 16 This page is intentionally left blank Chapter 1 CPU 1432 TFT Digital Interface This brief application note contains information about
9. nsulting the TFT LCD datasheet and the Table 3 CPU 1432 connector pin out write a table with the connections between the J19 CPU 1432 connector and the TFT LCD selected this may be useful when building the connection cable a Consulting the TFT LCD inverter datasheet and Table 3 CPU 1432 connector pin out make the proper cable a Refer to the TFT LCD input signal timing datasheet section to detect the parameters to insert into the CPU 1432 BIOS Flat Panel section and calculate it as described in the Chapter 2 BIOS Setup Q To connect the system carefully verify the connections cable the BIOS settings and all the information to prevent erroneous damages to the system After you ve verified the information power up the system verifying all information is properly displayed on the TFT LCD module Try some graphical test programs to detect the functionality of the images EurolecH
10. ync FP Front Porch Horizontal Sync 0 HSync AT Active Time Horizontal Sync 0 HSync BP Back Porch Horizontal Sync 0 VSync FP Front Porch Vertical Sync 0 VSync AT Active Time Vertical Sync 0 VSync BP Back Porch Vertical Sync 0 Table 5 BIOS Flat Panel Section Options To properly enter the parameters the user should analyze the information contained in the TFT LCD datasheet that the user wishes to connect to the CPU 1432 and insert the data for the various fields Sometimes if connecting both a CRT and TFT LCD devices the image shown on the CRT is rescaled and shifted because the parameters for the TFT interface modify the video settings Defining CPU 1432 BIOS parameters To enter the proper parameters into the Flat Panel BIOS settings refer to the TFT LCD datasheet Table 6 shows an example of a timing table referring to a 640x480 TFT LCD EurolecH Application Note 13 eos Rise fall Hsync Period CLK wp w a Fonte O e o Fanciers ecu Fa Ca e ox ome Co e on Fresa DE mode wo ce ox lt a cae Feed ting mode thp thb Fae Fixed timing mode u j m o oeme i i me e a e e mmama feale e e ee eee em f e vane Peres ioe ele eee ae Ea T Display period lay period EEE a e foe Pie wan a a hae ee DE mode Fixed timing mode DE mode Rise fall oo maxs fae S e ame ce e COENE Table 6 Timing Characteristic Example for a TFT LCD Th
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