NPMC860SIO User`s Manual
Contents
1. eerte tere tee heces eee e ete 20 4 4 PME CONNECTOR P ZA ener deceret teet refe he ete refe eode emen 21 4 5 PMC CONNECTOR 14 Jk A E E a 22 4 6 THE FRONT PANEL CONNECTOR S1 orrn eia e eaer ar erias ii e aS ii eie inas 23 5 PROGRAMMER S REFERENCE e a aE EE r A 24 5 1 OSPAN Estote td e a na te sx etd te qu E e Ee 24 5 1 1 Host Setup of the QSpan PCI eene 24 5 1 2 Q Bus Configuration iesus tret tee eee tribe t keeper 26 5 1 3 EEPROM Corfigurdtiori te ta pte dete e Ne eet eden 26 3 2 ON BOARD FIRMWARE ee eet coved e E te rere Rae eee 27 5 2 1 Boot SoftWare ea RUE IUE 27 5 2 1 The Board Support Packages eese trennen trennen 27 5 2 2 No on board Operating System nor Application Software eese trennen 27 APPENDIX A POWERQUICC CBU terret t rH E re E TR e PER ETE Dee eSI TRY ES 28 APPENDIX B OSPAN BUS BRIDGES e e Sho RM e vede 29 APPENDIX RAM ROM 30 APPENDIX D DOCUMENTATION 2 01 32 APPENDIX E DOCUMENT S HISTORY 00 ccccccccccccssscccecsseeeceessececesseeceeseeecessaeeccnssseceenseeecseaseesenseeeeeenae 33 Version 1 7 N A T GmbH NP2. There is no restriction on accessing the SRAM The flash memory area is located on the PowerQUICC bus so that the reset vector table in the boot flash is visible to the CPU after power on reset The boot flash memory has a size of 2 MByte optionally 4 Mbyte and can directly be accessed by the CPU The flash memory area is 8 bit wide organised The flash memory is a 5V only device For programming the Flash is no extra programming voltage necessary Programming the flash memory is possible in two ways Programming the entire flash memory from the PCI bus The module must be in the RESET State Programming the flash memory in the run state of the PowerQUICC N A T GmbH 31 NPMC 860 SIO Technical Reference Manual Appendix D Documentation reference PCI Interface chip Company TUNDRA Title QSPAN 91 860 PCI to Motorola Processor Bridge Manual 860 PowerQUICC Company Motorola Inc Title MPC860 PowerQUICC User s Manual PCI Specification Company PCISpecial Interest Group Title Peripherial Component Interconnect PCI Interface Data Book Revision 2 1 Version 1 7 N A T GmbH 32 NPMC 860 SIO Technical Reference Manual Appendix E Document s History Revision Date Description Name 0 9 1998 initial revision ga 1 0 01 03 1999 Layout adaptation mz 1 1 22 07 1999 Layout improvement as 02 11 2000 improved Diagram espec concer
3. Setaddress translation decoding on register PBTIO ADD at offset 0x0104 host system dependent Write the start address where the memory of the NPMC 860 SIO module should appear in the Memory Space of the PCI bus 5 Make certain that there are no address conflicts in your systems set check the amount of the memory occupied by the NPMC 860 SIO in the PCI memory space Version 1 7 N A T GmbH 25 NPMC 860 SIO Technical Reference Manual 5 1 2 Q Bus Configuration Through the MISC CTL register parameters for configurating the local bus Q Bus are set The settings to be performed are system dependant But the following aspect has to be taken into account in any case Setting of bit 0 SW RST will cause a RESET on the Q Bus if the Q BUS HRESET signal is connected to the RESETO pin of the QSPAN like for this module The RESETO signal follows the programming of the SW RST bit directly i e without any delay in time Therefore if the MPC860 is to be reset by this means the minimum time period necessary to perform an orderly hardware reset of the MPC860 has to be strictly obeyed Otherwise the MPC860 may enter an undefined state A time period of 100ms is recommended between the setting and resetting of this bit In time critical applications this period may be reduced Any value longer than 1ms should be suuficient 100ms is a period of time which is suitable and safe for resetting the Q Bus in all cases and for all CPU operating fr
4. DEXTx signals are connected to internal GND SMC ports are always RS232 no optical isolation Table 11 General Pin Assignment of the Front panel Connector Pin RS232 RS422 RS485 Pin RS232 RS422 RS485 GNDEXTI GNDEXTI GNDEXTI RTS3 RTS3 fs 2 GNDEXTI GNDEXTI GNDEXT 6 RTS3 37 CTS3 CTS3 42 5 GNDEXT4 GNDEXT4 10 4 GNDEXT4 GNDEXT4 GNDEXT4 RC a2 Rer RD TDA Ce 15 GNDEXT2 GNDEXT2 GNDEXT2 RTS4 RTS4 16 GNDEXT2 GNDEXT2 GNDEXT2 50 _ RTS4 51 CTS4 CTS4 Rm 5 OS Lo 9M 155 56 157 nc 8 5 o gt ae 00009 ne 2 60 ne e 61 C GENEVE 62 38 29 0 61 TD SMCI TTD SMCI TD SMCI 32 RxD3 R Tj 66 TxD_SMC2 TxD_SMC2 TxD_SMC2 a 68 33 34 Tx 17 18 1T m 23 24 25 26 27 28 29 32 33 34 Version 1 7 N A T GmbH 23 NPMC 860 SIO Technical Reference Manual 5 5 1 Programmer s Reference QSPAN 5 1 1 Host Setup of the QSpan PCI Bridge In order to configure the NPMC 860 SIO to work on the PCI bus the following steps must be taken 1 Look up the address of the PCI bus controller of the NPMC 860 SIO in the Configuration Space of the PCI bus of the carrier board please refer to the manual for the carrier board The PCI bus con
5. MC 860 SIO Technical Reference Manual List of Tables TABLE 1 860 5 MEMORY 14 TABLE 2 NPMC 860 SIO INTERRUPT 2 1 2 2 2000000000000000000000000000000000000000000 15 TABLE 3 POWERQUICC PORT PIN USAGE PORT 15 TABLE4 POWERQUICC PORT PIN 0 22 2 1 0 0 16 TABLE 5 POWERQUICC PORT PIN USAGE PORT C 1 000000 000 0000000000 enne 16 TABLE 6 POWERQUICC PORT PIN USAGE PORT 17 TABLE 7 DEVELOPMENT PORT BDM AND JTAG CONNECTOR PINOUT OPTIONS 00000 18 TABLES PMC CONNECTOR PPT1 or erede rere heec TREE LEE EE PUER Ce E EIS 20 TABLB9 PMC CONNECTOR P12 into eie eese ned E in deve ee Pee PUR UR e egt 21 TABLE 10 5 eaten eem eo veni Dane 22 TABLE 11 GENERAL PIN ASSIGNMENT OF THE FRONT PANEL 2 0 23 TABLE 12 NPMC 860 SIO MEMORY IN THE CONFIGURATION SPACE 24 TABLE 13 NPMC 860 SIO MEMORY MAP IN THE PCI MEMORY SPACE esee enne enne 25 List of Figures FIGURE 1 NPMC 860 SIO ON A VMEBUS CARRIER c cccesssscecesssececssccececsseeecesssececesseeceenseee
6. Memory DRAM The NPMC 860 SIO provides 4 or 16 MByte EDO DRAM on board The DRAM is 32 bit wide Default 16 MByte assembled Flash PROM The 8 bit boot Flash PROM provides a maximum capacity of 4 MByte Default 2 MByte assembled SRAM The high speed 32 bit SRAM capacity is 512 KByte max Default 128 KByte assembled Version 1 7 N A T GmbH NPMC 860 SIO Technical Reference Manual e Interfaces The NPMC 860 SIO includes a 32 bit 33 MHz PCI bus interface T O The 4 SCC channels and the 2 SMC channels are connected to the front panel connector by serial transceivers which optionally can form RS232 RS422 or RS485 interfaces All SCC channels may be optically decoupled separately The SMC channels are hard wired to 2 RS232 ports no handshake Alternatively all signals of the SCCs the SMCs the SPI and the PC ports are available on the PMC I O connector To be used there all front panel transceivers have to be disabled The normal data rate supported for RS232 is 115 KBaud for RS422 and RS485 it is 500 KBaud As an assembly option special drivers may be installed to support RS422 and RS485 data rates up to 10 Mbaud Depending on the application running and the number of interfaces used with high data rates the 80 MHz option CPU option may be applicable e CPU Depending on the used CPU the PowerQUICC runs with a minimum frequency of 33 MHz 40 50 or 80 MHz are optionally available Default 50 MHz C
7. NPMC 860 SIO Reference Manual NPMC 860 SIO CPU PMC Module Technical Reference Manual V1 7 HW Revision 1 1 NPMC 860 SIO Technical Reference Manual The NPMC 860 SIO has been designed by N A T GmbH Kamillenweg 22 D 53757 Sankt Augustin Phone 49 2241 3989 0 Fax 49 2241 3989 10 E Mail sales nateurope com Internet http www nateurope com Version 1 7 N A T GmbH NPMC 860 SIO Technical Reference Manual Disclaimer The following documentation compiled by N A T GmbH henceforth called N A T repre sents the current status of the product s development The documentation is updated on a regular basis Any changes which might ensue including those necessitated by updated speci fications are considered in the latest version of this documentation N A T is under no obli gation to notify any person organization or institution of such changes or to make these changes public in any other way We must caution you that this publication could include technical inaccuracies or typographi cal errors N A T offers no warranty either expressed or implied for the contents of this documentation or for the product described therein including but not limited to the warranties of merchant ability or the fitness of the product for any specific purpose In no event will N A T be liable for any loss of data or for errors in data utilization or processing resulting from the use of this product or the documentatio
8. PMC 860 SIO Technical Reference Manual Table of Contents b CINTRODUCTION eiiecco ti tecti tees hte ete yet tei bo eer Here E RE te T EEE 6 IT SPEGIEICATION t iate diee eie Ue 9 2 ON ERIS 10 24 acida eite Bee 10 22 INSTALLATION PREREQUISITES AND 11 2 2 1 Requirements ad ae e eR PAG RATE OR BERE ERE Be EAD ERE GERE ERE Ma rex 11 2 2 2 Power Supply ato ete e re ree P o Pu ee i ge ve Fee e eo 11 2 3 eee Ce Fe ERR eC ER TERRI E AREE Ee S 12 2 4 AUTOMATIC POWER UP a eaa AE eee att E a as GB ER eaea 13 2 5 SWITCH SETTINGS eed estre 13 3 HARDWARE 55 00 400400000 0 00000000 14 3 1 MEMORY MAP uie Eee eec ee eee nce Te te ie ais EE E re a eal 14 3 2 INTERRUPT STRUCTURE eee eae eter Peg ewe e VE e eR CET VENERE E RW 15 3 3 POWERQUICC PORT PINS USAGE 2 oem edntavo e ict c b c pde 15 CONNECTORS odeur tere eo lt E e REV te 18 4 1 DEVELOPMENT PORT BDM AND JTAG 18 4 2 CONNECTOR 19 4 3 22
9. PU assembled Version 1 7 N A T GmbH NPMC 860 SIO Technical Reference Manual 1 1 Specification Processor PowerQUICC MPC860 based Embedded PowerPC Architecture PMC Module Standard PCI Mezzanine Card Type 1 PCI to QBUS bridge QSPAN Micro SCSI connector Main Memory 4 16 MByte EDO DRAM Flash PROM 2 4 MByte Flash PROM On board programmable Fast SRAM opt up to 512kByte fast SRAM serial Interfaces RS232 115 KBaud RS422 and RS485 500 KBaud up to 10MBaud opt PSOS BSP VxWorks BSP on request Power consumption 3 3V 0 5A 5 0 0 6A Environm conditions Temperature operating Temperature storage 40 C to 85 C ae 5 to 95 non condensing Humidity Standards compliance PCI Rev 2 1 P1386 1 Draft 2 4a 0 C to 50 C Version 1 7 N A T GmbH 9 NPMC 860 SIO Technical Reference Manual 2 Installation 2 1 Safety Note To ensure proper functioning of the NPMC 860 SIO during its usual lifetime take the following precautions before handling the board CAUTION Malfunction or damage to the board or connected components Electrostatic discharge and incorrect board installation and uninstallation can damage circuits or shorten their lifetime e Before installing or uninstalling the board read this installation section e Before installing or uninstalling the NPMC 860 SIO read the Installation Guide and the User s Manual of the NPMC 860 SIO carrier board e Before installing or uninstall
10. cessaeeecnsseeceensseeeseaaess 6 FIGURE 2 NPMC 860 SIO BLOCK DIAGRAM cccccccssscccesssececesseececesececeesseeecsssseeecnssseceenseeecsesseeecnsseeeeenteeeeseaaees 7 FIGURE 3 LOCATION DIAGRAM OF THE NPMC 860 SIO 12 FIGURE 4 CONNECTORS OF THE NPMC 860 SIO sess nennen ener nene 19 Version 1 7 N A T GmbH NPMC 860 SIO Technical Reference Manual 1 Introduction The NPMC 860 SIO is a high performance standard CPU PCI Mezzanine Card Type 1 It can be plugged onto any carrier board supporting PMC standards Figure 1 NPMC 860 SIO on a VMEbus carrier Backplane Connectors m NPMC 860 SIO NPMC 8280 4E1 T1 J1 Back View Back View The NPMC 860 SIO has the following major features on board e PowerQUICC MPC860 based Embedded PowerPC Architecture e Front panel I O e PCI Bus interface e Single Slot VME solution together with the PMC carrier board Version 1 7 N A T GmbH NPMC 860 SIO Technical Reference Manual Figure 2 NPMC 860 SIO Block Diagram i 50 66 80 MHz 32 Bit PMC Bridge 128 256 512 KByte MPC860 Fast SRAM PowerQUICC 4 16 MByte 50 66 80 MHz Connector DRAM FlashPROM 2 4 MByte PMC l O Assembly Option Assembly Option optical isolation SCC1 SCC4 SMC1 2 SPI I2C The onboard devices are in detail as follows e
11. e 9 PMC Connector P12 Ext Signal PCI Signal PCI Signal Ext Signal GND 6 GND GND PCLRSV3 8 NC N C 9 PCLRSV N C 2 RST BUSMODE 3 4 GND PCI_AD30 PCI_AD29 GND PCI AD26 PCI AD24 3 3V IDSEL PCI AD23 43 3 PCI_AD20 18 GND ADI6 CBE2 GND N C TRDY 3 3 GND STOP PERR GND 3 3 SERR CBEI GND PCI ADI4 PCI ADI3 GND PCI ADIO PCI ADOS 3 3 PCI AD07 N C 3 3 N C N C GND N C N C GND RESV_ 60 NC GND Version 1 7 N A T GmbH 21 NPMC 860 SIO Technical Reference Manual 45 Connector P14 10 14 Signal Signal CTS SCCI o 6 CTSSCC2 RTS SCCI 1 8 RTSSCC CD SCCI 9 BRGO SCCI CLK2 CLK4 LITSYNCA LITSYNCB LIRSYNCA LIRSYNCB LIST3 1 1874 LIRxDA LIRxDB LITxDA LITxDB RxD_SCC3 RxD_SCC4 TxD_SCC3 TxD_SCC4 CTS_SCC3 CTS_SCC4 RTS_SCC3 RTS_SCC4 CD_SCC3 CD_SCC4 BRGO_SCC3 BRGO_SCC4 CLK6 CLK8 c nc nc nc nc RxD SMCI TxD SMCI 60 TxDSPI Version 1 7 N A T GmbH NPMC 860 SIO Technical Reference Manual 4 6 The Front Panel Connector S1 The front panel connector is a micro SCSI II connector 68 pins The serial interfaces RS232 RS422 RS485 are available on the pins of the front panel connector The pin assignment shows all possible configurations If optical isolation is not required the GN
12. equencies 5 1 5 EEPROM Configuration By means of register EEPROM C S the Configuration EEPROM may be read and reprogrammed which the QSPAN uses for Power Up initialialisation Please be aware of the fact that programming the EEPROM with unsuitable values may cause the PCI Bus to hang completely NOTE For more information please refer to the QSpan manual Please make certain that you use the correct endian format when writing into the QSpan registers Version 1 7 N A T GmbH 26 NPMC 860 SIO Technical Reference Manual 5 2 On board Firmware 5 2 1 Boot Software After a power up or reset the on board firmware starts automatically with the basic memory and I O tests 5 2 1 The Board Support Packages If the NPMC 860 SIO is delivered with a vx Works BSP please refer to the vx Works BSP Readme file for the implementation details of this BSP 5 2 2 No on board Operating System nor Application Software If the NPMC 860 SIO is delivered without operating system or protocol software please take the following steps e Refer to the MPC860 manual for information on how to generate your boot code e Configure the local memory map see Figure 7 the interrupt registers of the 860 Load your boot code into the FlashPROM of the NPMC 860 SIO while the MPC860 is in RESET mode and start the code Version 1 7 N A T GmbH 27 NPMC 860 SIO Technical Reference Manual Appendix A PowerQUICC CPU Introduction V
13. ersion 1 7 The MPC860 PowerPC Quad Integrated Communications Controller PowerQUICC is a versatile one chip integrated microprocessor and peripheral controller combination that can be used in a variety of applications It particularly excels in both communications and networking systems The MPC860 is a PowerPC based derivative of Motorola s MC68360 Quad Integrated Communications Controller QUICC The CPU on the MPC860 is a 32 bit PowerPC implementation that incorporates memory management units MMUS and instruction and data caches The communications processor module CPM of the MC68360 QUICC has been enhanced with the addition of the interprocessor integrated controller channel Moderate to high digital signal processing DSP functionality has been added to the CPM The memory controller has been enhanced enabling the MPC860 to support any type of memory including high performance memories and newer dynamic random access memories DRAMs Overall systems functionality is completed with the addition of a PCMCIA socket controller supporting up to two sockets and a real time clock For further information please consult the MPC860 User s Manual supplied by Motorola N A T GmbH 28 NPMC 860 SIO Technical Reference Manual Appendix QSpan Bus Bridge Introduction Features Version 1 7 The QSpan chip is a member of Tundra Semiconductor Corporation s family of PCI bus bridging devices The QSpan is d
14. esigned to gluelessly bridge the QUICC MC68360 the PowerQUICC as well as the MPC801 embedded controllers to PCI The QSpan has the following features e A direct connect interface to the PCI bus for Motorola s QUICC MC68360 PowerQUICC MPC860 M68040 the PMC821 and the MPC861 embedded controllers 32 bit PCI interface compliant with PCI Revision 2 1 Decoupled transfer technology three 16 entry deep FIFOs buffer multiple transaction in both directions allowing zero wait state bursting on the PCI and Motorola buses IDMA peripheral support for QUICC and PowerQUICC Flexible address space mapping and translation between the PCI and Motorola buses Programmable endian byte ordering Two user programmable slave images available for PCI access to the Motorola buses QSpan control and status registers accessible from both PCI and Motorola buses PCI bus and Motorola buses can be operated at different clock frequencies N A T GmbH 29 NPMC 860 SIO Technical Reference Manual Appendix C RAM ROM DRAM Version 1 7 The NPMC 860 SIO provides an on board DRAM EDO DRAM This memory is accessible from the PowerQUICC or the QSPAN PCI bridge chip The memory controller of the PowerQUICC is responsible for controlling the DRAM This flexible memory controller allows the implementation of memory systems with very specific timing requirements The user is allowed to define different timing patters for the contro
15. ing optical Isolation mz Pin Assignment of connector S1 corrected pin65 66 1 2 22 03 2001 Memory layout map corrected description of IMSEL ga Also minor changes in signal names 1 3 30 10 2001 minor amendments in various chapters ga 1 4 22 11 2001 Programmer s Reference added some corrections ga concerning address map and interrupts 1 5 24 01 2002 Chapter 2 4 adapted to NW Rev 1 0 ga 1 6 25 08 2003 Chapters 3ff new organized port pin description added ga figure 4 corrected 17 25 10 2005 Figure updated serial transfer rate info added ga Version 1 7 N A T GmbH 33
16. ing the NPMC 860 SIO on a carrier board or both in a VME cPCI rack Check all installed boards and modules for steps that you have to take before turning on or off the power Take those steps Finally turn on or off the power e Before touching integrated circuits ensure to take all require precautions for handling electrostatic devices e Ensure that the NPMC 860 SIO is connected to the carrier board via all PMC connectors and that the power is available on both PMC connectors GND 5 and 3 3V e When operating the board in areas of strong electromagnetic radiation ensure that the module is bolted to the front panel or VME cPCI rack and shielded by closed housing Version 1 7 N A T GmbH 10 NPMC 860 SIO Technical Reference Manual 2 22 Installation Prerequisites and Requirements IMPORTANT Before powering up e check this section for installation prerequisites and requirements 2 2 1 Requirements The installation requires only e acarrier board for connecting the NPMC 860 SIO e apower supply 2 2 2 Power Supply The power supply for the NPMC 860 SIO must meet the following specifica tions 3 3V 0 5 A typical 5 0V 0 6 A typical Version 1 7 N A T GmbH 11 NPMC 860 SIO Technical Reference Manual 2 3 Location Overview The figure 1 Location Diagram of the NPMC 860 SIO highlights the position of the important components Depending on the board type it might be that your board d
17. l 3 NC IRQ Level 4 NC IRQ Level 5 NC IRQ Level 6 NC IRQ Level 7 lower level 3 3 PowerQUICC Port Pins Usage Table 3 Signal Function PowerQUICC Port Pin Usage Port A PowerQUICC Port A Pin Description RxD SCCI 15 RxD SCCI TxD SCCI PA14 TxD SCCI RxD SCC2 PA13 RxD SCC2 TxD SCC2 PA12 TxD_SCC2 LITxDB TDM only on P14 LIRxDB PA10 TDM only on P14 LITxDA PA9 TDM only on P14 LIRxDA PA8 TDM only on P14 BRGO SCCI Clock Out CLK2 PA6 Clock In SCC1 BRGO_SCC2 PAS Clock Out SCC2 CLK4 PA4 Clock In SCC2 BRGO_SCC3 PA3 Clock Out SCC3 CLK6 PA2 Clock In SCC3 BRGO_SCC4 PAI Clock Out SCC4 CLK8 PAO Clock In SCC4 Version 1 7 N A T GmbH 15 NPMC 860 SIO Technical Reference Manual Table 4 Signal Function PowerQUICC Port Pin Usage Port B PowerQUICC Port B Pin SPISEL PB31 SPI only on P14 SPICLK PB30 SPI only on P14 SPI TxD PB29 SPI only on P14 SPI RxD PB28 SPI only on P14 SDA PB27 data SCL PB26 clock TxD SMCI PB25 TxD SMCI RxD SMCI PB24 RxD SMCI DMAACK PB23 DMA Ack QSpan not used PB22 TxD SMC2 PB21 TxD SMC2 RxD SMC2 PB20 RxD SMC2 RTS SCCI PB19 RTS SCCI RTS_SCC2 PB18 RTS SCC2 LIST3 17 TDM only on P14 LISTA 16 TDM only on P14 not used PB15 IMSEL PB14 Image Select for QSpan Table 5 Po
18. l signals that govern a memory device This patterns define how the external control signals behave in a read access request write access request burst read access request or burst write access request The user defines how the external control signals toggle when the periodic timers reach the maximum programmed value for refresh operation The memory capacity is 4 MByte optionally 16 MByte the memory is 32 bit wide The access time of the EDO DRAM is 60 nsec for new accesses the access time within a row is 30 nsec bursting For different operating frequency of the MPC860 the user need to define different timing patters The User Programmable Machine A UPM A controls the PowerQUICC and the PCI accesses to the DRAM memory In the PowerQUICC Reset state accesses to the DRAM will be inhibited Parity generation and check will not supported by the module N A T GmbH 30 NPMC 860 SIO Technical Reference Manual SRAM Boot Flash Version 1 7 The NPMC 860 SIO provides optionally an on board high speed SRAM This memory is accessible from the PowerQUICC or the QSPAN PCI bridge chip The memory controller of the PowerQUICC is responsible for controlling the SRAM This flexible memory controller allows the implementation of memory systems with very specific timing requirements The memory capacity is 128 kByte optionally 256 kByte the memory is 32 bit wide The access time of the SRAM is 10 nsec for every access type
19. n In particular N A T will not be responsible for any direct or indirect damages including lost profits lost savings delays or interruptions in the flow of business activities including but not limited to special incidental consequential or other similar damages arising out of the use of or inability to use this product or the associated documentation even if N A T or any authorized N A T representative has been advised of the possibility of such damages The use of registered names trademarks etc in this publication does not imply even in the absence of a specific statement that such names are exempt from the relevant protective laws and regulations patent laws trade mark laws etc and therefore free for general use In no case does N A T guarantee that the information given in this documentation is free of such third party rights Neither this documentation nor any part thereof may be copied translated or reduced to any electronic medium or machine form without the prior written consent from N A T GmbH This product and the associated documentation is governed by the N A T General Conditions and Terms of Delivery and Payment Note The release of the Hardware Manual is related to a certain HW board revision given in the document title For HW revisions earlier than the one given in the document title please contact N A T for the corresponding older Hardware Manual release Version 1 7 N A T GmbH N
20. ode BDM functionality if set to On when the module is reset If set to Off the MPC860 boots normally from FLASH Version 1 7 N A T GmbH 18 NPMC 860 SIO Technical Reference Manual 4 22 Connector Overview Figure 4 Connectors of the NPMC 860 SIO P11 1 NPMC 860 SIO Please refer to the following table to look up the pin assignment of the NPMC 860 SIO Version 1 7 N A T GmbH 19 NPMC 860 SIO Technical Reference Manual 4 3 Connector P11 Table 8 PMC Connector P11 Ext Signal PCI Signal PCI Signal Ext Signal 4 TO py Dv N 6 Dpsv js J RSVI 10 PCI RSV2 12 JN c GNE Tu TAM GNT BN i sv AD31 20 PCLADSI PCI AD28 22 PCI_AD22 PCI AD25 4 GND 6 CBE PCI AD2 SV PCI ADI FRAME DEVSEL C 4l N C 43 PAR GND PCI ADIS PCI ADI2 ADIT 5v 52 54 2 56 2 10 12 14 16 18 2 2 2 2 N GND NC _ CLK GND REQ AD2S AD25 23 ND 25 Nc i FRAME DEVSEL 37 GND 39 INC SI PCI AD09 GND 531 GND 52 CBEO PCI AD06 54 PCI AD05 PCI AD04 56 GND N C Dot PCI 59 2 ADO 60 PCI_ADOI PCI ADOO Ou UA Version 1 7 N A T GmbH NPMC 860 SIO Technical Reference Manual 4 4 PMC Connector P12 Tabl
21. oes not include all components named in the location diagram Figure 3 Location Diagram of the NPMC 860 SIO J2 PCI Bridge D driver C coupler 81 C S PCI CPU R 7 M Top View D R A SRAM M driver coupler FLASH area Bottom View Version 1 7 N A T GmbH 12 NPMC 860 SIO Technical Reference Manual 2 4 Automatic Power Up In the following situations the NPMC 860 SIO will automatically be reset and proceed with a normal power up Voltage sensors The voltage sensor generates a reset e when 5V voltage level drops below 4 4V e when 5V voltage level rises above 5 6V e when 3 3V voltage level drops below 2 65V e when 3 3V voltage level rises above 3 9V e or when the carrier board signals a PCI Reset Watchdog timer Per factory default the watchdog timer of the PowerQUICC is disabled If the watchdog timer is enabled it generates an non maskable interrupt NMJ fol lowed by a reset when it is not retriggered by software see the PowerQUICC users manual PCI Specifications Revision 2 1 Section 4 2 1 1 and Section 4 3 2 2 5 Switch Settings There is a 8 position DIP switch SW1 on the NPMC 860 SIO 7 bits of which can be used for customer configuration settings Switch positions 1 7 are readable by software Position 8 of the switch enables the BDM functionality if set to On when the module is rese
22. t All options necessary for normal operation are pre installed in the factory By default SW1 8 is set to Off Version 1 7 N A T GmbH 13 NPMC 860 SIO Technical Reference Manual 3 Hardware Details 3 1 Memory Map All addresses are set up by programming the corresponding Chip Select Decoder of the PowerQUICC The given addresses represent only one possible configuration This configuration is used by N A T firmware Table 1 NPMC 860 SIO Memory Map Device CS Default Function Notes Line Address Flash PPROM FF000000 2 4 MByte Flash Prom 8 Bit wide DRAM 00000000 416 MByte EDO DRAM 32 Bit wide Fast SRAM 01800000 77 128 256k Fast SRAM 32 Bit wide QSPAN CS3 1000 0000 PCIbus window to the PCI bus 32 Bit wide access There are two PCI images available selected by the IMSEL Signal This signal is generated by the Port PB14 Alternately it may be generated by Port PD15 if R4 OQ is installed In this case PB14 has to be set to tristate By default R4 is not installed Qbus access to the QSPAN Registers Registers 32 Bit wide 4467 Version 1 7 N A T GmbH 14 NPMC 860 SIO Technical Reference Manual 3 2 Interrupt Structure The NPMC 860 SIO has the following Interrupt structure Table2 NPMC 860 SIO Interrupt Mapping Interrupt source PowerQUICC Interrupt level NC IRQ Level 0 highest level NC IRQ Level 1 NC IRQ Level 2 QSPAN IRQ Leve
23. troller of the NPMC 860 SIO occupies 256 Bytes in the Configuration Space and you should see the following address map first 64 bytes according to PCI specification 2 1 Table 12 NPMC 860 SIO Memory Map in the Configuration Space control and status 0 000 PCI MISCO 0x0010 PCI BSM base address for memory 0 003 PCI MISCI For more details regarding the QSpan registers of the NPMC 860 SIO please refer to the QSpan manual s register map Table A 1 App A 2 Now write to the offset address 0x0010 QSpan register PCI BSM 32 bit the start address of the NPMC 860 SIO where it should appear in the memory space of the carrier board s PCI bus Please note that all PCI register accesses have to be done in little endian format The register image of the QSpan should now be visible in the PCI memory space Version 1 7 N A T GmbH 24 NPMC 860 SIO Technical Reference Manual Table 13 NPMC 860 SIO Memory Map in the PCI Memory Space control and status 00014 QSpanunimplemened 0 003 PCI MISCI 0 800 MISC CTL 0x804 EEPROM CS EEPROM control OxOffc QSpan reserved 3 Initialize the register PBTIO CTL for target image 0 and set the necessary parameters The longword read write access must be enabled by writing the at offset 0x0100 image enable block size BS 3 0 0110 4 MB or BS 3 0 1000 16 MB Q bus destination port size DSIZE 1 0 00 32 bit 4
24. werQUICC Port Pin Usage Port C Signal Function PowerQUICC Port C Pin Description DMAREQ 15 DMA Ack QSpan not used PC14 not used PC13 not used PC12 CTS_SCC1 11 CTS SCCI CD SCCI PC10 CD SCCI CTS SCC2 PC9 CTS SCC2 CD SCC2 PC8 CD SCC2 CTS_SCC3 PC7 CTS SCC3 CD_SCC3 PC6 CD SCC3 CTS 5 5 5 5 CD 5 CD SCC4 Signals with asterisk are described in detail below Version 1 7 N A T GmbH 16 NPMC 860 SIO Technical Reference Manual Table 6 PowerQUICC Port Pin Usage Port D Signal Function PowerQUICC Port D Pin Description LITSYNCA PD15 TDM only on P14 alternate IMSEL Image Select for QSpan LIRSYNCA PD14 TDM only on P14 LITSYNCB PD13 TDM only on P14 LIRSYNCB PD12 TDM only on P14 RxD_SCC3 PD11 RxD SCC3 TxD_SCC3 PD10 TxD SCC3 RxD_SCC4 PD9 RxD SCC4 TxD_SCC4 PD8 TxD SCC4 RTS_SCC3 PD7 RTS SCC3 RTS_SCC4 PD6 RTS SCC4 not used PD5 not used PD4 not used PD3 Version 1 7 N A T GmbH 17 NPMC 860 SIO Technical Reference Manual 4 Connectors 4 1 Development Port BDM and JTAG Connector Table7 Development Port BDM and JTAG Connector Pinout Options Development Port BDM Port GND TCK GND VFLSI TDI 5 TDO The location of the BDM port connector be seen in figure 4 on the following page Position 8 of the DIP switch SW1 enables the Background Debug M
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