TLL5000 Electronic System Design Base Module
Contents
1. VGA S Vico Nc on wecrmucour um Figure 2 9 Various interfaces in TLLS009 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 Chapter 3 Digital Design using Xilinx ISE In this section we will introduce the steps needed to create digital design with the schematic entry method of circuit design Schematic entry is often a starting step in learning digital design prior to the Hardware Description Language approach to digital design but can also be used Concurrently with HDL approaches when a block diagram or circuit view Is the most natural method of specifying the design Now let us start with a basic design 1 Run the ISE application by double clicking on the shortcut icon for the ISE tool or selecting it from your Programs menu Figure 3 1 Invoking Xilinx IS 2 When the tool is invoked the following windows will appear in the ISE tool Woes opar Ses ee oom ali Figure 3 2 XILINX welcome screen Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 Now a new project has to be created To create a new project cick on the File menu and Select New Project option Figure 3 3 Creating a new project When the new p2. Figure 4 25 Applying numbers 28 After entering the pin numbers in the LOC field save the file and exit the PACE tool Then in the Sources for window in ISE select the VHD file and run the Generating Programming File process This process will generate the bit file which can be downloaded onto the FPGA 56 Copyright 2007 The Learning Labs Inc TLLS000 Electronic System Design Base Module Getting Started Manual v3 2 This process wil run all the ether processes that are there before the generation of the programming file An individual process may also be run separately TXITICUETIMUTNT 9 Edt vio Project Scurco Process Window H Deana olsen s 3 ea EE li e e SMe IO O jee m E Decr waman 10 El E E eoe ES Processes lor B Behaviors 31 LE abem amay n 8 35 mus H WE Ronn al ls E Figure 4 26 Generating bit fle 57 Copyright 2007 The Learning Labs Inc 5000 Electronic System Design Base Module Getting Started Manual v3 2 Programming TLL5000 29 After completing Generating Programming File process expand Generating Programming File process tab in the Process for window and run Configure Device IMPACT process When this process is executed the target board has to be connected with the appropri
3. Electronic System Design Base Module Getting Started Manual v3 2 TLL5000 Electronic System Design Base Module The Learning Labs Inc Copyright 2007 Manual Revision 2007 12 28 1 Copyright 2007 The Learning Labs Inc 5000 Electronic System Design Base Module Getting Started Manual v3 2 Copyright Notice The Learning Labs Inc TLL All rights reserved 2007 Reproduction in any form without permission is prohibited Disclaimer Information in this document is subject to change without notice and does not represent a commitment on the part of TLL TLL provides this document as is without warranty of any kind expressed or implied including but not limited to the warranty of merchantability or fitness for a particular purpose TLL may make improvements and or changes in this manual or in the products s and or the program s described in this manual at any time Information in this manual is intended to be accurate and reliable However TLL assumes no responsibility for its use for any infringements of rights of other parties which may result from its This document could include technical or typographical errors Changes are periodically made to the information herein these changes may be incorporated in new editions of the publication This manual is provided solely and exclusively for educational use and this information or related products should not be used nor relied upon
4. ET D Co Figure 4 5 Selecting target hardware Note 1 The Simulator Chosen ModelSim XE Synthesis Tool XST this is the built in Webpack 158 Note 2 The device Package and speed are chosen based on the detalls of an FPGA chip on the TLLS000 XC351500 afg676 XC Xilinx Component 38 Device Family in this example itis Spartan 3 Family 1500 Device Gate density As per this example 1500 kilo gates are present in this chip 4 Speed Grade FG Package type Fine pitch Ball Grid Array 676 Number of 1 05 on the chip a Copyright 2007 The Learning Labs Inc TLLS000 Electronic System Design Base Module Getting Started Manual v3 2 To create new source click on the New Source button ue Ti rm Figure 4 6 Creating new source fie 7 When the new source button is clicked give a file name for the Input source code and select the file type from the left hand side list In this example it is a VHDL module Is VER rom zx JD Lm SEE Figure 4 7 Selecting file type 43 Copyright 2007 The Learning Labs Inc 5000 Electronic System Design Base Module Getting Started Manual v3 2 After giving the file name amp file type the input and output port list of the design has to be given Port list is the top level
5. pun den peser tei aee Froana em Figure 3 32 Synthesizing the design 36 When the next button is clicked the Associate Source window gets opened Here select the appropriate entity file name If only one file is added to the project then by default the same is Selected If more than one number fles are there only then we need to select the file entity name 29 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 37 Select the fle entity name and click on Next pM E te Figure 3 33 Selecting an associated source 38 Then again click on the Finish button If any changes are to be made click on Back and make the required changes IET EU pe SR ue nets Caron i Brie Nae aa m Figure 3 34 File summary 30 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 39 When this is completed the ucf file is created and added to the project To check this click on the sign beside the input file name in the Sources for window In this example design the pin constraints wil be in the uct Deuh nnen elms SR Gd 111358260 m Be 1 TER
6. 52 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 22 Once the simulation is run the output for the given input can be observed in the wave window This is known as functional simulation in which only the software code is simulated prior to the design being implemented directly on the hardware File edt vew men romat Toole window Figure 4 21 Viewing the simulated waveform Synthesis of the Design 23 The next step after simulation is to synthesize the design Synthesis is the process which will Generate the gate level netlist of the design In order to run the synthesis process the selection has to be changed as Synthesis Implementation in the sources for window This netlist output will be the input file for the implementation process Jc aen f 2 Figure 4 22 Selecting synthesis option The progress of the Synthesis process will be shown in the console of the ISE Left down corner In case of any errors the detalls of the errors wil be displayed With any type of error the design will not proceed to the Implementation stage The synthesis generates the synthesis report RTL schematic Technology Schematics The user should verify these reports In order to understand the actual logical circuitry that will be configured in the FPGA 53 Copyright 2007 The Learning Labs
7. ammo STG Teti BOSIO Redes c m Ta o faim m CES T m pom 7 Assy teh cor arts Ons Bose E ce Imm rte Manet E E a voci rerit smt cio s re Kemi woes Drain Owen a zbe C E EET NN E P wax 8 o Ce 77 poer sed Figure 2 5 Platform power up 10 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 Setup for Xilinx Platform Cable amp TLL5000 Base Module Note Before connecting the Xilinx Platform Programming Cable from the PC to the target TLLSOOO it is required to complete all the steps of TLLSOO0 Power ON and Configuration using the TLLS000 Hardware Manager as explained in the above section When the Xilinx Platform Programming Cable is plugged into the system the hardware is identified This can be verified by right clicking on My Computer gt Properties gt Hardware gt Device Manager gt Programming cables tao AER pae EQ msde Iu tiet etre Figure 2 6 Checking status of the platform USB cable Now observe the color of the status LED on the Platform cable USB box It will be orange The status will remain orange til the other end af Platform cable USB a 14 pin Flat ri
8. Figure 3 35 Assigning pin numbers 40 To give the pin constraints select the ucf file and expand the User Constraints in the Process for window and run the process Assign Package Pins This will invoke another XILINX built in tool called PACE Pinout Area Constraint Editor 41 Enter the pin numbers where the inputs and the outputs are supposed to be connected The details of these pin numbers may be found in the user manual 42 After entering the pin numbers the save the file and PACE tool may be exited 43 Then again select the design file in the Sources for window n Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 44 The next step is to run the implementation process So right cick on the Implement Design Yocess and select Run from the pop up menu eet view Prone Procent Ade Tok Mra T sel Renar xao oeer s 09 m TH as RES Se pase Emm Figure 3 36 Implementing design 45 During the project design of a digital system each process can be found in some af the following states Running the process is in the running phase Up to date Process is successfully executed without mistakes or warnings If the rapport is in this condition it means that i s up to date although it could happen that the tasks covered with t
9. Inc Electronic System Design Base Module Getting Started Manual v3 2 Implementation of the Design 24 The Implementation process has three different sub processes in it They are Translate Map and the third is Place amp Route Translate This is the process that merges all the input files and the constraint file into a single netlist Map The process of mapping the logical components to the physical components is known as Map Logical components are nothing but the components that we have as per the design circuit diagram Physical components are the components that are there inside FPGA such as LUTS gates flip flops Place And Route This is the process of configuring the appropriate CLBs amp 1085 inside the FPGA and interconnecting them Also known as PAR 25 To do the implementation process the constraints fle has to be given as another input file To create a new user constraint fle uc click on project from the ISE software and select new source Once that is completed the window shown below appears Select implementation constraint file and give the desired file in the file name field Then click on Next Next and Finish xm i tee oars tom Be E User Document Pater 6 Evora tote c arm ciae Frnt ass ai tee Cot Pease ve reete 1m res ma j E Figure 4 23 Applying input constraints Copyright 20
10. please update with the service packs for getting the drivers for the Xilinx Programming Cable This tool is provided with ISE simulator XST synthesizer PAR and downloads IMPACT applications ModelSim XE the Simulation software for behavioral simulation One should also be able to do these exercises using the full ModeiSim software from Mentor Graphics but there wil be differences in methods and commands that this manual does not address Hardware requirements The following items are required to start using the system TLL5000 Base Module Power supply for TLLSOOO 18volts 3 5 Amps USB cables 2 Nos Xilinx Platform Programming Cable newer versions use an USB interface but parallel cables will also work CDs with User Documentations and Software 4 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 The CDs provided with the TLL5000 will typically contain the following items Please consult with your local TLL product partner for specific details as your configuration may be different from this table 5 Directory Description Remarks Various application utilities and Please check with your oca TLL partner to verify that the associated software and hardware PO manuals and software are the most current versions TLL User Software and Manuals ea convenience for the user this Thes
11. 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 25 By selecting the input flle name in the Sources for window expand the Modelsim Simulator Window from the Process for window and run the process called Simulate Behavioral Model This will invoke the simulator that we use to simulate the design Here ModelSim XE 6 2c is the simulator used ene aoe eae then res Tame eel eT Figure 3 26 Forcing the input signals 26 Force the selected input signals with the desired values and click on G Dive Deposit Figure 3 27 Docking the window 26 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 27 Then click on Run button in order to view the simulated results umo Mi Rulis Figure 3 28 Run simulation 28 The simulated results can be seen in the wave form window The vertical yellow bar is the cursor Wherever the cursor is placed the corresponding values will be displayed in the wave window as marked in the below shown figure Different inputs can be applied and the output can be viewed accordingly Once the satisfied output is got the simulator may be quitted Fig
12. Development Board option in Step 6 The following screen appears on PC rus Fi pem Kee X fee so vertes vieles Soe ATS amne 9 ce e T e E E ce i hee nese omms m je c ce ET TEES Figure 2 4 Checking platform status At this stage the screen displays the status as Board Powered Down see the Status information marked in blue in the above screen This means the platform is not powered up Once the Power ON button is clicked then the platform will get powered up The power supplies for the various TLLSODO elements FPGA memories peripherals etc are started by clicking on POWER marked in the red color in the above screen Now the Power supply is enabled for all the parts of the board and the screen is shown as below Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 3 The above screen provides monitoring of the TLLSOO onboard power supplies and Configuration of the various user settable parameters such as the system clocks shown in the lower tables For example the expected voltages and the actual voltages wil be displayed in the Power Values Monitor section in the upper left of the display screen pues amem NM cs EXE men dons azy vod mT
13. as given previously To make the communication expand the Generate Programming File process and select the Configure Device IMPACT process He Eat Vow Project Sourc Pres Add Taole Winds jaAga la amp max aea 1 at ci 9 D x cose s Gennana Flo en bai hi fide shel ech oe Esser ec Ham HD stes 251 omen Desen PugennigFio FEED Pee mesi ilo Rept Gonera PROM ACE TAB Fe Ei Frocees conrigure it Without E properties Figure 3 38 Configuring the target device 48 Before running the process Generate Programming File right click on Generate Programming File and select Properties In the properties window select the start up Options and set the value as TAG Clock in order to avoid the warning messages in the future 34 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 49 This opens another software tool called iMPACT Click on Finish button In this window Figure 3 39 Checking for boundary scan devices 50 This process detects three different devices that are present on TLLS000 target The xcf32p is the flash device 7 95727 is the CPLD device and xc3s1500 is the FPGA device as Copyright 2007 The Le
14. ch EE Was J Retz I Figure 3 7 Completing the new source wizard B In the next window dick Yes to create the new project directory ee ati A EST One itta pim Figure 3 8 Confirming the project creation i Copyright 2007 The Learning Labs Inc TLLS000 Electronic System Design Base Module Getting Started Manual v3 2 9 Then click on Next in the New Project Wizard one Figure 3 9 Creating a project 10 Again click on Next button on the Add Existing Sources window since at this point of time there are no existing source designs pm ETIN gl fng peres non scis ob or rrt de gpl Sct et aio Ses con sa emer n Figure 3 10 Adding an existing flle 18 Copyright 2007 The Learning Labs Inc 5000 Electronic System Design Base Module Getting Started Manual v3 2 11 Click Finish on the Project Summary window to create the project or click Back to go back and make some changes if any Figure 3 12 Viewing the project summary 12 Once the finish button is clicked the project Is created and the design summary is also given in the ISE tool window as shown below And click on the file name tab to edit the file as shown in the red circle on the
15. entity of the design After giving the port names the directions of the ports can also be entered as per the design requirement If the port is a type of bus that can also be entered along with the number of bits specifying the width of the bus per Figure 4 8 Enter the port lit Note The Port names to be entered in the above window shall also be 1 bit for typical logical gate implementations In the above design we have taken an input port of B bits D to 7 amp output port of B bits 0 to 7 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 9 After giving those details click on Next amp Finish LT FEF Pa ete a ain se i ee 1 NE t een men ene M Eee pen xem a Figure 4 9 File summary 10 After clicking on Next the tool will ask for the confirmation of creating a new folder Simply Yes can be clicked This will create a folder named as the project name in the specified location And based on the information that is given a skeleton of the VHDL file is created which will have all the declaration parts of the file This is common for all the VHDL files SRT ar Er mn n ee ES annee dama Tien Fuse tren TE seguita p E w orem 3 Figure 4 10 Creating proj
16. figure Figure 3 13 Viewing project summary in HTML format 19 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 13 Click on the Float Window button to get a better view of the schematic editor This is the Same as an undocking feature Figure 3 14 Undacking the window 14 Once the schematic editor is undocked i e the window is floated the following window can be observed Te ttr Wir Figure 3 15 Selecting the components In this window click on Symbols tab in order to get the various components under different component categories in the left side of the window 20 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 15 From the Categories tab in left side of the window select buffer and select the desired symbol from the Symbols tab and place in the editor window as shown in the figure The editor be zoomed in out as per the requirement Notice the grid positions as guides to drawing a neat layout o gt 4G ew eS i F sies sse ren uan aman var UNUS Selec the ino segment NN Honi nlar Cane Keepihe connections to Ee ar p H s Ss poe ble TOUR I Fig
17. shown icon on your desktop Figure 4 1 Invoking XILINX tool 2 Once the tool is invoked the below shown window will open Figure 4 2 Tool welcame screen 40 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 To start a new project click on File tab and select New Project The same is shown in the below figure 4 3 Figure 4 3 Creating new project 4 When New Project is selected new window is opened as shown in the figure In the Project field enter the desired project name Now it can be observed that a folder is created with the same name in the Project Location field This is for keeping track of all the input amp output files in the same location Figure 4 Entering project name Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 5 Let the Top Level Source be as HDL itself After giving the necessary inputs and clicking on Next the next window appears This is the place where the target hardware amp necessary tools are selected Key in the inputs as per the requirements Then click on Next EET Sakr tn Denis ar Deng an CEL Pona casse Fest pre Sho Toal Estee ler
18. 07 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 26 The above process will create an uef file and automatically add it to the project By selecting the file in sources for window Run Assign Package Pins process from Processes for window The detalis of the pin locations are for switches and LEDs available on TLLSOOO board Cie Edk View Project Source Process Window eb JOS ee ole t Cs x v e 2 159 CUN t RE _ Ded TI Qbura Sut ele LE Nee Sp fend buster E Denie Mew Sauce E x I aper Ea Ceva led Tm BE rerit bue EE 190 pen Without Un dating E AEN Figure Assigning package pins 55 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 27 Once Assign Package Pins process is run another bullt in tool fram ISE will be opened called Pin out Area Constraint Editor PACE Enter the pin numbers in the LOC field as shown in the figure The pin number detalls in the figure below bottom left window labeled Design Object List 170 Pins are as needed for the 5000 LEDs and Switches eT jpeg Rs ieee Ba ome XARXANOOMOOBI D
19. 07 The Learning Labs Inc 5000 Electronic System Design Base Module Getting Started Manual v3 2 Chapter 1 Prerequisites System Requirements The following are the prerequisites for a computer to run the required software tools for doing basic digital designs on theTLL5000 Make sure that these components and minimum hardware are present Personal Computer Pentium 1 GHz or higher Although lower processors will run the software tools the desired results are not guaranteed 512M8 RAM for average applications larger designs a 1GB RAM or greater is useful Minimum 5 68 on Hard Disk The Webpack ISE requires around 3 5 GB for all its components SVGA Monitor with the resolution of 1024x768 Monitor resolutions has been kept at 1024x768 which is ideal Windows 2000 or X operating system with ServicePack 4 for Windows 2000 amp ServicePack 2 for winx Three USB2 0 ports One RS232 serial port Ethernet Network Interface Card NIC The network interface card should have been configured your system Make sure that you have configured the network card with a static IP address Software requirements The following software needs to be installed in the PC used for connecting to the TLLSODO Base Module Xilinx Webpack ISE 9 x our limited experience is that the Xilinx ISE version 8 x should also work but we recommend that you use version 9 x If you are using the previous versions of ISE
20. TLLSOOO is tested for correct functionality with the use of Switches and LEDs available on the target TLL5000 joule uns TET Figure 4 35 Observing outputs As the switches are toggled to ON OFF positions if the design is functioning correctly then the corresponding output LEDs will turn ON OFF to match the switch positions Copyright 2007 The Learning Labs Inc
21. al v3 2 Power ON and TLL5000 Configuration using Hardware Manager Connect the power supply to the power supply connector CON100 Connect the USB cablel between PC USB port amp 1 This connection is used for Communication and configuration of the TLLSOO0 from the PC using the TLL software provided with your system Switch ON the power supply on the TLLS000 with POWER ON OFF Switch the power is switched ON the LEDs near the power connector will turn ON Now use the TLLSODO Hardware Manager utilty typically included as a menu selection in the TLL Design Center software please consult your local TLL partner for specific directions to configure This wili bring up the following screen on the monitor Figure 2 2 Hardware Manager 7 Copyright 2007 The Learning Labs Inc 5000 Electronic System Design Base Module Getting Started Manual v3 2 1 Click on the Choose device option in the step S screen options will be displayed as shown below Bas Figure 2 3 Selection of target platform In the options above we shall see 5000 Development Board This option will be enabled only by connecting USB cable between TLLSQOO base module and PC Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 2 Now click on the TLLSO00
22. arning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 Figure 3 40 Selecting the target device 51 The Assign New Configuration File is place where the programming file will be browsed to the location and selected by clicking on the Open button But here DO NOT Select or configure the flash device and the CPLD So click on the Bypass button to bypass these components And finally when the FPGA is highlighted select the generated bit fle and click Open E aee E D ES Em Tere rei pz Fe yee Tiber Fee PERT ue n Ej em p traberiogerams ER Fish Atache ttir FPGA d Figure 3 41 Selecting the bit file 52 After completing this process the bit fle will be selected for the FPGA to be programmed m xe9572d EE bypass bypass buffer schbt Figure 3 42 Selecting the bit file Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 53 Now right click on the FPGA and select Program from the pop up menu 8 waits E ET _ e D mel e cet ave Snare Userade rain Configuration Figure 3 43 Programming the device 54 In the Programming Properties window just click on O
23. ate cable connections 2 pE uestre E E tigres E Brett E zc h ro Sera Senes Figure 4 27 Configuring the target platform window just click on Finish ma Figure 4 28 Welcome screen of iMPACT 30 Once the Configure Device IMPACT process is run the below shown below appears In this Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 7B Once the Finish is licked the IMPACT tool will detect the boundary scan devices on the target 5000 Here xcf32p is a flash prom amp xc9572 is a CPLD These devices will NOTI be programmed Click Bypass on the following window IE iron tts p M Figure 4 29 Detecting boundary scan devices E Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 32 This window is to select the programming file for the CPLD Since we are not going to program that this can also be bypassed Hn rto Figure 4 30 Selecting programming file 60 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Star
24. bbon connector is connected to the TLLS000 suns un 14 pin FRC connector goes to TLL 5000 board This end goes to coni PCUSB port Figure 2 7 Checking status checking n Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 Now connect the Xilinx Platform Programming Cable to the JTAG 14 pin FRC connector labeled CON on the lower right of the TLLS000 this is non reversible connector with a notch on the connector long side Please refer to the following diagram for connections CONI Figure 2 TLLS000 platform JTAG connector When the Xilinx Platform Programming Cable is connected to the TLLS000 the status LED of the Platform Programming Cable will turn GREEN indicating that the JTAG communication is successful with target board Note If the 5000 Power ON and Configuration using the TLLSOO0 Hardware Manager not followed then the reference voltage for JTAG will not be available on CONI of TLLS000 and the status LED will remain ORANGE Until the status LED turns GREEN the bit file cannot be downloaded onto the target Platform 12 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 TLL5000 Interfaces and Peripherals
25. e tools will have a licenze Web downloadable CD has the freely downloadable duration determined Xilinx 2 Web downloadable FPGA software from the Xilinx and they wil provide updates Website The registration is through their standard update online by the user mechanisms Notet The installation of Xilinx tools are self guided Click on the Setup exe in the directory and the installation starts Note2 Choose the option of cable drivers during the installation of Webpack ISE If these drivers are not chosen then the drivers for Platform cable USB will nat be installed in the System 5 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 Chapter 2 Setting up TLL5000 Base Module The following picture shows the connections to be made between the PC and TLLSOOO Base Module Please strictly fellow the steps as per the manual to avoid any problems to the hardware The wrong sequence of applying power and connection sequence can cause damage to the system Power Supply av 358 Power ON commctor ier erus Connecton cons vshCabiel port conn Fom PC io 15000 Tapin CONI Figure 2 1 TLLS000 platform setup 6 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manu
26. ect directory as Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 11 Click on Next in this window Em usi Edere co em cc eh eign ae ah rae he ow ee enacts e py e md cante silente vip Meet ee en d Figure 4 11 Creating new source 12 Since new project is being created it is not required to add any existing source at this point f time So click on Next ETT E bash eres lent a sm Don Figure 4 12 Adding existing file any Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 13 The summary is created based on the information that is given so far Now click on Finish Viewing project summary 14 Figure 4 14 shows the VHDL file for the given design Normally whenever the file is generated it wil contain the library declaration port declaration amp architecture declaration Only the functionality of the design has to be entered by the designer This simplifies the job of the designer and time is also saved Figure 4 14 Tool generated VHDL file ar Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getti
27. for any purpose except for education and training Technical Support Please contact your local TLL authorized product representative for questions regarding hardware software or applications issues Any updates or patches will be sent to you as long as your registration is current The TLL products are designed to be supported remotely by allowing viewing of the user desktop It is highly recommended that the PC from which you are using TLL products is connected to an Internet link that allows Web browser access In this way our technical support staff can view your desktop and work with you to understand and solve technical issues 2 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 Table of Contents CHAPTER 1 PREREQUISITES SYSTEM REQUIREMENTS SOFTWARE REQUIREMENTS HARDWARE REQUIREMENTS CHAPTER 2 SETTING Ue TLL5000 BASE MODULE PoWER ON AND TLL5000 CONFIGURATION USING HARDWARE MANAGER EXE 7 SETUP FOR XILINX PLATFORM CABLE amp 5000 BASE MODULE TLL5000 INTERFACES AND PERIPHERALS CHAPTER 3 DESIGN USING XILINX ISE FUNCTIONAL TEST ON THE TLLSOQO CHAPTER 4 4 Dicitat DesicN Using VHDL BEHAVIORAL SIMULATION OF THE DESIGN SYNTHESIS OF THE DESIGN IMPLEMENTATION OF THE DESIGN PROGRAMMING TLLSOOO FUNCTIONAL TEST ON THE TLLS000 3 Copyright 20
28. his process have mistakes and warnings By Warnings reported the process is successfully executed but there are warnings Errors reported the process is finished with at least one error G out of Date signifies that there have been made some changes and that the process needs to be dane again No icon In the case of there Is no any of these icons the process hasn t been started 32 Copyright 2007 The Learning Labs Inc 5000 Electronic System Design Base Module Getting Started Manual v3 2 46 After the design implementation process is complete the programming file needs to be created to download into the FPGA to correctly configure it To generate the programming file run the rocess called Generate Programming File from the Process for window Ear gon ET E DUI l gesimo T Eine eh peche Hp stes os Ten rr Er Figure 3 37 Generating bit file This process will generate the programming file i e the file that will be downloaded anto the FPGA the bit stream file will be generated This is Once the file is generated the next step is to make the communication between the host system the target TLL5000 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 AT Before starting this process Power ON the board
29. it the object properties of the IO markers in the name field delete the existing name and ve the desired name and click OK Essere pores es Figure 3 21 Renaming the markers Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 21 Repeat the same for all the ports Save the schematic Next perform a Check Schematic function has to be done This same as check syntax process in the text based design entries 24522 Check Schematic Figure 3 22 Checking the schematic 22 Observe the No error or warning is detected message in the console window as shown below E Start DRE No error or warming is detected WE Figure 3 23 Observing console window 23 Then dock the floating window by clicking on the Dock Window button Deck thie sides Figure 3 24 Docking the window 28 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 24 Then click on the Sources amp Process tabs in the ISE tool window Select the option as Behavioral Simulation in the Sources for window Mos NEC IDI NE gt m IE nD SS Figure 3 25 Selecting the simulation option 25 Copyright
30. k Essere P ELS as Figure Programming the device 37 Copyright 2007 The Learning Labs Inc TLLS000 Electronic System Design Base Module Getting Started Manual v3 2 55 The program status can be observed by the viewing the Progress Dialog box E bypace ialog 2451 Execuing cenmand Figure 3 45 Downloading the file 56 Once the device is program is downloaded the Program Su B 8 8 message appears Ed n Program Succeeded Figure 3 46 Viewing status message Copyrig he 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 Functional Test on the TLL5000 The design downloaded onto the 5000 is tested for correct functionality with the use of switches LEDs avallable on the target TLL5000 Figure 3 47 Observing the outputs As the switches are toggled to ON OFF positions if the design is functioning correctly then the corresponding output LEDs will turn ON OFF to match the switch positions 39 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 Chapter 4 Digital Design Using VHDL 1 To invoke the ISE 9 1 tool double click on the below
31. ng Started Manual v3 2 In the above window the IEEE libraries are included by default the design b lt a is entered by the user This code will act as a buffer where the value of a is loaded to b all the 8 bit 15 As per the design flow after design entry the 1 step is to simulate So to simulate the simulation option has to be selected The steps for selecting I s shown in figure 4 15 Behavioral Simulation of the Design 116 When the design is ready choose the Behavioral Simulation option This option is available on top left hand corner of your ISE near Sources for Deo Soe cs Figure 4 15 Selecting simulate operation Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 17 Then select the VHDL flle in the source for window and run the Simulate Behavioral Model Function To run any process select the appropriate process and press enter or double click the process or right click on the process and select run option fram the pop up menu JOE S I nj lagal gma Ie e TT LEITET pee IE n E 25 Figure 4 16 Simulating the design 49 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 18 The sim
32. roject option is selected the following window is seen In this window type a project name buffer sch and specify a location Select Schematic as the Top Level Source Type And click Next ED E Figure 3 Entering the project name m Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 5 After these inputs the tool will ga to the next window Here select the target device and the tools that will be used in developing the design Then click Next re rer Fost oer spen B Ten ST rate ance Des Enable esnpe es maemo E teca Figure 3 5 Selecting of a device 6 In the next window click on New Source tab In the New Source Wizard window give the fle name and select the input file type as schematic Fomei en treet a ei ren ET Figure 3 6 Selecting a source type 16 Copyright 2007 The Learning Labs Inc TLLS000 Electronic System Design Base Module Getting Started Manual v3 2 7 When the Next button is clicked the New Source Wizard summary window will be seen Click on Finish here rie Navi il ese renr steleton oco withthe flowin spec Vos Sce Fenton desire bo coh Saute Te Scheme Seis Nene bere
33. ted Manual v3 2 The third window is for the FPGA Please ensure that the FPGA is selected by being highlighted Then select the appropriate bit file and click on Open Figure 4 31 Selecting bit file e Copyright 2007 The Learning Labs Inc TLLS000 Electronic System Design Base Module Getting Started Manual v3 2 34 Now it can be observed that the FPGA is selected with the given bit file asus oix 012 SAIS S jiga Waka we Oe t me ines eripe Bret pum Figure 4 32 Programming selection 7 Right click on the FPGA that is xc3s1500 and select program from the pop up menu Then the below shown window appears Click on OK in this window This will download the bit file onto the target device re e pa Panonian prc ee Figure 4 33 Viewing programming properties 62 Copyright 2007 The Learning Labs Inc TLLS000 Electronic System Design Base Module Getting Started Manual v3 2 35 programming is successfully completed the Program Succeeded message appears as Shown in the given figure GXk amp x OO 252 Figure 4 34 Programming status Functional Test on the TLL5000 36 The design downloaded onto the
34. there that according to the circuit diagram And the physical components are the ones that are physically present inside the FPGA Place And Route PAR The map output file will be taken as the input file for the PAR process The map file will contain how many CLBs amp IOBs are required to implement the design And also it will have the details of which are the CLBs amp IOBs that are used In the design implementation Based on that information those particular CLBs and IOBs will be configured This process is called as placing and the routing is the process which makes the interconnection CLBs and or 1085 Before going to the process of implementation it is necessary to write the user constraints uch fle This is the file where the designer can give the constraints for the design to be implemented 28 Copyright 2007 The Learning Labs Inc TLLS000 Electronic System Design Base Module Getting Started Manual v3 2 34 To enter an ucf click on Project menu and select New Source option T a Cleans Fraject PTC Pathe ies archie Apply Project control MESES BM Figure 3 31 Creating a new source for constraints file 35 0nce the new source is selected the New Source Wizard window gets opened Here enter the file name and select the input fle type as Implementation Constraints File and click on Next ERES There
35. ulator used here is ModelSim XE from Xilinx Once the process is started the simulator tool is invoked The simulator main window and the wave window are opened As shown in the below figure ONES aet Bt earner AD rri E nmi te sas m FEN THEOREMS IPPON LER Ua ean ue e eR ee DIETS 21 Figure 4 17 Compiling and simulating 50 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 19 Now maximize the wave window and right click on the input signal and select Force from the op up menu zm mcm Figure 4 18 Selecting Force option 51 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 20 When in the Force Selected Signal enter the desired value for the input signal s and click ET res Figure 4 19 Forcing the input signals 21 After forcing the input signal click on the run button The shortcut to the run button is encircled in red color in the below shown figure wave aetan File Edt View Insert format Tools Window cea sees r TLUUCUUT Figure 4 20 Run simulation
36. ure 3 16 Placing the components 16 After placing the components the wire has to be connected To connect the wires right click in the editor select Add select Wire Figure 3 17 Adding wires to the components n Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 17 Now as shown in the below given figure add the wires to the components in the editor window zw Lm NIRE Figure 3 18 Placing wires 18 After adding wires to the components the 10 markers are to be added to the wires which should be used for applying the inputs and monitoring the outputs To add 10 markers again right click in the schematic editor select Ada and select 1 0 Marker Pint Curent shost Previous view iem gt net name E Figure 3 19 Adding 1 0 marker 2 Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 19 Place the 10 markers as shown in the figure While placing the input marker select Add an input maker and for the output marker Add an output marker in the options window on the left hand side of the window d xu sn EN TRI RD DUOC Ea ER Se ir B XD L6 ess e Figure 3 20 Renaming 1 0 markers 20 To ed
37. ure 3 29 Viewing the simulated output 29 The next step in the FPGA design flow is to synthesize the design Synthesis is the process that generates the equivalent gate level netlist for the input design file The netist is a text based file that contains the details of the devices and the interconnection network that are used in the design 30 1n order to run the synthesize process select Synthesis Implementation option in the Source for tab and right click on the Synthesize XST process Process for window and select Run from the pop up menu Once the synthesis is completed expand the synthesis process to view the synthesis report RTL Schematic amp Technology view of the given design E Copyright 2007 The Learning Labs Inc Electronic System Design Base Module Getting Started Manual v3 2 31 The above processes are shown below ears cee ee y Hz zm i rtr Errare aos rmn Sx tnn an EX en Pan me Figure 3 30 Synthesizing the design 32 The next process is the Implementation process This process has three major steps under it They are a Translate b Map and c Place And Route Translat Translate is the process that merges all the Input files and the constraint file into a single netlist is the process that maps the logical components to the physical components Logical components are the ones which are
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