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USER`S MANUAL

1. 40 FPGA 5 41 PCle BUS 42 CERTIFICATE OF VOLATILITY 44 DRAWINGS Trademarks are the property XMC SLX BLOCK 45 R172 Resistor Location 46 OMINA reS PERENG Owners XMC SLX External Power Location 46 The following manuals and part specifications provide the necessary information for in depth understanding of the AX board RELATED PUBLICATIONS Spartan 6 Data Book http www xilinx com IDT70T3519S Spec http www idt com IDT70T3509MS Spec http www idt com MT47H32M16CC Spec http www micron com CY23EP05 Specification http WWww cypress com Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com A XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 1 0 GENERAL INFORMATION Table 1 1 The XMC SLX boards are available in both standard and extended temperature ranges with an option of memory KEY FEATURES The re configurable XMC SLX modules use the Xilinx Spartan 6 XC6SLX150 FPGA Re configuration of the FPGA 1 possible a direct download into the Xilinx FPGA over the PCle bus In addition on board flash memory can be loaded with FPGA configuration data for automatic Xilinx configuration on p
2. THE LEADER IN INDUSTRIAL Series XMC SLX150 Spartan 6 Based FPGA XMC Module USER S MANUAL LWEEOTS 011063 ACO9nWWA 1 4 1 v 99 1 0v00 160019359933 10 amp 1 82 GALHA ccnt 0110 N AV N A JWEEOTQ 01106 a ejpown y 9 BP INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions oacromag com Copyright 2011 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 893 A11B000 2 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module TABLE OF IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring CONTENTS component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility 1 0 General Information The information of this manual KEY FEATURES uiris t db 4 may change without notice PCle INTERFACE FEATURES 5 Acromag makes no warranty ENGINEERING DESIGN KIT 6 of any kind with reg
3. These bits will read 010 when the AXM A30 high speed analog input mezzanine module is present Bits 27 and 28 are DMA acknowledgement bits and will read a logic high while the corresponding DMA channel transfer is active Bit 29 indicates the completion of initialization and calibration of the DDR2 controller Bit 31 of this register when set to a logic 1 will issue a reset signal to the FPGA hardware Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Table 3 14 Software Reset and Status Register FUNCTION 4 Mezzanine interrupt status is identified data bits O to 1 All bits labeled Not Used 7 Read of a 1 indicates that an interrupt is pending will return logic 0 when for the corresponding data bit A pending interrupt will read remain active until disabled via the mezzanine interrupt control registers Logic 0 Interrupt Not Pending Logic 1 Interrupt Pending USERo Control USERoControl amp Board clock PLL CLK Default Logic 1 Board clock 125MHz Mezzanine Identification Code 15 13 001 for all Acromag digital I O mezzanine boards 010 for the AXM A30 mezzanine board DACKO Status 27 Logic high is a valid acknowledgement for channel 0 DACK1 Status 28 Logic high is a valid acknowledgement for DMA channel 1 The most significant bit of this register when set to a logic 1 will issue a software
4. configuration software scans the PCle bus to determine what PCle devices are present The software also determines the configuration requirements of the PCle card The system software accesses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base address Since this board is relocatable and not fixed in address space its device driver must use the mapping information stored in the board s Configuration Space registers to determine where the board is mapped in memory space The memory maps in this chapter reflect byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte Little Endian means that the least significant byte is stored at the lowest memory address and the most significant byte is stored at the highest memory address The Intel x86 family of microprocessors uses Little Endian byte ordering Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Big endian means that the most significant byte is stored at the lowest memory address and the least significant byte is stored at the highest memory address Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual
5. acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module O Powering the XMC SLX150 as an independent board is possible using the J7 and J8 board through holes As an independent standalone board the XMC SLX150 board would not be plugged into a PCle slot To independently power the board the required 12 VPWR5 12 volt and 3 3 volt power supplies must be provided via the J7 and J8 contact holes The holes have 29 mil openings with 60 mil pads The location of the contact holes on the board are shown in diagram at the end of this manual By default the flash memory U6 is read write enabled Removal of resistor R172 disables writing the flash configuration device Refer to Resistor Location Drawing at the end of this manual to identify the board location of R172 This Section provides the specific information necessary to program and operate the board GETTING STARTED 1 The XMC SLX board is shipped with the user programmable Xilinx FPGA code stored in flash memory Upon power up the XMC SLX will automatically configure the FPGA with the example design code stored in flash As a first step become familiar with the XMC SLX as supplied by Acromag The board will perform all the functions of the example design as described in this manual The Example Design Memory Map section gives a description of the I O operations performed by the example design It will allow testing of digital I O interrupts read write of dual port SRAM
6. or hardware Hardware signal DREQO driven active by the programmable FPGA will start a DMA channel transfer Hardware signal DREQ1 driven active will start a DMA channel 1 transfer To identify the pins corresponding to these signals see the user constraints UCF file provided in the engineering design kit The DACKO and DACK1 signals will go active upon the start of a DMA transfer and remain active until its completion The example device driver software purchased separately can be used to exercise DMA block software and demand hardware modes of operation SYNCHRONOUS Dual Port A 256K x 64 bit synchronous Dual Port SRAM is provided on the base SRAM model XMC SLX150 The XMC SLX150 1M model increase the DPSRAM size to 1M x 64 bit One port of the SRAM interfaces to the PCle bus interface chip the Xilinx Virtex 5 LX30T device U5 The other port connects directly to the programmable FPGA 17 This configuration allows for a continuous data flow from the field inputs through the FPGA to the SRAM and then to the PCle bus Both ports of the SRAM operate in Pipeline mode This allows for faster operational speed but does cause a one cycle delay during read operations The pins corresponding to the control signals address and data buses are in the user constraint UCF file provided in the engineering design kit The SRAM port connected directly to the user programmable FPGA U7 supports continuous writes or single cycle reads The
7. software product sold separately consisting of board VxWorks software This software Model PMCSW API VXW is composed of VxWorksQ real time operating system libraries for all Acromag PMC and 1 0 board products PCI and PCle Cards and CompactPCI Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag provides a software product sold separately consisting of board software This software Model PMCSW API QNX is composed of QNX real time operating system libraries for all Acromag and XMC I O board products PCI and PCle I O cards and CompactPCI I O cards The software supports X86 PCI bus only and is implemented as library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag provides a software product consisting of board Linux amp software This software Model PMCSW API LNX is composed of Linux libraries for all Acromag and XMC board products PCI and PCle I O cards and CompactPCI I O cards The software supports X86 PCI bus only and is implemented as library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s M
8. 2 L D A with 8mm stack height Power XMC Modules Requirements VG Mise 820mA 984mA Typical 700 1 VPRW may alternative be 5V 5 A 5V supply will consume approximately the same wattage as a 12V source On Board 1 2V Power to Current Rating Spartan 6 FPGA Maximum available for the T S FPGA 1 TEN 2596 4A Maximum Operating Temperature 0 to 70 C 40 C to 85 C E Version Conduction Cooled XMC mezzanine card Complies with ANSI VITA 20 2001 R2005 The XMC SLX without a faceplate is fully compatible with a conduction cooled host card Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 125 C Non Isolated Logic and field commons have a direct electrical connection Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module A 1 Designed to comply with EMC Directive 2004 108 EC Class B ENVIRONMENTAL Radiated Field Immunity Complies with IEC 61000 4 3 with no register upsets Conducted F Immunity Complies with IEC 61000 4 6 with no register upsets Surge Immunity Not required for signal I O per IEC 61000 4 5 Electric Fast Transient EFT Immunity Complies with IEC 61000 4 4 Level 2 0 5KV at field I O terminals Electrostatic Discharge ESD Immunity Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge Level 2 4KV enclo
9. 2 MEMORY 19 Flash Configuration 21 Direct PCle bus to Xilinx Configuration 22 CONFIGURATION CONTROL REGISTERS 22 FLASH CONTROL REGISTERS 23 SYSTEM MONITOR REGISTERS U5 PCle bus 26 Software Reset and Status Register 27 Rear Connector Read Register 29 Rear Connector Write Register 29 DMA Control Register 30 DUAL PORT SRAM REGISTERS 30 XMC Board Identification Code Register 33 SYSTEM MONITOR REGISTERS U7 FPGA 34 BAR4 MEMORY 35 Dual Port 35 Static RAM 35 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 3 4 0 THEORY OF OPERATION PCle INTERFACE 36 SYNCHRONOUS DUAL PORT SRAM 36 LOCAL BUS 5 5 37 CLOCK CONTROL a 37 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE 39 PRELIMINARY SERVICE PROCEDURE 39 WHERE TO GET coit rax EE E ra Eva 39 6 0 SPECIFICATIONS 40
10. 7 13 ROISP 26 8 28 14 ROI4P 29 31 15 39 5 32 16 33 2 35 17 34 RION 86 18 ROt8P 37 RIOI8N X 39 Dg 38 40 EA 43 EH 42 44 45 E _ Ea 46 48 24 49 E 25 50 52 26 5377 585 54 56 28 57 59 29 58 60 pairs are routed to pins 1 3 2 4 etc 30 6 683 31 16 This connector is a 64 pin female receptacle header AMP 120527 1 or equivalent which mates to the male connector on the carrier CPU board AMP 120521 1 or equivalent 2 2 2 2 2 3 9 3 3 D 3 4 4 4 4 5 5 5 5 10 13 14 16 17 19 18 0 E 21 3 22 4 25 7 26 8 29 1 30 2 33 5 34 6 3 9 38 0 a 3 42 4 45 7 46 8 49 1 50 2 53 5 54 6 57 9 58 i3 61 63 62 64 4 5 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Non Isolation The board is non isolated since there is electrical continuity between the Considerations logic and field I O grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www
11. 8 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 1 O The memory space address map used to program the FPGA and flash BAR2 MEMORY device is shown in Table 3 8 Note that the base address for the board BAR2 in memory space must be added to the addresses shown to properly access these registers Register accesses as 32 16 and 8 bit transfers in memory space are permitted All addresses in BAR2 from 0 to 7FFF hex are fixed and cannot be changed by the user the programmable Spartan 6 FPGA A D31 008 D07 BAR2 Table 3 8 oa COT m AGO BAR2 Memory Map _ siiis 1 The board will return 0 for bara 003B PCle bus FPGA oystem Monitor Status Control Register 0038 PCle bus FPGA System Monitor Address Register 003C Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module EXAMPLE DESIGN MEMORY MAP Table 3 8 Example Design BAR2 Memory Map 1 The board will return O for all addresses that are Not Used BAR2 BAR2 8003 Software Reset and Status Register 8000 8007 8004 Mezzanine Module 4 Memory Space Rear I O Connector Read Register 802C ow Rear I O Connector Write Register 8030 8037 DMA Control Register 8034 803B FPGA Port SRAM Register Data Lines 31 to 0 8038 FPGA Port SRAM Register Bo Data Lines 63 to 32
12. 803C 8043 FPGA Port SRAM Control Register 8040 8047 FPGA Port SRAM Address Register 8044 804B DMA Channel 0 Threshold Register DP SRAM 8048 804F DMA Channel 1 Threshold Register DP SRAM 804C Address Reset Register 0 DP SRAM 8050 8057 Address Reset Register 1 DP SRAM 8054 805B XMC Board Identification Code A3 for Acromag Example Design 8058 B05 1 05 808F Not Used 808C 1 Air Temperature 8093 Not Used Register 8090 8093 Additional Mezzanine Module Space 8100 gt 8137 80 E 3FFFFF Otherwise Not Used 3FFFFC This memory map reflects byte accesses using the Little Endian byte ordering format Little Endian uses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering In Big Endian the lower order byte is stored at odd byte addresses Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 2 1 The SLX150 board uses a flash configuration device to store Flash Configuration programming information for the Xilinx FPGA The flash configuration device and FPGA are hardwired together so that during power up the contents of the configuration device are downloaded to the FPGA The flash configuration data can be reprogrammed using the PCle bus interface The following is the general procedure for reprogramming the flash memory and reconfigu
13. 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 3 D DUAL PORT MEMORY STATIC RAM MEMORY A 256K x 64 bit Dual Port synchronous SRAM DP SRAM is provided on the XMC SLX150 board A 1Meg x 64 bit Dual Port synchronous SRAM is provided on the XMC SLX150 1M board One port of the SRAM connects directly to the local bus to allow for PCle access The remaining port connects directly with the user programmable FPGA This design allows for the user to maximize data throughput between the Field l O s and the controlling processor There are two automatic DMA initiators available that will trigger upon a user set threshold Furthermore upon a DMA transfer the internal counter can be reset to a user specified value See DMA Registers for more information on these operations These features can be individually controlled through the SRAM Control Registers Static RAM Memory Read Write BAR4 MEMORY BARA 000000H to 7FFFFFH The Static RAM memory space is used to provide read or write access to on board SRAM memory This memory space allows access to the SRAM from the port on the PCle bus side of the SRAM The Static RAM device has a 1Meg x 64 bit capacity on the XMC SLX150 1M The Static RAM device on the base model XMC SLX150 has only a 256K x 64 bit capacity and only uses a portion of this memory space Reading or writing to this memory space using DMA access is also only poss
14. AND INSPECTION SENSITIVE ELECTRONIC DEVICES 00 NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC RADIOACTIVE FIELDS WARNING This board utilizes Static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS IMPORTANT Adequate air circulation or conduction cooling must be provided to prevent a temperature rise above the maximum operating temperature BOARD CONFIGURATION Default Hardware Configuration Front Panel Field I O Connector Rear P4 Field I O Connector Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 8 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module The example design defines the rear connector with 32 LVDS pairs The LVDS pairs are arranged in the same row in table 2 1 For example RIOO P and RIOO_N form a signal pair The P identifies the Positive input while the N identifies the Negative input Pin Negative Pin Description Pin RIOO P RIOO ES Table 2 1 Board Rear Field Positive Pin Description I O Pin Connections 0 E En ION E e example design 2 2 P us HIO2 FE implements 2 5volt LVDS I O EN E m to the rear connector Signal 51 ROSP 10 61 13 7 14 _16_ 171 _19_ 0 18 20 10 21 23 A1 222 Ra 12 RIOtl2P 25 2
15. H Issuing of a Flash Erase Sector command will erase the contents of the flash chip only in the sector specified A flash bit cannot be programmed from logic 0 to logic 1 Only an erase chip operation can convert logic O back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip or Flash Erase Sector command must be performed The system can determine the status of the erase operation by reading the Flash Ready Busy status Bit 7 of the Flash Status 2 register at base address plus 10H will read as logic O when chip erase is completed Any other flash commands written to the flash chip during execution of the flash erase sector operation are ignored Note that a hardware reset during the erase sector operation will immediately terminate the operation Flash Erase Chip Write Only BAR2 24H This write only register is used to erase the entire contents of the flash chip A flash bit cannot be programmed from logic 0 to logic 1 Only an erase chip operation can convert logic 0 back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip command must be performed A Flash Erase Chip command is executed by writing logic 1 to bit O of this register at base address plus 24H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is accomplished by reading bit 7 of the Flash Status 2 register as logic O The system can determine the status of the erase o
16. Memory Space Required BAR4 64 bit Base Address Register 1 for access to Dual Port SRAM Interrupts Source of interrupt can be from the U7 programmable FPGA or DMA Channels Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 44 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module Certificate of Volatility Acromag Model Manufacturer XMC SLX150 E Acromag Inc XMC SLX150 E 1M 30765 Wixom Rd Wixom MI 48393 Volatile Memory Does this product contain Volatile memory i e Memory of whose contents are lost when power is removed m Yes No Type SRAM SDRAM etc Size User Function Process to Sanitize SRAM 256K x 72 Modifiable Data storage Power Down or m Yes for FPGA 1Meg x 72 o No Type SRAM SDRAM etc Size User Function Process to Sanitize FPGA based RAM Variable Modifiable Data storage Power Down up to m Yes for FPGA 1Mbyte No Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed m Yes No Type EEPROM Flash etc Size User Function Process to Sanitize Flash 16Mbyte Modifiable Storage of Clear Flash memory by m Yes Code for FPGA writing a logic 1 to bit 0 of No the Flash Erase Chip Hegister at BAR2 24H Type EEPROM Flash etc Size User Function Process to Sanitize Flash 32Mbit Modifiable Storage of Not Applicable Yes Code for PCl
17. NCTION Table 3 3 Interrupt STEMS Ec Parr eae Control Status Register is bit when set indicates a pending board interrupt It reflects When designing software a pending interrupt from DMA channel 0 or DMA channel 1 or drivers it treat this the U7 FPGA It will reflect this status even if the Board register as two 16 bit registers le bit 31 is disabled nterrupt enable bit 31 is disabled The upper 16 bits are Interrupt 0 No Interrupt Pending Control bits and the lower 16 Interrupt Pending bits are Interrupt Status DMA Channel 0 Interrupt Pending Status Bit 16 must be set to logic high for this bit to go active Write logic high to clear bit 0 No Interrupt Pending Interrupt Pending DMA Channel 1 Interrupt Pending Status Bit 17 must be set to logic high for this bit to go active Write logic high to clear bit No Interrupt Pending Interrupt Pending be set to logic high for this bit to go active ls Interrupt Pending Interrupt Pending Tarra Ro Used bits are read as logic DMA Channel 0 Interrupt Enable 0 DMA Channel 0 Interrupt Disabled DMA Channel 0 Interrupt Enabled 17 DMA Channel 1 Interrupt Enable 0 Channel 1 Interrupt Disabled DMA Channel 1 Interrupt Enabled 18 U7 Programmable FPGA Interrupt Enable 0 Interrupt Disabled Interrupt Enabled 19 31 Not Used bits are read as logic 0 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag co
18. RAMMING INFORMATION Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 3 After you have thoroughly tested your customized FPGA design you can erase the flash and write your code to flash Once the flash is erased you will not be able to go back to the example design by simply powering down and restarting the board oee the Flash Configuration section for a description of the steps required to write new or reprogram of example design code to the flash device The registers provided in the FPGA Programming Memory Map are used to implement a flash erase and reprogram operations This board is a PCI Express Base Specification Revision 1 1 compliant PCle CONFIGURATION PCle bus board ADDRESS SPACE The PCle bus is defined to address three distinct address spaces I O memory and configuration space This board can be accessed via the PCle bus memory and configuration spaces The card s configuration registers are initialized by system software at power up to configure the card The board is a Plug and Play PCle card As a Plug and Play card the board s base addresses are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCle bus configuration access is used to read write the PCle card s configuration registers When the computer is first powered up the computer s system
19. SRAM port connected to the PCle bus through U5 supports reading and writing using a burst double word 4 byte DMA transfers For double word 4byte accesses address and control signals are applied to the SRAM during one clock cycle and either a write will occur on the next cycle or a read in two clock cycles DMA accesses operate using the continuous burst method for maximum data throughput The control signal starting address and data if writing are applied to the SRAM during one clock cycle Then during a write DMA transfer new data is applied to the bus every subsequent clock cycle until the transfer is complete During DMA transfers the address is held constant and incremented internally the Dual Port SRAM Please refer to the IDT70T3509SM Data Sheet See Related Publications for more detailed information Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 3 f The local bus interface between the PCle bus interface chip U5 and the THEORY OF OPERATION user programmable FPGA U7 consists of the following signals CONTINUED The Local Address bus LA bits 21 to 2 are used to decode the 4M byte address space allocated by the PCle bus to BAR2 Also LA 26 bit 26 of the local address bus is logic high when the PCle bus is performing an access to BAR2 address space LBEO n LBE1 n LBE2 n and LBES n are the local bus b
20. Spartan 6 Based FPGA XMC Module 1 1 Layout of a 64 bit long int High address The PCle specification requires software driven initialization and CONFIGURATION configuration via the Configuration Address space This board provides 512 REGISTERS bytes of configuration registers for this purpose It contains the configuration registers shown in Table 3 1 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Ports The most important Configuration Registers are the Base Address Registers and the Interrupt Line Register which must be read to determine the base address assigned to the board and the interrupt request line that goes active on a board interrupt request LN 015 08 D7 DO Table 3 1 Configuration Registers Device ID Vendor ID 0 5807 SLX150 0 5808 SLX150 1M 16D5 Class Code 118000 Rev ID200 Cache interrupt and DMA Registers 4K Space BARO 64 bit Memory Base Address 32 bit Data to Spartan 6 User Registers 4M Space BAR2 64 bit Memory Base Address 64 bit Data to Dual Port Memory 8M Space BAR4 Subsystem ID Subsystem Vendor ID 0x5807 SLX 150 0x5808 SLX150 1M 16D5 Not Used This board is allocated memory space address BARO to access the PCle interrupt and DMA registers The PCle bus decodes 4K bytes for these memory space registers This board is allocated a 4M byte block of memory BAR2 that is addressable in the PCle bus
21. T LT LT LT LT la 21 downto 2 0200E 02011 Id 000 00003030 ain AJ gc e RSS readyn Iw rn IbeO_n lbe1 n 2 n 26 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and soft
22. Table 3 15 Rear I O UL Bit Channels ER Channels Registers Column 1 identifies the write data bit that drives the output channel listed in column 2 Column 1 also identifies the read data bit that returns the input channel listed in column 3 For example data bit 0 drives output channel 1 when written and returns channel 0 register setting when read 1 All bits labeled Not Used will return logic 0 when read 16 31 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module DMA REGISTERS AT BAR2 Control Register Read Write BAR2 8034H The DMA Control Register is used to request a DMA Demand mode transfer The hardware signals DREQO and DREQG are driven active by software setting of bits O or 1 of this register to request the DMA transfer The transfer must include the Static RAM Memory as either the source or the destination For software triggered DMA 61 0 is used to request a DMA channel 0 transfer while bit 1 is used to request a channel 1 transfer The bit must be set to logic high to request a transfer Once set the bit will remain asserted until the DMA transfer has started If both bits are set simultaneously the channel 0 transfer will be implemented first followed by channel 1 In a user application a data ready condition such as a memory buffer full condition can be physically
23. air filtering In a conduction cooled assembly adequate thermal conduction must be provided to prevent a temperature rise above the maximum operating temperature Remove power from the system before installing board cables termination panels and field wiring The board may be configured differently depending on the application When the board is shipped from the factory it is configured as follows The on board flash memory device is read write enabled e The default configuration of the programmable software control register bits at power up are described in section 3 control registers must be programmed to the desired configuration before starting data input or output operation The front panel connector provides the field I O interface connections via optional mezzanine I O modules purchased separately The rear I O P4 connector connects directly to the user programmable FPGA The VCCO pins are powered by 2 5 volts and thus will support the 2 5 volt lOStandards The IOSTANDARD attribute can be set in the user constraints file UCF For example rear I O can be defined for LVCMOS25 low voltage CMOS The example design defines the rear I O to LVDS_25 Low Voltage Differential Signaling in the user constraints file Additional information regarding the 2 5V IlOStandards is available in the Spartan 6 selectlO Users Guide available from Xilinx Spartan 6 Based FPGA XMC Module f 2 0 PREPARATION FOR USE UNPACKING
24. al bus clk signal is controlled by USERo The board clock is routed to the Dual Port SRAM and user programmable FPGA U7 using a low skew clock driver Cypress CY23EP05 The on board 125MHz crystal oscillator is input to the user programmable FPGA via signal FPGA CLK PLL After the user programmable FPGA U7 is configured an FPGA DCM generated clock signal PLL_CLK is selected as the board clock the default condition By setting bit 8 of the Software Reset and otatus register at BAR2 plus 8000H to a logic high the 125MHz clock may be selected as the board clock By setting bit 8 to a logic low the PLL becomes the board clock frequency The default state of bit 8 is logic low Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 8 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module Local Bus Write Cycle Diagram ek LALO AA la 21downto 2 Id 00003030 ads n ee rdak 171 lwrn EoO RTT TICLLCLTULCLCOICLL CLR n 1 n Ibe2 n n la 26 Local Bus Read Cycle Diagram ek LETT UELUT LE LI UIT LE LT LT LT LT LE LT LT LE UT LT LT LT LT LT LT LT LT LT la 21 downto 2 00001 Jozon SSS id 000005 ads n DE S rdyack n Go hern 1 n lbe2 n n la 26 Local Bus Write and Read Cycle Diagram ek LU UU LE LT LT LT LE LT LT LT LT LT LT LE LE LT LT LT LE LT L
25. an 6 Based FPGA XMC Module R172 Resistor Location Board Bottom View 4s 2 o mm eee Ree YSN WOXIM SVWOHOV m e co 00 mr e ENS i Ae XMC SLX External Power Location Board Top View gt B iini JN El Ay Acromag Tel 248 624 1541 Fax 248 624 9234 Email solutions acromag com http www acromag com
26. and testing of both DMA channels It is strongly recommended that you become familiar with the board features by using the example design as provided by Acromag Do not attempt to reconfigure the flash memory until after you have tested and become familiar with the XMC SLX as provided in the example design 2 After you are familiar with the XMC SLX and have tested it using the example design you can move on to step 2 Here you will modify the example design VHDL code slightly It is recommended that you test this modified example design using the reconfiguration direct method is not recommended that the flash be overwritten until you have tested your code The reconfigure direct method will allow programming of the FPGA directly from the PCle bus If for some reason the XMC SLX does not perform as expected you can power the XMC SLX down Upon power up the example design provided by Acromag will again be loaded into the FPGA The document Using the XMC SLX Engineering Design Kit provided in the engineering design kit will guide you through the steps required to modify the example design for your custom application see the Direct PCle bus to Xilinx Configuration section for a description of the steps required to perform reconfiguration directly from the PCle bus The registers provided in the FPGA Programming Memory Map are used to implement a direct reconfiguration Standalone Operation Flash Write Disable Resistor 3 0 PROG
27. anual Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened lf the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the system boards plus the installed Acromag board within the voltage tolerances specified In an air cooled assembly adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to
28. ard to this BOARD DLL CONTROL SOFTWARE 6 material including but not BOARD VxWORKS SOFTWARE 6 limited to the implied BOARD QNX 5 6 warranties of merchantability BOARD LINUX 5 6 and fitness for a particular purpose Further Acromag 2 0 PREPARATION FOR USE assumes no responsibility for any errors that may appear in UNPACKING AND 7 eU ana MARES NO CARD CAGE 5 5 7 commitment to update or BOARD 7 Keep CUROM the information Default Hardware Configuration 7 Front Panel 1 7 par t of this manual na be Rear P4 Field I O Connector 7 copied or we oduced aay Non Isolation Considerations 8 form without the prior written Standalone Operation 9 consent of Acromag Inc 3 0 PROGRAMMING INFORMATION GETTING 9 PCle CONFIGURATION ADDRESS SPACE 10 BARO MEMORY 12 Interrupt Control Status Register 13 BARO 14 BAR
29. ash Chip to receive the new data byte to the Flash Address registers at base address plus 2CH 30H and 34H Issuing a Flash Start Write will automatically increment this address after the prior Flash Write has been completed Thus the address will not need to be set prior to issuing the next Flash Start Write The first byte of the configuration file should be written to address 0 of the Flash Chip The Flash Start Write operation will take 9u seconds to complete Issue a Flash Start Write command to the Flash Chip by writing logic 1 to bit 0 of base address plus 1CH Verify that the Flash Chip is not busy by reading bit 7 as logic 0 of the Flash Status 2 register at base address plus 10H before going back to step i to write the next byte Enable auto configuration by setting bit O0 Stop Configuration of the Configuration Control register to logic low Verify that the configuration is complete by reading DONE bit 0 of Configuration Status Register as logic high 10 Thereafter at power up the configuration file will automatically be loaded into the FPGA Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 22 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module Direct PCle bus to Xilinx Configuration of the Xilinx FPGA can be implemented directly from the Configuration PCle bus The following is the general procedure for re configuration of the Xilinx FPGA via the PCle bus 1 Disab
30. d Not Used bits are read as logic 0 DMA Channel 0 Abort on write of logic high to this bit O0 No Action Abort Channel 0 DMA transfer DMA Channel 1 Abort on write of logic high to this bit O0 No Action Abort Channel 1 DMA transfer Not Used bits are read as logic 16 19 20 23 Channel 1 State Encoding see bit descriptions given for Channels 0 on bits 16 19 24 31 Not Used bits are read as logic 0 Global Interrupt Enable Bit 31 Read Write 08H GLOBAL INTERRUPT ENABLE This Global Interrupt Enable bit at BARO base address offset 08H is used to enable all board interrupts An interrupt can originate from the two DMA channels or U7 the programmable FPGA All board interrupts are enabled when bit 31 is set to logic high Likewise board interrupts are disabled with bit 31 set to logic low Bit 31 of this register can be read or written FUNCTION Table 3 5 Global Interrupt Not Used bits are read as logic 0 Enable Bit XMC Board Interrupt Enable This bit must be set to enable the PCle bus interrupt signal to be driven active by the board 31 0 Board Interrupts Disabled Board Interrupts Enabled Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 6 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module DMA System Starting Address LSB Registers Read Write 100H and 120H This register contains the
31. e m No bus Interface Device Type EEPROM Flash etc User Function Process to Sanitize EEPROM Modifiable IMPI FRU Not Applicable n Yes information m No Acromag Representative Name Title Office Office Fax Joseph Dir of Sales jprimeau acromag com Phone 248 248 624 9234 Primeau and 295 0823 Marketing Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 45 opartan 6 Based FPGA XMC Module XMC SLX User s Manual XMC SLX Block Diagram 3OV3H3 NI sng 910d 19 8 X 9 AYOWSW NOLLVHPIOI3NOO HSV14 HOSN3S 3un1vu3dia uiv JI901 LdfiiH3 1NI 0 HO VAQ 91901 1044405 91901104109 9 3OV3H3 NI 93 LOEXT S XALHIA LOCAL BUS 91901 39V3U31NI snd 1V901 91901 1OHLNOO 32V383 NI 1 4 1 H39VNVN 49010 9 NVLYVdS 91907 19931 108109 LNOU3 V9d3 9 NVLYVdS 119 79 2 Scl 19 79 ZHI Sel NL 79 X WE 015 v9 X 4960 VHS 1HOd 1Vna 39019 snd W001 349010 WWHS 39019 NVUS 390190 V9d3 AdOOSdIHO OVI SH3AIHQ 32019 M33S MOT 03351 49019 OL V9d3 4900 ZHNSCI IV1SAHO uvad JINON WXV sng 3NINVZZ3N TANVd LNOH3 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 46 XMC SLX User s Manual Spart
32. e last descriptor in the 63 32 chain Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 8 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module DMA XMC Board Starting Address Registers Read Write BARO 110H and 130H The DMA XMC Board Starting Address register specifies the physical address of the board s Dual Port SRAM memory where data will be read written Data bits 22 down to 2 of this register are used to address the SRAM Data bit 2 select the low 32 bit SRAM U4 when logic low and selects the upper 32 bit SRAM U19 when logic high Data bits 22 down to 3 correspond to SRAM address lines 19 down to 0 Bits 19 and 18 are only used on the XMC SLX150 1M model For the standard model XMC SLX150 bits 19 and 18 should always be zero The DMA XMC Board Starting Address register at BARO base address plus 110H 130H is used to set the DMA channel 0 1 data starting address Writing to these registers is possible via 32 bit data transfers Start DMA Transfer Write Only BARO 114H and 134H The Start DMA Transfer register is used to software start a DMA transfer Set bit 0 to logic 1 will start the corresponding channels DMA transfer The Start DMA Transfer register at BARO base address plus 114H 134H is used to start the DMA channel 0 1 transfer Writing to these registers is possible via 32 bit data transfers Acromag Inc Tel 248 295 0310 Fax 24
33. ed and output from the ADC can be converted to voltage by using the following equation ADCcode S lyVolagevolts x 3V upplyVolage amp volts TE Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 2 f System Monitor Address Register Write Only BAR2 3CH This write only register is used to set the system monitor address register with a valid address for the System Monitor internal status or control registers Valid addresses are given in the following table Additional addresses can be found in the Xilinx System Monitor document UG192 available from Xilinx Writing this register is possible via 32 bit data transfers The address value written to this register can be read on bits 22 to 16 of the System Monitor Status Control register at BAR2 plus 38H Table 3 13 System Monitor Register Map 2th 22h 24h Minimum Temperature 25h Minimum Vccint 26h Software Reset and Status Register Read Write BAR2 U7 FPGA REGISTERS BAR2 8000H This read write register is used to Software reset the board monitor the status of board interrupts and select the on board active clock Bits O to 7 of this register are used to monitor the interrupt pending status of interrupts originating from the front mezzanine module Bit 8 of this register controls the USERo signal The USERo con
34. esholds respectively of the FPGA Port SRAM Control Register Note that the DMA transfers do not have to be enabled for this feature to function Reading of either register will return the corresponding internal address reset value Writing this register will set the corresponding internal address reset register to the provided value Bits O to 17 of this register are used in the XMC SLX150 Bits 0 to 19 of this registers are used in the XMC SLX150 1M The most significant bits are not used and will return logic when read A system reset will cause these registers to reset to 00000 XMC Board Identification Code Register Read Only BAR2 8058H The XMC Board Identification Code register at BAR2 plus 8058H stores an ID code that can used to uniquely identify the XMC Spartan 6 card This register will read A3 hex as provided by the Acromag example design The user can change the hardware setting of this register in the programmable FPGA code This ID code can be used to properly assign software drivers to multiple XMC boards that may have the same device and vender ID in a given system Reading from this register is possible 32 bit 16 bit or 8 bit data transfers D19 DO SLX150 SLX150 1M Not Used Read as logic 0 1FFFF 7FFFFH Reg Not Used Read as logic 0 SFFFF FFFFFH Reg Spartan 6 Based FPGA XMC Module 3 3 Table 3 18 Dual Port DMA Threshold Registers Reset Values 1 Bits 18 and 19 are Not Used in
35. ial signaling as 32 LVDS input output signals e Write Disable Jumper User configurable flash memory can be hardware write disabled by removal of an on board zero ohm surface mount resistor Example Design Provided The example VHDL design includes implementation of the Local bus interface control of digital front and rear I O and SRAM read write interface logic Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module D e PCle Bus A four lane PCI Express 1 1 operating at bus speed of 2 5 PCle INTERFACE Gbps per lane per direction is provided This gives up to 2GBytes sec FEATURES data rate on the bus PCle Bus Master The PCle interface logic becomes the bus master to perform DMA transfers e DMA Operation The PCle bus interface supports two independent DMA channels capable of transferring data to and from the on board SRAM The example design implements DMA block and demand modes of operation 64 32 16 8 bit I O Register Read Write is performed through data transfer cycles in the PCle memory space All registers can be accessed via 32 16 or 8 bit data transfers Access to Dual Port Memory can be accessed via 64 or 32 bit transfers Compatibility Complies with PCle Base Specification Revision 1 1 Provides one multifunction interrupt The XMC VLX is compatible with XMC VITA 42 3 specification fo
36. ible via 32 bit data transfers only The SRAM Internal Address will automatically be incremented upon a write or read of the most significant SRAM Data Port at BAR2 803CH FPGA Port SRAM Internal Address Register iiia SRAM Internal Address FPGA Port SRAM DMA Channel 0 1 Threshold Registers Read Write BAR2 8048H 804CH SRAM Internal Not Used Read as Address Reset logic 0 The FPGA Port SRAM DMA Channel 0 1 Threshold Registers are used to initiate an automatic DMA transfer When the internal address counter is equal to the value in the Channel 0 Threshold Register a Channel 0 DMA request will be initiated Similarly when the internal address counter is equal the value in the DMA Channel 1 Threshold Register and there is valid data at that address a Channel 1 DMA request will be initiated This feature must be enabled via bits 1 and 2 for Channels 0 amp 1 respectively of the FPGA SRAM Control Register Note that DMA settings must be set prior to the initiated transfer on both the BARO and BAR2 registers A DMA transfer in progress is indicated via bits O and 1 for DMA Channels 0 and 1 respectively in the DMA Control Register See the DMA Registers section of this manual for further details Reading of the Threshold register will return the corresponding DMA Threshold Writing the Threshold registers will set the corresponding DMA Threshold to the provided value Bits O to 17 of this register are
37. ible via 64 bit transfers The FPGA Port SRAM Register at BAR2 8038H and 803CH provided for testing the SRAM port that links directly to the user programmable Spartan 6 FPGA Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 3 6 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module This section contains information regarding the design of the board A 4 0 THEORY OF description of the basic functionality of the circuitry used on the board is also OPERATION provided Refer to the Block Diagram shown in Drawing 4502 131 as you review this material The PCle bus interface logic on this board provides a 2 5Gbps interface to the carrier CPU board per PCI Express Specification 1 1 The interface to the carrier CPU board allows complete control of all board functions PCle INTERFACE LOGIC The PCle bus endpoint interface logic is contained within a user interface FPGA This logic includes support for PCle commands including configuration read write and memory read write In addition the PCle interface requester and or completion accesses Payload of up to 256 bytes is supported The logic also implements interrupt requests via message signaled interrupts Messages are used to assert and de assert virtual interrupt lines on the link to emulate the Legacy PCI interrupt INTA signal The board performs DMA transfers on channels 0 and 1 The DMA transfers can be started via software
38. implemented in BARO These registers are read write registers that are software controlled These registers provide interrupt control status and DMA control status The Interrupt Control Status is at BARO base address plus OOH offset The DMA registers are at base address plus offset 100H to 134H These registers control the transfer Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 1 3 direction size system address and XMC addresses for DMA channels 0 and 1 The Dual Port SRAM control registers at BAR2 must also be used to set DMA Demand Mode transfer The Demand mode transfer is initiated by driving signals DREQO or DREQ1 active The SRAM control register method allows a DMA transfer to be initiated when an FPGA generated address counter is equal to the DMA Channel Threshold Register That is when the predetermined amount of data is available in the SRAM the hardware will automatically start a DMA transfer Interrupt Control Status Register Read Write BARO 00H INTERRUPT REGISTER This Interrupt Control Status register at base address offset 00H is used to monitor and clear pending board interrupts An interrupt can originate from the two DMA channels or U7 the user programmable FPGA All board interrupts are enabled or disabled via bit 31 of the Global Interrupt Enable register at BARO 08H FU
39. is register s pending status bits Status Abort Register Read Write 04H DMA transfers must start aligned to Double Lword boundary when performing 64 bit DMA transfers identify a DMA transfer complete status and issue DMA channel abort The complete status bit 0 or 1 will remain logic high until cleared by writing logic high back to the same bit The start of a new DMA transfer hardware initiated will also clear a set Transfer Complete bit The abort bits 8 and 9 corresponding to channels 0 and 1 respectively when set to logic high will abort the current DMA transfer If asserted and the channel still has outstanding requests all requests are handled before the transfer is aborted otherwise the transfer is immediately aborted If asserted and the current transfer is a Completion than a Completion with Completion Abort status is sent and the DMA transfer is stopped This register can be read or written via 32 bit transfers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 1 D FUNCTION Table 3 4 DMA Status DMA Channel 0 Transfer Complete This bit is cleared by Register write of logic high to this bit or start of a new DMA transfer 0 Transfer not Complete Transfer Completed write of logic high to this bit or start of a new transfer 0 Transfer not Complete Transfer Complete
40. its 15 to 8 of the address to which the flash chip is written upon issue of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Flash Address 23 216 Read Write BAR2 34H This read write register sets bits 23 to 16 of the address to which the flash chip is written upon issue of a Flash Start Write command Reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfer System Monitor Status Control Register Read Write BAR2 38H This read write register will access the system monitor register at the address set in the System Monitor Address Register For example the address of the System Monitor Status register that is to be accessed is first set via the System Monitor Address register at BAR2 plus 3CH Next this register at BAR2 plus 38H is read Bits 22 to 16 of this register hold the address of system monitor register that is accessed Data bits 15 to 6 of this register hold the temperature Vccint or Vccaux value Data bits 5 to 0 are not used Valid addresses are given in column one of Table 3 12 Reading or writing this register is possible via 32 bit data transfers The 10 bits digitized and output from the ADC can be converted to temperature by using the following equation ee OE AE 273 15 1024 The 10 bits digitiz
41. le auto configuration by setting bit O Stop Configuration of the Configuration Control register to logic high 2 Clear the Xilinx FPGA of its previous configuration by setting the Configuration Control register bit 2 to logic high 3 Read INIT as logic high Bit 1 of Configuration Status register before programming is initiated 4 Download the Configuration file directly to the Xilinx FPGA by writing to the Configuration Data register The entire configuration file must be written to the Xilinx FPGA one byte at a time to the Configuration Data register at base address plus 08H 5 Verify that the configuration is complete by reading DONE bit O of Configuration Status Register as logic high DONE is expected to be logic high immediately after the last byte of the configuration file is written to the Xilinx FPGA At each power up the configuration file will need to be reloaded into the FPGA CONFIGURATION CONTROL Configuration Status Register Read Only BAR2 REGISTERS 0000H This read only register reflects the status of configuration complete and Xilinx configuration clear bits This Configuration Status register is read at base address plus OH Table 3 9 Configuration FUNCTION Status Register DONE 0 Xilinx FPGA is not configured Xilinx FPGA configuration is complete INIT INIT is held low until the Xilinx is clear of its current configuration INIT transitions high when the clearing of the current Xilinx co
42. least significant 32 address bits of the DMA oystem Starting Address The DMA System Starting Address register meaning depends on the selected DMA mode see bit 3 of DMA command register For Direct DMA Mode this address register specifies the physical address of a contiguous memory buffer where data will be read written For scatter gather DMA mode this address register points to the first element of the chained listed of page descriptors The DMA System Starting Address Register at BARO base address plus 100H 120H is used to set the DMA channel 0 1 data starting address Writing to these registers is possible via 32 bit transfers DMA System Starting Address MSB Registers Read Write BARO 104H and 124H This register contains the most significant 32 address bits of the DMA oystem Starting Address The DMA System Starting Address register meaning depends on the selected DMA mode see bit 3 of DMA command register For Direct DMA Mode this address register specifies the physical address of a contiguous memory buffer where data will be read written For scatter gather DMA mode this address register points to the first element of the chained listed of page descriptors The DMA System Starting Address Register at BARO base address plus 104H 124H is used to set the DMA channel 0 1 data starting address Writing to these registers is possible via 32 bit transfers DMA Transfer Size Registers Read Write 108H a
43. m http www acromag com 1 A XMC SLX User s Manual Spartan 6 Based FPGA XMC Module DMA BARO REGISTERS This DMA Status register at BARO base address plus 04H is used to DMA BARO REGISTERS A board pending interrupt is identified via bit O of this register Logic high on bit 0 indicates a board pending interrupt Bit O indicates a pending interrupt as long as DMA Channel 0 DMA Channel 1 or U7 Programmable FPGA interrupt pending status bits 1 2 or 3 respectively remain active A DMA channel 0 pending status can be cleared released by writing logic high to bit 1 the interrupt pending status bit Likewise writing logic high to bit 2 of this register clears DMA channel 1 pending status U7 Programmable FPGA interrupt Pending status will pass the interrupt status of U7 only when bit 18 is set to logic high The Software Reset and Status Register at BAR2 8000H can be read to identify the exact source of the Programmable Spartan 6 FPGA interrupt Bits 16 to 18 of this register are used to enable or disable interrupts from specific functions This Interrupt register must have bits 16 and 17 set to logic high in order for DMA interrupts to occur on DMA channels 0 and 1 respectively Bit 18 must be set to logic high to enable interrupts from U7 the programmable FPGA The mezzanine board interrupt enable bits must also be set if interrupts are to originate from the mezzanine board which are passed through the programmable FPGA to th
44. memory space BAR2 space is used to access the board s flash configuration functions and the reprogrammable Spartan 6 FPGA registers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 1 2 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module In addition this board is allocated BAR4 memory of 8M bytes The BAR4 memory is addressable in the PCle bus memory space to access the board s Dual Port Memory transfers Note that the base model XMC SLX150 does not utilize the entire block of memory BARO MEMORY MAP Note that any registers bits not Interrupt Control Status mentioned will remain at the default value logic low om Status Abort Register om Global interrupt Enable 81 37 Channel 0 System Address LSB DMA Channel 0 System Address MSB DMA Channel 0 Transfer Size in bytes 10CH DMA Channel 0 Command Channel 0 XMC Board Starting 31 0 Address DMA Channel 0 Start DMA Transfer Bit 118H to 30 DMA Channel 1 System Address LSB izm DMA Channel System Adress MSB Channel 1 Transfer Size in bytes 12CH DMA Channel 1 Command DMA Channel 1 XMC Board Starting 31 0 Address 0 DMA Channel 1 Start DMA Transfer Bit Dm registers are implemented the PCle bus interface chip and not the user programmable FPGA As such the user cannot change the logic functions
45. moves from SRAM to system memory Writing to these registers is possible via 32 bit data transfers Table 3 6 DMA Command 0 Not Used bitis read as logic 0 Register 3 Scatter gather Setting this bit enables scatter gather mode DMA transfers must start aligned to Double Lword boundary when performing DMA transfers Direct DMA Mode Enable Scatter Gather Mode 7to4 DMA Command Memory Read Burst Memory Write Burst In Scatter Gather DMA transfer mode the DMA start address is a pointer to a chained list of page descriptors Each descriptor contains the address and size of a data block page as well as the next descriptor block The following table describes the 20 byte block Scatter Gather descriptor wes The Start address of memory page that Page Address must be aligned on an 8 byte boundary 31 3 bits2 0 must be 000 If a page is located in 32 bit address space then bits 63 32 must be set to O Page Address f a page is located in 64 bit address space 32 then the full 64 bit address must be Table 3 7 Scatter Gather Descriptor Block initialized eS The size of the memory page in units of 31 0 bytes and a multiple of 8 bytes Next Descriptor The address of the next page descriptor 31 2 which must be aligned on a 4 byte boundary Bit 0 is End bits 1 0 must be 00 Chain bit Setting bit 0 to logic 1 indicates that the Next Descriptor current descriptor is th
46. must first verify that that Flash Chip is not busy before executing a new Flash command The Flash Chip is busy if bit 7 of this register is set to logic 1 The Flash will always be Busy while bit 0 of the Configuration Control register is set to logic 0 Table 3 12 Flash Status 2 Bit s FUNCTION Register Not Used bits are read as logic 0 Busy Ready Set bit 0 of the Configuration Control register to logic 1 before monitoring this busy bit Flash Chip is Ready Flash Chip is Busy Flash Read Read Only 14H A Flash Read command is executed by reading this register at base address plus 14H Prior to issue of a Flash Read the Flash Address registers must be set with the desired address to be read See the Flash Address registers at base address plus 2CH 30H and 34H The system must issue the Flash Reset command to re enable the device for reading array data if DQ5 goes high DQ5 can go high during a Flash Start Write Flash Erase Chip or Flash Erase Sector operation DQ5 can be monitored via the Flash Status 1 register at base address plus OCH Flash Reset Write Only BAR2 18H This write only register is used to initiate a reset of the flash chip A Flash Reset command is executed by writing logic 1 to bit O of this register at base address plus 18H Writing the flash reset command resets the chip to reading data mode Flash reset can be useful when busy is held active Flash S
47. nd 128H The DMA Transfer Size Register is used to set the size of the DMA transfer that moves data between system memory and the board s Dual Port SHAM The transfer size indicates to total amount of data to transfer in units of bytes The onboard static RAM for the XMC SLX150 has 2 Megabyte maximum capacity As such the maximum value that should be written to this register is 200000 The XMC SLX150 1M has an 8 Megabyte capacity and the maximum value that can be written is 800000 WARNING The XMC SLX150 will allow for a larger value to be written than available SRAM size which will cause undesirable operations This address must be set to a DWORD boundary multiple of 4 for proper operation The Transfer Size Register at BARO base address 108 128H is used to set the DMA channel 0 1 data transfer size Writing to these registers is possible via 32 bit data transfers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 1 f Command Registers Read Write BARO 10CH and 12CH The DMA Command register is used to set the priority Scatter Gather enable and to indicate the command to be used for the DMA transfer Memory Read Burst command is used to program a read transfer The data is moved from system memory to the boards SRAM memory Memory Write Burst command is used to program a write transfer The data
48. nfiguration is complete Not Used bits are read as logic 0 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 2 3 Configuration Control Read Write BAR2 04H CONFIGURATION CONTROL REGISTERS This read write register is used to stop Xilinx configuration and clear Xilinx configuration memory This Configuration Control register is accessed at base address plus 04H FUNCTION Table 3 10 Configuration Stop Xilinx Configuration Control Register 0 Enable Xilinx FPGA configuration Stop Xilinx FPGA configuration This bit should be set to logic high until after the Flash device is written with valid Not Used bit is read as logic 0 2 Clear Current Xilinx Configuration Logic low has no effect Logic high resets the Xilinx configuration logic Re configuration can begin after INIT transitions high Not Used bits are read as logic Configuration Data Write Only BAR2 08H This write only register is used to write Xilinx configuration data directly to the Xilinx FPGA from the PCle bus The Configuration Data register is accessed at base address plus 08H The entire configuration file must be written to the Xilinx FPGA one byte at a time Configuration complete is verified by reading DONE bit 0 of the Configuration Status Register as logic high A write to the Configu
49. ode Voltage 0 3 volt min 1 2 volt typical 2 35 volt max See the mezzanine module users manual for front I O specifications This PMC module uses the 150 pin Samtec connector part number QSS 075 01 L D A which mates with the mezzanine module connector part number QTS 075 02 L D A K Write Disable Jumper Removal of surface mount resistor R172 disables write to the to the Xilinx FPGA configuration flash device The location of R172 is shown in diagram 4502 088 Board Crystal Oscillator 125MHz Frequency Stability 0 0020 or 20 XMC SLX150 256k x 64 bit Integrated Devices Technology IDT701T3519S133BC 133 Megahertz Speed XMC SLX150 1M 1Meg x 64 bit Integrated Devices Technology IDT70T3509MS133BP 133 Megahertz Speed 16M x 8 bit 128 addressable sectors of which 41 are used for FPGA Configuration PCI Express 1 1 PCI Express electrical and protocol standards Performs 2 5 Gbps data rate per lane and per direction ANSI VITA 42 0 Complies with XMC module mechanicals and connectors Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 43 ANSI VITA 42 3 XMC module with PCI Express Interface 4K Memory Space Required 64 bit Base Address Register 0 for access to configuration registers 4M Memory Space Required BAR2 64 bit Base Address Register 2 for access to the user programmable FPGA U7 8M
50. ower up Flash programming is also implemented over the PCle bus Acromag provides an example design that includes an interface to the user rear I O and front I O connectors The example design also includes an interface to the SRAM with DMA hardware support OPERATING MODEL Dual P dla TEMPERATURE RANGE XMC SLX150 256K x 64 bit 0 C to 70 XMC SLX150E 256K x 64 bit 40 to 85 XMC SLX150 1M 1M x 64 bit 0 C to 70 XMC SLX150E 1M 1M x 64 bit 40 C to 85 C e Reconfigurable Xilinx FPGA In system configuration of the FPGA is performed through a flash configuration device or via the PCle bus This provides a means for creating custom user defined designs e Dual Port SRAM A 256K x 64 bit dual port static random access memory SRAM is included One port of the SRAM provides a direct link from the PCle bus to the SRAM memory The second port of the SRAM provides a direct link to the Xilinx user programmable FPGA There is an order option 1M to increase the SRAM size to 1 Meg x 64 bit Interface to Front Multifunction Modules Various mezzanine modules model prefex ordered separately allow the user to select the Front I O required for their application e Interface to Rear P4 Connector The Spartan 6 FPGA is directly connected to 64 pins of the rear P4 connector All 2 5volt standards supported by the Spartan 6 device are available The example design provides low voltage different
51. peration by reading the Flash Ready Busy status Bit 7 of the Flash Status 2 register at base address plus 10H will read as logic 0 when chip erase is completed Any other flash commands written to the flash chip during execution of the flash erase chip operation will be ignored Note that a hardware reset during the chip erase operation will immediately terminate the operation Flash Data Register Read Write BAR2 28H This read write register holds the data byte which is sent to the flash chip upon issuing of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 2 6 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module FLASH REGISTERS SYSTEM MONITOR REGISTERS U5 PCle bus This system monitor is within the Virtex 5 LX3OT that controls the PCle Interface Flash Address 7 50 Read Write BAR2 2CH This read write register holds the least significant byte of the address to which the flash chip is written upon issue of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Flash Address 15 58 Read Write BAR2 30H This read write register sets b
52. r P15 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 6 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module ENGINEERING DESIGN KIT BOARD DLL CONTROL SOFTWARE BOARD VxWORKS SOFTWARE BOARD QNX SOFTWARE BOARD Linux SOFTWARE Acromag provides an engineering design kit for the SLX boards sold separately a must buy for first time SLX module purchasers The design kit model XMC SLX EDK provides the user with the basic information required to develop a custom FPGA program for download to the Xilinx user programmable FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source and other utility files The SLX modules are intended for users fluent in the use of Xilinx FPGA design tools Acromag provides a software product sold separately to facilitate the development of Windows 2000 XP Vista 7 applications accessing Acromag PMC and 1 0 board products PCI and PCle 1 0 Cards and CompactPCI I O Cards This software Model PCISW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLs that are compatible with a number of programming environments including Visual C Visual Basic and others The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers Acromag provides a
53. ration Data register while auto configuration from Flash is active will cause the Xilinx configuration to fail Auto configuration is stopped by writing logic 1 to bit O of the Configuration Control register at base address plus 04H The Xilinx FPGA should also be cleared of its current configuration prior to loading of a new configuration file The FPGA is cleared of its current configuration by writing logic 1 to bit 2 at address plus 04H Flash Status 1 Read Only BAR2 FLASH CONTROL REGISTERS This read only register is used to read the DQ5 status of the flash chip The Flash Status 1 register is at base address plus OCH Bit s FUNCTION Table 3 11 Flash Status 1 0104 Not Used bits are read as logic 1 or 0 Register DQO Chip enabled for reading array data goes high DQ5 will go high during a Flash Start Write Flash Erase Chip or Flash Erase Sector operation 6 6and Not Used bits are read as logic 1 or 0 The system must issue the Flash Reset command to re enable the device for reading array data if DQ5 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 24 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module FLASH CONTROL Flash Status 2 Read Only BAR2 10H REGISTERS This read only register is used to read the ready or busy status of the flash chip The Flash Status 2 register is at base address plus 10H The system
54. ration of the Xilinx FPGA 8 9 Disable auto configuration by setting bit 0 Stop Configuration of the Configuration Control register to logic high Clear the Xilinx FPGA of its previous configuration by setting the Configuration Control register bit 2 to logic high Software must also keep bit 0 set to a logic high Read INIT as logic high Bit 1 of Configuration Status register before programming is initiated Verify that the Flash Chip is not busy by reading bit 7 of the Flash otatus 2 register at base address plus 10H as logic 0 before starting a new Flash operation Erase the current flash contents by using the Flash Erase Sector method Flash erase sectors are implemented by setting bit O of the Flash Erase Sector register to logic high There are 128 flash sectors which are addressed via the most significant seven flash address lines The most significant seven flash address lines are set via the Flash Address 23 17 register at base address plus 34H Issuing a Flash Erase Sector command will erase the contents of the flash chip only in the sector specified Verify that the Flash Chip is not busy by reading bit 7 of the Flash otatus 2 register at base address plus 10H as logic 0 before going to the next step Download the Configuration file to the flash configuration chip via the PCle bus ii iii iv Write the byte to be sent to the Flash Data register at base address plus 28H Write the address of the Fl
55. reset Bit 31 Logic 0 Loaic 1 Software reset issued to Xilinx user 9 programmable FPGA Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 29 Rear I O Connector Read Register Read Only BAR2 802CH REAR Read REGISTER The Rear I O Connector Read Register is used to read the LVDS input status of 16 channels This example design has 16 channels identified in Table 3 14 programmed as LVDS input only channels Table 2 1 shows each channel and it s corresponding P4 connector pin assignment This Rear I O Connector Read register is a read only register and writing to this register has no effect on the LVDS input channels Reading from this register is possible via 32 bit 16 bit or 8 bit data transfers Rear I O Connector Write Register Read Write BAR2 8030H REAR Write REGISTER The Rear I O Connector Write Register is used to set 16 LVDS output channels This example design has 16 channels identified in Table 3 11 fixed as LVDS output only channels Table 2 1 shows the P4 connector pins and their corresponding channel identifiers This Rear I O Connector Write register is written to set the LVDS output channels and can also be read to verify the output channel settings Reading from this register is possible via 32 bit 16 bit or 8 bit data transfers Write Read Data Rear Connector Write Rear Connector Read
56. romag com http www acromag com 3 2 XMC SLX User s Manual DP SRAM REGISTERS Warning To guarantee functionality disable DP SRAM write cycles via bit 0 of the DP SRAM Control Registers before writing to the DP SRAM Internal Address Register Table 3 17 FPGA Port SHAM Internal Address Register 1 Bits 18 and 19 are only used in the XMC SLX150 1M model They read as logic 0 in the XMC SLX150 base model Note An SHAM DMA Request will occur only after a data write cycle to the address defined by the DMA Threshold Registers Spartan 6 Based FPGA XMC Module FPGA Port SRAM Internal Address Register Read Write BAR2 8044H The FPGA Port SRAM Internal Address Register is used to view and set the internal SRAM address The FPGA will only write using 64 bit data transfers allowing for SFFFF hex unique memory accesses for the base XMC SLX150 model and FFFFF hex unique addresses for the XMC SLX150 1M model Reading this register will return the internal SRAM address Due to delays during data processing and the PCle transfer the actual internal address may be slightly greater than the address read Writing to this register will set the Internal SRAM Address to the provided value Bits 0 to 19 of this register are used Writing logic 1 to bit 31 of this register or a system reset will cause the Internal SRAM Address to reset to 000000 the start of the SRAM memory Reading or writing to this register is poss
57. sure port contact discharge Radiated Emissions Meets or exceeds European Norm 61000 6 3 2007 for class B equipment Shielded cable with I O connections in shielded enclosure is required to meet compliance Xilinx XC6SLX150 3FG676 FPGA XMC SLX150 e 184 304 CLB Flip Flops 1 355Kbit Distributed RAM e 268 18Kbit Block RAMs e 180 DSP48A1 Slices 6 Clock Management Tiles Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 42 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module REAR I O FRONT I O Write Disable Jumper Dual Port SRAM Flash Memory PCle Bus Interface The rear I O P4 connector connects directly to banks 0 of the FPGA The bank 0 Vcco pins are powered by 2 5 volts and thus will support the 2 5 volt lOStandards Refer to the Spartan 6 SelectlO Users Guide available from Xilinx for more information on the lOStandards available The example design defines the rear I O with 2 5 volt LVDS e Maximum Recommended Clock Rate 150MHz 6 7ns clock period Vcco Supply Voltage 2 5 volt Voy Output High Voltage 1 602 volt Vo Output Low Voltage 0 898 volt e Vopirr Differential Output Voltage 350m volt typical e Output Common Mode Voltage 1 25 volt typical e Differential Input Voltage 100m volt minimum e Vicy Input Common M
58. tart Write Write Only BAR2 1CH This write only register is used to initiate the write of a byte to the flash chip A Flash Start Write command is executed by writing logic 1 to bit O of this register at base address plus 1CH Prior to issuing of a Flash Start Write the Flash Data and Address registers must be set with the desired data and address to be written See the Flash Data and Address registers at base address plus 28H 2CH 30H and 34H Issuing of a Flash Start Write will automatically increment this address after the previously issued Flash Write has completed Thus the address will not need to be set prior to issuing of the next Flash Start Write if consecutive addresses are to be written Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 2 D Flash Erase Sector Write Only BAR2 20H FLASH CONTROL e REGISTERS A Flash Erase Sector command is executed by writing logic 1 to bit O of this register at base address plus 20H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is accomplished by reading bit 7 of the Flash Status 2 register as logic O There are 128 flash sectors which are addressed via the most significant seven flash address lines The most significant seven flash address lines are set via the Flash Address 23 17 register at base address plus 34
59. the If enabled via this bit a DMA Channel 1 request will be issued when the internal address counter is equal to the Doy d Channel 1 Threshold Register This will have the same effect lee Cei as writing a 1 to bit 1 of the DMA Control Register at BAR2 Threshold Register is not 2 olus 8034H equal to the Address Logic 0 Disable Auto DMA Request Channel 1 Reset nese registers are equal and Logic 1 Enable Auto DMA Request Channel 1 enabled an infinite loop will be If enabled via this bit the Internal Address Counter will be created within the internal loaded with the value in Address Reset Register 0 when the logic of the FPGA counter is equal to the DMA Channel 0 Threshold Register see the Address Reset Register description for further details DMA does not have to be enabled to use this feature Logic 0 Disable Add Reset on DMA Ch 0 Threshold Logic 1 Enable Add Reset on DMA Ch 0 Threshold If enabled via this bit the Internal Address Counter will be loaded with the value in Address Reset Register 1 when the counter is equal to the DMA Channel 1 Threshold Register see the Address Reset Register description for further details DMA does not have to be enabled to use this feature Logic 0 Disable Add Reset on DMA Ch 1 Threshold Logic 1 Enable Add Reset on DMA Ch 1 Threshold Not Used Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions ac
60. the XMC SLX150 DP SRAM REGISTERS WARNING The DMA Ch 0 Threshold Register must not equal the Address Reset Register 0 and the Ch 1 Threshold Register must not equal the Address Reset Register 1 If these registers are equal and the address reset is enabled via the FPGA Port SRAM Control Register an infinite loop will be created within the internal logic of the FPGA ID Code REGISTER Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 34 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module SYSTEM MONITOR Temperature Data Register Read only BAR2 8090H REGISTERS U7 FPGA This read only register provides the data from the external temperature monitor on the XMC SLX This register is automatically updated every second Data bits 12 to O of this register hold the temperature information Reading this register is possible 16 bit or 32 bit data transfers The 12 bits digitized output from the temperature sensor reads from 55 C minimum to 150 C maximum The number is stored in two s compliment format with each bit equal to 0 0625 C Refer to table 3 19 for data values Table 3 19 Temperature Data External Temperature Data Conversions WE 0 0000 0000 0000 0 0000 0000 0001 0 06285 C 0 1001 0110 0000 150 C Max 11111 1111 1111 0 06285 C 1 1110 0111 0000 1 1100 1001 0000 55 Min Acromag Inc Tel 248 295 0310 Fax 248 624
61. thresholds The default power up state of this register is logic low A reset will set all bits in this register to 0 Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual Spartan 6 Based FPGA XMC Module 3 1 FUNCTION Table 3 16 FPGA Port SRAM This bit controls the vhdl signal SRAM ENABLE This signal Control Register must be set to logic high to enable writes to SRAM from the FPGA The SRAM Internal Address register must also be set 1 Bits are not used and will with the start address at which the data begins filling the return logic 0 when read SRAM Disable Write and Enable Read 2 All DMA transfer settings in the DMA Registers at Enable Write and Disable Read BARO should be set prior If enabled via this bit a DMA channel 0 request will be issued to enabling automatic when the internal address counter is equal to the DMA DMA transfers Channel 0 Threshold Register This will have the same effect as writing a 1 to bit 0 of the DMA Control Register at BAR2 WARNING Bef plus 8034H See Synchronous DP SRAM in Section 4 0 for yn further details on using this feature g on DMA Thresholds bits 3 Logic 0 Disable Auto DMA Request Channel 0 amp 4 verify that the Logic 1 Enable Auto DMA Request Channel 0 on is not equal to
62. tied via logic in the FPGA to the DREQO or DREQ1 FPGA signals to cause the DMA transfer to start Note that the Spartan 6 FPGA has input signals DACKO n and DACK1 n that are active during DMA transfer These signals are not accessible via a register but can be used in custom firmware DUAL PORT SRAM FPGA SRAM Data Register Read Write BAR2 8038H and 803CH REGISTERS The FPGA SRAM Data Read Register is provided to access the SRAM port that links directly to the user programmable Spartan 6 FPGA Reading or writing BAR2 8038H accesses the SRAM least significant data lines 31 to 0 Reading or writing BAR2 803CH accesses the most significant SRAM data lines 63 to 32 Reading or writing these registers is only possible in 32 bit transfers The address for the SRAM read or write is initialized by the Dual Port SRAM Internal Address register at BAR2 8044H With each additional read or write to BAR2 803CH the address is automatically incremented Writing the SRAM would proceed by first setting the Address register at BAR2 8044H Next the least significant 32 bit data word is written to BAR2 8038H Finally after the most significant 32 bit data word is written at BAR2 803CH the address is automatically incremented FPGA Port SRAM Control Register Read Write BAR2 8040H This read write register is used to control the Dual Port SRAM including enabling write automatic DMA transfer and automatic address reset on DMA
63. trol USERo CLOCK CONTROL signal is used to select between the 125MHz clock and the user defined clock The user defined clock is defined in the example code of the FPGA and output on signal PLL_CLK The Digital Clock Manager of the FPGA offers a wide range of clock management features including clock multiplication and division for generation of a user defined clock PLL A 125MHz crystal generated clock signal FPGA CLK PLL is input to the FPGA for use in generation of the user defined clock signal The PLL CLK can be a minimum of 62 5MHz and a maximum of 125MHz since the PLL signal is generated and driven by the FPGA it will only be available after the FPGA is configured See the example VHDL file included in the engineering design kit and the Xilinx documentation on the Digital Clock Manager for more information Note USERo selects the Local bus clock The USERo signal is controlled via a bit 8 of the Software Reset and Status Register at BAR2 plus 8000H The USERo control bit 8 at by default is set to a logic low to select the PLL_CLK clock as the board clock frequency Bit 8 set to logic high will select the 125MHz clock as the board clock frequency Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 28 XMC SLX User s Manual Spartan 6 Based FPGA XMC Module Bits 15 to 13 of this register will read 001 for all Acromag digital I O mezzanine modules
64. used in the XMC SLX150 Bits O to 19 of this registers are used in the XMC SLX150 1M Reading or writing to this register is possible via 32 bit data transfers only The default and reset values of these registers is shown in Table 3 18 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com XMC SLX User s Manual FPGA Port SRAM DMA Channel 0 1 Threshold Registers Reset Values DMA D30 D20 Channel 0 Threshold DMA Channel 1 Threshold FPGA Port SRAM Address Reset Registers 0 1 Read Write BAR2 8050H 8054H The FPGA Port SRAM Address Reset Registers are used to reset the internal address counter to a user defined value immediately upon reaching the DMA Threshold value For example after an SRAM write cycle where the internal address counter is equal to the value defined in the DMA Channel 0 Threshold Register the internal address counter will then be loaded with the value defined in the Address Reset Register 0 Similarly after a SRAM write cycle where the internal address counter is equal to the value defined in the DMA Channel 1 Threshold Register the internal address counter will then be loaded with the value defined in the Address Reset Register 1 This allows for the internal address counter to be changed without any interruption in the transfer of data from the front connector input to the DP SRAM This feature must be enabled via bits 3 and 4 for Channel 0 amp 1 thr
65. ware information Acromag s application engineers can also be contacted directly via telephone or via email for technical assistance through the number or email address listed at the bottom of this page When needed complete repair services are also available opartan 6 Based FPGA XMC Module 3 O 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com 40 XMC SLX User s Manual 6 0 SPECIFICATIONS PHYSICAL Unit Weight Connectors Table 6 1 Power Requirements for Example Design Power will vary dependent on the application 5V Maximum rise time of 100m seconds ENVIRONMENTAL Spartan 6 Based FPGA XMC Module Single XMC Board Height 13 5 mm 0 531 in Stacking Height 10 0 mm 0 394 in Depth 149 0 mm 5 866 in Wiath 74 0 mm 2 913 in Board Thickness 2 21 mm 0 08 in XMC SLX 3 590z 0 1016Kg typical P15 XMC 3 144 pin Samtec ASP 103614 05 connector Complies with ANSI VITA 42 3 2006 P14 Rear I O Interface One 64 pin female receptacle header AMP 120527 1 or equivalent This connector provide 64 rear I O connections Front Field Connector on XMC module Samtec QSS 075 01 L D A Mating Mezzanine Connector Samtec QTS 075 01 L D A with 5mm stack height or Samtec QTS 075 0
66. yte enables Local Bus Signals LBEO n when logic low indicates that the least significant byte on data lines D7 to DO is selected for the read or write transfer Likewise LBE3 n when logic low indicates that the most significant byte on data lines D31 to D24 is selected for the read or write transfer The Local Data LD bus bits 31 to 0 are bi directional signals used for both read and write data transfers ADS n the address data strobe signal will pulse low for one local bus clock cycle at the start of a new read or write access The ADS n signal is driven by the PCle bus interface chip U5 Readyn must be driven low on read or write cycle by the programmable FPGA U7 and held low until RdyAck n is driven low by the PCle bus interface chip U5 This is shown on the read and write diagrams that follow Rdyack_n is driven low by the PCle bus FPGA U5 to signify the end of the read or write cycle The n signal when logic high indicates a write transfer in which data is moving from the PCle bus to the reprogrammable FPGA U7 This signal when logic low indicates a read transfer in which data is moving from the reprogrammable FPGA U7 to the PCle bus the local bus clock as seen in the following timing diagrams can be one of two sources By default clk is a Digital Clock Manager DCM generated clock frequency CIk can also be selected directly from the board 125MHz frequency Local Bus CLOCK CONTROL The Loc

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