TC1766 Micro Link Interface: Quick Start
Contents
1. no How to set up an MLI connection Stand By Command Frame on pipe 3 received PESP Y Clear all errors Y Clear receive interrupt flags MLI Quick Start Y Enable Move Engine Y Send Command Frame on pipe 3 Y Clear transmit interrupt flags Y Stand By Figure 9 Application Note Start up procedure MC2 step 2 16 V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start How to set up an MLI connection 3 2 1 3 Start up procedure third step This step finalizes the start up of MC1 When MC1 acknowledges the command frame on pipe 3 it will initiate an interrupt routine where several actions are performed A flow chart describing step 3 is depicted Fig 10 First all errors flags are cleared bits MLIO TRSTAR CNAE MLIO TRSTAR CTPE MLIO RCR PE Then the interrupt flags registers MLIO RIER and MLIO TIER are reset Interrupts are besides enabled on the reception of normal frames interrupt source DMA MLIOSRCO SRPN 1 in this example This interrupt source is used when answer frames are received Optimized frame mode is then enabled by setting MLIO TCR NO Finally a flag will be set which will trigger the read write operations in this example the flag is a global variable called MLI Remote Ready Application Note 17 V 1 0 2005 04 tec2. AP32087 MLI Quick Start Practical Implementation 25 Processor Bypasses Select All bypasses TriCore YX toolset Project Options CPU Functional Problem Bypasses TC1 766 Ej Processor pe Processor Definition ce f All bypasses TC1766 s Bypasses 2 a EN LJ CPU TC 013 see note TC 048 Hm EE E C Compiler o CHI TE EE l Assembler CPU TC 068 H PCP Assembler ee ge Link CFU TC 063 Linker ee CPU TE Ul Crossyiem Pro L E O CPU_TC 071 O CPU_TC 072 Mote The system startup code lib sresestart asm must have been added to your project Cancel Default Help Application Note 38 V 1 0 2005 04 py Infineon technologies AP32087 MLI Quick Start Practical Implementation 26 C Compiler gt Preprocessing Disable automatic inclusion of sfr files TriCore VX toolset Project Options REESE a B l x Preprocessing H Processor E C Compiler Store the C compiler preprocess output lt file gt pre E C Compiler Utomatic inclusion of str file e g disable for DAYE projects de Preprocessing pv Language Define user macros e g VALLIE 100 SERIAL Debug Information Code Generation Optimization H Allocation Include this file before source Warnings NENNEN ER e MISAA C L Miscellaneous Assembler PCP Assembler Linker rass View Pro Options string Wie no tasking str Lte1 bbb Wwit c99 wes
3. rrrrrrrnrrrarerarrrnnrnrnnernnrrnarnranrnnnennannnnnennnennn 19 4 Practical Implementation rarornnrnnnnrnanrrnnennarnranernnennnnnnanennnennannnnnennsnnnnenn 21 4 1 Hardware connection esssssssssssssssssseee eene nennen nennen nna nnn nns 21 4 2 Setting up MC1 rrrnnnnnrnnnnnronrnnnrvnnnnnrnnnnerenrnnnsnnnnnnrnrnnsrenrnnesnnnnsnsnnnnsnennnnssen 23 4 2 1 Configuration of the local controller rrrrnnrrrrnnrrrrrnnrrnrnnrrnrnnnrenrnnrrnnnnn 23 4 2 2 Setting up Tasking environment rrnnranrnnnrenrnnrrrnrnnrervnnerennnnrrrnnnsnennnnsne 36 4 2 3 Programming of the Local CoOntroller ccccseccceeeeeeeeeeeeeeeeeeeeeaeeeeesaees 45 4 3 SUNN M ON 52 4 3 1 Configuration of the remote controller eseeesseseeeseeeeeeee 52 4 3 2 Setting up Tasking environment rrrnnrrnrnnnrerrnnnrrrrnrenvnnerennnnrrnnnnsrennnnsne 57 4 3 3 Programming of the Remote Controller cccccccccsseeeeeeeeeeeeeeeeeeeeeeeeens 58 4 4 Running the applications rarrrnrrrnnrrrarerarernnrrranrrnnrnnarnnanennernnannnnnennsennnsne 62 9 Riceel cge 63 Application Note 3 V 1 0 2005 04 Infineon AP32087 technologies MILE Quick Start Scope 1 Scope The goal of this document is to provide practical information on how to configure and program two TC1766 microcontrollers in order to establish a Mi
4. TELKA TCLEA Pin Selection C No pin as TELKA selected Use pin P20 as MLIO transmit channel clock output T CLEA Push Pull Open Drain Driver Mode Activate open drain function for P2 Driver of P2 0 Emergency Stop Emergency Output Value Enable emergency stop function for P2 0 Set P20 to high level in emergency case Tx Lines TREADYA TREADYA pin selection Use pin P2 1 Driver Mode Medium Driver O 7 Tx Lines TVALIDA TVALIDA pin selection Use pin P2 2 8 Tx Lines TDATAA TDATAA pin selection Use pin P2 3 Application Note 27 V 1 0 2005 04 yn Infineon technologies AP32087 MLI Quick Start Practical Implementation 9 Tx Lines Change Transmitter Ready Selector to TREADYA Enable output signal TCLK input signal TREADY output signal TVALIDA a Micro Link Serial Bus Interface 0 MLIO a ea 2 Module Clock Tx Lines Fix Lines Contral Tx Interrupts Fix Interrupts Memory SAN Interrupts Functio 4 Configure Alternate Port Functions TCLKA P2 0 TREAD YA P2 1 TCLEB none TREAD none Enable State Of Transmitter Signals After Initialization Enable output signal TOLK TCE Enable input signal TREAD TRE Enable output signal TVALIDB TWEE Enable output signal TVALIDD TVED 28 Application Note Polarity Of Transmitter Signals TVYALID A P2 2 TVALIDB
5. AP32087 MLI Quick Start Practical Implementation 28 C Compiler gt Allocation Disable Default near allocation TriCore X toolset Project Options yy H Processor E C Compiler El C Compiler i Preprocessing Default aQ allocation for objects below threshold D 5 Language Default al allocation for objects below threshold D Debug Information z Code Generation Optimization Be Allocation Warnings MISRA C Miscellaneous Assembler PCP Assembler Linker ErazsView Fra Options string Wic no tasking str Cho1 766b wc c83 w c Ax Wc g switch auto W c alignzl c D nline max incr235 inline mas sige210 Wco NO JA S PR BDIB INnclude silican bugzall tc1 766 Cancel Default Help p Application Note 41 V 1 0 2005 04 ee Infineon technologies AP32087 MLI Quick Start Practical Implementation 29 Linker gt Script file gt internal memory SPRAM Alloc select ON Type select ROM TriCore YX toolset Project Options MEN E x E Processor Internal Memory ope BPE Compier OFF ROM 16k OXAFFFCODD H Assembler ON RAM 8k xCO000000 H PCP Assembler DIN EAM BEK DD 0000000 Linker ON ROM 16k DD4000000 i Qutput Format ON PCPRAM Bk xF 0050000 El Script File ON PCPCODE 12k xF OO60000 z Special Areas Defines Stack Heap Internal Memory External Memory ha Sections 2 Output Sections i i Reserved
6. 10 include MLIO Config Remote h USER CODE END 4 3 3 5 Main Remote C Main function USER CODE BEGIN Main 9 int i uword volatile p p remote piped base for 1 0 1 lt 5 1 p Oxffff0000 i p p 1 while 1 USER CODE END Application Note 61 AP32087 MLI Quick Start Practical Implementation V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start Practical Implementation 4 4 Running the applications Once both programs below have been compiled successfully 2 distinct debugger sessions one for MC1 the other for MC2 can be started The two programs can now be downloaded to MC1 and MC2 The application in MC2 should be started first then the application of MC1 The following should be observed e The LED of the TriBoard of MC2 switches on e The values 0xaaaa0000 0xaaaa0001 0xaaaa0005 which are defined in the main function of the application of MC1 can be read on MC2 at the following memory locations 0xd000a000 0xd000a004 0xd000a014 e The values 0xffff0000 Oxffff0001 OxffffO005 which are defined in the main function of the application of MC2 can be read on MC1 at the following memory locations d0006000 0xd0006004 0xd0006014 Application Note 62 V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start Ready to use files 5 Ready to use files The files attached with this application note can directly be used to
7. Wic g switch auto W c alignz1 c D2 w c r inline mas ner 35 inline max size 1 wi c N8 PRUDDBIB Include slican bugzall te1 766 Cancel Default Help p Application Note 39 V 1 0 2005 04 Infineon technologies 27 C Compiler gt Optimization Select no optimization AP32087 MLI Quick Start Practical Implementation TriCore YX toolset Project Options yy AX Processor H C Compiler C Compiler es Preprocessing Language in Debug Information bs Code Generation Optimization Allocation Wamings MISRA E i Miscellaneous Assembler PCP Assembler Linker Cross iew Pro Application Note Optirnization Optimization leve Ho optimization Size speed trade off Eustam optimization Coalescer remove Unnecessary moves Common subexspressian elimination CSE Expression simplification Control flow optimization and code reordering Generic assembly optimizations Function inlining Instruction scheduler All addresses available for CSE evaluation hi arimunm size Increment inlining 35 Masimum size for functions to always inline 10 Options string W c na tasking sfr Etel 7bbb c c38 e Wyic g smltch auto w c aliqnz1 c DIU inline mas nor 35 inline mas sizez10 Wc NO J FRODDIR include silicon bug all tel 766 Cancel Default Help E 40 V 1 0 2005 04 ee Infineon technologies
8. add this code in the dedicated area between the two comments USER CODE BEGIN add code USER CODE BEGIN All the files containing this code are attached and can be used directly Comments are also included there 4 3 3 1 MLIO C void MLIO vinit void e End of the routine USER CODE BEGIN Init 3 MLIO RCR 0x00010000 USER CODE END void INTERRUPT MLIO INT1 MLIO_viSRN1 void USER CODE BEGIN SRN1 17 MLIO config remote n ready 7 while MLIO RISR amp MLIO RISR CFRI3 0 USER CODE END 4 3 3 2 MLIO Config Remote H Start of file define remote piped base 0xd0008000 define wait cf while MLIO ubTxCmdReady 0 define wait cf neg while MLIO ubTxCmdReady 0 define NOP asm nop Mn define wait states 10000 void MLIO startup procedure void void MLIO config remote n ready void Application Note 58 V 1 0 2005 04 technologies void wait int End of file 4 3 3 3 MLIO Config Remote C Start of File include MAIN Remote h uword volatile pel flag pe2 flag void MLIO config remote n ready void MLIO startup procedure MLIO vResetErrors MLIO RIER MLIO RIER 0x03ff0000 while MLIO RISR 0 MLIO SCR MLIO SCR MLIO SCR SMOD MLIO vSendCmdUser 0 wait cf neg Walt cr MLIO TIER MLI1 TIER 0x03FF0000 while MLIO TISR 0 j void MLIO startup procedure void int k 0 unsigned int line delay line
9. can autonomously write it to the given address In order to avoid write actions to safety critical address areas an access protection scheme has been added A read access to a pipe transfers a request to the MLI receiver on controller 2 If enabled the MLI executes the read operation autonomously and the requested data will be sent back to the MLI on controller 1 by the MLI transmitter on controller 2 to the MLI receiver of controller 1 When this information is available in the MLI module of Application Note 8 V 1 0 2005 04 Infineon AP32087 JE MLI Quick Start Introduction to the Micro Link Interface controller 1 an interrupt can be generated and the CPU or a DMA etc of controller 1 can read the requested data Controller 1 Controller 2 MLI Transmitter MLI Receiver BSx 1 0 BSx 1 0 31 BSx 0 A 8 Base Acer Oset Size Pipe x Veke 31 BSx 0 DEKT Pipe x Figure 5 Target address generation The kernel MLI includes an optimized mode to transfer data blocks Whenever the MLI transmitter detects that the new address and the previous one follow a predictable scheme it will send just the data reducing this way the number of transferred bits If the complete autonomous feature set of MLI connection is enabled data transfers between two participants can take place without any CPU action for data handling The transmitting MLI stores the write access to its pipes does the complete encodin
10. further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Infineon AP32087 technologies 2 MLI Quick Start Table of Contents Table of Contents Page 1 gt 0 8 0 fM EORQ 4 2 Introduction to the Micro Link Interface rrnrrrnrnnrrnrnnnrervnnrrerrnnnrrnnnernvnnnnen 5 3 How to set up an MLI connection rrrrareranennnrrrnrnrannrnnennernnnnnnnnennsennnnnn 10 3 1 t MMMETC M 10 3 2 Funchonal GOESCIIDTON P RR ERROR TERES 11 3 2 1 vitai o 11 3 2 2 Read and Write operations
11. run the application described in this document The attached zip file contains especially the following files Folder MLI local Local dav DAVE file options opt project option file for Tasking v2 2 Main Local h Main Local c MLIO h MLIO c MLIO Config Local h MLIO Config Local c TC1766Regs h Folder MLI Remote Remote dav DAVE file options opt project option file for Tasking v2 2 Main Remote h Main Remote c MLIO h MLIO c MLIO Config Remote h MLIO Config Remote c I1O c JO h TC1766Regs h Application Note 63 V 1 0 2005 04 http www infineon com Published by Infineon Technologies AG
12. source DMA_MLIOSRC1 SRPN 2 in this example This pipe will be used by MC2 to tell MC1 that it is ready for communication The MC1 sends then four copy base address frames in order to configure the remote window of MC2 Once this is done it sends a command frame pipe 3 code 0 in this case to the remote controller and stands by until the MC2 sends a command frame on pipe 3 Application Note 12 V 1 0 2005 04 technologies AP32087 MLI Quick Start How to set up an MLI connection Crash action Crash action Crash action Send a dummy Command Frame on Pipe Y Read TSTATR RDC Write TCR MDP TSTATR RDC 1 Y Sends command frame on Pipe 1 to set RCR DPE TCR MDP 3 Y Sends dummy Command Frame with parity error on pipe 0 Parity error detected Sends dummy Command Frame with no parity error on pipe 0 Parity error detected Figure 7 Parity Error Signaling Procedure PESP Application Note V 1 0 2005 04 Infineon technologies AP32087 MLI Quick Start How to set up an MLI connection PESP Y Enable Interrupt on pipe 3 Y Send Base Address Frames on all pipes Y Send Command Frame on pipe 3 Y Stand By no Command Frame o
13. up procedures described below MC2 is also used briefly as local controller and MC1 as remote The initialization procedures are divided into 3 steps First step MC1 initiates the start up procedures and stands by Second step getting MC2 ready for communication Third step getting MC1 ready for communication 3 2 1 1 Start up procedure first step During this step MC1 first configures both local transmitter MC1 and remote receiver MC2 so that the parity error signaling is performed correctly MC1 also configures the base address of the remote window and initiates some start up procedures in MC2 A flow chart describing step 1 is depicted Fig 8 First the local controller MC1 has to configure its transmitter and the remote receiver of MC2 so that parity error signaling is performed correctly This is performed according to the set up procedure described in the User s Manual For the sake of 1 User s Manual Peripheral Units V0 2 Dec 2004 section 21 1 9 Application Note 11 V 1 0 2005 04 Infineon AP32087 technologies MILE Quick Start How to set up an MLI connection clarity in order to avoid mismatch between this specific procedure and the rest of the procedures described here which are also start up procedures the set up procedure described in the User s Manual will be referred as parity error start up procedure or PESP PESP A flow chart describing the PESP is depicted Fig 7 MC
14. wait_rf while MLIO ubTxAllPendingReadReady 0 define wait_rf neg while MLIO ubTxAllPendingReadReady 0 Application Note 46 V 1 0 2005 04 AP32087 MLI Quick Start Practical Implementation technologies define NOP asm nop n define wait states 10000 void MLIO config local n standby void void MLIO startup procedure void void Initiate Transmission void void wait int i End of file 4 2 3 3 MLIO Config Local C Start of file include MAIN Local h extern uword volatile MLI Remote Ready uword volatile pel flag pe2 flag void MLIO config local n standby void MLIO startup procedure MLIO RIER 0x00000020 DMA MLIOSRC1 0x00004002 DMA MLIOSRC1 0x00001002 MLIO vSendBaseAddr 0 remote pipeO base 12 wait bf neg wait bf MLIO vSendBaseAddr 1 remote pipel base 12 wait bf neg wait bf MLIO vSendBaseAddr 2 remote pipe2 base 12 wait bf neg wait bf MLIO vSendBaseAddr 3 remote pipe3 base 12 wait bf neg wait bf MLIO vSendCmdUser 0 wait cf neg wait cf Application Note 47 V 1 0 2005 04 AP32087 MLI Quick Start Practical Implementation technologies void Initiate Transmission void MLIO TCR MLIO TCR amp MLIO TCR NO MLIO vResetErrors MLIO TIER MLIO TIER 0x03FF0000 while MLIO TISR 0 MLIO RIER MLIO RIER 0x03FF0000 while MLIO RISR 0 MLIO RIER 0x00000021 DMA MLIOSRCO 0x000040
15. 01 DMA MLIOSRCO Ox00001 001 MLI Remote Ready 0x00000001 void MLIO startup procedure void int k 0 unsigned int line delay line delay 0 pel_flag 0 pe2_flag 0x00000001 MLIO TCR MLIO TCR RTY MLIO vResetCommunication MLIO vSendCmdInt 0 MLIO SCR MLIO SCR CCV0 wait wait states MLIO vResetCommunication line delay MLIO ubGetDelay 41 if line delay lt O0xC MLIO vSetDelay line delay else NOP MLIO vSendCmdDelay line delay 3 MLIO SCR MLIO SCR CCV1 wait wait states MLIO SCR MLIO SCR CTPE MLIO SCR CNAE while MLIO TSTATR amp MLIO TSTATR NAE amp MLIO TSTATR amp MLIO TSTATR PE 0 MLIO vParityErrorMode Application Note 48 V 1 0 2005 04 AP32087 MLI Quick Start Practical Implementation technologies MLIO vSendCmdInt 0 MLIO SCR MLIO SCR CCV0 wait wait states pel flag MLIO TSTATR amp MLIO TSTATR PE it pel flag s0 NOP MLIO vParityNormalMode MLIO SCR MLIO SCR CTPE MLIO SCR CNAE while MLIO TSTATR amp MLIO TSTATR NAE amp MLIO TSTATR amp MLIO TSTATR PE 120 MLIO vSendCmdInt 0 MLIO SCR MLIO SCR CCV0 wait wait states pe2 flag MLIO TSTATR amp MLIO TSTATR PE MLIO TSTATR amp MLIO TSTATR NAE if 4pe2 tlag 0 NOP void wait int i int j for j 0 j lt i j NOP j End of file Application Note 49 V 1 0 2005 04 AP32087 MLI Quick Start Practical Im
16. 1 sends a dummy frame to MC2 in this case a command frame on pipe 0 It waits for the transfer to complete and then measures how many cycles have elapsed between the beginning of the transfer and the moment when the signal Ready toggles from Low to High The measurement is done by reading the bit field MLIO TSTATR RDC This value represents the overall loop delay as defined in the PESP description In the case of this example the value RDC 1 is written to bit field MLIO TCR MDP MC1 then sends a command frame on pipe 1 to write on the remote controller bit field MLIO RCR DPE In the case of this example MLIO RCR DPE is chosen to be MLIO TCR MDP 2 As defined in the user s manual these settings need to be tested First a dummy frame with parity error is sent by setting bit MLIO TCR TP to 1 and the software checks if the error is detected by the transmitter by checking bit MLIO TSTATR PE If not special actions must be taken and the start up procedure must be restarted from the beginning If an error is correctly detected then MC1 sends a dummy frame with no parity error The software checks if no error occurs by checking bits MLIO TSTATR PE and MLIO TSTATR NAE If an error is detected special actions must be taken and the start up procedure must be restarted from the beginning If not this finishes PESP End of step 1 Once the PESP is correctly executed MC1 enables interrupts on received command frames on pipe 3 interrupt
17. Application Note V 1 0 April 2005 AP3208 TC1766 Micro Link Interface Quick Start Microcontrollers Never stop thinking TC1766 Revision History 2005 04 V 1 0 Previous Version Page Subjects major changes since last revision Controller Area Network CAN License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com Edition 2005 04 Published by Infineon Technologies AG 81726 Munchen Germany Infineon Technologies AG 2006 All Rights Reserved LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND INCLUDING WITHOUT LIMITATION WARRANTIES OF NON INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE Information For
18. Boards is depicted Fig 11 Application Note 21 V 1 0 2005 04 Infineon er A technologies MLI Quick Start Practical Implementation Figure 11 Hardware connection overview Note Make sure that the following resistances 0 Ohm are removed from both TriBoards R531 R532 R533 R534 R535 and R536 please refer to TriBoard manual Application Note 22 V 1 0 2005 04 y Infineon AP32087 technologies s MLI Quick Start Practical Implementation 4 2 Setting up MC1 All the operations below shall be performed on the PC connected to MC1 4 2 1 Configuration of the local controller The local controller MC1 can be configured using DAVE v2 1 Open a new project for TC1766 Project settings 1 General Settings Rename the Main Source File into Main Local c Rename the Main Header File into Main Local h Select Tasking 2 0 amp Project Settings o X A ota General System Clock Interrupt System PER System Pad Driver Startup Configuration Motes Controller Type Type Max system clock en MHz Main Source File Hain Header File EEE File name MAIN Local File name MAIN Localh Compiler Settings C GNU C Tasking 1 5 Application Note 23 V 1 0 2005 04 y Infineon technologies AP32087 MLI Quick Start Practical Implementation System Clock Change external clock frequency to 15 MHz Change input divider PDIV to 2 Chan
19. I interface supports different clock domains for the transmitter or the receiver module As the MLI interface is able to act as bus master on the system bus of the controller itself it autonomously acts like a DMA controller and Application Note 6 V 1 0 2005 04 Infineon AP32087 technologies s MLI Quick Start Introduction to the Micro Link Interface therefore might work in parallel to the CPU of the system As a result the MLI significantly reduces the CPU load for data transfer tasks Remote control of peripherals located in the other controller is offered as a feature by this behavior so calculation power or peripherals located in different sub controller systems might be shared via MLI MLI connection is not necessarily restricted to a controller to controller connection Other products such as smart companion devices ASSP can also be connected easily The advantage of these devices is their extended voltage range so that they could incorporate e g a 5V analog sensor interface or other analog and digital data preconditioning circuits smart companion Controller 1 Figure 3 Smart companion device with MLI connection General Description of MLI The communication between two participants is based on a pipe structure A pipe may be seen as a logical connection between a transmitter and a receiver In each MLI module 4 independent pipes ar
20. Map File Libraries z Optimization gt Warnings Options string Miscellaneous format elt o pepz 1 elf d pcp2 Tel Ctc1 766b E Crossviem Pro gilicon bug alltel 766 vl M VI mcfklM ors L FRODDIR Nb PROTECTED WI OCLTAT Cancel Default Help E Application Note 42 V 1 0 2005 04 une Infineon technologies AP32087 MLI Quick Start Practical Implementation 30 Linker gt Script file gt Sections Space select linear Sections type text main Group select order Copy select NO Alloc select intmem Location select spram TriCore toolset Project Options Processor C Compiler Space Sections J Gun Copy Aloe Location C Compiler near test main ordered NO intmem spram Assembler PCP Assembler Linker T Output Format Script File B Special Areas z Defines Stack Heap Internal Memory 2 External Memory Sections 2 Output Sections gt Reserved Map File T Libraries Z Optimization gt Warnings Options string Miscellaneous format elf a pcpZ T elt d pepz 1 Ctc1 766b H Crozsviem Pro gilicon bug all tel 766 lt AAI mefklkdobrsl L S PRODDIR Mib M PROTECTED WwI OCLTAT Cancel Default Help s Application Note 43 V 1 0 2005 04 Infineon technologies AP32087 MLI Quick Start Practical Implementation 31 CrossView Pro Execution environment Execution
21. YALID AWE BYSLID inverted passive level 1 RYP RREADYA inverted passive level 1 RAPA RREADYB inverted passive level 1 ARPE RREADYD inverted passive level 1 RRPD Application Note 29 V 1 0 2005 04 Infineon technologies AP32087 MLI Quick Start Practical Implementation 11 Control Select MLI Transmitter ON Disable optimized frames ig Micro Link Serial Bus Interface 0 MLIO EE X eta Module Clock Tx Lines Rx Lines Control Tx Interrupts Fix Interrupts Memory SAN Interrupts Functior 4 kj Maximum Non Acknowledge Errors M MAE Timeout error flag is set after I error Maximum Delay for Parity Error MD P fo clock periode h l arimum Parity Errors for Transmitter MPE Parit erar flag is set after I error hi aximum Parity Errors for Receiver MPE Each parity error will generate the interrupt Type OF Parity TF Force the MLI receiver to produce parity errors Data Line Level In Idle State DMT DATA line level in idle state is D DATA line level in idle state is 1 Break Out Enable BEN r Reception of break pulse command generates pulse in BREAKOUT line Application Note 30 V 1 0 2005 04 Infineon technologies AP32087 MLI Quick Start Practical Implementation 12 Rx Interrupt Normal Frame Received Interrupt Enable an interrupt is gene
22. cro Link Interface MLI link and execute basic read and write transfers Some programming examples are included with this application note The code has been created using DAvE 2 1 and Tasking 2 2r1 It is strongly recommended to uses those versions when using the code delivered with this application note Two TriBoards for TC1766 and two standard PCs are needed to run the application described in this document Please note that the code given in this application note shall be used for demonstration purpose only It aims at giving an example on how to build a functional MLI link It is not optimized nor is its robustness guaranteed Section 2 gives an overview of the MLI interface Readers already familiar with the MLI may want to skip this section Section 3 gives explanations on how to set up a basic MLI link between two microcontrollers from a functional point of view In section 4 step by step explanations are given in order to build physically the connection This includes hardware set up initialization of the microcontrollers programming of the start up procedures and of basic read and write operations In section 5 some explanations are given on the ready to use files provided with this application note UA compatible DavE DIP file is included in the package containing this document For more information about Tasking Tool Chain and the latest patches please visit www tasking com Application Note 4 V 1 0 2005 04 o7 Infin
23. delay 0 pel_flag 0 pe2_flag 0x00000001 MLIO TCR MLIO TCR RTY MLIO vResetCommunication MLIO vSendCmdInt 0 MLIO SCR MLIO SCR CCVO0 wait wait states Application Note 59 AP32087 MLI Quick Start Practical Implementation V 1 0 2005 04 AP32087 MLI Quick Start Practical Implementation technologies MLIO vResetCommunication line delay MLIO ubGetDelay 1 if line delay lt 0x MLIO vSetDelay line delay else NOP MLIO vSendCmdDelay line delay 3 MLIO SCR MLIO SCR CCV1 wait wait states MLIO SCR MLIO SCR CTPE MLIO SCR CNAE while MLIO TSTATR amp MLIO TSTATR NAE amp MLIO TSTATR amp MLIO TSTATR PE ten MLIO vParityErrorMode MLIO vSendCmdInt 0 MLIO SCR MLIO SCR CCV0 wait wait states pel flag MLIO TSTATR amp MLIO TSTATR PE if pel flag 0 NOP MLIO vParityNormalMode MLIO SCR MLIO SCR CTPE MLIO SCR CNAE while MLIO TSTATR amp MLIO TSTATR NAE amp MLIO TSTATR amp MLIO TSTATR PE 120 MLIO vSendCmdInt 0 MLIO SCR MLIO SCR CCVO0 wait wait states pe2 flag MLIO TSTATR amp MLIO TSTATR PE MLIO TSTATR amp MLIO TSTATR NAE if pe2 flag 0 NOP void wait int i int j for j 0 j lt i j wait until MDCstops NOP End of file Application Note 60 V 1 0 2005 04 Infineon technologies 4 3 3 4 Main Remote H At the end of the file USER CODE BEGIN MAIN Header
24. e available The pipes point to address areas in the receiver starting at programmable base addresses The MLI transmitter only sends a short offset relative to the base address instead of the full 32 bit address Each pipe Application Note 7 V 1 0 2005 04 Infineon AP32087 technologies MLI Quick Start Introduction to the Micro Link Interface defines a buffer in the receiver s address map defined by the base address the offset and the length of the offset Controller 1 Controller 2 MLI Transmitter MLI Receiver Size 31 BS0 1 0 Buffer 0 BSC 2 sent Jo 1o gt pipe 0 31 BS1 1 0 BS Buffer 1 2 Base Addr 1 o omm pipe 1 Base Addresses from the four pipes 31 BS2 1 0 sem o o pipe 2 31 BS3 1 0 meas Jo 06 pipe 3 Figure 4 MLI pipe structure In addition to the offset its bit width defines the buffer size the MLI transmitter sends a reference to the pipe in use When the MLI receiver obtains this data it elaborates the absolute target address by simply concatenating the received offset to the base address of the selected pipe A data write access to a pipe in controller 1 leads to an automatic transfer from the MLI transmitter to the MLI receiver on controller 2 This transfer includes the written data the offset address and the pipe number The received information becomes available in the MLI receiver The CPU of controller 2 can read it under SW control or the MLI
25. ect Enter a path for example CX MLI TC1766 QuickStart MLI Local and a name for example MLI Local Click OK 21 Add DAvE generated files to the project Right click once on the project MLI Local window on the left Select Add existing files Add TC1766REGS H MAIN LOCAL H MAIN LOCAL C MLIO H MLIO C Click OK 22 Add two new files to the projects Right click once on the project MLI Local window on the left Select Add new files Add MLIO Config Local c Click OK Repeat the previous steps and add MLIO Config Local h Application Note 36 V 1 0 2005 04 y Infineon technologies AP32087 MLI Quick Start Practical Implementation Setting up the project options 23 Open the project option dialog box Project gt Project Options 24 Processor Processor Definition Select TC1766 TriCore YX toolset Project Options i X Processor Definition Target processor i The FRU and MMU options are only relevant for user defined processors possible FPU MMU in the selected CPU will be supported regardless El Processor c Processor Definition ie Bypasses E Startup H Bus Configuration C Compiler E Compiler the state of the grayed checkbox Assembler FRU present PCP Assembler MMU present Linker rozsiew Pro Cancel Default Help Application Note 37 V 1 0 2005 04 Infineon technologies
26. environment Select TriBoard TC1766 with SRAM TriCore X toolset Project Options PCP2 1 PJT BEES x E Processor Execution Environment B C Compiler Execution environment H Compiler l B SUM DAS TCP IP Settings host port localhost 23 E PCP Assembler E Linker Target configuration file cfal Er Lross view Pro Browse 22 Execution Environment E Simulator Options string tefg infineon trboard tel 755b das cfg D tepiplocalhost 23 C tcl 766b i load application goto main true sync_on_halt on a 100 b 500 s 26 Cancel Default Help t Application Note 44 V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start Practical Implementation 4 2 3 Programming of the Local controller In addition to the code automatically generated by DAVE the following code shall be added It is recommended to add this code in the dedicated area between the two comments USER CODE BEGIN add code USER CODE END All the files containing this code are attached and can be used directly Comments are also included there 4 2 3 1 MLIO C Section Imported Global Variables USER CODE BEGIN MLIO General 6 extern uword volatile target read store USER CODE END void MLIO vinit void e End of the routine USER CODE BEGIN Init 3 MLIO RCK 0x00010000 USER CODE END void INTERRUPT MLIO INTO MLIO_viSRNO void e Beginning of the
27. eon AP32087 eeeebset MILI Quick Start Introduction to the Micro Link Interface 2 Introduction to the Micro Link Interface MLI is a serial high speed link up to 40 Mbaud for TC1766 which is based on a principle similar to the standard serial protocol Due to its symmetrical structure it supports full duplex transmission It only requires four signal lines in each data direction downstream transmit and upstream receive For each data transfer direction there is one clock line CLK one data line DATA and two handshake lines READY VALID One MLI transmitter might be connected to up to four scalable MLI receivers sharing the same Data and Clock line An individual addressing of receivers is done by independent sets of handshake lines MLI Transmit MLI Receiver VALID xy DATA xy Port Ctri Port Ctr CLK yx MLI Receiver MLI Transmit VALID yx DATA yx Figure 1 MLI Transmitter Receiver connection The MLI interface has been developed to meet the following application targets e Data and program exchanging without intervention of CPU or PCP between microcontrollers of the AUDO NG family The MLI is connected to the system bus and can do data move operations independently from the CPU s e The internal architecture of the block allows the communication between controllers in different clock domains e The read mode enables the desired data to be read from the other controller e Resources sharing between c
28. g and transfers the complete move action to the receiving MLI There the address and the data are reconstructed and the write action is executed on the system bus As a result a MLI module can be seen as a fully autonomous module transferring data moves between the system buses of independent controllers Application Note 9 V 1 0 2005 04 Infineon technologies 3 How to set up an MLI connection AP32087 MLI Quick Start How to set up an MLI connection 3 1 Goal The goal of this application note is to set up an MLI link between two microcontrollers MC1 and MC2 as depicted in Fig 6 Memory Mem Transmitter Reciever emory Write TREADYA RREADYA gt Transfer Remote window TVALIDA RVALIDA Mundos TCLKA RCLKA cm Pin 1 0 Read TDATAA RDATAA H Register P1_OUT Reciever Transmitter Memory Write RDATAA TDATAA s i RVALIDA TVALIDA 4 RCLKA TCLKA PEA MC1 RREADYA TREADYA MC2 Figure 6 MLI link between two controllers Both microcontrollers run at 80 MHz CPU frequency The MLI links runs at 10 Mbaud s Specifically the following actions will be performed via the MLI link MC1 writes to the register P1 OUT of MC2 The effect is that the LED on the TriBoard of MC2 is turned on MC1 w
29. ge VCOSEL to 400MHz 500 MHz Change feedback divider NDIV to 64 Change output divider KDIV to 6 Project Settings E b X General System Clock Interrupt System FCF System Pad Driver Startup Configuration Notes External Clock Frequency External clack frequen is gt m PLL Bypass operation fcpu fasc MHz pin BYPASS 1 Input divider PDIV C t5 fosc 2 7 500 MHz Voltage Controlled Oscillator VCO VCO Bypass mode YCOBYF VED range WEOSECT 400 MHz 500 MHz gt Feedback divider MEA ren EA CO output Reno fco fasc P 64 480 000 MHz ere MA 480 000 Output Divider Output divider KOK o B 80 000 MHz dz 80 00000000 The ratio tepu teys is 271 System Clock an OO000000 MHz f The ratio fopu fevete 1 1 Application Note 24 V 1 0 2005 04 Infineon technologies AP32087 MLI Quick Start Practical Implementation 3 Interrupt system Enable the Interrupt System globally ig Project Settings E x fra General System Clock Interrupt System PCP System Pad Driver Startup Configuration Notes CPU Global Interrupt Enable Number of Arbitration Cycles CARBC YC Four arbitration cycles max 255 interrupt sources Three arbitration cycles max 63 interrupt sources C Two arbitration cycles max 15 interrupt sources One arbitration cycle max 3 i
30. hnologies no AP32087 MLI Quick Start How to set up an MLI connection Stand By Command Frame on pipe 3 received Enable Optimized Frames Y Clear all errors Y Clear receive and transmit interrupt flags Y Enable Interrupts on received normal frames Y Set Remote Ready flag Y End of MC1 start up proc Figure 10 Application Note Start up procedure MC1 step 3 18 V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start How to set up an MLI connection 3 2 2 Read and Write operations At this point all errors or interrupt flags generated in both controllers by the start up procedure have been cleared The parity error signaling has been checked and is functional and the remote window of MC2 has been configured Besides both controllers are now ready to communicate with each other MC1 can now start read and write operations The write and read operations are triggered by the fact the flag MLI Remote Ready is set to 1 Write operation 1 The local controller MC1 sends a Write frame on pipe 3 It writes the value 0x00000000 to register P1 OUT of MC2 The effect is that the LED on the remote TriBoard is switched on as soon as the transfer is completed Write operation 2 The local controller MC1 sends 6 Write frames on pipe 1 in a row In a row means here tha
31. ller MC2 can be configured using DAvE v2 1 Most of the actions below are similar to the ones described in section 4 2 Open a new project for TC1766 Project settings 1 General Settings Rename the Main Source File into Main Remote c Rename the Main Header File into Main Remote h Select Tasking 2 0 2 System Clock Change external clock frequency to 15 MHz Change input divider PDIV to 2 Change VCOSEL to 400MHz 500 MHz Change feedback divider NDIV to 64 Change output divider KDIV to 6 3 Interrupt system Enable the Interrupt System globally MLIO 4 Module clock Change Divider Mode Control to Select normal divider mode Change Required Module Clock to 20MHz 5 Tx Lines Configure Alternate Port Function to TCLKA P2 0 TREADYA P2 1 TVALIDA P2 2 TDATA P2 3 Select medium driver Change Transmitter Ready Selector to TREADYA Enable output signal TCLK input signal TREADY output signal TVALIDA Application Note 52 V 1 0 2005 04 Infineon AP32087 technologies MILE Quick Start Practical Implementation 6 Rx Lines Configure Alternate Port Function to RCLKA 2 4 RREADYA P2 5 RVALIDA P2 6 RDATA P2 7 Change Receiver Data Selector to RDATAA Change Receiver Clock Selector to RCLKA Change Receiver Ready Selector to RREADYA Change Receiver Valid Selector to RVALIDA Enable input signal RCLK and RVALID 7 Control Select MLI Transmit
32. me MLIG c tion Library Part 1 Nnictien Library Part 2 MLID vEnableSignal MLIO vFesetCommunication LID vDisableSignal MLIO vAesetenos 000 LIO vTransmitterOn MLIO ubTsCmdReady LIO vTransmitterO tf MLIO ubTsDataReady LID vRecerverdode amp uto MLIQ_ubT sBase4ddrReady LIO_vRecerverModeListen MLIQ_ vSendCrnidl nt LID vParityMormaltiode MLIO vSendCmdDelay LIO vParityErrorMode MLIO vSendCmdD ummy LIQ_ubGetDelay MLIQ_ vSendCmdblodeListen MLIQ_vSetDelay MLIO vSendCmdtlode amp uto MLID ubTsAckError MLIO vSendCmdBreskPuse 00 MLIO ubTsParityError MLIO v SendCmallzer MLIO ubFisParityE ror MLIO vSendBaseAddr 17 Saving and generating code Now the configuration of the Local controller is finished Create a new folder on your hard drive for example CAMLI TC1766 QuickStart MLI_ Local Y and save there DAVE project for example local dav Code can now be generated with DAvE The following files will be created TC1766REGS H MAIN LOCAL H MAIN LOCAL C MLIO H MLIO C Application Note 35 V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start Practical Implementation 4 2 2 Setting up Tasking environment 18 Start Tasking v2 2 r1 19 Create a new project space File gt New Project Space Enter a path for example CMMLI TC1766 QuickStart and a name for example TC1766 20 Create a new project Right click once on the project space TC 1766 window on the left Select Add New Proj
33. n pipe 3 received yes Go to Step 3 Figure 8 Start up procedure MC1 step 1 Application Note 14 V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start How to set up an MLI connection 3 2 1 2 Start up procedure second step This step is needed for two reasons First it enables MC2 to know when to clear all its interrupt flags and its error flags generated by the frames received in the first step Secondly it lets MC1 know when MC2 is ready for transmission A flow chart describing step 2 is depicted Fig 9 When MC2 receives a command frame on pipe 3 an interrupt routine is started During this routine MC2 will operate as the local controller First a PESP as described in the User s Manual and similar to the one described in step one is performed It configures the transmitter of MC2 and the receiver of MC1 for parity error signaling Once the PESP is correctly executed MC2 clears all transmit and receive errors bits MLIO TRSTAR CNAE MLIO TRSTAR CTPE MLIO RCR PE It also clears all the interrupt flags on the receive side by writing to register MLIO RIER It then enables the automatic move engine by setting bit MLIO RCR MOD MC2 sends a command frame to MC1 on pipe 3 in order to indicate it is ready for transmission Finally it clears transmit interrupt flags by writing to register MLIO TIER Application Note 15 V 1 0 2005 04 e Infineon technologies
34. none TOAT AA P2 3 TDATAB none I TDATA inverted TDF TELE inverted passive level 1 TCF TREADY inverted passive level ITRF T ALIDA inverted passive level 1 TYPA T ALIDB inverted passive level 1 T PB TVALIDD inverted passive level 1 T PD V 1 0 2005 04 yn Infineon technologies AP32087 MLI Quick Start Practical Implementation 10 Rx Lines Configure Alternate Port Function to RCLKA P2 4 RREADYA P2 5 RVALIDA P2 6 RDATA P2 7 Change Receiver Data Selector to RDATAA Change Receiver Clock Selector to RCLKA Change Receiver Ready Selector to RREADYA Change Receiver Valid Selector to RVALIDA Enable input signals RCLK and RVALID T Micro Link Serial Bus Interface 0 MLIO Ix a eta 2 Module Clock Ts Lines Fix Lines Control Tx Interrupts Rix Interrupts Memory SAN Interrupts Functior Configure Alternate Port Functions FACLEA P2 4 FREAD YA P2 5 J RVALIDA P26 7 RDATAA P2 7 JF HCLKB none HREALD TB none AVALIDE none ADAT AB none Receiver Data Selector ADS Receiver Valid Selector AWS Te oa Receiver Clock Selector ACS Receiver Ready Selector ARS _ FCLKA gt lt RREADYA P Enable State Of Receiver Signals After Initialization Polarity Of Receiver Signals M RDATA inverted RDP nable input signal RCLE RCE nable input signal R
35. nterrupt sources Number of Clocks per Arbitration Cycle CONECTC Two clocks per arbitration cycle One clock per arbitration cycle for low frequency Application Note 25 V 1 0 2005 04 e Infineon technologies AP32087 MLI Quick Start Practical Implementation MLIO 4 Module clock Change Divider Mode Control to Select normal divider mode Change Required Module Clock to 20 MHz a Micro Link Serial Bus Interface 0 MLIO ea 2 Module Clock Tx Lines Hx Lines Control Tx Interrupts Fix Interrupts Memory SAN Interrupts Functiar 4 kj Mote The OMA clock is also used for the MLI modules as a common clock that can be individually divided for the ML modules Divider Mode Control CM Disable Clock Control Pp modde clock TT EMEN becomes inactive after initialization Enable Hardware Clock Control Select fractional divider made C a DI es hn gen Module Clack Control Required module clock MHz C 20 000 Real module clack MHz 20 000 Minimal module clock KHz 78 1 25 Percentage of deviation 0 000 Maximal module clack MHz 80 000 Step value STEP 0x3FC Application Note 26 V 1 0 2005 04 yn Infineon AP32087 technologies o MLI Quick Start Practical Implementation 5 Tx Lines TCLKA TCLKA pin selection Use pin P2 0 Driver Mode Medium Driver a Configure Alternate Pin Functions E Eu x Il
36. ontrollers Application Note 5 V 1 0 2005 04 Infineon AP32087 technologies 0 M Quick Start Introduction to the Micro Link Interface e Capability of triggering interrupts in the receiving controller by sending a command Controller 1 Controller 2 CPU CPU rq A Peripher X K gt Peripheral X K AK Peripheral Y Peripheral Z 4 C 9 NZ a System Bus System Bus Figure 2 MLI in a microcontroller MLI lI O pins are CMOS compliant allowing microcontrollers from the AUDO NG family to be mounted closely together on the same PCB This target doesn t necessarily require cost extensive LVDS drivers for better EMC behavior Usage of CMOS MLI I O drivers instead of LVDS drivers also has a beneficial impact on the absolute current consumption and requires less interface pins Nevertheless there might be applications where LVDS drivers are useful for MLI signals e g for electronic valve train where the ECU for the valves and the ECU for engine control are separated and need to communicate via longer MLI cable up to more than 1 meter might occur As a different cable length for the connection leads to a changing loop delay for transmitted or received messages the timing of the MLI handshake signals can be adapted via programming during the startup procedure The internal architecture of the ML
37. ory SAN Interrupts Furctior 4 Service Request Enable SHE Enable service request Normal frame received nable service request 1 LC STATES Bienne few Enable service request 2 no events enabled Enable service request 3 no events enabled Application Note 33 V 1 0 2005 04 Infineon technologies 15 Interrupts Drag and drop SRNO to CPU Level Drag and drop SRN1 to CPU Level2 T Micro Link Serial Bus Interface 0 MLIO da AP32087 MLI Quick Start Practical Implementation Ix Module Clock Tx Lines Aix Lines Control Tx Interrupts Fix Interrupts Memory SAN Interrupts Functio 4 kj CPU Interrupt max 255 PCP Interrupt max 255 MLIO SAN 1 Level 1 MLIOSRAN O Nr Level n on interrupting Mote To change the level and the group of an interrupt source click on it drag it to its new position and drop it To set an interrupt source to the non interrupting level Level 0 click on it drag it to the Level 0 list and drap it Application Note 34 V 1 0 2005 04 Infineon technologies AP32087 MLI Quick Start Practical Implementation 16 Functions Select all T Micro Link Serial Bus Interface 0 MLIO x a ta Hx Lines Control Tx Interrupts Fix Interrupts Memory SA Interrupts Functions Functions Paramete kj izlesin Function Source File j nuo vini File na
38. ote 56 V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start Practical Implementation MLIO H MLIO C 10 C O H 4 3 2 Setting up Tasking environment 16 Start Tasking v2 2 r1 17 Create a new project space File gt New Project Space Enter a path for example CMMLI TC1766 QuickStart and a name for example TC1766 18 Create a new project Right click once on the project space TC1766 window on the left Select Add New project Enter a path for example C MLI TC1766 QuickStartMLI Remote and a name for example MLI Remote Click OK 19 Add DAvE generated files to the project Right click once on the project MLI Remote window on the left Select Add existing files Add TC1766REGS H MAIN Remote H MAIN Remote C MLIO H MLIO C IO C IO H Click OK 20 Add two new files to the projects Right click once on the project MLI Remote window on the left Select Add new files Add MLIO Config Remote c Click OK Repeat the previous steps and add MLIO Config Remote h Setting up the project options 21 Repeat the same steps as for the Local controller Application Note 57 V 1 0 2005 04 Infineon technologies AP32087 MLI Quick Start Practical Implementation 4 3 3 Programming of the Remote controller In addition to the code automatically generated by DAVE the following code shall be added It is recommended to
39. plementation technologies 4 2 3 4 Main Local H At the end of the file USER CODE BEGIN MAIN Header 10 include MLIO Config Local h USER CODE END 4 2 3 5 Main Local C Section Global Variables USER CODE BEGIN MAIN General 7 uword volatile target write target read target read store uword volatile MLI Remote Ready USER CODE END Main function Tf USER CODE BEGIN Main 9 int i uword volatile xread DMA MLIOSRCO 0x00000001 DMA MLIOSRC1 0x00000002 MLI Remote Ready 0 MLIO contig local nm standby while MLI_ Remote Ready 0 target write MLIO SWIN3 0xd00 target write 0x0000000 wait df neg wait df target write MLIO SWIN1 for 1 0 1 lt 5 1 target write 0xaaaa0000 4i Application Note 50 V 1 0 2005 04 technologies wait df neg wait df target write target write l j target read MLIO SWINO target read store 0xd0006000 for i 0 i lt 5 i xread target_read wait_rf_neg wait_rf target_read target_read 1 target read store target_read_store 1 while 1 USER CODE END Application Note 51 AP32087 MLI Quick Start Practical Implementation V 1 0 2005 04 Infineon AP32087 technologies MILE Quick Start Practical Implementation 4 3 Setting up MC2 All the operations below shall be performed on the PC connected to MC2 4 3 1 Configuration of the remote controller The remote contro
40. r Interrupt Pointer BRAIP Memory Protection or Parity Error Interrupt Pointer MPPEIP Service Request Made 0 Service Request Node D Application Note 31 V 1 0 2005 04 y Infineon technologies AP32087 MLI Quick Start Practical Implementation 13 Memory Enable all address ranges Micro Link Serial Bus Interface 0 MLIO ES X je da gt Module Clock Tx Lines Hx Lines Control Tx Interrupts Rx Interrupts Memory SRAN Interrupts Functior t abled Address Ranges AENx Size of OVARAM Address Slice SIZET 512 Bytes OVRAM Address Slice SLICET OgE S000000 OxE 80001 FF w SCU incl WOT MEMCHE PPP LIO ModuleTr Windows LI Madule Tr Windows ogram Flash Space Data Flash Space Emulation Device Size of OM RAM Address Slice SIZE 2 DMI Image Pil Image 512 Bytes CPS CPU SFRsPGRs PML Flash Regs DMU BCU DMI PMI PECL LFI S SI lt 1 I XI I SI X I XI XI lt 1 XI I I XI DMI RAM Address Slice SLICE 2 OgE 8400000 OxES4001 FF m M LMU Image incl OVRAM Application Note 32 V 1 0 2005 04 e Infineon technologies AP32087 MLI Quick Start Practical Implementation 14 SRN Enable Service Request 0 and 1 a Micro Link Serial Bus Interface 0 MLIO Ix ea Module Clock Ta Lines Hu Lines Control Tx Interrupts Ri Interrupts Mem
41. rated each time a normal frame is correctly received Normal Frame Received Interrupt Pointer select Service Request Node 0 Command Frame Received Interrupt Enable enable interrupts for pipe 3 Command Frame Received Interrupt Pointer select Service Request Node 1 Micro Link Serial Bus Interface 0 MLIO E X Madule Clock Tx Lines Aix Lines Contra Ts Interrupts Fix Interrupts Memory SAN Interrupts Function 4 Normal Frame Recerved Interrupt Enable NFRIE Command Frame Received Interrupt Enable CFRIEx The int t tion is disabled M ips Pipe interrupt enabled interrupt command interrupt is generated each time a Formal frame is correctly received Pipe 1 interrupt enabled delay command Pipe 2 interrupt enabled made command Pine 3 interrupt enabled user command An interrupt is generated each time a normal frame is correctly received that is not automatically handled ame Eaesied ntemast Eanter IHFRIP Noma eFecered ag Fa N Service Request Node 0 v gt a 7 Interrupt Command Enable ICE Memory Protection or Parity Error Interrupt Enable MPPIE Interupt generation enabled r n interrupt is generated each time a memory protection error occurs Discarded Read Answer Interrupt Enable DRAAIE l l r n interrupt is generated each time the parity Interupt generation enabled error counter in receiver side has reached 0 Discarded Read Answe
42. rites six data words to the address space of MC2 address 0xd000a000 0xd000a004 0xd000a014 MC1 reads some 6 words in the memory space of MC2 address 0xd0008000 Oxd0008004 0xd0008014 and stores them in its own memory space at address 0xd0006000 Oxd0006004 0xd0006014 respectively Application Note 10 V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start How to set up an MLI connection 3 2 Functional description This section describes from a functional point of view the different steps necessary to create the MLI link The principles developed here are general and can be used in most of the cases However practical implementations may differ from the description below depending on the specific applications requirements 3 2 1 Start up When the two controllers are powered on and their respective MLI is statically initialized module enabled pin assignment etc some procedures are needed to initiate a transmission At the beginning all MLI Service Request Nodes SRN of MC1 are disabled They will be enabled later on This solution has been chosen here in order to avoid unwanted servicing of routines initiated by dummy frames On the contrary for MC2 at the beginning one SRN is enabled interrupt on received command frames on pipe 3 All other SRN are disabled MC1 is used as local controller during the transmission MC2 as the remote controller Please note that during the start
43. routine USER CODE BEGIN SRNO 2 uword volatile p1 uword volatile dummy USER CODE END Application Note 45 V 1 0 2005 04 AP32087 MLI Quick Start Practical Implementation technologies e Case 3 USER CODE BEGIN SRNO 133 pl target read store DL MOTO BDATAR dummy pl USER CODE END e End of the routine USER CODE BEGIN SRNO 13 while MLIO RISR amp MLIO RISR NFRI USER CODE END e void INTERRUPT MLIO INT1 MLIO viSRN1 void USER CODE BEGIN SRN1 17 Initiate Transmission while MLIO RISR amp MLIO RISR CFRI3 0 USER CODE END 4 2 3 2 MLIO Config Local H Start of file Hdefine Hdefine Hdefine Hdefine remote pipeO base remote pipel base remote pipe2 base remote pipe3 base 0xe8408000 0xe840a000 0xe840c000 Oxf0000d00 define MLIO ubTxAllDataReady ubyte MLIO TRSTATR amp MLIO TRSTATR DVO MLIO TRSTATR DV1 MLIO TRSTATR DV2 MLIO TRSTATR DV3 0 define MLIO ubTxAllPendingReadReady ubyte MLIO TRSTATR amp MLIO TRSTATR RPO MLIO TRSTATR RP1 MLIO TRSTATR RP2 MLIO TRSTATR RP3 0 define wait bf while MLIO ubTxBaseAddrReady 0 define wait bf neg while MLIO ubTxBaseAddrReady 0 define wait cf while MLIO ubTxCmdReady 0 define wait cf neg while MLIO ubTxCmdReady 0 define wait df while MLIO ubTxAllDataReady 0 define wait df neg while MLIO ubTxAllDataReady 0 define
44. t it sends frame 0 waits for bit MLIO TRSTATR DV1 to be set to 1 and then to get cleared then it sends frame 1 etc It writes the words 0xaaaa0000 0xaaaa0001 0xaaaa0005 respectively to the following memory locations in the memory space of MC2 0xd000a000 0xd000a004 0xd000a014 Note Actually the write operation is not performed directly on the DMI memory but on ist image That is why in the code the base address of pipe 1 is configured to be 0xe8408000 and not 0xd0008000 On the remote controller side the transfer is handled automatically by the move engine Read operation The local controller MC1 sends 6 Read frames on pipe 0 in a row In a row means here that it sends frame 0 waits for bit MLIO TRSTATR RPO to be set to 1 and then to get cleared then it sends frame 1 etc It reads the words OxffffOO00 OxffffO001 OxffffO005 respectively to the following memory locations in the memory space of MC2 0xd0008000 0xd0008004 0xd0008014 On the remote controller side since the move engine is activated it will automatically pass the wanted data to its transmit buffer as soon as a read frame is received The remote controller sends then the corresponding answer frames to MC2 Application Note 19 V 1 0 2005 04 Infineon AP32087 ale MLI Quick Start How to set up an MLI connection When MC1 receives the answer frame an interrupt request is generated and the CPU services the routine The data word of ans
45. ter ON Disable optimized frames 8 Rx Interrupt Command Frame Received Interrupt Enable enable interrupts for pipe 3 Command Frame Received Interrupt Pointer select Service Request Node 1 Application Note 53 V 1 0 2005 04 y Infineon technologies AP32087 MLI Quick Start Practical Implementation 9 Memory Enable all address ranges Size of DMI RAM Address Slice 64 kBytes In ota 2 Size of OVA AM Address Slice SIZE 512 Bytes DV RAM Address Slice SLICET OE S000000 OxE SOOO FF g MLIO ModulesTr Windows MLIT Module Tr Windows Data Flash Space mulation Device Size of OM RAM Address Slice SIZE 2 B4 kButes Z DMI RAM Address Slice SLICE 2 OE 8400000 OE SAUFFFF P5 CPU SFRs PGRs PMU Flash Regs OMU DECU OMI PMI PECL LFI LMU Image incl OVRAM Application Note 54 V 1 0 2005 04 Infineon AP32087 technologies 2 ML Quick Start Practical Implementation 10 SRN Enable Service Request 1 11 Interrupts Drag and drop SRN1 to CPU Level2 12 Functions Select all Application Note 55 V 1 0 2005 04 Infineon technologies AP32087 MLI Quick Start Practical Implementation PORT 13 Ports gt Configure Port 1 Use P1 0 as general IO General Description Out Output value high a Configure Port 1 cH E r x m ea Part 1 Input Charac
46. teristic Output Characteristic Parameters Notes Functionality 3 EF chon Push Pull Open Drain Output Value ze P1 0 as general IO C In ot Open drain d Use P1 1 as general 10 In But Open drain high Use P1 2 as general ID In Gut Open drain high Use P1 3 as general IU In Gut Open drain high Use P1 4 as general ID In Dut Open drain IT high Use P1 5 as general IU In Gut Open drain P high Use P1 6 as general ID In Gut Open drain high UseF1 as general ID In Gut Open drain high In Gut Open drain Thigh In Dut Open drain high In Gut Open drain high In Gut Open drain high In Gut Open drain high In Gut Open drain high In Gut Open drain high ERN ol m m Use P1 8 as general IU Use P1 9 as general I0 Use P1 10 as general 10 Use P1 11 as general 10 Use P1 12 as general 10 Use F1 13 as general 10 Use P1 14 as general 10 Ko gt i a o o SY o o o o 14 Functions Select IO_vlnit 15 Saving and generating code Now the configuration of the Remote controller is finished Create a new folder on your hard drive for example C MLI TC1766 QuickStartMLI Remote and save there DAVE project for example MLI Remote dav Code can now be generated with DAvE The following files will be created MAIN REMOTE H MAIN REMOTE C Application N
47. wer frame 0 Oxffff0000 is written to 0xd0006000 the data word of frame 1 Oxffff0001 to 0xd0006004 etc Application Note 20 V 1 0 2005 04 Infineon AP32087 technologies 2 MLI Quick Start Practical Implementation 4 Practical Implementation The following items are necessary to realize the set up described below e wo TriBoard Evaluation board for TC 1766 e Two TriBoard Logic Analyzer Extension Board e Tasking Tool Chain TriCore Compiler Assembler Linker Locator CrossView Pro Debugger version 2 2r1 Note The Quick Start may not work with a demo version of the Tasking Tool Chain Please contact Tasking a full featured version for demo purpose time limited For more information please visit www tasking com e DAVE the Digital Application Engineer version 2 1 Please install the DIP file for TC 1766 included in the package containing this document e 2standard PC with Windows NT XP or Windows 2000 4 1 Hardware connection The required MLI connection between the two controllers is described in Table 1 Local Controller Remote Controller Signa Pin Signa Pin TCLKA P24 TREADYA P2 5 TDATAA P2 7 RCLKA P2 0 RREADYA P2 1 RDATAA P2 3 Table 1 Physical MLI connections between remote and local controllers For example pin P2 0 of the local controller is connected to pin P2 4 of the remote controller etc All the other pins will not be used and thus may remain open The connection between the two Tri
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