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Simulator Configuration Guide for Synopsys Models

1. Using MemPro Models with VCS To use MemPro models with VCS follow this procedure VCS links external PLI routines during compilation of your design You do not need to rebuild the VCS simulator 1 To use the MemPro C testbench add the following line to your local copy of slm_pli tab Syour_task_name call your_fn_name 2 If you are using MemPro testbench interface commands in your design perform step 2a or step 2b If you are not using HDL or C testbenches skip to step 3 a If you are using Verilog testbench calls add the following line to your Verilog testbench include mempro_pkg v b If you are using the MemPro C testbench add the following line to your C testbench code include mempro_c_tb h July 31 2001 Synopsys Inc 51 Chapter 2 Using VCS with Synopsys Models Simulator Configuration Guide For more information on using the MemPro testbench interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual 3 Invoke VCS to compile and simulate your design HP UX If you are not using the MemPro C testbench ves Verilog_modules MemPro_model_files LMC_HOME 1ib hp700 1ib slm_pli o P LMC_HOME sim pli src slm_pli tab incdir SLMC_HOME sim pli sre RI LDFLAGS Wl a default ldld lc lm 1BSD If you are using the MemPro C testbench ves Verilog_modules MemPro_model_files
2. Warning Unknown signal level on DSACKO_PIN Assuming DSACKO_PIN is 1 SmartModel Instance 1 2751 U102 MC68030 20 sheet1 of schematic at time 200 0 Trace Returning read data to PCL program 0 O00000BFE 1 00000000 2 00000000 3 00000000 4 00000000 5 00000000 6 00000000 7 00000000 00000000 SmartModel Instance 1 2751 U102 MC68030 20 sheetl of schematic at time 1750 0 AJ 1 Trace PCL Bus Cmd Read Control 06 Addr 00000004 Bytes 4 SmartModel Instance 1 2751 U102 MC68030 20 sheet1 of schematic at time 1750 0 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Using SmartModel Windows with QuickSim II SmartModel Windows is a SmartModel Library feature that can be used for more efficient system level verification and debugging by allowing you to view window elements during simulation runs for microprocessor PLD memory and peripheral models Window elements that can be viewed include registers pointers states or latches for example depending on the part being modeled This section provides information about how to interact with SmartModel Windows using QuickSim IT SmartModel Windows can be used to e Review window element values and set breakpoints e Single step through simulations e Change window element values before proceeding with a simulation e Trace instruction execution e Re
3. gsub prev_signal n split prev_signal array_c a zA z0 9_ y 20 n if y gt 0 for i 1 i lt 20 n i prev_signal prev_signal if 0 amp amp pin_type 3 ending printf prev_signal data_type is_it_a_vector No updown prev_signal current_signal prev_test current_test prev_dir direction prev_number current_number END printf n printf end device n n printf architecture LMSI of device is n printis attribute FOREIGN of ILMSI printf begin n printf end IMSI n n July 31 2001 Synopsys Inc prev_dir std_logic data_type ending n architecture is Synopsys LMSI n 139 Chapter 6 Using Scirocco with Synopsys Models Simulator Configuration Guide 140 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 7 Using VSS with Synopsys Models 7 Using VSS with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels MemPro models and hardware models with VSS The procedures are organized into the following major sections e Setting Environment Variables on page 141 e Using SmartModels with VSS on page 143 e Using FlexModels with VSS on page 145 e Using MemPro Models with VSS on page 148 e Using Hardware Models with VSS on page 150 Setting Environment Variables First set the basic environment v
4. REPORT OBJECT Not supported by SmartModels Use the SIGNAL INSTANCE command to query a model and report its status REREAD MODELFILE Reloads any of the configuration files used by a model including memory image JEDEC MCF SCF and PCL command files Configuration files are only re read if the simulation has changed the configuration RESET STATE Causes all models to reinitialize their states to the original time zero power up conditions RESTORE STATE Restores all of the model s internal states as part of the operation SAVE STATE Records all of the model s internal states as part of the operation WRITE MODELFILE Causes a model to dump its memory image to a file SWIFT Command Channel You can use the SWIFT command channel to pass commands directly through to SmartModels Use the QuickSim II SIGNAL INSTANCE command to access the command channel To issue a command for selected instances use the following mw Signal instance swift_model p command_name arguments July 31 2001 Synopsys Inc 231 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide To issue a command for a session use the following Signal instance swift_session p command_name arguments For more information on using the SWIFT command channel refer to The SWIFT Command Channel on page 21 Checking the Model s Status Use the QuickSim II SIGNAL INSTANCE
5. vsim design Using MemPro Models with MTI VHDL To use MemPro models with MTI VHDL follow this procedure 1 Perform one of these platform dependent steps a On NT platforms verify that the shared library is visible from the current working directory The path to the shared library LMC_HOME lib pent lib was set at MemPro installation b On UNIX and Linux platforms append the MemPro shared library location to the library search path environment variable setting On Solaris or Linux workstations setenv LD LIBRARY PATH LMC_HOME 1lib plat 1ib LD_LIBRARY_PATH where plat is sun4Solaris or x86_linux respectively On HP UX workstations setenv SHLIB PATH LMC_HOME 1ib hp700 1ib LD_LIBRARY_PATH 2 Create a local copy of modelsim ini in the current working directory and a local logical library named slm_lib vlib slm lib vmap slm lib slm lib 3 Open the modelsim ini file in a text editor uncomment the line that enables VHDL 1993 and uncomment the lines that enable SWIFT uncomment only the lines that correspond to the platform you are using Turn on VHDL 1993 as the default Normally is off VHDL93 1 ModelSim s interface to Logic Modeling s SmartModel SWIFT software libsm MODEL_TECH libsm s l ModelSim s interface to Logic Modeling s SmartModel SWIFT software Windows NT libsm MODEL_TECH 1libsm d1l Logic Modeling s SmartModel SWIFT software HP 9000 Series 700 libswift SL
6. usertask 0 slm_inertial_checktf 0 slm_inertial 0 Sslm_inertial true nd section 2 7 2 You will need to edit the veriuser c file to pick up the LMTV header files as follows a After include vxl_veriuser h add include ccl_I1mtv_include h b After add user entries here add include ccl_I1mtv_include_code h 3 Invoke the Cadence PLI Wizard utility The instructions that follow summarize the procedure found in the Cadence PLI Wizard User Guide but are not intended to replace the Cadence procedure The PLI Wizard utility will present a series of forms for you to fill out After you have completed each window as described in the following steps click the Next button at the bottom to invoke the next window 62 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models 4 10 11 In the Select Config Session Name and Directory form o Enter the name of your session file in the Config Session Name field o Enter the path to the session file in the Config Session Directory field Select Verilog XL as the Verilog simulator Select Stand Alone as the Verilog target Select PLI 1 0 Application and SWIFT Interface as your components Specify your LMC_HOME path in the Root Path field next to SWIFT Interface Select Static Linking for the PLI Application Linking Mode Select Existing VERIUSER source ob
7. 142 Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you use for snpslmd based authorizations 5 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv LM DIR hardware_model_install_path sms 1m_dir setenv LM LIB hardware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly Depending on your platform set your load library variable to point to the platform specific directory in LMC_HOME as shown in the following examples Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD_LIBRARY_PATH LMC_HOME 1ib x86_linux 1ib LD_LIBRARY_PATH AIX setenv LIBPATH LMC_HOME 1lib ibmrs 1lib LIBPATH HP UX setenv SHLIB_ PATH LMC_HOME 1ib hp700 1lib SHLIB_ PATH NT Make sure that 7LMC_HOME lib pcnt lib is in the Path user variable Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 7 Using VSS with Synopsys Models Using SmartModels with VSS To use SmartModels with VSS follow this procedure 1 To create SmartModel VHDL templates check to
8. Parameters also called attributes 18 DelayRange 24 FlexCFile 25 FlexModelld 24 FlexModelSre 25 FlexTimingMode 24 Timing Version 24 PCLFile property 224 pin names overwriting by genInterface 186 PIN property 224 240 Pin symbols 222 pin_map file 241 example 242 PIN_NAME mapping 240 PIN_NAME property 225 240 pin_name_ovr statement 186 PIN_NO property 225 Pins mapping 241 mapping conditional 243 PINTYPE property 224 PKG property 225 PLI communication with Simulator Function Interface SFI 85 dynamic linking with FlexModels 115 dynamic linking with Hardware models dynamic linking with MemPro models 108 118 dynamic linking with SmartModels 61 113 static linking with FlexModels 106 117 static linking with MemPro models 108 119 static linking with SmartModels 114 PLIWizard 62 82 104 106 108 Properties COMP 225 editing 233 JEDECFile 224 MemoryFile 223 July 31 2001 Index MODEL 224 247 PCLFile 224 PIN 224 240 PIN_NAME 225 240 PIN_NO 225 PINTYPE 224 PKG 225 REF 225 SCFFile 224 SWIFT 239 SWIFT_TEMPLATE 224 symbol 222 symbol required for simulation 224 Timing Version 223 propogation command 259 Q QuickSim IT changing timing 233 command interaction 231 command line switches 230 component interface 247 constraint checking 233 constraint switch 230 default timing 229 installing SWIFT interface 219 interactive commands 231 managing user trees 219 model symbol propert
9. SLMC_HOME 1ib hp700 1ib slm_pli o P local_slm_pli tab your_testbench c CFLAGS ISLMC HOME include incdir SLMC_HOME sim pli sre RI LDFLAGS Wl a default ldld lc lm 1BSD Solaris If you are not using the MemPro C testbench ves Verilog_modules MemPro_model_files LMC_HOME 1lib sun4Solaris 1ib slm_pli o P LMC_HOME sim pli src slm_pli tab incdir SLMC_HOME sim pli sre RI If you are using the MemPro C testbench ves Verilog_modules MemPro_model_files LMC_HOME 1lib sun4Solaris 1ib slm_pli o P local_slm_pli tab your_testbench c CFLAGS ISLMC_HOME include incdir SLMC_HOME sim pli sre RI Example ves tbench v mydram v mysram v LMC_HOME 1lib sun4Solaris 1ib slm_pli o P LMC_HOME sim pli src slm_pli tab incdir SLMC_HOME sim pli sre RI 52 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models NT If you are not using the MemPro C testbench gt ves Verilog_modules MemPro_model_files LMC_HOME 1ib pent 1ib slm_pli_ves 1lib p LMC_HOME sim pli sre slm_pli tab incdir LMC_HOME sim pli sre RI If you are using the MemPro C testbench gt ves Verilog_modules MemPro_model_files LMC_HOME 1lib pent 1ib slm_pli_vces lib P local_sim_pli tab your_testbench c CFLAGS I LMC_HOME include incdir LMC_HOME sim pli srce RI Attention If you are using VCS 5 0 or earlier add the Zp4 switch to your
10. Switches help July 31 2001 Pathname to the FlexModel you want to set up Prints help information Synopsys Inc 25 Chapter 1 Using Synopsys Models with Simulators Simulator Configuration Guide d ir path Copies the contents of the FlexModel s versioned src verilog and src vhd directories into path src verilog and path src vhdl The directory specified by path must already exist Examples When run without the dir switch flexm_setup just prints the name of the versioned directory of the selected model s source files Lists name of versioned directory containing source files o flexm setup mpc860_fx When run with the dir switch pointing to your working directory flexm_setup copies over all the versioned package files you need to that working directory Creates copy in flexmodel directory of model source files mkdir workdir flexm setup dir workdir mpc860_fx Instantiating FlexModels with Direct C Control Direct C Control is how you use FlexModels on SWIFT simulators with standard FlexModel integrations With Direct C Control all model commands come from an external compiled C program that you point to using the FlexCFile SWIFT parameter For users familiar with Synopsys Hardware Verification models this is similar to setting the PCLFile parameter to point to the location of a compiled PCL program In addition you must also set the FlexModelld parameter which does not have a defaul
11. Using Hardware Models with Leapfrog on page 201 Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel FlexModel and MemPro model installation tree as follows setenv LMC HOME path_to_models_installation July 31 2001 Synopsys Inc 195 Chapter 10 Using Leapfrog with Synopsys Models Simulator Configuration Guide 2 Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example setenv LM LICENSE FILE path_to_product_authorization_file setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_file You can put license keys for multiple products for example SmartModels and hardware models into the same authorization file If you need to keep separate authorization files for different products use a colon separated list UNIX or semicolon separated list NT to specify the search path in your variable setting 8 Caution 196 Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you
12. e For SmartModel Windows to work with the SAVE STATE and RESTORE STATE commands the window elements defined at SAVE STATE must exactly match those defined at the start of the current simulation session 238 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models e The REREAD MODELFILE command does not redefine window elements for SmartCircuit models Using this command to redefine window elements after simulation startup disables the window elements Custom Symbols Synopsys provides symbols representing default package pinouts for SmartModels However you may need to create custom symbols for some of the following reasons e To conform to internal drafting requirements e To make a symbol match a component s pinout e To match external drafting specifications for example military specifications Users who choose to create custom symbols as an alternative to using the symbols provided can e Modify a SmartModel Symbol Start with the SmartModel symbol and modify it to match your drafting requirements The value of the user PIN property can now be changed without corrupting the value of the compiled PIN property e Create a New Symbol Create the symbol with your pin values figure out the corresponding pin names used by the model and change the user pin values to those names To create custom symbols follow these steps 1 Provide required SWIFT properties on the symbol 2
13. incdir SLMC_HOME sim pli sre SLMC_HOME 1ib hp700 1ib slm_pli o P SLMC_HOME sim pli src slm_pli tab 1 ves_sim log Mupdate RI 48 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models lmc swift LDFLGS a shared lm lc a archive Script for Running FlexModel Examples in VCS On page 50 is a Perl script Figure 1 that you can use to run VCS on a FlexModel examples testbench You can use this script on any installed FlexModel because each one comes with a prebuilt testbench example that shows how to use the model commands and all the Verilog wrapper and task definition files that you need This script runs on HP UX Solaris and NT To invoke VCS on a FlexModel and its example testbench follow these steps 1 N Oo Use the Acrobat Reader s text selection tool to select the script shown in Figure 1 and copy the contents to a local file named run_flex_examples_in_vcs pl Save the file and change the permissions so that the file is executable chmod 775 in UNIX If you are on NT you also need to copy the following line to a file named run_flex_examples_in_vcs cmd and put it in your working directory SLMC_HOME lib pcent lib sl_perl exe run_flex_example_in_vcs pl On NT you invoke this cmd wrapper which subinvokes the Perl script Invoke the script as shown in the following examples UNIX o run flex examples_in_vcs pl model_fx
14. on page 69 Verilog XL Design Flow Figure 2 shows the Verilog XL design flow with two paths You choose one path or the other based on the task at hand e LMTV SWIFT SmartModel mode recommended for new designs e LMTV Historic SmartModel mode recommended for older designs that use the Verilog XL specific SmartModel Library You can create a design file design v textually with an HDL description or graphically using Concept FlexModel users should also use the appropriate Verilog wrapper file from the model_fx examples verilog directory This file is copied to your working directory using the flexm_setup tool For information on flexm_setup refer to flexm_setup Command Reference on page 25 When Verilog XL simulates the design it references either the SWIFT SmartModel mode model v files or the Historic SmartModel mode model v files You must specify one of these directories when you invoke Verilog XL A design cannot reference both directories 66 Synopsys Inc July 31 2001 Simulator Configuration Guide SWIFT SmartModel Mode SWIFT model files ges alle verilog v file Figure 2 Verilog XL Design Flow Preparing to Use Verilog XL Chapter 3 Using Verilog XL with Synopsys Models Historic SmartModel Mode Historic modelv files design file verilog v file Before you use Verilog XL in either mode make sure that your executable search path points to the Verilog XL executa
15. defparam bank1 model_id bank1 memoryfil Le bank1 message_ vel tbench bank1 dram dat SLM_XHANDLING SLM_TIMING SLM_WARNING bankl default_data 64 hxxx MemPro VHDL Instantiation Ul dram1x64 generic map model_id memoryfil gt e gt message_l vel gt default_data gt port map a dq ras lcas ucas we oe 32 10 dram dat SLM_TIMING SLM _XHANDLING SLM WARNING XXXX adrw dataw rasw lcasw ucasw wew oew Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 1 Using Synopsys Models with Simulators Controlling MemPro Model Messages MemPro model messages are grouped into categories that you can individually enable or disable for each model instance Several message categories are applicable to all models additional categories may be defined for specific models or model types The general categories are Fatal Fatal messages are always enabled When a fatal error is detected the simulation stops immediately after reporting the message For example referencing an unknown MemPro model instance handle causes a fatal error Error Error messages apply to incorrect situations from which the model is able to recover allowing simulation to continue For example MemPro generates an error message when the model receives a command that would put it in an illegal state Warning Warnin
16. lm Copyright 1988 1996 Synopsys Incorporated 17 Aug 1998 R3 4a Default Modeler is venkat IM Utilities Menu 1 Create Logic Models 2 Verify Logic Models 3 Perform Maintenance 4 Run Diagnostics 5 Show Modeler Configuration h Help q Quit selection 2 Select item 5 Show Modeler Configuration selection 5 Modeler Configuration 1 Show Modelers 2 Show Logic Models 3 Show Users 4 Show Versions 5 Show Model Users 6 Show Licenses h Help q Quit selection July 31 2001 Synopsys Inc 181 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide 3 Select item 6 Show Licenses selection 6 Modeler Name ALL venkat License Server set to 5300 hal venkat Licenses Used No licenses being used on the modeler venkat Total Licenses Present in the License Fil Feature licenses Version Exp Date MSFAULTYes3 400 31 Dec 1999 MSCBSYes 3 400 31 Dec 1999 MS3400100 3 400 31 Dec 1999 MS3200100 3 400 31 Dec 1999 Using Hardware Models with Cycle Based Simulators ModelAccess for Cyclone allows you to prepare your hardware models for use in a Cyclone cycle based simulation This section describes how to use hardware models in a Cyclone simulation We begin with an overview of hardware modeling in the Cyclone environment and then provide instructions for using genInterface Timing Delays Synopsys hardware m
17. mymem use CONFIGURATION SLM MODELS mymem_behav END FOR END FOR END mymem_a 6 Add LIBRARY and USE statements to your testbench LIBRARY SLM_LIB USE SLM_LIB mempro_pkg all This also provides access to MemPro testbench commands For more information on using the MemPro testbench interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual 7 Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 For information on message levels and message level constants refer to Controlling MemPro Model Messages on page 33 8 Compile your design as shown in the following example o ncelab w work design_name 9 Invoke NC VHDL on your design as shown in the following example o nesim design_name 212 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 11 Using NC VHDL with Synopsys Models Using Hardware Models with NC VHDL To use hardware models with NC VHDL follow this procedure For the latest information on supported features refer to the Cadence documentation 1 Make sure NC VHDL is set up properly and all required environment variables are set as explained in Setting Environment Variables on page 205 2 Add the hardware model install tree to your path variable as shown in the following
18. s Shell Software as source files 1 Creates a symbol for the model and registers it with the component interface 2 Creates compiles and registers a technology File which contains the timing description of the model in a Mentor Graphics proprietary format The user can choose to use either this technology file or the Shell Software timing files during simulation For more information refer to Timing Shell Selection on page 258 3 Registers the functional description with the component interface The Im_model command as illustrated in Figure 18 calls a number of other utilities The reg_model utility and Technology Compiler tc are Mentor Graphics utilities for more information about these utilities refer to your Mentor Graphics documentation For more information on the tmg_to_ts converter refer to Im_model Command Reference on page 264 For more information on the Im_model utility refer to tmg_to_ts Command Reference on page 267 July 31 2001 Synopsys Inc 249 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Shell Software ASIC1 MDL ASIC1 DEV ASIC1 DCL PGA PKG ASIC1 TCK PGA160 ADP ASIC1 TRK ASIC1 0PT ASIC1 DLY ASIC1 NAM ASIC1 FRC technology ts Technology Compiler tc reg_model Technology Description Functional Graphical Des
19. typ and max DelayRange All SmartModels Specifies a propagation delay range for a particular instance of a SmartModel MemoryFile SmartModels with internal memory such as RAMs ROMs and processors and controllers that have on chip RAM or ROM Specifies a memory image file MIF to load for a particular instance of a SmartModel JEDECFile JEDEC based PAL and PLD models Specifies a JEDEC file to load for a particular instance of a SmartModel SCFFile FPGAs and CPLDs Specifies a model command file MCF to load for a particular instance of a SmartModel July 31 2001 Synopsys Inc Chapter 1 Using Synopsys Models with Simulators Simulator Configuration Guide Table 1 SmartModel SWIFT Parameters Continued Parameter Name Used By Description PCLFile Processor models for Specifies a compiled PCL example microprocessors program file to load for a and microcontrollers particular instance of a these are usually hardware SmartModel verification models gt Note To determine the required configuration file i e MemoryFile JEDECFile SCFFile or PCLFile for any SmartModel refer to the model s datasheet Instantiating SmartModels If you are using an HDL based simulator generate a model wrapper file model v or model vhd using your simulator vendor s procedure Use the model wrapper to instantiate the model in
20. For instructions on accessing SOLV IT refer to Getting Help on page 14 36 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models 2 Using VCS with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels MemPro models and hardware models with VCS These procedures are centered on VCS v5 1 but contain notes about other versions of VCS as well The procedures are organized into the following major sections Setting Environment Variables on page 38 Using SmartModels with VCS on page 39 Using FlexModels with VCS on page 42 Using MemPro Models with VCS on page 51 Using Hardware Models with VCS on page 55 Hint This chapter includes a script that you can use to run any FlexModel examples testbench with minimal setup required You can cut and paste the script right out of this PDF file Refer to Script for Running FlexModel Examples in VCS on page 49 July 31 2001 Synopsys Inc 37 Chapter 2 Using VCS with Synopsys Models Simulator Configuration Guide Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel FlexModel and MemPro model installation tre
21. Generates a list of the timing files loaded at simulation startup This is equivalent to setting the command channel command TraceTimeFile to ON The default is not to list the timing files For more information about the command channel refer to the SmartModel Library User s Manual Synopsys Inc 279 Appendix B LMTV Command Reference Simulator Configuration Guide lmoldstr Ilmoldtrans Imresstr 280 Maps all SmartModel Library signal strengths to strong for all output events that have resistive strength The default is to use resistive strength to reflect the true state of the SWIFT pin Use this switch if you have a design that was created in the Verilog XL specific SmartModel Library environment and you want simulation conditions to match the Verilog XL specific SmartModel Library Indicates that the historic style is to be used for transcribing messages The historic style message contains references only to timing version names and does not specify any time units The default is that messages contain references to both timing version names and model names Timing values are in nanoseconds ns Use this switch if you want to match the Verilog XL specific SmartModel Library simulation conditions Disables mapping of SmartModel Library signal strengths to strong strength even if a historic model model file vshell is detected Use this switch if you want your historic mode design to use true resistive
22. LMC_HOME 1lib sun4solaris 1ib vera_slm_pli o S VERA_HOME 1ib vlog libvlog_br a SVERA_HOME 1ib 1ibVERA a 4 Set the VERA_HOME variable to point to the location of your VERA installation directory setenv VERA_HOME path_to_VERA_installation 5 Set the SSI_LIB_FILES variable to point to the vera_local dl that you built in Step 3 setenv SSI_LIB FILES vera_local dl gt Note If you are using multiple dynamic libraries dl files use a colon separated list to specify the search path 6 Modify the simv build Modify the simv build by adding the following o P VERA_HOME lib vera_pli_dyn tab o VERA_HOME lib libSysSciTask a o the vshell file created in Step 2 gt Note For HP UX add LDFLAGS E For more information refer to the installation and setup chapter in the VERA System Verifier User Manual 7 Create a file for VERA to load at runtime This step assumes that the vro files are in the current working directory You need to create a file that looks like the following example The file name for this example file is files_to_load 1lstmodel vro swiftmodel vro flexmodel_pkg vro model_pkg vro testbench vro For more information refer to the documentation on vera_mload in the VERA System Verifier User Manual July 31 2001 Synopsys Inc 277 Appendix A Using VERA with FlexModels Simulator Configuration Guide 8 Run the simv executable Add the vera_mload swit
23. Maps an unknown input state to a logic zero state xl p pin_name Maps an unknown input state to a logic one state xz p pin_name Maps an unknown input state to a float state propagate Propagates unknowns through the hardware model nopropagate Turns off unknown propagation default default_ propagation Sets the number of additional sequences to be p number played to the instance when unknown propagation is enabled default 0 random_seed Sets the value of the seed for the random p seed sequence generator when unknown propagation is enabled default 0 Indeterminate is Maps an indeterminate strength i to a strong strength mapping strength s default iz Maps an indeterminate strength i to a high impedance strength z Test vector logvectors Turns on test vector logging logging p filename nologvectors Turns off test vector logging default July 31 2001 Synopsys Inc 257 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Table 32 Signal Instance Command Summary Continued Feature Command Description Timing tm p filename Turns on timing measurement returns the measurement actual measured delays to QuickSim II notm Turns off timing measurement uses the delay values specified in the Shell Software or in the technology file default Loop mode loop Turns on loop mode the modeling system repeatedly plays a pattern history to the physical device noloop Tu
24. Register the component 3 Map pin names to standard SWIFT pin names SWIFT Properties The following symbol properties are required to interface with a SWIFT model e model e TimingVersion e pin e pintype e swift_template Refer to Table 23 and Table 24 for information about other required symbol properties July 31 2001 Synopsys Inc 239 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Component Registration When creating new symbols you must add the SWIFT model to the component interface by registering the model with a type of SWIFT For example suppose you have created a new component called my_ttl00 and you want to use the SmartModel Library ttl0O binary as the simulation model You would register the ttl00 model as follows reg_model SMY_DIR my_comp_lib my_tt1l00 type SWIFT label my_label PIN_NAME Mapping The two methods for creating custom symbols described in Custom Symbols on page 239 cannot be used to map bus symbol pins to model pins You must use a pin_map file to accomplish this sort of custom symbol creation as explained in the following sections PIN Property A PIN property can have two distinct values in Design Architect as follows e Compiled pin value e User pin value The compiled pin value must be the same value that is used in the model When initially adding a pin to a symbol both these values are set to the specified value
25. strengths This switch only works with the SWIFT interface Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix B LMTV Command Reference LMTV Commands LMTV commands are predefined tasks that you place within your testbench or design LMTV commands all begin with an lm_ prefix Some of them have historic counterparts which begin with an lai_ prefix You can use any or all commands in either the SWIFT or the Historic SmartModel modes except for the lm_monitor_vec_map command which can be used only in SWIFT SmartModel mode gt Note The lai_ commands are provided to support older designs Therefore you do not have to convert lai_ commands to Im_ commands However when starting a new design it is best to use the 1m_ commands and not the lai_ commands Here is a list of the LMTV interface commands lm_command or lai_command on page 282 oN lm_dump_file Q or lai_dump_file on page 283 lm_help on page 284 Im_load_file or lai_load_file Q on page 285 lm_monitor_enable or lai_enable_monitor on page 286 lm_monitor_disable or lai_disable_monitor on page 286 lm_monitor_vec_map and lm_monitor_vec_unmap on page 288 lm_status or lai_status on page 290 July 31 2001 Synopsys Inc 281 Appendix B LMTV Command Reference Simulator Configuration Guide lm_command or lai_command These comma
26. 134 Using Hardware Models with Scirocco ss did dda eenedeeeieeeed anode ned 135 Scirocco Example with TILS299 Hardware Model 135 Scitpoco VOIES 428 54 seh eGe kes HiR GoD A eS ONS OR GROSS KW REDRESS amp 136 VHDL Model Generics with Scirocco ae idaskeesesewsi ee bedeneeeaws 136 Chapter 7 Using VSS with Synopsys Models sssssssssssssosssosssessosesoe 141 CIVervioW inc ene uses eeGe Lene bed coke Semel a ik e a a ea ERRE 141 Beene Environment Variables isisciosecs ertib Eiane i rEnREEE ERE EDA 141 Using SmartModels with VSS uisrenrneroenedrreutredmre nihair ute OSs 143 create_smartmodel_lib Command Reference nnunnnnannnnnn dense 144 Usame Fl xModels wih YSS ccrrsiiarierbereietki n ap Ek need cae ees 145 Usmge MemPro Models with VSS scrrrciecrisiocrsut radii Tupia dinna 148 July 31 2001 Synopsys Inc 5 Contents Simulator Configuration Guide Using Hardware Models with VSS ocaceeiveneecwieneee Vance sevice tans 150 VSS Example with TILS299 Hardware Model 20 55 150 NSS UNES nb 4 eeu cee as bnGhh fo oek oboe Hee NOESEN EREN 151 VHDL Model Generics With VSS ocicsrircssicsticipirabiidprii mi 151 Chapter 8 Using MTI VHDL with Synopsys Models cc cece ew cc cc ccccscees 155 CPE 56 8 EE E a kA FAS ee EAA RS 155 mete Environment Variables 255i coon se brea sd meee eee kO ee ROG oes 155 Using SmartModels with MTI VHDL 2syccoecdaesawsscuet ones aase seeees 1597 sm entity Command Reference
27. 2 Using VCS with Synopsys Models Simulator Configuration Guide One FlexModel on Solaris To use one FlexModel with VCS on Solaris invoke the simulator as shown in the following example VCS_HOME bin vcs LMC_HOME bin flexm setup model_fx examples verilog model_tst v LMC_HOME bin flexm setup model_fx examples verilog model v LMC_HOME bin flexm_setup model_fx examples verilog model_fx_ves v incdir SLMC_HOME sim pli sre incdir SLMC_HOME bin flexm_setup model_fx src verilog P LMC_HOME sim pli src slm_pli tab LMC_HOME 1ib sun4Solaris 1ib slm_pli o incdir SLMC_HOME sim pli sre 1 ves_sim log Mupdate RI lmc swift where model is the name of the FlexModel you are using 46 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models Table 10 lists each line in the invocation example above along with explanations for what each one does Table 9 VCS With One FlexModel On Solaris Model Explanation Line Reference Description SVCS_HOME bin vcs Path to the file that starts the VCS simulator LMC_HOME bin flexm_setup model_fx examples verilog model_tst v Specifies the path to the model testbench file IMC HOME bin flexm setup model_fx examples verilog model v Specifies the path to the model Verilog wrapper file IMC HOME bin flexm setup model_fx examples verilog model_fx ves v Specifi
28. Additional Synopsys documentation is available at this URL http www synopsys com products Im doc Datasheets for models are available using the Model Directory http www synopsys com products Im modelDir html Visit the online Support Center at this URL http www synopsys com support Im support html Synopsys Inc July 31 2001 Simulator Configuration Guide Preface This site gives you access to the following resources o SOLV IT the Synopsys automated problem resolution system o product specific FAQs frequently asked questions o lists of supported simulators and platforms o the ability to open a support help call o the ability to submit a delivery request for some product lines 3 If you still have questions you can call the Support Center North American customers Call the Synopsys Eaglei and Logic Modeling Products Support Center hotline at 1 800 445 1888 or 1 503 748 6920 from 6 30 AM to 5 PM Pacific Time Monday through Friday International customers Call your local sales office The Synopsys Website General information about Synopsys and its products is available at this URL http www synopsys com Synopsys Common Licensing SCL Document Set Synopsys common licensing SCL software is delivered on a CD that is separate from the tools that use this software to authorize their use The SCL documentation set includes the following publications which are located in root docs scl on the SCL CD and als
29. DATA C HEX Changing Program Flow by Setting Values You can use the SmartModel Windows feature to shorten large repetitive loops For example if a DMA controller has initiated a DMA transfer of 1 024 words to main memory you can view the transfer of the first couple of words before stopping the simulation By artificially setting the value of the DMA s transfer control register you can control which part of the transfer to view You can then view the last few words as they are transferred without having to wait for the entire process Be careful when inserting values into window elements especially when forcing data into program counters and instruction registers This SmartModel Windows feature is recommended only for users who completely understand the implications of what is being inserted into an element When forcing a value onto an element the FORCE command is always interpreted as if the CHARGED switch were present This means that the forced value vanishes when another event attempts to update the window element It is not possible to FIX or WIRE a forced value on a window element SmartModel Window Elements SmartModel Window elements for SmartCircuit models can be defined only at simulator startup This affects the way several QuickSim II commands interact with SmartCircuit models e The SAVE STATE and RESTORE STATE commands produce unpredictable effects if any SmartCircuit window elements are defined after saving the state
30. Information signal instance 263 Installation prerequisites hardware model 178 Instantiation FlexModel VHDL 40 43 61 80 103 105 113 116 130 147 162 Instruction tracing execution 236 Intel NT using MTI Verilog 115 using MTI VHDL 160 Interfaces hardware model component 249 Synopsys Inc 295 Index J JEDECFile property 224 K Keys do not match error message 189 L LAL LIB environment variable 77 LAI_OBJ environment variable 77 Id linker 191 LD_LIBRARY_PATH environment variable 38 39 60 61 102 112 125 142 156 172 189 196 206 218 LDFLAGS E switch 277 Leapfrog with FlexModels 173 198 with hardware models 201 with MemPro 198 210 Lespfrog utilities with hardware models 202 IfsmLibPck file 197 Libraries CLI functions 146 FMI 198 210 model_pkg ine 42 115 model_pkg o 27 model_pkg vhd 161 model_pkg vr 274 model_pkg vrh 274 model_user_pkg vhd 161 slm_lib 129 147 162 210 slm_pli o 27 slm_pli_dyn 82 106 108 117 119 SmartModel Library menus 220 SmartModel LMTV SWIFT 76 SmartModel Verilog XL 76 SMpackage vhd 207 swiftpli 61 79 80 81 103 104 106 107 113 115 118 vera_local_dll 276 296 Synopsys Inc Simulator Configuration Guide LIBRARY statement 129 147 162 207 209 license file settings ModelSource 181 linker 191 Linux compiling C files 29 with MemPro 163 LM_DIR environment variable 38 60 112 142 156 196 B ca command 202 Im_enable_timing
31. LMC_HOME as shown in the following examples Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD LIBRARY PATH LMC_HOME 1ib x86_linux 1lib LD_LIBRARY_PATH AIX setenv LIBPATH LMC_HOME 1ib ibmrs 1ib LIBPATH HP UX setenv SHLIB PATH LMC_HOME 1ib hp700 1ib SHLIB_PATH NT Make sure that 7LMC_HOME lib pcnt lib is in the Path user variable Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Using SmartModels and FlexModels with QuickSim Il This section explains how to use SmartModels and FlexModels with QuickSim II To use FlexModels with QuickSim II you use Direct C Control For information on Direct C Control refer to Using FlexModels with SWIFT Simulators on page 24 The rest of this section explains required installation steps and how to use model symbols in the schematic capture front end to the simulator This information is organized in the following major subsections Installing the QuickSim II SWIFT Interface Synopsys ships the part of QuickSim II that communicates with the SWIFT interface for versions of QuickSim II prior to the D 1 release If you are using a version of QuickSim II prior to D 1 you must install the Mentor Graphics application software for each Mentor Graphics user tree Attention Beginning with version D 1 of QuickSim II Mentor Graphics assumed responsibility for their i
32. MODE ON U1 TimingVersion timingversion U1 DelayRange range U1 FlexModelId TMS_INST1 6 Invoke the Verilog XL simulator to compile and simulate your design as shown in the examples below UNIX verilog testbench loadplil swiftpli swift_boot workdir examples verilog model v workdir examples verilog model_fx_vxl v incdir LMC_HOME sim pli sre t incdirt workdir sre verilog NT gt verilog testbench loadp1lil swiftp1li swift_boot workdir examples verilog model v workdir examples verilog model_fx_vxl v incdir LMC_HOME sim pli sre t incdir workdir sre verilog 80 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models gt Note For information on LMTV commands that you can use with FlexModels on Verilog XL refer to LMTV Commands on page 281 FlexModels PLI Static Linking with LMTV To use FlexModels on IBM with Verilog XL follow the procedure in Using SmartModels with Verilog XL on the IBMRS AIX Platform on page 62 Using MemPro Models with Verilog XL MemPro models work with Verilog XL using a PLI application called LMTV that is delivered in the form of a swiftpli shared library in LMC_HOME lib platform lib If you cannot use the swiftpli refer to Static Linking with LMTV on page 82 To use the prebuilt swiftpli follow this procedure 1 If you are on NT make sure 7LMC_HOME bin is in your Path
33. N Input Drive unknown level H Output Sense hard 1 L Output Sense hard 0 h Output Sense soft resistive 1 l Output Sense soft resistive 0 Z Output Sense floating level Used for an I O pin in the input state whose last driven value was 1 either U or u Z Output Sense floating level Used in two cases for an I O pin in the input state whose last driven value was 0 either D or d or for an output pin that is not driving July 31 2001 Synopsys Inc 93 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide Table 15 Test Vector Symbols Continued Symbol Input Output Definition X Output Sense unknown value Unknowns on outputs are generated by unknown propagation value forcing voltage unknowns or inconsistent unknowns Output Sense any level don t care Saving and Restarting the Simulation State The Verilog XL save task saves the complete simulation data structure into a specified file The saved data structure includes the pattern memory for each hardware model simulation instance The restart task restores the complete Verilog XL simulation from the specified file The pattern memory for each hardware model simulation instance is restored into the hardware modeler s pattern memory Linking the SFI Debug Library By default ModelAccess for Verilog dynamically links the non debug version of the SFI library If you want to us
34. NT gt run flex examples_in_vcs cmd model_fx where model_fx is the name of the FlexModel you want to run July 31 2001 Synopsys Inc 49 Chapter 2 Using VCS with Synopsys Models Simulator Configuration Guide TS Note This script was developed for internal use and is made available for user convenience It is not actively maintained as part of the licensed software usr local bin perl SRevisions Soutput_file Example_Simulator_Run_Script die nERROR running 0 No FlexModel name given n n unless SARGV 0 SLmcHome SENV LMC_HOME die ERROR running 0 The LMC_HOME environment variable must be set n unless LmcHome SVcsHome SENV VCS_HOME die ERROR running 0 The VCS_HOME environment variable must be set n unless SVcsHome VcsSwiftNotes SENV VCS_SWIFT_NOTES die ERROR running 0 The VCS_SWIFT_NOTES environment variable must be set n nSet VCS_SWIFT_NOTES to the value 1 n n unless VcsSwiftNotes require SLmcHome lib bin 1libmd101003 p1 SPlatform GetPlatform SPlatform_lib PlatformToLibDir Platform splatform_suffix hp700 gt o solaris gt o pent gt lib Ssuffix Splatform_suffix Platform flexmodel_name SARGV 0 Smodel_path LmcHome models Sflexmodel_name if e model_path else die nERROR running 0 FlexModel Sflexmodel_name Does not Exist in Library n n S version_path LmcHome bin flex
35. NT to specify the search path in your variable setting LS Caution Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you use for snpslmd based authorizations 3 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv LM DIR hardware_model_install_path sms 1m_dir setenv LM LIB hardware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly gt Note On NT these hardware modeler environment variables are set automatically when you install the software 4 Set the CDS_INST_DIR variable to the location of your Cadence installation tree as shown in the following example and make sure that Verilog XL is set up properly in your environment o setenv CDS_INST_DIR path to Cadence installation 5 Depending on your platform set your load library variable to point to the platform specific directory in LMC_HOME as shown in the following examples Solaris o setenv LD_LIBRARY_PATH LMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux o setenv LD_LIBRARY_PATH LMC_HOME 1ib x86_linux 1ib LD_LIBRARY_PATH 60
36. OG bit_7 E QE bit_5 H QH bit_8 QA high_bit QH low_bit ifdef MAX defparam hwm_1 DelayRange MAX endif Run your simulation as usual After running the vcs compiler you should see a compiled simv file To run your simulation type in simv You need an additional passcode to use the hardware model interface If you do not have a passcode contact VCS Simulation Support at 800 837 4564 VCS Utilities If you want to turn on test vector logging or timing measurement you can invoke tasks Im_log Im_log_ off Im_measure_time or Im_measure_time_off instance_name 1lm_measure_time instance_name 1m_measure_time_off where instance_name is a string that is the hierarchical path name of the instance for the hardware model For example assuming that our instance is top hwm_1 with these features it would look like the following example July 31 2001 Synopsys Inc 57 Chapter 2 Using VCS with Synopsys Models 58 module top TILS299 hwm_1 initial begin end top hwm_1 1lm_measure_time top hwm_1 1lm_log file_name 7000 top hwm_1 1m_measure_time_off top hwm_1 1m_log_off Synopsys Inc Simulator Configuration Guide July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models 3 Using Verilog XL with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels MemPro models and hardware models wit
37. PLI and locating it for the simulator Synopsys still ships the files needed to build your own PLI These include e edited copy of veriuser c in the LMC_HOME sim pli src directory e LMTV object Imtv o in the LMC_HOME lib platform lib directory e C Pipe shared library slm_pli_dyn ext in the LMC_HOME lib platform lib directory If you build your own PLI you will need to edit the veriuser c file to pick up the LMTV header files as follows a After include vxl_veriuser h add include ccl_Imtv_include h b After add user entries here add include ccl_lmtv_include_code h July 31 2001 Synopsys Inc 119 Chapter 5 Using MTI Verilog with Synopsys Models Simulator Configuration Guide Using Hardware Models with MTI Verilog To use hardware models with MTI Verilog follow this procedure This procedure covers users on UNIX and NT If you are on NT substitute the appropriate NT syntax for any UNIX command line examples percent signs around variables and backslashes in paths Note that hardware models are supported on MTI Verilog v5 4c and up 1 MTI Verilog only supports dynamic linking of PLI libraries The three ways to specify the required ModelAccess shared library and the order in which the simulator looks for PLI libraries is listed below Choose one of the following methods a Add the platform specific shared library to the Veriuser entry in the modelsim ini file Solaris V
38. Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models AIX setenv LIBPATH LMC_HOME 1ib ibmrs 1ib LIBPATH HP UX setenv SHLIB PATH LMC_HOME 1ib hp700 1ib SHLIB_PATH NT Make sure that 7LMC_HOME lib pcnt lib is in the Path user variable Using SmartModels with Verilog XL SmartModels work with Verilog XL using a PLI application called LMTV that is delivered in the form of a swiftpli shared library in LMC_HOME lib platform lib If you cannot use the swiftpli refer to Using SmartModels with Verilog XL on the IBMRS AIX Platform on page 62 To use the prebuilt swiftpli follow this procedure 1 N W Y gt Note Instantiate the SmartModels in your design defining the ports and defparams as required For details on required SmartModel SWIFT parameters and a model instantiation example refer to Using SmartModels with SWIFT Simulators on page 18 There is no need to build a Verilog executable You can use the one that Cadence provides at CDS_INST_DIR tools bin by adding it to your path variable To use the swiftpli shared library invoke the Verilog simulator to compile and simulate your design as shown in the examples below UNIX verilog testbench model v loadplil swiftpli swift_boot incdir SLMC_HOME sim pli sre NT gt verilog testbench model v loadplil swiftpli swift_boot incdir LMC_HOME sim pli sre For inform
39. Synopsys Models Simulator Configuration Guide Scirocco Template Generator Script for Hardware Models Here is the nawk script that you can use to generate VHDL wrappers for the hardware models Because of the length this script you will have to cut and paste one page at a time from this PDF file to get the whole thing copied to your environment TR RR KR RK KR RK KR KK KKK RK KK KK RR RK In your design directory type nawk f hwm2vhdl nawk SHWM lt model gt NAM gt lt outfile gt vhd where SHWM is the full path to your hardware modeling directory Instantiate vhd into your design THE SCRIPT Script to generate a VSS Scirocco VHDL shell for a hardware model using the lt model gt NAM file BEGIN pin_type 0 is_it_a_vector No data_type prev_signal prev_test prev_number prev_dir ending printf library SYNOPSYS n printf use SYNOPSYS ATTRIBUTES all n printf library IEEE n printf use IEEBE std_logic_1164 al11 n n 2 generic_device_name device 3 printf entity device is n printf generic n printf n printf timing LMSI_TIMING_MEASUREMENT DISABLED n printf delay_type LMSI_DELAY_TYPE TYPICAL n printf delay LMSI_DELAY ENABLED n printf log LMSI_LOG DISABLED n printf timing_violations LMSI_TIMING_VIOLATIONS DISABLED n prints xprop LMSI_XPROP DISABLED
40. UNIX or semicolon separated list NT to specify the search path in your variable setting 8 Caution Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you use for snpslmd based authorizations 3 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv LM DIR hardware_model_install_path sms 1m_dir setenv LM LIB hardware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly 4 Set the CDS_INST_DIR variable to the location of your Cadence installation tree as shown in the following example and make sure that NC Verilog is set up properly in your environment setenv CDS_INST_DIR path_to_Cadence_installation 5 Depending on your platform set your load library variable to point to the platform specific directory in LMC_HOME as shown in the following examples Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD_LIBRARY_PATH LMC_HOME 1ib x86_linux 1ib LD_LIBRARY_PATH AIX setenv LIBPATH SLMC_HOME 1ib ibmrs 1ib SLIBPATH 102 Synopsys Inc July 31 2001 Simulat
41. VCS command and replace the slm_pli_ves lib library with the slm_pli_v4vcs lib library If you are using VCS 5 1 or later add the ldI switch to your VCS command Linux If you are not using the MemPro C testbench ves Verilog_modules MemPro_model_files SLMC_HOME 1ib x86_linux 1lib slm_pli o P LMC_HOME sim pli src slm_pli tab incdir SLMC_HOME sim pli sre RI LDFLAGS rdynamic If you are using the MemPro C testbench ves Verilog_modules MemPro_model_files LMC_HOME 1ib x86_linux 1lib slm_pli o P local_slm_pli tab your_testbench c CFLAGS I LMC_HOME include incdir SLMC_HOME sim pli sre RI LDFLAGS rdynamic 4 Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 July 31 2001 Synopsys Inc 53 Chapter 2 Using VCS with Synopsys Models 5 Compile your design Simulator Configuration Guide If you are using the MemScope Dynamic Data Exchange feature ves vestlictwait incdir SLMC_HOME sim pli src design_name LMC_HOME 1ib platform 1lib slm_pli o Xstrict P SLMC_HOME sim pli src slm_pli tab cc cc path If you are not using the MemScope Dynamic Data Exchange feature ves vestlictwait incdir LMC_HOME sim pli sre design_name LMC_HOME 1ib platform 1lib slm_pli o P SLMC_HOME sim pli src slm_pli tab cc cc_path 6 In
42. XL SmartModel Windows also referred to as Windows is a SmartModel Library feature that allows you to view and change the contents of internal registers during simulation for models and simulators including Verilog XL that support this feature For general information about SmartModel Windows refer to the SmartModel Library User s Manual This section provides information about using SmartModel windows with Verilog XL LMTV SmartModel Windows Commands The following commands allow you to work with SmartModel Windows during Verilog XL simulation Commands are instance specific which means that they must be issued once for each instance These commands are most often placed in the testbench but can also be issued at the command line For details and examples refer to the specific command descriptions lm_monitor_enable lai_enable_monitor Enables SmartModel Windows for one or more window elements in a specified model instance Can be used in both Historic and SWIFT SmartModel modes but is recommended for use only in Historic SmartModel mode lm_monitor_disable lai_disable_monitor Disables SmartModel Windows for one or more window elements in a specified model instance Can be used in both Historic and SWIFT SmartModel modes but is recommended for use only in Historic SmartModel mode lm_monitor_vec_map lm_monitor_vec_unmap Enables or disables a direct mapping between a user defined variable and a wind
43. aedee sac aeuss cence 83 PICt VIS xin ccd Rohde eee S ed ese ORK REO Shee RS 83 Using Hardware Models 65 6 4ieoh 065 eds sae 5065 4e base Uka 6544 85 Sim_log test_vectors Command Reference i 4 sas cedacdesesabeases 94 Im_loop_instance Command Reference ici g oak ck ciese das nie decd gawes 95 Im_timing_information Command Reference 00 eeu 96 lm_timing_measurements Command Reference 0005 96 Im_unknowns Command Reference kg ncnccawvenecee es ceeesdeedankds 97 lmyvsg Command Referenc 5c oo segs ce weds ae house bbe EEEREN ER 99 Chapter 4 Using NC Verilog with Synopsys Models ccccccccccccccccscces 101 be a ee ee ee ee eee ee es ee eee ce ee ee ee 101 Setting Environment Variables 6 65icer0d o4e0bs avenddseadebbongnedes 101 Using SmartModels with NC Verilog 0 0 c cece eee ee eee 103 Static Linkine with LMTY 26 cei eres 4G Kid aW ewes be del reed ences 104 Using FlexModels with NC Verilog 644ic lt 0co0erscnn bowen Gunadane bandos 104 Static Linking with LMTV vias vanecas teens ese cdaeetuseeeas ee eaws 106 Using MemPro Models with NC Verilog on UNIX 0000 107 4 Synopsys Inc July 31 2001 Simulator Configuration Guide Contents Static Linking Wih LMTY Geocities cates i etpct open tunivewedciee tows 108 Using Hardware Models with NC Verilog 0 0 02 cece eee eee 108 PH Vere VON ns 6x5 60d 45 de R ESPRESSO NG HOU RADE TREE ERR NRA 109 Chapter
44. and library files To interface the hardware modeler to VCS add the Imc hm switch to the VCS command line as shown in the following example ves plusarg_save RI test v TILS299 1lmvc v lmc hm o simv override_model_delays maxdelays 1 vcs log amp You can optionally invoke VCS without the lmc hm switch by using the P switch to point to the VCS_LMC Imvc tab file and including the VCS_LMC Imvc o object file and LM_SFI Im_sfi a library as shown in the following example ves plusarg_save RI test v TILS299 1mvc v P VCS_LMC l1mvc tab VCS_LMC l1lmvc o SLM SFI 1m sfi a o simv override_model_delays maxdelays 1l vcs log amp where e vcs is the compiler e test v is the file that is part of the top level system source files e TILS299 lmvc v is the vcs template for the HW model e Imvc tab is the VCS file for Imvc calls for vector logging and timing measurement e Imvc o is the object code for LMC C file Imvc c which contains the definitions for all the Imvc tasks functions e lm_sfi a is the simulator function interface software that links the VCS simulator to the hardware modeler e override_model_delays is a switch that allows you to specify timing other than typical gt Note the RI option is not required to generate the simv file It is used to have the simulator automatically execute after compilation and to use the xvcs debugger For more information on using the tab c files and options
45. and the model v file as in the following example verilog TILS299 v tbench v loadp1lil mav mav_boot July 31 2001 Synopsys Inc 89 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide As Verilog executes it outputs progress status and error messages to the screen and saves the transcript to a file named verilog log which you can examine if necessary for troubleshooting Examining the Output verilog log File After echoing the command that invoked Verilog and the copyright and source information Verilog announces its progress as it compiles the input files When the prompt C1 gt is issued the simulator is waiting at time 0 for you to enter a command Typing a period which means continue starts the simulation run Typing finish at the prompt terminates the simulation session Notice in particular these lines which state the release numbers of ModelAccess for Verilog and SFI Runtime ModelAccess for Verilog XL R3 5a SFI Copyright 1988 2000 Synopsys Incorporated 08 30 00 R3 5a If you are troubleshooting and call Synopsys Technical Support for help you will be asked for the SFI release number in this case R3 5a For instructions on contacting Synopsys Technical Support refer to Getting Help on page 14 The following illustration shows an example verilog log file without errors Host command verilog 1mv Command arguments S TILS299 v tbench v VERILO
46. around variables and backslashes in paths gt Note 1 If you want the improved performance that comes with bused wrappers generate a Verilog model wrapper file by running VCS with the lmc swift template switch as shown in the following example SVCS_HOME bin vcs lmc swift template model where model is the name of the model you want to use This creates a model swift v file Note that VCS version 5 1 and up generates bused Verilog wrapper files by default For bit blasted wrappers use the old switch The bused wrappers enable improved performance but do not work with the examples testbench shipped with the model To exercise the examples testbench use the wrappers shipped with the model see Table 8 as explained in the rest of this procedure If you are using the bused wrappers adjust accordingly Create a working directory and run flexm_setup to make copies of the model s interface and example files there as shown in the following example SLMC_HOME bin flexm_setup dir workdir model_fx You must run flexm_setup every time you update your FlexModel installation with anew model version Table 8 lists the files that flexm_setup copies to your working directory Table 8 FlexModel VCS Verilog Files File Name Description Location model_pkg inc Verilog task definitions for FlexModel workdir src verilog interface commands This file also references the flexmodel_pkg inc and model_user_pkg inc
47. can refer to the model using a standard VHDL convention such as a CONFIGURATION statement CONFIGURATION mymem_a OF mymem_tst IS FOR atest FOR ALL mymem use CONFIGURATION SLM MODELS mymem_behav END FOR END FOR END mymem_a Add LIBRARY and USE statements to your testbench LIBRARY SLM_LIB USE SLM_LIB mempro_pkg all This also provides access to MemPro testbench commands For more information on using the MemPro testbench interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 For information on message levels and message level constants refer to Controlling MemPro Model Messages on page 33 July 31 2001 Synopsys Inc 133 Chapter 6 Using Scirocco with Synopsys Models Simulator Configuration Guide 10 Compile your design as shown in the following example whdlan design_name 11 Invoke Scirocco on your design making sure to include all libraries as shown in the following example scsim debug_all vhpi slm_vhpi foreignINITelab cpipe design_name fo gt Note The debug_all switch is only needed on Scirocco release 2000 02 Using MemPro Models in a Testbench To use a MemPro model in a testbench follow this procedure If you already
48. code for the file Your designs containing MemPro RDRAMs will simulate properly however o 6 After generating a model using MemPro compile the VHDL code for the model as shown in the following example vhdlan c mymem vhd 7 If you compiled the model to a library SLM_MODELS in these examples add a LIBRARY statement to your testbench LIBRARY SLM MODELS This makes models in SLM_MODELS accessible from your design You can refer to the model using a standard VHDL convention such as a CONFIGURATION statement CONFIGURATION mymem_a OF mymem_tst IS FOR atest FOR ALL mymem use CONFIGURATION SLM MODELS mymem_behav END FOR END FOR END mymem_a 8 Add LIBRARY and USE statements to your testbench LIBRARY SLM_LIB USE SLM_LIB mempro_pkg all This also provides access to MemPro testbench commands For more information on using the MemPro testbench interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual 9 Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 For information on message levels and message level constants refer to Controlling MemPro Model Messages on page 33 July 31 2001 Synopsys Inc 149 Chapter 7 Using VSS with Synopsys Models Simulator Configuration Guide 10 Compile your desig
49. create the technology file and then running tc to compile and register it with the component interface e If you make any changes to the Shell Software other than changing pin names and timing information you should use lm_model with the Step Register switch for example lm model 741s74 s r This step is equivalent to running reg_model e Ifyou have not changed any pin names and want to run both the registration and timing steps you can use Im_model with the Step Update switch to update the component interface without recreating the symbol For example lm model 741s74 s u This switch is particularly useful because symbol generation is the most time consuming step of registration and you lose all manual edits you have made to a symbol when you regenerate it e If you already have a working symbol you can use Step Update to register the hardware model functionality with the existing component For example you would use Step Update if you have a different type of model for the same component You can then change the MODEL property in the schematic in order to specify whether you want to use the hardware model or another type of model for an instance Simulating with Hardware Models in QuickSim II Once you have registered each hardware model in your design and set the MODEL property to the appropriate label for instances that reference those models you are ready to simulate You can use the SIGnal INSTance command to turn on an
50. created scsim when using a MemPro model or FlexModel skip to Step 4 1 Create a MemPro VHDL model using MemSpec Generate code for Cyclone or VSS 2 Instantiate the MemPro component in your testbench 3 Set your UNIX search path so that it points to the new vhdlsim executable you just created 4 Run the following commands to compile the required MemPro VHDL packages mkdir slm lib MY_WORK vhdlan noevent w slm lib SLMC_HOME sim vhpi src slm_hdlc vhd vhdlan event w slm lib LMC_HOME sim vhpi src mempro_pkg vhd AP o o 5 Compile the model and testbench that you just created vhdlan event w MY_WORK upd4516161 vhd vhdlan event w MY_WORK upd_testbench vhd o o 6 Run the simulation scsim vhpi slm_vhpi ForeignINITelab cpipe your_testbench 134 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 6 Using Scirocco with Synopsys Models Using Hardware Models with Scirocco To use Scirocco with hardware models follow this procedure Note that your design can include a mix of event based and cycle based but hardware models simulate only as event based 1 Make sure Scirocco is set up properly and all required environment variables are set as explained in Setting Environment Variables on page 124 2 Add the hardware model install tree to your path variable as shown in the following example set path install sms bin your_platform path 3 Create the model vhd wrapper file for your har
51. directory within the output_path for example MC68020 By default the name is created from the base name of input_dir by removing any leading dollar characters and converting all lowercase characters to uppercase If the output component directory name is the same as the input directory name Im_model will generate an error and fail rather than overwrite the input directory Specifies the component interface s with which to register the model Multiple component interfaces can be specified By default the model is registered with all component interfaces Specifies the label s to register with the component interface Multiple labels can be specified By default the model is registered with the lm label which corresponds to the functional description Specifies a particular model MDL file within the input_dir By default the system uses the model file with the same base name as the output component directory which is defined by the Dir switch Synopsys Inc 265 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Step RegisterlISymbollTiminglUpdate Replace VERBose Help Usage VERSion Old LM Examples Selects particular registration step s Step Register registers the model s functional description Step Symbol creates and registers the symbol Step Timing creates compiles and registers the technology file Step Update is equivalent to Step Registe
52. example set path install sms bin platform path 3 Create your own library directory for files that will be generated for the hardware model 4 Run the ncshell command to generate vhd wrapper files as shown in the following example neshell import lmsfi into vhdl models TILS299 TILS299 MDL You can also use the all switch to create vhd files for multiple hardware models NC VHDL Example with TILS299 Hardware Model The following example uses the TILS299 hardware model to show how to set up hardware models for use with NC VHDL 1 Create a testbench to instantiate the hardware model for example TB_TILS299 vhd 2 Run ncvhdl to compile your vhd files as shown in the following example nevhdl TILS299 vhd TILS299_comp vhd TB_TILS299 vhd 3 Elaborate the design as shown in the following example ncelab messages work tb_tils299 test 4 Invoke the NC VHDL simulator as shown in the following example ncesim gui work tb_tils299 test July 31 2001 Synopsys Inc 213 Chapter 11 Using NC VHDL with Synopsys Models Simulator Configuration Guide NC VHDL Utilities The following hardware modeler simulator commands are supported in NC VHDL Im_log_test_vectors instance_name 1 0 filename Enables 1 or disables 0 vector logging for hardware models Im_timing_measurements instance_name 1 0 filename Enables 1 or disables 0 timing measurements for hardware models Im
53. for all hardware models in the design and take the timing delays and timing checks directly from the Shell Software If you decided you wanted to use the technology files instead for all hardware models you could use the following command to switch back to the default timing shell without having to select every instance sig inst nolst p all To select Shell Software timing every time you invoke QuickSim II with a particular design you can create or edit a quicksim startup file under the design viewpoint Add the following line to the file to directly call the function that implements this Signal Instance command signal_instances 1st all IS1 Substitute the instance name of any hardware modeled device for I 1 You can also use the actual measured delays from the device as an alternative timing option with hardware models For more information about this feature refer to Timing Measurement on page 261 Performance Monitoring You can monitor the performance of the hardware modeler and append the results to the simulator log file after simulation To enable performance monitoring in the window where you are running the simulator enter the following o setenv LM OPTION monitor_performance For more information refer to Performance Monitoring in the ModelSource User s Manual Unknown Handling and Propagation The unknown handling and propagation commands enable you to modify the hardware model
54. for all window elements use this command lm_monitor_enable U4 2 To enable only window elements A_REG and D_REG for U4 use this command lm monitor _enable U1 A REG D_ REG 3 To read from a specific window element use the monitor strobe write and display Verilog commands For more information refer to the Cadence documentation 4 To display the contents of all window elements use Im_ status or lai_status For example to display all window elements for instance U1 use this command S lm_status U1 72 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models The information is returned in the following format Note SmartModel Windows Status INREG Input Register 000 OUTREG Output Register 000 IO_INREG I O Input Register 000 HREG Hidden Register 0 5 To write to a window element assign a value to the window element in this format instance window_element value For example to clear Bit 3 of the window element HREG in the instance U1 assuming that HREG has write access use this command U1 HREG 3 0 gt Note Refer to the individual model datasheets for information about the read write capabilities of model window elements In SWIFT SmartModel Mode In SWIFT SmartModel mode you can use the lm_monitor_enable or lai_enable_monitor commands to monitor scalar windows in exactly the same way as describe
55. form 1mc hm 3 Set the LM_SFI environment variable to the SFI directory in the hardware modeling tree as shown in the following example setenv LM SFI hardware_modeler_install_path sms 1lib platform 4 Set the VCS_LMC_HM_ARCH environment variable so that you can later use the Imc hm switch This variable must be set to find the SFI directory in the sms lib tree as shown in the following examples Solaris setenv VCS LMC HM ARCH sun4 solaris HP UX setenv VCS_LMC HM ARCH pa_hp102 5 Create a Verilog HDL template for the hardware model using the Imvc_template script provided by VCS as shown in the following example Q lmvc_ template model_file where model _file is the name of the hardware model s MDL file For example if your model is the TILS299 enter lmvc_ template TILS299 MDL This step produces a TILS299 lmvc v file that contains the module definition with all the calls declarations and assignments necessary to make the file a valid VCS module gt Note The Imvc_template program looks for Shell Software files in the directories indicated by the LM_LIB environment variable You can modify the port list generated by the Imvc_template to match the existing model instantiations by editing the NAM file July 31 2001 Synopsys Inc 55 Chapter 2 Using VCS with Synopsys Models Simulator Configuration Guide 6 Compile your description Make sure to include the hardware model template and supporting PLI
56. installed Use the instructions in this section to add the SmartModel menus only if after installation you do not find SmartModel menu entries under the Design Architect Libraries pull down menu To include SmartModel menu selections in the Design Architect DA menus follow these steps a Set the AMPLE_PATH environment variable If this variable already exists use one of these commands as appropriate UNIX setenv AMPLE PATH AMPLE_ PATH SLMC_HOME special qsim menus If you have a custom userware directory you can create links that point to LMC_HOME special qsim menus des_arch NT DRIVE path_to_menus b If the AMPLE_PATH environment variable does not exist use one of these commands as appropriate UNIX setenv AMPLE PATH S LMC_HOME special qsim menus If you have a custom userware directory you can create links that point to LMC_HOME special qsim menus des_arch NT DRIVE path_to_menus 4 Generate the menus as shown in the appropriate example UNIX LMC_HOME bin mgc_menu p1 NT gt LMC_HOMES bin mgc_menu cmd 220 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Ment entries are created for the models that you have installed If menu entries are missing for models you believe you have in your library use the Admin tool to verify your installed models If you change your model installation rerun mgc_menu to update the menu
57. interface and example files there as shown in the following example SLMC_HOME bin flexm_setup dir workdir model_fx You must run flexm_setup every time you update your FlexModel installation with anew model version Table 19 describes the FlexModel VSS interface and example files that the flexm_setup tool copies Table 19 FlexModel VSS VHDL Files File Name Description Location model_pkg vhd Model command procedure calls for HDL workdir src vhdl Command Mode model_user_pkg vhd Clock frequency setup and user workdir src vhdl customizations model_fx_vss vhd A SWIFT wrapper for the model workdir examples vhdl model_fx_comp vhd Component definition for use with the model workdir examples vhdl entity defined in the SWIFT wrapper file This is put in a package named COMPONENTS when compiled model vhd A bus level wrapper around the SWIFT model workdir examples vhdl This allows you to use vectored ports for the model in your testbench This file assumes that the COMPONENTS package has been installed in the logical library slm_lib model_tst vhd A testbench that instantiates the model and workdir examples vhdl shows how to use basic model commands 3 Update the clock frequency supplied in the model_user_pkg vhd file in your working directory to correspond to the desired clock period for the model After running flexm_setup this file will be located in workdir sre v
58. interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 For information on message levels and message level constants refer to Controlling MemPro Model Messages on page 33 Compile your code as shown in the following examples UNIX o vlog testbench model v incdir SLMC_HOME sim p1li sre NT gt vlog testbench model v incdir LMC_HOME sim pli sre Invoke the simulator as shown in the following examples HP UX vsim pli S LMC_HOME 1ib hp700 1ib swiftpli_mti sl design Solaris vsim pli LMC_HOME lib sun4Solaris lib swiftpli_mti so design Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 5 Using MTI Verilog with Synopsys Models Linux vsim pli SLMC_HOME 1ib x86_linux 1lib swiftpli_mti so design NT gt vsim pli LMC HOME lib pent lib swiftpli_mti dll design gt Note If you are also using SmartModels or FlexModels in your design you do not need to load the swiftpl_mti again since the same library is used to enable all three types of models in MTI Verilog Static Linking with LMTV If you cannot use the Synopsys supplied swiftpli shared library refer to the MTI documentation for information on building your own
59. is true for e Models of simple logic gates which are supplied with DeMorgan equivalent negative logic symbols in addition to standard symbols e Models that offer both pin and bus symbols For information about symbol compatibility with different versions of the Design Architect software refer to the SmartModel Library Release Notes July 31 2001 Synopsys Inc 221 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Pin and Bus Symbols For many high pin count parts you get pin and bus symbols Bus symbols may be more convenient to use than their pin equivalents because they take up less real estate on the schematic and are easier to connect and to read Figure 13 illustrates the differences between pin and bus symbols Pin Symbol Bus Syrnbol ue MRS 100 20 CASTA CEU GFETOCR D4 P12 Osu DRA DEE 01 ERR NUL PINFILE Figure 13 Sample Pin and Bus Symbols Symbol Properties Assigning specific values to symbol properties completes the definition of a SmartModel The properties used on the symbols provided for the Mentor Graphics Design Architect environment include e Symbol properties used by SWIFT interface models e Symbol properties required for simulation e Optional symbol properties 222 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models You can edit symbol property values either with the Schematic Editor p
60. just as you would any other files in your design Elaborating and Simulating the Design Performance Monitoring You can monitor the performance of the hardware modeler and append the results to the simulator log file after simulation To enable performance monitoring in the window where you are running the simulator enter the following setenv LM OPTION monitor_performance For more information refer to Performance Monitoring in the ModelSource User s Manual 188 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models 2 state and 4 state Simulation If you are using Release 1 1 or later of ModelAccess for Cyclone with Cyclone Release 1998 02 or later you can specify either 2 state 0 1 or 4 state 0 1 X Z simulation However for earlier releases 2 state simulation is not supported when running cylab you must specify 4state to create 4 state 0 1 X Z code Similarly for earlier releases you must specify 4state for 4 state simulation with cysim Defining LD_LIBRARY_PATH When using the output of genInterface with Cyclone the LD_LIBRARY_PATH environment variable must include the current directory This is also required by Cyclone so if you have set LD_LIBRARY_PATH as documented in the Cyclone user documentation LD_LIBRARY_PATH will be correct for genInterface Cyclone Elaboration Warnings Cyclone issues two elaborations warnings for ea
61. n printf xprop_method LMSI_XPROP_METHOD HIGH n printf n n printf port n printf n 4 in_pin 4 out_pin 4 io_pin 4 power_pin pin_typet 2 0 amp amp pin_type 3 if pin_type 1 direction in else if pin_type 2 direction out else if pin_type 3 direction inout else next current_signal 1 gsub current_signal gsub current_signal current_test current_signal 138 Synopsys Inc July 31 2001 Simulator Configuration Guide on r gsub 0 9 current_test n split current_signal array_a a zA Z current_number array_a n gsub current_number if prev_signal 0 9 if current_test prev_test if is_it_a_vector No data_start prev_number if current_number prev_number 1 is_it_a_vector Yes prev_signal current_signal prev_test current_test prev_number current_number next else if is_it_a_vector Yes total prev_number data_start if prev_number gt data_start data_end data_start data_start prev_number else data_end prev_number Chapter 6 Using Scirocco with Synopsys Models current_number prev_number 1 data_type _vector data_start downto data_end prev_signal prev_test if prev_signal
62. names used by the model not those on the symbol or in the pin_map file How the pin_map File Works At startup a PKG symbol value of BUS triggers the simulator to look for a pin_map file for that model The pin_map cross reference file is a free format ASCII file It contains statements that use the following syntax pin_type symbol_pin model_pin_names comment_text Following are descriptions of the fields and options pin_type Must be the same value as the PINT YPE property of the model Valid values are IN OUT IXO and IO Do not change this value symbol_pin The new pin name you want to use on your symbol This is the symbol s user PIN property not its PIN_ NAME property Optional model_pin_names A statement can have from 0 to 767 model_pin_names separated by spaces tabs or new lines The model_pin_names are ordered from most significant to least significant and refer to the PIN property not the PIN NAME property Ends a statement Starts a comment which runs to the end of the line July 31 2001 Synopsys Inc 241 Chapter 12 Using QuickSim II with Synopsys Models Example of a pin_map File The following example pin_map file customizes the standard symbol supplied with the model of the National Semiconductor DP8429 DRAM controller shown in Figure 15 ie OP seo 70 DIF Simulator Configuration Guide Figure 15 National Semiconductor DP8429 DRAM Controller In the exampl
63. passed to the device when an unknown value is passed to the hardware modeler for the instance Tbench U1 lm_unknowns propagate no value low Tbench U1 The following example disables unknown propagation causes a high value to be passed to the device when an unknown value is passed to the modeler specifies 20 random sequences to propagate unknowns through the hardware model and specifies 200 as the seed for the random sequence generator for all hardware model instances in the simulation lm_unknowns propagate yes value high sequence_count 20 random_seed 200 Imvsg Command Reference For a specified hardware model the Imsvg script creates a model v file and places it in the specified destination directory Syntax Imvsg d destination i w v vector_path h model MDL Arguments d destination Specifies the destination directory in which to store the generated model v file The default is the current directory i Generates a warning if a pin name is an illegal Verilog identifier By default no warning is issued July 31 2001 Synopsys Inc 99 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide W Specifies pullup and pulldown signal strength of weak1 and weako0 instead of the default pu111 and pul10 respectively This will provide compatibility with Cadence s hardware modeler interface y vector_path Specifies the pathname to
64. path to the VERA header files included in LMC_HOME The following is a sample compile script o vera cmp vera_testbench I LMC_HOME sim vera sre workdir srce vera Run the VERA testbench in a Verilog or VHDL simulation environment When you run the Verilog or VHDL simulator the VERA simulator needs to load your compiled VERA object files You also need to load the following VERA object files e Istmodel vro e swiftmodel vro e flexmodel_pkg vro e model_pkg vro e testbench vro For more information on loading VERA object files refer to the VERA System Verifier User Manual Attention To prevent your simulation from ending prematurely in cases where the VERA testbench completes before the Verilog VHDL testbench use the vera_finish_on_end switch on your simulator invocation line Using VERA with VCS The following steps show how to use FlexModels with VERA and VCS This is just one way of using the VERA simulator s UDF multiple vro files and so on For more information refer to the VERA System Verifier User Manual All steps shown here are also documented in that manual 1 Compile the VERA source files vera cmp ISLMC_HOME sim vera src SLMC_HOME sim vera src lstmodel vr vera cmp ISLMC_HOME sim vera src SLMC_HOME sim vera src swiftmodel vr July 31 2001 Synopsys Inc 275 Appendix A Using VERA with FlexModels Simulator Configuration Guide o vera cmp I LMC_HOME sim vera s
65. point to the platform specific directory in LMC_HOME as shown in the following examples Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD_LIBRARY_PATH SLMC_HOME 1ib x86_linux 1ib LD_LIBRARY_PATH 38 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models AIX setenv LIBPATH LMC_HOME 1lib ibmrs 1lib LIBPATH HP UX setenv SHLIB_ PATH LMC_HOME 1ib hp700 1lib SHLIB PATH NT Make sure that 7LMC_HOME lib pcnt lib is in the Path user variable 5 Set the VCS_HOME variable to the location of your VCS installation tree as shown in the following example and make sure that VCS is set up properly in your environment setenv VCS_HOME VCS_install_path 6 Set the VCS_SWIFT_NOTES variable to 1 as shown in the following example setenv VCS_SWIFT_NOTES 1 Using SmartModels with VCS To use SmartModels with VCS follow this procedure 1 Generate a Verilog model wrapper file by running VCS with the lmc swift template switch as shown in the following example SVCS_HOME bin vcs lmc swift template model where model is the name of the model you want to use This will create a model swift v file Note that VCS version 5 1 and up generates bused Verilog wrapper files by default If you want bit blasted wrappers use the old switch Synopsys provides a tool vcs_sg that allows you to generate multiple model wra
66. printf use SYNOPSYS ATTRIBUTES all n printf library IEEE n printf use IEEBE std_logic_1164 al11 n n 2 generic_device_name device 3 printf entity device is n printf generic n printf n printf timing LMSI_TIMING_MEASUREMENT DISABLED n printf delay_type LMSI_DELAY_TYPE TYPICAL n printf delay LMSI_DELAY ENABLED n printf log LMSI_LOG DISABLED n printf timing_violations LMSI_TIMING_VIOLATIONS DISABLED n prints xprop LMSI_XPROP DISABLED n printf xprop_method LMSI_XPROP_METHOD HIGH n printf n n printf port n printf n 4 in_pin 4 out_pin 4 io_pin 4 power_pin pin_typet 2 0 amp amp pin_type 3 if pin_type 1 direction in else if pin_type 2 direction out else if pin_type 3 direction inout else next current_signal 1 gsub current_signal gsub current_signal current_test current_signal July 31 2001 Synopsys Inc 153 Chapter 7 Using VSS with Synopsys Models on r gsub 0 9 current_test n split current_signal array_a a zA Z current_number array_a n gsub current_number if prev_signal 0 9 if current_test prev_test if is_it_a_vector No data_start prev_number if current_number prev_n
67. section describes how to include MemPro memory models and testbench interface commands in your design The MemPro VHDL interface code is contained in the following files slm_hdlc vhd Simulator specific HDL to C interface code MemPro specific module containing the VHDL implementation of the MemPro testbench interface rdramd_pkg vhd RDRAM specific module All of these files are located in the LMC_HOME sim simulator src directory mempro_pkg vhd Using MemPro Models with Verilog Simulators This section describes how to include MemPro memory models and testbench interface commands in your design The following files define MemPro PLI routines and interface commands PLI routines This file is located in the LMC_HOME lib platform lib directory slm_pli o Verilog testbench task definitions for MemPro interface commands This file is located in the LMC_HOME sim pli src directory mempro_pkg v July 31 2001 Synopsys Inc 31 Chapter 1 Using Synopsys Models with Simulators Simulator Configuration Guide mempro_c_tb h C testbench function definitions for MemPro interface commands This is located in the LMC_HOME include directory Instantiating MemPro Models You instantiate MemPro models just like any other HDL models as shown in the following DRAM examples MemPro Verilog Instantiation dram1x64 bank ras rasr ucas ucasr lcas lcasr we wer oe oer a adrr dq dataw
68. see if you have write permission for LMC_HOME synopsys smartmodel if so skip to Step 3 Otherwise open the Synopsys_vss setup file in your current working directory and search for the string SMARTMODEL By default the logical library name SMARTMODEL is mapped to LMC_HOME synopsys smartmodel as follows SMARTMODEL SLMC_HOME synopsys smartmodel 2 Change the directory to one for which you have write permission as in the following example SMARTMODEL smartmodel 3 To generate VHDL model wrapper files invoke create_smartmodel_lib with any optional arguments For information on the syntax for this command refer to create_smartmodel_lib Command Reference on page 144 SSYNOPSYS_SIM sim bin create_smartmodel_lib arguments 4 If you changed the SMARTMODEL mapping in Step 3 you must use the sredir option to specify that directory Also you can save time by using the model or modelfile option to specify the models you want Otherwise the script processes all installed SmartModels For example here is a recommended set of options to use for one SmartModel ttl00 in this example SSYNOPSYS_SIM sim bin create_smartmodel_1lib model tt100 srcdir smartmodel 5 After create_smartmodel_lib has finished executing verify that the VHDL template files have been created in the appropriate directory 6 To use SmartModels in the VHDL source file of your design specify the SMARTMODEL library and instantiate each Sm
69. statements to your testbench library sm_library use sm library component all 4 Instantiate SmartModels in your design using the wrapper files that you generated in Step 2 For information on required configuration parameters and instantiation examples refer to Using SmartModels with SWIFT Simulators on page 18 5 Compile the other VHDL files into the work library as shown in the following example ncevhdl w work testbench vhd 6 Elaborate your design as shown in the following example ncelab cfgtest 7 If you are using any SmartCircuit models in your design set the LMC_TIMEUNIT environment variable to 12 for 1 ps resolution as shown in the following example setenv LMC_TIMEUNIT 12 This sets a global timing resolution for all SmartModels in your simulation If this variable is not set the default timing resolution is 100 ps which is the resolution used by most SmartModels To see if a model is a SmartCircuit model refer to the model datasheet For more information on the LMC_TIMEUNIT environment variable refer to the Cadence documentation for NC VHDL 8 Invoke the NC VHDL simulator on your design as shown in the following example o nesim design July 31 2001 Synopsys Inc 207 Chapter 11 Using NC VHDL with Synopsys Models Using FlexModels with NC VHDL To use FlexModels with NC VHDL follow this procedures 1 Add the following lines to your cds lib file define slm lib slm_lib_path
70. std_logic_vector 11 downto 6 AA OUT std_logic_vector 21 downto 12 AB INOUT std_logic_vector 29 downto 22 Replacing Special Characters Cyclone allows only alphanumeric characters and underscores _ in the generation of valid signal names Hardware model Shell Software allows special characters such as slash asterisk minus and underscore _ The genInterface program follows the conversion rules specified in Table 21 Table 21 Rules for Special Character Mapping Conversion when Character in Shell Conversion when at appearing within Conversion when at Software beginning of name name end of name Slash SL_ _SL_ _SL Star ST_ _ST_ STE Minus NE_ _NE_ _NE 192 Synopsys Inc July 31 2001 Simulator Configuration Guide Table 21 Rules for Special Character Mapping Continued Conversion when Character in Shell Conversion when at appearing within Conversion when at Software beginning of name name end of name Underscore _ UN_ _ no conversion _UN Any other special Random Random Random character alphanumeric alphanumeric alphanumeric Chapter 9 Using Cyclone with Synopsys Models For every generated name genInterface then compares the name with the present list of names If there is a match a random string is added at the end of the name until it is unique The following examples illustrate how genInterface c
71. swiftpli_mti so design NT gt vsim LMC_HOME lib pent lib swiftpli_mti dll design For information on LMTV commands that you can use with SmartModels on MTI Verilog refer to LMTV Command Reference on page 279 July 31 2001 Synopsys Inc 113 Chapter 5 Using MTI Verilog with Synopsys Models Simulator Configuration Guide Static Linking with LMTV If you cannot use the Synopsys supplied swiftpli shared library refer to the MTI documentation for information on building your own PLI and locating it for the simulator Synopsys still ships the files needed to build your own PLI These include e edited copy of veriuser c in the LMC_HOME sim pli src directory e LMTV object Imtv o in the LMC_HOME lib platform lib directory If you build your own PLI you will need to edit the veriuser c file to pick up the LMTV header files as follows a After include vxl_veriuser h add include ccl_Imtv_include h b After add user entries here add include ccl_lmtv_include_code h Using SmartModels with MTI Verilog on the IBMRS AIX Platform 1 Open the modelsim ini file in a text editor and locate this line Veriuser veriuser o 2 Replace the line with the following The following expressions should all appear on one line with the PLI entry separated by a space Veriuser SLMC_HOME 1ib hp700 1ib slm_pli_mti sl SMODEL_TECH libswiftpli sl 3 Compile your code as shown in the follo
72. the modeling system However you might decide to run your simulation from the ModelSource Processor workstation as well unless you are using an LM 1400 as the ModelSource Processor The R3 3a and later ModelSource RMS has been enhanced to deliver higher performance in all configurations and has been optimized to generate the maximum performance gain over previous releases of the RMS when used by a single user running the simulation from the ModelSource Processor workstation This enhanced release of the RMS is available for Sun Solaris and HP 700 ModelSource Processor workstations LM 1400 LM family System Hardware and Software If you are using one of the LM family hardware model servers LM 1200 or LM 1400 your hardware modeling system configuration consists of the LM family unit This family of modelers includes a dedicated CPU within the modeling system chassis The LM family system connects to the rest of your network via Ethernet The LM family CPU runs the standard RMS You run your simulations from other workstations on the Ethernet network Configuration Options Figure 7 on page 177 illustrates some of the supported Cyclone configurations labeled from A the highest performance choice to D lower performance options Option A The recommended configuration for highest performance in cycle based simulation is an MS 3400 or MS 3200 hardware modeling system with the simulation executing on the ModelSource Processor workstation w
73. use for snpslmd based authorizations 3 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv LM DIR hardware_model_install_path sms 1m_dir setenv LM LIB hardware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly Set the CDS_VHDL variable to the location of your Leapfrog installation and make sure that Leapfrog is set up properly in your environment Depending on your platform set your load library variable to point to the platform specific directory in LMC_HOME as shown in the following examples Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD_LIBRARY_PATH LMC_HOME 1ib x86_linux 1ib LD_LIBRARY_PATH AIX o setenv LIBPATH LMC_HOME 1lib ibmrs 1lib LIBPATH HP UX setenv SHLIB_ PATH LMC_HOME lib hp700 lib SHLIB_ PATH NT Make sure that 7LMC_HOME lib pcnt lib is in the Path user variable Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 10 Using Leapfrog with Synopsys Models Using SmartModels with Leapfrog To use SmartModels with Leapfrog follow this procedure 1 To build the SmartModel interface first cd to the lib directory in the Cadence tree and execute the lfsmGen command ed S CDS_VHDL 1
74. uses no other switches variables as well as LMC_VLOG to find models LMTYV interface does not support Cadence Supports Cadence fault simulation fault simulation Environment Modifications This section describes environment modifications you need to make if you want to simulate an existing design in either the LMTV SWIFT or Historic SmartModel mode Environment Variables For both modes set the LMC_PATH and LMC_HOME environment variables instead of the LMC_VLOG LAI_OBJ and LAI_LIB environment variables which are ignored by the LMTV interface For more information about user configuration refer to the SmartModel Library Administrator s Manual Command Line Switches The LMTV interface ignores the laiobj and lailib switches regardless of which mode you are using However LMTV does recognize the laiudtmsg and lmudtmsg switches which are equivalent Resistive Strength For SWIFT SmartModel mode only the SWIFT interface reports the true resistive strength of output pins instead of mapping them all to strong as is done in the Verilog XL specific SmartModel Library You might want to modify your expected output accordingly However if you want only a quick comparison and do not want to modify your expected output you can revert to the Verilog XL specific behavior by using the Imoldstr command switch For more information about setting switches refer to Using FlexModels with Verilog XL on page
75. variable 2 To include MemPro testbench interface commands in your design add one of the following lines to your testbench Verilog testbench include mempro_pkg v C testbench include mempro_c_tb h For more information on using the MemPro testbench interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual Oo Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 For information on message levels and message level constants refer to Controlling MemPro Model Messages on page 33 4 There is no need to build a Verilog executable You can use the one from CDS_INST_DIR tools bin by adding CDS_INST_DIR tools bin to your path statement Nn Invoke the Verilog XL simulator to compile and simulate your design as shown in the examples below July 31 2001 Synopsys Inc 81 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide UNIX o verilog testbench Verilog modules MemPro_model_files tincdir SLMC_HOME sim pli sre loadplil swiftpli swift_boot NT gt verilog testbench Verilog_modules MemPro_model_files tincdir SLMC_HOME sim pli sre loadplil swiftpli swift_boot gt Note If you are also using SmartModels or FlexModels in your design you do not need to lo
76. vhd A testbench that instantiates the model and workdir examples vhdl shows how to use basic model commands 2 On NT add the following to your modelsim ini file libsm MODEL_TECH libsm d11 and add the following to your PATH LMC_HOME 1lib pent 1ib This is so MTI can find the slm_mti dll file 3 Update the clock frequency supplied in the model_user_pkg vhd file to correspond to the desired clock period for the model After running flexm_setup this file is located in workdir sre vhd1 model_user_pkg vhd where workdir is your working directory July 31 2001 Synopsys Inc 161 Chapter 8 Using MTI VHDL with Synopsys Models Simulator Configuration Guide 162 4 Add the following to your vsystem ini or modelsim ini file slm_1ib LMC_HOME sim mti 1lib VHDL93 1 5 Compile the FlexModel VHDL files into logical library slm_lib as follows AJP AP AP AP AP AP P P ae mti_path bin vlib LMC_HOME sim mti lib mti_path bin vcom work slm lib SLMC_HOME sim mti src slm_hdlc vhd UNIX mti_path bin vcom work slm lib SLMC_HOME sim mti src slm_hdlc_nt vhd NT mti_path bin vcom work slm lib SLMC_HOME sim mti src flexmodel_pkg vhd mti_path bin vcom work slm lib workdir sre vhdl1 model_user_pkg vhd mti_path bin vcom work slm lib workdir src vhdl model_pkg vhd mti_path bin vcom work slm lib workdir examples vhdl model_fx_comp vhd mti_path bin vcom work slm lib workdir examples vhdl model_fx_mti vhd UNIX mti_
77. your design The model wrapper must map the model s ports to signals in your design Modify SWIFT parameters in the model wrapper as needed Here are some parameter examples for a SmartModel memory model VHDL U1 cyc7150 GENERIC MAP TimingVersion gt cy7c150 DelayRange gt MAX MemoryFile gt mem1 Verilog defparam ul TimingVersion cy7c150 ul DelayRange MAX ul MemoryFile mem1 You can also instantiate SmartModels in schematic capture based systems by using model symbols and attaching values to symbol properties For details on instantiating SmartModels using symbols with QuickSim II refer to Using QuickSim II with Synopsys Models on page 217 20 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 1 Using Synopsys Models with Simulators The SWIFT Command Channel The SWIFT interface specification requires that simulator vendors include a minimal command interface to the SmartModel Library This interface is called the command channel The command channel supports several types of commands e Model Commands on page 21 e SmartBrowser Commands for SmartCircuit Models on page 21 e Session Commands on page 22 Model Commands Model commands affect only a selected model instance Following is a list of the model commands DumpMemory output_file Dumps the current memory image of a model to the specified output file If output_file exists it is overwritt
78. 01 Synopsys Inc 71 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide In SWIFT SmartModel Mode In SWIFT SmartModel mode you can access user defined windows either through lm_monitor_enable or lm_monitor_vec_map The lm_monitor_enable command is provided in SWIFT SmartModel mode for backward compatibility We recommend that you use this command only for existing designs The lm_monitor_vec_map command is intended for use with new designs Follow the same procedure as described in Historic SmartModel Mode on page 64 except that in Step 3 when invoking ccn_report use this value for the y argument y SLMC_HOME special cds verilog swift Accessing Window Elements The way you access SmartModel window elements depends on whether you are running in SWIFT mode or Historic SmartModel mode The following sections provide instructions for both modes In Historic SmartModel Mode In Historic SmartModel mode you can access only scalar window elements You cannot access the vectored memory window elements available in SWIFT SmartModel mode You read and write to predefined window elements using the lm_monitor_enable or lai_enable_monitor commands To access window elements in Historic SmartModel mode follow these steps 1 Enable SmartModel Windows for the model instance either for specific window elements or for all window elements For example to enable SmartModel Windows for instance U4
79. 12 Using QuickSim II with Synopsys Models cece cccccccccscces 217 eed ee ee ee eee er ee ee ee ee eee re eee ee 217 Setting Environment Variables uenenaennnn ununun 217 Using SmartModels and FlexModels with QuickSim H 219 Installing the QuickSim IT SWIFT Interface 0 0000 219 Using SmartModels FlexModels with QuickSim H 221 Schema CAME arrora dra 4 ENE r ee 221 Losic SUBUIAION Ci ccicneeeaeleiesndaeis een ieies ence beeen oneurs 228 Custom OI an och eck pane ond 0o stones bh ead ons ee Sas ees 239 Using Hardware Models with QuickSim H isgcs acs vea dened eee0e Fea des 244 Setting up Hardware Models in QuickSimIT 0 04 245 Using Hardware Models in QuickSim H 02 0 0 eee eee eee 247 Model Ree OW ope 49 0 ia 4 A SAR 249 Registering a Model with Im_model 214 ssi ia deinnee deed vn been bee ewe 250 Modifying a Hardware Model lt 66 cdsnccte ced erxdsenntnaceeewdes 253 Simulating with Hardware Models in QuickSim II 256 lm model Command Referenc ircsricdr sisriciiiecsriisriririiari 264 tmg_to_ts Command Reference ok nbc ae ceeeaeerk rae 267 Appendix A Using VERA with FlexModels sssssssssesssssosssoesoessosesoe 269 CENON ene eee ee ee er te ee ee ee ee ee a ARA 269 Using FlexModels with the VERA UDP Interface 6s0ccscevewssdweasawss 270 July 31 2001 Synopsys Inc 7 Contents Simulator Configuration Guid
80. 2 Sat Jun 22 10 56 50 PDT 1996 Falcon Framework v8 5_2 5 Thu May 30 17 31 43 PDT 1996 Copyright c Mentor Graphics Corporation 1982 1995 All Rights Reserved UNPUBLISHED LICENSED SOFTWARE 252 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS Mentor Graphics software executing under Sun SPARC SunOS Note lm model completed successfully Editing the Symbol During registration the lm_model utility reads the Shell Software to determine the device s input output and I O pin names The utility then flattens all buses to individual bits and generates a Mentor Graphics Design Architect script that creates the symbol The process uses the following rules to create the symbol e All input pins are placed starting in the lower left corner and proceeding upwards e All output pins are placed starting in the lower right corner and proceeding upwards e I O pins are placed for minimizing the symbol s height e All buses are grouped with the least significant bit placed lower on the symbol than the most significant bit e A single grid spacing is left between buses grouped scalar pins input and I O pins and output and I O pins Since symbol standards vary you may need to use t
81. 3 Using Verilog XL with Synopsys Models The following example shows how to instantiation a hardware model TILS299 in this case in a testbench Notice the two defparam statements the definitions of the Timing Version TILS299A MDL and DelayRange MIN parameters in the instantiation override the default definitions in the model v file TILS299 MDL and MAX respectively In this example TILS299A MDL represents a custom timing version that the designer wants to use instead of the default timing version TILS299 MDL Instantiate UUT ModelSource TILS299 hardware model U1 defparam U1 TimingVersion TILS299A MDL defparam U1 DelayRange MIN TILS299 U1 CLK clkw CLR clrw ZAHM UAwW Db HWA OP WBNER OO Q Q He Se SS wes SS Re oS NNN 28 QQ Y N e gz WM vu O HOT M W Q PROD be ee ee nn AW m a R Performance Monitoring You can monitor the performance of a hardware model and append the results to the simulator log file after simulation To enable performance monitoring in the window where you are running the simulator enter the following setenv LM OPTION monitor_performance For more information refer to Performance Monitoring in the ModelSource User s Manual Compiling and Simulating UNIX users accomplish this task by executing the Verilog XL executable previously built referencing the testbench
82. 41s74 SMGC_WD is set to a directory other than user models Model file 74LS74A MDL different from the component name Component output directory user models 74LS74 default output path and directory Command 1m_model user models 741s74 m 74LS74A Example 3 Input directory user models 741s74 MGC_WD is set to user models Model file 74LS74 MDL same as the component name Component output directory user project_xyz 74LS74 default directory non default path Command 1lm_model 741s74 user project_xyz Example 4 Input directory user models 741s74 S MGC_WD is set to user models Model file 74LS74 MDL same as the component name Component output directory user project_xyz latch_7474 non default path and directory Command 1lm_model 741s74 user project_xyz d latch_7474 tmg_to_ts Command Reference The tmg_to_ts utility reads the Shell Software timing files to create a technology file Comments from the Shell Software timing statements are not copied to the technology file You must use the technology compiler tc to compile the technology file that is created by the tmg_to_ts utility before using the technology file in QuickSim II In general you should run the Im_model utility which calls both tmg_to_ts and tc rather than running the stand alone tmg_to_ts utility If you just want to update a model s Technology File you can run Im_model with the Step Timing option For more informatio
83. 5 Using MTI Verilog with Synopsys Models ccccecccccccccccces 111 CE haa a pew on ok ee ke aa 111 Setting Environment Variables 34i sac baceeecdeisus baeseus aeaeed sass 111 Using SmartModels with MTI Verilog skis cei cGen esd coe eed ee ee ew Rae Bee 113 Slanic LN PLE bao ieee ing cans sek ees 4 ee ns 114 Using SmartModels with MTI Verilog on the IBMRS AIX Platform 114 Using FlexModels with MTI Veril g 244 cdbvceae ech dade ee seaweed erdaee 115 Statie Linkime wih LMTY xo eee ooo dee Rage oae boa Gao i eikai e 117 Using MemPro Models with MTI Verilog 4 4 scacdcdeusacucdecd cues 118 mi Le WILEY 250 esh cect ee ene ed hdese tad heehee seen 119 Using Hardware Models with MTI Verilog sciciarecavdaceeiwesins cdawes 120 MTI Verilog UGlities sssrirersrcrdserre srr ed bad ewe KREG REBAR REE 122 Chapter 6 Using Scirocco with Synopsys Models sssesssssosssoesosssosesoe 123 OVEN OW Aa eee eaii iria raea RAEE 123 Setting Environment Variables snssesunssesesseseresseserrerreo 124 Using SmartModels with Scirocco nc cncs bck ed de eeeetadeieseed awed eaks 125 create_smartmodel_lib Command Reference 2 5 c ork iw ee ieesaneredes 126 Using FlexModels with Scirocco s cd ke cabes hase eeeees dud sv eee cdawes 128 Script for Running FlexModel Examples in Scirocco 130 Using MemPro Models with Scirocco c240 lt cicncw eu ddsaaneerddeovass 132 Using MemPro Models in a Testbench os dccasecacviwsicadveasxeiaws
84. 50 or the same assignment can be done as follows define ISR ISR_HIGH ISR_LOW ISR 16h5000 this one statement will access two different and independent memory locations at once later in the simulation you can disable monitoring for the CONTROL register Slm_monitor_vec_unmap CONTROL U1 or you can disable monitoring of all windows in that instance Slm_monitor_vec_unmap U1 July 31 2001 Synopsys Inc 289 Appendix B LMTV Command Reference Simulator Configuration Guide lm_status or lai_status Use these commands to report the current status of the model instance inst_path The report includes the names and values of internal windows Syntax lm_status inst_path lai_status inst_path Arguments inst_path The path name to the SmartModel instance whose status is to be reported Examples The following example shows the output of the lm_status command for model instance U1 Cl gt lm status U1 Note lt gt Model template mem Version not available InstanceName DESIGN U1 TimingVersion MEM 0 DelayRange MAX MemoryFile memory 1 Timing Constraints On SmartModel Instance DESIGN U1 mem MEM 0 at time 1000 0 ns Note SmartModel Windows Description UMEM 2048 2K x 8 Static RAM SmartModel Windows not enabled for this model SmartModel Instance DESIGN U1 mem MEM 0 at time 1000 0 ns 290 Synopsy
85. 6 cflags 191 Characters mapping 192 Characters replacing special 192 Check Shell Software utility 252 Command Channel SWIFT 231 Command interaction QuickSim II 231 Command line switches LMTV 77 switches QuickSim II 230 Commands add_instance 227 228 Synopsys Inc 291 292 Index display 74 lai_command 282 lai_disable_monitor 70 286 lai_dump_file 283 lai_enable_monitor 70 72 73 286 lai_load_file 285 lai_status 70 72 290 lm_command 282 lm_dump_file 283 lm_help 284 lm_load_file 285 lm_log_test_vectors 94 lm_loop_instance 95 lm_monitor_disable 70 286 lm_monitor_enable 70 71 72 73 286 lm_monitor_vec_map 70 71 74 288 lm_monitor_vec_unmap 70 288 lm_status 70 72 290 lm_timing_information 96 lm_timing_measurements 96 lm_unknowns 97 add breakpoint 236 add bus 237 add lists 235 237 add monitors 235 add primitive 228 add synonym 237 add traces 235 ccn_report 71 command channel 21 create_smartmodel_lib 126 145 cyan 173 cysim 174 flexm_setup 25 force 236 genInterface 186 Im_disable_timing_checks 202 214 Im_enable_timing_ checks 202 214 Im_log_test_vectors 202 Im_loop_instance 203 214 Im_model 247 249 250 252 253 255 256 Im_model syntax 264 Im_pam_shortage 203 214 Im_pattern_history 203 214 Synopsys Inc Simulator Configuration Guide Im_timing_ measurements 202 214 lm_unknowns 202 214 Im_vconfig 99 Imc
86. 68 library ieee use 1eee std_logic_1164 all entity TILS299 is generic DelayRange STRING port G2 in std_logic CLR in std_logic SR in std_logic CLK in std_logic SO in std_logic Gl in std_logic SL in std_logic S1 in std_logic QA out std_logic QH out std_logic H inout std logic E inout std logic G inout std logic A inout std_logic C inout std logic B inout std_logic F inout std_logic D inout std_logic end architectur e Hardware a ttribu a ttribu te FOREIGN MODEL_TECH libhm sl te FOREIGN of TILS299 is STRING of Hardware TILS299 MDL begin end Hardware Synopsys Inc architecture is Simulator Configuration Guide Max i hm init July 31 2001 Simulator Configuration Guide Chapter 8 Using MTI VHDL with Synopsys Models MTI VHDL Utilities The following hardware modeler simulator commands are supported in MTI VHDL Im_vectors on off instance_name filename The Im_vectors utility turns on vector logging for the hardware model instance The vectors record stimulus to the input and I O pins and responses from the output and I O pins during simulation Im_measure_timing on off instance_name filename The Im_measure_timing utility causes the modeler to measure timing between an input transition and resulting output tra
87. 73 e Using SmartModels with Cyclone on page 173 e Using Hardware Models with Cyclone on page 174 Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your MemPro installation tree as shown in the following example setenv LMC HOME path_to_models_installation 2 Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example setenv LM LICENSE FILE path_to_product_authorization_file setenv SNPSLMD LICENSE_FILE path_to_product_authorization_file July 31 2001 Synopsys Inc 171 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide 172 You can put license keys for multiple products for example MemPro models and hardware models into the same authorization file If you need to keep separate authorization files for different products use a colon separated list UNIX or semicolon separated list NT to specify the search path in your variable setting Caution Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different licens
88. 79 July 31 2001 Synopsys Inc 77 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide Edits to Design File This section describes edits you need to make to your design file if you want to simulate an existing design in the LMTV SWIFT SmartModel mode gt Note Note that lai_ commands are recognized by the LMTV interface so you do not have to change command names for either mode Model Parameter Names Change the parameter names to the corresponding SWIFT SmartModel mode entries as shown in Table 11 on page 64 Model Names Change the alphabetic parts of model names to all lower case If you use SWIFT UC mode this step is not required Port Names If you have used explicit port naming in your module instantiations that is if you have explicitly mapped each net name to the corresponding port name in the model instantiation statement you do not need to do anything about port names If on the other hand you have used implicit port naming that is if you have listed the nets in the model instantiation statement in the same order as the ports were declared in the v file you need to ensure that your port names conform to the ordering scheme used in the SWIFT SmartModel mode as described in Table 11 on page 64 78 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models Using FlexModels with Verilog XL FlexModels work with Veril
89. Abort User utility to remove the unwanted processes manually Both of these methods release modeling system resources For more information about Imdaemon and the Im utilities refer to the LM family Modeler Manual or the ModelSource User s Manual LM family and ModelSource modeling systems support simulation save and restore capabilities When a save simulation state is performed the state of all hardware models being used by the simulation session is automatically saved into a QuickSim II save directory Similarly restoring the simulation state automatically restores the state of the model as used by the saved simulation including all stored pattern history Attention If you are using Shell Software that contains enhanced features such as model state tracking or when conditions the translation to the resulting technology file may be incomplete and contain compromise statements If you elect to use the technology file instead of the Shell Software during simulation the device may exhibit incorrect timing and or behavior To eliminate this possibility translate the technology file from pre R2 0 Shell Software which does not contain these statements or use the Shell Software directly during simulation by issuing the SIGnal INSTance Ist command on the hardware model instance For more information about this procedure refer to Timing Shell Selection on page 258 Im_model Command Reference The Im_model shell command
90. C Verilog refer to LMTV Command Reference on page 279 July 31 2001 Synopsys Inc 103 Chapter 4 Using NC Verilog with Synopsys Models Simulator Configuration Guide Static Linking with LMTV If you cannot use the Synopsys supplied swiftpli shared library refer to the Cadence documentation for information on using the PLT Wizard to build your own PLI library Synopsys still ships the files needed to build your own PLI These include e edited copy of veriuser c in the LMC_HOME sim pli src directory e LMTV object Imtv o in the LMC_HOME lib platform lib directory If you build your own PLI you will need to edit the veriuser c file to pick up the LMTV header files as follows a After include vxl_veriuser h add include ccl_I1mtv_include h b After add user entries here add include ccl_lmtv_include_code h Using FlexModels with NC Verilog FlexModels work with NC Verilog using a PLI application called LMTV that is delivered in the form of a swiftpli shared library in LMC_HOME lib platform lib If you cannot use the swiftpli refer to Static Linking with LMTV on page 106 To use the prebuilt swiftpli follow this procedure 1 Create a working directory and run flexm_setup to make copies of the model s interface and example files there as shown in the following example SLMC_HOME bin flexm_setup dir workdir model_fx You must run flexm_setup every time you update your F
91. C_HOME sim vss src vss_dummy_calls c vss_dummy_calls 2 Link the MemPro binary into the vhdlsim simulation executable cli ansi s build libs LMC_HOME lib platform lib slm vss o where platform is hp700 or sun4Solaris The new version of vhdlsim you just created must be used when you simulate a design that includes MemPro memory models In order to use vhdldbx on a design that includes MemPro models the vhdlsim you just created must be defined as the first vhdlsim in your UNIX search path 3 For Solaris set the LD_LIBRARY_DATA environment variable as follows setenv LD LIBRARY DATA SYNOPSYS sparcOS5 sim 1lib 4 Create a logical library named slm_lib The default physical library mapping for this is LMC_HOME sim vss lib however you can create slm_lib any where you want Add the following line to your synopsys_vss setup file SLM _LIB SLMC_HOME sim vss 1ib TIMEBASE PS 148 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 7 Using VSS with Synopsys Models 5 Compile the MemPro VHDL files into logical library slm_lib Note that rdramd_pkg vhd is not required unless you are simulating RDRAM MemPro models o vhdlan c w slm lib LMC_HOME sim vss src slm_hdlc vhd vhdlan c w slm lib LMC_HOME sim vss src mempro_pkg vhd vhdlan c w slm lib LMC_HOME sim vss src rdramd pkg vhd gt Note The vhdlan program returns an Error compiling file warning message for rdramd_pkg vhd and reverts to interpreted
92. E To ensure that SWIFT instances are evaluated as primitives you can add to the primitive rule using the add primitive command within DVE In the following example the add primitive command causes all instances of the MODEL property value SWIFT to be evaluated as primitives by QuickSim II o add primitive model noexcept string SWIFT The string SWIFT can be substituted with any other labels that you have registered with the model type of swift Logic Simulation The following sections in this chapter provide information about using SmartModels for logic simulation in the Mentor Graphics s QuickSim II environment For related information refer to the following Mentor Graphics manuals e Common Simulation User s and Reference Manual e Getting Started with QuickSim II Training Workbook e QuickSim II User s Manual 228 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Current Support Levels Please note the following important items before starting a simulation SmartModel Library models currently e Do support the implementation of location maps You can use location maps to install a library anywhere on the system Set an environment variable and a location map variable before using location maps e Do support extended time 64 bit simulations e Do not support the unit delay timing mode Default Timing Mode The default timing
93. FT libraries 76 logic simulation 228 message format 233 message formats 233 pin and bus symbols 222 PLI static linking 104 114 reconfiguring for simulation 232 renaming instances in QuickSIM 237 signal levels 229 status checking 232 support levels 229 SWIFT usage notes for MGC users 221 symbol properties used by SWIFT 223 symbols creating new 239 symbols modifying 239 technology descriptions with QuickSim II 247 timing constraint checks 233 trace messages 233 user defined window elements 70 using with SWIFT simulators 18 Verilog XL libraries 76 July 31 2001 Index warning messages 233 Windows SWIFT mode 72 with Cyclone 173 with MTI VHDL 157 197 with NC Verilog 103 with NC VHDL 206 with Scirocco 125 with VCS 39 with Verilog XL 61 63 with VSS 143 SMILibrary vhd file 197 SMLibrary vhd 207 SMpackage vhd 207 SMpackage vhd file 197 SNPSLMD_LICENSE_FILE environment variable 38 60 102 112 124 142 155 171 196 205 217 Solaris compiling C files 28 SOLV IT 15 Special characters mapping rules 192 replacing 192 SSI_LIB_FILES environment variable 277 State tracking 253 Statements technology file 253 SunOS changing global settings on 184 Support center contacting 14 Support levels SmartModels 229 SWIFT 17 SWIFT Command Channel 21 231 SWIFT interface properties 239 QuickSim II installing 219 symbol properties 222 usage notes for MGC users 221 SWIFT parameters with
94. Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 July 31 2001 Figures run_flex_examples_in_vcs pl Script ssssnsnnu eho ek ees 50 Verilog XL Design FIOW ssreivesrniotar ar EERE 4S KH RES RERES ES 67 Concept Desien FPIOW 4 4546e oh5 9G ohe ds see 8106S e ih ess 445 454 69 The ma vorilog GUase Tre 44d o 30 49 Shee eed eediaes 84 SFI Communication with PLI occa sd csand dawkins deadvawscdauyes 85 run_flex_examples_in_scirocco pl Script v4 saciaxer reer aveseases 131 Cyclone Configuration Guidelines fie ki ehh Ghee de eee ede ee enes 177 ModelAccess for Cyclone Installation Tree 178 Process Flow Chat 655d ce oc eee engia erett tonaka ieuna ai 180 Slang Hardware Model Conceptual Diagram 183 Default synopsys_lm_hw setup File siccacivacscasivadtveasewiass 184 Sample System Dependent Setup File synopsys_Im_hw setup hp700 191 Sample Pin and Bus Symbols 4 6 54 eS hee darko deeds ed eee ans 222 Visible Symbol Propertics onda dc bed oo intro rE ENESE RENED 223 National Semiconductor DP8429 DRAM Controller 242 BRA Pmi Symbols sereprrritinssrd tr iiiaae a aini 244 Sample Component Interface for a Hardware Model 248 Hardware Model Registration nnsuenesann annene 250 Synopsys Inc 9 Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Ta
95. FlexModels 24 with SmartModels 18 Synopsys Inc 301 Index SWIFT_TEMPLATE property 224 swiftpli 61 79 80 81 103 104 106 107 113 115 118 Switches vera_finish_on_end 275 command line QuickSim II 230 constraint mode 230 debug_all 134 LDFLAGS E 277 time scale 230 timing mode 230 VCS Zp4 53 Symbol properties required for simulation 224 Symbols 221 256 alternate selecting 228 buses 222 creation 249 custom 239 editing 253 pins 222 properties 222 registration 249 rules for creating 253 SmartModel creating new 239 SmartModel modifying 239 SYNOPSYS environment variable 141 synopsys_Im_hw setup file 184 synopsys_Im_hw setup sunos file 184 SYNOPSYS_SIM environment variable 124 141 synopsys_vss setup file 129 147 T Technology descriptions 249 Technology files 249 253 264 conversions 254 types 253 Teradyne LASAR with hardware models 36 302 Synopsys Inc Simulator Configuration Guide Test vector logging 261 Test vector logging hardware model example 91 Timescale changing with SmartModels 76 switch with SmartModels 230 Timing checks with hardware models 253 Timing descriptions 249 Timing files 251 Timing measurement with hardware models 91 Timing modes changing 233 default 229 switch 230 Timing shell selection 258 Timing Version 24 TimingVersion property 223 tmg_to_ts command 267 tmg_to_ts converter 249 Tools Admin 220 analysis Mentor Graphics 247 flexm_set
96. For example lmsi logon all To turn off vector logging replace logon with logoff and omit the filename in the above examples VHDL Model Generics with VSS You can also control hardware model behavior using VHDL generics in your hardware model instantiations The nawk script on page 153 creates VHDL wrappers for hardware models with these VHDL generics set to values that are reasonable for most simulations However you can modify the values of the VHDL generics in your model vhd files to suit your verification needs For more information on supported VHDL generics refer to the Synopsys VHDL Simulation Interfaces Manual Following are descriptions of some of the most useful generics July 31 2001 Synopsys Inc 151 Chapter 7 Using VSS with Synopsys Models Simulator Configuration Guide LMSIL TIMING MEASUREMENT You can use the LMSI_TIMING_MEASUREMENT generic to direct where timing values for your simulation session come from There are two legal values ENABLED The hardware modeler measures and records actual pin to pin timing values and passes them to the simulator DISABLED The hardware modeler passes to the simulator the pin to pin timing values from the TMG file This is the default value LMSI_DELAY_TYPE You can use the LMSI_DELAY_TYPE generic to specify whether the hardware modeler returns pin values to the simulator with minimum typical or maximum delays as you can see in the following legal values MINIMUM Retur
97. For example naming a pin A causes both its user pin value and the compiled pin value to be A Changing a PIN property value causes the compiled pin value to track the user pin value Specifically changing the compiled PIN property value disables this tracking mechanism To re enable tracking set the value of the compiled PIN property to null i PIN_NAME Property SmartModel Library symbols include a property called PIN_NAME that is used purely for graphical purposes The PIN_NAME property is provided because SmartModel Library symbols do not completely match the Mentor Graphics requirements for pin names Deleting a PIN_NAME property does not affect model functionality in any way Attention Do not confuse the PIN property with the PIN_ NAME property on SmartModel symbols 240 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Purpose of the pin_map File Use the pin_map file to map custom symbol pins to model pins If your symbol does not have buses then you can use the user pin value and compiled pin value combinations previously described to do this mapping without using the pin_map file If you have bus pins on your symbol then you need to use a pin_map file and ensure that the PKG symbol property is set to the value BUS Following is a general description of the pin_map file which describes both cases TS Note Error messages cite the pin
98. G XL 2 2 1 log file created Jan 8 1997 14 14 00 VERILOG XL 2 2 1 Jan 8 1997 14 14 00 Compiling source file TILS299 v Compiling source file tbench v Runtime ModelAccess for Verilog R2 0 SFI Copyright 1988 1996 Synopsys Incorporated 05 Sep 1996 R3 3a Type for help C1 gt L47 tbench v stop at simulation time 4200 Cl gt Sfinish Cl Sfinish at simulation time 4200 54 simulation events 10 accelerated events 90 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models CPU time 0 4 secs to compile 0 2 secs to link 0 5 secs in simulation End of VERILOG XL 2 2 1 Jan 8 1997 14 15 09 Optional Capabilities During Simulation During simulation you can optionally enable timing measurement and test vector logging Timing Measurement LM family modeling systems can measure input to output propagation delays on a hardware model You enable timing measurement using the command lm_timing_measurements described in lm_timing_measurements Command Reference on page 96 gt Note Timing measurement is not supported for ModelSource 3200 and 3400 The following illustration shows an example of timing measurement for the TILS299 model The six lines of code following SIMULATION run time duration turn on timing measurement measure for 4200 timing units then turn off timing m
99. HOME synopsys smartmodel directory This directory is specified by SMARTMODEL logical name mapping in the setup file Suppresses the generation of warning messages that notify you of any port name mappings A list of SMARTMODEL component names is read from file Names are separated by spaces Only the specified component names are included in the SMARTMODEL component library The model_name is included in the resulting SMARTMODEL component library Repeat this option to specify multiple models Only specified component names are included in the SMARTMODEL component library When issued without options the create_smartmodel_lib command takes all of the files in the LMC_HOME models directory creates and analyzes the VHDL template files and saves them in the LMC_HOME synopsys smartmodel directory If you do not have write permission for LMC_HOME synopsys smartmodel the command terminates with an error message In that case you must use the src_dir option to specify a writable directory in which to place the VHDL templates You must also specify that directory through the SMARTMODEL library mapping in the Synopsys_vss setup file in your current working directory July 31 2001 Synopsys Inc 127 Chapter 6 Using Scirocco with Synopsys Models Simulator Configuration Guide Using FlexModels with Scirocco To use FlexModels with Scirocco follow this procedure 1 If you want the improved performance that comes with bused wrapper
100. Im_procedure call ncsim gt call 1lm_log_test_vectors U0 1 299 VEC July 31 2001 Synopsys Inc 215 Chapter 11 Using NC VHDL with Synopsys Models Simulator Configuration Guide 216 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models 12 Using QuickSim Il with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels and hardware models with QuickSim II The procedures are organized into the following major sections e Setting Environment Variables on page 217 e Using SmartModels and FlexModels with QuickSim IT on page 219 e Using Hardware Models with QuickSim IT on page 244 gt Note MemPro models are not supported on QuickSim II Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel FlexModel and MemPro model installation tree as shown in the following example setenv LMC HOME path_to_models_installation 2 Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example setenv LM LICENSE FILE path_to_product_authorization_file setenv SNPSLMD LICENSE_FILE pat
101. July 31 2001
102. LE DEFAULT work n print OFILE SLM_LIB slm_lib n print OFILE TIMEBASE PS n print OFILE n close OFILE Swork_dir TmpDir DirSep work slm_lib_dir TmpDir S DirSep slm lib mkdir work_dir 0777 mkdir slm_lib_dir 0777 if Platform eq pent source_setup_file cmd c SynopsysHome admin setup environ bat else Ssource_setup_file source SynopsysHome admin setup environ csh Sanalyze_slm_hdle vhdlan noevent w slm lib S lmcHome sim vhpi src slm_hdlc vhd Sanalyze_flexmodel_pkg vhdlan event w slm lib LmcHome sim vss src flexmodel_pkg vhd Sanalyze_model_user_pkg vhdlan event w slm lib version_path src vhdl flexmodel_name _user_pkg vhd Sanalyze_model_pkg vhdlan event w slm lib version_path src vhdl flexmodel_name _pkg vhd Sanalyze_model_prim vhdlan event w slm lib version_path examples vhdl flexmodel_name Sflex_or_c _vss vhd Sanalyze_model_comp vhdlan event w slm lib version_path examples vhdl flexmodel_name Sflex_or_c _comp vhd Sanalyze_model vhdlan event w slm lib version_path examples vhdl flexmodel_name vhd Sanalyze_model_tst vhdlan event S version_path examples vhdl flexmodel_name _tst vhd if Platform eq pent run_file TmpDir DirSep run_scirocco_ flexmodel_name cmd else Srun_file TmpD
103. LMC_HOME 1ib hp700 1ib SHLIB_PATH NT Make sure that 7LMC_HOME7 lib pcnt lib is in the Path user variable Using SmartModels with NC VHDL To use SmartModels with NC VHDL follow this procedure 206 1 Add the following line to your cds lib file to specify the logical library sm_library for SmartModels as shown in the following example DEFINE sm_library sm_library 2 Run the ncshell utility to generate a wrapper for the model that you want to use as shown in the following example neshell import swift into vhdl model work sm library This step produces a wrapper file model vhd and a component declaration model_comp vhd for the specified model in the sm_library work directory Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 11 Using NC VHDL with Synopsys Models If you want to generate wrappers for all SmartModels in your LMC_HOME tree add the all switch to the ncshell invocation In this case ncshell creates one file shell vhd that contains all the model wrappers and another file component vhd that contains the component declarations Q Hint gt AADA_s_aA_Yr NC VHDL also works with wrappers created for Leapfrog If you want to reuse SmartModel wrappers created for Leapfrog use ncvhdl to recompile the SMLibrary vhd and SMpackage vhd files For more information on using SmartModels with Leapfrog refer to Using SmartModels with Leapfrog on page 197 3 Add LIBRARY and USE
104. LMC_HOME synopsys directory Lets you specify the location of the VHDL source files that you create The default location is LMC_HOME synopsys Analyzes the SMARTMODEL library source files vhd files by invoking vhdlan The analyzed files sim and mra files are saved in the LMC_HOME synopsys smartmodel directory This directory is specified by the SMARTMODEL logical name mapping in the setup file Suppresses the generation of warning messages that notify you of any port name mappings See VHDL Reserved Port and Window Names in the VSS Expert Interface Manual for more information about port name mappings Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 7 Using VSS with Synopsys Models modelfile file A list of SMARTMODEL component names is read from file Names are separated by spaces Only those component names specified are included in the SMARTMODEL component library model modelname Each specified modelname is included in the resulting SMARTMODEL component library Repeat this option to specify multiple models Only those component names specified are included in the SMARTMODEL component library Description The create_smartmodel_lib command if issued without options uses as input all of the files in the LMC_HOME models directory creates and analyzes the template files and saves them in the LMC_HOME synopsys smartmodel directory If you do not have write permission for LMC_HOME synopsys s
105. LS299 CLK CLR y Gl G2 SO Sl SL SR GA OH A B Cup Dig Bp EF ap Gy Be Pin declarations input CLK input CLR input Gl input G2 input SO input S1 input SLi input SR output QA reg QA_ PULL reg QA STRONG assign pull0 pulll QA QA PULL 86 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models assign QA QA STRONG output QH reg QH_ PULL reg QH_ STRONG assign pull0 pulll QH QH PULL assign QH QH__STRONG inout A reg A PULL reg A__ STRONG assign pull0 pulll A A PULL assign A A__STRONG inout B reg B_ PULL reg B_ STRONG assign pull0 pulll B B_ PULL assign B B__STRONG inout Cae reg C__ PULL reg C__STRONG assign pull0 pulll C C__PULL assign C C__STRONG inout D reg D_ PULL reg D__STRONG assign pull0 pulll D D_ PULL assign D D__STRONG inout E 3 reg E_ PULL reg E_ STRONG assign pull0 pulll E E__PULL assign E E__STRONG inout ES lt 3 reg F_ PULL reg F__ STRONG assign pull0 pulll F F_ PULL assign F F__STRONG inout G reg G_ PULL reg G_ STRONG assign pull0 pulll G G_PULL assign G G__STRONG inout H reg H_ PULL reg H__STRONG assign pull0 pulll H H_ PULL assign H H__STRONG Parameter declarations paramet
106. MC_HOME 1lib hp700 1lib libswift s Logic Modeling s SmartModel SWIFT software IBM RISC System 6000 Ne Ne Ne Ne July 31 2001 Synopsys Inc 163 Chapter 8 Using MTI VHDL with Synopsys Models Simulator Configuration Guide libswift SLMC_HOME 1lib ibmrs lib swift o Logic Modeling s SmartModel SWIFT software Sun4 Solaris libswift SLMC_HOME 1ib sun4Solaris lib libswift so Logic Modeling s SmartModel SWIFT software Sun4 SunOS 7Cdo setenv LD_LIBRARY_PATH SLMC_HOME 1ib sun4Sun0S lib 7Cand run vsim swift Logic Modeling s SmartModel SWIFT software Windows NT libswift LMC_HOME 1ib pcnt lib libswift dll gt Note This UNIX like syntax is valid on NT workstations as well as all UNIX platforms i 4 Compile the MemPro VHDL files into your local slm_lib a If you are simulating RDRAM MemPro models o vcom work slm lib SLMC_HOME sim mti src slm_hdlc vhd vcom work slm lib LMC_HOME sim mti src mempro_pkg vhd vcom work slm lib LMC_HOME sim mti src rdramd_pkg vhd o o b If you are not simulating RDRAM MemPro models vcom work slm lib SLMC_HOME sim mti src slm_hdlc vhd vcom work slm lib LMC_HOME sim mti src mempro_pkg vhd o 5 After generating a model using MemPro compile the VHDL code for the model a If you are simulating SDRAM Module MemPro models you
107. Models This is the mode intended for primary use Use this mode if you are implementing a new design using the SWIFT SmartModel Library if you are a new Verilog XL user or if you want to transition your existing design into this mode Two sets of v shells support SWIFT SmartModel mode swift and swift uc With swift uc module names and attribute names are provided in all uppercase The two sets of v shells provide compatibility with most third party tools Historic SmartModel Mode In Historic SmartModel mode the models you instantiate have the characteristics of the Verilog XL specific SmartModels Historic SmartModel mode is provided only for backward compatibility for designs that use models from the Verilog XL specific SmartModel Library Use the Historic SmartModel mode only if you are continuing with an older design that was captured using the Verilog XL specific SmartModel Library lt gt Note You must use the same mode throughout a design You cannot mix modes within a design Table 11 lists the different characteristics of the SWIFT and Historic SmartModel modes Table 11 Characteristics of Historic and SWIFT SmartModel Modes SWIFT SmartModel Mode Historic SmartModel Differences swift swift uc Mode Model Attributes Timing Version TIMINGVERSION COMPONENT ModelType MODELTYPE MODELTYPE DelayRange DELAYRANGE RANGE MemoryFile MEMORYFILE MEMORYFILE JEDECFile JEDECFILE JEDECFILE SCFFil
108. NPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example o setenv IM LICENSE FILE path_to_product_authorization_file o setenv SNPSIMD_LICENSE FILE path_to_product_authorization_file July 31 2001 Synopsys Inc 205 Chapter 11 Using NC VHDL with Synopsys Models Simulator Configuration Guide You can put license keys for multiple products for example FlexModels and MemPro models into the same authorization file If you need to keep separate authorization files for different products use a colon separated list UNIX or semicolon separated list NT to specify the search path in your variable setting a Caution Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you use for snpslmd based authorizations 3 Make sure that NC VHDL is set up properly in your environment 4 Depending on your platform set your load library variable to point to the platform specific directory in LMC_HOME as shown in the following examples Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD_LIBRARY_PATH LMC_HOME 1ib x86_linux 1lib LD_LIBRARY_PATH AIX setenv LIBPATH LMC_HOME 1ib ibmrs 1ib LIBPATH HP UX setenv SHLIB_ PATH
109. Place the hardware model in the testbench file and invoke the simulator For this TILS299 example we used the Synopsys VHDL Debugger as follows vhdldbx t ns TB _TILS299 The ns argument invokes the simulator with nanosecond timesteps 150 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 7 Using VSS with Synopsys Models VSS Utilities The following hardware modeler simulator commands are supported in VSS Imsi list devices ids You can use the Imsi list devices command to list all hardware model instances by device name and the Imsi list ids command to list all hardware model instances by id name For example Imsi list devices device name id instance name logging TILS299 0 TB_TILS299 U0 OEr Imsi list ids id device name instance name logging 0 TILS299 TB_TILS299 U0 Off You can also log test vectors for the hardware model To log by ID number specify an id and a filename The extension TST is appended to the vector file name If no file name is specified VSS writes to a file named device_name id TST For example lmsi logon id filename To log vectors by instance name specify an instance_name and filename The extension TST is appended to the output file name For example lmsi logon instance_name filename To log vectors for all hardware model device instances specify all A log file is created for each instance The output files are named device_name id TST
110. Pro models and hardware models with NC Verilog The procedures are organized into the following major sections e Setting Environment Variables on page 101 e Using SmartModels with NC Verilog on page 103 e Using FlexModels with NC Verilog on page 104 e Using MemPro Models with NC Verilog on UNIX on page 107 e Using Hardware Models with NC Verilog on page 108 Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel FlexModel and MemPro model installation tree as shown in the following example setenv LMC HOME path_to_models_installation July 31 2001 Synopsys Inc 101 Chapter 4 Using NC Verilog with Synopsys Models Simulator Configuration Guide 2 Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example setenv LM LICENSE FILE path_to_product_authorization_file setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_file You can put license keys for multiple products for example SmartModels and hardware models into the same authorization file If you need to keep separate authorization files for different products use a colon separated list
111. STance propagate command turns on unknown propagation for all instances of the selected components The modeling system propagates the unknowns through the model using multi sequence pattern play The SIGnal INSTance nopropagate command turns off unknown propagation for all instances of the currently selected component which is the default behavior When unknown propagation is on two pattern sequences are used by default However you can specify up to twenty additional sequences with the default_propagation p number command for a total of 22 sequences You can also specify the value of the seed for the random sequence generator with the random_seed p seed command The value of the seed is 0 by default but any number from 0 to 65 535 can be used For example you can issue the following Sig inst propagate sig inst default_propagation p 8 sig inst random seed p 7896 These commands turn unknown propagation on for all instances of the selected components The modeling system plays a total of ten sequences the primary secondary and eight additional sequences per instance to the device and uses the random sequence seed 7 896 These Signal Instance commands perform the same function as the Shell Software on_unknown statement Note that explicit Shell Software settings override any Signal Instance commands except for when the SIGnal INSTance nopropagate command is used This exception allows the simulator to turn off unknown propagation
112. SYNOPSYS Simulator Configuration Guide for Synopsys Models Simulator Configuration Guide Copyright 2001 Synopsys Inc All rights reserved Printed in USA Information in this document is subject to change without notice SmartModel ModelAccess ModelTools SourceModel Library LM 1200 and Synopsys Eaglei are registered trademarks MemPro MemSpec MemScope FlexModel LM family LM 1400 Logic Model ModelSource and SourceModel are trademarks of Synopsys Inc All company and product names are trademarks or registered trademarks of their respective owners Synopsys Inc July 31 2001 Simulator Configuration Guide Contents Contents PERCE 64 6464 Hehe Ra OE ARDEA RYE aEKE nud OLSON SEEOLADA CARO ESSE EERE 11 About This NIN eb 5854 5565s e505 55a a8 8G 0 5s 11 TCE a i ny heh GTN Sed TAR h ede odes 11 Some Hyperlioks May Not Work sb ccioneesie eS k0s ded Ke Kee ee Re eee 12 Mangal OVEIVIEW ane en eae oe eee ee ence rA A A N 12 Typographical and Symbol Conventions 4a donee 6564 ed nasere reena 13 Goine Holp 5 xed ng ob4ddHRKS SOROS ARIRE EEE RR ORNS ESES 14 The Synopsys I oa 5s a he eS ee oh ee es 15 Synopsys Common Licensing SCL Document Set 15 Bo a ee ee ee ee eee ee ee eee E eer eee eee kee eee eee ee ee ee 16 Chapter 1 Using Synopsys Models with Simulators ccc ccc cece ccc cee scene 17 Ca ae i he he ee ee a ees 17 Using SmartModels with SWIFT Simulators 0 0 0 0 0 e
113. Scirocco VHDL Files 3 05 c60seseshaeeeeesy aes syases 128 FlexModel VSS VHDL Files 6a cba eho oie rri eee ewe dace Eaa 146 FlexModel MTI VHDL Piles oo vidos cueecsese beswteus Keawadvaae s 161 Rules for Special Character Mapping g4ccescduseaasen esses haees 192 FlexModel Dey FL ee ssrsriririeikrtd tibi tatid tp AEAN 208 Symbol Properties used by SWIFT Models 2 55 223 Symbol Properties Required for Simulation 20055 224 Optional Symbol Properties oy oo 64 4h 6601S ES ee Rd eae eens 225 ON Siate Vales oc ev ko ONS HES SASHES UR ERPI E PRADEES ESA 229 QuickSim II Command Interaction 4466 06c00 6s nasedw shade coe wen 231 Elements in a TIBPAL22V 10 Devic vg cade ide eiene eed ednstenans 231 Mentor Graphics Vendor CPU Operating System Suffixes 245 mami Component Directory lt cs52cse cies neste ee enue eae oie wes 251 Shell Software to Technology File Conversion 000085 254 Signal Instance Command Summary 0 cee eee eee 257 FlexModel Files Containing VERA UDF Information 270 VERA Hender PIES Sen ee rane ae er Gr mee rg ee E Gre a e ee 271 FlexModel VERA PUGS 45 00ee8daeiedeed ee od danke eHVaaoevdaws 274 Synopsys Inc July 31 2001 Simulator Configuration Guide Preface Preface About This Manual This manual contains procedures for using Synopsys models with the most widely used simulators The scope includes the following types of models e Smar
114. System Suffix vco Sun SPARC Solaris ss5 HP 9000 Series 700 hpu Intel Pentium Windows NT ixn When the script completes the following message appears on the screen 1 Invoke the Mentor Installation tool gt cd an_idea_tree install8 gt install July 31 2001 Synopsys Inc 245 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide tS Note 2 From the Mentor Graphics Install tool window gt Admin gt Rebuild MGC Tree 3 In the Prompt window enter the proper path to the MGC_HOME to be rebuilt Click on gt OK 4 Rebuild MGC Tree Results window appears AFTER Rebuild completes Click on gt OK 5 From the Mentor Graphics Install tool window gt File gt Exit 6 Install Warning window appears Click on gt OK This process rebuilds the Mentor tree with the newly installed hardware modeler package Rebuilding the Mentor Graphics Tree The final step is to rebuild the Mentor Graphics tree using the Mentor Graphics installation script Using install version C 1 246 1 To invoke this program enter the following cd mgc_home install8 install 2 When the install tool appears use the mouse to select the Admin gt Rebuild MGC Tree pull down menu item The program prompts you to enter the MGC tree pathname If you have defined MGC_HOME that path will appear otherwise enter the full pathname of the Mentor Graphi
115. T SmartModel Library but they use different sets of model v files vshells to invoke the models For each mode there is a specific directory shown in Table 12 that contains model v files to be referenced by that mode You determine the mode that will be used both during design capture and when you invoke Verilog XL as follows 1 During design capture use the appropriate model attributes port ordering command channel memory access user defined windows module names and resistive strength output expectations shown in Table 11 July 31 2001 Synopsys Inc 65 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide 2 When you invoke Verilog XL reference the appropriate model v directory using the y switch as described in Concept Design Capture on page 68 Table 12 model v Directories Mode Directory SWIFT SmartModel Mode LMC_HOME special cds verilog swift SWIFT SmartModel Mode Uppercase LMC_HOME special cds verilog swift uc Historic SmartModel Mode LMC_HOME special cds verilog historic Capturing and Simulating the Design Capturing and simulating the design in Verilog XL involves the following steps each of which is described in detail in this section e Verilog XL Design Flow on page 66 e Preparing to Use Verilog XL on page 67 e Verilog XL Design Capture on page 67 e Concept Design Capture on page 68 e Concept Procedure
116. Table 33 FlexModel Files Containing VERA UDF Information File Name Description Location vera_user c Source file containing table of UDF LMC_HOME sim vera src functions used by FlexModels vera_slm_pli o Object file for VCS and Verilog XL This LMC_HOME lib platform lib file contains the compiled code for the UDF functions used by FlexModels vera_slm_mti o Object file for MTI Verilog and MTI LMC_HOME lib platform lib VHDL This file contains the compiled code for the UDF functions used by FlexModels When building the VERA dynamic library you need to compile the vera_user c file and link the object file vera_slm_pli o or vera_slm_mti o for the simulator you are using 6G Attenion If you are building the VERA dynamic library for Verilog on Solaris do not use the B symbolic Using this switch results in unresolved symbol warnings For more information on building the VERA dynamic library refer to the UDF information in the VERA System Verifier User Manual 270 Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix A Using VERA with FlexModels Linking VERA with Verilog Simulators For details on how to link Vera with Verilog simulators using the PLI refer to the README file in the VERA installation directory SVERA_HOME 1ib vlog README In the instructions for Including Your Own C Code UDF with VERA at the end of the README file 1 Su
117. Verilog on UNIX MemPro models work with NC Verilog using a PLI application called LMTV that is delivered in the form of a swiftpli shared library in LMC_HOME lib platform lib If you cannot use the swiftpli refer to Static Linking with LMTV on page 108 To use the prebuilt swiftpli follow this procedure 1 To include MemPro testbench interface commands in your design add one of the following lines to your testbench Verilog testbench include mempro_pkg v C testbench include mempro_c_tb h For more information on using the MemPro testbench interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual N Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 For information on message levels and message level constants refer to Controlling MemPro Model Messages on page 33 Oo There is no need to build a Verilog executable You can use the one from CDS_INST_DIR tools bin by adding it to your path statement 4 Invoke the NC Verilog simulator to compile and simulate your design as shown in the example below neverilog testbench Verilog_modules MemPro_model_files incdir SLMC_HOME sim pli srce loadplil swiftpli swift_boot lt gt Note If you are using ncelab and ncsim use the loadplil switc
118. _enable_timing_checks device_name s Enables timing checks for hardware models Im_disable_timing_checks device_name s Disables timing checks for hardware models Im_unknowns option value device_or_pin Determines how unknown values are handled by hardware models Supported options include propagate yes no e value previous high low e sequence_count 0 20 e random_seed 0 65535 e device_or_pin Im_loop_instance instance_name Makes the hardware modeler enter loop mode where it continually replays the pattern history of the specified instance Im_pam_shortage actions save sleep finish free suspend drop_faults sleep_minutes n sleep_count n save_file filename Lets you specify the action the hardware modeler is to take when it has used up most of the available pattern memory Im_pattern_history device_name s Saves the pattern memory for a private device instance 214 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 11 Using NC VHDL with Synopsys Models Examples You can use any of these utilities by calling them from VHDL code or invoking them from the debugger prompt with an lm_procedure call Example call from VHDL code Variable ret Natural ret 1lm_log_test_vectors U1 1 U1 VEC wait for 800 ns ret 1lm_log_test_vectors U1 0 U1 VEC Example invocation from the debugger prompt with
119. _swift_templates 39 42 Imsi list 136 Imsi logon 136 Imsvg 99 LMTV 279 LMTV SmartModel windows 70 Imvc_template 55 ncelab 210 ncshell 206 ncsim 207 neverilog 109 nevhdl 207 nologvectors signal instance 261 propagation 259 reg_model 240 249 256 reread modelfile 239 restore state 238 save state 238 scsim 134 signal instance 231 256 261 262 264 simv 278 sm_entity 157 160 tmg_to_ts 249 tmg_to_ts syntax 267 unknown handling 259 vcom 159 162 VERA 275 vhdlan 129 134 vhdlsim 147 vlib 159 vsim 159 163 Comments submitting 16 COMP property 225 Compiling C files AIX 28 HP UX 28 Linux 29 NT 29 Solaris 28 July 31 2001 Simulator Configuration Guide Component interface 249 Component registration 240 Concept procedure 69 Constraint mode switch 230 Conversions shell software 254 technology file 254 Converter tmg_to_ts 249 create_smartmodel_lib command 126 145 Custom symbols 239 mapping 241 cyan command 173 Cyclone elaboration warnings with hardware models 189 setup options with hardware models 190 with FlexMocdels 173 with MemPro models 173 with SmartModels 173 cylab 4 state in 189 cysim command 174 cysim 4 state in 189 D debug_all switch 134 Declarations variable 253 defparam statement with hardware models 88 Delay files 253 DelayRange 24 Delays propagation 253 Descriptions functional 247 249 graphical 247 249 technology 249 timing 249 Descriptors de
120. _unmap DATA U1 end if ADDR hx Sdisplay Warning Multiple simultaneous transactions end July 31 2001 Synopsys Inc 75 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide Customizing Model Timing You can customize the timing of SmartModels by changing the timescale or creating custom timing files Changing the Timescale As with the Verilog XL specific SmartModel Library you can change the timescale of SmartModels from the default of 100 ps picoseconds time_units and 100 ps precision defined in the module definitions These values are specified by the first line of the module definition as shown in the following example timescale 100 ps 100 ps For both the SWIFT and Historic SmartModel modes to change the timescale you must copy the affected model v files into a separate directory Then modify each timescale compiler directive to the desired value When invoking the simulator use the y switch to indicate the path to the directory that contains your modified model v files Creating Custom Timing Files You can create and use custom timing files in both the SWIFT and Historic SmartModel modes The procedure is the same for both For more information on User Defined Timing refer to the SmartModel Library User s Manual Simulating an Older Design Using LMTV If you have an older design that was created using the Verilog XL specific Sma
121. able on the network verifySetup reports the error o verifySetup Copyright 1988 1996 Synopsys Incorporated 05 Sep 1996 R1 0 xx xx Environment Setup User home home klt MA_CY tools lmc sms ma_cyclone LM include directory tools lmc sms include IM library directory tools lmc sms lib sun4 solaris CY include directory tools cyclone sparcOS5 cyclone include xx x x Setup Files Modeler engineeringl SFI ERROR modeler not responding Message Number 972 Running geninterface The genInterface program takes hardware model Shell Software files as input and creates the following files e A VHDL shell for each hardware model you specified e A dynamically linkable C library which is used in communicating simulator requirements to from the hardware modeling system via the hardware modeling Simulator Function Interface software July 31 2001 Synopsys Inc 179 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide With the output of genInterface you proceed as with any other VHDL input by compiling the hardware model VHDL files elaborate and analyze along with your other VHDL design files and then simulating the design Figure 9 gives an overview of the entire process and the following sections describe each step in detail Invoke genInterface from the directory in which you want the interface files to be created On the command line specify the hardware mo
122. ad the swiftpli again since the same library is used to enable all three types of models in Verilog XL Static Linking with LMTV If you cannot use the Synopsys supplied swiftpli shared library refer to the Cadence documentation for information on using the PLT Wizard to build your own PLI library Synopsys still ships the files needed to build your own PLI These include e edited copy of veriuser c in the LMC_HOME sim pli src directory e LMTV object Imtv o in the LMC_HOME lib platform lib directory e C Pipe shared library slm_pli_dyn ext in the LMC_HOME lib platform lib directory If you build your own PLI you will need to edit the veriuser c file to pick up the LMTV header files as follows a After include vxl_veriuser h add include ccl_lmtv_include h b After add user entries here add include ccl_lmtv_include_code h 82 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models Using Hardware Models with Verilog XL This section describes how to configure Release 3 5a of ModelAccess for Verilog ModelAccess is the software you use to interface hardware models with the simulator To dynamically link the SFI with Verilog XL you must have version 2 8 or later of Verilog XL on UNIX and version 3 0 on NT You also need Release 3 5a of ModelAccess for Verilog The hardware modeling information is present
123. all use slm lib model_user_pkg all oA WP OP o For example you would use the following statement for the tms320c6201_fx model use slm lib tms320c6201_pkg all use slm lib tms320c6201_user_pkg all 9 Instantiate FlexModels in your design defining the ports and generics as required refer to the example testbench supplied with the model You use the supplied bus level wrapper model vhd in the top level of your design to instantiate the supplied bit blasted wrapper model_fx_vss vhd Example using bus level wrapper model vhd without timing Ul model generic map FlexModelID gt TMS INST1 port map model ports July 31 2001 Synopsys Inc 147 Chapter 7 Using VSS with Synopsys Models Simulator Configuration Guide Example using bus level wrapper model vhd with timing Ul model generic map FlexModelID gt TMS INST1 FlexTimingMode gt FLEX_TIMING_MODE_ON TimingVersion gt timingversion DelayRange gt range port map model ports 10 Compile your testbench as shown in the following example vhdlan testbench 11 Invoke the VSS simulator as shown in the following example vhdlsim design Using MemPro Models with VSS To use MemPro models with VSS follow this procedure Note that on Solaris VSS requires the Sunsoft compiler and Solaris 2 5 or later 1 Compile a dummy module to force linking of CLI library functions cli ansi s add cf LM
124. ance command to instantiate a part in the Schematic Editor as shown in the following minimal command add instance LMC_HOME special qsim symbols The symbol name and TimingVersion property value can also be included on the same line as follows All punctuation marks are required Sadd_instance SLMC_HOME special qsim symbols TimingVersion July 31 2001 Synopsys Inc 227 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide If the Timing Version property value is not specified the default timing version is activated If a symbol is not specified when applicable the default is used The defaults are positive for logic version and pin for symbol type Selecting Alternate Symbols When there are DeMorgan equivalent symbols the positive version is the default Specify NEG as the symbol name to get the negative logic symbol if desired as follows add instance LMC_HOME special qsim symbols tt100 NEG TimingVersion SN74AS00 When activating parts manually remember that the pin symbol is the default when both pin and bus symbols are available Specify the bus symbol if desired as follows add instance SLMC_HOME special qsim symbols mc68030_hv BUS TimingVersion MC68030 33 Use the Mentor Graphics Design Viewpoint Editor DVE to set the primitive type for SWIFT in DV
125. and file MCF when the MCF is configured with a particular timing mode For more information about configuring SmartCircuit models of FPGA and CPLD devices refer to the SmartModel Library User s Manual Time Scale Switch Use the time_scale switch to adjust time values delays and checks to the desired resolution by specifying the time scale in nanoseconds ns The default is 0 1 ns Use the following syntax when setting this switch time_scale timescale Constraint Mode Switch Use the constraint_mode switch to enable or disable timing constraint checking The default is off Any value other than off causes a model to perform constraint checking Use the following syntax when setting this switch constraint_mode off state_only messages 230 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models QuickSim Il Command Interaction There are many QuickSim II simulator commands that interact with SmartModels in a design Table 27 lists some of the QuickSim IT commands that affect SmartModels Table 27 QuickSim Il Command Interaction QuickSim IT Command Effect on SmartModels INITIALIZE Causes a model to reevaluate until the simulation reaches DC stability It will not reset the model or set internal values to the state_value specified SIGNAL INSTANCE Reports the status of selected instances with the swift_dump parameter
126. arated list UNIX or semicolon separated list NT to specify the search path in your variable setting 8 Caution 112 Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you use for snpslmd based authorizations 4 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv LM DIR hardware_model_install_path sms 1m_dir setenv LM LIB hardware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly Depending on your platform set your load library variable to point to the platform specific directory in LMC_HOME as shown in the following examples Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD LIBRARY PATH LMC_HOME 1lib x86_linux lib LD_LIBRARY_PATH AIX setenv LIBPATH LMC_HOME 1ib ibmrs 1ib LIBPATH HP UX setenv SHLIB PATH LMC_HOME 1ib hp700 1ib SHLIB_PATH NT Make sure that 7LMC_HOME lib pcnt lib is in the Path user variable Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 5 Using MTI Verilog with Synopsys Models Using SmartModel
127. archive library can be found at HP UX LMC_HOME 1ib hp700 1ib libfmi_ar a Solaris SLMC_HOME 1ib sun4Solaris 1lib libfmi_ar a Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 10 Using Leapfrog with Synopsys Models You must create a new archive that includes the MemPro archive library table file declaration object file and your archive Detailed instructions for this process can be found in Foreign Model Integration in the Cadence Leapfrog C Interface User Guide As shown in the following example you must combine the contents of the MemPro library table file with your own FMI application library table include lt fmilib h gt extern fmiModelTableT CpipeModelTable extern fmiModelTableT myFMITable fmiLibraryTableT fmiLibraryTable Cpipe CpipeModelTable myFMI1ib myFMITable 0 0 Link the MemPro archive library with the new library table object file and any other FMI application object files you wish to include following the instructions in the Cadence C Interface User Guide The following examples show compiling the library table object files and linking MemPro libfm_ar a with the library table object file and the FMI application you developed shown in the examples as new_FMI_table o and your_archive a HP UX bin cc D_NO_PROTO c Z I CDS_VHDL include new FMI table c bin ld b o libfmi sl new_FMI_table o your_archive a LMC_HOME lib hp700 lib libfmi_ar a Sol
128. ardware model installation tree Similarly hyperlinks to other books installed in LMC_HOME will only work in that location To work around this limitation you can visit the Synopsys Web site and navigate to the latest documentation for all Synopsys models http www synopsys com products Im doc Manual Overview This manual contains the following chapters Preface Chapter 1 Using Synopsys Models with Simulators Chapter 2 Using VCS with Synopsys Models Chapter 3 Using Verilog XL with Synopsys Models Chapter 4 Using NC Verilog with Synopsys Models Chapter 5 Using MTI Verilog with Synopsys Models Chapter 6 Using Scirocco with Synopsys Models Chapter 7 Using VSS with Synopsys Models 12 Describes the manual and lists the typographical conventions and symbols used in it Tells how to get technical assistance Basic information for configuring and instantiating SmartModels FlexModels MemPro models and hardware models for use in hardware simulators How to configure SmartModels FlexModels MemPro models and hardware models for use with VCS Includes a script that you can use to run FlexModel example testbenches in VCS How to configure SmartModels FlexModels MemPro models and hardware models for use with Verilog XL How to configure SmartModels FlexModels MemPro models and hardware models for use with NC Verilog How to configure SmartModels FlexModels MemPro models and hardware mode
129. ardware models with MTI VHDL The procedures are organized into the following major sections e Setting Environment Variables on page 155 e Using SmartModels with MTI VHDL on page 157 e Using FlexModels with MTI VHDL on page 160 e Using MemPro Models with MTI VHDL on page 163 e Using Hardware Models with MTI VHDL on page 165 Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel FlexModel and MemPro model installation tree as follows o setenv LMC HOME path _ to models_ installation 2 Make sure that MTI VHDL is set up properly in your environment 3 Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example o setenv LM LICENSE FILE path_to_product_authorization_file o setenv SNPSLMD_LICENSE_ FILE path_to_product_authorization_file July 31 2001 Synopsys Inc 155 Chapter 8 Using MTI VHDL with Synopsys Models Simulator Configuration Guide You can put license keys for multiple products for example SmartModels and hardware models into the same authorization file If you need to keep separate authorization files for different produ
130. ardware models you are using Note that you cannot use any model v files that might have existed prior to your use of ModelAccess for Verilog All model v files must be newly generated For each hardware model both UNIX and Windows NT users issue this command at the operating system prompt Imvsg d destination_model MDL The complete syntax of the Imvsg command is provided in Imvsg Command Reference on page 99 84 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models Using Hardware Models To instantiate hardware models in Verilog XL ModelAccess for Verilog maps the Cadence PLI to the Simulator Function Interface SFI as shown in Figure 5 For information about the SFI refer to the Simulator Integration Manual ModelSource System SFI MEE ModelAccess for Verilog XL PLI Interface E Synopsys f __ Cadence Verilog XL Figure 5 SFI Communication with PLI ModelAccess for Verilog Methodology To simulate with hardware models using ModelAccess for Verilog consists of these tasks e Simulation Example on page 86 e Creating the Model Shell on page 86 e Instantiating the Hardware Model on page 88 e Performance Monitoring on page 89 e Compiling and Simulating on page 89 e Examining the Output verilog log File on page 90 July 31 2001 Synopsys Inc 85 Chapter 3 Using Verilog XL with Synop
131. ariables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel FlexModel and MemPro model installation tree as follows setenv LMC HOME path_to_models_installation 2 Set the SYNOPSYS variable to point to the VSS installation directory as follows setenv SYNOPSYS VSS_installation directory 3 Source the environ csh VSS environment file For VSS version 1998 08 1 and earlier use this path source SYNOPSYS admin install sin environ csh July 31 2001 Synopsys Inc 141 Chapter 7 Using VSS with Synopsys Models Simulator Configuration Guide For VSS version 1999 05 and later use this path source SSYNOPSYS admin setup environ csh Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example setenv LM LICENSE FILE path_to_product_authorization_file setenv SNPSLMD LICENSE_FILE path_to_product_authorization_file You can put license keys for multiple products for example SmartModels and hardware models into the same authorization file If you need to keep separate authorization files for different products use a colon separated list UNIX or semicolon separated list NT to specify the search path in your variable setting LS Caution
132. aris opt SUNWspro bin cc c KPIC I CDS_VHDL include new_FMI_table c opt SUNWspro bin cc G o libfmi so new_FMI_table o your_archive a LMC_HOME lib sun4Solaris lib libfmi_ar a 2 Set up the library search path to locate the MemPro shared library Attention You must add the MemPro shared library to the beginning of your SHLIB_PATH or LD_LIBRARY_PATH contents If the MemPro shared library is added to the tail of the path list the library search order will be incorrect and Leapfrog will not simulate properly HP UX setenv SHLIB PATH SLMC_HOME 1ib hp700 1ib SHLIB_PATH July 31 2001 Synopsys Inc 199 Chapter 10 Using Leapfrog with Synopsys Models Simulator Configuration Guide Solaris setenv LD LIBRARY PATH SLMC_HOME 1ib sun4Solaris 1lib LD LIBRARY PATH 3 Create a logical library named slm_lib The default physical library mapping for this is LMC_HOME sim leapfrog lib If you do not want to install the library in the LMC_HOME tree you can create it in any other location Add the following line to your cds lib file define slm lib LMC_HOME sim leapfrog 1lib 4 Compile the MemPro VHDL files into logical library slm_lib Note that rdramd_pkg vhd is not required unless you are simulating RDRAM MemPro models o cv w slm lib S LMC_HOME sim leapfrog src slm_hdlc vhd cv w slm lib IMC_HOME sim leapfrog src mempro_pkg vhd cv w slm lib LMC_HOME sim leapfrog src rdramd pkg vhd o 5 After generatin
133. artModel component In the VHDL design file that uses SmartModel components enter the following library and use clauses library SMARTMODEL use SMARTMODEL components all The library logical name SMARTMODEL must be mapped to appropriate directories in your synopsys_vss setup file 7 Add the following line to your synopsys_vss setup file TIMEBASE PS July 31 2001 Synopsys Inc 143 Chapter 7 Using VSS with Synopsys Models Simulator Configuration Guide 8 Instantiate SmartModels in your VHDL design For information on required configuration parameters and instantiation examples refer to Using SmartModels with SWIFT Simulators on page 18 9 Compile your testbench as shown in the following example vhdlan testbench 10 Invoke the VSS simulator as shown in the following example vhdlsim design For information about vhdlsim and the VHDL debugger refer to the VSS User s Guide create_smartmodel_lib Command Reference The command reference for create_smartmodel_lib is as follows Syntax create_smartmodel_lib nc create srcdir dirpath analyze nowarn modelfile file model model_name Arguments NC create src_dir dir analyze nowarm 144 Displays the usage and all the command line options of the utility Suppresses the Synopsys copyright message Creates the VHDL source files vhd files for the SMARTMODEL library and saves the source files in the
134. ate yes no When yes the default enables the on_unknown propagate statement if there is one in the model s options file for example TILS299 OPT for the specified instance or pin or for all hardware model instances in the simulation Set July 31 2001 Synopsys Inc 97 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide propagate no if you want to disable or override the on_unknown propagate statement in the OPT file for a specific instance or pin TS Note If there is no on_unknown propagate statement in the model s OPT file unknown propagation is disabled even if you use lm_unknowns propagate yes For the propagate yes option to have an effect there must be an on_unknown propagate statement in the model s OPT file For more information about the on_unknown statement refer to the Shell Software Reference Manual value previous high low float Specifies the value to be passed to the device when an unknown value is passed to the modeler The default is previous meaning that if the simulator sets an input pin to unknown the modeler drives the input to its previous value For more information refer to the description of set_previous in the on_unknown reference pages in the Shell Software Reference Manual sequence_count num_sequences Specifies the number of random sequences to propagate unknowns through the hardware mo
135. ation on LMTV commands that you can use with SmartModels on Verilog XL refer to LMTV Commands on page 281 July 31 2001 Synopsys Inc 61 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide Using SmartModels with Verilog XL on the IBMRS AIX Platform To use SmartModels and FlexModels on IBM with Verilog XL follow this procedure The instructions provided here are based on the assumption that you are already using Verilog XL 1 The following lines are already in the copy of veriuser c at LMC_HOME sim pli src If you are using another veriuser c file copy these lines into it They are needed to make the SmartModel C Pipe interface cut here section 1 C pipe interface extern int pli_slm_post extern int slm_mempro_handle extern int slm_mempro_width_info extern int slm_transport extern int slm_transport_checktf extern int slm_inertial extern int slm_inertial_checktf nd section 1 xf cut here section 2 usertask 0 0 0 pli_slm post 0 Sslm_post_hdl true usertask 0 0 0 pli_slm post 0 Sslm_post true usertask 0 0 0 slm_mempro_handle 0 Sslm_mempro_handle true usertask 0 0 0 slm_mempro_width_info 0 Ssim_mempro_width_info true usertask 0 slm_transport_checktf 0 slm transport 0 slm transport true
136. ation on supported VHDL generics refer to the Synopsys VHDL Simulation Interfaces Manual Following are descriptions of some of the most useful generics LMSL TIMING MEASUREMENT You can use the LMSI_TIMING_MEASUREMENT generic to direct where timing values for your simulation session come from There are two legal values 136 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 6 Using Scirocco with Synopsys Models ENABLED The hardware modeler measures and records actual pin to pin timing values and passes them to the simulator DISABLED The hardware modelers passes to the simulator the pin to pin timing values from the TMG file This is the default value LMSI_DELAY_TYPE You can use the LMSI_DELAY_TYPE generic to specify whether the hardware modeler returns pin values to the simulator with minimum typical or maximum delays as you can see in the following legal values MINIMUM Return minimum delays for pin values to the simulator TYPICAL Return typical delays for pin values to the simulator This is the default MAXIMUM Return maximum delays for pin values to the simulator LMSI_LOG You can use the LMSI_LOG generic to specify whether the hardware modeler logs test vector or not There are two legal values ENABLED The hardware modeler logs test vectors DISABLED The hardware modelers does not log test vectors This is the default value July 31 2001 Synopsys Inc 137 Chapter 6 Using Scirocco with
137. ator Function Interface SFI Procedures for linking the simulator with the SFI are specific to the particular simulator Synopsys provides four ModelAccess products supporting QuickSim I Cyclone Verilog XL and NC Verilog For usage information refer to the following sections in this book e Using Hardware Models with QuickSim IT on page 244 e Using Hardware Models with Cyclone on page 174 e Using Hardware Models with Verilog XL on page 83 e Using Hardware Models with NC Verilog on page 108 Linking Other Supported Simulators Because many hardware modeling features are provided through the SFI software the functionality of your environment is determined by the version of the SFI that is integrated with your simulator Some simulators can be dynamically or statically linked on site with the most recent SFI For the current list of simulators and versions that are supported for dynamic or static linking on site with the SFI refer to Hardware Modeling Supported Platforms and Simulators If you use one of the simulators on this list you can link your simulator with the most recent version of the SFI libraries on the distribution media allowing you to take advantage of the latest hardware modeling system software enhancements and bug fixes Some simulators have additional requirements For information refer to your simulator vendor s documentation July 31 2001 Synopsys Inc 35 Chapter 1 Using Synopsys Mo
138. bfmi_ar a Solaris opt SUNWspro bin cc c KPIC ISCDS_VHDL include new_FMI_table c opt SUNWspro bin cc G o libfmi so new_FMI_table o your_archive a LMC_HOME 1lib sun4Solaris 1lib libfmi_ar a 2 Create a logical library named slm_lib The default physical library mapping for this is LMC_HOME sim ncvhdl lib If you do not want to install the library in the LMC_HOME tree you can create it in any other location Add the following line to your cds lib file define slm lib LMC_HOME sim ncvhdl 1lib 3 Compile the MemPro VHDL files into logical library slm_lib Note that rdramd_pkg vhd is not required unless you are simulating RDRAM MemPro models o nevhdl w slm lib LMC_HOME sim ncvhdl src slm_hdlc vhd nevhdl w slm lib LMC_HOME sim ncvhdl1 src mempro_pkg vhd nevhdl w slm lib LMC_HOME sim ncvhdl src rdramd pkg vhd o July 31 2001 Synopsys Inc 211 Chapter 11 Using NC VHDL with Synopsys Models Simulator Configuration Guide 4 After generating a model using MemPro compile the VHDL code for the model as shown in the following example o nevhdl mymem vhd 5 If you compiled the model to a library SLM_MODELS in these examples add a LIBRARY statement to your testbench LIBRARY SLM_MODELS This makes models in SLM_MODELS accessible from your design You can refer to the model using a standard VHDL convention such as a CONFIGURATION statement CONFIGURATION mymem_a OF mymem_tst IS FOR atest FOR ALL
139. ble 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Simulator Configuration Guide Tables SmartModel SWIFT Parameters bo es oe boo 6 deh oe 46S e deh ees 19 FlexModel SWIFT Parameters 6 4 sos dd kasi e HU eee sud i oeae KE Ree Os 24 FlexModel Direct C Control Files 4 423 486 45940 5 0hedRG bess 65545u5 2l MemPro Generic Parameter Descriptions n 4 iis e deed od eeeeanws 30 MemPro Supported Simulators o4 cc sd cd aside ed iae dees rewerecawes 31 MemPro Message Constant Descriptions ssssusuesnn ennea 34 VCS SmartModel Explanation sennsnanena nunen 41 FlexModel YCS Verilog Files scrsarrcrsorcaressti idian sedate 42 VCS With One FlexModel On Solaris Model Explanation 47 VCS MemPro Model Explanation oan ede 4 ede doe 4s eed ee bod nes 54 Characteristics of Historic and SWIFT SmartModel Modes 64 modely Lee eshte h 644 B05 05958 594 aS sees a 66 LMTV SWIFT and Verilog XL specific Libraries 76 FlexModel Verilog XL Files og kh hoe 84 da S OUR KURE SEES HemO SERED ES 79 Test vocior OE as paw ks ettr reae ees 93 FlexModel Bie Vee Fil s 4 4 44 46o ede de iiteraria d Ep CE Loe 104 Fl xModel MTI Verilog Fils ccccdactstg sida ee das isadeegaedcaws 115 FlexModel
140. ble that contains the LMTV interface Verilog XL Design Capture You instantiate models from the SWIFT SmartModel Library by creating HDL descriptions for Verilog XL The following example shows the Verilog XL code for instantiating a simple NAND gate ttl00 in a design v file for the LMTV SWIFT SmartModel mode For instance U1 the Timing Version and DelayRange parameter values have both been changed from the defaults For instance U2 only the DelayRange attribute value has been changed from the default top_mod contains module TOP_MOD defparam Ul TimingVersion 54F00 FAI U1 DelayRange min U2 DelayRange typ July 31 2001 Synopsys Inc 67 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide tt100 U1l I1l clk I2 enable Ol output tt1l100 U2 I1 clk I2 enable Ol output endmodule The following example shows the Verilog XL code for the same instantiation but for the LMTV Historic SmartModel mode Notice that the attribute names are different and that the alphabetic characters in the model name are upper case top_mod contains module TOP_MOD defparam U1 COMPONENT 54F00 FAI U1L RANGE min U2 RANGE typ TTLOO Ul I1l clk 12 enable Ol output TTLOO U2 I1l clk I2 enable Ol output endmodule Concept Design Capture As an alternative you can captu
141. bstitute the edited copy of vera_user c in LMC_HOME sim Vera src on the compile line 2 Substitute vera_slm_pli o for lt UDF_o_files gt on the link line if you are using VCS or Verilog XL For MTI Verilog substitute vera_slm_mti o Linking VERA with the MTI VHDL Simulator For information on how to link VERA with MTI VHDL refer to the README file in the VERA installation directory S VERA_HOME 1ib mti README In the instructions for Linking in VERA UDFs Into The MTI VHDL Simulator at the beginning of the README file 1 Substitute the edited copy of vera_user c in LMC_HOME sim Vera src on the compile line 2 Substitute vera_slm_mti o for lt o_files gt on the link line Creating a VERA Testbench To create a VERA testbench to use with FlexModels follow these steps 1 Include the header files Table 34 lists the two required header files Table 34 VERA Header Files File Name Description Location flexmodel_pkg vrh Contains definitions for generic constants LMC_HOME sim vera src useful in FlexModel commands model_pkg vrh Contains definitions for model class and LMC_HOME models model model specific constants useful in _fx model_fxversion src vera FlexModel commands July 31 2001 Synopsys Inc 271 Appendix A Using VERA with FlexModels 2 Create an instance of the ModelFx class Before using FlexModel commands you must create an instance of the ModelFx class in
142. ce750_12 v LMC_HOME bin flexm_setup mpc750_12 fx examples verilog mpc750_12 fx ves v LMC_HOME bin flexm_setup mpc740_fx examples verilog mpc740 v LMC_HOME bin flexm_setup mpc740_fx examples verilog mpc740_fx vcs v incdir LMC_HOME sim pli sre incdirt LMC_HOME bin flexm_setup mpc750_12 fx src verilog incdirt LMC_HOME bin flexm_setup mpc740_fx src verilog P LMC_HOME sim pli src slm_pli tab LMC_HOME 1ib sun4Solaris 1lib slm_pli o incdir LMC_HOME sim pli sre 1 ves_sim log Mupdate RI 1lmc swift Three FlexModels on HP UX This next example shows how to use the PCI system testbench and the pcimaster_fx pcislave_fx and pcimonitor_fx FlexModels together with VCS on HP UX Follow these steps 1 Set up the PCI system testbench as shown in the following example o mkdir pci_tb cp rf LMC_HOME bin flexm setup pcimaster_fx pci_tb cp rf LMC_HOME bin flexm setup pcimonitor_fx pci_tb cp rf LMC_HOME bin flexm setup pcislave_fx pci_tb oA o o 2 Invoke the VCS simulator as shown in the following example VCS_HOME bin vcs pci_tb examples verilog pcisys_tst v pci_tb examples verilog pcimaster v pci_tb examples verilog pcimaster_fx vcs v pci_tb examples verilog pcislave v pci_tb examples verilog pcislave_fx vcs v pei_tb examples verilog pcimonitor v pci_tb examples verilog pcimonitor_fx vces v t incdir pci_tb src verilog
143. ch as shown in the following example Q simv vera_mload files_to_load vera_finish_on_end gt Note The vera_finish_on_end switch prevents your simulation from ending prematurely in cases where the VERA testbench completes before the Verilog testbench 278 Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix B LMTV Command Reference B LMTV Command Reference Overview LMTYV is a PLI application that is used to interface SmartModels and FlexModels with Verilog XL NC Verilog and MTI Verilog Note that VCS uses the SWIFT interface and not LMTV You can control the features of the LMTV interface by using e LMTV Command Line Switches on page 279 e LMTV Commands on page 281 LMTV Command Line Switches LMTV command line switches have a session wide scope that impacts all SmartModel instances Notice that the laiobj switch used by the LAI interface is not used in either mode of the LMTV interface Following are brief descriptions for each of the command line switches that you can use with the LMTV interface 4 notimingchecks min typ max delays lmudtmsg or laiudtmsg July 31 2001 Disables timing checks for example setup and hold times and their accompanying messages The default is to perform the timing checks Specifies a single delay range for all SmartModel instances The default is to use the delay range in the SmartModel s DelayRange or RANGE attributes
144. ch hardware model in your design This is because Cyclone divides the circuit into two types of blocks sequential and combinatorial At every clock edge the sequential blocks get executed first and then the combinatorial blocks get executed The hardware model is neither fully sequential nor fully combinatorial so Cyclone declares it as a special block Cyclone discourages you from using special blocks by issuing warnings however special blocks are fine for hardware models so you can ignore the warnings for hardware models Keys Do Not Match Error Message If you receive the following error message during Cyclone simulation LM_HW integration error Keys do not match this indicates that you do not have a consistent set of genInterface output for example the liblm_hw so file was not generated in the same genInterface session as one or more of the vhd files so the information is not valid for simulation This can occur if you run genInterface more than once on the same hardware model files with the overwrite_files option left at its default setting of no To correct this error refer to Overwriting Existing Files on page 185 then rerun genInterface on the complete set of hardware models you want to use in the Cyclone simulation Analyze and elaborate the new genInterface output before proceeding with your simulation July 31 2001 Synopsys Inc 189 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration G
145. checks ommand 202 214 LM_LIB environment variable 38 60 112 142 156 196 LM_LICENSE_FILE environment variable 38 60 102 112 124 142 155 171 196 205 217 Im_log_test_vectors command 202 Im_loop_instance command 203 214 lm_model command 247 249 250 252 253 255 256 264 Im_model symbol generation 253 Da a environment variable 89 Im_pam_shortage command 203 214 Im_pattern_history command 203 214 Im_timing_measurements command 202 lm_unknowns command 202 214 Im_vconfig command 99 LM 1200 175 LM 1400 175 LMC_COMMAND setting SWIFT session commands 22 July 31 2001 Simulator Configuration Guide LMC_HOME environment variable 38 59 77 101 111 124 141 155 171 195 205 217 MC_PATH environment variable 77 MC_SFI environment variable 55 e oe environment variable 7 MC_VLOG environment variable 77 LMC_VLOG environment variables 77 Imc swift template command 39 42 Immsi logon command 136 Imsi list command 136 LMSI_DELAY_TYPE VHDL generic 137 152 LMSI_LOG VHDL generic 137 152 LMSI_TIMING_MEASUREMENT L L L L L VHDL generic 136 152 MTV command reference 279 command line switches 77 279 historic SmartModel mode for Verilog XL 64 modes of operation for Verilog XL 64 simulating older designs with Verilog XL 76 static linking with PLI 81 82 83 106 108 117 SWIFT SmartModel mode with Verilog XL 64 lmvc_template command 55 Imvsg command 84 Imvsg commnd 99 L
146. command to query a model directly Select one or more instances in the design and then issue the command to display the internal element status of all selected instances as shown in the example below Signal instance swift_dump TS 142 TS1 Note lt lt Status Report gt gt TS1 Model template pal20r4i TS1 Version not available TS1 InstanceName 1 2742 TS1 TimingVersion MMI_20R4A COM TS1 DelayRange TYP IS1 JEDECFile user bobb design schematic selack jedec TS1 Timing Constraints Off TS1 SmartModel Instance 1 2742 U103 MMI_20R4A COM sheetl of schematic at time 0 00 nsec TS1 Ta I 1 Note SmartModel Windows Description I 1 Q20 PAL Internal Register connected to pin 20 TS1 Q19 PAL Internal Register connected to pin 19 TS1 Q18 PAL Internal Register connected to pin 18 TS1 Q17 PAL Internal Register connected to pin 17 TS1 SmartModel Windows not enabled for this model TS1 SmartModel Instance 1 2742 U103 MMI_20R4A COM sheet1 of testbed schematic at time 0 00 nsec 17I Ta mY Reconfiguring Models for Simulation You can use QuickSim II to reconfigure models for additional simulations by e Editing properties e Changing timing modes of model instances e Enabl
147. commands workdir examples vhdl 208 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 11 Using NC VHDL with Synopsys Models 4 Update the clock frequency supplied in the model_user_pkg vhd file in your working directory to correspond to the desired clock period for the model After you run flexm_setup this file is located in workdir sre vhdl1 model_user_pkg vhd where workdir is your working directory 5 Create a logical library named slm_lib The default physical library mapping for this is LMC_HOME sim simulator lib however you can put the physical library anywhere you want 6 Add LIBRARY and USE statements to your testbench library slm lib use slm lib flexmodel_pkg all use slm lib model_pkg all use slm lib model_user_pkg all For example you would use the following statement for the tms320c6201_fx model use slm lib tms320c6201_pkg all use slm lib tms320c6201_user_pkg all 7 Instantiate FlexModels in your design defining the ports and generics as required refer to the example testbench supplied with the model You use the supplied bus level wrapper model vhd in the top level of your design to instantiate the bit blasted wrapper generated in Step 2 model_fx vhd using ncshell Example using bus level wrapper model vhd without timing Ul model generic map FlexModelID gt TMS INST1 port map model ports Example using bus level wrapper model vhd w
148. cpipe design Script for Running FlexModel Examples in Scirocco On page 131 is a Perl script Figure 6 that you can use to run Scirocco on a FlexModel examples testbench You can use this script on any installed FlexModel because each one comes with a prebuilt testbench example that shows how to use the model commands and all the VHDL wrapper and procedure definition files that you need This script runs on HP UX and Solaris To invoke Scirocco on a FlexModel and its example testbench follow these steps 1 Make a working directory and set the TMPDIR variable to that location as shown in the following example setenv TMPDIR path_to_workdir 2 Use the Acrobat Reader s text selection tool to select the script shown in Figure 6 and copy the contents to a local file named run_flex_examples_in_scirocco pl 3 Save the file and change the permissions so that the file is executable chmod 775 in UNIX 4 Invoke the script as shown in the following example run_flex_examples_in_ scirocco pl model_fx 130 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 6 Using Scirocco with Synopsys Models where model_fx is the name of the FlexModel you want to run Note This script was developed for internal use and is made available for customer convenience It is not actively maintained as part of the licensed software usr local bin perl Revision 1 4 die nERROR running 0 No FlexModel name gi
149. cription Description technology tecf_1 ASIC1 ASIC1 mgc_ mgc_I m attr symbol attr technology Tf_tfile_ ASIC1 rss_1 ASIC1 Figure 18 Hardware Model Registration Registering a Model with Ilm_model All hardware models whether user created or purchased from Synopsys must be registered with the Im_model utility before you can use them in the QuickSim II simulation environment The following list shows the basic steps involved in preparing a hardware model for simulation 1 Running the Im_model Utility discussed next 2 Checking the Transcript for any errors or warnings 250 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models 3 Editing the Symbol to meet any additional symbol conventions optional 4 Verifying the Technology File not required if Shell Software timing files are used in place of this file for more information refer to Timing Shell Selection on page 258 Running the Im_model Utility You can use the Im_model shell command to register a hardware model To run Im_model use the following syntax Syntax Im_model input_dir output_path Dir name LAbel label Mdl mdl_filename Step RegisterlSymbollTiming Update Replace For a complete description of Im_model syntax and options refer to Im_model Command Reference on page 264 Example The
150. cs software including QuickSim II V8 6 or later and the Design Data Port package as described by Mentor Graphics Corporation e R3 la or later of ModelSource or LM family hardware modeling software 244 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Setting up Hardware Models in QuickSim Il To set up the LM family ModelAccess interface software for QuickSim II complete the following steps 1 Running Imc_hm_install on page 245 2 Rebuilding the Mentor Graphics Tree on page 246 Running Imc_hm_install To run the ModelAccess installation script enter the following commands If you are on NT execute these commands in a MGC mkns shell ed install_dir sms mags_30 1mc_hm Svco bin Imc_hm_install m mgc_home 1l 1m home p ma_home where e vco is the vendor CPU operating system suffix that corresponds to your platform as shown in Table 29 e mgc_home is the directory path that contains the Mentor Graphics software tree You can use MGC_HOME if you have set it or a pathname such as home mentor e m_home is the directory path that contains the LM family and ModelSource system software for example home Im e ma_home is the directory path that contains the ModelAccess interface software for example home Imc_hm sss Table 29 Mentor Graphics Vendor CPU Operating System Suffixes Vendor CPU Host Operating
151. cs tree that you want to rebuild such as the mgc_home pathname described in Rebuilding the Mentor Graphics Tree on page 246 Click on OK or press the Return key to accept this pathname The install program takes several minutes to rebuild the Mentor Graphics tree The program prints a number of messages to the Results screen You should ensure that no errors or warnings are printed especially warnings generated by the Imc_hm package indicating that you are missing certain Mentor Graphics software packages Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models 5 When the rebuild is complete click on OK to delete the Results screen 6 Use the mouse to select the File gt Exit pull down menu item This completes the ModelAccess installation procedure You are now ready to begin model registration and simulation Using Hardware Models in QuickSim Il This section describes how to prepare and use hardware models in QuickSim II We begin with an overview of the Mentor Graphics design environment that describes why models must be registered in order to function in this environment The section also describes how to use the Im_model utility to register hardware models The operation of the hardware modeling system during simulation is transparent to the user in most respects However a number of signal instance commands are available to enable or disable QuickSim II or hardwar
152. ct this is equivalent to running the Im Check Shell Software utility If Im_model encounters an error condition it stops execution and prints a message describing the source of the error Warning and information messages print to the screen but do not halt the execution of Im_model If you get an error you should fix the problem in the Shell Software and then run Im_model again to complete the registration The following is an Im_model transcript for the 74LS74 model fh odelAccess for QuickSim II v2 0 a k a lmc_ hm v2 0 lm model v8 5_2 1 Fri Oct 18 18 32 32 PDT 1996 Note Input directory 741s74 resolves to user johnd 1lmc qa 1lmc_hm work sss 741s74 Note Output directory 74LS74 resolves to user johnd 1mc qa 1imc_hm work sss 74LS74 Note Using 74LS74A MDL file for conversion Note Compiling symbol generator program Note Linking symbol generator program Note Creating symbol tmg_to_ts v8 5_2 1 Sat Oct 19 20 18 24 PDT 1996 Falcon Framework v8 5_2 5 Thu May 30 17 31 43 PDT 1996 Copyright c Mentor Graphics Corporation 1982 1995 All Rights Reserved UNPUBLISHED LICENSED SOFTWARE CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS Mentor Graphics software executing under Sun SPARC SunOS Li TC The Technology Compiler v8 5_2
153. cts use a colon separated list UNIX or semicolon separated list NT to specify the search path in your variable setting a Caution Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you use for snpslmd based authorizations 4 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv LM DIR hardware_model_install_path sms 1m_dir setenv LM LIB hardware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly 5 Depending on your platform set your load library variable to point to the platform specific directory in LMC_HOME as shown in the following examples Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD_LIBRARY_PATH LMC_HOME 1ib x86_linux 1ib LD_LIBRARY_PATH AIX setenv LIBPATH LMC_HOME 1lib ibmrs 1lib LIBPATH HP UX setenv SHLIB_ PATH LMC_HOME 1ib hp700 1lib SHLIB PATH NT Make sure that 7LMC_HOME lib pcnt lib is in the Path user variable 156 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 8 Using MTI VHDL with Synopsys Mo
154. d in In Historic SmartModel Mode on page 72 However as before you cannot use these commands to access vectored memory windows To use memory windows available in SWIFT but not in Historic SmartModel mode you must use the lm_monitor_vec_map command This command works for both scalar and vectored windows D gt Hint For simplicity when implementing new designs in SWIFT SmartModel mode use the lm_monitor_vec_map command for both scalar and vectored windows applications It is best not to use the lm_monitor_enable or lai_enable_monitor commands at all To access window elements using the lm_monitor_vec_map command follow these steps 1 Define a register for the window element You can give the register the same name as the window element or a different name For example to define the register MY_A_REG to map to the 32 bit register A_REG you could use this definition reg 31 0 MY_A REG July 31 2001 Synopsys Inc 73 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide 2 Enable the window element and map it to the register For example to enable the window element A_REG for instance U1 and map A_REG to the register MY_A_REG you could use this command lm_monitor_vec_map MY_A REG U1 A REG 3 To read from a window element use any appropriate Verilog command to examine the contents of the register mapped to that window element For example to read the content
155. d off a number of QuickSim II or hardware modeling features for selected instances during simulation Signal Instance Command Summary Table 32 provides a summary of these features and the specific commands used to implement them the subsections that follow describe the features in more depth Some features can also be implemented through Shell Software statements or the lm utilities for details refer to the Shell Software Reference Manual For instructions on how to select one or more instances refer to your QuickSim IT documentation TS Note If the simulator is reset with the reset_state function any prior Signal Instance commands are lost because the simulator is reset to the same state it was at invocation 256 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Table 32 Signal Instance Command Summary Feature Command Description Model evaluation enable Enables evaluation of the instance by QuickSim II default disable Disables evaluation of the instance by QuickSim I Timing shell Ist p all Selects hardware model Shell Software files to selection describe the instance s timing nolst p all Selects the Technology File to describe the instance s timing Default Unknown xp p pin_name Maps an unknown input state to the previous handling and state Default propagation x0 p pin_name
156. define work work_lib_path Simulator Configuration Guide 2 Generate a VHDL wrapper file for the model by invoking ncshell as shown in the following example neshell import swift into vhdl model_fx nocompile work slm lib 3 Create a working directory and run flexm_setup to make copies of the model s interface and example files there as shown in the following example LMC_HOME bin flexm setup dir workdir model_fx You must run flexm_setup every time you update your FlexModel installation with a new model version Table 22 describes the FlexModel NC VHDL interface and example files that the flexm_setup tool copies Table 22 FlexModel NC VHDL Files File Name Description Location model_pkg vhd Model command procedure calls for HDL workdir src vhdl Command Mode model_user_pkg vhd Clock frequency setup and user workdir src vhdl customizations model_fx_comp vhd Component definition for use with the model entity defined in the SWIFT wrapper file This is put in a package named COMPONENTS when compiled workdir examples vhdl model vhd A bus level wrapper around the SWIFT model This allows you to use vectored ports for the model in your testbench This file assumes that the COMPONENTS package has been installed in the logical library slm_lib workdir examples vhdl model_tst vhd A testbench that instantiates the model and shows how to use basic model
157. del The num_sequences setting is an integer of value 0 the default through 20 The default value 0 is usually sufficient setting a higher value ensures that unknowns will be propagated but uses more pattern memory random_seed seed_value device_or_pin 98 Specifies the initial seed for the random sequence generator seed_value is an integer of value 0 the default through 65535 Specifies the Verilog pathname of a device or pin whose unknown values are to be translated into the value specified by value The default is to apply the statement to all hardware model instances in the simulation Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models Description The lm_unknowns command lets you override the hardware modeler s default handling of unknown values for specified model instances or pins or for all hardware model instances in the simulation By default the hardware modeler translates all unknown values to previous before passing them to the device Using this command you can specify values of high 1 low 0 or float or disable unknown propagation for a specified instance or pin or for all hardware model instances in the simulation if no instance or pin is given For detailed information about unknown handling refer to the Shell Software Reference Manual Examples The following example disables unknown propagation and causes a low value to be
158. del instantiated in the testbench must have a model swift v wrapper file listed on the VCS invocation line VCS SmartModel Explanation Table 7 lists each line in the invocation examples above along with explanations for what each one does Table 7 VCS SmartModel Explanation Line Reference Description SVCS_HOME bin vcs lmc swift model swift v model_tb v Path to the file that starts the VCS simulator a switch that causes VCS to load the SWIFT interface and then the specified model wrapper and Verilog testbench files 1 vcs_sim log Specifies a log file where VCS writes compilation and simulation messages Mupdate This specifies incremental compilation which causes VCS to compile only the modules that have changed since the last run RI This makes VCS run interactively VCS invokes the XVCS GUI after compilation and pauses the simulator at time zero LDFLAGS switches Additional platform specific switches that may be needed July 31 2001 Synopsys Inc 41 Chapter 2 Using VCS with Synopsys Models Simulator Configuration Guide Using FlexModels with VCS To use FlexModels with VCS follow this procedure VCS links the external PLI routines that contain the custom FlexModel integration code during compilation of your design This procedure covers users on UNIX and NT If you are on NT substitute the appropriate NT syntax for any UNIX command line examples percent signs
159. del_pkg obj I LMC_HOME sim C sre Iworkdir sre C wsock32 1ib gt Note The entire compilation expression must appear on the same line The NT example was tested using Microsoft s Visual C compiler v5 0 The C executable file that you created in this step is the program that you point to using the FlexCFile SWIFT attribute for the model instance in your design Using MemPro Models with VHDL and Verilog Simulators Regardless of which simulator you are using you must configure MemPro models by defining the required parameters or attributes shown in Table 4 for each MemPro model instance in your design You configure MemPro models when you instantiate them in your design using these generics or parameters July 31 2001 Synopsys Inc 29 Chapter 1 Using Synopsys Models with Simulators Simulator Configuration Guide Table 4 MemPro Generic Parameter Descriptions Name Data Type Description model_id Integer model_alias String Either the model_id or model_alias generic or parameter specifies a unique user handle for a specified model instance This user handle is used to address a memory model using testbench commands Note You do not have to assign all MemPro model instances a model_id or model_alias only those instances on which you wish to use the testbench interface However each model with a model_id or model_alias must be assigned a unique handle memoryfile String Specifi
160. dels Using SmartModels with MTI VHDL To use SmartModels with MTI VHDL follow this procedure 1 Open the modelsim ini file in a text editor and uncomment the lines corresponding to the platform you are using ModelSim s interface to Logic Modeling s SmartModel SWIFT software libsm SMODEL_TECH libsm sl ModelSim s interface to Logic Modeling s SmartModel SWIFT software Windows NT libsm SMODEL_TECH 1libsm d1 Logic Modeling s SmartModel SWIFT software HP 9000 Series 700 libswift LMC_HOME 1lib hp700 lib libswift s Logic Modeling s SmartModel SWIFT software IBM RISC System 6000 libswift SLMC_HOME 1lib ibmrs lib swift o Logic Modeling s SmartModel SWIFT software Sun4 Solaris libswift SLMC_HOME 1lib sun4Solaris lib libswift so Logic Modeling s SmartModel SWIFT software Sun4 SunOS do setenv LD_LIBRARY_PATH SLMC_HOME 1ib sun4SunOS 1lib and run vsim swift Logic Modeling s SmartModel SWIFT software Windows NT libswift SLMC_HOME 1lib pcnt lib libswift d1ll 2 To create the SmartModel Library VHDL wrappers or templates run the MTI sm_entity script with any optional arguments The sm_entity script takes SmartModel names as input and writes the VHDL output to STDOUT You can redirect the output to a file Run sm_entity as follo
161. dels with Simulators Simulator Configuration Guide If you use a simulator that is not on the list consult your simulator vendor about which version of the SFI has been integrated with your simulator Depending on the version of the SFI you should be able to install and use the most recent Runtime Modeler Software although you may not be able to take advantage of all hardware modeling system software enhancements and fixes IKOS Voyager For information on this interface refer to the Voyager LM Hardware Interface chapter of the Voyager Series User s Guide Volume 4 Do not install the hardware modeling system software under the VOYAGER_HOME directory or files could be overwritten and the installation corrupted The IKOS created sms directory under VOYAGER_HOME and the Synopsys created sms directory must be kept separate Teradyne LASAR You can dynamically link the SFI with LASAR For complete Teradyne specific installation information refer to Teradyne s LASAR Manager Guide for UNIX Systems VEDA Vulcan You can dynamically link the SFI with Vulcan at simulator runtime For current linking information please contact VEDA technical support directly Viewlogic Fusion ViewSim You can statically link the SFI on site with ViewSim For information refer to the Viewlogic Fusion ViewSim manual or contact Viewlogic technical support directly at 1 800 223 8439 In addition Synopsys provides a SOLV IT article with some information
162. dels you want to use with Cyclone For details on genInterface syntax refer to genInterface Command Reference on page 186 gt Note The genInterface program relies on the software described in Cyclone genInterface Setup Files on page 190 The verifySetup program helps you verify that these prerequisites have been set up correctly ModelAccess for Cyclone Cyclone Figure 9 Process Flow Chart 180 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models Confirming License File Settings ModelSource Only The genInterface program is not license protected However in order to use the output of genInterface to run Cyclone simulations with ModelSource hardware models several licenses are required e MSCBS licenses the use of hardware models with cycle based simulators e MS3400 or MS3200 specifies the number of MS 3400 or MS 3200 units licensed In addition you need the appropriate licenses to run Cyclone gt Note The LM family hardware model servers LM 1400 and LM 1200 are not license protected and do not have a license file This step is required only for ModelSource systems MS 3400 MS 3200 For information about installing hardware model licenses or updating an existing license file refer to the Hardware Modeling Release Notes To confirm that your licenses are working correctly follow these steps 1 Invoke the Im utilities
163. design_name vhd 9 Invoke Cyclone on your design as shown in the following example o cysim 4state 2state i design_name Using Hardware Models with Cyclone This section describes how to set up and configure Release 3 5a of ModelAccess for Cyclone After completing the setup tasks for usage information refer to Using Hardware Models with Cycle Based Simulators on page 182 The hardware modeling configuration you choose affects the performance you get when running hardware models in Cyclone simulations This section reviews the fundamentals of the ModelSource and LM family hardware modeling systems and then provides guidelines for a number of possible configurations 174 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models ModelSource System Hardware and Software If you are using a ModelSource system your hardware modeling system configuration consists of one or more MS 3400 or MS 3200 units plus a ModelSource Processor For a description of a ModelSource Processor refer to the ModelSource Hardware Installation Guide For information about the software refer to the ModelSource User s Manual The ModelSource Processor is connected to the rest of your network via Ethernet and to the MS 3400 MS 3200 units via fiber optic cable The ModelSource Processor provides the CPU for the ModelSource units and at a minimum it executes the runtime modeler software RMS for
164. disables trace messages that list the timing files loaded at simulation startup The default is OFF TracePath ON OFF Enables or disables tracing of paths to files used to determine versions of models The default is OFF Verbose ON OFF Enables or disables the generation of error messages when a SmartModel instance cannot be created The default is OFF NoLicenseFatal ON OFF When set to ON causes the SWIFT session to send a fatal error message to the simulator and terminate if any SmartModel in the simulation fails to authorize The default is OFF Je Attention aA _ You must invoke the TraceTimeFile TracePath and NoLicenseFatal commands before the start of the simulation run if you want them to take effect for that session 22 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 1 Using Synopsys Models with Simulators Fault Simulations The SmartModel Library fault simulation capability is folded into the logic simulation SmartModel Library so that only one set of directories and utilities need to be installed and maintained Fault simulation availability depends on the e Model Note that the following types of models are incompatible with fault simulation o Hardware verification HV models are driven by PCL commands rather than machine instructions and do not respond adequately to propagated faults Fault simulation results may not be as accurate when HV models are present in the c
165. dware model You can use the nawk script provided in Scirocco Template Generator Script for Hardware Models on page 138 to generate this file Copy the script and paste it into an executable file called hwm2vhdl nawk 4 If you generate the wrapper by hand you must provide o an entity architecture pair declaration so Scirocco can reference it in a later component instantiation statement o a package for defining constants declaring components and instantiating components Scirocco Example with TILS299 Hardware Model The following example uses the TILS299 hardware model to show how to set up hardware models for use with Scirocco 1 After creating the wrapper vhd file analyze the file using vhdlan as shown in the following example whldan event TILS299 vhd 2 Place the hardware model in the testbench file and invoke the simulator as follows scsim t ns TB _TILS299 The ns argument invokes the simulator with nanosecond time steps EY k Attention When using hardware models with Scirocco your design can include a mix of event based and cycle based but hardware models simulate only as event based July 31 2001 Synopsys Inc 135 Chapter 6 Using Scirocco with Synopsys Models Simulator Configuration Guide Scirocco Utilities The following hardware modeler simulator commands are supported in Scirocco lmsi list devices ids You can use the Imsi list devices command to list all hardware model instances by de
166. dware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly 6 Depending on your platform set your load library variable to point to the platform specific directory in LMC_HOME as shown in the following examples 124 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 6 Using Scirocco with Synopsys Models Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD_LIBRARY_PATH LMC_HOME 1ib x86_linux 1ib LD_LIBRARY_PATH AIX setenv LIBPATH LMC_HOME 1lib ibmrs 1lib LIBPATH HP UX setenv SHLIB_ PATH LMC_HOME 1ib hp700 1lib SHLIB PATH NT Make sure that 7LMC_HOME7 lib pcnt lib is in the Path user variable Using SmartModels with Scirocco To use SmartModels with Scirocco follow this procedure l N To create SmartModel VHDL templates check to see if you have write permission for LMC_HOME synopsys smartmodel if so skip to Step 4 Otherwise open the Synopsys_vss setup file in your current working directory and search for the string SMARTMODEL By default the logical library name SMARTMODEL is mapped to LMC_HOME synopsys smartmodel as follows SMARTMODEL SLMC_HOME synopsys smartmodel Change the directory to one for which you have write permission as shown in the following example SMARTMODEL
167. e Linking VERA with Verilog Simulators 1 00c neesvnevnsecaevcduws 271 Linking VERA with the MTI VHDL Simulator 271 Creanga a VERA Testbendhi sprsasrorrtdrp See Ko OSG CRE REESE EER aD RHE HSS 211 VERA T stbench Example dg cade ycenc deed owe ehetaieicd eed ee eeeun Pe Incorporating FlexModels ina VERA Testbench 0000 274 SNe VERA witli VCS 664d de cee heoo bss Ky eaw eee We ens RV EI e Sew R aoe 215 Appendix B LMTYV Command R ferente serciseccsrcnresenrasosie Eriu csrer teken kaS 279 Oo e ee ee eee mre E E E E E E ee EE E E E E A 279 LMTV Command Line Switches sec besos dso bar ennnen err 279 LITVY COMMAS ba eee en ea inrait irera rae oaeen 281 Im_command or lai_command 46 kdb ees Shwe a oS ODER RSS KS a OSs 282 Im_dump_file or lai_dump_fileQ gave cadee ve tedden ves dodnaddans 283 Cs 25 ba bab a paw EN E aa wee eee eas Heed ae oe eee 284 Slmi_ toad filet or lai_load_fileO kde wen vine stwoiaws dies ianedienss 285 lm_monitor_enable or lai_enable_monitor 0000 286 lm_monitor_disable or lai_disable_monitor 0005 286 lm_monitor_vec_map and lm_monitor_vec_unmap 288 Im_status or lai_statusQ oy kc oo bed ed wee deeds dues ceed essere 290 hs ee eee A ee ee ee ee ee E E re er ee 291 8 Synopsys Inc July 31 2001 Simulator Configuration Guide Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
168. e as shown in the following example Q setenv IMC HOME path_to models_ installation 2 Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example setenv LM LICENSE FILE path_to_product_authorization_file setenv SNPSLMD LICENSE_FILE path_to_product_authorization_file You can put license keys for multiple products for example SmartModels and hardware models into the same authorization file If you need to keep separate authorization files for different products use a colon separated list UNIX or semicolon separated list NT to specify the search path in your variable setting 8 Cau ti o n s Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you use for snpslmd based authorizations 3 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv LM DIR hardware_model_install_path sms 1lm_dir setenv LM_LIB hardware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly 4 Depending on your platform set your load library variable to
169. e SCFFILE CGAFILE PCLFile PCLFILE PCLFILE 64 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models Table 11 Characteristics of Historic and SWIFT SmartModel Modes SWIFT SmartModel Mode Historic SmartModel Differences swift swift uc Mode Module Names Alphabetic Alphabetic Alphabetic characters are characters are characters are uppercase lowercase uppercase Port Ordering Numeric for example ports of bus Alphanumeric for A 0 11 are in this order AO Al A2 A3 A9 A10 All example ports of bus A 0 11 are in this order AO Al A10 A11 A8 A9 Command Names Begin with Im_ Begin with lai_ Switch Names Begin with lm Begin with lai Message Format Refers to model names and timing version names Timing units are in nanoseconds ns Refers only to timing version names No timing units specified Ignored laiobj ignored laiobj ignored LAI_OBJ ignored LAI_OBJ ignored User defined model v files do not have to be modified model v files must be Windows modified Resistive Strength Reports true resistive strength of outputs Maps resistive strength of outputs to strong Memory Windows Supports memory windows Does not support memory windows Implementing SWIFT Mode or Historic SmartModel Mode Both the SWIFT and the Historic SmartModel modes reference the SWIF
170. e SWIFT parameters This could take the form of Verilog defparams VHDL generics or symbol properties depending on the simulator you are using Table 2 FlexModel SWIFT Parameters Parameter Data Type Description FlexTimingMode FLEX _ TIMING MODE _ OFF Disables enables timing simulation default For Verilog prepend a back quote FLEX TIMING MODE ON to the constant FLEX_TIMING_MODE_CYCLE Note Direct C Control users can set this parameter to 0 for timing mode off 1 for timing mode on 2 for cycle based timing Timing Version Model timing version The FlexModel timing version Refer to the individual FlexModel datasheets for available timing versions DelayRange MIN TYP MAX default If you set FlexTimingMode to on you can select MIN TYP or MAX delay values with this parameter FlexModelld instance_name A unique name that identifies each FlexModel instance This name is also used by the flex_get_inst_handle command to get an integer instance handle Note Used only with _fx models FlexModelld_cmd_stream instance_name A unique name that identifies each FlexModel instance or command stream This name is also used by the flex_get_inst_handle command to get an integer instance handle For information on cmd_stream names refer to the individual FlexModel datasheets Note Used only with _fz models 24 Synopsys Inc J
171. e User s Manual or the LM family Modeler Manual Example The following example enables test vector logging for the instance U1 and saves the test vector log in the file U1 log lm_log_test_vectors Tbhench U1 1 U1 1lo0g lm_loop_instance Command Reference The lm_loop_instance command enables the loop mode for a specified model instance Syntax lm_loop_instance instance_path Arguments instance_path Specifies the pathname of the model instance for which the loop mode is to be enabled Description Enables the loop mode for a specified instance In loop mode the hardware modeler repeatedly plays to the physical device the pattern history of the specified device instance This command is most often used to analyze the behavior of a device and its pattern history with an oscilloscope or logic analyzer connected to the device Once in loop mode the interface prompts you to press the Return key to exit the loop mode Examples The following example turns on loop mode for the U1 model instance lm_loop_instance U1 July 31 2001 Synopsys Inc 95 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide The following message is displayed while the instance is in loop mode Entering loop mode for hardware model instance U1 Press Return to terminate loop mode lm_timing_information Command Reference The lm_timing_information command lets yo
172. e leiscieves inet acd evden tone 39 Using FlexModels with VES snccccav So 8bs pe edeen SoS So haw eee de Soe oes 42 NES FlerModel Examples bah he ch eed deo dartan dent kha RK RR SES 45 Script for Running FlexModel Examples in VCS 04 49 Example Simulator Run Script 6 5 5 box daesads esaeewd eed deaaeen anes 5il Using MemPro Models with VCS siscddsiddviaseee yee nanne era 51 Usmg Hardware Models with VCS ocnien ide 664 oes ene denedeaks Snes baw ds 55 Example Using Runtime Option 2 lt 6 lt a ncescetevaenenatesaw erx ase 57 Example Using DelayRange Parameter 0 0 eee eee eee ee ST We UNS aperire bidden t ieie eeaeee ved eE 57 Chapter 3 Using Verilog XL with Synopsys Models ccc wcccccccccccccscees 59 RPMS cer egeieh ewe Se seeds 1 oeGhLdeUaee u inii e AE 59 Setune Environment Variables 2444460 h0e deka sendin h0edee cd nner cesar es 59 Using SmartModels with Verilog XL nach ase reas ecu siaee esa eh dws cdanees 61 Using SmartModels with Verilog XL on the IBMRS AIX Platform 62 Verilog XL Usage Notes for Smart Models 22 isesddssvenscdnesinecreens 63 Using FlexModels with Verilog XL cp caceleceeeesreussaceshudosdusiaeses 79 FlexModels PLI Static Linking with LMTV 0 2 0 2 2 ee eee 81 Using MemPro Models with Verilog XL icacc4eesdaeasan ees ci ewe ceew ed 81 Statie Linking wih LMTY wseseaeesaeseceeeeee titani EEk se4eees 82 Using Hardware Models with Verilog XL casi lt sues due
173. e modeling features for selected instances during simulation This section provides descriptions and examples of those commands The Mentor Graphics Design Environment In the post V8 0 QuickSim family environment an instance of a component placed on a schematic references a component interface A component interface contains a set of descriptors that define aspects of a component such as its functionality graphical representation symbol and timing constraints There can be several variations of each descriptor for a component such as e Several functional descriptions of the component using different modeling methods such as BLM VHDL or hardware models e Several graphical descriptions symbols of the component such as ANSI MG_STD or your company standard e Several technology descriptions timing constraints of the component with different timing grades The Mentor Graphics analysis tools use the value of the MODEL property as a label to identify the descriptors that define the model For example Figure 17 shows an instance with a MODEL property of lm The Im label is the default label for the functional description of a hardware model By examining the model table of the component interface a match can be found between the MODEL property and the files that comprise the functional description of the hardware model July 31 2001 Synopsys Inc 247 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuratio
174. e pin_map file shown below the names that are changed on the first symbol are labeled CS RASIN R C CASIN WIN RA RB RC RD and M2 They will have an L added to the name to denote that they are asserted low Notice that a bus has been defined for each of these sets of pins QO through Q9 RO through R9 CO through C9 and BO through B1 r DP8429 PIN NAME CHANGES IN CSL cS IN RASINL RASIN IN CASINL CASIN IN RCL R C IN WINL WIN IN RFSH M2 INR 242 R9 R8 R7 R6 R5 R4 R3 R2 R1 RO Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models INC C9 C8 C7 C6 C5 C4 C3 C2 Cl C0 INB B1 BO OUT WEL WE OUT RAL RAS3 OUT RBL RAS2 OUT RCL RAS1 OUT RDL RASO OUT Q Q9 Q08 QO7 Q6 O5 O4 Q3 Q2 Q1 Q0 Conditional Pin Mapping Use a conditional clause in the pin_map file to cause the model to use different parts of a pin_map file based on the value of a certain property The syntax is property_name property_value This method is used by the models to map the pins from the BUS symbols to the model The pin map parser searches for the property_name in the design database and then compares the property_value Ifthe property is not present or if the actual value of the property does not match the property_value exactly everything in the file until the next percent sig
175. e server Imgrd process than the one you use for snpslmd based authorizations 3 Set the SYNOPSYS_CY environment variable to point to the Cyclone installation tree as shown in the following example setenv SYNOPSYS CY Cyclone_install_path 4 Set the MA_CY environment variable to point to the ma_cyclone directory as shown in the following example o setenv MA CY ModelAccess_install_path 5 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv IM DIR hardware model_install_path sms lm dir setenv IM LIB hardware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly 6 Depending on your platform set your load library variable to point to the platform specific directory in LMC_HOME as shown in the following examples Solaris setenv LD LIBRARY PATH SLMC HOME 1ib sun4Solaris 1lib LD LIBRARY PATH Linux setenv LD LIBRARY PATH LMC_HOME 1ib x86_linux 1lib LD_LIBRARY_ PATH AIX setenv LIBPATH LMC_HOME 1ib ibmrs 1ib LIBPATH HP UX setenv SHLIB PATH LMC_HOME 1ib hp700 1ib SHLIB_PATH NT Make sure that 7LMC_HOME lib pcnt lib is in the Path user variable Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models Using SmartModel
176. e the SFI library s debug version for troubleshooting define the environment variable HOSTDEBUG For information about setting and using HOSTDEBUG refer to the Simulator Integration Manual For troubleshooting assistance contact Synopsys Technical Support for instructions refer to Getting Help on page 14 lm_log_test_vectors Command Reference The lm_log_test_vectors command enables test vector logging for a specified instance and specifies a file name for the test vector log Syntax lm_log_test_vectors instance_path on_off filename Arguments instance_path Specifies the pathname of the model instance for which test vector logging is to be enabled or disabled on_off Indicates whether test vector logging is to be enabled or disabled Allowed values are 1 to enable logging or 0 the default to disable logging 94 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models filename Specifies the file name to be used for the test vector log Description Enables test vector logging for a specified instance and specifies a filename for the test vector log By default test vector logging is not performed When test vector logging is on the pin value information created during the simulation for the specified device instance is written in test vector file format to filename For detailed information about test vector logging refer to the ModelSourc
177. e to point to a file If you use a relative path name it is resolved relative to the value of MGC_WD Symbol Properties Required for Simulation Table 24 lists symbol properties that are required for simulation Table 24 Symbol Properties Required for Simulation Property Description MODEL The MODEL property contains a label registered as type SWIFT PIN Logic simulation requires that each pin on a symbol have a property A PIN property has two values associated with it e User pin name e Compiled pin name You can change the user pin name to adhere to drafting standards but you must not change the compiled pin name PINTYPE Each model pin has an associated PINT YPE property which describes the pin entry point type i e IN OUT IXO or IO QuickSim II requires this property SWIFT_TEMPLATE The SWIFT_TEMPLATE property always has a value that specifies the model name This property cannot be changed 224 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Table 24 Symbol Properties Required for Simulation Continued Property Description PKG Each model has a PKG property equal to the physical package type for example DIP LCC that the symbol s pin numbers match When using the bus symbol for a component the PKG property is set to the value BUS Optional Symbol Properties Table 25 lists optio
178. e useful for analyzing the device behavior and pattern history with an oscilloscope or logic analyzer connected to the device However while loop mode is enabled no other user can access the modeling system patterns are replayed to the selected device exclusively until loop mode is disabled For this reason QuickSim II returns an error if this command is specified when more than one user is accessing the modeling system 262 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Printing Model Information A number of Signal Instance commands are available for printing information about the selected model instances The SIGnal INSTance dump command prints all information available about the currently selected instances including e Instance ID e Name of the modeling system in which the hardware model is located e Setting for test vector logging On or Off e Setting for indeterminate strength mapping S or Z e Setting for Shell Software timing On or Off e Model name as specified in the Shell Software device_name e Setting for timing measurement On or Off e Setting for loop mode On or Off e Runtime vector count e Evaluation status Enabled or Disabled The SIGnal INSTance Imc and SIGnal INSTance vector commands print subsets of the information provided by SIGnal INSTance dump e The SIGnal INSTance Imc p shell command prints the Shell Software timing setting On i
179. easurement The timing information is saved in the file TILS299 TIM Test Vector Logging ModelSource and LM family modeling systems can capture and write to a file the input stimuli presented to a hardware model as well as the resulting sampled output values Test vectors are useful for debugging a simulation and for verifying the functionality of a hardware model You enable test vector logging by using the command lm_log_test_vectors described in lm_log_test_vectors Command Reference on page 94 The following illustration also shows an example of test vector logging for the model TILS299 The six lines of code following the timing measurement enable test vector logging implement the logging for 4200 time units the duration of the simulation and then disable the logging The test vectors are saved in a file named hwm299 vec Instantiate UUT ModelSource TILS299 hardware model U1 TILS299 U1 CLK clkw CLR clrw HI a w Pp T O za fe e B WN FO July 31 2001 Synopsys Inc 91 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide F iolw 5 G iolw 6 H iolw 7 Gl glw G2 g2w QA qaliw QH qhlw SO sOw S1 siw SL slw SR srw SIMULATION run time duration initial begin Slm_timing_measurements tbench U1 1 TILS299 TIM 4200 Slm_timing_measurements tbench U1 0 TILS299 TIM end ini
180. ed in the following sections of this chapter e Prerequisites on page 83 e The ma_verilog Software Tree on page 84 e Using Hardware Models on page 85 Prerequisites If you have not already done so perform these tasks e Install the Verilog XL simulator according to instructions provided by Cadence Design Systems Inc e Perform the complete installation and configuration of the hardware modeling system including hardware and software R3 5a or later as outlined in the Quick Reference in Chapter 1 of either the ModelSource Hardware Installation Guide or the LM family Hardware Installation Guide e Boot the modeler if it is not already booted July 31 2001 Synopsys Inc 83 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide The ma_verilog Software Tree The ModelAccess for Verilog ma_verilog directory structure is illustrated in Figure 4 ma_verilog lib include om sun4_5 6 mav_include h sun4_5 6 mav o mav_include_code h Imvsg mav sl mav imp pa_hp102 pa_hp102 mav o Imvsg mav sl pa_hp11 pa_hp11 F Imvsg rs6000_4 1 5 rs6000_4 1 5 mav o Imvsg mav so pent pent mav lib Imvsg exe mav dll mav_miti lib mav_mti dll Im_vconfig mav_static lib Figure 4 The ma_verilog Software Tree Generating the Verilog XL Model Shell You must use the Logic Modeling Verilog Shell Generator Imvsg to generate new Verilog HDL shells model v files for the h
181. ed to dealing with each 1 bit element one at a time Table 28 shows the elements of a sample device the Texas Instruments TIBPAL22V 10 All window elements for this example are 1 bit wide with read and write access Table 28 Elements in a TIBPAL22V10 Device Element Description Q23 PAL Internal Register connected to pin 23 Q22 PAL Internal Register connected to pin 22 Q21 PAL Internal Register connected to pin 21 Q20 PAL Internal Register connected to pin 20 Q19 PAL Internal Register connected to pin 19 Q18 PAL Internal Register connected to pin 18 Q17 PAL Internal Register connected to pin 17 Q16 PAL Internal Register connected to pin 16 Q15 PAL Internal Register connected to pin 15 Q14 PAL Internal Register connected to pin 14 July 31 2001 Synopsys Inc 237 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide gt Note Because the block diagram of this part does not denote specific names for the elements their names reflect the output pin numbers on the DIP symbol for example pin 23 maps to Q23 For example to program the first six elements listed in Table 28 as counters and register the last four elements as data pins from an I O port you would use the following commands ADD BUS CNTR 1 230 023 1I 230 022 1I 230 021 1 230 020 1I 230 019 I 230 Q18 ADD BUS DATA 1 230 Q17 1I 230 016 I 230 015 I 230 Q14 ADD LISTS CNTR
182. eded by the simulator to configure a model You configure SmartModels when you instantiate them in your design using these SWIFT parameters This could take the form of Verilog defparams VHDL generics or symbol properties depending on the simulator you are using For details refer to the documentation for your simulator 18 Synopsys Inc July 31 2001 Simulator Configuration Guide Table 1 lists the SmartModel configuration parameters All SmartModels require an Chapter 1 Using Synopsys Models with Simulators InstanceName Timing Version and DelayRange In addition some SmartModels need a MemoryFile JEDECFile SCFFile or PCLFile attribute FlexModels use a slightly different set of attributes for configuration described in FlexModel SWIFT Parameters on page 24 Table 1 SmartModel SWIFT Parameters Parameter Name Used By Description InstanceName All SmartModels Specifies an instance name for a particular instance of a SmartModel Used in messages to indicate which instance is issuing the message also used in user defined timing Can be set by the simulator from the hierarchical name in the HDL description or can be set using the InstanceName property on the symbol Timing Version All SmartModels Specifies the timing version a SmartModel instance should use when scheduling changes on its outputs or checking setup and hold times on its inputs The allowed values are min
183. edures are organized into the following major sections e Setting Environment Variables on page 111 e Using SmartModels with MTI Verilog on page 113 e Using FlexModels with MTI Verilog on page 115 e Using MemPro Models with MTI Verilog on page 118 e Using Hardware Models with MTI Verilog on page 120 Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel FlexModel and MemPro model installation tree as shown in the following example setenv LMC HOME path_to_models_installation 2 Make sure MTI Verilog is set up properly in your environment July 31 2001 Synopsys Inc 111 Chapter 5 Using MTI Verilog with Synopsys Models Simulator Configuration Guide 3 Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example setenv LM LICENSE FILE path_to_product_authorization_file setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_file You can put license keys for multiple products for example SmartModels and hardware models into the same authorization file If you need to keep separate authorization files for different products use a colon sep
184. ee eee eee 18 SmartModel SWIFT Parameters onc c snk cede cedeneeneanisrad oo ees 18 Instantiatme SmartModels i ek a rdnr ti 5 a ee es 20 The SWIFT Command Channel ota ch ces bees vee skies Pde ee dade eae he 21 Fault Simulations ee ee ee ee ae ee eer ee ee eee eee wee 23 Using FlexModels with SWIFT Simulators 4cc doses vsawiyede sade veanees 24 flexm_setup Command Reference ssi ns oeegeh eae bagi ckdesanwes dies 25 Instantiating FlexModels with Direct C Control 0000 26 Using MemPro Models with VHDL and Verilog Simulators 29 Using MemPro Models with VHDL Simulators 2 04 31 Using MemPro Models with Verilog Simulators 004 31 Instantiatinge MemPro Models sorri 6 HARA RIVERA OS 44 ALO KERR 32 Controlling MemPro Model Messages 00 cee ee eee ees 33 Controlling MemPro Message Output 02 4265 se0eesscnsuwaveswases 34 Tile Level COmtaniS nh ih 9 i he en ho ee ee eee dos 34 Using Hardware Models with Different Simulators 00 35 Linking Other Supported Simulators snesena n aeee n nae eux ede 35 Chapter 2 Using VCS with Synopsys Models ssssssssssssosssoesoessosesoee 37 COFEIVIO sorrrracisrioiintusacidi ELASSEREKS OEE ki pds iiba HERES ED 37 Setting Environment Variables 6ccncchededer dd ceive tedudenved ee ededans 38 July 31 2001 Synopsys Inc 3 Contents Simulator Configuration Guide Using SmattModels with YCS ancien es de
185. eling s hardware modeler SFI software Sun4 Solaris libsfi lt sfi_dir gt lib sun4 solaris libsfi so Logic Modeling s hardware modeler SFI software Sun4 SunOS libsfi lt sfi_dir gt lib sun4 sunos libsfi so Logic Modeling s hardware modeler SFI software Window NT where ext is so for Solaris a for AIX or sl for HP UX 4 Run the hm_entity script to generate a vhd file for the hardware model as shown in the following example For details on hm_entity refer to hm_entity Command Reference on page 167 5 You are now ready to use the model in your simulation MTI VHDL Example Using TILS299 Hardware Model Here is an example that uses the TILS299 hardware model Follow these steps 166 1 2 Put the TILS299 hardware model in the testbench Create a working library directory by invoking vsim gui and selecting Library Create This creates a working directory called work Compile the vhd files as shown in the following example vecom work work TILS299 vhd TB_TILS299 vhd This step compiles the two VHDL files and puts them in the specified work library Note that the TILS299 vhd file must be specified first or you get an error because the TB_TILS299 vhd utilizes the TILS299 entity Invoke the simulator as shown in the following example o vsim When the window comes up select the testbench to load Use the View Wave
186. ements of a model instance specified by inst_path The SmartModel Windows feature allows you to view and change the contents of a model s internal registers through predefined windows which usually reflect the model s internal state After enabling SmartModel Windows you can read from the register using an appropriate Verilog command or by adding the path name to the list of signals being traced If you attempt to read from an internal register without enabling SmartModel Windows the window content is not read The lm_monitor_enable and lm_monitor_disable commands are provided for compatibility with the historic environment You cannot access arrays of registers as in memory window elements using these commands In addition you cannot create dynamic windows needed for SmartCircuit models if you define a window in a configuration file The lm_monitor_vec_map and lm_monitor_vec_unmap commands provide these capabilities gt Note Accessing internal states is memory intensive so you may notice some performance degradation when SmartModel Windows is enabled Syntax lm_monitor_enable inst_path window_element lm_monitor_disable inst_path window_element lai_enable_monitor inst_path window_element lai_disable_monitor inst_path window_element Arguments inst_path The path name to the SmartModel instance for which SmartModel Windows
187. en otherwise a new file is created ReportStatus Prints a message that describes the configuration status of a model SetConstraints ON OFF Enables or disables timing constraint checks for a model By default models check for and warn of timing constraints TS Note Some simulator vendors supply additional interfaces to the DumpMemory ReportStatus and SetConstraints capabilities SmartBrowser Commands for SmartCircuit Models In addition to the model commands which apply to all SmartModels the command channel also supports the following SmartBrowser commands for SmartCircuit models e Analyze Commands e Assign Commands e Examine Commands e List Commands e Set and Show Commands e Trace Commands e General Commands July 31 2001 Synopsys Inc 21 Chapter 1 Using Synopsys Models with Simulators Simulator Configuration Guide For more information about these SmartBrowser commands refer to the SmartModel Library Users Manual Session Commands Session commands act on all models in the simulation session You can enable session commands by setting the LMC_COMMAND environment variable Here is an example that enables tracing of timing files and model versions followed by a list of all the session commands setenv LMC_COMMAND TraceTimeFile on TracePath ON gt Note The session command strings are case insensitive as illustrated above ON and on are equivalent TraceTimeFile ON OFF Enables or
188. ena eee inne d esa eea was 190 Cyclone genlintert ace Processing ica ci icki edo eehed cennsdonieket ean 191 Chapter 10 Using Leapfrog with Synopsys Models cccccccccccccccccscces 195 Be eee ee ee eee EEE ey er ee ee emery ere T ewe ei cee ee eee 195 mets Eivironm nt Varies 24 454d his 0449 dE RE AH ROE ROE 195 Using SmartModels with Leapfrog aceevedsieseceedareensey nae chases 197 6 Synopsys Inc July 31 2001 Simulator Configuration Guide Contents Using FlexModels with Leapfrog lt cicccedeniviccienee iwi yard esiee dans 198 Using MemPro Models with Leapfrog 0 00 e eee ee eee 198 Using Hardware Models with Leapfrog 000 cee cece eee eee 201 Leapfrog Example with TILS299 Hardware Model 201 Fes UTNES ee oe re a ee eee eee se ee eee Sere E ewe 202 Chapter 11 Using NC VHDL with Synopsys Models ccc cece cece ccccccscees 205 Bled ee ee ee ee ee ee ee eT eee eer ye eee 205 Setting Environment Variables si05 40shc0oeeieoeaesiaeseresi ans Ea 205 Using SmartModels with NC VHDL indo ied ddd doe ne be eeedeeeo ane 206 Using FlexModels with NC VHDL i614 40ccd corde ese ene ceees beens ee carn 208 Using MemPro Models with NC VHDL ics 40sdescussaweedc coeds eeiees 210 Using Hardware Models with NC VHDL 6ne 6 ede sanbeaneeev dud neren 213 NC VHDL Example with TILS299 Hardware Model 213 RV WI gnc tent tas es ado ec eess are se onde si oe ere aE 214 Chapter
189. er model_fx_mti v Example using bus level wrapper model v without timing model U1 model ports defparam U1 FlexModelId TMS INST1 Example using bus level wrapper model v with timing model U1 model ports defparam U1 FlexTimingMode FLEX TIMING MODE ON U1 TimingVersion timingversion U1 DelayRange range U1 FlexModelId TMS_INST1 Compile your code as shown in the following examples UNIX vlog testbench workdir examples verilog model v workdir examples verilog model_fx_mti v incdir SLMC_HOME sim pli sre t inedir workdir sre verilog NT gt vlog testbench workdir examples verilog model v workdir examples verilog model_fx_mti v incdir LMC_HOME sim pli sre inedir workdir sre verilog Invoke the simulator as shown in the following examples HP UX vsim pli SLMC_HOME 1ib hp700 1ib swiftpli_mti sl design Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 5 Using MTI Verilog with Synopsys Models Solaris vsim pli LMC_HOME 1lib sun4Solaris 1lib swiftpli_mti so design Linux vsim pli LMC_HOME lib x86_linux lib swiftpli_mti so design NT gt vsim pli LMC_HOME lib pcnt 1ib swiftpli_mti dll design gt Note For information on LMTV commands that you can use with FlexModels on MTI Verilog refer to LMTV Command Reference on page 279 Static Linking with LMTV If you cannot use the Synopsys supplied swiftpl
190. er ModelType HARDWARE July 31 2001 Synopsys Inc 87 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide parameter TimingVersion TILS299 MDL parameter DelayRange Max Invoke the model initial begin S1lmhw_model TILS299 MDL ModelType attr timingversion TimingVersion attr delayrange DelayRange Saga ye CTR Sin CIR inl GL Min pG 3 inl S00 STE SOAs Vin s Sey Sins SR out QA QA STRONG QA PULL out QH QH_ STRONG QH_ PULL io A A STRONG A PULL io B B_ STRONG B_PULL io C C__STRONG C__PULL io D D_ STRONG D_PULL io E E_ STRONG E_PULL io F F_ STRONG F_PULL io G G STRONG G PUIL io H H_ STRONG H_ PULL end endmodule autoexpand_vectornets Instantiating the Hardware Model Before instantiating a hardware model you first examine the model v file you created to get the port names to use in the instantiation and also to see whether you want to change any of the model s default parameters The model v files contain default values for the model parameters which you can override using the defparam statement in the model instantiation 88 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter
191. er link PERFORMANCE OPTION High performance ModelSource Processor workstation running Sun SPARC or HP700 Cyclone running ModelSource RMS 400 MS 3200 B Ethernet Same subnet Fiber link LM 1400 High performance running LM 1400 RMS workstation running Cyclone Ethernet Same subnet High performance ModelSource Processor workstation running Sun SPARC or HP700 Cyclone running ModelSource RMS Fiber link MS 3400 MS 3200 Ethernet different subnets LM 1400 running LM 1400 RMS Figure 7 Cyclone Configuration Guidelines July 31 2001 Synopsys Inc 177 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide Cyclone User Setup Before proceeding with the setup instructions that follow perform these tasks e Install the Cyclone simulator package as described in the Cyclone Installation Guide e Install and configure the hardware modeling system including hardware and software R3 5a or later as outlined in the Quick Reference in Chapter 1 of either the ModelSource Hardware Installation Guide or the LM family Hardware Installation Guide e If necessary boot the modeler e Make sure all required environment variables are set as explained in Setting Environment Variables on page 171 The ma_cyclone Software Tree The ModelAccess for Cyclone ma_cyclone directory structure is illustrated in Figure 8 ma_cyclone bin C setup sun5 5 1 Im_
192. eric commands are also sent to through the model s instance model_l synchronize 2 synch_2 timeout status Send commands to the FlexModel Instance 2 model_2 write addressl datal FLEX_WAIT_F status model_2 write address2 data2 FLEX_WAIT_F status model_2 write address3 data3 FLEX_WAIT_F status Synchronize Instance 1 amp 2 model_2 synchronize 2 synch_2 timeout status join End of fork End of program model_test July 31 2001 Synopsys Inc 273 Appendix A Using VERA with FlexModels Simulator Configuration Guide Incorporating FlexModels in a VERA Testbench To incorporate FlexModels in your VERA testbench use the following procedure For more information on creating VERA interface files and using models in VERA refer to the VERA System Verifier User Manual 1 Create a working directory and run flexm_setup to make copies of the model s interface and example files there as shown in the following example SLMC_HOME bin flexm_setup dir workdir model_fx You must run flexm_setup every time you update your FlexModel installation with anew model version Table 35 lists the files that flexm_setup copies to your working directory Table 35 FlexModel VERA Files File Name Description Location model_pkg vr Contains FlexModel VERA class and workdir src vera method definitions model_pkg vrh Contains model de
193. eriuser mav so AIX Veriuser mav so HP UX Veriuser mav sl NT Veriuser mav_mti dll b Add an item in the PLIOBJS environment variable list setenv PLIOBJS mav ext c Use the pli switch on the simulator invocation line vsim pli mav ext TS Note For steps b and c fill in the correct extension for your platform 2 Regardless of the option you choose you must locate the ModelAccess PLI library for the simulator using a platform specific environment variable or by specifying the full path to the library in Step 1 Here are examples for setting the environment variables which show the full paths to the libraries Solaris setenv LD LIBRARY PATH hardware_model_install_path sms ma_verilog 1ib sun4_5 6 mav so 120 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 5 Using MTI Verilog with Synopsys Models HP UX setenv SHLIB PATH hardware_model_install_path sms ma_verilog 1ib pa_hp102 mav sl AIX setenv LIBPATH hardware_model_install_path sms ma_verilog 1ib rs6000_4 1 5 mav so For NT add this path to the PATH user variable hardware_model_install_path sms ma_verilog lib pent 3 Generate a Verilog module definition or shell for each hardware model that you want to use by running the Synopsys provided Imvsg script as shown in the following example o Imvsg destination_model MDL For this to work the hardware_model_install_path sms ma_verilog bin platform directo
194. es the file name of the memory image file to preload during model initialization If memoryfile is set to a null string memoryfile memory image preloading during initialization is disabled Supported files formats are SmartModel Memory Image Motorola S Record Intel Hex and Verilog readmemh Memory models can also be loaded using the mem_load command default_data String Specifies the default data returned from all uninitialized memory addresses Note Models in non volatile memory classes may not have their Default Memory Value set to anything except all ones Any other setting is ignored and MemGen issues an warning message_level Integer Specifies the type or types of messages returned by the model For a detailed description of message types refer to Controlling MemPro Model Messages on page 33 30 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 1 Using Synopsys Models with Simulators MemPro models are supported on the simulators listed in Table 5 Table 5 MemPro Supported Simulators Verilog Simulators VHDL Simulators VCS Scirocco Verilog XL VSS NC Verilog Cyclone MTI Verilog Leapfrog MTI VHDL NC VHDL Each of the simulators in Table 5 has its own chapter in this manual that explains the simulator specific procedure for using MemPro models in those environments Using MemPro Models with VHDL Simulators This
195. es the path to the model VCS template file incdir LMC_HOME sim pli srce Includes the path to the flexmodel_pkg inc file which contains Verilog task definitions for general FlexModel interface commands incdir LMC_HOME bin flexm setup model_fx src verilog Includes the path to the model specific Verilog task files including model_pkg inc P SLMC_HOME sim pli src slm_pli tab Specifies the FlexModel MemPro PLI table entry file LMC_HOME 1ib sun4Solaris 1ib slm_pli o Specifies the platform specific PLI object file l vcs_sim log Specifies a log file where VCS writes compilation and simulation messages Mupdate This specifies incremental compilation which causes VCS to compile only the modules that have changed since the last run RI This makes VCS run interactively VCS invokes the XVCS GUI after compilation and pauses the simulator at time zero lmc swift This switch causes VCS to load the SWIFT interface July 31 2001 Synopsys Inc 47 Chapter 2 Using VCS with Synopsys Models Simulator Configuration Guide Two FlexModels on Solaris This example shows how to use the mpc740_fx and mpc750_12_fx FlexModels together with VCS on Solaris Invoke the simulator as shown in the following example VCS_HOME bin vcs LMC_HOME bin flexm_setup mpc750_12 fx examples verilog mpc750_12 tst v LMC_HOME bin flexm_setup mpc750_12_ fx examples verilog mp
196. essing This section describes how genInterface processes input Shell Software to create the VHDL shell needed by Cyclone Note that genInterface ignores NAM files when processing pin names July 31 2001 Synopsys Inc 191 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide Rules for Signal Renaming Because certain characters and keywords are permitted in Shell Software pin names but are illegal as VHDL signal names genInterface must convert these signal names in order to generate correct VHDL The rules that genInterface uses to map the signal names to legal values are explained in the following sections The following rules are applied by default You can explicitly specify the mapping for any signal name by using the pin_name_ovr statement in the genInterface setup file as described in Overwriting Pin Names Per Model on page 186 Renaming Buses The genInterface program sorts all pins in ascending order Groups of pins having the same basename are combined into buses If part of the bus is in a different mode for example inout and out then the bus is split by mode and the basenames are made unique For example consider the following bus described in the Shell Software out_pin A 21 12 110 109 108 107 106 105 104 103 99 98 io_pin A 11 6 97 96 95 94 93 92 A 29 22 119 118 117 116 115 114 113 112 This is converted as follows in the generated VHDL file A INOUT
197. execute_command n command n close OFI i E system execute_command Figure 1 run_flex_examples_in_vcs pl Script 50 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models Example Simulator Run Script The run_flex_examples_in_vcs pl script also creates an example simulator run script in your current working directory for the specified model You can use this run script to invoke VCS after running the run_flex_examples_in_vcs pl script The following example shows the contents of the Example_Simulator_Run_Script after running the run_flex_examples_in_vcs pl script using the mpc860_fx model This is an example of VCS command line to run the supplied FlexModel testbench Note The model version was calculated using the flexm_setup command d ves501 vcs5 0 1A bin vcs Mupdate RI 1 vcs_sim log d lmgqa2 install lmc_home models mpc860_fx mpc860_fx02009 examples veri log mpc860_tst v t tincdirt d lmgga2 install lmc_home models mpc860_fx mpc860_fx02009 src v erilog libext inc d imgga2 install lmc_home models mpc860_fx mpc860_fx02009 examples veri log mpc860 v d imgga2 install lmc_home models mpc860_fx mpc860_fx02009 examples veri log mpc860_fx_ves v d lmgqa2 install lmc_home lib hp700 lib slm_pli o P d imgga2 install lmc_home sim pli src slm_pli tab lmc swift tincdirt d 1lmgqa2 install 1lmc_home sim pli sre
198. f you have specified SIGnal INSTance Ist Off if you have not for the selected instances SIGnal INSTance Imc p allshell prints the Shell Software timing setting for all hardware model instances if you have at least one instance selected If you do not specify one of the p arguments this command will print a list of the available subcommands e The SIGnal INSTance vector command prints the runtime vector count of the selected instances Performance Monitoring You can monitor the performance of the hardware modeler and append the results to the simulator log file after simulation To enable performance monitoring in the window where you are running the simulator enter the following o setenv LM OPTION monitor_performance For more information refer to Performance Monitoring in the ModelSource User s Manual July 31 2001 Synopsys Inc 263 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Ending the Simulation Session Termination of a normal simulation session notifies the hardware modeling system that the simulation session has ended All modeling system resources being used by that simulation are then made available for other users If the simulation exits abnormally orphaned processes may exist on the modeling system even though the simulation has terminated If Imdaemon is running on your workstation it automatically deletes orphaned processes You can also use the Im
199. files model_user_pkg inc Clock frequency setup and user workdir src verilog customizations model_fx_vcs v A SWIFT wrapper that you can use to workdir examples verilog instantiate the model 42 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models Table 8 FlexModel VCS Verilog Files Continued File Name Description Location model v A bus level wrapper around the SWIFT workdir examples verilog model This allows you to use vectored ports for the model in your testbench model_tst v A testbench that instantiates the model and workdir examples verilog shows how to use basic model commands 3 Update the clock frequency supplied in the model_user_pkg inc file to correspond to the CLK period you want for the model This file is located in workdir sre verilog model_user_pkg inc where workdir is your working directory 4 Add the following line to your Verilog testbench to include FlexModel testbench interface commands in your design include model_pkg inc lt gt Note Be sure to add model_pkg inc within the module from which you will be issuing FlexModel commands Because the model_pkg inc file includes references to flexmodel_pkg inc and model_user_pkg inc you don t need to add flexmodel_pkg inc or model_user_pkg inc to your testbench 5 Instantiate FlexModels in your design defining the ports and de
200. files have been left at their default values the genInterface command creates the following files in the current directory e liblm_hw so Solaris only e IPENTIUMPRO vhd e 182451GX vhd e 182452GX vhd e 182453GX vhd e 182454GX vhd July 31 2001 Synopsys Inc 187 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide The following example shows genInterface executed on the ID3052EA hardware model Model file ID3052EA MDL genInterface m engineeringl ID3052EA MDL Copyright 1988 1996 Synopsys Incorporated 05 Sep 1996 R1 0 Processing Common files Done Processing ID3052EA MDL file Done Running make Done Running clean Done This command creates one dynamic library and a vhd file for each model specified in the command line For the Solaris example shown above the liblm_hw so library and 1D3052E vhd file are created The genInterface program requires an ANSI C compiler If you receive compiler errors while attempting to run genInterface for information about updating setup files refer to Cyclone genInterface Setup Files on page 190 Cyclone Simulation After successfully running verifySetup and genInterface you can simulate using Cyclone For detailed information on using Cyclone refer to the Cyclone Reference Manual Following are some Cyclone usage notes for hardware models Analyzing the Design You analyze the generated VHDL files created by genInterface
201. finitions for use in workdir src vera VERA testbenches 2 Compile the VERA source files in the LMC_HOME tree You need to compile three files Istmodel vr swiftmodel vr and flexmodel_pkg vr The following is a sample compile script o vera cmp lstmodel vr I LMC_HOME sim vera srce vera cmp swiftmodel vr I LMC_HOME sim vera srce vera cmp flexmodel_pkg vr I LMC_HOME sim vera src o o If you are using VERA version 4 0 or earlier you must compile the flexmodel_pkg vr object with a VERA_4 preprocessor flag Your compile line would therefore look like the following example vera cmp flexmodel_pkg vr ISLMC_HOME sim vera src DVERA 4 3 Compile the model s VERA source file model_pkg vr This file includes the flexmodel_pkg vrh file but the VERA compiler needs to find the other header files too therefore you must include the path to the other header files The following is a sample compile script vera cmp model_pkg vr IS LMC_HOME sim vera sre workdir sre vera 4 Create a VERA testbench For details refer to Creating a VERA Testbench on page 271 274 Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix A Using VERA with FlexModels 5 N Compile the VERA testbench Although you need to include only the flexmodel_pkg vrh and model_pkg vrh files in your VERA testbench the VERA compiler needs to find the other header files too therefore you need to include the
202. following example shows how you might register a 74LS74 model which has a model file named 74LS74A MDL This example assumes that MGC_WD is set to user models which contains a Shell Software directory called 741s74 lm model 741s74 m 74LS74A This command creates a user models 74LS74 component directory if one did not already exist containing the files shown in Table 30 Table 30 Sample Component Directory File Description T4LS74A rss_1 Registered Shell Software 74LS74A mgc_Im attr Compiled and registered Shell Software part part_1 EDDM part part Eddm_part attr EDDM part 74LS74 smbl_1 Symbol graphics 74LS74 mgc_symbol attr Symbol graphics T4LS74A_tech ts Source technology file TALS74A_tech tecf_1 Compiled technology file T4LS74A_tech Tf_tfile_do attr Versioned technology file July 31 2001 Synopsys Inc 251 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide gt Note Previous versions of Im_model copied Shell Software source files into the component directory and registered these files However the current version registers only a reference pathname to the Shell Software files and does not copy the files Checking the Transcript The transcript displays information about the progress of the registration in addition to notes warnings and errors The Im_model utility checks that the Shell Software is syntactically and semantically corre
203. fparams as required refer to the example testbench supplied with the model You use the supplied bus level wrapper model v in the top level of your design to instantiate the supplied bit blasted wrapper model_fx_vcs v Example using bus level wrapper model v without timing model U1 model ports defparam U1 FlexModelId TMS _INST1 Example using bus level wrapper model v with timing model U1 model ports defparam U1 FlexTimingMode FLEX TIMING MODE_ON U1 TimingVersion timingversion U1 DelayRange range U1 FlexModelId TMS_INST1 July 31 2001 Synopsys Inc 43 Chapter 2 Using VCS with Synopsys Models Simulator Configuration Guide 44 6 Invoke VCS to compile and simulate your design as shown in the following examples Solaris 9 fo p fo ves o simv workdir examples verilog model v workdir examples verilog model_fx_ves v LMC_HOME 1ib sun4Solaris 1lib slm_pli o testbench v P SLMC_HOME sim pli src slm_pli tab lmc swift incdir LMC_HOME sim pli srce t incdirt workdir sre verilog simv HP UX 2 fo o AIX o ves o simv workdir examples verilog model v workdir examples verilog model_fx_ves v SLMC_HOME 1ib hp700 1ib slm_pli o testbench v P SLMC_HOME sim pli src slm_pli tab lmc swift incdir LMC_HOME sim pli srce t incdir workdir sre verilog LDFLAGS a shared lm lc a archive simv ves o si
204. g a model using MemPro compile the VHDL code for the model as shown in the following example o cv mymem vhd 6 If you compiled the model to a library SLM_MODELS in these examples add a LIBRARY statement to your testbench LIBRARY SIM MODELS This makes models in SLM_MODELS accessible from your design You can refer to the model using a standard VHDL convention such as a CONFIGURATION statement CONFIGURATION mymem a OF mymem tst IS FOR atest FOR ALL mymem use CONFIGURATION SLM MODELS mymem behav END FOR END FOR END mymem a 7 Add LIBRARY and USE statements to your testbench LIBRARY SIM_LIB USE SLM_LIB mempro_pkg all This also provides access to MemPro testbench commands For more information on using the MemPro testbench interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual 200 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 10 Using Leapfrog with Synopsys Models 8 Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 For information on message levels and message level constants refer to Controlling MemPro Model Messages on page 33 9 Compile your design as shown in the following example cv w work design_name 10 Invoke Leapfrog on your design as shown in the followin
205. g example sv design_name Using Hardware Models with Leapfrog To use hardware models with Leapfrog follow this procedure For the latest information on supported features refer to the Cadence documentation 1 Make sure Leapfrog is set up properly and all required environment variables are set as explained in Setting Environment Variables on page 195 2 Add the hardware model install tree to your path variable as shown in the following example set path install sms bin platform path 3 Run the install sh script so that the hardware models option is turned on and the LMlibrary vhd LMpackage vhd and LMproc vhd are created Also make sure the cds lib file points to the correct libraries including LMSFI which is located in the install area 4 Create your own library directory for files that will be generated for the hardware model In the Leapfrog Notebook you can set up the directory so that the library files get placed in there by using the Library menu 5 Generate a custom Leapfrog simulator executable sv to work with the hardware model and imported Verilog model This is done in the install sh The install generates a new svvlog exe When this completes you are ready to run using the custom sv executable Leapfrog Example with TILS299 Hardware Model The following example uses the TILS299 hardware model to show how to set up hardware models for use with Leapfrog 1 Create a testbench to instantiate
206. g messages apply to situations that users may want to check but are not obviously wrong For example MemPro generates a warning message when significant bits of an address are ignored Info Info messages inform you of the status or behavior of the model MemPro generates info messages infrequently For example when a memory model is initialized from a file MemPro issues an info message Timing MemPro uses timing messages to report timing constraint violations Typical situations that cause timing messages are setup or pulse width violations X Handling MemPro generates X handling messages if a model samples unknowns on input ports when valid data was expected July 31 2001 Synopsys Inc 33 Chapter 1 Using Synopsys Models with Simulators Simulator Configuration Guide Controlling MemPro Message Output There are three ways to control messaging for MemPro models 1 Set individual Message Settings when you specify the model message categories except Fatal 2 Use the message_level generic or parameter For more information refer to Message Level Constants on page 34 3 Use a command stream or testbench command By default MemPro models display all the general message categories Fatal Error Warning Info Timing and X handling If you set a generic or parameter for a model instance that setting overrides the default behavior In turn if the command stream or testbench interface is used it overrides the gener
207. genInterface again You can add your custom code to the newly updated vhd files e If you don t want to save the old vhd files delete them from the target directory or change the overwrite_files setting to yes before you run genInterface Attention Whenever you receive this warning you must correct the situation and re run genInterface so that a complete integrated set of vhd files and the corresponding C library are created The genInterface program keys the results of each session so if you attempt to mix files from different genInterface sessions in your Cyclone simulation you receive a fatal simulation error LM_HW integration error Keys do not match Selecting Options Per Model The synopsys_Im_hw setup file allows you to set specific options per model including the following e delete_files e overwrite_files e cflags DLM_HW_DEBUG e pin_name_ovr The cflags debugging options are intended for system administrators and are explained in cflags on page 191 The pin_name_ovr statement which enables the overwriting of automatically generated pin names is only available on a per model basis as explained below July 31 2001 Synopsys Inc 185 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide Overwriting Pin Names Per Model The Shell Software syntax for hardware model pin names uses special characters and VHDL keywords that are not allowed in legal VHDL signal names Therefo
208. gns around variables and backslashes in paths 1 Create a working directory and run flexm_setup to make copies of the model s interface and example files there as shown in the following example LMC_HOME bin flexm setup dir workdir model_fx 160 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 8 Using MTI VHDL with Synopsys Models You must run flexm_setup every time you update your FlexModel installation with anew model version Table 20 describes the FlexModel interface and example files that the flexm_setup tool copies Table 20 FlexModel MTI VHDL Files File Name Description Location model_pkg vhd Model command procedure calls for HDL workdir src vhdl Command Mode model_user_pkg vhd Clock frequency setup and user workdir src vhdl customizations model_fx_mti vhd A SWIFT wrapper for the UNIX model workdir examples vhdl model_fx_mti_nt vhd A SWIFT wrapper for the NT model workdir examples vhdl model_fx_comp vhd Component definition for use with the model workdir examples vhdl entity defined in the above SWIFT wrapper file This is put in a package named COMPONENTS when compiled model vhd A bus level wrapper around the SWIFT model workdir examples vhdl This allows you to use vectored ports for the model in your testbench This file assumes that the COMPONENTS package has been installed in the logical library slm_lib model_tst
209. h MemPro 34 license file settings 181 MemPro error 33 system hardware and software 175 MemPro fatal 33 MS 3200 175 MemPro info 33 MS 3400 175 MemPro timing 33 MTI Verilog MemPro warning 33 simulating using LMTV 113 MemPro X handling 33 with FlexModels 115 SmartModel error 233 with Hardware models 120 SmartModel format 233 with MemPro models 118 SmartModel note 233 MTI VHDL SmartModel trace 233 With FlexModaly 160 SmartModel warning 233 with hardware models 165 MGC component interface 247 with MemPro models 163 Model Access with SmartModels 157 197 Cycolne configuration options 175 Model directory 14 Model files N model_fx_sim vhd 161 ncshell command 206 MODEL property 224 neshell file 208 model v files generated by crshell 86 nesim command 207 model vy files generating 84 nesim file 210 model vhd 115 161 NC Verilog model vhd file 105 simulating with LMTV 103 with hardware models 108 with MemPro models 108 with SmartModels 103 neverilog command 109 NC VHDL with FlexModels 208 with MemPro 210 model_fx_comp vhd 161 model_fx_sim vhd 115 161 model_fx_sim vhd file 104 model_pkg o 27 model_pkg vhd 161 model_tst vhd 115 161 model_tst vhd file 105 with SmattModels 206 model_user_pkg vhd 161 novhdicomnanmd oe ModelAccess nologvectors signal instance command 261 for Cyclone 174 NT for QuickSim H 244 compiling C files 29 for Verilog 85 298 Synopsys Inc July 31 2001 Simulator Configuration Guide P
210. h Verilog XL The procedures are organized into the following major sections e Setting Environment Variables on page 59 e Using SmartModels with Verilog XL on page 61 e Using FlexModels with Verilog XL on page 79 e Using MemPro Models with Verilog XL on page 81 e Using Hardware Models with Verilog XL on page 83 Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel FlexModel and MemPro model installation tree as shown in the following example setenv LMC HOME path_to_models_installation July 31 2001 Synopsys Inc 59 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide 2 Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example Q setenv IM LICENSE FILE path_to_product_authorization_file Q setenv SNPSLMD_LICENSE_FILE path_to_product_authorization_file You can put license keys for multiple products for example SmartModels and hardware models into the same authorization file If you need to keep separate authorization files for different products use a colon separated list UNIX or semicolon separated list
211. h instead of the loadplil switch July 31 2001 Synopsys Inc 107 Chapter 4 Using NC Verilog with Synopsys Models Simulator Configuration Guide Static Linking with LMTV If you cannot use the Synopsys supplied swiftpli shared library refer to the Cadence documentation for information on using the PLI Wizard to build your own PLI library Synopsys still ships the files needed to build your own PLI These include e edited copy of veriuser c in the LMC_HOME sim pli src directory e LMTV object Imtv o in the LMC_HOME lib platform lib directory e C Pipe shared library slm_pli_dyn ext in the LMC_HOME lib platform lib directory If you build your own PLI you will need to edit the veriuser c file to pick up the LMTV header files as follows a After include vxl_veriuser h add include ccl_Imtv_include h b After add user entries here add include ccl_l1mtv_include_code h Using Hardware Models with NC Verilog This section explains how to use Release 3 5a of ModelAccess for Verilog to interface hardware models with NC Verilog It is not necessary to edit and use the Makefile nc to build a standalone version of the simulator to link to the hardware modeler Note that dynamic linking is only supported on version 2 8 and above of NC Verilog on HP UX and Solaris and version 3 0 on NT 1 There is no need to build a Verilog executable You can use the one from CDS_INST_DIR tools bin b
212. h_to_product_authorization_file July 31 2001 Synopsys Inc 217 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide You can put license keys for multiple products for example SmartModels and hardware models into the same authorization file If you need to keep separate authorization files for different products use a colon separated list UNIX or semicolon separated list NT to specify the search path in your variable setting Caution Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you use for snpslmd based authorizations 3 Set MGC_HOME to the location of your Mentor installation and make sure QuickSim II is set up properly in your environment setenv MGC_HOME path_to_Mentor_installation 4 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv LM DIR hardware_model_install_path sms 1m_dir setenv LM_LIB hardware_model_install_path sms models hardware_model_install_path sms maps If you put your models in a directory other than the default of sms models modify the above variable setting accordingly 5 Depending on your platform set your load library variable to point to the platform 218 specific directory in
213. hdl1 model_user_pkg vhd where workdir is your working directory 4 Compile a dummy module to force linking of CLI library functions as shown in the following example cp SLMC_HOME sim vss src vss_dummy_calls c vss_dummy_calls c cli ansi s add cf vss_dummy_calls c vss_dummy_calls 146 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 7 Using VSS with Synopsys Models 5 Link the FlexModel binary into the vhdlsim simulation executable cli ansi s build libs SLMC_HOME 1ib platform 1lib slm_vss o where platform is hp700 or sun4Solaris The new version of vhdlsim you just created must be used when you simulate a design that includes FlexModels This vhdlsim must be defined as the first vhdlsim in your UNIX search path 6 Add the following line to your synopsys_vss setup file SIM LIB SLIM LIB PATH TIMEBASE PS 7 Compile the FlexModel VHDL files into logical library slm_lib as follows o vhdlan c w slm lib LMC_HOME sim vss src slm_hdlc vhd vhdlan c w slm lib LMC_HOME sim vss src flexmodel_pkg vhd vhdlan c w slm lib workdir src vhdl model_user_pkg vhd vhdlan c w slm lib workdir sre vhdl model_pkg vhd vhdlan c w slm lib workdir sre vhd1 model_fx_comp vhd vhdlan c w slm lib workdir src vhdl model_fx vss vhd vhdlan c w slm lib workdir sre vhdl model vhd 8 Add LIBRARY and USE statements to your testbench library slm lib use slm lib flexmodel_pkg all use slm lib model_pkg
214. he Symbol Editor in Design Architect to modify the appearance of the automatically generated symbol For more information refer to your Design Architect documentation Verifying the Technology File During registration lm_model calls the tmg_to_ts converter This converter extracts timing information from the following Shell Software files to create a Technology File e Variable declarations DCL file e Timing checks TCK file e State tracking TRK file e Delays DLY file e Force values FRC file The technology file specifies propagation delays and some timing checks as well as technology dependent data for the simulation model Table 31 shows how Shell Software timing statements are converted into technology file statements July 31 2001 Synopsys Inc 253 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide gt Note Many Shell Software statements have no technology file equivalents The tmg_to_ts converter includes each untranslatable statement in the technology file as a comment and or generates a warning message For this reason we recommend that you use the Shell Software timing files instead of the technology file during simulation For instructions refer to Timing Shell Selection on page 258 Table 31 Shell Software to Technology File Conversion Shell Software Statements Technology File Statements cycle_time input_state storage_pin timi
215. hich has the SBus or EISA card connection to the modeling systems This configuration eliminates network overhead in the communication between the modeling system processor and the simulation July 31 2001 Synopsys Inc 175 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide Option B In this configuration the Cyclone simulation is executing on a different workstation from the ModelSource Processor workstation In this case the simulation workstation and the ModelSource Processor workstation must be on the same Ethernet subnet Option C Because the LM 1400 has its own dedicated CPU within the LM 1400 chassis the simulation must be run on a separate workstation For best performance with an LM 1400 or any of the LM family hardware model servers keep the simulation workstation and the LM 1400 on the same Ethernet subnet Option D In this configuration the hardware modeling system which can be either a ModelSource system or an LM family hardware model server exists on a different Ethernet subnet from the workstation on which the Cyclone simulation is running Because of the extra overhead of the router this is a lower performance configuration 176 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models ModelSource Processor Sun SPARC or HP700 with SBus or EISA card running Cyclone and MS 3400 MS 3200 ModelSource RMS A BEST Fib
216. hw_slang c setup csh geninterface Im_hw_slang h setup sh verifySetup synopsys_Im_hw setup pa_hp102 geninterface verifySetup synopsys_Im_hw setup hp700 synopsys_Im_hw setup solaris Figure 8 ModelAccess for Cyclone Installation Tree The setup process consists of the following tasks e Setting Up Your Environment on page 179 e Running verifySetup on page 179 e Running geninterface on page 179 e Confirming License File Settings ModelSource Only on page 181 178 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models Setting Up Your Environment Make sure all required environment variables are set properly as explained in Setting Environment Variables on page 171 If any of the required environment variables are not defined the source command will fail with an error message indicating the cause of the error Running verifySetup Run the provided verifySetup program This verifies that your environment is set up correctly so that genInterface can run 1 To run verifySetup change directory to tmp then execute verifySetup as follows ed tmp verifySetup The verifySetup program returns messages confirming the setup information that will be used both the environment setup information and the genInterface setup options taken from the synopsys_Im_hw setup file For example if the hardware modeling system is not booted and avail
217. i shared library refer to the MTI documentation for information on building your own PLI and locating it for the simulator Synopsys still ships the files needed to build your own PLI These include e edited copy of veriuser c in the LMC_HOME sim pli src directory e LMTV object Imtv o in the LMC_HOME lib platform lib directory e C Pipe shared library slm_pli_dyn ext in the LMC_HOME lib platform lib directory If you build your own PLI you will need to edit the veriuser c file to pick up the LMTV header files as follows a After include vxl_veriuser h add include ccl_Imtv_include h b After add user entries here add include ccl_lmtv_include_code h July 31 2001 Synopsys Inc 117 Chapter 5 Using MTI Verilog with Synopsys Models Simulator Configuration Guide Using MemPro Models with MTI Verilog MemPro models work with MTI Verilog ModelSim using a PLI application called LMTV that is delivered in the form of a swiftpli_mti shared library in LMC_HOMElib platform lib If you cannot use the swiftpli_mti refer to Static Linking with LMTV on page 119 To use the prebuilt swiftpli_mti follow this procedure 118 l 4 To include MemPro testbench interface commands in your design add one of the following lines to your testbench Verilog testbench include mempro_pkg v C testbench include mempro_c_tb h For more information on using the MemPro testbench
218. ib 1lfsmGen This step produces a liblfsm so 1 1 file on SunOS liblfsm so on Solaris liblfsm sl on HP UX and liblfsm a on AIX 2 To build the VHDL libraries needed to simulate with SmartModels cd to the CDS_VHDL bin directory and execute the IfsmLibPckGen command ed CDS_VHDL bin 1lfsmLibPckGen This step produces a lfsmLibPck file 3 Determine where you want the SmartModel VHDL libraries to go and cd to that location Then execute the IfsmLibPck you built in the previous step 1lfsmLibPck This step can take 30 minutes or more When the process completes you get the following two VHDL files that you need to analyze in LeapFrog e SMILibrary vhd e SMpackage vhd The SMILibrary vhd file contains entity architecture pairs for all SmartModels in your LMC_HOME tree These include the generics used to configure SmartModel SWIFT parameters Note that SmartModels are identified as follows attribute FOREIGN of SmartModel architecture is LFSM LFSmartModels The SMpackage vhd file contains component declarations for the SmartModels You must specify required SWIFT parameters for every generic in a component that you want to simulate within Leapfrog For more information on required SWIFT parameters refer to Using SmartModels with SWIFT Simulators on page 18 July 31 2001 Synopsys Inc 197 Chapter 10 Using Leapfrog with Synopsys Models Simulator Configuration Guide 8 Caution On the HP platfor
219. ic or parameter value Message Level Constants MemPro provides constants for setting message levels on each instantiated model The constants described in Table 6 are defined in mempro_pkg v for Verilog simulators and mempro_pkg vhd for VHDL simulators Table 6 MemPro Message Constant Descriptions Constant Value Description SLM_ERROR 1 Fatal and error messages generated SLM_WARNING 2 Fatal and warning messages generated SLM_TIMING 4 Fatal and timing messages generated SLM_XHANDLING 8 Fatal and X handling messages generated SLM_INFO 16 Fatal and info messages generated SLM_ALL_MSGS 728_ All message types generated SLM_NO_MSGS 0 Only fatal messages generated a Note that bits 5 through 27 are unused but reserved You can combine these constants to get any combination of messages you desire The following Verilog and VHDL code fragments define a model instantiation having timing X handling and warning as well as fatal messages enabled 34 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 1 Using Synopsys Models with Simulators Verilog bankl message_level SLM_XHANDLING SLM_TIMING SLM_WARNING VHDL message_level gt SLM_TIMING SLM_XHANDLING SLM_WARNING Using Hardware Models with Different Simulators After you install your hardware modeling system the final task is to link your simulator with the Synopsys Simul
220. ical and Symbol Conventions e Default UNIX prompt Represented by a percent sign e User input text entered by the user Shown in bold type as in the following command line example ed SLMC_HOME hd1 e System generated text prompts messages files reports Shown as in the following system message No Mismatches July 31 2001 66 Vectors processed 66 Possible Synopsys Inc Preface Simulator Configuration Guide e Variables for which you supply a specific value Shown in italic type as in the following command line example setenv IMC HOME proq dir In this example you substitute a specific name for prod_dir when you enter the command Command syntax Choice among alternatives is shown with a vertical bar as in the following syntax example effort_level low medium high In this example you must choose one of the three possibilities low medium or high Optional parameters are enclosed in square brackets as in the following syntax example pinl pin2 pinN In this example you must enter at least one pin name pin but others are optional pin2 pinN Getting Help If you have a question while using Synopsys products use the following resources l Start with the available product documentation installed on your network or located at the root level of your Synopsys CD ROM Every documentation set contains overview information in the intro pdf file
221. ies 224 simulating logic models 256 SmartModel windows with 235 SWIFT interface 219 time_scale switch 230 timing switch 230 with hardware models 247 R Reconfiguration models for simulation 232 REF property 225 reg_model command 240 249 256 Register elements combining with SmartModels 237 Synopsys Inc 299 Index Registration 256 component 240 errors dealing with 252 hardware models 249 logic models 249 250 models 249 Registration tools reference 264 Related documents 1 reread modelfile command 239 restore state command 238 run_flex_examples_in_scirocco pl 130 run_flex_examples_in_vcs pl Script 51 running verifySetup 179 S save state command 238 SCFFile property 224 Schematic capture adding SmartModel to schematic 221 Schematic Editor creating instances 227 228 Scirocco hardware model utilities 136 script for hardware models 138 VHDL generics 136 with FlexModels 128 with hardware models 135 with MemPro models 132 with SmartModels 125 Scripts run_flex_examples_in_scirocco pl 130 run_flex_examples_in_vcs pl 51 scsim command 134 Selection timing shell 258 Session ending the simulation 264 setup file editing 184 SFI linking hardware models 35 SFI see Simulator Function Interface Shell Software conversion to VHDL 193 names 193 300 Synopsys Inc Simulator Configuration Guide Shell Software Cconversions with hardware models 254 Shell timing with hardware models 258 SHLIB_PATH envir
222. if the modeling system is running out of pattern memory For more information about unknown propagation refer to the Shell Software Reference Manual and the LM family Modeler Manual or the ModelSource User s Manual 260 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Indeterminate Strength Mapping The SIGnal INSTance is and SIGnal INSTance iz commands enable you to map indeterminate strength pin values received on inputs of hardware models to either strong hard or high impedance float strengths The modeling system treats high impedance strength pin values as unknowns and maps or propagates them accordingly By default the system maps indeterminate strengths to strong strengths Test Vector Logging The SIGnal INSTance logvectors p filename command turns on modeling system test vector logging for the selected instance With test vector logging enabled the inputs to the device and sensed outputs from the device are stored to filename By convention the filename used for the test vector output is device_name VEC The SIGnal INSTance nologvectors command turns off test vector logging for the selected instance which is the default behavior For example consider the following commands sig inst logvectors p SASIC2 vectors vector11 VEC dofile SASIC2 dofiles runl1l1 do sig inst nologvectors In this example the modeling system creates a test vector file called vect
223. imingMode 1 ul TimingVersion pcimaster ul DelayRange MAX For both of these examples the C testbench file must have the same instance name as follows int Id 1 status char sInstName modelId_1 Get the instance handle flex_get_inst_handle sInstName amp Id_1 amp status Create a working directory and run flexm_setup to make a copy of the model s C object file there as shown in the following example SLMC_HOME bin flexm_setup dir workdir model_fx You must run flexm_setup every time you update your FlexModel installation with anew model version Table 3 lists the files that flexm_setup copies to your working directory Table 3 FlexModel Direct C Control Files File Name Description Location model_pkg o Model specific functions for UNIX workdir src C model_pkg obj Model specific functions for NT workdir src C July 31 2001 Synopsys Inc 27 Chapter 1 Using Synopsys Models with Simulators Simulator Configuration Guide 3 Compile the C object files in with the C program that you write to drive commands into the model represented in the following examples as your_C_file c Note that these examples include creation of a working directory workdir and running flexm_setup as explained in the previous step The compile line differs based on your platform a On HP UX you need to link in the LBSD library as shown in the following example mkdir workdir fle
224. imulation with SmartModels 23 Files cds lib 200 208 211 delay DLY 253 force value FRC 253 IfsmLibPck 197 Imtv o 82 104 106 108 114 117 119 mapping pin 241 MCF 230 model vhd 105 115 161 model_fx_comp vhd 161 model_fx_sim vhd 104 115 161 model_tst vhd 105 115 161 modelsim ini 157 162 163 ncshell 208 ncsim 210 pin_map 241 pin_map example 242 SMILibrary vhd 197 SMLibrary vhd 207 SMpackage vhd 197 state tracking TRK 253 synopsys_vss setup 129 technology 249 253 264 294 Synopsys Inc Simulator Configuration Guide technology types 253 timing 251 timing check TCK 253 variable declaration DCL 253 veriuser c 62 82 104 106 108 114 117 119 vhdlsim 148 vsystem ini 162 FlexCFile 25 flexm_setup 25 27 FlexModel attributes 19 examples with VCS 45 fault simulation 23 FlexModel SWIFT parameters 24 FlexModelld 24 FlexModels dynamic linking with PLI 104 115 example isnatiations 207 209 model vhd 79 model_fx_sim vhd 79 model_pkg ince 79 model_tst vhd 79 PLI static linking 81 106 117 using with MTI VHDL 160 VHDL instantiation 207 209 with Cyclone 173 with Leapfrog 173 198 with MTI Verilog 115 with NC VHDL 208 with Scirocco 128 with VCS 42 with VERA 269 with VSS 145 FlexModelSre 25 FlexTimingMode 24 FMI libary 198 210 Force command 236 Force values file 253 G genilterface command 186 genInterface deleting intermediate files 184 July 31 2001 Simulator Configuratio
225. ing or disabling constraint checking 232 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Editing Properties Adding or changing the value of a JEDECFile SCFFile PCLFile or MemoryFile property causes the simulator to read the file and initialize the model to the power up state Select the following menu choices to change a property Edit gt Properties gt Add Edit gt Properties gt Change and Edit gt Properties Changing Timing Modes SmartModels support minimum typical and maximum timing modes Unit delay mode is not supported Select the following menu choices to display the form for changing the timing mode of specific model instances Setup gt Kernel gt Change gt Timing Mode You can also use instance names to specify which instance to change Constraint Checking Select the following menu choices to enable disable the various timing constraint checks for example setup hold Setup gt Kernel gt Constraint Mode gt Change To enable constraint checking select either State Only or Messages on the Change Constraint Mode form To disable constraint checking select Off on the Change Constraint Mode form SmartModel Library Message Formats SmartModels issue four different kinds of messages to provide relevant information to users during simulations These include e Error messages e Warning messages e Trace messages e No
226. ing system s default handling of device input and I O pins that the simulator sets to unknown Unknown Mapping Since the hardware modeling system cannot present an unknown logic level to a physical device unknown values presented to inputs of hardware models must be mapped to known values The SIGnal INSTance xp x0 x1 and xz commands map unknowns for all instances of the selected components to the previous state logic zero logic one or high impedance float respectively By default unknowns are mapped to the previous state Unknowns mapped to high impedance are also mapped to the previous state July 31 2001 Synopsys Inc 259 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide You can customize unknown handling per pin by using the p pin_name argument For example you can issue the following sig inst x0 sig inst x1 p clkl These commands map all unknowns for the selected components except for unknowns received on the clk pin to logic zero 0 Any unknowns received on clk1 are mapped to logic one 1 These Signal Instance commands perform the same function as the Shell Software on_unknown statement and the set_previous set_low set_high and set_float attributes of the in_pin and io_pin statements For more information refer to the Shell Software Reference Manual Note that explicit Shell Software settings override any Signal Instance commands Unknown Propagation The SIGnal IN
227. ir DirSep run_scirocco_ flexmodel_name open OFILE gt run_file die Could not create file run_file n if Platform eq pent else print OFILE bin csh f n print OFILE Ssource_setup_file n print OFILE Sanalyze_slm_hdlc n print OFILE Sanalyze_flexmodel_pkg n print OFILE Sanalyze_model_user_pkg n print OFILE Sanalyze_model_pkg n print OFILE Sanalyze_model_prim n print OFILE Sanalyze_model_comp n print OFILE Sanalyze_model n print OFILE analyze_model_tst n virsim_command virsim simtype Scirocco simargs vhpi slm_vhpi foreignINITelab cpipe cfgtest print OFILE virsim command n close OFILE if Platform eq pent else chmod 0777 run_file if Platform eq pent run_it wstart d TmpDir Means nothing until Scirocco is on PCNT run_it ww Srun_it Seun it run_file else run_it cd TmpDir Srun_it run_it run_file print n run_it n system S run_it Figure 6 run_flex_examples_in_scirocco pl Script July 31 2001 Synopsys Inc 131 Chapter 6 Using Scirocco with Synopsys Models Simulator Configuration Guide Example Simulator Run Script The run_flex_examples_in_scirocco pl script also creates an example C Shell simulator run script for the specified model in your STMPDIR directory You can use this run script to invoke Scirocco after running the run_flex_examples_in_sci
228. ircuit o FlexModels do not support fault simulation o SmartCircuit models do not support fault simulation e Simulator Fault analysis is supported by Mentor s QuickFault II WEDA s VerdictFault and Teradyne s LASAR For more information about fault simulation support refer to your simulator documentation e Authorization You need one of the following license features o simmodel ultra O simmodel prem o simmodel sw all o simmodel std o simmodel base o simmodel sw model model_name e g simmodel sw ttl00 In most cases you can use the same circuit description for both logic and fault simulation However you may need to supply different circuit stimuli for each type of simulation All model messages except version copyright and configuration error messages are suppressed in fault simulation Usage and timing messages are suspended because they are meaningless in a fault simulation In order to work efficiently during a fault simulation each model manages its own diverge and converge operations July 31 2001 Synopsys Inc 23 Chapter 1 Using Synopsys Models with Simulators Simulator Configuration Guide Using FlexModels with SWIFT Simulators Regardless of which simulator you are using you must configure FlexModels by defining the required SWIFT parameters or attributes shown in Table 2 for each FlexModel instance in your design You configure FlexModels when you instantiate them in your design using thes
229. is to be enabled window_element The name of the internal register to read This can be a single value or a list The default is to read all internal registers of the instance 286 Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix B LMTV Command Reference Examples The following example enables SmartModel Windows for all windows in instance U1 then reads from the predefined window element IENA Notice that you must enable SmartModel Windows before attempting to read from the window element somewhere in the testbench enable access to all windows in instance U1 Slm_monitor_enable U1 display contents of window element IENA Sdisplay Value of register IENA is th STENA The following example disables the window explicitly for the register IENA 1m_monitor_disable Ul IENA The following example disables all windows in instance U1 1lm_monitor_disable U1 The following example does not read the register IENA because SmartModel Windows was not enabled somewhere in the testbench Sdisplay Value of register IENA is h SIENA July 31 2001 Synopsys Inc 287 Appendix B LMTV Command Reference Simulator Configuration Guide lm_monitor_vec_map and lm_monitor_vec_unmap Use these commands to enable or disable direct mapping between the user defined variable var_name and a model instance s internal register window_element This mapping allows yo
230. ith timing U1 model generic map FlexModelID gt TMS INST1 FlexTimingMode gt FLEX_TIMING_MODE_ON TimingVersion gt timingversion DelayRange gt range port map model ports July 31 2001 Synopsys Inc 209 Chapter 11 Using NC VHDL with Synopsys Models Simulator Configuration Guide 8 Compile the FlexModel VHDL files into logical library slm_lib as follows o nevhdl w slm lib SLMC_HOME sim ncvhdl src slm_hdlc vhd nevhdl w slm lib LMC_HOME sim ncevhdl src flexmodel_pkg vhd nevhdl w slm lib workdir src vhdl model_user_pkg vhd nevhdl w slm lib workdir src vhdl model_pkg vhd nevhdl w slm lib workdir examples vhd1 model_fx_comp vhd ncvhdl w slm lib model_fx vhd nevhdl w slm lib workdir examples vhd1 model vhd ncvhdl w work testbench AP oP oP AP oP o 9 Elaborate your design as shown in the following example o ncelab cfgtest 10 Invoke the NC VHDL simulator as shown in the following example o nesim design Using MemPro Models with NC VHDL To use MemPro models with NC VHDL follow this procedure 1 If you have built your own Foreign Model Interface FMI shared library perform this step Attention 210 If you do not build your own FMI library skip to Step 2 NC VHDL binds in only one shared FMI library at runtime If your design uses FMI you need to build a new FMI shared library that contains your library and the MemPro library A MemPro arch
231. ive library can be found at HP UX LMC_HOME 1ib hp700 1ib libfmi_ar a Solaris SLMC_HOME 1ib sun4Solaris 1lib libfmi_ar a You must create a new archive that includes the MemPro archive library table file declaration object file and your archive Detailed instructions for this process can be found in the Foreign Model Integration chapter of the Affirma NC VHDL Simulator C Interface User Guide Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 11 Using NC VHDL with Synopsys Models As shown in the following example you must combine the contents of the MemPro library table file with your own FMI application library table include lt fmilib h gt extern fmiModelTableT CpipeModelTable extern fmiModelTableT myFMITable fmiLibraryTableT fmiLibraryTable Cpipe CpipeModelTable myFMI1ib myFMITable 0 0 Link the MemPro archive library with the new library table object file and any other FMI application object files you wish to include following the instructions in the Cadence C Interface User Guide The following examples show compiling the library table object files and linking MemPro libfm_ar a with the library table object file and the FMI application you developed shown in the examples as new_FMI_table o and your_archive a HP UX bin cc D_NO PROTO c Z ISCDS VHDL include new FMI table c bin ld b o libfmi sl new_FMI_table o your_archive a LMC_HOME 1ib hp700 1ib li
232. ject file and enter the path to your edited veriuser c source file Enter the path to the LMC_HOME lib platform lib slm_pli o object file in the PLI Object Files field Leave the Select Compiler amp Options form as is 12 13 When the Session Setup Summary form appears click Finish Click Yes when asked whether or not to build targets now The new Verilog XL executable that includes LMTV amp the C Pipe interface will then be built in the session directory Add this directory to your PATH statement to use the new Verilog XL executable Verilog XL Usage Notes for SmartModels This section describes the Synopsys Logic Models To Verilog LMTV interface You can use LMTV to instantiate and work with SmartModels in Verilog XL as described in the following sections LMTV Modes of Operation Capturing and Simulating the Design Using SmartModel Windows with Verilog XL Customizing Model Timing Simulating an Older Design Using LMTV Using FlexModels with Verilog XL July 31 2001 Synopsys Inc 63 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide LMTV Modes of Operation To take advantage of the SWIFT SmartModel Library while maintaining compatibility with the older Verilog XL specific SmartModel Library the LMTV interface has two modes of operation SWIFT SmartModel Mode and Historic SmartModel Mode SWIFT SmartModel Mode In SWIFT SmartModel mode the models you instantiate are SWIFT Smart
233. l installed it must only be booted and running Runtime Modeler Software v3 3 or later 186 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models mdlfile1 You can list individual models by their Model MDL file name such as IPENTIUM MDL Separate multiple file names with a blank space character f model _list You can create a file listing the Model MDL files to be included Create the file with one MDL file name per line a The a option allows you to generate an interface that includes all available model files found in directories specified by the LM_LIB environment variable X Hint The a option is convenient when you want to create one interface incorporating all hardware models in your environment However depending on how your LM_LIB environment variable is set this could be a large file Examples The following example creates interface files for the hardware models listed in the my models file genInterface f my models The following example creates interface files for all hardware models in the LM_LIB search path using the hardware modeling system named engineering1 genInterface m engineeringl a The following example creates interface files for the hardware models IPENTIUMPRO 182451GX I182452GX 182453GX and 182454GX genInterface IPENTIUMPRO MDL I82451GX MDL I82452GX MDL I82453GX MDL I82454GX MDL Assuming that all setup
234. le defines three variables and maps them to specific memory locations in the memory array UMEM for memory model instance U1 Note that these tasks cannot be performed using lm_monitor_enable Although the example features an array of registers the tasks are equally useful for scalar windows where you can omit the index option or set it to 0 288 Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix B LMTV Command Reference Assume a 4Kx8 memory model on a controller board Such a model would typically have one window called UMEM This window is a 4K deep array of 8 bit registers In particular the user is interested in these 3 locations Interrupt service routine LOW ADDRESS 100 Interrupt service routine HIGH ADDRESS 101 Control store 200 that are significant to the design reg 7 0 ISR_LOW variable to map to location 100 reg 7 0 ISR_HIGH variable to map to location 101 reg 7 0 CONTROL variable to map to location 200 enable monitoring of these variables Slm_monitor_vec_map ISR_LOW Ul UMEM 100 Slm_monitor_vec_map ISR_HIGH Ul UMEM 101 Slm_monitor_vec_map CONTROL Ul UMEM 200 at this time you can read write or trace these variables For example assign the address of the interrupt service routine to be 0x5000 ISR_LOW 0x00 ISR_HIGH 0x
235. lexModel and MemPro model installation tree as follows setenv LMC_HOME path_to_models_installation 2 Set the SYNOPSYS_SIM variable to point to the Scirocco installation directory as follows setenv SYNOPSYS_SIM Scirocco_installation_directory 3 Source the environ csh Scirocco environment file source SSYNOPSYS_SIM admin install setup environ csh 4 Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the product authorization file as shown in the following example setenv LM LICENSE FILE path_to_product_authorization_file setenv SNPSLMD LICENSE_FILE path_to_product_authorization_file You can put license keys for multiple products for example SmartModels and hardware models into the same authorization file If you need to keep separate authorization files for different products use a colon separated list UNIX or semicolon separated list NT to specify the search path in your variable setting 8 Caution Do not include la_dmon based authorizations in the same file with snpslmd based authorizations If you have authorizations that use la_dmon keep them in a separate license file that uses a different license server Imgrd process than the one you use for snpslmd based authorizations 5 If you are using the hardware modeler set the LM_DIR and LM_LIB environment variables as shown in the following examples setenv LM DIR hardware_model_install_path sms 1m_dir setenv LM_LIB har
236. lexModel installation with anew model version Table 16 lists the files that flexm_setup copies to your working directory Table 16 FlexModel NC Verilog Files File Name Description Location model_pkg inc Verilog task definitions for FlexModel workdir src verilog interface commands This file also references the flexmodel_pkg inc and model_user_pkg inc files model_user_pkg inc Clock frequency setup and user customizations workdir src verilog model_fx_vxl v A SWIFT wrapper that you can use to instantiate workdir examples verilog the model 104 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 4 Using NC Verilog with Synopsys Models Table 16 FlexModel NC Verilog Files Continued File Name Description Location model v A bus level wrapper around the SWIFT model workdir examples verilog This allows you to use vectored ports for the model in your testbench model_tst v A testbench that instantiates the model and shows workdir examples Verilog how to use basic model commands 2 Update the clock frequency supplied in the model_user_pkg inc file to correspond to the CLK period you want for the model This file is located in workdir sre verilog model_user_pkg inc where workdir is your working directory 3 Add the following line to your Verilog testbench to include FlexModel testbench interface commands in your design include model_
237. log model_fx_vxl v incdir LMC_HOME sim pli srce t tincdirt workdir sre verilog NT gt neverilog testbench loadp1lil swiftp1li swift_boot workdir examples verilog model v workdir examples verilog model_fx_vxl v incdir LMC_HOME sim pli sre t incdir workdir sre verilog gt Note If you are using ncelab and ncsim use the loadplil switch instead of the loadplil switch For information on LMTV commands that you can use with FlexModels on NC Verilog refer to LMTV Command Reference on page 279 Static Linking with LMTV If you cannot use the Synopsys supplied swiftpli shared library refer to the Cadence documentation for information on using the PLI Wizard to build your own PLI library Synopsys still ships the files needed to build your own PLI These include e edited copy of veriuser c in the LMC_HOME sim pli src directory e LMTV object Imtv o in the LMC_HOME lib platform lib directory e C Pipe shared library slm_pli_dyn ext in the LMC_HOME lib platform lib directory If you build your own PLI you will need to edit the veriuser c file to pick up the LMTV header files as follows a After include vxl_veriuser h add include ccl_Imtv_include h b After add user entries here add include ccl_1lmtv_include_code h 106 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 4 Using NC Verilog with Synopsys Models Using MemPro Models with NC
238. ls for use with MTI Verilog How to configure SmartModels FlexModels MemPro models and hardware models for use with Scirocco Includes a script that you can use to run FlexModel example testbenches in Scirocco How to configure SmartModels FlexModels MemPro models and hardware models for use with VSS Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 8 Using MTI VHDL with Synopsys Models Chapter 9 Using Cyclone with Synopsys Models Chapter 10 Using Leapfrog with Synopsys Models Chapter 11 Using NC VHDL with Synopsys Models Chapter 12 Using QuickSim II with Synopsys Models Appendix A Using VERA with FlexModels Appendix B LMTV Command Reference Preface How to configure SmartModels FlexModels MemPro models and hardware models for use with MTI VHDL How to configure MemPro models and hardware models for use with Cyclone How to configure SmartModels FlexModels MemPro models and hardware models for use with Leapfrog How to configure SmartModels FlexModels MemPro models and hardware models for use with NC VHDL How to configure SmartModels FlexModels MemPro models and hardware models for use with QuickSim II How to configure FlexModels for use with Vera Includes a separate procedure for using FlexModels with Vera and VCS Reference information for LMTV commands used with SmartModels and FlexModels on Verilog XL NC Verilog and MTI Verilog Typograph
239. m all users must use the same LMC_HOME in order to prevent erroneous simulation results or fatal simulation errors This precaution is necessary because the IfsmGen command modifies the liblfsm sl file to require LMC_HOME and on the HP platform the liblfsm sl file references an absolute path name to libswift sl the SWIFT library When the absolute path name is not the same as the user s LMC_HOME the result is the loading of two different versions of libswift sl during the simulation Using FlexModels with Leapfrog To use Leapfrog with FlexModels follow the same steps laid out for SmartModels in Using SmartModels with Leapfrog on page 197 On Leapfrog you use FlexModels with Direct C Control For information on the required SWIFT parameters for FlexModels which differ from regular SmartModels and how to use Direct C Control refer to Using FlexModels with SWIFT Simulators on page 24 Using MemPro Models with Leapfrog To use MemPro models with Leapfrog follow this procedure 1 If you have built your own Foreign Model Interface FMI shared library you need to perform this step in order to combine your shared library with the MemPro FMI shared library Attention 198 If you do not build your own FMI library skip to Step 3 Leapfrog binds in only one shared FMI library at runtime If your design uses FMI you need to build a new FMI shared library that contains your library and the MemPro library A MemPro
240. m cyclone src mempro_pkg vhd 4 After generating a model using MemPro compile the VHDL code for the model as shown in the following example cyan nc synthoff lang vhdl mymem vhd If you compiled the model to a library SLM_MODELS in these examples add a LIBRARY statement to your testbench nN LIBRARY SLM_MODELS July 31 2001 Synopsys Inc 173 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide This makes models in SLM_MODELS accessible from your design You can refer to the model using a standard VHDL convention such as a CONFIGURATION statement CONFIGURATION mymem_a OF mymem_tst IS FOR atest FOR ALL mymem use CONFIGURATION SLM MODELS mymem_behav END FOR END FOR END mymem_a 6 Add LIBRARY and USE statements to your testbench LIBRARY SLM_LIB USE SLM_LIB mempro_pkg all This also provides access to MemPro testbench commands For more information on using the MemPro testbench interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual 7 Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 For information on message levels and message level constants refer to Controlling MemPro Model Messages on page 33 8 Compile your design as shown in the following example o cyan
241. m_setup flexmodel_name chomp version_path if Sflexmodel_name _fx Sflexmodel_name s _fx g Sflex_or_c _fx elsif Sflexmodel_name _fz Sflexmodel_name s _fz g Sflex_or_c _fz else die nERROR running 0 Sflexmodel_name is not a FlexModel Model must have an _fx or _fz to be a FlexModel n n Sexecute_command VcsHome bin vcs Mupdate RI 1 vcs_sim log Sversion_path examples verilog Sflexmodel_name _tst v incdir Sversion_path src verilog libext inc Sversion_path examples verilog flexmodel_name Sversion_path examples verilog S flexmodel_name flex_or_c _vcs v if SPlatform eq pent Sexecute_command execute_command LmcHome Platform_lib slm_pli_vcs Ssuffix else Sexecute_command execute_command SLmcHome Platform lib slm_pli o Ssuffix Sexecute_command execute_command P SLmcHome sim pli src slm_pli tab lmc swift tincdirt LmcHome sim pli src print Sexecute_command n open OFILE gt Soutput_file die Could not create file Soutput_file n print OFILE This is an example of VCS command line to run the n print OFILE supplied FlexModel testbench n print OFILE Note The model version was calculated using the flexm_setup print OFILE nS
242. martmodel the command terminates with an error message In that case you must use the src_dir option to specify a writable directory in which to place the VHDL templates You must also specify that directory through the SMARTMODEL library mapping in the synopsys_vss setup file in your current working directory Using FlexModels with VSS To use FlexModels with VSS in UNIX follow this procedure There is no custom integration for VSS on NT but you can use Direct C Control For information on using Direct C Control refer to Instantiating FlexModels with Direct C Control on page 26 1 If you want the improved performance that comes with bused wrappers you can generate VHDL model wrapper files by invoking create_smartmodel_lib with any optional arguments For more information on the syntax for this command refer to create_smartmodel_lib Command Reference on page 144 SSYNOPSYS_SIM sim bin create_smartmodel_lib arguments gt Note The bused wrappers enable improved performance but do not work with the examples testbench shipped with the model To exercise the examples testbench use the wrappers shipped with the model see Table 19 as explained in the rest of this procedure If you are using the bused wrappers adjust accordingly July 31 2001 Synopsys Inc 145 Chapter 7 Using VSS with Synopsys Models Simulator Configuration Guide 2 Create a working directory and run flexm_setup to make copies of the model s
243. me 1 0 filename enables 1 or disables 0 vector logging for hardware models Im_timing_measurements instance_name 1 0 filename Enables 1 or disables 0 timing measurements for hardware models Im_enable_timing_checks device_name s Enables timing checks for hardware models Im_disable_timing_checks device_name s Disables timing checks for hardware models Im_unknowns option value device_or_pin Determines how unknown values are handled by hardware models Supported options include e propagate yes no e value previous high low 202 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 10 Using Leapfrog with Synopsys Models e sequence_count 0 20 e random_seed 0 65535 e device_or_pin Im_loop_instance instance_name Makes the hardware modeler enter loop mode where it continually replays the pattern history of the specified instance Im_pam_shortage actions save sleep finish free suspend drop_faults sleep_minutes n sleep_count n save_file filename Lets you specify the action the hardware modeler is to take when it has used up most of the available pattern memory Im_pattern_history device_name s Saves the pattern memory for a private device instance Examples You can use any of these utilities by calling them from VHDL code or invoking them from the debugger prompt with an lm_proced
244. ment argument and does not look in the model v files Therefore you do not need to create modified model v files before executing the lm_monitor_vec_map command For more information about creating window elements using auto windows refer to the SmartModel Library User s Manual In Historic SmartModel Mode In Historic SmartModel mode you can access user defined windows only by using the lm_monitor_enable command This means that you must create user defined windows for SmartCircuit FPGA and CPLD models by creating modified model v files l If you do not already have a compiled configuration netlist CCN file generate one by executing smartccn on your design For details on how to use the smartccn tool refer to the SmartModel Library User s Manual Generate a windows definition file by executing ccn_report on your CCN file as shown in the following example o ccn_report ccn filename m model_name A1 windows_file Generate a modified model v file that contains the window information by executing ccn_report again as shown in the following example cen_report ccn filename m model_name v w windows file y LMC_HOME special cds verilog historic mn module_name o modified_model v Add the windows definition file to your Model Command File MCF in the form of a do command statement as follows do windows_file Make sure that your design references the modified_model v file July 31 20
245. mode for SWIFT SmartModels is typ You can use the timing mode switch at QuickSim invocation time to force the timing mode to be min typ or max Signal Levels and Drive Strengths SmartModels recognize the nine signal levels and drive strengths listed in Table 26 QuickSim II maps indeterminate strengths to unknowns for 12 state simulations The models generate strong and resistive states The high impedance unknown state XZ is used when a model places an output in the high impedance state Table 26 Signal State Values The state values shown in bold type are generated by the models All values are Signal Level Drive Strength Low 0 High 1 Unknown x Strong S 0S 1S XS Resistive R OR IR XR High Impedance Z OZ 1Z XZ recognized July 31 2001 Synopsys Inc 229 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide QuickSim II Command Line Switches When QuickSim II is invoked from the command line the following switches are the only ones recognized by SmartModels Timing Mode Switch Use the timing_mode switch to set the global timing mode to minimum maximum or typical Unit delay timing mode is not currently supported Use the following syntax when setting this switch timing_mode min max typ gt Note SmartCircuit models override settings made with the timing mode switch by means of the model comm
246. must compile these three files in the following order o vcom work slm models model_eeprom vhd vcom work slm models model_sdram vhd vcom work slm models model vhd o o b If you are not simulating SDRAM Module MemPro models vcom work slm models model vhd 6 If you compiled the model to a library SLM_MODELS in these examples add a LIBRARY statement to your testbench LIBRARY SIM MODELS 164 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 8 Using MTI VHDL with Synopsys Models This makes models in SLM_MODELS accessible from your design You can refer to the model using a standard VHDL convention such as a CONFIGURATION statement CONFIGURATION mymem_a OF mymem_tst IS FOR atest FOR ALL mymem use CONFIGURATION SLM MODELS mymem_behav END FOR END FOR END mymem_a 7 Add LIBRARY and USE statements to your testbench LIBRARY SLM_LIB USE SLM_LIB mempro_pkg all This also provides access to MemPro testbench commands For more information on using the MemPro testbench interfaces refer to the HDL Testbench Interface and C Testbench Interface chapters in the MemPro User s Manual 8 Instantiate MemPro models in your design Define ports and generics as required For information on generics used with MemPro models refer to Instantiating MemPro Models on page 32 For information on message levels and message level constants refer to Controlling MemPro Model Messages
247. mv workdir examples verilog model v workdir examples verilog model_fx_ves v LMC_HOME 1ib ibmrs lib slm_pli o testbench v P SLMC_HOME sim pli src slm_pli tab lmc swift incdir LMC_HOME sim pli srce t incdir workdir sre verilog LDFLAGS lld simv Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models Linux ves o simv workdir examples verilog model v workdir examples verilog model_fx_ves v LMC_HOME 1ib x86_linux 1ib slm_pli o testbench v P S LMC_HOME sim pli src slm_pli tab lmc swift incdir LMC_HOME sim pli sre t incdir workdir sre verilog LDFLAGS rdynamic simv NT gt ves o simv examples verilog model v workdir examples verilog model_fx_ves v incdir LMC_HOME sim pli sre t incdir workdir sre verilog testbench v lmc swift P LMC_HOME sim pli srce slm_pli tab LMC_HOME 1lib pent 1ib slm_pli_vces lib gt simv exe gt Note The entire compilation expression must appear on the same line The NT example was tested using Microsoft s Visual C compiler v5 0 VCS FlexModel Examples First we present a basic one model example and then show you how to use more than one FlexModel in the same simulation in the following sections e One FlexModel on Solaris on page 46 e Two FlexModels on Solaris on page 48 e Three FlexModels on HP UX on page 48 July 31 2001 Synopsys Inc 45 Chapter
248. n is ignored The following example shows the pin_map file that provides mapping from the pin to the bus symbols for the Logic Devices LSH32 32 bit barrel shifter Bus Package for the LSH32 PKG BUS IN I 131 130 129 128 127 126 125 124 123 122 121 120 119 118 TA ILE TLS 114 ES Te PE TLO 9 EB EY 66 LI L4 T3602 Ta OUT Y Y15 Y14 Y13 Y12 Y11 YLO Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO IN SI SI4 SIS SI2 SI1 SIO OUT SO S04 SO3 SO2 SO1 SOO July 31 2001 Synopsys Inc 243 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Figure 16 illustrates both symbol types Bus Symbol Pin Symbol Li LS RIG O nana par Eade Es ETE goth aeiiae Figure 16 Bus and Pin Symbols lt gt Note The properties on custom symbols must be the same as those on standard SmartModel symbols Using Hardware Models with QuickSim Il This section describes how to configure Release 3 5a of ModelAccess for QuickSim II ModelAccess is the software you use to interface hardware models with the simulator Before you begin review the release notes for ModelAccess for QuickSim in the Hardware Modeling Release Notes If you are using the C series releases of QuickSim II you must use R3 0 or better of the ModelAccess for QuickSim II interface software These instructions assume that you have already installed the following software e Mentor Graphi
249. n Guide Mentor Graphics Schematic ASIC1 Instance MODEL lm l Functional Description ASIC1 rss_1 ASIC1 mgc_Im attr Component Interface lm default_sym Graphical Description def tech ASIC1 smbl_1 ASIC1 mgc_symbol attr Technology Description technology ts technology tecf_1 technology Tf_tfile_do attr Figure 17 Sample Component Interface for a Hardware Model Mentor Graphics analysis tools use the following rules to determine the appropriate descriptors 1 If a label match is found the analysis tool uses the descriptor identified by the label 2 If a label match is not found the analysis tool uses the default label for the descriptor 3 If a label match is not found and there is no default label the descriptor is optional and is not used 248 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Model Registration Because multiple descriptions can exist for the same component you must register each model to specify the model s component interface and descriptors The Im_model utility is a tool for registering hardware models If a QuickSim II component does not already exist Im_model creates one along with a component interface that specifies the functional graphical and technology descriptions for the model The Im_model utility registers a hardware model in three steps using the model
250. n Guide example 188 examples 187 how it works 179 options per model 185 overwriting files 185 overwriting pin names per model 186 processing 191 running 186 syntax 186 Getting help 14 Graphical descriptions 249 H Hardware model functional descriptions with QuickSim II 249 Hardware models dynamic linking with PLI 89 108 120 elaborating and simulating design 188 functional descriptions with QuickSim II 247 installation prerequisites 178 instantiating 88 instantiating in Verilog XL 88 keyword replacement 193 linking simulators 35 linking with SFI 35 loop mode 262 modifying 255 performance monitoring 89 188 259 263 264 propagation delays 253 registering 249 250 registration 249 rules for determining descriptors 248 script for Scirocco 138 SFI 85 shell timing 258 test vector symbols 93 timing measurement 261 timing checks 253 timing checks with Cyclone 182 timing delays with Cyclone 182 understanding test vector files 93 unknown propagation 260 July 31 2001 Index variable declarations 253 verilog log file example 90 with Cyclone 183 with IKOS Voyager 36 with Leapfrog 201 with MTI Verilog 120 with MTI VHDL 165 with NC Verilog 108 with QuickSim II 247 256 with Scirocco 135 with Teradyne LASAR 36 with VEDA Vulcan 36 with ViewLogic Fusion 36 HP UX compiling C files 28 I Iflags 191 IKOS Voyager 36 with hardware models 36 Indeterminate strength mapping 261
251. n as shown in the following example whdlan design_name 11 Invoke VSS on your design as shown in the following example vhdlsim design_name Using Hardware Models with VSS To use hardware models with VSS follow this procedure 1 Make sure VSS is set up properly and all required environment variables are set as explained in Setting Environment Variables on page 141 Also make sure you have the VSS LMSI key in your license file for the interface licensing N Add the hardware model install tree to your path variable as shown in the following example set path install sms bin your_platform path W Create the model vhd wrapper file for your hardware model You can use the nawk script provided in VSS Template Generator Script for Hardware Models on page 153 to generate this file Copy the script and paste it into an executable file called hwm2vhdl nawk 4 If you generate the wrapper by hand you must provide o an entity architecture pair declaration so VSS can reference it in a later component instantiation statement o a package for defining constants declaring components and instantiating components VSS Example with TILS299 Hardware Model The following example uses the TILS299 hardware model to show how to set up hardware models for use with VSS 1 After creating the wrapper vhd file analyze the TILS299 vhd using vhdlan as shown in the following example vhldan TILS299 vhd 2
252. n minimum delays for pin values to the simulator TYPICAL Return typical delays for pin values to the simulator This is the default MAXIMUM Return maximum delays for pin values to the simulator LMSI_LOG You can use the LMSI_LOG generic to specify whether the hardware modeler logs test vector or not There are two legal values ENABLED The hardware modeler logs test vectors DISABLED The hardware modelers does not log test vectors This is the default value 152 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 7 Using VSS with Synopsys Models VSS Template Generator Script for Hardware Models Here is the nawk script that you can use to generate VHDL wrappers for the hardware models Because of the length this script you will have to cut and paste one page at a time from this PDF file to get the whole thing copied to your environment TR RR KR RK KR RK KR KK KKK RK KK KK RR RK In your design directory type nawk f hwm2vhdl nawk SHWM lt model gt NAM gt lt outfile gt vhd where SHWM is the full path to your hardware modeling directory Instantiate vhd into your design THE SCRIPT Script to generate a VSS Scirocco VHDL shell for a hardware model using the lt model gt NAM file BEGIN pin_type 0 is_it_a_vector No data_type prev_signal prev_test prev_number prev_dir ending printf library SYNOPSYS n
253. n on Technology File creation refer to Verifying the Technology File on page 253 July 31 2001 Synopsys Inc 267 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Syntax tmg_to_ts input_dir Out filename Replace Help Usage Version Required Arguments input_dir Specifies the pathname to the Shell Software timing files that you want to convert If the input_dir is not a full path it is assumed to be relative to the current directory specified by MGC_WD Optional Arguments Out filename Replace Help Usage Version 268 Specifies an alternative filename for the output file By default the output file is called technology ts All pathname specifications use the following location convention If the pathname is a relative pathname the output file is placed relative to the component directory If the pathname starts with period and slash the output file is placed in the current working directory as specified by MGC_WD if it exists If the pathname starts with a dollar sign the output file is placed in the location of the location map variable specified after the dollar sign If the pathname is an absolute pathname the output file is placed in the location of the absolute pathname Replaces the existing contents of the output directory with the new output Prints help information on each of the available options then immediately exit
254. nal symbol properties Table 25 Optional Symbol Properties Property Description COMP The COMP property provides an interface to layout or other applications Synopsys does not use this property The COMP property is assigned the default value Timing Version with the property attribute expression This causes the COMP property to track the value of the Timing Version property for Synopsys symbols PIN _NAME The PIN_NAME property is the visible text on a symbol representing a pin s name Changing this text has no effect on the model s operation PIN_NO The PIN_NO property value matches the physical pin number of the component for the default package Changing the value of this property has no effect on the model s operation REF The REF reference property provides an identifier for use in Advanced Verification messages Changing the value of this property has no effect on the model s operation Building a Design Using the Menus The Synopsys entries in the Design Architect menu system can be useful when building a design for the first time because all of the alternatives at each menu level are apparent To add SmartModels to a design using the menus follow these steps 1 Identify the desired model using the Schematic Editor menu system to traverse the menus July 31 2001 Synopsys Inc 225 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide 2 Insta
255. name instances e Combine register elements Most SmartModels contain predefined window elements that correspond to the manufacturer s specifications In addition SmartCircuit models allow users to define their own window elements so that the actual structure of the device can be examined To determine if a specific model is equipped with SmartModel Windows check the model s online datasheet How SmartModel Windows Works SmartModel Windows couples the models and the simulator so that model elements can be used almost as if they were nets in the design Normal QuickSim II commands are used with SmartModel Windows except that an instance designator must be added to a QuickSim IT command to address a model s window elements even at the top level The general format for using QuickSim II commands with SmartModel Windows is command model_instance element_name Use any of the following commands to enable window elements with the simulator ADD LISTS model_instance element_name ADD MONITORS model_instance element_name ADD TRACES model_instance element_name July 31 2001 Synopsys Inc 235 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Window elements must be activated with one of the preceding commands in order for SmartModel Windows to begin displaying data Each model s online datasheet lists its predefined window elements which are available during simulation Using windows you can read or display eleme
256. nds provide access to the SWIFT command channel You can use them to send a command to the session or to a model instance Syntax lm_command session_cmmd_string lm_command inst_path model_cmmd_string lai_command session_cmmd_string lai_command inst_path model_cmmd_string Arguments session_cmmd_string The SWIFT interface command to be sent to the session inst_path The path name to the SmartModel instance to send the command to Used only with model commands model_cmmd_string The SWIFT interface command to be sent to the model instance For more information about the SWIFT command channel refer to The SWIFT Command Channel on page 21 Examples The following example sends the ReportStatus command to the instance U1 causing it to generate a message reporting its configuration status lIm command U1 ReportStatus The following example sends the TraceTimeFile off command to the session causing it to stop issuing trace messages Note that the absence of an instance name identifies the command as session specific lm_command TraceTimeFile off 282 Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix B LMTV Command Reference lm_dump_file or lai_dump_file Use these commands to dump the memory contents of the instance inst_path into the file filename This works only for memory models If the specified file already e
257. ng _spec fMIN min_freq on storage_pin input_trans fMAX max_freq on storage_pin input_trans decrement name default_delay timing_spec tP timing_spec on eval_storage_pin input_trans to output_pin output_trans delay from input_state eval_storage_pin to output_state output_pin timing_spec tP timing_spec on eval_storage_pin input_trans to output_pin output_trans force_value output_pin pin_value hold after input_state storage_pin of input_state input_pin timing_spec tH timing_spec on input_pin input_state to storage_pin input_trans if condition statements else_if condition statements else statements end_if increment name print severity arguments pulse_width input_state storage_pin timing_spec tW timing_spec on storage_pin input_state No equivalent to maximum pulse width time 254 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Table 31 Shell Software to Technology File Conversion Continued Shell Software Statements Technology File Statements recovery after condition during condition before input_state storage_pin timing_spec else_during condition before input_state storage_pin timing_spec else before input_state storage_pin timing_spec end_during set name value setup before inpu
258. nopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models compiler acc default acc cflags values are cumulative cflags z DA1 1 DS2 0 cflags fPIC default fPIC cflags DLM_HW_DEBUG cflags DLM_HW_PIN_DEBUG linker ld default ld lflag values are cumulative lflags b default b Kh Figure 12 Sample System Dependent Setup File synopsys_Ilm_hw setup hp700 compiler The genInterface program requires access to a C compiler The ANSI C compiler acc which is required for use with Cyclone is also recommended for genInterface By default genInterface searches for the acc compiler If this is not correct for your environment update the information following the compiler keyword as follows compiler gcc cflags The DLM_HW_DEBUG and DLM_HW_PIN_DEBUG flags create a special debug version of the Cyclone interface By default these options are always commented out preceded by a There is no need to enable these options unless you are requested to do so by the Synopsys Technical Support Center linker and Iflags By default genInterface uses the ld linker with the flags specified in each platform dependent setup file If you choose to use another linker contact the Synopsys Technical Support Center For instructions refer to Getting Help on page 14 Cyclone genlinterface Proc
259. nsition on the hardware model Note that this is only supported on LM family systems Im_timing_checks on off instance_name The Im_timing_checks utility allows you to enable or disable timing checks such as setups and holds Im_loop_patterns on off instance_name The Im_loop_patterns utility causes the hardware modeler to continually replay the pattern history of a specified device instance Im_unknowns on off instance_name The Im_unknowns utility turns off unknown propagation This on_unknown feature is also in the OPT file for hardware models It modifies the system s default handling of device input and I O pins that are set to unknown by the simulator This utility does not turn on unknown propagation unless it is also turned on in the OPT file but it can override the setting in the OPT file to turn this feature off when it is set to on in the OPT file July 31 2001 Synopsys Inc 169 Chapter 8 Using MTI VHDL with Synopsys Models Simulator Configuration Guide 170 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models 9 Using Cyclone with Synopsys Models Overview This chapter explains how to use MemPro models and hardware models with Cyclone The procedures are organized into the following major sections e Setting Environment Variables on page 171 e Using SmartModels with Cyclone on page 173 e Using FlexModels with Cyclone on page 1
260. nstantiated 226 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Vendor Each subfunction menu selection has an associated vendor menu which displays a list of part manufacturers for that subfunctional group of models Part Each vendor menu selection has an associated part menu which displays a list of all SmartModels for the selected subfunction class and vendor Component Each part menu selection has an associated component menu which displays a list of all the timing and or symbol versions available for a particular model Example The following sequence of menu selections activates a Motorola MC88100 SmartModel Library gt Processor gt Microprocessor gt Motorola gt 88100 gt MC88100 20 BUS Choosing the function subfunction and vendor brings up the part menu which shows all the Motorola microprocessor models Choosing the MC88100 brings up the component menu which shows both the component and the symbol Building a Design Without the Menus Users who are familiar with the SmartModel Library may prefer to use Schematic Editor commands to build designs This approach can be faster than using the menu system The basic steps are the same 1 Identify the model you need 2 Instantiate the model s symbol on the schematic sheet 3 Use Design Architect or the Schematic Editor to edit property values as necessary Creating An Instance Use the add_inst
261. ntegration of the SWIFT interface If you are using version D 1 or higher refer to the Mentor Graphics documentation for information about using SWIFT Every time you install or update Mentor Graphics application software you must create a user tree for the SWIFT SmartModel Library Use the MGC install tool to create duplicate Mentor Graphics user trees User trees typically require between 10 20 MB of disk space For questions about creating Mentor Graphics user trees refer to the Mentor Graphics documentation Follow these steps 1 If you are using a version of QuickSim II prior to D1 for each Mentor Graphics home directory user or master tree that requires access to the SWIFT interface execute the following command UNIX LMC_HOME bin mgc_ins m MGC_HOME 1 LMC_HOME NT You will be running a mkns shell in the MGC environment for more information on the mkns shell refer to Mentor Graphics QuickSim II documentation July 31 2001 Synopsys Inc 219 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide In the Control Panel set the following drives to the appropriate system environment variables DRIVE port LMC_HOME DRIVE port MGC_HOME 2 Add LMC_HOME followed by a blank line to your location map file 3 Add SmartModel Library Menus to Design Architect Normally as part of installation the Admin tool automatically adds SmartModel menus to Design Architect for the models you
262. ntiate the model s symbol on the schematic sheet 3 Edit property values as necessary using Design Architect or the Schematic Editor The Menu System The menu system consists of several levels starting with the pull down menu that is accessed with the Libraries choice from the Design Architect menu bar At that point the following menu choices are available e Logic Modeling SmartModel Library e Logic Modeling SimuBus Products this entry is present only if you have installed SimuBus models gt Note Normally the Admin tool installs the Logic Modeling entries in the Design Architect Libraries menu automatically as part of model installation If after installing your models you do not find at least the Logic Modeling SmartModel Library entry you can perform the menu installation yourself For more information refer to Installing the QuickSim II SWIFT Interface on page 219 Following are descriptions of the relevant menu levels Top level The top level menu offers a number of choices including component libraries and the first SmartModel product menu Function The first SmartModel product menu offers a choice of functions as follows o General purpose logic menu o Logic block menu o Memories menu o Processor menu o Programmable logic menu o Support peripheral menu Subfunction Each item on the function menu has its own subfunction menu which is used to further specify the symbol for the model being i
263. nts force new values onto them and stop the simulation based on their values Tracing Instruction Execution SmartModel Windows provides the ability to trace peripheral component activity in a design Most larger peripherals and microprocessors equipped for SmartModel Windows have a 1 bit element named TRACE_ENABLE Setting TRACE_ENABLE to one 1 causes trace messages to display in the transcript window Use the following command to enable instruction tracing for a model FORCE model_instance TRACE_ENABLE 1 Some trace message examples follow I 2752 Trace Logical Master writing to PMMU Operand Address CIR I 2752 SmartModel Instance 1 2752 U103 MC68851 12 sheetl of my_design at time 819500 0 I 2752 Trace MC68851 is starting a table search using CRP I 2752 SmartModel Instance 1 2752 U103 MC68851 12 sheetl of my_design at time 822150 0 Setting Breakpoints and Word Triggering Use the ADD REAKPOINT command to stop the simulation at critical points and examine internal window elements You can set breakpoints based on the contents of specific elements inside components within the design For example the following command causes the simulation to stop at the breakpoint when the specified condition is met ADD BREAKPOINT model_instance TC 0B You can use Boolean expressions with the Add Breakpoint command to set up complex word triggers that provide a l
264. nv SHLIB PATH SSYNOPSYS_SIM hpux10 sim 1ib SHLIB_PATH Solaris setenv LD LIBRARY PATH SSYNOPSYS_SIM sparcOS5 sim 1ib LD_LIBRARY_PATH 2 Add the Scirocco executable to your search path set path SSYNOPSYS_SIM platform sim bin path where platform is hpux10 or sparcOSS 132 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 6 Using Scirocco with Synopsys Models 3 Nn ON o0 O Create a logical library named slm_lib The default physical library mapping for this is LMC_HOME sim vhpi lib If you do not wish to install the library in the LMC_HOME tree you can create it in any other location Add the following line to your synopsys_vss setup file SLM _ LIB LMC_HOME sim vhpi 1ib TIMEBASE PS Compile the MemPro VHDL files into logical library slm_lib Note that rdramd_pkg vhd is not required unless you are simulating RDRAM MemPro models o vhdlan noevent w slm lib LMC_HOME sim vhpi src slm hdlc vhd vhdlan event w slm lib LMC_HOME sim vhpi src mempro_pkg vhd vhdlan event w slm lib LMC_HOME sim vhpi src rdramd pkg vhd o o After generating a model using MemPro compile the VHDL code for the model as shown in the following example o vhdlan mymem vhd If you compiled the model to a library SLM_MODELS in these examples add a LIBRARY statement to your testbench LIBRARY SLM MODELS This makes models in SLM_MODELS accessible from your design You
265. o available on the Synopsys FTP server ftp ftp synopsys com e Licensing QuickStart 142K PDF file This booklet provides instructions for obtaining an electronic copy of your license key file and for installing and configuring SCL on UNIX and Windows NT e Licensing Installation and Administration Guide 2 08M PDF file This guide provides information about installation and configuration key concepts examples of license key files migration to SCL maintenance and troubleshooting You can find general SCL information on the Web at http www synopsys com keys July 31 2001 Synopsys Inc 15 Preface Simulator Configuration Guide Comments To report errors or make suggestions please send e mail to doc synopsys com To report an error on a specific page select the entire page including headers and footers and copy to the buffer Then paste the buffer to the body of your e mail message This will provide us with the information we need to correct the problem 16 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 1 Using Synopsys Models with Simulators 1 Using Synopsys Models with Simulators Overview There are a variety of different types of models used in the verification process This manual covers the following kinds e SmartModels including FlexModels e MemPro models e Hardware models SmartModels and FlexModels are binary behavioral models that connect to over 30 commercial sim
266. ocation maps variables Mentor Graphics 220 Logging test vectors 261 Logic simulation 228 with SmartModels 228 July 31 2001 Index Loop mode with hardware models in QuickSim II 262 M MA_CY environment variable 179 ma_cyclone software tree 178 Manual overview 11 Mapping indeterminate strength 261 pin 241 PIN_NAME 240 pins conditional 243 rules for special characters 192 unknowns 259 MCF file 230 with SmartModels 230 Measurement timing 261 MemoryFile property 223 MemPro with NC VHDL 210 MemPro models controlling message output 34 dynamic linking with PLI 81 108 118 error messages 33 fatal messages 33 generics 29 info messages 33 instantiating 32 message level constants 34 parameters 29 PLI static linking 82 83 108 119 timing messages 33 using in testbench 134 using with simulators 29 warning messages 33 with Cyclone 173 with Leapfrog 198 210 with MTI Verilog 118 with MTI VHDL 163 with NC Verilog 108 with Scirocco 132 with VCS 51 with Verilog XL 81 with VSS 148 Synopsys Inc 297 Index Simulator Configuration Guide X handling messages 33 ModelAccess for Cyclone Mentor Graphics version number 174 analysis tools 247 ModelAccess for QuickSim II design environment 247 version number 244 location map variables 220 ModelAccess for Verilog user tree management 219 version number 90 Messages modelsim ini file 157 162 163 constants level with MemPro 34 ModelSource controlling output wit
267. odel_2 new modeliInstName_2 u2 CLK NOTE This example assumes that the aguments to the methods have been defined in the VERA testbench Check that no errors have occured if model_1l showStatus FLEX_VERA FATAL model_2 showStatus FLEX_VERA_ FATAL 272 Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix A Using VERA with FlexModels Errors exist take suitable action fork Send commands to the FlexModel Instance 1 Note that the id is encapsulated in the model class and thus is not an argument to the commands model_l write addressl datal FLEX_WAIT_F status model_l write address2 data2 FLEX_WAIT_F status model_l write address3 data3 FLEX_WAIT_F status model_l write address4 data4 FLEX_WAIT_F status Read Back model_1l read_req addressl FLEX_WAIT_F status model_1l read_req address2 FLEX_WAIT_F status model_l read_req address3 FLEX_WAIT_F status model_l read_req address4 FLEX_WAIT_F status Check Results model_l read_rslt addressl tag resultl status model_l read_rslt address2 tag result2 status model_l read_rslt address3 tag result3 status model_l read_rslt address4 tag result4 status Synchronize Instance 1 amp 2 Note that the gen
268. odels typically include pin to pin delay information and can optionally include timing checks However in cycle based simulation the simulator ignores delay information and timing checks in the hardware models Cycle Based Simulation Constraints Before using a hardware model in cycle based simulation review the design coding and testbench guidelines provided in the Cyclone documentation set Although there are no inherent limitations because of hardware modeling technology when compared to a VHDL model or C language model of the same device you must follow the same usage guidelines for a circuit using hardware models as you would follow for a circuit using any other types of models when creating a cycle based simulation testbench 182 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models How Hardware Models Interface with Cyclone Cyclone provides the Slang C language interface to enable you to integrate external C and C models into the Cyclone runtime environment Hardware models are also integrated into the Cyclone environment using a special purpose implementation of the Slang interface A Slang C or C software model consists of a collection of C language entry points compiled into a shared object library plus a VHDL shell that determines which entry points are called at runtime A Slang hardware model requires a shared object library one VHDL shell per model the hardwa
269. og XL using a PLI application called LMTV that is delivered in the form of a swiftpli shared library in LMC_HOME lib platform lib If you cannot use the swiftpli refer to FlexModels PLI Static Linking with LMTV on page 81 To use the prebuilt swiftpli follow this procedure 1 Create a working directory and run flexm_setup to make copies of the model s interface and example files there as shown in the following example SLMC_HOME bin flexm_setup dir workdir model_fx You must run flexm_setup every time you update your FlexModel installation with anew model version Table 14 lists the files that flexm_setup copies to your working directory Table 14 FlexModel Verilog XL Files File Name Description Location model_pkg inc Verilog task definitions for FlexModel workdir src verilog interface commands This file also references the flexmodel_pkg inc and model_user_pkg inc files model_user_pkg inc Clock frequency setup and user customizations workdir src verilog model_fx_vxl v A SWIFT wrapper that you can use to instantiate workdir examples verilog the model model v A bus level wrapper around the SWIFT model workdir examples verilog This allows you to use vectored ports for the model in your testbench model_tst v A testbench that instantiates the model and shows workdir examples verilog how to use basic model commands 2 There is no need to build a Verilog executable Yo
270. ogic DI in std_logic D2 in std_logic D3 in std_logic D4 in std_logic D5 in std_logic D6 in std_logic D7 in std_logic D8 in std_logic OC in std_logic Ql out std_logic Q2 out std logic Q3 out std_logic Q4 out std_logic Q5 out std_logic Q6 out std_logic Q7 out std_logic Q8 out std_logic end component end comp Synopsys Inc Simulator Configuration Guide July 31 2001 Simulator Configuration Guide Chapter 8 Using MTI VHDL with Synopsys Models 3 Compile the model vhd into a library called slm_lib as follows o vlib slm lib vmap slm lib slm lib vcom work slm lib model vhd o o 4 Instantiate the SmartModel component in your testbench by specifying the required SWIFT parameters in the generic map Here is an example instantiation for the TTL373 model with the library and use statements the instance U1 and the Timing Version and DelayRange options specified in the generic map for the TTL373 SmartModel Library component Use the SmartModel Library slm_lib just as you would use any other VHDL resource library Here is an example library IEEE use IEEE STD_LOGIC_1164 ALL library SLM_LIB use SLM_LIB COMPONENTS ALL entity TestBench is end TestBench architecture ArchTestBench of TestBench is signal A B C STD_LOGIC Ul TTL373 generic map TimingVersion gt SN74LS373 DelayRange gt Typ po
271. ogic analyzer during simulation For example the following command causes the simulation to stop at the breakpoint when both of the two specified conditions are met ADD BREAKPOINT model_instance SCC 0 amp amp model_instance TC B Trigger terms do not have to refer to the same instance or model In addition net values and window element contents can be combined to make trigger terms Single Step Simulation The ADD BREAKPOINT command defaults to stopping the simulator when a signal or expression in a window element changes state As a result you can use the ADD BREAKPOINT command to single step through a simulation 236 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Renaming Instances Use the ADD SYNONYM command to rename instances with easier to remember substitute names For example to rename a model for an MC68851 with an instance name of I 289 to an easier to remember name such as PMMU use the following command ADD SYNONYM PMMU 1 289 Once you add a synonym you can use it in place of the original instance name in commands For example the following command lists the MC68851 translation control register ADD LISTS HEX PMMU TC Combining Register Elements You can use the ADD BUS command to combine meaningful 1 bit elements of a PLD into a single bus that can be viewed or changed after the PLD has been programmed This saves effort compar
272. on page 33 9 Compile your design as shown in the following example weom design_name 10 Invoke the simulator on your design as shown in the following example o vsim design name Using Hardware Models with MTI VHDL To use hardware models with MTI VHDL follow this procedure 1 Make sure MTI VHDL is set up properly and all required environment variables are set as explained in Setting Environment Variables on page 155 2 Add the hardware model install tree to your path variable as shown in the following example set path install sms bin your_platform path 3 Modify the modelsim ini or project_name mpf file to include the hardware modeling information Locate the line 1lmc July 31 2001 Synopsys Inc 165 Chapter 8 Using MTI VHDL with Synopsys Models Simulator Configuration Guide Remove the semicolons from the libhm line and the libsfi line you will be changing for your platform Provide the correct path for the SFI For example ModelSim s interface to Logic Modeling s hardware modeler SFI software libhm SMODEL_TECH 1libhm s1 amine Logic Modeling s hardware modeler SFI software HP 9000 Series 700 libsfi hardware_model_install_path lib plat form libsfi ext e Ne Ne Ne Ne Ne Ne libsfi lt sfi_dir gt lib pent lm sfi dll Logic Modeling s hardware modeler SFI software IBM RISC System 6000 libsfi lt sfi_dir gt lib rs6000 libsfi a Logic Mod
273. onment variable 39 61 103 112 125 142 156 172 196 206 218 signal instance command 231 256 261 262 264 signal renaming rules 192 Signal strength with SmartModels 77 Simulation session ending 264 Simulations fault 23 reconfiguring models for 232 single step 236 Simulator Function Interface SFD 85 version number 90 Simulator integration Cyclone 173 Leapfrog 198 210 ModelSim 160 ModelSim VHDL 163 MTI VHDL 160 V System 5 0 160 simv command 278 Slang hardware model 183 Slang interface 183 sm_entity command 157 160 SmartCirctuit models Models SmartCircuit 207 SmartCircuit models with SWIFT Cxmmand Channel 21 SmartModel Library documentation 11 fault simulation 23 message formats 233 SmartModel Windows in SWIFT SmartModel mode 72 in Verilog XL historic mode 71 SmartModel windows elements 238 July 31 2001 Simulator Configuration Guide how they work 235 LMTV commands 70 tracing instruction execution 236 with QuickSim II 235 with Verilog XL 70 SmartModels adding to schematic 221 attributes required 19 changing program flow 238 changing program flows 238 changing timescale 76 creating instances in QuickSim 227 customizing timing 76 drive strengths 229 dynamic linking with PLI 61 103 113 editing properties 233 evaluation 258 fault simulation 23 functional descriptions in Quickim II 247 graphical descriptions with QuickSim H ij instantiating 20 library menus to Design Architect 220 LMTV SWI
274. onverts existing Shell Software names in the generated VHDL file KSO is converted to NE_CS BMO BYTE is converted to NE_BMO_SL_BYTE DT R is converted to DT_SL_NE_R TOUT2 IRQ3 is converted to NE_TOUT2_SL_NE_IRQ3 TO94_ RCLK_ BUSY RDY is converted to 1094_NE_RCLK_NE_BUSY_SL_RDY Keyword Replacement Certain VHDL keywords cannot be used as signal names for example IN OUT PROCESS The genInterface program scans the list of signal names replaces disallowed keyword is found that name is replaced by S_keyword If another signal already exists by this name a random string is appended to the end of the present signal name For example the Shell Software notation IN 6 1 would be converted as follows S_IN IN std_logic_vector 6 downto 1 July 31 2001 Synopsys Inc 193 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide 194 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 10 Using Leapfrog with Synopsys Models 10 Using Leapfrog with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels MemPro models and hardware models with Leapfrog The procedures are organized into the following major sections e Setting Environment Variables on page 195 e Using SmartModels with Leapfrog on page 197 e Using FlexModels with Leapfrog on page 198 e Using MemPro Models with Leapfrog on page 198 e
275. op up menu or by using the QuickSim H CHANGE TEXT VALUE command These properties are hidden or visible depending on the visibility attributes selected by your library manager Figure 14 illustrates the positions of the visible properties on a symbol supplied by Synopsys Li REF Timing TC ROP AS Version tie mery MemoryFile Figure 14 Visible Symbol Properties Symbol Properties used by SWIFT Models Table 23 lists symbol properties that are used by SWIFT interface models Table 23 Symbol Properties used by SWIFT Models Property Description TimingVersion Timing version to use with a model Any value assigned to the Timing Version property must be a valid timing version for that model MemoryFile Name and path of a memory image file July 31 2001 Synopsys Inc 223 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide Table 23 Symbol Properties used by SWIFT Models Continued Property Description PCLFile Name and path of a compiled PCL file JEDECFile Name and path of a JEDEC fuse map file SCFFile Name and path of an MCF file for SmartCircuit models gt Note FlexModels use a slightly different set of symbol properties For information on the required configuration properties for FlexModels refer to Using FlexModels with SWIFT Simulators on page 24 You can use either an absolute or relative path nam
276. or Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models Arguments instance_path Specifies the pathname of the model instance for which timing measurement is to be enabled or disabled on_off Indicates whether test vector logging is to be enabled or disabled Allowed values are 1 to enable logging or 0 the default to disable logging filename Specifies the file name to be used for the test vector log Description The lm_timing_measurements command enables timing measurement for a specified model instance By default timing measurement is not performed Instead the hardware modeler uses the delay values provided in the DLY file in the Shell Software When timing measurement is enabled the hardware modeler returns to the simulator and logs to the specified file the actual delays measured from the device Example The following example enables timing measurements for the U1 model instance and saves the timing measurement log in the U1 log file Slm_timing_measurements Tbench U1 1 U1 1lo0g lm_unknowns Command Reference The lm_unknowns command lets you override the hardware modeler s default handling of unknown values for specified instances or pins or for all hardware model instances in the simulation Syntax lm_unknowns option value option value device_or_pin Arguments You can use the following values for option value propag
277. or Configuration Guide Chapter 4 Using NC Verilog with Synopsys Models HP UX setenv SHLIB PATH LMC_HOME 1ib hp700 1ib SHLIB_PATH NT Make sure that 7LMC_HOME lib pcnt lib is in the Path user variable Using SmartModels with NC Verilog SmartModels work with NC Verilog using a PLI application called LMTV that is delivered in the form of a swiftpli shared library in LMC_HOME lib platform lib If you cannot use the swiftpli refer to Static Linking with LMTV on page 104 To use the prebuilt swiftpli follow this procedure 1 Instantiate SmartModels in your design defining the ports and defparams as required For details on required SmartModel SWIFT parameters and model instantiation examples refer to Using SmartModels with SWIFT Simulators on page 18 N There is no need to build a Verilog executable You can use the one from CDS_INST_DIR tools bin by adding it to your path statement Oo To use the swiftpli shared library invoke the NC Verilog simulator to compile and simulate your design as shown in the following examples UNIX neverilog testbench model v loadplil swiftpli swift_boot incdir SLMC_HOME sim pli sre NT gt neverilog testbench model v loadplil swiftpli swift_boot incdir LMC_HOME sim pli sre IS Note If you are using ncelab and ncsim use the loadplil switch instead of the loadplil switch For information on LMTV commands that you can use with SmartModels on N
278. or11 VEC This file contains the vectors played to and sensed from the selected instance during the simulation run by the dofile The SIGnal INSTance nologvectors command turns off the modeling system test vector logging capability After logging vectors you can replay them directly to the device and note any discrepancies using the Im Play Vectors utility This utility is particularly useful for ASIC verification For more information about ASIC verification and test vector VEC file format refer to the LM family Modeler Manual or the ModelSource User s Manual Timing Measurement The SIGnal INSTance tm p filename command turns on the modeling system timing measurement for the selected instance The system then returns to the simulator the actual measured delay values for that instance If you provide an optional filename the system also saves the measured delays to a timing measurement TIM file By convention device_name TIM is the filename used for the timing measurement output The SIGnal INSTance notm command turns off timing measurement for the selected instance which is the default behavior If timing measurement is disabled the Technology File delays or the Shell Software delays if SIGnal INSTance Ist is specified are returned to the simulator July 31 2001 Synopsys Inc 261 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide For example consider the following commands sig inst tm
279. ow element in a specified model instance The window element can be part of an array Can be used only in SWIFT SmartModel mode lm_status lai_status Displays the names and values of internal windows for a specified model instance Can be used in both Historic and SWIFT SmartModel modes Creating User Defined Window Elements You can create user defined window elements only for SmartCircuit FPGA or CPLD models The way you create these window elements depends on whether you will access the window elements using lm_monitor_enable which can be used in either the Historic or the SWIFT SmartModel mode or 1m_monitor_vec_map which can be used only in SWIFT SmartModel mode 70 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models Both lm_monitor_enable and lm_monitor_vec_map need to be given the names of the model s window elements However these two commands receive the window element names differently as follows The lm_monitor_enable command expects to find the window element names in the model v files Therefore before invoking lm_monitor_enable you must use ccn_report to modify the model v files so that they contain the window element names For details on how to use the ccn_report tool refer to the SmartModel Library User s Manual The lm_monitor_vec_map on the other hand expects to be passed the window element names through its own window_ele
280. p SASIC2 timing timingl1 TIM dofile SASIC2 dofiles runl1l1 do sig inst notm In this example the modeling system creates a timing measurement file called timing11 TIM This file contains the delays of the selected instance measured during the simulation run created by the dofile The SIGnal INSTance notm command turns off the modeling system timing measurement capability This Signal Instance command performs a similar function to that of the Im Measure Timing utility Timing measurement is particularly useful for ASIC verification For more information about ASIC verification and timing measurement TIM file format refer to the LM family Modeler Manual or the ModelSource User s Manual gt Note The timing measurement TIM file can be converted to a Shell Software delays DLY file by using the Im Create Timing File utility For more information refer to the LM family Modeler Manual or the ModelSource User s Manual The delays file can then be converted into a technology file if desired by using the Im_model utility with the Step Timing option Loop Mode The SIGnal INSTance loop command turns on the modeling system pattern looping capability loop mode for the currently selected instance In loop mode the modeling system continually replays the complete pattern history of the selected instance to the device The SIGnal INSTance noloop command turns off pattern looping Pattern looping is a model development featur
281. page 95 33 66 lm_timing_information instance_path timing_option The lm_timing_information command lets you override the hardware modeler s default handling of timing information for a specified model instance For a detailed syntax description refer to lm_timing_information Command Reference on page 96 lm_timing_measurements instance_path on_off filename The lm_timing_measurements command enables timing measurements for a specified model instance It is not supported for ModelSource 3200 and 3400 For a detailed syntax description refer to lm_timing_measurements Command Reference on page 96 lm_unknowns option value option value device_or_pin The lm_unknowns command lets you override the hardware modeler s default handling of unknown values for specified instances or pins or for all hardware model instances in the simulation For a detailed syntax description refer to 1m_unknowns Command Reference on page 97 July 31 2001 Synopsys Inc 109 Chapter 4 Using NC Verilog with Synopsys Models Simulator Configuration Guide 110 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 5 Using MTI Verilog with Synopsys Models s Using MTI Verilog with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels MemPro models and hardware models with MTI Verilog ModelSim VLOG The proc
282. path bin vcom work slm lib workdir examples vhdl model_fx_mti_nt vhd NT mti_path bin vcom work slm lib workdir examples vhdl model vhd 6 Add LIBRARY and USE statements to your testbench library slm lib use slm lib flexmodel_pkg all use slm lib model_pkg all use slm lib model_user_pkg all For example you would use the following statement for the tms320c6201_fx model use slm lib tms320c6201_pkg all use slm lib tms320c6201_user_pkg all Instantiate FlexModels in your design defining the ports and generics as required refer to the example testbench supplied with the model You use the supplied bus level wrapper model vhd in the top level of your design to instantiate the supplied bit blasted wrapper model_fx_mti vhd for UNIX or model_fx_mti_nt vhd for NT Example using bus level wrapper model vhd without timing U1 model generic map FlexModelID gt TMS INST1 port map model ports Example using bus level wrapper model vhd with timing U1 model generic map FlexModelID gt TMS INST1 FlexTimingMode gt FLEX TIMING MODE ON TimingVersion gt timingversion DelayRange gt range port map model ports 8 Compile the testbench as shown in the following example o vecom testbench Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 8 Using MTI VHDL with Synopsys Models 9 Invoke the MTI VHDL simulator as shown in the following example
283. pkg inc lt gt Note Be sure to add model_pkg inc within the module from which you will be issuing FlexModel commands Because the model_pkg inc file includes references to flexmodel_pkg inc and model_user_pkg inc you don t need to add flexmodel_pkg inc or model_user_pkg inc to your testbench 4 Instantiate FlexModels in your design defining the ports and defparams as required refer to the example testbench supplied with the model You use the supplied bus level wrapper model v in the top level of your design to instantiate the supplied bit blasted wrapper model_fx_vxl v Example using bus level wrapper model v without timing model U1 model ports defparam U1 FlexModelId TMS _INST1 Example using bus level wrapper model v with timing model U1 model ports defparam U1 FlexTimingMode FLEX TIMING MODE ON Ul TimingVersion timingversion U1 DelayRange range U1 FlexModelId TMS_INST1 July 31 2001 Synopsys Inc 105 Chapter 4 Using NC Verilog with Synopsys Models Simulator Configuration Guide 5 There is no need to build a Verilog executable You can use the one from CDS_INST_DIR tools bin by adding it to your path statement 6 Invoke the NC Verilog simulator to compile and simulate your design as shown in the following examples UNIX o neverilog testbench loadplil swiftpli swift_boot workdir examples verilog model v workdir examples veri
284. pper files You must select VCS as your Verilog simulator during the SmartModel installation in order to have vcs_sg available It will be installed as LMC_HOME bin vcs_sg The vcs_sg tool also extends the usefulness of the model wrapper files generated by VCS in two ways o it adds statements that allow the DelayRange to be controlled by the VCS command line define parameters or a defparam in your testbench o it adds a check for the VCS command line define SwiftChecksOff parameter that turns constraints off July 31 2001 Synopsys Inc 39 Chapter 2 Using VCS with Synopsys Models Simulator Configuration Guide You can change the default name of the generated wrapper files lt model gt swift v as well as the location that the generated wrappers are written to Invoke LMC_HOME bin vcs_sg h to return the usage message for the vcs_sg tool HP UX B 10 20 u mikehu 3 gt SLMC_HOME bin vcs_sg h Copyright C 2001 Logic Modeling Synopsys Inc ALL RIGHTS RESERVED vcs_sg pl Revision main 5 Date 2001 03 02 13 42 03 HHT HEH EEE EE EEE ETE HEHEHE EERE HERE TEPER TEE EEAEEEE REET EEEH Generate v files for VCS for Smartmodels Command line options h this message 1l lt path gt to specify location of created files default is current directory m lt model_name gt to specify which model to process default is entire library if no m switch multiple m lt model_name gt switches may be used u conve
285. pull down menu to get the wave window In the wave window use File Load Format wave do to get the waveforms After the waveform viewer comes up and the vsim prompt appears enter run 10000 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 8 Using MTI VHDL with Synopsys Models 7 You can also use some of the hardware model utilities listed below but the commands must be entered at the simulator command prompt because they are not VHDL statements For the TILS299 example you can also put these commands into the do file Here is an example wave do file lm_ vectors on tb_tils299 U0 TEST VEC add wave logic clk add wave logic clr add wave logic s add wave logic s0 add wave logic gl add wave logic g2 add wave logic sr add wave logic s add wave logic qa add wave logic gh add wave literal t hm_entity Command Reference The hm_entity script creates vhd files for hardware models Syntax hm_entity options shell_software_filename Arguments xe Do not generate entity declaration xa Do not generate architecture body C Generate component declaration 93 Use extended identifiers where needed July 31 2001 Synopsys Inc 167 Chapter 8 Using MTI VHDL with Synopsys Models Example For example the following hm_entity invocation hm entity TILS299 MDL gt TILS299 vhd generates a vhd file that looks like the following 1
286. r and Step Timing By default lm_model performs all the registration steps Deletes the existing component directory and then recreates it If you try to overwrite an existing symbol without using this switch Im_model fails and generates an error message Prints additional messages while Im_model is executing Prints help information on each of the available options then immediately exits Expands the command line and displays each argument and switch After printing the usage message Im_model immediately exits Prints the single line version message then immediately exits Registers the model using the pre V8 3 method for compatibility purposes Does not affect lm_model execution The system accepts this argument for compatibility purposes The Im_model utility provides several ways of specifying input and output files and directories The following examples list a given input directory model file and desired output component directory and then show the Im_model command line you would use to get this result Example 1 Input directory user models 741s74 MGC_WD is set to user models Model file 74LS74 MDL same as the component name 266 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Component output directory user models 74LS74 default output path and directory Command 1m_model 741s74 Example 2 Input directory user models 7
287. r file This is put in a package named COMPONENTS when compiled model vhd A bus level wrapper around the SWIFT model workdir examples vhdl This allows you to use vectored ports for the model in your testbench This file assumes that the COMPONENTS package has been installed in the logical library slm_lib 128 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 6 Using Scirocco with Synopsys Models Table 18 FlexModel Scirocco VHDL Files Continued File Name Description Location model_tst vhd A testbench that instantiates the model and workdir examples vhdl shows how to use basic model commands 3 Update the clock frequency supplied in the model_user_pkg vhd file in your working directory to correspond to the desired clock period for the model After you run flexm_setup this file is located in workdir sre vhd1 model_user_pkg vhd where workdir is your working directory 4 Add the following line to your synopsys_vss setup file SIM LIB SLM LIB PATH TIMEBASE PS 5 Compile the FlexModel VHDL files into logical library slm_lib as follows o vhdlan noevent w slm lib LMC_HOME sim vhpi src slm hdlc vhd vhdlan event w slm lib LMC_HOME sim vhpi src flexmodel_pkg vhd vhdlan event w slm lib workdir src vhdl model_user_pkg vhd vhdlan event w slm lib workdir src vhdl model_pkg vhd vhdlan event w slm lib workdir src vhdl model_fx_comp vhd
288. r for all hardware model instances in the simulation For a detailed syntax description refer to lm_unknowns Command Reference on page 97 122 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 6 Using Scirocco with Synopsys Models 6 Using Scirocco with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels MemPro models and hardware models with Scirocco The procedures are organized into the following major sections e Setting Environment Variables on page 124 e Using SmartModels with Scirocco on page 125 e Using FlexModels with Scirocco on page 128 e Using MemPro Models with Scirocco on page 132 e Using Hardware Models with Scirocco on page 135 X Hint This chapter includes a script that you can use to run any FlexModel examples testbench with minimal setup required You can cut and paste the script right out of this PDF file Refer to Script for Running FlexModel Examples in Scirocco on page 130 for details July 31 2001 Synopsys Inc 123 Chapter 6 Using Scirocco with Synopsys Models Simulator Configuration Guide Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel F
289. re IMC_HOME sim vera src flexmodel_pkg vr If you are using VERA version 4 0 or earlier you must compile the flexmodel_pkg vr object with a VERA_4 preprocessor flag Your compile would therefore look like this vera cmp flexmodel_pkg vr I LMC_HOME sim vera srce DVERA 4 o vera cmp ISLMC_HOME sim vera src Iworkdir sre vera workdir sre vera model_pkg vr lt gt Note If you are building the VERA dynamic library on Solaris do not use the B symbolic switch Using this switch results in unresolved symbol warnings 2 Compile your VERA testbench o vera cmp I LMC_HOME sim vera sre Iworkdir sre vera testbench vr This step produces two files testbench vro and testbench vshell 3 Build vera_local dl o Compile LMC_HOME sim vera src vera_user c HP UX bin c89 c z ISVERA_HOME 1lib SLMC_HOME sim vera src vera_user c Solaris cc K pic c ISVERA_HOME 1lib SLMC_HOME sim vera src vera_user c o Link in LMC_HOME lib platform lib vera_slm_pli o and vera_user o during the link stage of building the vera_local dl HP UX o ld b e syssci_prod_entry e errno o vera_local dl vera_user o LMC_HOME lib hp700 lib vera_slm pli o VERA_HOME lib vlog libvlog_br a VERA_HOME lib libVERA a lm lc 276 Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix A Using VERA with FlexModels Solaris ld G z text o vera_local dl vera_user o
290. re when genInterface creates VHDL shells for each model it converts illegal VHDL signal names to legal equivalents This process is explained in Rules for Signal Renaming on page 192 If you prefer to use your own VHDL signal names you can use the pin_name_ovr statement to specify the mapping from the original name to the new name The syntax for this statement is for model_name use pin_name_ovr shell_sw_namel VHDLnamel pin_name_ovr shell_sw_name2 VHDLname2 end For example the pin name ALE is allowed in the Shell Software but not in VHDL By default genInterface removes the leading hyphen and replaces it with the string NE_ creating the new pin name NE_ALE If you prefer the alternate legal name NALE add the following lines to your setup file for I80960M use pin_name_ovr ALE NALE end geninterface Command Reference After successfully running verifySetup you can run genInterface specifying the hardware models you want to include in Cyclone simulation Syntax genInterface m modeler_name mdlfilel mdlfile2 f model_list a Arguments m modeler_name This optional switch specifies the hardware modeling system for genInterface to use The modeler must be installed on the network and be booted and running If a modeler_ name is not specified genInterface searches the modelers lis file for the name of an available modeler The modeler does not need to have the hardware mode
291. re a design using the Concept design flow refer to Figure 3 First diagram the design in Concept using a custom symbol library Next execute vloglink to generate the vloglink v file Finally for the SWIFT SmartModel mode only execute the mod_param utility provided by Synopsys to convert model instance parameter names to SWIFT compliant names in the vloglink v file 68 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models Create Design Diagram Using Concept Y Execute vloglink design v file SWIFT E t SmartModel xecute Mode mod_param Y SWIFT compliant vloglink v file Figure 3 Concept Design Flow Concept Procedure To create a design file graphically using Concept follow these steps 1 Merge the file into your master local file 2 Invoke Concept instantiate the symbols and write the schematic 3 Execute vloglink 4 If you are using the SWIFT SmartModel mode use one of these methods to prepare vloglink v for simulation o Run verilog with the u switch Or o Run mod_param on the vloglink v file This converts parameter names to SWIFT compliant form For more information about the mod_param utility run mod_param with the h to display the usage message July 31 2001 Synopsys Inc 69 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide Using SmartModel Windows with Verilog
292. re model s Shell Software and the model itself installed in the hardware modeler A conceptual diagram of a Slang hardware model is shown in Figure 10 E Files created by genInterface EE Hardware Model Figure 10 Slang Hardware Model Conceptual Diagram gt Note The genInterface program creates the C library and VHDL shell files needed by Cyclone to evaluate hardware models July 31 2001 Synopsys Inc 183 Chapter 9 Using Cyclone with Synopsys Models Simulator Configuration Guide Editing the Setup File The genInterface program has its own setup file synopsys_Im_hw setup that you use to specify various options to be applied to the entire genInterface session or to particular models within the session including e Deleting intermediate files e Overwriting existing files e Overwriting pin names per model Default values are provided for all required items so you only need to edit this file if you want to alter the default values If you decide to edit the file copy it from MA_CY setup synopsys_Im_hw setup to your own local working directory The copy must be renamed to synopsys_Im_hw setup Now you can edit and customize the local synopsys_Im_hw setup file appropriately for your session If you want to change the global settings on a Solaris system you must edit the following file MA_CY setup synopsys_Im_hw setup solaris The other file extension is hp700 To change the file copy line
293. refer to the SmartModel Library User s Manual 74 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models The following example code monitors the memory device If there is a memory write the code checks to see if the write was to any location in the address range between h100 and h200 not allowed and if so issues an error message If the Mem_addr window element which contains the most recently accessed address contains unknown values no test is performed and another error message is issued ram model U1 Declare registers for the address rw and memory data window elements reg 11 0 ADDR reg 1 0 RW reg 7 0 DATA initial Map the ADDR and RW registers to the MEM_addr and MEM_rw windows begin Slm_monitor_vec_map ADDR Ul MEM _ addr Slm_monitor_vec_map RW Ul MEM _ rw end Whenever there is a memory transaction check the address and the direction for an illegal write and the address for unknown values always RW begin if ADDR gt h100 amp amp ADDR lt h200 amp amp RW 1 O amp amp ADDR hx begin There was an illegal write Temporarily map DATA register to address pointed to by ADDR and enable MEM array window element to get value of data Slm_monitor_vec_map DATA U1 MEM ADDR Sdisplay Illegal write of value Sh at address h DATA ADDR Turn off enabling of memory array Slm_monitor_vec
294. registers a hardware model by invoking hardware model registration and conversion programs Syntax Im_model input_dir output_path Dir name Ifc interface LAbel label Mdl mdl_filename Step RegisterlSymbollTiming Update Replace VERBose Help Usage VERSion Old LM 264 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models Required Argument input_dir Specifies the pathname to the directory containing the files to be registered This argument is required and must appear first All pathname specifications use the following location convention If the pathname is relative the input_dir is assumed to be in the working directory as specified by MGC_WD If MGC_WD is not set the input_dir is assumed to be in the current working directory If the pathname starts with a dollar sign the input_dir is assumed to be in the location of the location map variable specified after the dollar sign If the pathname is an absolute pathname the input_dir is assumed to be in the location of the absolute pathname Optional Arguments output_path Dir name Ifc interface LAbel label Mdl mdl_filename July 31 2001 Specifies the pathname to the directory that contains the component information If an output_path is not specified then it defaults to the parent directory of the input_dir Specifies just the new name of the output component
295. rns off loop mode default Information dump Reports all available information about the selected instance of a hardware modeled device Ime Reports the type of timing shell Shell Software p shelllallshell or technology file for the selected instance vector Reports the runtime vector count of the selected instance Model Evaluation By default all component instances are evaluated in QuickSim II If you want to disable evaluation of models for selected instances you can use the SIGnal INSTance disable command This command isolates sections of the design and shortens the simulation time for debugging purposes To turn model evaluation on again for selected instances you can use SIGnal INSTance enable Timing Shell Selection The SIGnal INSTance Ist command lets you use the hardware model s Shell Software timing files instead of the default technology file during evaluation of the selected instances You can use the SIGnal INSTance nolst command to switch back to the technology file for selected instances The optional p all argument enables you to choose the type of timing shell for all hardware models in the design if you have at least one instance selected For example you could use the following command before simulating sig inst lst p all 258 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 12 Using QuickSim II with Synopsys Models QuickSim II ignores the technology files
296. rocco pl script Here is what the script looks like for the mpc860_fx model bin csh f source d edavs snps 2000 02PROD admin setup environ csh hdlan noevent w slm lib d lmgqa2 dalew flex 1lmc_home sim vhpi src slm_hdlc vhd hdlan event w slm lib d lmgqa2 dalew flex lmc_home sim vss src flexmodel_pkg vhd hdlan event w slm lib lmgqa2 dalew flex lmc_home models mpc860_fx mpc860_fx02012 src vhdl mpc860_user_pkg v ao N t w slm lib lew flex lmc_home models mpc860_fx mpc860_fx02012 src vhdl mpc860_pkg vhd t w slm lib lew flex lmc_home models mpc860_fx mpc860_fx02012 examples vhdl mpc860_fx_vs hdlan even lmgqa2 da hdlan even lmgqa2 da vhd hdlan event w slm_lib lmgqa2 dalew flex lmc_home models mpc860_fx mpc860_fx02012 examples vhdl mpc860_fx_co vhd hdlan event w slm_lib d lmgqa2 dalew flex lmc_home models mpc860_fx mpc860_fx02012 examples vhdl mpc860 vhd vhdlan event d lmgqa2 dalew flex lmc_home models mpc860_fx mpc860_fx02012 examples vhdl mpc860_tst v hd virsim simtype Scirocco simargs vhpi slm_vhpi foreignINITelab cpipe cfgtest Q Mi aog ALs a T a S Q k Q N N lt Using MemPro Models with Scirocco You must have MemPro version 2000 04 or higher to use MemPro models with Scirocco To use Scirocco with MemPro models follow this procedure 1 Add the Scirocco library path to your library path environment variable HP UX sete
297. rt file name to uppercase t truncate name to lt model gt v a add mode generate only models without v file in specified destination o lt file_name gt create log file file_name b bit only i f no bus i f if supported v verbose mode to see all messages d set debug mode HAR AR AR AR aE aE aE EEE EE EE EE EE EE EEE EEE EE EE AEE AE EE EEE 2 Instantiate SmartModels in your design defining the ports and defparams as required For details on the required SWIFT parameters and SmartModel instantiation examples refer to SmartModel SWIFT Parameters on page 18 3 Invoke the VCS simulator as shown in the following examples Solaris VCS_HOME bin vcs lmc swift model swift v model_tb v 1 ves_sim log Mupdate RI HP UX VCS_HOME bin vces lmc swift model swift v model_tb v 1 vces_sim log Mupdate RI LDFLAGS a shared lm lc a archive 40 Synopsys Inc July 31 2001 Simulator Configuration Guide AIX Chapter 2 Using VCS with Synopsys Models VCS_HOME bin vcs lmc swift model swift v model_tb v 1 ves_sim log Mupdate RI LDFLAGS lld Linux VCS_HOME bin vcs lmc swift model swift v model_tb v 1 ves_sim log Mupdate RI LDFLAGS rdynamic where model swift v is the template you created in the previous step and model_tb v is the testbench where the model is instantiated Each mo
298. rt map A gt D1 B gt D2 C gt Q1 Pl process begin For more information on SmartModel configuration parameters refer to Using SmartModels with SWIFT Simulators on page 18 5 Compile the top level testbench to a work library WYWORK as shown in the following example wlib MYWORK vcom work MYWORK top vhd o 6 Invoke the simulator by running vsim as shown in the following example vsim lib MYWORK CFGTEST For information on how to use MTI VHDL refer to the ModelSim User s Manual July 31 2001 Synopsys Inc 159 Chapter 8 Using MTI VHDL with Synopsys Models Simulator Configuration Guide sm_entity Command Reference The command reference for sm_entity is as follows Syntax sm_entity options SmartModels Arguments read XC Xa C all y Read SmartModel names from standard input Do not generate entity declarations Do not generate architecture bodies Generate component declarations Select all models in the SmartModel Library Display progress messages By default sm_entity generates an entity and architecture Optionally you can include the component declaration c exclude the entity xe or exclude the architecture xa Using FlexModels with MTI VHDL To use FlexModels with MTI VHDL follow this procedure This procedure covers users on UNIX and NT If you are on NT substitute the appropriate NT syntax for any UNIX command line examples percent si
299. rtModel Library you can simulate it in either mode e Historic SmartModel mode in this case you do not have to modify the design e SWIFT SmartModel mode in this case you must modify the design In both cases you must make some modifications to the simulation environment as described in the following sections LMTV SWIFT and Verilog XL Specific SmartModel Libraries Table 13 lists the differences between the LMTV SWIFT and Verilog XL specific SmartModel Libraries Table 13 LMTV SWIFT and Verilog XL specific Libraries LMTV SWIFT SmartModel Library Verilog XL specific SmartModel Library Uses simplified search algorithm for user Uses complex search algorithm for user defined defined timing files timing files 76 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 3 Using Verilog XL with Synopsys Models Table 13 LMTV SWIFT and Verilog XL specific Libraries Continued LMTV SWIFT SmartModel Library Verilog XL specific SmartModel Library In SWIFT SmartModel mode reports true Always maps resistive strength of outputs to resistive strength of outputs a switch strong optionally maps all to strong In Historic SmartModel mode mimics Verilog XL specific SmartModel Library Supports the Verilog reset and restart Does not support the Verilog reset and restart commands commands Always uses only LMC_HOME to find Uses laiobj LAI_OBJ lai_lib LAI_LIB models
300. ry must be in your PATH For details on the complete syntax of the Imvsg command refer to Imvsg Command Reference on page 99 4 Use the Verilog module definitions to instantiate the hardware models in your testbench The following example shows an example instantiation for the TILS299 hardware model Notice the two defparam statements the definitions of the Timing Version TILS299A MDL and DelayRange MIN parameters in the instantiation override the default definitions in the model v file TILS299 MDL and MAX respectively In this example TILS299A MDL represents a custom timing version that the designer wants to use instead of the default timing version TILS299 MDL Instantiate UUT ModelSource TILS299 hardware model U1 defparam UL TimingVersion TILS299A MDL defparam U1 DelayRange MIN TILS299 U1 CLK clkw CLR clrw A iolw 0 B iolw 1 me iolw 2 D iolw 3 EB iolw 4 EF iolw 5 G iolw 6 H iolw 7 Gl glw G2 g2w OA qalw QH qghiw SO sOw July 31 2001 Synopsys Inc 121 Chapter 5 Using MTI Verilog with Synopsys Models Simulator Configuration Guide S1 siw SL slw SR srw 5 Invoke the MTI Verilog simulator as shown in the following example which illustrates the use of the pli switch to specify the PLI library o vsim pli mav_library MTI Verilog Utilities The follo
301. s Expands the command line and displays each argument and switch After printing the usage message tmg_to_ts immediately exits Prints the single line version message then immediately exits Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix A Using VERA with FlexModels A Using VERA with FlexModels Overview VERA is a testbench automation tool that works as a front end to Verilog or VHDL simulators For general information on VERA refer to http www synopsys com products vera This appendix explains how to use VERA with FlexModels including a special section on how to use VERA with FlexModels with VCS This information is presented in the following sections e Using FlexModels with the VERA UDF Interface on page 270 e Creating a VERA Testbench on page 271 e VERA Testbench Example on page 272 e Incorporating FlexModels in a VERA Testbench on page 274 e Using VERA with VCS on page 275 gt Note For information on using MemPro models with VERA refer to the VERA Testbench Interface chapter in the MemPro User s Manual July 31 2001 Synopsys Inc 269 Appendix A Using VERA with FlexModels Simulator Configuration Guide Using FlexModels with the VERA UDF Interface FlexModels use the VERA UDF interface To use FlexModels with Vera you need to build the VERA dynamic library Table 33 lists the files containing the Vera UDF information for FlexModels
302. s Inc July 31 2001 Simulator Configuration Guide Index index Symbols add_instance command 227 228 display command 74 lai_command command 282 lai_disable_monitor command 70 286 lai_dump_file command 283 lai_enable_monitor command 70 72 73 lai_load_file command 285 lai_status command 70 72 290 lm_command command 282 lm_dump_file command 283 lm_help command 284 lm_load_file command 285 lm_log_test_vectors 94 lm_loop_instance 95 lm_monitor_disable command 70 286 lm_monitor_enable command 70 71 72 73 286 lm_monitor_vec_map command 70 71 74 288 lm_monitor_vec_unmap command 70 288 lm_status command 70 72 290 lm_timing_information 96 lm_timing_measurements 96 lm_unknowns 97 vera_finish_on_end switch 275 A add breakpoint command 236 add bus command 237 add lists command 235 237 add monitors command 235 add primitive command 228 add synonym command 237 add traces command 235 Admin tool 220 AIX July 31 2001 compiling C files 28 AMPLE_PATH environment variable 220 Analysis tools Mentor Graphics 247 rules to determine descriptors 248 ANSI C compiler with Cyclone 191 Attributes SmartModel 18 B Breakpoints setting with SmartModels 236 Bus symbols SmartModel 222 Buses renaming with hardware models 192 C C compiler 191 ccn_report command 71 cds lib file 200 211 cds lib path 208 ceca A environment variable CDS_VHDL environment variable 19
303. s generate a VHDL model wrapper file by invoking create_smartmodel_lib with any optional arguments For more information on the syntax for this command refer to create_smartmodel_lib Command Reference on page 126 SSYNOPSYS_SIM sim bin create_smartmodel_lib arguments gt Note The bused wrappers enable improved performance but do not work with the examples testbench shipped with the model To exercise the examples testbench use the wrappers shipped with the model see Table 18 as explained in the rest of this procedure If you are using the bused wrappers adjust accordingly 2 Create a working directory and run flexm_setup to make copies of the model s interface and example files there as shown in the following example SLMC_HOME bin flexm_setup dir workdir model_fx You must run flexm_setup every time you update your FlexModel installation with anew model version Table 18 describes the FlexModel Scirocco interface and example files that the flexm_setup tool copies Table 18 FlexModel Scirocco VHDL Files File Name Description Location model_pkg vhd Model command procedure calls for HDL workdir src vhdl Command Mode model_user_pkg vhd Clock frequency setup and user workdir src vhdl customizations model_fx_vss vhd A SWIFT wrapper for the model workdir examples vhdl model_fx_comp vhd Component definition for use with the model workdir examples vhdl entity defined in the SWIFT wrappe
304. s from the default synopsys_lm_hw_setup file shown in Figure 11 and uncomment the lines delete_files yes default yes overwrite files no default no for PPC403GA use delete_files yes overwrite files no pin_name_ovr DSR CTS NSRSCTS pin_name_ovr HALT NHALT Figure 11 Default synopsys_Im_hw setup File Deleting Intermediate Files delete_files yes no default yes By default genInterface deletes the intermediate files it creates If you want to retain the intermediate files specify delete_files no in the setup file and delete the leading character Typically you need to save these files only for debugging purposes the files are not used by Cyclone 184 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 9 Using Cyclone with Synopsys Models Overwriting Existing Files overwrite_files yes no default no By default genInterface does not overwrites files in the target directory This is to protect you from accidentally overwriting earlier versions of vhd files that you might have customized If genInterface detects a file with the same name in the target directory it generates the following warning genInterface warning retaining older version of model_name whd file If you receive this warning you must choose one of the following e If you want to save the old vhd files rename them and then run
305. s of window element A_REG you could use this command S display Address is b MY_A REG 4 To write to a window element assign a value to the register mapped to that window element For example to set Bit 4 of the window element A_REG you could use this command MY_A REG 4 1 Example 1 The following example shows the predefined scalar window elements w0 and w2 as they might appear in a typical testbench reg MY_VAR_WO users can choose descriptive variable reg MY_VAR_W2 names to fit their applications the next two lines map the variable names to the window elements and enable the window elements Slm_monitor_vec_map MY_VAR_WO U1 w0 O Slm_monitor_vec_map MY_VAR_W2 U1 w2 0 Once these window elements are set up in your testbench you can use the graphical or monitoring capabilities of Verilog XL to read write or trace the variables MY_VAR_W0O and MY_VAR_W2 which now hold the values of the window elements w0 and w2 Example 2 The following example illustrates the use of the Im_monitor_vec_map command to use memory window elements to track transactions on a memory device In the example a 4K x 8 bit memory model with instance name U1 has these predefined memory window elements e Memory array window element MEM 4K x 8 bits e Memory address window element Mem_addr 12 bits e Memory read write window element Mem_rw 2 bits For more information about memory windows
306. s with Cyclone For information on using SmartModels with Cyclone refer to Using SmartModels with SWIFT Simulators on page 18 Using FlexModels with Cyclone To use FlexModels with Cyclone you use Direct C Control For information on the required SWIFT parameters for FlexModels which differ from regular SmartModels and how to use Direct C Control refer to Using FlexModels with SWIFT Simulators on page 24 Using MemPro Models with Cyclone To use MemPro models with Cyclone follow this procedure Note that RDRAM models are not supported on Cyclone 1 For HP UX Cyclone incorrectly uses hpux10 lib in paths to platform specific directories The correct path leaf should be hp700 lib Correct the paths by creating symbolic links as follows ln s LMC_HOME 1ib hp700 1ib LMC_HOME 1ib hpux10 1ib ln s LMC_HOME mempro 1ib hp700 1ib LMC_HOME mempro 1ib hpux10 1lib 2 Create a logical library named slm_lib The default physical library mapping for this is LMC_HOME sim cyclone lib but you can put the slm_lib anywhere you want Add the following line to your synopsys_vss setup file and adjust accordantly if you put slm_lib anywhere but the default location SLM _ LIB LMC_HOME sim cyclone lib Compile the MemPro VHDL files into logical library slm_lib Oo Cyan nc synthoff lang vhdl w slm lib LMC_HOME sim cyclone srce slm_hdlc vhd Cyan nc synthoff lang vhdl w slm lib LMC_HOME si
307. s with MTI Verilog SmartModels work with MTI Verilog using a PLI application called LMTV that is delivered in the form of a swiftpli_mti shared library in LMC_HOME lib platform lib If you cannot use the swiftpli_mti refer to Static Linking with LMTV on page 114 Synopsys does not currently ship a swiftpli_mti file for use on the IBMRS AIX platform If you are using this platform refer to Using SmartModels with MTI Verilog on the IBMRS AIX Platform on page 114 To use SmartModels with the prebuilt swiftpli_mti follow this procedure l N W Y gt Note Instantiate SmartModels in your design defining the ports and defparams as required For details on the required SWIFT parameters and SmartModel instantiation examples refer to Using SmartModels with SWIFT Simulators on page 18 Compile your code as shown in the following examples UNIX vlog testbench model v incdir LMC_HOME sim pli srce NT gt vlog testbench model v incedir LMC_HOME sim pli sre where the model v files are located at LMC_HOME special cds verilog swift These v files are installed during the SmartModel installation if the customer selects either Cadence or MTI for an EDAV option Invoke the simulator as shown in the following examples HP UX vsim pli SLMC_HOME 1ib hp700 1ib swiftpli_mti sl design Solaris vsim pli LMC_HOME lib sun4Solaris lib swiftpli_mti so design Linux vsim pli LMC_HOME lib x86_linux lib
308. smartmodel Generate a VHDL model wrapper file by invoking create_smartmodel_lib with any optional arguments For information on the syntax for this command refer to create_smartmodel_lib Command Reference on page 126 SSYNOPSYS_SIM sim bin create_smartmodel_lib arguments If you changed the SMARTMODEL mapping in Step 2 you must use the srcdir option to specify that directory Also you can save time by using the model or modelfile option to specify the models you want Otherwise the script processes all installed SmartModels For example here is a recommended set of options to use for one SmartModel ttl00 in this example SSYNOPSYS_SIM sim bin create_smartmodel_1l1ib model tt100 srcdir smartmodel July 31 2001 Synopsys Inc 125 Chapter 6 Using Scirocco with Synopsys Models Simulator Configuration Guide 5 After create_smartmodel_lib has finished executing verify that the VHDL template files have been created in the appropriate directory 6 To use SmartModels in the VHDL source file of your design specify the SMARTMODEL library and instantiate each SmartModel component In the VHDL design file that uses SmartModel components enter the following library and use clauses library SMARTMODEL use SMARTMODEL components all The library logical name SMARTMODEL must be mapped to appropriate directories in your synopsys_vss setup file as described on page 125 7 Add the following line to your synops
309. spiris irpiikrierkera riii eriei eai 160 Using FlexModels with MTI VA i 44iccd cards ese ees ee eecae ender dapi 160 Using MemPro Models with MTI VHDL 9 4402666 44045405000 604 400 163 Using Hardware Models wath MTI VHDL 6 occas teva siednesevdwd nee ea ws 165 MTI VHDL Example Using TILS299 Hardware Model 166 hm entity Command Reference sda deus usp aebe be sieseeoigs eee kedis 167 PV ee ag le iy 4h Oe eee 169 Chapter 9 Using Cyclone with Synopsys Models ccc ccecccccccccsccsccees 171 Se ee ee eae Te eee eee ee ee ee er er Teer er ere ene TT ae we 171 PR Environment Variables ona pa eee ott tir ENF EINE Hea Gos 171 Using SmartModels with Cyclone 4 crib eked isd oni carte sewrne eine eheue 173 Using FlexModels with Cyclone occ iw ences na eesetherdesbadedeaeervdss 173 Usme MemPro Models with Cyclone bs i550 045 de Gees HR A OPA iaat 173 Using Hardware Models with Cyclone 5 cciasisadeieneaiwnicencd cee ee dens 174 ModelSource System Hardware and Software 0 0 00 0s 175 LM 1400 LM family System Hardware and Software 173 Configuration Options isch okt che ceed ee eehes eee cH eda E tari 175 Cyclone User SCUD 65244 rtndee eaten eE E E E 178 Using Hardware Models with Cycle Based Simulators 182 genlInterface Command Reference 2iievkicdawienbeiweten ced abwedent 186 Cyclone Simulation 2S akdend 4S de enmehsdecnd bokenenneceaeewaes 188 Cyclon seninterface Setup Files 6p ind c
310. sys Models Simulator Configuration Guide Simulation Example This simulation example illustrates how to use hardware models in a Verilog XL simulation using ModelAccess for Verilog This example assumes that all ModelAccess for Verilog configuration tasks have been accomplished Creating the Model Shell If you use ModelAccess for Verilog you cannot use existing model v files that were generated by crshell you must regenerate the model v files as described The task of creating a model shell should have been accomplished by executing Imvsg as described in Generating the Verilog XL Model Shell on page 84 For example to create the model shell model v file for the TILS299 hardware model an 8 bit universal shift storage register with 3 state outputs in the current working directory execute the following Imvsg TILS299 MDL By default if no destination is specified the current working directory is the destination directory for the TILS299 v file For complete syntax of the Imvsg script refer to Imvsg Command Reference on page 99 The following illustration shows the TILS299 v file that contains a listing of the model s pin names pin declarations parameter declarations and the model invocation which references the model MDL file in this case TILS299 MDL Generated by lmvsg 1 000 Copyright c 1984 1996 Synopsys Inc ALL RIGHTS RESERVED timescale 1 ns 1 ns expand_vectornets module TI
311. t value To generate model wrappers and instantiate models you use the same simulator specific procedures as you would for traditional SmartModels Note that the individual FlexModel datasheets document the command syntax and examples for issuing model commands from Verilog VHDL VERA or C but HDL control and switching between different command sources from the testbench are only available to the simulators with custom integrations Other SWIFT simulators must stick to Direct C Control for issuing commands to FlexModels To use Direct C Control follow these steps 1 If you are using an HDL based simulator generate a model wrapper file model_fx v or model_fx vhd using your simulator vendor s procedure Use the model wrapper to instantiate the model in your design Add the FlexCFile parameter to the model instantiation and point it to the location of your_compiled_C_file that you create to drive commands into the model Modify other SWIFT parameters in the model wrapper as needed Here are some examples for how to instantiate a model for use with Direct C Control 26 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 1 Using Synopsys Models with Simulators VHDL U1 pcimaster GENERIC MAP FlexModelId gt modelId_1 FlexCFile gt tb o FlexTimingMode gt 1 TimingVersion gt pcimaster DelayRange gt MAX Verilog defparam ul FlexModelId modelId_1 ul FlexCFile tb o ul FlexT
312. tModels including FlexModels e MemPro Models e Hardware Models Note that this manual contains illustrations of third party software files solely to demonstrate the end user modifications needed to get Synopsys models working with these tools Third party software changes frequently Refer to the third party tool vendor s documentation for definitive information about their licensed software Related Documents For more information about SmartModels including FlexModels or to navigate to a related online document refer to the Guide to SmartModel Documentation For information on supported platforms and simulators refer to SmartModel Library Supported Simulators and Platforms For detailed information about specific SmartModels including FlexModels use the Browser tool LMC_HOME bin sl_browser to access the online model datasheets For more information about MemPro or to navigate to a related online document refer to the Guide to MemPro Documentation For more information about hardware models or to navigate to a related online document refer to the Guide to Hardware Model Documents July 31 2001 Synopsys Inc 11 Preface Simulator Configuration Guide Some Hyperlinks May Not Work Because this manual is included with multiple product documentation sets some hyperlinks do not work properly in all cases For example hyperlinks from this manual to other books in the hardware model documentation set will only work from a h
313. t_path file_name file_type load file of programmable device or memory im_monitor_enable inst_path win_element enable window Monitor im_monitor_disable inst_path win_element disable window Monitor im_monitor_vec_map var_name inst_path win_element index map window to a variable for monitoring im_monitor_vec_unmap var_name inst_path unmap window to stop monitoring im_status inst_path dump instance status Commands compatible with old release lai_enable_monitor inst_path win_element enable window Monitor lai_disable_monitor inst_path win_element disable window Monitor lai_dump_file inst_path file_name file type dump memory into file lai_load_file inst_path file_name file_type load file of programmable device or memory lai_status inst_path dump instance data 284 Synopsys Inc July 31 2001 Simulator Configuration Guide Appendix B LMTV Command Reference lm_load_file or lai_load_file Use these commands to load the memory contents of the file filename into the instance inst_path which can be either a programmable device or a memory model Using these commands eliminates the write cycles required to set up the contents of the model The load_file operation causes the selected model to reset its internal state to simulation s
314. t_state storage_pin of input_state input_pin timing_spec tS timing_spec on input_pin input_state to Sstorage_pin input_trans stable valid input_pin while store_pin input_state tSTAB 0 O on input_pin V to store_pin trans1 trans2 var enumerated_list name identifier var counter name number when condition statements else_when condition statements else statements end_when with condition No equivalents to else_when and else clauses Modifying a Hardware Model Whenever you change a hardware model s Shell Software you need to rerun Im_model However you may be able to use the Step option to perform just the steps you need The following list provides some guidelines about how to take advantage of the Step option e If you change add or delete a pin name in the Shell Software then you must rerun all three steps of Im_model the default Because you are recreating the symbol you must also use the Replace option For example lm model 741s74 r e Ifyou change add or delete a timing specification in the Shell Software timing files and you are using the Technology File in QuickSim II you should use Im_model with the Step Timing switch For example lm model 741s74 s t July 31 2001 Synopsys Inc 255 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide This step is equivalent to running tmg_to_ts to
315. tartup conditions and then read the specified file After the file is read the model is evaluated as a function of the new internal state and the current inputs and outputs are scheduled with zero delay After this initial evaluation phase the model behaves as it would normally You can load a model with any file type that would normally be accepted by the model at initialization Additionally the new configuration file you load is used for the specified model instance after any subsequent command to reset or reinitialize Syntax lm_load_file inst_path filename file_type lai_load_file inst_path filename file_type Arguments inst_path The path name to the SmartModel instance into which the contents of filename is to be loaded filename The path name to the configuration file that is to be loaded for the model instance specified by inst_path The default is to use a path name defined with the defparam statement in the design file_type The type of file to be loaded Allowed values are MEMORY JEDEC PCL and SCF The default is to use the file type of the file defined with the defparam statement in the design July 31 2001 Synopsys Inc 285 Appendix B LMTV Command Reference Simulator Configuration Guide lm_monitor_enable or lai_enable_monitor lm_monitor_disable or lai_disable_monitor Use these commands to enable or disable SmartModel Windows for one or more window el
316. terface 270 with FlexModels 269 with FlexModels in testbench 272 with VCS 275 VERA command 275 vera_local dll library 276 verifySetup error message 179 executing 179 Verilog include pkgs 115 slm_pli o 27 Verilog XL capturing designs 66 compiling and simulating 89 Concept procedure 69 design capture with Concept 68 design capture 67 design flow 66 design flow with SmartModels 67 executable 89 save and restore 94 simulating and compiling 89 simulating using LMTV 76 using SmartModel windows with 70 using with SmartModels 63 with MemPro 81 with SmartModels 61 July 31 2001 Synopsys Inc 303 Index Version numbers finding 90 VHDL generics LMSI DELAY_TYPE 137 152 LMSL LOG 137 152 LMSL TIMING MEASUREMENT 136 152 with Scirocco 136 with VSS 151 VHDL keywords unacceptable as signal names 193 VHDL shell creating for Cyclone 191 vhdlan command 129 134 vhdlsim command 147 vhdlsim file 148 ViewLogic Fusion with hardware models 36 Visual C 29 45 vlib command 159 vsim command 159 163 VSS VHDL generics 151 with FlexModels 145 with MemPro models 148 with SmartModels 143 V System 160 vsystem ini file 162 W Windows LMTV SmartModel commands 70 SmartModel elements 238 SmartModel tracing instruction execution 236 SmartModels how they work 235 SmartModels with QuickSim II 235 Word triggering setting 236 Wrappers SWIFT 104 Z Zp4 switch for VCS 53 304 Synopsys Inc Simulator Configuration Guide
317. termining for hardware models 248 Design capture Verilog XL 67 flow Verilog XL 66 July 31 2001 Index Design Architect SmartModel library menus to 220 with SmartModels 220 Design Architect menus building designs with SmartModels 225 levels 226 system 226 Design environment MGC 247 Designs building using menus 225 building without menus 227 Direct C Control compiling C files 28 with FlexModels 26 DLM_HW_DEBUG flag 191 DLM_HW_PIN_DEBUG flag 191 Drive strengths 229 E Environment variables AMPLE_PATH 220 CDS_INST_DIR 102 CDS_VHDL 196 LAI_LIB 77 LAL OBJ 77 LD_LIBRARY_PATH 38 39 60 61 102 112 125 142 156 172 196 206 218 M_DIR 38 60 112 142 156 196 M_LIB 38 60 112 142 156 196 M_LICENSE_FILE 38 60 102 112 124 142 155 171 196 205 217 M_OPTION 89 188 MC_HOME 38 59 77 MC_PATH 77 MC_SFI 55 MC_TIMEUNIT 207 MC_VLOG 77 MA_CY 179 setting for LMTV 77 SHLIB_PATH 39 61 103 112 125 142 156 172 196 206 218 SNPSLMD_LICENSE_FILE 38 60 102 112 124 142 155 171 196 205 217 SS EER MERE Synopsys Inc 293 Index SSIL_LIB_FILES 277 SYNOPSYS 141 SYNOPSYS_SIM 124 141 VCS_HOME 39 42 VCS_LMC 55 VCS_LMC_HM_ARCH 55 VCS_SWIFT_NOTES 39 Error message Keys do not match 189 Errors messages 233 registration 252 Evaluation hardware models in QucikSim II 258 Examples FlexModel VHDL instantiation 43 80 105 116 130 147 162 FlexModels with VCS 45 F Fault s
318. tes Error messages can be generated by timing or usage checks Warning messages error messages and notes can all be generated by usage checks depending on the situation Hardware verification models also issue trace messages if enabled Error messages itemize selected information For example a setup time violation causes an error message that documents e Pin name e Part by instance reference designator and component name July 31 2001 Synopsys Inc 233 Chapter 12 Using QuickSim II with Synopsys Models Simulator Configuration Guide e Sheet name e Design name e Simulation time Signals and edges as appropriate Setup times as they occurred and as required by vendor data sheet Here are some sample messages 1 2751 1 2751 X Error Unknown signal level on CIK pin I 275 I 275 1 2790 1 2790 1 2790 1 2790 1 2751 1 2751 1 2751 VAES2 1514 1 2751 ES2T51 PIS2154 1 2751 1 2751 1 2751 234 This will probably cause problems later in the simulation SmartModel Instance 1 2751 U102 MC68030 20 sheet1 of schematic at time 0 0 vot Note Loading the memory image file user bobb design schematic rom_image 0_7 SmartModel Instance 1 2790 U201 127512 sheet2 of schematic at time 0 0 14 values have been initialized
319. the VERA testbench Simulator Configuration Guide 3 Send commands to a FlexModel through the model s methods In VERA Command Mode you can use the same FlexModel features and commands that you use in HDL Command Mode There are a few differences in command usage however refer to Command Syntax Differences in VERA Command Model in the FlexModel User s Manual For details on specific commands refer to FlexModel Command Reference in the FlexModel User s Manual VERA Testbench Example The following example shows how to incorporate FlexModels in a VERA testbench include lt vera_defines vrh gt Vera Dei include flexmodel_pkg vrh here include model_pkg vrh constants dei fines FlexModel generic constants defined fined here program model_test Model class and model specific Create an instance of the model argument 1 to the constructor is the string name of the instance in top level Verilog VHDL testbench argument 2 is the path to the models clock pin Here the assumption made is that the model is instantiated in a Verilog testbench Since the constructor has been called this will return at the next posedge of ul CLkK ModelFx model_1l new modeliInstName_1 ul CLK Create another instance since time has already elapsed above this call will return immediately ModelFx m
320. the file containing a list of vectors h Displays the online help for this command model MDL Specifies the name of the MDL file of the hardware model whose model v file is to be generated Description The Imvsg script creates a model v in the destination directory The model s pin names may not be legal Verilog identifiers If a pin name is found that is not a legal Verilog identifier Imvsg escapes the illegal name for example the pin name CLR becomes CLR and if the i switch was issued displays a warning message If a pin alias is defined in the model NAM file the pin alias is used as the pin name For information about editing the model NAM file refer to the ModelSource User s Manual By default Imvsg generates a module that contains a port for each logical pin If you want the module to use vectors for buses you can provide a file containing a list of the vectors For example if a device contains a 32 bit address bus the default behavior of Imvsg is to generate a module with a port list containing the ports AO A1 A31 You can use the v switch to name a file containing the statement A 31 0 Imvsg then generates the module using a 32 bit vector for the address bus 100 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 4 Using NC Verilog with Synopsys Models 4 Using NC Verilog with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels Mem
321. the hardware model for example TB_TILS299 vhd July 31 2001 Synopsys Inc 201 Chapter 10 Using Leapfrog with Synopsys Models Simulator Configuration Guide 2 Invoke Leapfrog This brings up the Notebook window where you can compile elaborate and simulate your VHDL testbench Type leapfrog amp 3 In the Notebook window select your vhd testbench file and click on the compile button 4 Once compiled use the Unit menu and select elaborate Fill in the Design Unit with your compiled information and fill the snapshot with SIM For example mywork is the directory specified to place compiled work so we use mywork TB TILS299 5 To simulate select simulate from the Unit menu and fill in the information for simulating in the snapshot line For example mywork tb_tils299 test sim This syntax can also be found at the end of the elaborate 6 To see waveforms use the simulator window to select Tools gt Navigator When you select the hardware model instance in the subscopes the signal pins come up in the Object window Select all the signals to be traced in the waveforms and right click to select Set trace simple 7 Go back to the simulator window and select Tools gt Waveview When the cwaves window comes up with all your signal pins click on run on the simulator window to simulate Leapfrog Utilities The following hardware modeler simulator commands are supported in Leapfrog Im_log_test_vectors instance_na
322. tial begin Slm_log_test_vectors tbench U1 1 hwm299 vec 4200 Sstop Slm_log_test_vectors tbench U1 0 hwm299 vec end The Test Vector Log File This next illustration shows part of a test vector log file hwm299 vec test_vector_ format 2 test TILS299 time stamp 1 nanosecond runtime_modeler_ software R3 3a Simulator_function_interface R3 3a SR 1 I SL 2 I IIIIIIIIBBBBBBBBOO SSSSCGGCHGFEDCBAQQ RL1LOL21L HA K RQQQQQQQQ HGFEDCBA INIT DDDDDUUDTTTTTTTT ZZZZZZZZLL 0 DDDDUDDDTTTTTTTT LLLLLLLLLI 30 DDDDUDDDDDDDDDDD 50 DDDDDDDDDDDDDDDD 100 DDDDUDDDDDDDDDDD patterns Se Se OSE H H a a a ee on 92 Synopsys Inc July 31 2001 Simulator Configuration Guide 150 200 250 300 350 395 Chapter 3 Using Verilog XL with Synopsys Models Understanding the Test Vector File The test vector file is written in Logic Modeling test vector format Symbols for input and output values are defined in Table 15 Table 15 Test Vector Symbols Symbol Input Output Definition U Input Drive hard 1 D Input Drive hard 0 u Input Drive soft resistive 1 d Input Drive soft resistive 0 T Input Drive floating level
323. tion about using hardware models refer first to Using Hardware Models with Different Simulators on page 35 for an overview and then consult the appropriate simulator specific chapter in this manual for detailed setup procedures The procedures in this chapter are organized into the following major sections e Using SmartModels with SWIFT Simulators on page 18 e Using FlexModels with SWIFT Simulators on page 24 e Using MemPro Models with VHDL and Verilog Simulators on page 29 e Using Hardware Models with Different Simulators on page 35 Using SmartModels with SWIFT Simulators SWIFT is a standard EDA event level simulation interface developed by Synopsys The SWIFT interface enables multiple simulators with different requirements to use models from the same SmartModel Library Each simulator provides a standard model interface specified by SWIFT that allows it to load the same SmartModel Library When the simulator encounters a SmartModel during simulation it uses a set of SWIFT functions to create and configure the model map to its ports initialize it and set its time units The SWIFT interface also allows participating simulators to integrate the SmartModel Library into their particular framework including application specific menus For more information refer to the documentation provided by your simulator vendor SmartModel SWIFT Parameters SmartModel attributes or parameters are model specific values ne
324. to reflect the new model list After successful menu activation the Libraries pull down menu of the Schematic Editor contains an entry for Logic Modeling SmartModel Library If you have SimuBus models installed the pull down menu also contains an entry for Logic Modeling SimuBus Products Using SmartModels FlexModels with QuickSim II This chapter provides information about using SmartModels including FlexModels with Mentor Graphics MGC tools This information is organized in the following major sections e Schematic Capture e Logic Simulation e Custom Symbols Schematic Capture Adding a SmartModel Library model to a design schematic involves identifying the desired symbol instantiating it and then editing its properties as necessary Synopsys supplies a complete Schematic Editor menu system in the QuickSim II environment that you can use to identify and instantiate a component You can also instantiate symbols from the command line and edit property values interactively using Design Architect This chapter provides information about both approaches to building a design following an introductory discussion of the symbols and their properties For more information about Design Architect and the Schematic Editor refer to the Mentor Graphics documentation Symbols Synopsys provides symbols representing default package pinouts for each SmartModel Some models have more than one symbol associated with them This
325. u can use the one from CDS_INST_DIR tools bin by adding CDS_INST_DIR tools bin to your path statement 3 Update the clock frequency supplied in the model_user_pkg inc file to correspond to the CLK period you want for the model This file is located in workdir sre verilog model_user_pkg inc where workdir is your working directory July 31 2001 Synopsys Inc 79 Chapter 3 Using Verilog XL with Synopsys Models Simulator Configuration Guide 4 Add the following line to your Verilog testbench to include FlexModel testbench interface commands in your design include model_pkg inc lt gt Note Be sure to add model_pkg inc within the module from which you will be issuing FlexModel commands Because the model_pkg inc file includes references to flexmodel_pkg inc and model_user_pkg inc you don t need to add flexmodel_pkg inc or model_user_pkg inc to your testbench 5 Instantiate the FlexModel in your design defining the ports and defparams as required refer to the example testbench supplied with the model You use the supplied bus level wrapper model v in the top level of your design to instantiate the supplied bit blasted wrapper model_fx_vxl v Example using bus level wrapper model v without timing model U1 model ports defparam U1 FlexModelId TMS INST1 Example using supplied bus level wrapper model v with timing model U1 model ports defparam U1 FlexTimingMode FLEX TIMING
326. u override the hardware modeler s default handling of timing information for a specified model instance Syntax lm_timing_information instance_path timing_option Arguments instance_path Specifies the Verilog pathname of the instance whose timing information is to be modified timing_option Allowed values are nodelay to ignore all delay information delay to process all delay information notimingchecks to ignore all timing checks and timingchecks to apply all timing checks The defaults are delay and timingchecks Description The lm_timing_information command allows you to override the hardware modeler s default handling of timing information for a specified model instance By default the hardware modeler processes all delay information and applies all timing checks You can decrease model evaluation time by disabling these activities The hardware modeler does not process information that is not needed by the simulator Example The following example disables timing checks for the U1 model instance lm_timing_information U1 notimingchecks lm_timing_ measurements Command Reference The lm_timing_measurements command enables timing measurements for a specified model instance It is not supported for ModelSource 3200 and 3400 Syntax lm_timing_measurements instance_path on_off filename 96 Synopsys Inc July 31 2001 Simulat
327. u to read from write to or trace the internal register through your user defined variable You must define this variable with a width corresponding to that of the predefined window somewhere in the design hierarchy typically in the testbench before using these commands Note that these commands only work in SWIFT SmartModel mode Using lm_monitor_vec_map you can access arrays of registers which is useful for addressing specific memory locations as in the memory window elements feature In addition lm_monitor_vec_map allows dynamic window creation Thus if a SmartCircuit model changes its configuration file so that more windows are created you can add those names to your testbench and enable tracing directly Syntax lm_monitor_vec_map var_name inst_path window_element index lm_monitor_vec_unmap var_name inst_path Arguments var_name The name of a user defined variable to map to window_element The variable must be already defined somewhere in the design hierarchy The default for lm_monitor_vec_unmap is to unmap all mapped variables for that instance inst_path The path name to the SmartModel instance whose internal register is to be mapped to the user defined variable var_name window_element The name of the internal register to be mapped to var_name Can be part of an array index The index of the array if the window element is a memory window The default is 0 Examples The following examp
328. uide Cyclone genlnterface Setup Files This section describes the ModelAccess for Cyclone setup file syntax and usage Setup File Definition Two sets of setup files are provided for genInterface 1 Model dependent setup information is stored in the following file SMA_CY setup synopsys_lm_hw setup This file is typically copied by each user from this central location into the their own directory where it can be edited for a particular session Use of this setup file is described in Editing the Setup File on page 184 2 System dependent setup information is stored in these three platform specific files o MA_CY setup synopsys_Im_hw setup hp700 o MA_CY setup synopsys_lm_hw setup solaris These files are provided to allow a system administrator to update compiler and linker information if necessary If the ANSI C compiler acc is used then no editing of these files should be required Search Path Upon invocation the genInterface program searches for the synopsys_Im_hw setup file and the synopsys_Im_hw setup platform files in the following locations in the order listed 1 Current working directory files preceded by 2 User s home directory files preceded by 3 MA_CY setup files without a prefix System Dependent Setup Options The system dependent setup files allow you to change default settings for genInterface A sample of the HP UX version of the file is shown in Figure 12 190 Sy
329. ulators through the SWIFT interface If you are using a SWIFT simulator that does not have a separate chapter devoted to it in this manual refer to this chapter for the basic information needed to get the models working on your simulator For information on SmartModel FlexModel supported simulators refer to the SmartModel Library Supported Platforms and Simulators Manual MemPro models are produced in Verilog or VHDL and do not use the SWIFT interface They do require simulator specific PLI CLI FLI code that needs to be bound in to the supported simulator executable MemPro is supported on the simulators listed in Table 5 The hardware modeler uses real silicon in combination with specialized hardware and software to represent the full functionality of modeled devices in your simulation It does not have a standard interface comparable to SWIFT Hardware models are a combination of hardware and software as follows e The hardware consists of the actual silicon of the device being modeled installed on a special purpose Device Adapter and inserted into the hardware modeling system July 31 2001 Synopsys Inc 17 Chapter 1 Using Synopsys Models with Simulators Simulator Configuration Guide e The software consists of a series of ASCII files containing Shell Software that describes the device interface and initialization along with optional information such as timing delays state tracking and timing checks For simulator specific informa
330. uly 31 2001 Simulator Configuration Guide Chapter 1 Using Synopsys Models with Simulators Table 2 FlexModel SWIFT Parameters Continued Parameter Data Type Description FlexCFile path_to_C_file u c Specifies the path to an executable C program and whether to start up in coupled c or uncoupled u mode Uncoupled mode is the default Note Used only with _fx models for Direct C Control FlexModelSrc_cmd_stream path_to_C_file u c If you want to control a FlexModel using Direct C Control change the default value for cmd_stream HDL to the name of the command stream defined in the individual FlexModel datasheets Use this parameter to specify the path to an executable C program and whether to start up in coupled c or uncoupled u mode Uncoupled mode is the default Note Used only with _fz models for Direct C Control a Some FlexModels have additional SWIFT parameters that need to be specified to configure internal memory for example the usbhost_fz For details refer to the individual FlexModel datasheets flexm_setup Command Reference In addition to specifying SWIFT parameters you must run the flexm_setup utility each time you install a new or updated FlexModel into your LMC_HOME tree This ensures that you pick up the latest package files for that version of the model Syntax flexm_setup help dir path model Argument model
331. umber 1 is_it_a_vector Yes prev_signal current_signal prev_test current_test prev_number current_number next else if is_it_a_vector Yes total prev_number data_start if prev_number gt data_start data_end data_start data_start prev_number else data_end prev_number data_type _vector data_start downto data_end prev_signal prev_test if prev_signal gsub prev_signal n split prev_signal array_c a zA z0 9_ y 20 n if y gt 0 for i 1 i lt 20 n i prev_signal prev_signal if 0 S amp amp pin_type 3 Simulator Configuration Guide current_number prev_number 1 ending printf prev_signal prev_dir std_logic data_type ending n data_type is_it_a_vector No updown prev_signal current_signal prev_test current_test prev_dir direction prev_number current_number END printf n printf end device n n printf architecture LMSI of device is n printis attribute FOREIGN of ILMSI printf begin n printf end IMSI n n 154 Synopsys Inc architecture is Synopsys LMSI n July 31 2001 Simulator Configuration Guide Chapter 8 Using MTI VHDL with Synopsys Models 8 Using MTI VHDL with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels MemPro models and h
332. up 25 27 Im_model 247 249 250 252 253 255 256 Im_model syntax 264 reg_model 240 249 256 registration reference 264 tmg_to_ts 249 tmg_to_ts syntax 267 Tracing instruction execution 236 Tracking state 253 Transcript registration checking 252 Trees management Mentor Graphics 219 Triggering word setting 236 July 31 2001 Simulator Configuration Guide Typographical conventions 13 U Unknown mapping with hardware models 259 Unknown propagation with hardware models 260 USE statement 129 147 162 207 209 Using 83 Using FlexModels with Direct C Control 26 with SWIFT simulators 26 Using MemPro models with Verilog simulators 31 with VHDL simulators 31 Utilities called by Im_model command 249 Check Shell Software 252 Im_model 247 249 250 252 253 255 256 Vv Variables location map Mentor Graphics 220 vcom command 159 162 VCS FlexModel examples run script 49 invoking on AIX 41 invoking on HP UX 40 invoking on Linux 41 invoking on Solaris 40 with FlexModels 42 with MemPro models 51 with SmartModels 39 with VERA 275 VCS utilities with hardware models 57 Index VCS_HOME environment variable 39 42 VCS_LMC environment variable 55 VCS_LMC_HM_ARCH environment variable 55 VCS_SWIFT_NOTES environment variable 39 Vectors test logging 261 VEDA Vulcan with hardware models 36 VERA compiling source files 274 compiling testbench 275 testbench creation 271 testbench example 272 UDF in
333. ure call Example call from VHDL code Variable ret Natural ret 1lm_log_test_vectors U1 1 U1 VEC wait for 800 ns ret 1lm_log_test_vectors U1 0 U1 VEC Example invocation from the debugger prompt with Im_procedure call gt call 1lm_log_test_vectors U1 1 U1 VEC July 31 2001 Synopsys Inc 203 Chapter 10 Using Leapfrog with Synopsys Models Simulator Configuration Guide 204 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 11 Using NC VHDL with Synopsys Models 11 Using NC VHDL with Synopsys Models Overview This chapter explains how to use SmartModels FlexModels and MemPro models with NC VHDL The procedures are organized into the following major sections e Setting Environment Variables on page 205 e Using SmartModels with NC VHDL on page 206 e Using FlexModels with NC VHDL on page 208 e Using MemPro Models with NC VHDL on page 210 e Using Hardware Models with NC VHDL on page 213 Setting Environment Variables First set the basic environment variables If you are not using one of the model types skip that step In some cases the procedures that follow in this chapter include steps for setting additional environment variables 1 Set the LMC_HOME variable to the location of your SmartModel FlexModel and MemPro model installation tree as follows o setenv LMC HOME path to models_ installation 2 Set the LM_LICENSE_FILE or S
334. ven n n unless ARGV 0 STmpDir SENV TMPDIR die ERROR running 0 The TMPDIR environment variable must be set n unless TmpDir SImcHome SENV LMC_HOME die ERROR running 0 The LMC_HOME environment variable must be set n unless LmcHome SSynopsysHome SENV SYNOPSYS_SIM die ERROR running 0 The SYNOPSYS_SIM environment variable must be set n unless S SynopsysHome require SLlmcHome 1lib bin libmd101003 p1 Platform GetPlatform SPlatform_lib PlatformToLibDir Platform Sflexmodel_name SARGV 0 DirSep Soutput_file TmpDir DirSep Example_Simulator_Run_Script_ flexmodel_name txt Smodel_path LmcHome models flexmodel_name if e model_path else die nERROR running 0 FlexModel flexmodel_name Does not Exist in Library n n Sversion_path lmcHome bin flexm_setup flexmodel_name chomp version_path if flexmodel_name _fx flexmodel_name s _fx g flex_or_c _fx elsif flexmodel_name _fz flexmodel_name s _fz g flex_or_c _fz else die nERROR running 0 S flexmodel_name is not a FlexModel Model must have an _fx or _fz to be a FlexModel n n Ssetup_file TmpDir DirSep synopsys_vss setup open OFILE gt setup_file die Could not create file setup_file n print OFILE Example Scirocco library setup file n print OFILE work gt DEFAULT n print OFI
335. vhdlan event w slm lib workdir src vhdl model_fx vss vhd vhdlan event w slm lib workdir src vhdl model vhd 6 Add LIBRARY and USE statements to your testbench library slm lib use slm lib flexmodel_pkg all use slm lib model_pkg all use slm lib model_user_pkg all oA oP oP AP Ol o For example you would use the following statement for the tms320c6201_fx model use slm lib tms320c6201_pkg all use slm lib tms320c6201_user_pkg all July 31 2001 Synopsys Inc 129 Chapter 6 Using Scirocco with Synopsys Models Simulator Configuration Guide 7 Instantiate FlexModels in your design defining the ports and generics as required refer to the example testbench supplied with the model You use the supplied bus level wrapper model vhd in the top level of your design to instantiate the supplied bit blasted wrapper model_fx_vss vhd Example using bus level wrapper model vhd without timing Ul model generic map FlexModelID gt TMS INST1 port map model ports Example using bus level wrapper model vhd with timing U1 model generic map FlexModelID gt TMS INST1 FlexTimingMode gt FLEX_TIMING_MODE_ON TimingVersion gt timingversion DelayRange gt range port map model ports 8 Compile your testbench as shown in the following example vhdlan testbench 9 Invoke the Scirocco simulator as shown in the following example scsim vhpi slm_vhpi foreignINITelab
336. vice name and the Imsi list ids command to list all hardware model instances by id name For example Imsi list devices device name id instance name logging TILS299 0 TB_TILS299 U0 OEr Imsi list ids id device name instance name logging 0 TILS299 TB_TILS299 U0 Off You can also log test vectors for the hardware model To log by ID number specify an id and a filename The extension TST is appended to the vector file name If no file name is specified VSS writes to a file named device_name id TST For example lmsi logon id filename To log vectors by instance name specify an instance_name and filename The extension TST is appended to the output file name For example lmsi logon instance_name filename To log vectors for all hardware model device instances specify all A log file is created for each instance The output files are named device_name id TST For example lmsi logon all To turn off vector logging replace logon with logoff and omit the file name in the above examples VHDL Model Generics with Scirocco You can also control hardware model behavior using VHDL generics in your hardware model instantiations The nawk script on page 138 creates VHDL wrappers for hardware models with these VHDL generics set to values that are reasonable for most simulations However you can modify the values of the VHDL generics in your model vhd files to suit your verification needs For more inform
337. voke VCS on your design simv VCS MemPro Model Explanation Table 10 lists each line in the invocation examples above along with explanations for what each one does Table 10 VCS MemPro Model Explanation Line Reference Description SVCS_HOME bin vcs mempro_model v mempro_model_tb v Path to the file that starts the VCS simulator followed by the specified model and testbench Verilog files P SLMC_HOME sim pli src slm_pli tab Specifies the MemPro PLI table entry file LMC_HOME 1ib sun4Solaris 1ib slm_pli o Specifies the platform specific MemPro PLI object file Mupdate This specifies incremental compilation which causes VCS to compile only the modules that have changed since the last run RI This makes VCS run interactively VCS invokes the XVCS GUI after compilation and pauses the simulator at time zero LDFLAGS switches Additional platform specific switches that may be needed 54 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models Using Hardware Models with VCS To use hardware models with VCS follow this procedure 1 Add the hardware model install tree to your path variable as shown in the following example set path install sms bin platform path 2 Set the VCS_LMC environment variable to the hm directory in the VCS install as shown in the following example setenv VCS_LMC VCS_HOME plat
338. wing example mti_path bin vlog testbench incdir LMC_HOME sim pli sre t incdirt workdir sre verilog 4 Invoke the simulator as shown in the following example mti_path bin vsim design Note that the loadpli switch is not supported on this platform 114 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 5 Using MTI Verilog with Synopsys Models Using FlexModels with MTI Verilog FlexModels work with Verilog XL using a PLI application called LMTV that is delivered in the form of a swiftpli_mti shared library in LMC_HOME lib platform lib If you cannot use the swiftpli_mti refer to Static Linking with LMTV on page 117 To use the prebuilt swiftpli_mti follow this procedure 1 Create a working directory and run flexm_setup to make copies of the model s interface and example files there as shown in the following example SLMC_HOME bin flexm_setup dir workdir model_fx You must run flexm_setup every time you update your FlexModel installation with anew model version Table 17 lists the files that flexm_setup copies to your working directory Table 17 FlexModel MTI Verilog Files File Name Description Location model_pkg inc Verilog task definitions for FlexModel workdir src verilog interface commands This file also references the flexmodel_pkg inc and model_user_pkg inc files model_user_pkg inc Clock frequency setup and user customizations workdir src verilog model_f
339. wing hardware model utilities are supported in MTI Verilog lm_log_test_vectors instance_path on_off filename The lm_log_test_vectors command enables test vector logging for a specified instance and specifies a file name for the test vector log For a detailed syntax description refer to lm_log_test_vectors Command Reference on page 94 lm_loop_instance instance_path The 1m_loop_instance command enables the loop mode for a specified model instance For a detailed syntax description refer to l1m_loop_instance Command Reference on page 95 lm_timing_information instance_path timing_option The lm_timing_information command lets you override the hardware modeler s default handling of timing information for a specified model instance For a detailed syntax description refer to lm_timing_information Command Reference on page 96 lm_timing_measurements instance_path on_off filename The lm_timing_measurements command enables timing measurements for a specified model instance It is not supported for ModelSource 3200 and 3400 For a detailed syntax description refer to lm_timing_measurements Command Reference on page 96 lm_unknowns option value option value device_or_pin The lm_unknowns command lets you override the hardware modeler s default handling of unknown values for specified instances or pins o
340. with VCS refer to the VCS Users s Guide Note that in the previous VCS releases the hardware model could only be simulated with typical delays The VCS 5 2 release has removed this restriction so you can now either use a runtime option on the command line or make the change in the delayrange parameter Note that the runtime option does override any delayrange parameter specification The following excerpt is from the VCS 5 2 Release Notes 56 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 2 Using VCS with Synopsys Models VCS 5 2 has a new runtime option override_model_delays that enables you to use the mindelays typdelays or maxdelays runtime option to specify timing in SWIFT SmartModels or Synopsys hardware models and in so doing override the DelayRange parameter in the template files for these models that otherwise specifies the timing for the model Example Using Runtime Option Here is an example using the runtime option o ves plusarg_save RI test v TILS299 lmvc v P VCS_IMC lmvc tab VCS_IMC lmvc o LM_SFI 1lm_sfi a o simv override model_delays maxdelays 1 vcs log amp Example Using DelayRange Parameter Here is an example using the DelayRange parameter TILS299 hwm 1 SL shift_left CLK clock SR shift_right NCIR clear G2 g2 G1 gl S1 select_1 SO select_0 D QD bit_4 F OF bit_6 B OB bit_2 C QC bit_3 A QA bit_1 G
341. ws For more information refer to sm_entity Command Reference on page 160 Q sm entity c model gt model vhd For example sm entity c tt1373 gt tt1373 vhd generates the following VHDL file which has both entity and component declarations for the model Edit the resulting VHDL file to add the portions of text that are highlighted in the following example library IEEE use IEEE std logic_1164 all entity tt1373 is generic TimingVersion STRING SN74LS373 DelayRange STRING MAX ModelMapVersion STRING 01008 port C in std logic D1 in std_logic D2 4 an std logic D3 in std_logic D4 in std_logic July 31 2001 Synopsys Inc 157 Chapter 8 Using MTI VHDL with Synopsys Models 158 D5 in std_logic D6 in std_logic D7 in std_logic D8 in std_logic OG in std_logic Ql out std_logic Q2 out std_logic Q3 out std_logic Q4 out std_logic Q5 out std_logic Q6 out std_logic Q7 out std_logic Q8 out std_logic end architecture SmartModel of tt1373 is attribute FOREIGN STRING attribute FOREIGN of SmartModel architecture is sm_init SMODEL_TECH libsm sl tt1373 begin end SmartModel library ieee use ieee std_logic_1164 all package comp is component tt1373 generic TimingVersion STRING SN74LS373 DelayRange STRING MAX ModelMapVersion STRING 01008 port C in std_l
342. x_mti v A SWIFT wrapper that you can use to instantiate workdir examples verilog the model model v A bus level wrapper around the SWIFT model workdir examples verilog This allows you to use vectored ports for the model in your testbench model_tst v A testbench that instantiates the model and shows workdir examples Verilog how to use basic model commands 2 Update the clock frequency supplied in the model_user_pkg inc file to correspond to the CLK period you want for the model This file is located in workdir sre verilog model_user_pkg ine where workdir is your working directory 3 Add the following line to your Verilog testbench to include FlexModel testbench interface commands in your design include model_pkg inc July 31 2001 Synopsys Inc 115 Chapter 5 Using MTI Verilog with Synopsys Models Simulator Configuration Guide gt Note 116 Be sure to add model_pkg inc within the module from which you will be issuing FlexModel commands Because the model_pkg inc file includes references to flexmodel_pkg inc and model_user_pkg inc you don t need to add flexmodel_pkg inc or model_user_pkg inc to your testbench Instantiate FlexModels in your design defining the ports and defparams as required refer to the example testbench supplied with the model You use the supplied bus level wrapper model v in the top level of your design to instantiate the supplied bit blasted wrapp
343. xists it is overwritten Using this command eliminates the read cycles required to verify the success of a test You can reload the dumped file into a memory model using the lm_load_fileQ command The format of the dumped file is the same as the Synopsys memory image file format required by a memory model at initialization Syntax lm_dump_file inst_path filename file_type lai_dump_file inst_path filename file_type Arguments inst_path The path name to the SmartModel instance whose memory information is to be dumped filename The path name to the file that is to receive the dumped memory information from the model instance file_type The type of configuration file to be dumped The only allowed value is MEMORY which is also the default This argument is provided for compatibility with the historic environment July 31 2001 Synopsys Inc 283 Appendix B LMTV Command Reference Simulator Configuration Guide lm_help Use this command to display the syntax for all of the SWIFT interface commands Syntax lm_help Examples The following example shows the results of issuing the command lm_help C2 gt Im help LMTV commands lm_command session_command execute a session command im_command inst_path model_command execute a model command im_dump_file inst_path file_name file_type dump memory into file Im_load_file ins
344. xm_setup dir workdir model_fx bin c89 o executable_name your_C_file c workdir sre C hp700 model_pkg o IMC_HOME 1ib hp700 1ib flexmodel_pkg o ISLMC_HOME sim C src Iworkdir sre C 1BSD ol b On Solaris you need to link in the lsocket library as shown in the following example mkdir workdir flexm_setup dir workdir model_fx cc o executable_name your_C_file c workdir sre C solaris model_pkg o LMC_HOME 1ib sun4Solaris 1ib flexmodel_pkg o ISLMC_HOME sim C sre Iworkdir sre C lsocket c AIX mkdir workdir flexm_setup dir workdir model_fx bin ce o executable_name your_C_file c workdir sre C ibmrs model_pkg o LMC_HOME 1lib ibmrs 1lib flexmodel_pkg o Iworkdir sre C IS LMC_HOME sim C src ldl o o o o 28 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 1 Using Synopsys Models with Simulators d Linux oe mkdir workdir flexm_setup dir workdir model_fx eges o executable_name your_C_file c workdir sre C x86_linux model_pkg o LMC_HOME 1ib x86_linux 1ib flexmodel_pkg o Iworkdir sre C IS LMC_HOME sim C src oe oe e On NT you need to link in a Windows socket library as shown in the following example gt md workdir gt flexm setup dir workdir model_fx gt cl 02 MD DMSC DWIN32 Feexecutable_name your_C_file c workdir sre C pent model_pkg obj LMC_HOME 1ib pent 1ib flexmo
345. y adding it to your path statement 2 Set your SHLIB_PATH or LD_LIBRARY_PATH variable to point to the directories that contain the ModelAccess libraries Solaris users also need to add the usr dt lib and usr openwin lib libraries HP UX setenv SHLIB PATH hardware_model_iinstall_path sms ma_verilog 1lib pa_hp102 SCDS_ INST DIR tools 1ib Solaris setenv LD LIBRARY PATH hardware_model_install_path sms ma_verilog 1ib sun4 solaris CDS_INST_DIR tools 1lib usr dt 1lib usr openwin lib For NT add this path to the PATH user variable hardware_model_install_path sms ma_verilog lib pent 108 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 4 Using NC Verilog with Synopsys Models 3 Invoke the simulator as shown in the following example o nceverilog testbench v model v loadplil mav mav_boot NC Verilog Utilities The following hardware model utilities are supported in NC Verilog lm_log_test_vectors instance_path on_off filename The Im_log_test_vectors command enables test vector logging for a specified instance and specifies a file name for the test vector log For a detailed syntax description refer to lm_log_test_vectors Command Reference on page 94 lm_loop_instance instance_path The lm_loop_instance command enables the loop mode for a specified model instance For a detailed syntax description refer to 1m_loop_instance Command Reference on
346. ys_vss setup file TIMEBASE PS 8 Instantiate SmartModels in your VHDL design For information on required configuration parameters and instantiation examples refer to Using SmartModels with SWIFT Simulators on page 18 9 Compile your testbench as shown in the following example vhdlan testbench 10 Invoke the Scirocco simulator as shown in the following example scsim design For information about scsim and the VHDL debugger refer to the Scirocco User s Guide create_smartmodel_lib Command Reference The command reference for create_smarmodel_lib is as follows Syntax create_smartmodel_lib nc create srcdir dirpath analyze nowarn modelfile file model model_name Arguments Displays the usage message and lists the command line options nc Suppresses the Synopsys copyright message 126 Synopsys Inc July 31 2001 Simulator Configuration Guide Chapter 6 Using Scirocco with Synopsys Models create src_dir dirpath analyze nowarm modelfile file model model_name Description Creates the VHDL source files vhd files for the SMARTMODEL library and saves the source files in the LMC_HOME synopsys directory Lets you specify the location of the VHDL source files that you create The default location is LMC_HOME synopsys Analyzes the SMARTMODEL library source files vhd files by invoking vhdlan The analyzed files sim and mra files are saved in the LMC_

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