Working with the Embedded Artists LPC2148 evaluation boards
Contents
1. i Part one of the system initialization code contains low level initialization Copyright 2006 IAR Systems All rights reserved 5 Revision 30870 MODULE cstartup Forward declaration of sections SECTION IRQ STACK DATA NOROOT 3 5 SECTION STACK DATA NOROOT 3 SECTION ABT STACK DATA NOROOT 3 SECTION SVC STACK DATA NOROOT 3 SECTION UND STACK DATA NOROOT 3 SECTION CSTACK DATA NOROOT 3 The module in this file are included in the libraries and may be replaced by any user defined modules that define the PUBLIC symbol ar program start or a user defined start symbol To override the cstartup defined in the library simply add your modified version to the workbench project SECTION intvec CODE NOROOT 2 PUBLIC _ vector PUBLIC _ vector 0 14 PUBLIC iar program start EXTERN irq handler fiq handler ARM Vector ldr 24 Reset B Undefined instructions B 5 Software interrupt SWI SVC B Prefetch abort B Data abort vector 0 14 DC32 0 RESERVED ldr 24 5 IRQ ldr 24 FIQ DC32 iar program start Reset DC32 0 Undefined instructions DC32 0 Software interrupt SWI SVC DC32 0 Prefetch abort DC32 0 Data abort DC32 0 RESERVED DC32 irq handler 5 IRQ DC32 fiq handler FIQ cstartup low level system initialization code2. 332444 484848 weananananan 9 red ded yuu EmbeddedArtists I YY YY A 29 Figure Appearance of the debug board 2 Compile and debug programs using debugging tools 21 Compiling the project Consider debugging created in the first part of the draft program with the debug board To do this make sure that part of the project files added Main cpp and lcd cpp as well as customized configuration of the project Debug Release and RAM Now the project is ready for compiling and debugging To assemble and build the object files you can use the menu PROJECT select the tab where the MAKE or COMPILE After completion of the compilation with er rors or warnings will automatically open with the results of MESSAGES 22 Hardware debugging After simulation process is successfully completed it is useful to test the pro gram with the help of the development board This step of the development process allows to test software hardware interaction Attach J Link module to JTAG connect or on the development board and insert the cable to the USB connector on your PC then connect carefully with the cable USB minijack on the development board close to power connector to the left of JTAG with the second USB connector on your PC Power LED should confirm the presence of the power on the development board Check LED blinking on J Link module Set RAM configuration and start the debugger as mentioned earlier the
3. View Terminal I O Look at the output messages initiated by IRQ handler Press the button P0 14 and look at the result in the terminal window Remove from the project file main VIC cpp and add file main VIC UART cpp Carefully put the cable from USB jack UART connector on the left Set RAM configuration build and start program Start program RS 232 that Is intended for RS 232 information interchange set there baudrate 19200 and se lect appropriate COM port set checkbox ASCII Look at the information transmitted by development board to the PC in the main window of the program Change baudrate to 9600 and check the operability 3 5 SPI module Remove files main VIC cpp and lpc2xxx startup s and add files main SPI cpp spi cpp Also copy file spi h into the project directory Set RAM configuration build and start program Using joystick in the right lower corner of the development board change position of active LED in the matrix Correct the program to provide diagonal movement Create your own effect of LED movement Schematic diagram of joystick connections is shown in the appendix 3 6 ADC operation Remove files main SPLcpp spi cpp spi and add files AD C cpp adc cpp lcd cpp Also copy file main ADC h Instead Ipc2xxx startup s insert file 2 startup no fiq s where fiq handler is blocked This allows to disable FIQ interrupt Set RA
4. Dmitry Kornilin Samara State Aerospace University SSAU
5. STACK DATA NOROOT 3 SECTION UND STACK DATA NOROOT 3 SECTION CSTACK DATA NOROOT 3 The module in this file are included in the libraries and may be replaced by any user defined modules that define the PUBLIC symbol iar program start or a user defined start symbol To override the cstartup defined in the library simply add your modified version to the workbench project SECTION intvec CODE NOROOT 2 PUBLIC _ vector PUBLIC q vector 0 14 PUBLIC iar program start EXTERN irq handler ARM Vector ldr 24 Reset B Undefined instructions B 5 Software interrupt SWI SVC B Prefetch abort B Data abort vector 0 14 DC32 0 RESERVED ldr pc pc OxFFO IRQ DC32 0 3 DC32 iar program start Reset DC32 0 Undefined instructions DC32 0 5 Software interrupt SWI SVC DC32 0 Prefetch abort DC32 0 Data abort DC32 0 RESERVED DC32 0 5 IRQ DC32 0 3 cstartup low level system initialization code After a reser execution starts here the mode is ARM supervisor with interrupts disabled SECTION text CODE NOROOT PUBLIC cstartup EXTERN main REQUIRE vector ARM _ jar program start cstartup 9 Add initialization needed before setup of stackpointers here LPC2148 Errata Date August 5 2005 Document Release Version 1 0 Device Affected LPC2148 Incorrect read of data from SRAM after Reset and MAM is not enable
6. a program of light effects on matrix display that changes at random po sition of luminous points 10 Create a program for a device that displays on the LCD display the contents of the counter milliseconds when you click P0 14 S Bibliography l Trevor Martin The insider s guide to the Philips ARM7 BASED MICROCONTROLLERS An engineer s introduction to the LPC 2000 Series 2 UM10139 Volume 1 LPC214X User Manual Rev 01 15 August 2005 3 ARM7 TDMI Rev 3 Technical Reference Manual Appendix Source code of programs main cpp include lt NXP iolpc2148 h gt include lt stdio h gt int main void void InitLCD void void SetBacklight int Backlight void LCDTextOut unsigned char const top line unsigned char const bottom line int Sleep int _ slp int main InitLCD 0 SetBacklight 1 LCDTextOut NXP LPC2148 Basic project IOODIR 0x0000FF00 Set PO 8 P0 15 as outputs IOOSET 0x0000FF00 Clear PO 8 P0 15 IOODIR amp OxFFFFBFFF 14 input MAMCR 0 3 int 1 8 while 1 IOOCLR 1 lt lt i shift LEDs Sleep 200 IOOSET 1 4 Sleep 200 if Hi 14 i 8 if IOOPIN amp 0x00004000 0 MAMCR 2 else MAMCR 0 lcd cpp include lt NXP iolpc2148 h gt define bD
7. int j for int i 0 1 lt 1000 i j i 1 return j j 5 1 include lt NXP iolpc2148 h gt include spi h void InitSPI void IOODIR 1 lt lt 15 Chip select for shift registers IOOSET 1 lt lt 15 PINSELO 1 lt lt 8 1 lt lt 10 1 lt lt 12 SOSPCR 0 2 set up bits per transfer 0 8bit 1 defined 1 3 CPHA mode 1 lt lt 4 SCK is active high 1 lt lt 5 Set SPI as master 0 lt lt 8 16 bits per transfer SOSPCCR 64 void SPIPutDot int x int y IOOSET 1 lt lt 15 Pull up P0 15 SOSPDR 1 lt lt y 1 while SOSPSR amp 1 lt lt 7 0 Wait until data is sent SOSPDR 1 lt lt 8 x while SOSPSR amp 1 lt lt 7 0 Wait until data is sent IOOCLR 1 lt lt 15 Pull down P0 15 apply new settings 5 1 ifndef SPI define SPI void InitSPI void void SPIPutDot int x int y endif main ET sie SF SF ie sk sje ie oie sk zk zk sk 2 ok oR oR oR fe SF SF oe oe ole sk oe ie zk zk e ak ok oR oR ok SF ie SF SF oe oe 2 fe a 2 oe oe sk k R oR 2 ae SR SF oko fe Minimal code for setting up Timer0 to
8. interrupt on compare match on channel 0 to interrupt at 100Hz XTALFREQ 12000000 X T AL frequency in Hz PCLKFREQ XTALFREQ 4 pclk must always be XTALFREQ 4 Open terminal I O window in debugger using View Terminal I O in C SPY to see VICVectAddr value in exception handler This is not routed to the serial port because UARTx is not configured and no implementation of putchar TK ok ok e sk oF SE ok SF oe ole sk oe leoi zk zk ole ak oR e oR oe oie 9 ok oe oe 2 oe a a ok oe ole 2 ok oR oR oj eoe SF include lt NXP iolpc2148 h gt include lt stdio h gt include lt intrinsics h gt include main ADC h unsigned int Speed int main void unsigned char buffer 32 VPBDIV bit VPBDIV 0 Init Peripherial divider Pclk Clk 4 TOIR OxFF reset match and capture event interrupts TOTC 0 Clear timer counter TOPR 0 No Prescaler 1000 Count up to 36 864 for 1000Hz interrupt period 1ms 3 Reset Timer Counter amp Interrupt on match TOTCR 1 Counting enable VICIntSelect 0 Set all VIC interrupts to IRQ for now VICIntEnClear OXFFFFFFFF Diasable all interrupts VICProtection 0 VIC registers can be accessed in User or privileged mode VICVectAddr 0 Clear interrupt VICProtection 0 Accesss VIC in USR PROTECT VICIntSelect amp 1 lt lt Timer 0 intrpt is an IRQ VIC TIMERO 4 VICVectAddr0 unsigned int amp irq han
9. msr Idr bic OIT msr 2 Idr bic orr msr Idr bic orr msr Idr r0 cpsr r0 70 7MODE MSK r0 r0 78SVC MODE cpsr_c r0 sp SFE SVC_STACK r0 r0 MODE MSK r0 r0 ABT_MODE cpsr_c r0 sp SFE ABT_ STACK r0 70 7MODE MSK r0 70 7UND MODE cpsr_c r0 sp SFE UND_STACK r0 70 7MODE MSK r0 r0 4FIQ MODE cpsr_c r0 sp SFE FIQ STACK r0 70 7MODE MSK r0 r0 4IRQ MODE cpsr_c r0 sp SFE IRQ STACK r0 70 7MODE MSK r0 r0 4SYS_ MODE cpsr_c r0 sp SFE CSTACK ARMVFP _ Enable the VFP coprocessor mov fmxr r0 0x40000000 fpexc r0 Original PSR value Clear the mode bits Set Supervisor mode bits Change the mode End of SVC STACK Clear the mode bits Set Abort mode bits Change the mode End of ABT STACK Clear the mode bits Set Undefined mode bits Change the mode End of UND STACK Clear the mode bits Set FIR mode bits Change the mode End of FIR STACK Clear the mode bits Set IRQ mode bits Change the mode End of IRQ STACK Clear the mode bits Set System mode bits Change the mode End of CSTACK Set EN bit in VFP FPEXC clear others Disable underflow exceptions by setting flush to zero mode For full IEEE 754 underflow compliance this code should be removed and the appropriate exception handler installed mov r0 0x01000000 Set FZ bit in VFP fmxr fpscr rO FPSCR clear others endif Add more i
10. to FIQ or IRQ interrupt Enable Register This register controls which of the 32 interrupt requests and software interrupts are enabled to contribute to FIQ or IRQ interrupt Enable Clear Register This register allows software to clear one or more bits In the Interrupt Enable register Software Interrupt Register The contents of this register are ORed with the 32 Interrupt requests trom various peripheral functions Software Interrupt Clear Register This register allows software to clear one or more 085 In the Software interrupt register Protection enable register This register aliows mlting access to the VIC registers by software running in privileged mode Vector Address Register When an IRQ Interrupt occurs the IRQ service routine can read this register and jump to the value read Default Vector Address Register This register the address of the Interrupt Service routine 158 for non vectored IRQs The main registers VicSoftInt register bits which correspond to the existing demand at the moment in terrupts VicSoftIntClear register reset VicSoftInt VicIntEnable register an individual permit prohibit interrupt VicIntEnClear register reset VicIntEnable VicIntSelect register selection anchor IRQ or FIQ for each interrupt RO RO RO RMI wo wo 0 0 0 0 0 0 0 0 OxFFFF FOCO FOOS Ox
11. 02 0004 02 0008 002 nnnc 002 01 Appendix Table E 1 The timer registers Generic Description Name IR Interrupt Register The IR be written to clear Interrupts The can be read to which of eight possible Inberrupt sources are pending TCR Timer Control Register The TCR used to control the Timer Counter functions The Timer Counter can be disabled reset Inrougn the TCR TC Timer Counter The 32 bit TC 15 Incremented every 1 cydes af PELE The TC le can ralled through ihe TCR PR Frescale Regisiter The Prescale Counter below 15 equal ta this value the next clack Increments the TC and Gears the PG Frescale Counter The 22 07 PG counter Is Incremarited to the value stored PRL When the value In PR is reached the TC Is Incremented and the cleared The ls abservable and contrallabie through the bus Interface MCR Match Control Register The MCR Is used control an Irterrupt Is generated and ihe TC is reset when Malch occurs MRD Match Register 2 MRD can be enabled through the MCR fo reset ine TC stop both the and FC andor generate an Intemupt every time MRO matches TC MRI Match Register 1 See MRD description MR Match Register 2 See MRD description MRS Match Register 3 See MRO description COR Capiure Control Register The CCR corrales which edges of the capture Inputs are used to load
12. 0403 OME000 305 TDEMR TIEMR 00 4070 000 8070 TDCTCR TICTCR The main registers X 0 or 1 depending on the timer ThTCR control register TxTC count register TxPR register prescaler TxMRO register containing the value at which the match interrupt is generated and the counter 15 reset TxMCR control register mode matching TxIR timer interrupt control register Appendix E Table F 1 ADC registers ADGDR ADSTAT ADGSR ADINTEN ADDR7 Control The ADCR register must be RN 0 0000 0001 oxe002 200 OxE006 0000 written to the operating mode before A D ADICR conversion can occur A D Global Data Register This register contains the RAN 003 2004 OxE006 0004 ADC s DONE bit and the result of tne most recent A D ADOGDR ADIGOR conwersion A D Status Register This register contains DONE and RO 0 0000 0000 OxE0034030 OxE006 0030 OVERRUN flags for all of the A D channels well as ADOSTAT AD1STAT the A D interrupt flag A D Global Start Register This address can be written WO 0 00 OxE003 4008 In the ADO address range to start conversions In both ADGSR converters simuitanecusly interrupt Enable Register This register contains RAN 0 0000 0100 OxE003400C OxE006 000C enable bits Tat allow the DONE flag of A D ADOINTEN ADITINTEN channel to be included or exciuded from contributing to the generation of an A D interrupt AD Channel 0 Data This re
13. 7TDMI S has 512 KB of FLASH memory 32KB SRAM as well as a rich set of peripherals Microcon trollers are equipped with in circuit programming system based on the JTAG inter face and a special boot loader that allows to download the program via UART De velopment tools include support for the C C use of which is considered in these guidelines Methodical instructions allow students to learn the basics of debugging boards to develop and debug programs microcontroller core ARM Guidance does not de scribe the features of the core ARM7TDMI LPC2148 microcontrollers NXP com pany or a development environment Embedded Workbench provides only brief comments necessary to understand the above code snippet the appendix contains fragments of circuit debug board a list of jobs for own work and sample programs 1 Overview of the debug board Evaluation Boards such as LPC2148 Education Boards firm Embedded Artists have in their composition apart from a microcontroller LCD display but tons joystick serial adapter speaker stepper motor LED matrix interface SPI tem perature sensor and potentiometer for working with ADC module jack FLASH card module and ZigBee Also on the board Figure 1 has all the necessary piping micro controller system power and clock and connectors for interface with a computer and external breadboard 990 SS 32444 2 2 09
14. End of UND STACK bic r0 70 2MODE MSK Clear the mode bits 10 0 8 1 0 MODE Set FIR mode bits msr cpsr c r Change the mode ldr sp SFE FIQ STACK End of FIR STACK bic r0 70 2MODE MSK Clear the mode bits or rO r0 ZIRO MODE Set IRQ mode bits msr cpsr c r Change the mode ldr sp SFE IRQ STACK End of IRQ STACK bic r0 70 2MODE MSK Clear the mode bits or 10 r0 4SYS_ MODE Set System mode bits msr cpsr c r Change the mode ldr sp SFE CSTACK End of CSTACK ifdef ARMVFP__ Enable the VFP coprocessor mov r0 0x40000000 Set EN bit in VFP fmxr fpexc r0 FPEXC clear others Disable underflow exceptions by setting flush to zero mode For full IEEE 754 underflow compliance this code should be removed and the appropriate exception handler installed mov 0 0 01000000 Set FZ bit in fmxr fpscr r0 FPSCR clear others endif Add more initialization here Continue to main for more IAR specific system startup ldr r0 main bx r0 END Appendix B Table 1 IO ports control registers IOXPIN Designed to read the state of pin IOXSET Recording 1 set high logic level at pin 0x00000000 IOXCLR Recording 1 set low logic level at pin RW 0 00000000 IOXDIR The direction of transmission Record E eed ing 1 configures the output mode to out put Appendix C Table 1 UARTO Registers P ini UIRSR Recelver Butter Register UTHR Hoking 8 bt Writ
15. FFFF F008 OxFFFF F00C OxFFFF F010 OxFFFF 14 OxFFFF F018 OxFFFF FOIC OxFFFF F020 OxFFFF F030 OxFFFF F034 Appendix G VicVectCntl0 15 slots Registers IRQ bit resolution and contain a number of slots for each of the 16 vector interrupt IRQ VicVectAddr0 15 Address registers vectors IRQ VicVectDefAddr address register handler nevektornogo IRQ VicVectAddr register containing the address of the treated IRQ VicProtection register to enable access to the registers of VIC Table G 2 Interrupt Sources TIMWER1 co 1 SSP PLL System Control Watchdog Interrupt WDINT Reserved for Sofware interupts only Embedded ICE DbgcommRx Embedded ICE bg commTX Match D 3 MRO MR MEO Capture 3 ORD CR1 Match D 3 MRO MET MEZ ME Capture 3 CRD CR1 Rx Line Status RLS Transmit Holding Reglster Empty THRE Rx Data Avallabie ROA Character Time oui Indicator Rx Lina Status RLS Transmit Holding Register Empty THRE Fix Data Avallable RDA Character Tima aut Indicator Modem Status Interrupt Match D 8 MRO MR ME ME MERE SI Stabe change SPI Interrupt Flag SPIF Made Fault TX FIFO at least empty TARIS Rx FIFO at least half ull RXRIS Receive Timeout condition TRIS averun RORRIS PLL Lock PLOCK Counter Increment RTCCIF Alarm RT
16. Flag int main void bl TimerFlag FALSE VPBDIV bit VPBDIV 0 Init Peripherial divider Pckl CIk 4 U0OFCR 0x07 Configure UARTO to 19200 baud 8 bit stop no parity UOLCR 0x83 Enable FIFOs whether used or not UOLCR 0X80 enable access to divisor latch bit necessary for setting baud rate Eight bits No panty One stop bit UODLL 0x0A UODLM 0 UOLCR amp 0x7F Disable access to divisor latch PINSELO 0x05 TOIR OxFF reset match and capture event interrupts TOTC 0 Clear timer counter TOPR 0 No Prescalar TOMRO PCLKFREQ 100 Count up to 36 864 for 100Hz interrupt period 10ms TOMCR 3 Reset Timer Counter amp Interrupt on match TOTCR 1 Counting enable hnitialize P0 14 to EINTI active falling edge EXTMODE 0x00000002 EINTI is edge sensitive EXTPOLAR 0x00000000 EINTI is falling edge sensitive PINSELO amp 0 30000000 PINSELO 0x20000000 EXTINT 0x00000002 reset EINTI IRQ flag VICIntSelect 0 Set all VIC interrupts to IRQ for now VICIntEnClear OxFFFFFFFF Diasable all interrupts VICProtection 0 VIC registers can be accessed in User or privileged mode VICVectAddr 0 Clear interrupt VICProtection 0 Accesss VIC in USR PROTECT VICIntSelect 0x00008000 EINTI interrupt is assigned to FIQ not IRQ VICIntSelect amp 1 lt lt TIMERO Timer 0 intrpt is an VIC TIMERO 4 VICVectA
17. GALF External Interrupt External Interrupt 1 EINT1 External Interrupt 2 2 External Interrupt 3 EINTS A D Converter T end of conversion SI Stabe change 12 14 15 16 17 18 19 0080 2100 D200 2400 0900 DxDDOD 1000 Ox0000 2000 0000 4000 cocan 8000 0001 0000 0002 0000 0004 0000 0 D000 Appendix H SS 28488880 pSesossass PYRO Y OLIM HG uhm 5 LE Figure Stepper motor schematics Figure H 4 Temperature sensor schematics 5 R21 ba L lt 1k LEDS e RED o R22 w C g 1k LEDS RED 5 jaf R26 w 1k LED7 RED 5 M R30 w L 1k LEDS RED R31 w 1k LEDS 2 RED R32 ba SWI L 1k LED10 FT PUSHBUTTONSMD RED E 270 R33 w La 1k LED11 J21 m 9 R34 1 LED12 Figure P0 14 button RED Figure H 7 LEDs L4 BLM21AG121SN1D N 68 2 m gt D D U32 8 1 5 8 d Sr E C72 5 100nF 5 GND 3ND D Figure H 8 Speaker schematics Educational edition Working with the Embedded Artists LPC2148 evaluation boards Learner s guide Compilers Ilya Kudryavtsev
18. ISPLAY 16 void SetCommLCD unsigned char bT void SetDataLCD unsigned char bT void WaitReadyLCD void void ShowMsgLCD unsigned char bT unsigned char const szT unsigned char szHi bDISPLAY 8 szLo bDISPLAY 8 unsigned char const Symbols 0x100 0x20 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 1 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 2 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 4 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 5 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 6 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0xC5 0x01 7 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 8 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 9 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0xA2 0xB5 0x20 0x20 0x20 0x20 0x20 0x02 0x20 0x20 0x20 0x20 0x20 0x20 0x20 0x20 B 0x41 0xA0 0x42 0x A 1 0xE0 0x45 0x A3 0xA4 0xA5 0x A6 0x4B 0xA7 0x4D 0x48 0x4F 0xA8 C 0x50 0x43 0x54 0xA9 0xAA 0x58 0xE1 0xAB 0xAC 0xE2 0xAD 0xAE 0xC4 0xAF 0xB0 0xB1 0
19. M configuration build and start program Using AINI potentiometer adjust motor rotation rate simultaneously looking at the LCD Try to determine rota tion rate analyzing the program and derive formula connecting the number on LCD with actual rotation rate Make the program to display rotational velocity 4 Tasks for your own work The complexity of tasks marked with asterisks 1 Using existing on board speaker and DAC module of the microcontroller cre ate audio frequency generator with a frequency change of command the computer is received via the UART 2 Using existing on board speaker and DAC module of the microcontroller cre ate audio frequency oscillator with frequency controlled potentiometer AIN2 3 Create a program that writes the data block of 100 bytes in the external EEP ROM via I2C 4 Create a program that depicts a snake crawling on dot matrix display in the direction of their choice the length of 6 pixels 5 Create a program that displays the current temperature using a sensor on the board on the LCD display 6 Create a program counter pressing P0 14 displaying decimal result on the LCD To provide for counter reset 7 Create a program unit that displays the decimal equivalent of the number re ceived by the RS 232 dot matrix display 8 Create a program of random numbers in the range 0 99 to display on the LCD display in decimal format by pressing the P0 14 9 Create
20. PAD rAnSoqid 2 2 Hardware DI AM sassa ase INVESTIGATION OF MCU S FEATURES u 6 31 Bus EOS tli Ct Gis 30 MAM docct pa d ate OTA Re Tnietrupt RR ka au au 3 508 DI Diode 8 cce omnta aoc 3 6 ADC Ico TASKS FOR YOUR OWN WORN 5 2 7 S u u 9 INTRODUCTION During the development of devices based on microcontrollers there are two in terdependent objectives the development of hardware and software creation In the process of development may change the program and circuit devices which presents certain difficulties and requires significant time and cost In order to facilitate the de velopment of widely used ready evaluation boards which set a microcontroller and a set of standard peripherals In this paper described the development board LPC2148 Education Boards from Embedded Artists LPC2148 microcontrollers are 32 bit RISC core with ARM
21. THE MINISTRY of EDUCATION and SCIENCE of RUSSIAN FEDERATION SAMARA STATE AEROSPACE UNIVERSITY Working with the Embedded Artists LPC2148 evaluation boards Learner s guide SAMARA 2011 Compilers Kudryavtsev Alexandrovich Kornilin Dmitry Vladimirovich Working with the Embedded Artists LPC2148 evaluation boards Embedded Artists LPC2148 Electronic resource Learner s guide The Ministry of Education and Science of Russian Federation Samara State Aerospace University compilers I A Kudryavtsev D V Kornilin Electronic text and graphic data 0 56 Mb Samara 2011 1 CD ROM Learner s guide describes the problems of creating and debugging programs in C C language for NXP ARM7 MCUs and using the evaluation boards LPC2148 Education Boards Learner s guide is developed in the Interuniversity Space Re search Department The learner s guide is intended for the students studying on the educational program 010900 68 Applied mathematics and physics on the discip line Radio complexes for flight monitoring and control of the micro nanosatellites in semester O Samara State Aerospace University 2011 CONTENTS INTRODUCTION visions dies aeu eur ud EUR UE eR n en 4 1 OVERVIEW OF THE DEBUG 4 2 COMPILE AND DEBUG PROGRAMS USING DEBUGGING TOOLS 5
22. d VICIntEnable 0x00008000 enable eintl interrupt VICIntEnable 1 lt lt enable Timer0 Interrupt enable interrupt Global interrupt enable while TRUE Foreground task if bl TimerFlag 1 TimerFlag FALSE Clear this flag if set by MM TIMERO ISR printf IRQ interrupt n sprintf char buffer Interrupt od Int Count LCDTextOut IRQ TEST buffer end foreground loop end main E Tk HE sk oR oF oR oF oe le oie ie sk oR oR oR fe SF ake oe sk oe le 2 ok oe k oR oR oR SR SR oe e 2 oie oe o she oe 9k k R e SR SR afe 2s fe E R Function Name fiq handler Parameters void Return void Description FIQ subroutine Note This is ARM mode code full 32 bit code TR sk se esie sie ak ak sk oe oe sk o oie ae sk oe ole 2 fe ak ak ak ak oe 2 oe SF extern C arm void fiq handler void printf FIQ interrupt n EXTINT 0x00000002 reset IRQ flag VICVectAddr 0x00 dummy write to VIC to signal end of interrupt j __irq arm void MM TIMERO ISR 1 static unsigned int us Ticks 0 us Ticks if us_Ticks TICKS SECOND bl TimerFlag TRUE The background task us Ticks 0 TOIR 1 Clear timer interrupt VICVectAddr 0 j 2 _startup S
23. d or partially enabled MAM 1 Init MAM before acsses to SRAM MAMCR DEFINE OxE01FCO00 MAM Control Register MAMTIM DEFINE 0xE01FC004 MAM Timing register ldr 10 4 ldr r1 2MAMTIM ldr 120 str 12 00 ldr 12 7 str 12 1 ldr 12 2 str 12 r0 Initialize the stack pointers The pattern below can be used for any of the exception stacks SVC UND SYS The USR mode uses same stack as SYS The stack segments must be defined in the linker command file and be declared above Mode correspords to bits 0 5 in CPSR MODE MSK DEFINE 0x1F USR MODE DEFINE 0x10 FIQ MODE DEFINE 0x11 IRQ MODE DEFINE 0x12 SVC MODE DEFINE 0x13 ABT MODE DEFINE 0x17 UND MODE DEFINE 0x1B SYS MODE DEFINE 0x1F Bit mask for mode bits in CPSR User mode Fast Interrupt Request mode Interrupt Request mode Supervisor mode Abort mode Undefined Instruction mode System mode mrs r cpsr Original PSR value bic r0 70 2MODE MSK Clear the mode bits or rO r0 75SVC MODE Set Supervisor mode bits msr cpsr c r Change the mode ldr 5 5 5 STACK End of SVC STACK bic r0 70 2MODE MSK Clear the mode bits 10 r0 4ABT_ MODE Set Abort mode bits msr cpsr c r Change the mode ldr sp SFE ABT STACK End of ABT STACK bic r0 70 2MODE MSK Clear the mode bits 10 r0 4UND_ MODE Set Undefined mode bits msr cpsr c r Change the mode ldr sp SFE UND STACK
24. ddr0 unsigned int amp irq handler Install ISR in VIC addr slot 0 VICVectCntl0 0x20 VIC TIMERO TRQ type TIMER 0 int enabled VICIntEnable 0x00008000 enable eintl interrupt VICIntEnable 1 lt lt enable TimerO Interrupt enable interrupt Global interrupt enable while TRUE Foreground task if bl TimerFlag 1 bl TimerFlag FALSE TransmitString IRQ Interrupt processed j end foreground loop end main ET HE S oR oF oF SF oe SF ake oie ie sk zk zk ak sk oe le 2 oe le 2 oie oe ole sk oe le 2 oe e ak ak oe le akk oe Function Name irq handler Parameters void Return void Description IRQ exception handler this will call appropriate isr after reading value out of VICVectAddr Note This is ARM mode code full 32 bit code T sk ok ok oR sie ak ak sk oe e sk a oe e ok o oie oR ok oe akk SF fe e e oe a fe 2k 9k 2k k ak ak R oR extern C void irq handler void static unsigned int us_count 0 us_count if us_count TICKS SECOND us count 0 bl TimerFlag TRUE VICVectAddr 0 Clear interrupt in VIC TOIR 1 E Tk sk sk k oF oR SF oe SF oe Ie ok sk zk zk sk oR oR oR fe SF SR oe oe ole sk oe le 2 oe ie 2k ok oe k oR oR oR SR oe oe oe a sk oe 9k ak R oR oR SR SR SF afe fe E K K Function Name
25. dler Install ISR in VIC addr slot 0 VICVectCntl0 0x20 VIC TIMERO TRQ type TIMER 0 int enabled VICIntEnable 1 lt lt enable TimerO Interrupt InitADC InitLCD 0 SetBacklight 1 LCDTextOut NXP LPC2148 ADC project IOODIR 0x0020FF00 Set P0 8 PO 15 P0 21 as outputs IOOSET 0x0020FF00 Clear PO 8 15 21 enable interrupt Global interrupt enable while TRUE 1 Speed 1023 ADCReadValue if Speed lt 23 Speed 23 sprintf char buffer Speed od_ 1023 Speed LCDTextOut NXP LPC2148 buffer Sleep 100 ET HR S ok oF oF SF SF ie sk sie ie oie sk oe ole sk zk zk sk k oR oR 2 oe SF SF oe oe oe sk oe le 2 oR oR SF SF SF ok oe e obe fe ae a oie oe oe R R oR ok SR e SF SF oe oe e 9k 9k R R ak ak ie Function Name handler Parameters void Return void Description IRQ exception handler this will call appropriate isr after reading value out of VICVectAddr Note This is ARM mode code full 32 bit code HE sk k oR 2 sk se oe sk oe e ok ae oie oie ok oe sk ok sje oR extern C arm void handler void const int A 12 1 1 0 0 1 1 0 0 1 1 0 0 const int 12 0 1 1 0 0 1 1 0 0 1 1 0 static unsigned int us Ticks n us Ticks if us_Ticks gt Speed us Ticks 0 if A n 0 IOOCLR 1 lt lt 21 else IOOSET 1 lt lt 21 if B n 0 IOOCLR 1 lt lt 12 else IOOSET 1 l
26. e Data 222000 DLAB 0 UODLL a Latch LSB 8 08 Data 000 DLAB 1 UQDLM Di4sorLalch MSS OxE000 Coos DLAB 1 UDIER interrupt Enable 5 EnABTO EnABEO RW 0 000 004 Register DLAB 0 Lin Stint THRE Int DaLAvint UIR intemupt ID Reg FIFOs Enabled I IR IRI IIRO UIFCR FIFO Control RX Trigger I TXFIFO RXFIFO FIFO 0 000 Register Reset Reset Enable UDLCR Control Sk Even Pall Noof Word Lengtn Select 0 000 Register Break Party ParSekt Enable Stop Sits UOLSR Une Status RXFIFO TEMT THRE BI FE PE DA Ox 000 014 Register 40508 Seraten Pad Reg fm RE EDI COC UDACR 0 000 C020 int Cr Mode UDFOR Fractional Divider Reserved 31 8 0 000 C025 Register Ure xewemg mi OO fr The formula for calculating the UART transmission rate PCLE 16 16 x VODLM UODIL 1 DivAdd The main registers UORSR register the received data UOTHR data register for transmission UOIER Interrupt Enable UART Bit 0 1 enable interrupt if the received data Bit 1 1 enable interrupt when buffer under the program Bit 2 1 enable interrupt when a particular state line RX UOLSR line control status register Configures the format make 3 UOLSR line status register Current status of the port err
27. fiq handler Parameters void Return void Description FIQ subroutine Note This is ARM mode code full 32 bit code TE sk ok eoe oe sk oe oe sk ake ie oi fe k oR oR oR ak sk e o ok oe a ok oe oie k extern C fiq arm void fiq handler void TransmitString FIQ interrupt EXTINT 0x00000002 VICVectAddr 0x00 dummy write to VIC to signal end of interrupt j void TransmitString char pStr while pStr 0 1 UOTHR pStr while UOLSR amp 0x40 pstr main SPI cpp include lt NXP iolpc2148 h gt include spi h int main void int Sleep int slp int main void int X 4 Y 4 InitSPI O while 1 switch IO0PIN amp 0 1 lt lt 16 gt gt 16 Read value from joystick 1 case OxID if Y lt 8 break Up case OxOF if Y gt 1 Y break Down case 0x17 if X gt 1 X break Left case 0 18 1 lt 8 X 4 break Right case 0x1D amp 0x17 if Y lt 8 amp X gt 1 Y X break UpLeft case OX1D amp Ox1B if Y lt 8 amp X lt 8 Y X break UpRight case OXOF amp 0x17 if Y gt 1 amp X gt 1 Y X break DownL eft case OXOF amp Ox1B if Y gt 1 amp X lt 8 Y X break DownRight default break SPIPutDot X Y Sleep 300 int Sleep int
28. gister contains the RO NA OxE003 2010 OxE006 0010 result of the most completed on ADODRO AD1 DR2 channel 0 A D Channel 1 Data Register This register contains the RO NA OxE003 4014 OxE006 0014 result of the most recent conversion completed on ADODR1 ADIDRt channel 1 AD Channel 2 Data Register This register contains the RO NA OxE003 4018 OxE006 0016 result of the most recent conversion completed on ADODR2 ADIDR2 channel 2 AD Channel 3 Data Register This register contains the RO NA OxE003 401C OxE006 001C result of the most recent conversion completed on ADODRS AD1DR23 channel 3 AD Channel 4 Data Register This register contains the RO NA 003 2020 OxE006 0020 result of the most recent conversion completed on ADODRA AD1DR4 channel 4 AD Channel 5 Data Register This register contains the RO NA OxE003 2024 OxE006 0024 result of the most recent conversion completed on ADODRS ADIDRS channel 5 A D Channel 6 Data Register This register contains tne RO NA OxE003 2028 OxE006 0026 result of the most recent conversion completed on ADODRE ADIDRE channel 6 A D Channel 7 Data Register This register contains the RO NA OxE003 402C OxE006 002C result of the most recent conversion completed on ADODRT AD1DR7 channel 7 The main registers ADCR control register ADGDR a register containing the result and the last bit of preparedness ADSTAT ADC status register all channels the result register of the channel Table E 2 Fo
29. he MAM operation 3 3 PLL module When PLL 15 not active MCU s clock frequency 15 equal to the frequency of quartz crystal unit To use maximum performance you need to set and activate PLL module This requires following procedure Store M and P coefficients in PLLCFG start PLL wait until capture is performed set PLL as a clock signal source for the MCU Remove main cpp file from the project click right mouse button on its name then select Remove from context menu and add main pll cpp file Select RAM configuration compile the project and start the program Compare LED blink ing period before and after P0 14 button pressing Determine frequency value of MCU when PLL is active 3 4 Interrupt system Remove main pllcpp and lcd cpp files from the project and add main VIC cpp and lpc2xxx_startup s instead The latter is a standard file in cluding start code of LPC2148 MCU This file is written in assembler language and is used for the initializing of interrupt vectors Usually developers use the copy of this file with necessary modifications File main VIC cpp describes interrupt handlers for IRQ and FIQ interrupts IRQ will be attached to timer 0 and FIQ will be attached to the external interrupt activating by P0 14 button press Details of VIC and timer operation are described in MCU datasheet placed in the same directory Set RAM configuration build and start program then open message window
30. id WaitReadyLCD void Sleep 1 void ShowMsgLCD unsigned char bT unsigned char const szT WaitReadyLCD SetCommLCD bT for int i 0 i lt bDISPLAY i if szT break WaitReadyLCD SetDataLCD Symbols szT void InitLCD void Sleep 20 SetCommLCD 0x30 Sleep 20 SetCommLCD 0x30 Sleep 20 SetCommLCD 0x30 WaitReadyLCD SetCommLCD 0x38 WaitReadyLCD SetCommLCD 0x08 WaitReadyLCD SetCommLCD 0x01 WaitReadyLCD SetCommLCD 0x06 WaitReadyLCD SetCommLCD 0x0C WaitReadyLCD SetCommLCD 0x40 WaitReadyLCD SetCommLCD 0xC4 void LCDTextOut unsigned char const top line unsigned char const bottom line ShowMsgLCD 0x80 top_line ShowMsgLCD 0xC0 bottom line WaitReadyLCD SetCommLCD 0xC4 void SetBacklight int Backlight if Backlight IOOSET 1 lt lt 30 else IOOCLR 1 lt lt 30 j main pll cpp include lt NXP iolpc2148 h gt include lt stdio h gt int main void void InitLCD void void SetBacklight int Backlight void LCDTextOut unsigned char const top line unsigned char const bottom line int Sleep int _ slp int main int LOW 1 InitLCD SetBacklight 1 LCDTextOut NXP LPC2148 Basic project IOODIR 0x0000FF00 Set P0 8 P0 15 as outputs IOOSET 0x0000FF00 Clear PO 8 P0 15 IOODIR am
31. k kK K K K KK k K K K K of of of oie K K K of ok ok of of K K of ok ok ok while ADCValue AD0DR amp 0x80000000 0 E T HE sk ok oR oR SF oF SF oe le sk oe ie oe sk ole ak 2 oe ake ake oe oe e sk p Separate ADC value from other information E T HE S k oF oF oe ole sk oe oie oe sk oe ak 2 oe e return ADCValue gt gt 6 amp 0x3FF main ADC h define XTALFREQ 12000000 XTAL frequency in Hz define PCLKFREQ XTALFREQ 4 pclk must always be XTALFREQ 4 define FALSE 0 define TRUE FALSE int main void void InitLCD void void SetBacklight int Backlight void LCDTextOut unsigned char const top line unsigned char const bottom line int Sleep int _ slp void InitADC void int ADCRead Value void extern _ arm void irq_handler void lpc2xxx_startup_no_fiq S 55555555555555555555555555 Part one of the system initialization code contains low level initialization Copyright 2006 IAR Systems All rights reserved 5 SRevision 30870 MODULE cstartup Forward declaration of sections SECTION IRQ STACK DATA NOROOT 3 SECTION FIQ STACK DATA NOROOT 3 SECTION ABT STACK DATA NOROOT 3 SECTION SVC
32. n start the program with the help of Debug Go or F5 Check the project operation 3 Investigation of MCU s features 3 1 Basic I O functions After the project is started you can see the words on LCD and LED blinking below LCD Using LCD means setting options of its controller and storing codes of necessary symbols in appropriate location The details of display s controller opera tion you can see in the datasheet which is placed in Samples subdirectory C language offers set of functions for the operation with text strings prototypes of such functions are described in STDIO H header file Detailed description you can find in the Samples subdirectory You can also use built in help system of Embed ded Workbench IDE This project demonstrates basic options of LPC2148 I O system with the help of LED blinking and button polling Development board has signatures showing which pins of the MCU are connected to the certain LED or button and you can find schematic file in the Doc subdirectory 3 2 MAM module MAM accelerates MCU s operation with FLASH memory with the help of preliminary instruction fetching The details of MAM operation are described in the manual The project demonstrates operation of MAM which is activated deactivated by the button connected to P0 14 pin Select Release configuration load the code into MCU s memory and start the program Pressing the button you can see performance changes caused by t
33. nitialization here Continue to main for more IAR specific system startup ldr bx r0 main r0 END main VIC UART cpp E T E Sk oR oF e sk oe le sk zk ie oie sk oR ole ake oe le SF oe oe e sk oe le 2 oe ie oie R oR oR ok akk ie oie ok Minimal code for setting up Timer0 to interrupt on compare match on channel 0 to interrupt at 100Hz XTALFREQ 12000000 X T AL frequency in Hz PCLKFREQ XTALFREQ 4 pclk must always be XTALFREQ 4 Open terminal I O window in debugger using View Terminal I O in C SPY to see VICVectAddr value in exception handler This is not routed to the serial port because UARTx is not configured and no implementation of putchar TK sk ok oF ak oF e ok sk se oe sk o eoi oj zk ole ak ok oR oR oe oie oe ok oe oe 2 ae oe oe 2 ok oR oR ake SF oe e ok oe e ae ok oe e 2 fe R oR oR oe oe SR oe 9 2 ae a a ak include lt NXP iolpc2148 h gt include lt stdio h gt include lt intrinsics h gt define TICKS PER SECOND 100 TIMERO interrupt is 100Hz define XTALFREQ 12000000 XTAL frequency in Hz define PCLKFREQ XTALFREQ A pclk must always be XTALFREQ 4 define FALSE 0 define TRUE FALSE int main void extern _ arm void fiq handler void extern C 19 arm void handler void void TransmitString char pStr bool bl Timer
34. nst bottom_line extern _ fiq _ arm void fiq handler void irq arm void MM TIMERO ISR unsigned int Int Count unsigned char buffer 16 bool bl TimerFlag int main void Int Count 0 InitLCD SetBacklight 1 bl TimerFlag FALSE VPBDIV bit VPBDIV 0 Init Peripherial divider Pckl 4 TOIR OxFF reset match and capture event interrupts TOTC 0 Clear timer counter TOPR 0 No Prescalar TOMRO PCLKFREQ 100 Count up to 36 864 for 100Hz interrupt period 10ms TOMCR 3 Reset Timer Counter amp Interrupt on match TOTCR 1 Counting enable hnitialze P0 14 to EINTI active falling edge EXTMODE 0x00000002 EINTI is edge sensitive EXTPOLAR 0x00000000 EINTI is falling edge sensitive PINSELO amp 0x30000000 PINSELO 0x20000000 EXTINT 0x00000002 reset EINTI IRQ flag VICIntSelect 0 Set all VIC interrupts to IRQ for now VICIntEnClear OxFFFFFFFF Diasable all interrupts VICProtection 0 VIC registers can be accessed in User or privileged mode VICVectAddr 0 Clear interrupt VICProtection 0 Accesss VIC in USR PROTECT VICIntSelect 0x00008000 EINTI interrupt is assigned to FIQ not IRQ VICIntSelect amp 1 lt lt Timer 0 intrpt is an IRQ VIC TIMERO 4 VICVectAddr0 unsigned int amp MM_TIMERO_ISR Install ISR in VIC addr slot 0 VICVectCntl0 0x20 VIC TIMERO type TIMER 0 int enable
35. or SCK CPOL o A J vA wa N V VY VY VY VY V W SSEL 0 0 X 1 X 2 X X X s X X 7 YX X J vosi cra S2 rs ara Yars X ars X r ETEK ca o ETT STEN ETX Siri BEY BITTY BTS 1 X t AZ AGASASASAT ASA MOSI CPHA 1 wso cera i AETIA ETAN ETX eme X rr Cara Figure C 1 Formats the transfer module in SPI Table D 1 SPI module registers Description Access Reset S05PCR X SP Control Register This register controls the FW 0x00 operation of the SPI S USPSR SA Status Register This register shows the RO 000 status of the SPI SUSPDR SP Data Register This bi directional register Fu 0x00 provedes the transmit and receive data for the SP Transmit data is provided to the SPIO by writing to this register Data received by the SPIO can be read from this register SOSPCCR SR Clock Counter Register This register RN i00 controls the frequency of a master s SCKO_ SOSPINT SP interrupt Flag This register contains the RN 0x00 interrupt flag for the SP1 interface The most important registers are SOSPCR control register the format detailed in 3 SOSPSR status register reflects the current state error SOSPDR register containing the transmitted and received data SOSPCCR register control the frequency transmit mode MASTER Address 002 0000 0 0
36. p OxFFFFBFFF P0 14 input int i 8 while 1 IOOCLR 1 lt lt i shift LEDs Sleep 200 IOOSET 1 lt lt i Sleep 200 if i 14 i 8 if IOOPIN amp 0x00004000 0 if LOW 1 PLLCFG 0x45 M 5 P 2 PLLCON 0x01 PLL Enable PLLFEED 0xAA Feed Sequence PLLFEED 0x55 Feed Sequence 2 while PLLSTAT amp 0x0400 0 Wait for PLL Lock PLLCON 0x03 PLL Enable amp Connect PLLFEED 0xAA Feed Sequence PLLFEED 0x55 Feed Sequence 2 LOW 0 j else if LOW 0 PLLCFG 0x23 M 3 P 1 PLLCON 0x01 PLL Enable PLLFEED 0xAA Feed Sequence PLLFEED 0x55 Feed Sequence 2 while PLLSTAT amp 0x0400 0 Wait for PLL Lock PLLCON 0x03 PLL Enable amp Connect PLLFEED 0xAA Feed Sequence PLLFEED 0x55 Feed Sequence 2 LOW 1 VIC cpp include lt NXP iolpc2148 h gt include lt stdio h gt include lt intrinsics h gt define XTALFREQ 12000000 XTAL frequency in Hz define PCLKFREQ XTALFREQ 4 pclk must always be XTALFREQ 4 define TICKS PER SECOND 20 TIMERO interrupt is 100Hz define FALSE 0 define TRUE FALSE int main void void InitLCD void void SetBacklight int Backlight int Sleep int _ slp void LCDTextOut unsigned char const top_line unsigned char co
37. p y After a reser execution starts here the mode is ARM supervisor with interrupts disabled SECTION text CODE NOROOT 2 PUBLIC cstartup EXTERN main REQUIRE vector ARM jar program start cstartup 9 Add initialization needed before setup of stackpointers here LPC2148 Errata Date August 5 2005 Document Release Version 1 0 Device Affected LPC2148 Incorrect read of data from SRAM after Reset and MAM is not enabled or partially enabled 1 Init MAM before acsses to SRAM MAMCR DEFINE OxE01FCO00 MAM Control Register MAMTIM DEFINE 0xE01FC004 MAM Timing register ldr r0 MAMCR ldr r1 2MAMTIM ldr 120 str 12 00 ldr 12 7 str 12 1 ldr 122 str 12 r0 Initialize the stack pointers The pattern below can be used for any of the exception stacks FIQ IRQ SVC ABT UND SYS The USR mode uses the same stack as SYS The stack segments must be defined in the linker command file and be declared above Mode correspords to bits 0 5 in CPSR MODE MSK DEFINE 0x1F Bit mask for mode bits in CPSR USR MODE DEFINE 0x10 User mode MODE DEFINE 0x11 Fast Interrupt Request mode IRQ MODE DEFINE 0x12 Interrupt Request mode SVC_MODE DEFINE 0x13 Supervisor mode ABT MODE DEFINE 0x17 Abort mode UND_MODE DEFINE 0x1B Undefined Instruction mode SYS MODE DEFINE 0x1F System mode mrs bic orr msr Idr bic orr msr Idr bic orr
38. rmat Registry DACR 0xE006C000 DAC control 3137 Reserved user sofware should nat write ares ta reserved bits The value read Tram a reserved bit is not defined After the selected time after this Is writen wit a 0 new VALUE the voltage an the A pin with respect 1p Vasa VALLIEHD24 Vie current ie 700 28 The sewing time af tne DAC ls 1 us max and ipe maximum 0 1 The setting time af the DAC ls 2 5 us and the maximum current is 350 Reserved user sofware should nat write ones ta reserved bits The value read Tram a reserved bit is not defined To activate the DAC to set bits 19 18 in the state register PINSEL1 10 Appendix F Table G 1 interrupt controller registers VICIRQStatus VICFIQStatus ViCRawintr VICIntSeiect VICIn Enable VICIntEnCir vicSottint VICSoflintCiear ViCProtection vicvectAdar VicDefvectAcdr Description IRQ Status Register This register reads out the state of those Interrupt requests that are enabled and classified as IRQ FIQ Status Requests This register reads out tne state of Interrupt requests that enabled and classified as FIQ Raw interrupt Status Register This register reads out the state of the 32 Interrupt requests software interrupts regardiess of enabilng or classification interrupt Select Register This register classifies each of the 32 Interrupt requests as contributing
39. t lt 12 if n gt 11 n 0 TOIR 1 Clear timer interrupt VICVectAddr 0 Clear interrupt in VIC include lt NXP iolpc2148 h gt void InitADC void oR oF oF Connect PIN connect block to ADC0 1 E T HE sk ok oF oF 2 oR oR SR SF 2 PINSELI 1 lt lt 24 E T HE Sl k oF oF Configure ADC EF K k k ak ak ak ak ake ake ake ake e ake e a a ae ak ak ak ak ak ak ake ake ake afe ake sfe ake e ke ae a ae ae ae ake ak ak ak akk akk akk afe ake afe afe fe e ale a 2k ADOCR 1 lt lt 1 Select ADC0 1 channel is active 4 lt lt 8 Set Clock divider 1 lt lt 16 Set BURST 0 lt lt 17 Set ADC resolution 1 21 Power on ADC 1 lt lt 24 Start conversion now int ADCRead Value void int ADCValue ET sk S ok oR oR oF oF SF he ie oie sk oe ole ok oe zk zk sk ok oR oR fe SF 2 oe oe ole sk oe oe 2 a e oe oko oe ak R oR he oR SR SF K p Read value from ADC KK E K K k k k k k k k kK k k k k k K k k k K K K
40. the Capture Registers and wne er or nat an interrupt I generated when a caplure taies place CRO Capture Register CRO ts loaded with the value of when there Is evenit an the CAP D CAPD or CAP1 0 respectively Input Capture Register 1 See CRO description CR2 Capture Register 2 See CRO description Capture Register 3 See CRO description EMIR External Match Register The controls external match pins MATn B 3 2 3 and MAT 1 0 3 respectively Count Cont Regisiter The CTCR select between Timer and Counter mode and In Counter mode selecis Ine signal and edges for counting Access Reset TIMERS RAN RAW RW 111 RAN R R R R RAN RAW TIMERI Address amp Nama Address amp Nama 2000 DxEnon 8000 4004 DxEDO0 8004 TITER TITER 2008 DxEDO0 8008 TOTS TITC 400C OXE000 00 TIPR TIPR DxEDOD 4010 0 000 8010 TeC 1 0004014 000 8014 TUMCR TIMCR DxEDOD 2018 DxEDOD 8018 TIMRO TIMRO OMEN 401C E000 3U1C TIMR1 2020 0 000 8020 TDMR2 TIMR2 082000 2024 0 000 8024 TOMR3 TIMR3 2028 DxEDO0 8028 TDCCR TICCR DxEDOD 402C DxEDOD 802 TICRD 4030 DxEDO0 8050 TDCR1 TICR1 4054 DxEDO0 8034 TUCR2 TICR2 DxEDOQ 4038 0 000 8038 TUCR3 TICR3 82 00
41. x61 0xB2 0xB3 0xB4 0xE3 0x65 0xB6 0xB7 0xB8 0xB9 0xXBA 0xBB OxBC OxBD Ox6F OxBE 0x70 0x63 0xBF 0x79 0xE4 0x78 0xE5 0xC0 0xC1 0xE6 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 F int Sleep int _slp int j for inti 0 1 1000 i j i 1 return j void SetCommLCD unsigned char bT IOIDIR OxFF lt lt 16 Set data bus as outputs IOIDIR 1 lt lt 24 Set RS as output IOIDIR 1 lt lt 25 Set E as output IOODIR 1 lt lt 30 Set Backlight control as output IOODIR 1 lt lt 22 Set R W as output IOICLR 1 lt lt 25 E down IOICLR 1 lt lt 24 RS 0 IOOCLR 1 lt lt 22 RW 0 IOICLR OxFF lt lt 16 Clear data bus bT lt lt 16 Write data to bus IOISET 1 lt lt 25 Eup Sleep 10 Wait IOICLR 1 lt lt 25 E down void SetDataLCD unsigned char bT IOIDIR OxFF lt lt 16 Set data bus as outputs IOIDIR 1 lt lt 24 Set RS as output IOIDIR 1 lt lt 25 Set E as output IOODIR 1 lt lt 30 Set Backlight control as output IOODIR 1 lt lt 22 Set R W as output IOICLR 1 lt lt 25 E down IOISET 1 lt lt 24 8 1 IO0CLR 1 lt lt 22 RW 0 IOICLR OxFF lt lt 16 Clear data bus bT lt lt 16 Write data to bus IOISET 1 lt lt 25 Eup Sleep 10 Wait IOICLR 1 lt lt 25 E down vo
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