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Datasheet - NXP Semiconductors

1. Fig 37 TSSOP20 package outline SOT360 1 P89LPC92X1 All information provided in this document is subject to legal disclaimers Product data sheet Rev 2 1 27 August 2012 NXP B V 2012 All rights reserved 68 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 DIP20 plastic dual in line package 20 leads 300 mil seating plane in 1 index we scale DIMENSIONS inch dimensions are derived from the original mm dimensions 8 bit microcontroller with 8 bit ADC SOT146 1 UNIT A max A1 min A2 max b bi c p p 4 2 0 51 3 2 26 92 26 54 6 40 6 22 inches 0 17 0 02 0 13 1 060 1 045 0 25 0 24 Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included OUTLINE VERSION REFERENCES JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT146 1 MS 001 SC 603 cgo 99 12 27 03 02 13 Fig 38 DIP20 package outline SOT146 1 P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 69 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 14 Abbreviations 8 bit microcontr
2. SCL P1 3 SDA P1 2 SCL OTHER DEVICE OTHER DEVICE P89LPC9201 9211 WITH C BUS WITH PPC BUS 922A1 9241 9251 INTERFACE INTERFACE 002aae430 Fig 11 I C bus configuration All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 39 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 8 bit microcontroller with 8 bit ADC 8 Ny INPUT FILTER P1 3 SDA OUTPUT STAGE BIT COUNTER ARBITRATION 4 CCLK 2 INPUT AND SYNC LOGIC TIMING em FILTER AND z NTROL Z P1 2 SCL us th SERIAL CLOCK i iz OUTPUT interrupt z timer 1 EE overflow P1 2 I2CON CONTROL REGISTERS AND I2SCLH SCL DUTY CYCLE REGISTERS I2SCLL STATUS status bus DECODER I2STAT STATUS REGISTER a 002aaa899 Fig 12 1 C bus serial interface block diagram 7 24 Analog comparators Two analog comparators are provided on the P89LPC9201 9211 922A1 9241 9251 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logical one which may be read in a register and or routed to a pin when the positive input one of two selectable inputs is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to ca
3. Voo V Central frequency of internal RC oscillator 7 3728 MHz Fig 25 Average internal RC oscillator frequency vs Vpp at 25 C 002aae346 0 2 frequency deviation 0 1 Vpp V Note Central frequency of internal RC oscillator 7 3728 MHz Fig 26 Average internal RC oscillator frequency vs Vpp at 40 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 58 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 P89LPC92X1 8 bit microcontroller with 8 bit ADC 002aae347 0 2 frequency deviation 0 Voo V Central frequency of internal RC oscillator 7 3728 MHz Fig 27 Average internal RC oscillator frequency vs Vpp at 85 C 002aae348 2 5 frequency deviation 1 5 0 5 1 5 2 4 2 8 3 2 3 6 Vpp V Central frequency of watchdog oscillator 400 kHz Fig 28 Average watchdog oscillator frequency vs Vpp at 25 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 59 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 P89LPC92X1
4. 36 3 Ordering information sess 3 7 20 1 Mode sies ERPEEEEY E be xA ed 36 34 Orderi ti 3 7 20 2 Mode iens ne Red manuia ii 36 i TOGT OPONSE E T3035 Mods ciccncenes eie Xe peut tre sue at 36 4 Block diagram sees 4 7204 M ded store vere recor oett bet 36 5 Functional diagram 6 7 20 5 Mode 6 oss cs cix dace eigen ctos 36 6 Pinning information 7 7 20 6 Timer overflow toggle output 37 6 1 PUDE socie cades ardere beanies opue 7 72 RTO system timer 0322 02 es ser errevwed 37 6 2 Pin description c 2422 20 2 cere ene 9 7 22 UART 1 6 eee ee ee eee eee 37 7 Functional description 12 7 22 1 Mode Qa Fenice Re te ERES 37 7 22 2 Mode Foes gtd dgellmme eene 37 7 1 Special function registers 12 7 22 3 Mode 2 odors cues ERR ae enema cama 37 7 2 Enhanced CPU 000 eee eee 26 7 22 4 Mode 3 usi xen D RPRVS 38 7 3 GlockKs iei RUE bie eset end 26 7225 Baud rai t d selecti 38 7 3 4 Clockdefinitions 0 0 0020 ee BB ae ae a Pria rae S 7 32 CPU clock OSCCLK sssssssss 26 e saa eek RC 7 22 7 Break detect 200 cee 38 7 4 Crystal oscillator option 26 7 22 8 Double buffering 04 38 7 4 1 Low speed oscillator option 26 ub 7 22 9 Transmit interrupts with double buffering 7 4 2 Medium speed oscillator option
5. 26 enabled modes 1 2 and3 39 7 4 8 High speed oscillator option 26 BH IRE DT 7 22 10 The 9 bit bit 8 in double buffering 7 5 Clock output 2 2 20 eee eee 27 modes 1 2 and 3 39 7 6 On chip RC oscillator option 27 2 en 7 23 I C bus serial interface 39 7 7 Watchdog oscillator option 27 7 24 Analog comparators 0 40 7 8 External clock input option 27 A 7 24 1 Internal reference voltage 41 7 9 Clock sources switch on the fly 27 A 7 24 2 Comparator interrupt 00 41 7 10 CCLK wake up delay sues 28 7243 Comparstorsnd power reduction modes 41 7 11 CCLK modification DIVM register 28 ee Vul p p P 7 12 Low power select llseslsessss 28 EA 0 OREL A EY Posey ee f ea eG Ave ane 7 26 Watchdog timer 0 00 42 7 13 Memory organization 29 oe 7 27 Additional features 0 43 7 14 Data RAM arrangement 29 7 27 1 Software reset 000 cece eaee 43 7 15 Interrupts ccr Poe ie eee ee is 29 t 7 27 2 Dual data pointers 0 43 7 15 1 External interrupt inputs 30 7 28 Flash program memory Lus 43 7 16 l O BOflS 2e emere ba HM bcd 32 7284 General description 43 7 16 1 Port configurations
6. ms P89LPC9201 9211 922A1 9241 pus 9251 8 bit microcontroller with accelerated two clock 80C51 core 2 kB 4 kB 8 kB 3 V byte erasable flash with 8 bit ADC Rev 2 1 27 August 2012 Product data sheet 1 General description The P89LPC9201 9211 922A1 9241 9251 is a single chip microcontroller available in low cost packages based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the device in order to reduce component count board space and system cost 2 Features and benefits 2 1 Principal features E 2kB 4 kB 8 kB byte erasable flash code memory organized into 1 kB sectors and 64 byte pages Single byte erasing allows any byte s to be used as non volatile data storage W 256 byte RAM data memory E 4 input multiplexed 8 bit ADC single DAC output P89LPC9241 9251 Two analog comparators with selectable inputs and reference source B On chip temperature sensor integrated with ADC module P89LPC9241 9251 W Two 16 bit counter timers each may be configured to toggle a port output upon timer overflow or to become a PWM output E A 23 bit system timer that can also be used as real time clock consisting of a 7 bit prescaler and a programmable and readable 16 bit timer B Enhanced UART with a fractional baud rate generator break detect framing
7. Dual channel continuous conversion mode Single step mode Three conversion start modes Timer triggered start Start immediately Edge triggered 8 bit conversion time of 21 61 us at an A D clock of 8 0 MHz Interrupt or polled operation Boundary limits interrupt DAC output to a port pin with high output impedance Clock divider Power down mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 47 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 8 3 Block diagram input MUX x Anin00 comp Anin01 gt 2 1 MUX Anin02 aa 1 Anin03 T SAR Vret bg Vsen CONTROL LOGIC input MUX Anin10 AD10 AD11 AD12 AD13 Anin13 002aae432 Fig 15 ADC block diagram 8 4 Temperature sensor An on chip wide temperature range temperature sensor is integrated It provides temperature sensing capability of 40 C 85 C ADCO is dedicated for the temperature sensor and the temperature sensor is measured through Anin03 To get an accurate temperature value it is necessary to get supply voltage by measuring the internal reference voltage Vret og first Please see the P89LPC9201 9211 922A 1 924 1 9251 User manual for detailed usage of temperature sensor 8 5 ADC operating modes 8 5 1 Fixed channel
8. 254 253 252 code out 1LSB ideal Lu 1 2 3 4 5 6 7 i 253 254 255 256 Via LSB offset error IA LSBigea Eo VppA V 1 LSB PPA SSA 256 002aae372 1 Example of an actual transfer curve 2 The ideal transfer curve Fig 36 ADC characteristics P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 67 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 13 Package outline TSSOP20 plastic thin shrink small outline package 20 leads body width 4 4 mm SOT360 1 4 detail X DIMENSIONS mm are the original dimensions UNIT Ay A2 Ag bp c pM E2 mm 0 15 0 95 0 30 02 6 6 4 5 0 05 0 80 0 19 0 1 6 4 4 3 Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic interlead protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION ISSUE DATE IEC JEDEC JEITA PROJECTION SOT360 1 MO 153 t I ce
9. pemasa suu Ily ZLOZ 8 dXN Table 6 indicates SFRs that are bit addressable Special function registers P89LPC9241 9251 Name ACC ADCONO ADCON1 ADINS ADMODA ADMODB ADOBH ADOBL ADODATO ADODAT1 ADODAT2 ADODAT3 AD1BH AD1BL AD1DATO Description SFR addr Bit address Accumulator EOH A D control 8bEH register 0 A D control 97H register 1 A D input A3H select A D mode COH register A A D mode A1H register B A D 0O BBH boundary high register A D O A6H boundary low register A D O0 data C5H register 0 A D O0 data C6H register 1 A D 0 data C7H register 2 A D O0 data F4H register 3 A D_0O C4H boundary high register A D_0O BCH boundary low register A D_0 data D5H register 0 Bit functions and addresses Reset value MSB E7 ENBIO ENBI1 AIN13 BNDI1 CLK2 E6 ENADCIO ENADCI1 AIN12 BURST1 CLK1 E5 TMMO TMM1 AIN11 SCC1 CLKO E4 EDGEO EDGE1 AIN10 SCAN1 INBNDO E3 ADCIO ADCI1 AINO3 BNDIO ENDAC1 E2 ENADCO ENADC1 AINO2 BURSTO ENDACO E1 ADCS01 ADCS11 AINO1 SCCO BSA1 LSB EO ADCSO00 ADCS10 AINOO SCANO BSAO Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 000x 0000 FF 1111 1111 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 FF 111
10. 8 bit microcontroller with 8 bit ADC 002aae349 0 5 frequency deviation 0 5 1 5 24 2 8 3 2 3 6 Vpp V Central frequency of watchdog oscillator 400 kHz Fig 29 Average watchdog oscillator frequency vs Vpp at 40 C 002aae350 1 5 frequency deviation 0 5 1 5 24 2 8 3 2 3 6 Vpp V Central frequency of watchdog oscillator 400 kHz Fig 30 Average watchdog oscillator frequency vs Vpp at 85 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 60 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 10 3 BOD characteristics Table 13 BOD static characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit BOD interrupt Vtrip trip voltage falling stage BOICFG1 BOICFGO 01 2 25 2 55 V BOICFG1 BOICFGO 10 2 60 2 80 V BOICFG1 BOICFGO 11 3 10 3 40 V rising stage BOICFG1 BOICFGO 01 2 30 2 60 V BOICFG1 BOICFGO 10 2 70 2 90 V BOICFG1 BOICFGO 11 3 15 3 45 V BOD reset Virip trip voltage falling stage BOE1 BOEO 01 2 10 2 30 V BOE1 BOEO 10 2
11. unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified All limits valid for an external source impedance of less than 10 kQ Symbol Parameter Conditions Min Typ Max Unit VDDA ADO ADC analog supply voltage V Vssa analog ground voltage V ViA analog input voltage Vss 0 2 Vpp 0 2 V Cia analog input capacitance 15 pF Ep differential linearity error s 5 1 LSB EL adi integral non linearity 1 LSB Eo offset error 2 LSB Ec gain error 1 96 Euttot total unadjusted error 2 LSB Mctc channel to channel matching 1 LSB C ct port crosstalk between port inputs 0 kHz to 100 kHz 60 dB SRin input slew rate 100 V ms Tey ADC ADC clock cycle time 111 2000 ns tADC ADC conversion time ADC enabled i3To Apc uS Temperature sensor Vsen sensor voltage Tamb 0 C 890 mV TC temperature coefficient 11 3 mvV C tstartup start up time 200 us start trigger adc clk 1 2 3 4 5 6 7 8 9 10 11 12 13 clk ia o Y Y os X o X s X o Yor Ao ADCDATA REG 002aae371 Fig 35 ADC conversion timing P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 66 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC offset gain error error Eo EG 255
12. 0000 low FMADRH Program flash E7H 00 0000 0000 address high FMADRL Program flash E6H 00 0000 0000 address low 40 9npuooliul9S dXN LGc6 Lt66 FLV666 LE66 L0c60d 168d DAV HO 8 YUM 19 01 UODOISIW 319 8 Jays Lep 19npoJd eL0z 1snDny ZZ L Z ed sieuirejosip eba 0 joefqns s jueuunoop S14 ui pepi oid uoneuuojul Iv 8210 pL LXe60d 68d pamasa suu Iv ZLOZ 5h 8 dXN Table 4 Special function registers P89LPC9201 9211 922A1 indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary FMCON Program flash E4H BUSY HVA HVE SV Ol 70 0111 0000 control Read Program flash E4H FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD O control Write FMDATA Program flash 5H 00 0000 0000 data I2ADR I C bus slave DBH I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR O GC 00 0000 0000 address register Bitaddress DF DE DD DC DB DA D9 D8 I2CON I2C bus control D8H I2EN STA STO SI AA CRSEL 00 x000 00x0 register I2DAT I C bus data DAH register I2SCLH Serial clock DDH 00 0000 0000 generator SCL duty cycle register high I2SCLL Serial clock DCH 00 0000 0000 generator SCL duty cycle register low I2STAT I2C bus status D9H STA 4 STA 3 STA 2 STA 1 STA 0 0 0 0 F8 1111 1000 register Bit address AF AE AD AC AB AA A9 A8 IENO Interrupt A8H EA EWDRT EBO ES ESR ET1 EX1 ETO EXO 00 0000 0000 enable 0 Bit
13. 1 CIN2B s CO eT CMP2 P0 0 2 i E OE2 Fig 13 Comparator input and output connections 002aae433 7 24 1 7 24 2 7 24 3 P89LPC92X1 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used The value of the internal reference voltage referred to as Vret bg is 1 23 V 10 Comparator interrupt Each comparator has an interrupt flag contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector If both comparators enable interrupts after entering the interrupt service routine the user needs to read the flags to determine which comparator caused the interrupt Comparators and power reduction modes Either or both comparators may remain enabled when Power down or Idle mode is activated but both comparators are disabled automatically in Total Power down mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 41 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 25 7 26 P89LPC92X1 8 bit microcontroller with 8 bit ADC If a comparator interrupt is enabled except in Total Power down mo
14. 1 q 8 YPM 19 01 UOTOISIW 1Iq 8 SJOJONPUODIWIIS dXN LGc6 Lt66 FV666 EE66 L0c60d 168d Jays Lep 19npoJd eL0z isnbny ZZ L z ed sieuirejosip eba 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y 8410 Ic LXe60d 68d pamasa suu Iv ZLOZ 5h 8 dXN Table 6 indicates SFRs that are bit addressable Special function registers P89LPC9241 9251 continued Name FMADRH FMADRL FMCON FMDATA I2ADR I2CON I2DAT I2SCLH I2SCLL I2STAT IENO IEN1 Description SFR addr Program flash E7H address high Program flash EGH address low Program flash E4H control Read Program flash E4H control Write Program flash E5H data I2C bus slave DBH address register Bit address I2C bus control D8H register I C bus data DAH register Serial clock DDH generator SCL duty cycle register high Serial clock DCH generator SCL duty cycle register low I2C bus status D9H register Bit address Interrupt A8H enable 0 Bit address Interrupt E8H enable 1 Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 BUSY HVA HVE SV Ol 70 0111 0000 FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD O 00 0000 0000 I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR O GC 00 0000 0000 DF DE DD DC DB DA D9 D8 I2EN STA STO SI AA CRSEL 00 x000 00x0 00 0000 0000 00 0000 0000 STA 4 STA 3 STA 2 STA 1 STA O 0 0
15. 1 q 8 YUM 19 01 UODOISIW 319 8 SJOJONPUODIWIIS dXN LS26 L7 c6 LVcc6 L C6 LOC60d 168d Jays Lep 19npoJd eL0z isnbny ZZ L Z ed sieuirejosip ea 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y 8210 8L LXe60d 68d pe iese suu Ily ZLOZ 5 8 dXN Table 5 Extended special function registers PS9LPC9201 9211 922A1l11 Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary BODCFG BOD FFC8H BOICFG1 BOICFGO El configuration register CLKCON CLOCK Control FFDEH CLKOK XTALWD CLKDBL FOSC2 FOSC1 FOSCO B register RTCDATH Real time clock FFBFH 00 0000 0000 data register high RTCDATL Real time clock FFBEH 00 0000 0000 data register low 1 Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX DPTR A instructions are used to access these extended SFRs 2 The BOICFG1 0 will be copied from UCFG1 5 and UCFG1 3 when power on reset 3 CLKCON register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 DAV 1 q 8 YUM 19 01 UODOISIW 1q 8 SJOJONPUODIWIIS dXN LGc6 Lt66 FV666 LE66 L06c60d 168d Jeaus Lep jonpoJd eL0z 1snDny ZZ L Z ed sieuirejosip ea 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y GZ 40 6L X 60d 168d
16. 2012 74 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 8 1 General description illus 46 8 2 Features and benefits 47 8 3 Block diagram 00 e eee eee eee 48 8 4 Temperature sensor 48 8 5 ADC operating modes 48 8 5 1 Fixed channel single conversion mode 48 8 5 2 Fixed channel continuous conversion mode 48 8 5 3 Auto scan single conversion mode 49 8 5 4 Auto scan continuous conversion mode 49 8 5 5 Dual channel continuous conversion mode 49 8 5 6 Single step mode uuluslusue 49 8 6 Conversion start modes 49 8 6 1 Timer triggered start 0 49 8 6 2 Start immediately 0 0 000 5 49 8 6 3 Edge triggered 2 2 4 49 8 7 Boundary limits interrupt 50 8 8 DAC output to a port pin with high output impedance 0000s carassin 50 8 9 Clock divider 2000e eee eeee 50 8 10 Power down and Idle mode 50 9 Limiting values 0000 cece eee 51 10 Static characteristics 52 10 1 Current characteristics 54 10 2 Internal RC watchdog oscillator characteristicS 000 00000 58 10 3 BOD characteristics 61 11 Dynamic characteristics 62 11 1 Waveforms 0 000 eee ee eee 6
17. 25 2 55 V BOE1 BOEO 11 2 80 3 20 V rising stage BOE1 BOEO 01 2 20 2 40 V BOE1 BOEO 10 2 30 2 60 V BOE1 BOEO 11 2 90 3 30 V BOD EEPROM FLASH Vtrip trip voltage falling stage 2 25 2 55 V rising stage 2 30 2 60 V 1 Typical ratings are not guaranteed The values listed are at room temperature 3 V VDD Vtrip BOF BOIF BOF BOIF can be set by hardware I i E cleared in software i i BOF BOIF EC 002aae352 Fig 31 BOD interrupt reset characteristics P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 61 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 11 Dynamic characteristics 8 bit microcontroller with 8 bit ADC Table 14 Dynamic characteristics 12 MHz Vpp 2 4 V to 3 6 V unless otherwise specified Tamp 40 C to 85 C for industrial applications unless otherwise specified 11l2 Symbol Parameter Conditions Variable clock fosc 12 MHz Unit Min Max Min Max fosc RC internal RC oscillator nominal f 2 7 3728 MHz 7 189 7 557 7 189 7 557 MHz frequency trimmed to 1 at Tamb 25 C clock doubler option OFF default nominal f 14 7456 MHz 14 378 15 114 14 378 15 114 MHz clock doubler option ON Vpp 2 7 V to 3 6 V osc WD internal watchdog Tamb 25 C 380 420 380
18. 420 kHz oscillator frequency fosc oscillator frequency 0 12 MHz Toy clk clock cycle time see Figure 33 83 ns CLKLP low power select clock 0 8 MHz frequency Glitch filter tgr glitch rejection time P1 5 RST pin 50 50 ns any pin except P1 5 RST 5 15 15 ns tsa signal acceptance time P1 5 RST pin 125 125 ns any pin except P1 5 RST 50 5 50 ns External clock tcHcx clock HIGH time see Figure 33 33 Toy clk tcLcx 33 ns tcLox clock LOW time see Figure 33 33 Tey cik tcHcx 33 ns tcLcH clock rise time see Figure 33 8 ns tcHcL clock fall time see Figure 33 8 ns Shift register UART mode 0 TXLXL serial port clock cycle see Figure 32 16Tey ctk 1333 ns time tovxH output data set up to see Figure 32 13Tey cik 1083 ns clock rising edge time txHax output data hold after see Figure 32 Toy clk 20 103 ns clock rising edge time txHDx input data hold after see Figure 32 0 0 ns clock rising edge time txupv input data valid to clock see Figure 32 150 150 ns rising edge time 1 Parameters are valid over operating temperature range unless otherwise specified 2 Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz P89LPC92X1 All information provided in this document is subject to legal disclaimers Rev 2 1 27 August 2012 NXP B V 2012 All rights reserved 62 of 75 Product data sheet NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 T
19. Fig 20 Ipp igie VS frequency at 25 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 55 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 P89LPC92X1 8 bit microcontroller with 8 bit ADC 2 7 50 002aae36 18 MHz Ipp mA 4 0 12 MHz 3 0 8 MHz 2 0 6 MHz 4 MHz 1 0 2MHz 1 MHz 32 kHz 0 0 2 4 2 8 3 2 3 6 Vpp V Test conditions Idle mode entered executing code from on chip flash using an external clock with no active peripherals with the following functions disabled real time clock and watchdog timer Fig 21 lpp gie VS frequency at 40 C 5 0 002aae368 Ipp mA 4 0 3 0 2 0 a Se MM NES 0 0 24 2 8 3 2 Vpp V Test conditions Idle mode entered executing code from on chip flash using an external clock with no active peripherals with the following functions disabled real time clock and watchdog timer Fig 22 lpp igie VS frequency at 85 C 3 6 18 MHz 12 MHz 8 MHz 6 MHz 4MHz 2MHz 1MHz 32 kHz All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 56 of 75 NXP Semiconductors P8
20. RTC system timer The P89LPC9201 9211 922A1 9241 9251 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down The RTC can be a wake up or an interrupt source The RTC is a 23 bit down counter comprised of a 7 bit prescaler and a 16 bit loadable down counter When it reaches all logic Os the counter will be reloaded again and the RTCF flag will be set The clock source for this counter can be either the CPU clock CCLK or the XTAL oscillator Only power on reset and watchdog reset will reset the RTC and its associated SFRs to the default state The 16 bit loadable counter portion of the RTC is readable by reading the RTCDATL and RTCDATH registers UART The P89LPC9201 9211 922A1 9241 9251 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC9201 9211 922A1 9241 9251 does include an independent baud rate generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent baud rate generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection automatic address recognition selectable double buffering and several interrupt options The UART can be operated in four modes shift register 8 bit UART 9 bit UART and CPU clock 32 or CPU clock 16 Mode 0 Serial data enters a
21. aaua aaau 32 und Ue oe oer nae ne oie vee rere eee abe 7 28 2 Features coe tee pa a GU 44 7 16 1 1 Quasi bidirectional output configuration 32 ee 7 28 3 Flash organization 00 44 7 16 1 2 Open drain output configuration 32 7 28 4 Using flash as data storage 44 7 16 1 3 Input only configuration 33 7 28 5 Flash programming and erasing 44 7 16 1 4 Push pull output configuration 33 7 28 6 ICP ane Wa Guess ets EL ERLEBEN REIR NUS 45 7 16 2 Port 0 analog functions 33 7287 IAP 45 7 16 3 Additional port features 33 7288 sp O 45 7 17 Power monitoring functions 33 prit eh ek Oe Gok ap Maeght et 7 28 9 Power on reset code execution 45 7 17 1 Brownout detection 005 34 ne 7 28 10 Hardware activation of the bootloader 46 7 17 2 Power on detection 005 34 7 29 User configuration bytes 46 7 18 Power reduction modes 34 7 30 Usersector rtv bytes 46 7 18 1 WB mode oe ces dsc vc Spann cee ca 34 Se SELIO SSCUMY in E estes E 7 18 2 Power down mode 2 e00 34 8 ADC P89LPC9241 9251 eee 46 continued gt gt P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August
22. address EF EE ED EC EB EA E9 E8 IEN1 Interrupt E8H EST EC EKBI EI2C ool 00x0 0000 enable 1 Bit address BF BE BD BC BB BA B9 B8 IPO Interrupt B8H PWDRT PBO PS PSR PT1 PX1 PTO PXO ool x000 0000 priority O DAV 1q 8 YUM 19 01 U090191W 319 8 SJOJONPUODIWISS dXN LS26 L7c6 LVcc6 L C6 LOC60d 168d Jays Lep 19npoJd eL0z isnbny ZZ L z ed sieuirejosip ea 0 1oefqns s jueuunoop S14 ui pepi oid uoneuuojul y GZ 40 SI X260d 168d pemasal suu Ily ZLOZ 8 dXN Table 4 Special function registers P89LPC9201 9211 922A1 indicates SFRs that are bit addressable Name IPOH IP1 IP1H KBCON KBMASK KBPATN PO P1 P3 POM1 POM2 P1M1 P1M2 P3M1 P3M2 Description SFR addr Interrupt B7H priority O high Bit address Interrupt F8H priority 1 Interrupt F7H priority 1 high Keypad control 94H register Keypad 86H interrupt mask register Keypadpattern 93H register Bit address Port 0 80H Bit address Port 1 90H Bit address Port 3 BOH Port 0 output 84H mode 1 Port 0 output 85H mode 2 Port 1 output 91H mode 1 Port 1 output 92H mode 2 Port 3 output B1H mode 1 Port 3 output B2H mode 2 Bit functions and addresses Reset value MSB LSB Hex Binary PWDRTH PBOH PSH PT1H PX1H PTOH PXOH oot x000 0000 PSRH FF FE FD FC FB FA F9 F8 PST PC PKBI PI2C ool 00x0 0000 PSTH PCH PKBIH PI2CH ooi 00x0 0000 z z PATN KBIF
23. are required to hold the device in reset at power up until Vpp has reached its specified level 7 7 Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz calibrated to t 5 96 at room temperature This oscillator can be used to save power when a high clock frequency is not needed 7 8 External clock input option In this configuration the processor clock is derived from an external source driving the P3 1 XTAL1 pin The rate may be from 0 Hz up to 18 MHz The P3 0 XTAL2 CLKOUT pin may be used as a standard port pin or a clock output When using an oscillator frequency above 12 MHz BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are required to hold the device in reset at power up until Vpp has reached its specified level 7 9 Clock sources switch on the fly P89LPC9201 9211 922A1 9241 9251 can implement clock source switch in any sources of watchdog oscillator 7 MHz 14 MHz internal RC oscillator external clock source external crystal or external clock input during code is running CLKOK bit in CLKCON register is used to indicate the clock switch status CLKOK is cleared when starting clock source switch and set when completed Notice that when CLKOK is 0 writing to CLKCON register is not allowed P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 27 of 75 NXP Sem
24. consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof P89LPC92X1 All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical system
25. if the result meets the selected interrupt criteria The boundary limit may be disabled by clearing the boundary limit interrupt enable An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits In this case after the four MSBs have been converted these four bits are compared with the four MSBs of the boundary high and low registers If the four MSBs of the conversion meet the interrupt criteria i e outside the boundary limits an interrupt will be generated if enabled If the four MSBs do not meet the interrupt criteria the boundary limits will again be compared after all 8 bits have been converted The boundary status register BNDSTAO flags the channels which caused a boundary interrupt 8 8 DAC output to a port pin with high output impedance The DAC block of ADC1 can be output to a port pin In this mode the AD1DATS register is used to hold the value fed to the DAC After a value has been written to the DAC written to AD1DATS3 the DAC output will appear on the channel 3 pin 8 9 Clock divider The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to maintain accuracy A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose 8 10 Power down and Idle mode In Idle mode the ADC if enabled will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A D inte
26. oscillator information Changed data sheet status to Product P89LPC92xX v 1 20090416 Preliminary data sheet P89LPC92X1 All information provided in this document is subject to legal disclaimers Product data sheet Rev 2 1 27 August 2012 NXP B V 2012 All rights reserved 71 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 16 Legal information 8 bit microcontroller with 8 bit ADC 16 1 Data sheet status Document status J 2 Product status Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 16 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP
27. pin RST 1 us VDD tvR ian RST RL 002aaa912 Fig 34 ISP entry waveform P89LPC92X1 All information provided in this document is subject to legal disclaimers Product data sheet Rev 2 1 27 August 2012 NXP B V 2012 All rights reserved 64 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 12 Other characteristics 8 bit microcontroller with 8 bit ADC 12 14 Comparator electrical characteristics Table 17 Comparator electrical characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 485 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Vio input offset voltage Vic common mode input voltage 0 CMRR common mode rejection ratio 0 tres tot total response time t cE ov chip enable to output valid time lu input leakage current OV lt Vi lt Vpp Max 20 Vpp 0 3 500 10 1 Unit mV dB ns us 1 This parameter is characterized but not tested in production P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 65 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 8 bit microcontroller with 8 bit ADC 12 2 ADC temperature sensor electrical characteristics Table 18 ADC temperature sensor electrical characteristics Vpp 2 4 V to 3 6 V
28. reserved Product data sheet Rev 2 1 27 August 2012 52 of 75 NX P Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC Table 12 Static characteristics continued Vpp 24 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Typi Max Unit Ira HIGH LOW transition all ports Vi 1 5 V at m1 30 450 uA current Vpp 3 6 V Rnsr win internal pull up resistance pin RST 10 30 ko on pin RST Vref bg band gap reference voltage 1 11 1 23 1 34 V TCbg band gap temperature 10 20 ppm coefficient oC 1 2 Typical ratings are not guaranteed The values listed are at room temperature 3 V The Ipp oper Specification is measured using an external clock with code while 1 executed from on chip flash 3 The lpp aie specification is measured using an external clock with no active peripherals with the following functions disabled real time clock and watchdog timer 4 The lpp pa Specification is measured using internal RC oscillator with the following functions disabled comparators real time clock and watchdog timer 5 The lpp pa specification is measured using an external clock with the following functions disabled comparators real time clock brownout detect and watchdog timer 6 See Section 9 Limiting values for steady state no
29. single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel An interrupt if enabled will be generated after the conversion completes 8 5 2 Fixed channel continuous conversion mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the four result register The user may select whether an interrupt can be generated after every four conversions Additional conversion results will again cycle through the four result register overwriting the previous results Continuous conversions continue until terminated by the user P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 48 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 5 3 8 5 4 8 5 5 8 5 6 8 6 8 6 1 8 6 2 8 6 3 P89LPC92X1 8 bit microcontroller with 8 bit ADC Auto scan single conversion mode Any combination of the four input channels can be selected for conversion A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel An interrupt if enabled will be generated after all selected channels have been
30. the port outputs a logic HIGH it is weakly driven allowing an external device to pull the pin LOW When the pin is driven LOW it is driven strongly and able to sink a fairly large current These features are somewhat similar to an open drain output except that there are three pull up transistors in the quasi bidirectional output that serve different purposes The P89LPC9201 9211 922A1 9241 9251 is a 3 V device but the pins are 5 V tolerant In quasi bidirectional mode if a user applies 5 V on the pin there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt trigger input that also has a glitch suppression circuit Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port driver when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 32 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 7 16 1 3 7 16 1 4 7 16 2 7 16 3 7 17 P89LPC92X1 8 bit microcontroller with 8 bit ADC An open drain port pin has a Schmit
31. 0 F8 1111 1000 AF AE AD AC AB AA A9 A8 EA EWDRT EBO ES ESR ET1 EX1 ETO EXO 00 0000 0000 EF EE ED EC EB EA E9 E8 EAD EST EC EKBI EI2C ool 00x0 0000 OQV 1 q 8 YPM 19 O1 UODOISIW 319 8 SJOJONPUODIWIIS dXN LS26 L7 c6 LVcc6 L C6 LOC60d 168d Jays Lep 19npoJd eL0z isnbny ZZ L Z ed sieuirejosip ea 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y 8410 ZZ LXe60d 68d pamasa suu Iv ZLOZ 5 8 dXN Table 6 indicates SFRs that are bit addressable Special function registers P89LPC9241 9251 continued Name IPO IPOH IP1 IP1H KBCON KBMASK KBPATN PO P1 P3 POM1 POM2 P1M1 P1M2 Description SFR addr Bit address Interrupt B8H priority O Interrupt B7H priority O high Bit address Interrupt F8H priority 1 Interrupt F7H priority 1 high Keypad control 94H register Keypad 86H interrupt mask register Keypadpattern 93H register Bit address Port 0 80H Bit address Port 1 90H Bit address Port 3 BOH Port 0 output 84H mode 1 Port 0 output 85H mode 2 Port 1 output 91H mode 1 Port 1 output 92H mode 2 Bit functions and addresses Reset value MSB LSB Hex Binary BF BE BD BC BB BA B9 B8 PWDRT PBO PS PSR PT1 PX1 PTO PXO oot x000 0000 PWDRTH PBOH PSH PT1H PX1H PTOH PXOH oot x000 0000 PSRH FF FE FD FC FB FA F9 F8 PAD PST PC PKBI PI2C oot 00x0 0000 PADH PSTH PCH PKBIH PI2CH ooi 00x0 0000 PATN KBIF ool
32. 1 8 bit microcontroller with 8 bit ADC Reset vector Following reset the P89LPC9201 9211 922A1 9241 9251 will fetch instructions from either address 0000H or the Boot address The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address 00H The boot address will be used if a UART break reset occurs or the non volatile boot status bit BOOTSTAT 0 1 or the device is forced into ISP mode during power on see P89LPC9201 9211 922A1 9241 9251 User manual Otherwise instructions will be fetched from address 0000H Timers counters 0 and 1 The P89LPC9201 9211 922A1 9241 9251 has two general purpose counter timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counters An option to automatically toggle the TO and or T1 pins upon timer overflow has been added In the Timer function the register is incremented every machine cycle In the Counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin TO or T1 In this function the external input is sampled once during every machine cycle Timer 0 and Timer 1 have five operating modes Modes 0 1 2 3 and 6 Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bi
33. 1 1111 00 0000 0000 00 0000 0000 OAV HO 8 YUM 19 01 UODOISIW 319 8 SJOJONPUODIWIIS dXN LGc6 Lt66 FV666 LE66 L0c60d 168d Jays Lep 19npoJd eL0z isnbny ZZ L Z ed sieuirejosip eba 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y 8410 0c LXe60d 68d pamasa suu Iv ZLOZ 8 dXN Table 6 indicates SFRs that are bit addressable Special function registers P89LPC9241 9251 continued Name AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 B BRGROE BRGR1EI BRGCON CMP1 CMP2 DIVM DPTR DPH DPL SFR addr Description A D_0 data D6H register 1 A D_0 data D7H register 2 A D_0 data F5H register 3 Auxiliary A2H function register Bit address B register FOH Baud rate BEH generator 0 rate low Baud rate BFH generator 0 rate high Baud rate BDH generator 0 control Comparator1 ACH control register Comparator 2 ADH control register CPU clock 95H divide by M control Data pointer 2 bytes Data pointer 83H high Data pointer 82H low Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 F7 F6 F5 F4 F3 F2 F1 FO 00 0000 0000 00 0000 0000 00 0000 0000 SBRGS BRGEN _ 00 21 xxxx xx0O CE1 CP1 CN1 OE1 CO1 CMF1 ool xx00 0000 CE2 CP2 CN2 OE2 CO2 CMF2 ool xx00 0000 00 0000 0000 00 0000 0000 00 0000 0000 DAV
34. 1 922A1 9241 9251 examines the contents of the Boot Status bit If the Boot Status bit is set to zero power up execution starts at location OOOOH which is the normal start address of the user s application code When the Boot Status bit is set to a value other than zero the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to OOH All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 45 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 28 10 7 29 7 30 8 bit microcontroller with 8 bit ADC Table 10 shows the factory default Boot Vector setting for these devices A factory provided bootloader is pre programmed into the address space indicated and uses the indicated bootloader entry point to perform ISP functions This code can be erased by the user Remark Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this bootloader Instead the page erase function can be used to erase the first eight 64 byte pages located in this sector A custom bootloader can be written with the Boot Vector set to the custom bootloader if desired Table 10 Default boot vector values and ISP entry points Device Default Default Default bootloader 1 kB sector boot vector bootloader code range range entry point P
35. 2H high RTC register D3H low Serial port A9H address register Serial port B9H address enable Serial Portdata 99H buffer register Bit address Serial port 98H control Serial port BAH extended status register Stack pointer 81H Timer 0 and 1 8FH auxiliary mode Bit functions and addresses Reset value MSB LSB Hex Binary SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO 00 0000 0000 RTCPD VCPD Il2PD SPD ool 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00 000x BOIF BOF POF R BK R WD R SF REX B RTCF RTCS1 RTCSO ERTC RTCEN 60 l6 011x xx00 ool l 0000 0000 ool l 0000 0000 00 0000 0000 00 0000 0000 XX XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 07 0000 0111 T1M2 TOM2 00 Xxx0 xxx0 DAV 1 q 8 YUM 19 01 UODOISIW 1q 8 SJOJONPUODIWIIS dXN LS26 L7 c6 LVcc6 L C6 LOC60d 168d Jays Lep 19npoJd eL0z 1SnDny 22 L Z ed sieuirejosip eba oj joefqns s jueuunoop siu ui pepi oid uoneuuojul Iv 8410 ZI LXe60d 68d pe uese suu Iv ZLOZ 8 dXN Tabl e4 Special function registers P89LPC9201 9211 922A1 indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 88H TF1 T
36. 360 1 leads body width 4 4 mm P89LPC92X1 3 1 Ordering options Table 2 Ordering options Type number Flash memory Temperature range Frequency P89LPC9201FDH 2 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC9211FDH 4kB 40 C to 85 C 0 MHz to 18 MHz P89LPC922A1FDH 8 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC922A1FN 8 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC9241FDH 4 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC9251FDH 8 kB 40 C to 85 C 0 MHz to 18 MHz All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 3 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 8 bit microcontroller with 8 bit ADC 4 Block diagram P89LPC9201 9211 922A1 HIGH PERFORMANCE ACCELERATED 2 CLOCK 80C51 CPU CSS 2 kB 4 kB 8 kB TXD CODE FLASH gt C9 UART RXD internal 256 BYTE bus REAL TIME CLOCK DATA RAM O G SYSTEM TIMER E 3 SCL POSITI e enin CONFIGURABLE I Os C C C BUS SDA PORT 1 WATCHDOG TIMER P1 7 0 eT a Os C AK gt AND OSCILLATOR PORTO TIMER 0 TO Poro a CONFIGURABLE 110s f AK ec cw ial CIN2B KEYPAD lt _ ANALOG CIN2A INTERRUPT COMPARATORS onia MPI CIN1B nd PROGRAMMABLE CPU OSCILLATOR DIVIDER clock XTAL1 SOME CONFIGURABLE ON CHIP RC POWER MONITOR OosciLATOR OSCILLATOR WITH POWER ON RESET EEBON
37. 4 11 2 ISP entry mode 000 eee eee 64 12 Other characteristics 65 12 1 Comparator electrical characteristics 65 12 2 ADC temperature sensor electrical characteristicS 20000000 66 13 Package outline 68 14 Abbreviations lslseeesssese 70 15 Revision history eeseses 71 16 Legal information Lsee 72 16 1 Data sheet status 72 16 2 DefinitIONS 32 20 6422 seer kl li In 72 16 3 Disclaimers llle 72 16 4 Trademarks 0 eee 73 17 Contact information L 73 18 Contenis isree e n rn 74 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2012 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 27 August 2012 Document identifier P89LPC92X1
38. 80 420 kHz 0 18 MHz 55 ns 0 8 MHz 50 50 ns 15 15 ns 125 125 ns 50 50 ns 22 Tey clk tcLex 22 ns 22 Tey cik tcHex 22 nS 5 5 ns 5 5 ns 1 6Tey cik i 888 P ns 1 ST cy clk s 722 ns Toy ci 20 75 ns 0 0 ns 150 150 ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 63 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 8 bit microcontroller with 8 bit ADC 11 1 Waveforms TXLXL ud clock output data write to SBUF al txHDX tXHDV set TI T Quo XX Kae eX eux Kx KX clear RI r set RI 002aaa906 Fig 32 Shift register mode timing 002aaa907 Fig 33 External clock timing with an amplitude of at least Vigus 200 mV 11 2 ISP entry mode Table 16 Dynamic characteristics ISP entry mode Vpp 2 4 V to 3 6 V unless otherwise specified Tamp 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit tv Vpp active to RST active delay pin RST 50 us time try RST HIGH time pin RST 1 32 us tRL RST LOW time
39. 89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 5 Functional diagram Vpp Vss KBIO CMP2 lt gt TXD KBI1 CIN2B RXD KBI2 gt CIN2A 4 T0 SCL KBI3 CIN1B lt INTO SDA KB cinta PORT OV lt gt PORT 1 INTI KBI5 CMPREF gt P89LPC9201 lt RST KBI6 CMP1 gt 9211 922A1 gt KBI7 T1 4 gt i PM CLKOUT lt XTAL2 4 lt gt PORT 3 4 XTAL1 gt 002aae423 Fig 3 Functional diagram P89LPC9201 9211 922A1 Vpp Vss KBIO CMP2 lt TXD ADi0 gt KBl CIN2B gt RXD ADii gt KBI2 CIN2A gt gt T0 SCL AD12 gt KBI3 gt CIN1B gt had INTO gt SDA DAC1 AD13 KBI4 gt cinta PORTO VL PORT INTI KBI5 CMPREF gt P89LPC9241 lt lt RST KBI6 CMP1 lt 9251 er CLKOUT 4 XTAL2 4 PORT 3 XTAL1 gt 002aae424 Fig 4 Functional diagram P89LPC9241 9251 P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 6 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 8 bit microcontroller with 8 bit ADC 6 Pinning information 6 1 P
40. 89LPC9201 07H 0700H 0600H to 07FFH 0400H to 07FFH P89LPC9211 9241 OFH OFOOH OEOOH to OFFFH OCOOH to OFFFH P89LPC922A1 9251 1FH 1FOOH 1E00H to 1FFFH 1C00H to 1FFFH Hardware activation of the bootloader The bootloader can also be executed by forcing the device into ISP mode during a power on sequence see the P89LPC9201 9211 922A1 9241 9251 User manual for specific information This has the same effect as having a non zero status byte This allows an application to be built that will normally execute user code but can be manually forced into ISP operation If the factory default setting for the boot vector is changed it will no longer point to the factory pre programmed ISP bootloader code After programming the flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H User configuration bytes Some user configurable features of the P89LPC9201 9211 922A1 9241 9251 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of the flash byte UCFG1 and UCFG2 Please see the P89LPC9201 9211 922A1 9241 9251 User manual for additional details User sector security bytes There are two four eight User Sector Security Bytes on the P89LPC9201 9211 922A1 9241 9251 Each byte corresponds to one sector Please see the P89LPC9201 9211 922A1 9241 9251 User manual for additional details 8 AD
41. 9LPC9201 921 1 922A1 9241 9251 P89LPC92X1 8 bit microcontroller with 8 bit ADC 20 0 002aae369 Ipp uA 0 18 0 aa 16 0 2 14 0 NEMO ee NN 34 12 0 oe 10 0 2 4 28 3 2 3 6 Vpp V Test conditions Power down mode using internal RC oscillator with the following functions disabled comparators real time clock and watchdog timer 1 485 C 2 425 C 3 40 C Fig 23 Ipp pa VS Vpp 002aae370 0 4 0 0 24 2 8 3 2 3 6 Vpp V Test conditions Total Power down mode using internal RC oscillator with the following functions disabled comparators brownout detect real time clock and watchdog timer 1 85 C 2 40 C 3 25 C Fig 24 Ipp tpd VS VoD All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 57 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 10 2 Internal RC watchdog oscillator characteristics P89LPC92X1 Note The graphs provided are a statistical summary based on a limited number of samples and only for information purposes The performance characteristics listed are not tested or guaranteed 002aae344 0 2 frequency deviation 0 1
42. ATE CLOCK DOUBLER BROWNOUT RESET XTAL2 002aae421 Fig 1 Block diagram P89LPC9201 9211 922A1 P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 4 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 8 bit microcontroller with 8 bit ADC P89LPC9241 9251 HIGH PERFORMANCE ACCELERATED 2 CLOCK 80C51 CPU W 4 kB 8 kB d CODE FLASH C TXD UART RXD internal 256 BYTE E Bus 4 X REAL TIME CLOCK DATA RAM SYSTEM TIMER AK PORT 3 P3 1 0 D CONFIGURABLE ls K SCL 2C 2C BUS SDA m umm 1 Pi EL CONFIGURABLE I Os C y WATCHDOG TIMER AND OSCILLATOR PORTO PO 7 0 a CONFIGURABLE Oe f SA 40v y TIMER 0 TO TIMER 1 T1 ELE Ez INTERRUPT PROGRAMMABLE OSCILLATOR DIVIDER XTAL1 OPSTA CONFIGURABLE OSCILLATOR RESO XTAL2 Fig 2 Block diagram P89LPC9241 9251 CPU clock bd ON CHIP RC OSCILLATOR WITH CLOCK DOUBLER IM CMP CIN2B ANALOG CIN2A ear COMPARATORS TINTA CIN1B AD10 ADC1 DAC1 AD11 TEMPERATURE AD12 SENSOR AD13 DAC1 POWER MONITOR POWER ON RESET BROWNOUT RESET 002aae422 P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 5 of 75 NXP Semiconductors P
43. C P89LPC9241 9251 8 1 P89LPC92X1 General description The P89LPC9241 9251 has two analog to digital converter modules ADCO and ADC1 ADC1 is an 8 bit 4 channel multiplexed successive approximation analog to digital converter ADCO is dedicated for on chip temperature sensor which operates over wide All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 46 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 P89LPC92X1 8 2 8 bit microcontroller with 8 bit ADC temperature The temperature sensor is measured through Anin03 AninOO Anin01 and Anin02 are unused A block diagram of the ADC is shown in Figure 15 ADC block diagram The ADC consists of an 4 input multiplexer which feeds a sample and hold circuit providing an input signal to comparator inputs The control logic in combination with the SAR drives a digital to analog converter which provides the other input to the comparator The output of the comparator is fed to the SAR Features and benefits 8 bit 4 channel multiplexed input successive approximation ADC On chip wide range temperature sensor Four result registers for each A D Six operating modes Fixed channel single conversion mode Fixed channel continuous conversion mode Auto scan single conversion mode Auto scan continuous conversion mode
44. C1 channel 2 analog input P89LPC9241 9251 P0 4 CIN1A 17 l O P0 4 Port 0 bit 4 High current source KBM DACT AD13 l CIN1A Comparator 1 positive input A l KBI4 Keyboard input 4 O DAC1 Digital to analog converter output 1 P89LPC9241 9251 AD13 ADC1 channel 3 analog input P89LPC9241 9251 P0 5 CMPREF 16 l O P0 5 Port 0 bit 5 High current source KBIS l CMPREF Comparator reference negative input l KBI5 Keyboard input 5 P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 9 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 8 bit microcontroller with 8 bit ADC Table 3 Pin description continued Symbol Pin Type Description TSSOP20 DIP20 P0 6 CMP1 KBI6 14 l O P0 6 Port 0 bit 6 High current source O CMP1 Comparator 1 output KBl6 Keyboard input 6 PO 7 T1 KBI7 13 lO P0 7 Port 0 bit 7 High current source lO T1 Timer counter 1 external count input or overflow output l KBI7 Keyboard input 7 P1 0 to P1 7 l O 1 Port 1 Port 1 is an 8 bit I O port with a user configurable output type except for three pins as noted below During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port conf
45. R1 TFO TRO IE1 IT1 IEO ITO 00 0000 0000 control THO Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TLO Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1 89H T1GATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 mode TRIM Internal 96H RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O BII6 oscillator trim register WDCON Watchdog A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK MIS control register WDL Watchdog load C1H FF 1111 1111 WFEED1 Watchdog C2H feed 1 WFEED2 Watchdog C3H feed 2 t 2 3 4 5 All ports are in input only high impedance state after power up BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable The RSTSRC register reflects the cause of the P89LPC9201 9211 922A1 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is x011 0000 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WDRUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset and watchdog reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register The only reset sources that affect these SFRs are power on reset and watchdog reset DAV
46. Rev 2 1 27 August 2012 8 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 6 2 Pin description Table 3 Pin description Symbol Pin Type Description TSSOP20 DIP20 P0 0 to P0 7 VO Port 0 Port 0 is an 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 16 1 Port configurations and Table 12 Static characteristics for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt trigger inputs Port 0 also provides various special functions as described below P0 0 CMP2 1 l O P0 0 Port 0 bit 0 KBIO O CMP2 Comparator 2 output KBIO Keyboard input 0 P0 1 CIN2B 20 O P0 1 Port O bit 1 KBIT AD10 l CIN2B Comparator 2 positive input B l KBI1 Keyboard input 1 AD10 ADC1 channel 0 analog input P89LPC9241 9251 P0 2 CIN2A 19 lO P0 2 Port 0 bit 2 KBI2 AD11 l CIN2A Comparator 2 positive input A l KBI2 Keyboard input 2 l AD11 ADC1 channel 1 analog input P89LPC9241 9251 P0 3 CIN1B 18 O P0 3 Port 0 bit 3 High current source KBIS AD12 l CIN1B Comparator 1 positive input B l KBI3 Keyboard input 3 AD12 AD
47. SBUF Serial Portdata 99H buffer register Bit address SCON Serial port 98H control SSTAT Serial port BAH extended status register Bit functions and addresses Reset value MSB LSB Hex Binary 5 P3M1 1 P3M1 0 03i XXXX XX11 P3M2 1 P3M2 0 00L xxxx xx00 SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO 00 0000 0000 RTCPD VCPD ADPD I2PD SPD ool 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 a 00 xx00 000x BOIF BOF POF R_BK R_WD R_SF REX B RTCF RTCS1 RTCSO ERTC RTCEN 60l ll5 011x xx00 0018 0000 0000 0018 0000 0000 00 0000 0000 00 0000 0000 XX XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 DAV 1 q 8 YUM 19 O1 UODOISIW 319 8 SJOJONPUODIWISS dXN LS26 L7c6 LVcc6 L C6 LOC60d 168d Jeaus Lp jonpoJd eL0z isnbny ZZ 12 ed sieuirejosip eba 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul Iv GZ 40 tC X 60d 168d pemasa suu Ily ZLOZ 5 8 dXN Table 6 Special function registers P89LPC9241 9251 continued indicates SFRs that are bit addressable Name SP TAMOD TCON THO TH1 TLO TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2 SFR addr Description Stack pointer 81H Timer 0 and 1 8FH auxiliary mode Bit address Timer 0 and 1 88H control Timer 0 high 8CH
48. Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 16 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the
49. Timer 1 high 8DH Timer 0 low 8AH Timer 1 low 8BH Timer 0 and 1 89H mode Internal 96H oscillator trim register Watchdog A7H control register Watchdog load C1H Watchdog C2H feed 1 Watchdog C3H feed 2 Bit functions and addresses Reset value MSB LSB Hex Binary 07 0000 0111 T1M2 TOM2 00 XXxx0 xxxO 8F 8b 8D 8C 8B 8A 89 88 TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 TIGATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Ile PRE2 PRE1 PREO WDRUN WDTOF WDCLK is FF 1111 1111 1 All ports are in input only high impedance state after power up 2 BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable 3 The RSTSRC register reflects the cause of the P89LPC9241 9251 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is x011 0000 4 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WDRUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF 5 On power on reset and watchdog reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 6 The only reset sou
50. UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 DAV 1 q 8 YUM 19 01 UODOISIW 1q 8 SJOJONPUODIWIIS dXN LGc6 Lt66 FV666 LE66 L06c60d 168d NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 2 7 3 7 3 1 7 3 2 7 4 7 4 1 7 4 2 7 4 3 P89LPC92X1 8 bit microcontroller with 8 bit ADC Enhanced CPU The P89LPC9201 9211 922A1 9241 9251 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clocks Clock definitions The P89LPC9201 9211 922A1 9241 9251 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock Sources see Figure 8 and can also be optionally divided to a slower frequency see Section 7 11 CCLK modification DIVM register Remark fosc is defined as the OSCCLK frequency CCLK CPU clock output of the clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output The clock doubler option when enabled provides an output frequency of 14 746 MHz PCLK Clock for the various peripheral devices and is CPU clock OSCCLK The P89LPC9201 9211 922A1 9241 9251 provides several user se
51. able 15 Dynamic characteristics 18 MHz Vpp 3 0 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified 112 8 bit microcontroller with 8 bit ADC Symbol Parameter fosc Rc internal RC oscillator frequency fosewp internal watchdog oscillator frequency fosc oscillator frequency Tey clk clock cycle time foLKLP low power select clock frequency Glitch filter tgr glitch rejection time tsa signal acceptance time External clock tcHcx teLcx teLcH tcHcL clock HIGH time clock LOW time clock rise time clock fall time Shift register UART mode 0 TXLXL tavxH txHax txHDx txHDv serial port clock cycle time output data set up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time Conditions nominal f 7 3728 MHz trimmed to 1 at Tamb 25 C clock doubler option OFF default nominal f 14 7456 MHz clock doubler option ON Tamb 25 C see Figure 33 P1 5 RST pin any pin except P1 5 RST P1 5 RST pin any pin except P1 5 RST see Figure 33 see Figure 33 see Figure 33 see Figure 33 see Figure 32 see Figure 32 see Figure 32 see Figure 32 see Figure 32 Variable clock fose 18 MHz Unit Min Max Min Max 7 189 7 557 7 189 7 557 MHz 14 378 15 114 14 378 15 114 MHz 380 420 3
52. be written with 0 and will return a 0 when read 1 must be written with 1 and will return a 1 when read P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 12 of 75 LXe60d 68d Jays Lep 19npoJd eL0z snbny ZZ 12 ed sieuirejosip ea oj joefqns s jueuunoop siu ui pepi oid uoneuuojul y pe iese suu Ily ZLOZ 8 dXN 8210 L Table 4 Special function registers P89LPC9201 9211 922A1 indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 EO ACC Accumulator EOH 00 0000 0000 AUXR1 Auxiliary A2H CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 function register Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 0000 0000 BRGRO Baud rate BEH 00 0000 0000 generator 0 rate low BRGRi1l2 Baud rate BFH 00 0000 0000 generator 0 rate high BRGCON Baud rate BDH SBRGS BRGEN 008 Xxxx xx00 generator 0 control CMP1 Comparator 1 ACH CE1 CP1 CN1 OE1 CO1 CMF1 ool xx00 0000 control register CMP2 Comparator2 ADH 7 CE2 CP2 CN2 OE2 CO2 CMF2 ool xx00 0000 control register DIVM CPU clock 95H 00 0000 0000 divide by M control DPTR Data pointer 2 bytes DPH Data pointer 83H 00 0000 0000 high DPL Data pointer 82H 00 0000
53. bits configuration bytes and device ID These functions are selected by setting up the microcontroller s registers before making a call to PGM_MTP at FFO3H The Boot ROM occupies the program memory space at the top of the address space from FFOOH to FEFFH thereby not conflicting with the user program memory space In addition IAP operations can be accomplished through the use of four SFRs consisting of a control status register a data register and two address registers Additional details may be found in the P89LPC9201 9211 922A 1 9241 9251 User manual ISP ISP is performed without removing the microcontroller from the system The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC9201 9211 922A1 9241 9251 through the serial port This firmware is provided by NXP and embedded within each P89LPC9201 9211 922A1 9241 9251 device The NXP ISP facility has made in system programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vpp Vss TXD RXD and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature Power on reset code execution The P89LPC9201 9211 922A1 9241 9251 contains two special flash elements the Boot Vector and the Boot Status bit Following reset the P89LPC9201 921
54. ck output function on the P3 0 XTAL2 CLKOUT pin when crystal oscillator is not being used This condition occurs if another clock source has been selected on chip RC oscillator watchdog oscillator external clock input on XTAL1 and if the RTC and WDT are not using the crystal oscillator as their clock source This allows external devices to synchronize to the P89LPC9201 9211 922A1 9241 9251 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power 7 6 On chip RC oscillator option The P89LPC9201 9211 922A1 9241 9251 has a 6 bit TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7 373 MHz x 1 at room temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies When the clock doubler option is enabled UCFG2 7 1 the output frequency is 14 746 MHz If CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to reduce power consumption On reset CLKLP is logic 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower When clock doubler option is enabled BOE 1 bit UCFG1 5 and BOEO bit UCFG1 3
55. converted If only a single channel is selected this is equivalent to single channel single conversion mode Auto scan continuous conversion mode Any combination of the four input channels can be selected for conversion A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel An interrupt if enabled will be generated after all selected channels have been converted The process will repeat starting with the first selected channel Additional conversion results will again cycle through the four result register pairs overwriting the previous results Continuous conversions continue until terminated by the user Dual channel continuous conversion mode This is a variation of the auto scan continuous conversion mode where conversion occurs on two user selectable inputs The result of the conversion of the first channel is placed in the result register AD1DATO The result of the conversion of the second channel is placed in result register AD1DAT1 The first channel is again converted and its result stored in AD1DAT2 The second channel is again converted and its result placed in AD1DAT3 An interrupt is generated if enabled after every set of four conversions two conversions per channel Single step mode This special mode allows single stepping in an auto scan conversion mode Any combination of the four input channels can be selected for convers
56. d modes 1 2 and 3 Unlike the conventional UART in double buffering mode the TI interrupt is generated when the double buffer is ready to receive new data The 9t bit bit 8 in double buffering modes 1 2 and 3 If double buffering is disabled TB8 can be written before or after SBUF is written as long as TB8 is updated some time before that bit is shifted out TB8 must not be changed until the bit is shifted out as indicated by the TI interrupt If double buffering is enabled TB8 must be updated before SBUF is written as TB8 will be double buffered together with SBUF data I C bus serial interface The I C bus uses two wires SDA and SCL to transfer information between devices connected to the bus and it has the following features Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer e The I2C bus may be used for test and diagnostic purposes A typical 1 C bus configuration is shown in Figure 11 The P89LPC9201 9211 922A1 9241 9251 device provides a byte oriented I C bus interface that supports data transfers up to 400 kHz Rp Rp ea a a
57. de a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in Power down and Idle modes as well as in the normal operating mode This fact should be taken into account when system power consumption is an issue To minimize power consumption the user can disable the comparators via PCONA 5 or put the device in Total Power down mode KBI The Keypad Interrupt function KBI is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks The Keypad Interrupt Mask Register KBMASk is used to define which input pins connected to Port 0 can trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if
58. device supports individual byte erasing and programming Any byte in the code memory array may be read using the MOVC instruction provided that the sector containing the byte has not been secured a MOVC instruction is not allowed to read code memory contents of a secured sector Thus any byte in a non secured sector may be used for non volatile data storage Flash programming and erasing Four different methods of erasing or programming of the flash are available The flash may be programmed or erased in the end user application IAP under control of the application s firmware Another option is to use the ICP mechanism This ICP system provides for programming through a serial clock serial data interface As shipped from the factory the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device This device does not provide for direct verification of code memory contents Instead this device provides a 32 bit CRC result on either a sector or the entire user code space Remark When voltage supply is lower than 2 4 V the BOD FLASH is tripped and flash erase program is blocked All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 44
59. during power down These include Brownout detect watchdog timer comparators note that comparators can be powered down separately and RTC system timer The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled Total Power down mode This is the same as Power down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled If the internal RC oscillator is used to clock the RTC during power down there will be high power consumption Please use an external low frequency clock to achieve low power with the RTC running during power down Reset The P1 5 RST pin can function as either a LOW active reset input or as a digital input P1 5 The Reset Pin Enable RPE bit in UCFG1 when set to logic 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin Remark During a power up sequence the RPE selection is overridden and this pin always functions as a reset input An external circuit connected to this pin should not hold this pin LOW during a power on sequence as this will keep the device in reset After power up this pin will function as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE b
60. enabled The PATN SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in P87LPC76x series the user needs to set KBPATN OFFH and PATN SEL 1 not equal then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than six CCLKs Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count It consists of a programmable 12 bit prescaler and an 8 bit down counter The down counter is decremented by a tap taken from the prescaler The clock source for the prescaler can be the PCLK the nominal 400 kHz watchdog oscillator or low speed crystal oscillator The watchdog timer can only be reset by a power on reset When the watchdog feature is disabled it can be used as an interval timer and may generate an interrupt Figure 14 shows the watchdog timer in Watchdog mode Feeding the watchdog requires a
61. error detection and automatic address detection 400 kHz byte wide I2C bus communication port B 2 4 V to 3 6 V Vpp operating range I O pins are 5 V tolerant may be pulled up or driven to 5 5 V B Enhanced low voltage brownout detect allows a graceful system shutdown when power fails W 20 pin TSSOP and DIP packages with 15 I O pins minimum and up to 18 I O pins while using on chip oscillator and reset options NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 P89LPC92X1 8 bit microcontroller with 8 bit ADC 2 2 Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz This is six times the performance of the standard 80C51 running at the same clock frequency A lower clock frequency for the same performance results in power savings and reduced EMI Serial flash In Circuit Programming ICP allows simple production coding with commercial EPROM programmers Flash security bits prevent reading of sensitive application programs Serial flash In System Programming ISP allows coding while the device is mounted in the end application In Application Programming IAP of the flash code memory This allows changing the code in a running application Watchdog timer with separate on chip oscillator nominal 400 kHz calibrated to 5 96 requiring no external components The watchdog prescaler is selectable fro
62. g mechanisms The P89LPC9201 9211 922A1 9241 9251 uses Vpp as the supply voltage to perform the Program Erase algorithms When voltage supply is lower than 2 4 V the BOD FLASH is tripped and flash erase program is blocked Features Programming and erase over the full operating voltage range Byte erase allows code memory to be used for data storage Read Programming Erase using ISP IAP ICP Internal fixed boot ROM containing low level IAP routines available to user code Default loader providing ISP via the serial port located in upper end of user program memory Boot vector allows user provided flash loader code to reside anywhere in the flash memory space providing flexibility to the user e Any flash program erase operation in 2 ms Programming with industry standard commercial programmers Programmable security for the code in the flash for each sector 100 000 typical erase program cycles for each byte 10 year minimum data retention Flash organization The program memory consists of two four eight 1 kB sectors on the P89LPC9201 9211 922A1 9241 9251 devices Each sector can be further divided into 64 byte pages In addition to sector erase page erase and byte erase a 64 byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time Using flash as data storage The flash code memory array of this
63. hase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 72 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 17 Contact information 8 bit microcont
64. iconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC XTAL1 HIGH FREQUENCY MEDIUM FREQUENCY t RTC XTAL2 LOW FREQUENCY m ADC P89LPC9241 9251 OSCCLK CCLK d on HH CPU RC OSCILLATOR RCCLK WITH CLOCK DOUBLER 7 3728 MHz 14 7456 MHz 1 96 PCLK WATCHDOG gt WDE OSCILLATOR 400 kHz 5 96 PCLK TIMER 0 AND 2 TIMER 1 I C BUS UART 002aae428 Fig 8 Block diagram of oscillator control 7 10 7 11 7 12 P89LPC92X1 CCLK wake up delay The P89LPC9201 9211 922A1 9241 9251 has an internal wake up timer that delays the clock until it stabilizes depending on the clock source used If the clock source is any of the three crystal selections low medium and high frequencies the delay is 1024 OSCCLK cycles plus 60 us to 100 us If the clock source is the internal RC oscillator the delay is 200 us to 300 us If the clock source is watchdog oscillator or external clock the delay is 32 OSCCLK cycles CCLK modification DIVM register The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register DIVM to generate CCLK This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate This can also allow bypas
65. iguration selected Each of the configurable port pins are programmed independently Refer to Section 7 16 1 Port configurations and Table 12 Static characteristics for details P1 2 to P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt trigger inputs Port 1 also provides various special functions as described below P1 0 TXD 12 l O P1 0 Port 1 bit 0 O TXD Transmitter output for serial port P1 1 RXD 11 VO P1 1 Port 1 bit 1 RXD Receiver input for serial port P1 2 TO SCL 10 lO P1 2 Port 1 bit 2 open drain when used as output lO TO Timer counter 0 external count input or overflow output open drain when used as output lO SCL I C bus serial clock input output P1 3 INTO SDA 9 lO P1 3 Port 1 bit 3 open drain when used as output l INTO External interrupt 0 input lO SDA l C bus serial data input output P1 4 INT1 8 l O P1 4 Port 1 bit 4 High current source INT1 External interrupt 1 input P1 5 RST 4 l P1 5 Port 1 bit 5 input only RST External Reset input during power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force ISP mode P1 6 l O P1 6 Port 1 bit 6 High current source P1 7 VO P1 7 Port 1 bit 7 High curre
66. in SCON 7 respectively If SMODO is logic 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are set up when SMODO is logic O Break detect Break detect is reported in the status register SSTAT A break is detected when 11 consecutive bits are sensed LOW The break detect can be used to reset the device and force the device into ISP mode Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters as long as the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SBUF while the previous data is being shifted out Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 38 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 22 9 7 22 10 7 23 P89LPC92X1 8 bit microcontroller with 8 bit ADC Transmit interrupts with double buffering enable
67. inning P0 0 CMP2 KBIO P0 1 CIN2B KBH AD10 P1 7 C P0 2 CIN2A KBI2 AD1 1 P1 6 P0 3 CIN1B KBI3 AD12 P1 5 RST PO 4 CIN1A KBI4 AD13 DAC1 Vss P0 5 CMPREF KBI5 P3 1 XTAL1 VDD P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 P0 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD 002aae425 Fig 5 P89LPC9241 9251 TSSOP20 pin configuration P0 0 CMP2 KBIO P0 1 CIN2B KBI1 P1 7 C P0 2 CIN2A KBI2 P1 6 P0 3 CIN1B KBI3 P1 5 RST P0 4 CIN1A KBI4 sa P89LPC9201 9211 aie la P3 1 XTAL1 922A1 Vpp P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 P0 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD 002aae426 Fig 6 P89LPC9201 9211 922A1 TSSOP20 pin configuration P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 7 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC P89LPC922A1 P0 0 CMP2 KBIO P0 1 CIN2B KBI1 P1 7 P0 2 CIN2A KBI2 P1 6 P0 3 CIN1B KBI3 P1 5 RST PO 4 CIN1A KBI4 Vss P0 5 CMPREF KBI5 P3 1 XTAL1 VDD P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 PO 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD 002aae427 Fig 7 P89LPC922A1 DIP20 pin configuration P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet
68. ion After each channel is converted an interrupt is generated if enabled and the A D waits for the next start condition May be used with any of the start modes Conversion start modes Timer triggered start An A D conversion is started by the overflow of Timer 0 Once a conversion has started additional Timer 0 triggers are ignored until the conversion has completed The Timer triggered start mode is available in all ADC operating modes Start immediately Programming this mode immediately starts a conversion This start mode is available in all ADC operating modes Edge triggered An A D conversion is started by rising or falling edge of P1 4 Once a conversion has started additional edge triggers are ignored until the conversion has completed The edge triggered start mode is available in all ADC operating modes All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 49 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 8 7 Boundary limits interrupt Each of the A D converters has both a high and low boundary limit register The user may select whether an interrupt is generated when the conversion result is within or equal to the high and low boundary limits or when the conversion result is outside the boundary limits An interrupt will be generated if enabled
69. isters Selected CPU registers and peripheral control and status registers accessible only via direct addressing CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC9201 9211 922A1 9241 9251 has 2 kB 4 kB 8 kB of on chip Code memory Data RAM arrangement The 256 bytes of on chip RAM are organized as shown in Table 8 Table8 On chip data memory usages Type Data RAM Size bytes DATA Memory that can be addressed directly and indirectly 128 IDATA Memory that can be addressed indirectly 256 Interrupts The P89LPC9201 9211 922A1 9241 9251 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the many interrupt sources The P89LPC9201 9211 922A1 9241 9251 supports 12 13 interrupt sources external interrupts O and 1 timers 0 and 1 serial port TX serial port RX combined serial port RX TX brownout detect watchdog RTC I2C bus keyboard comparators 1 and 2 A D Converter P89LPC9241 9251 Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global disable bit EA which disables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in p
70. it Other sources of reset will not override the RPE bit When this pin functions as a reset input an internal pull up resistance is connected see Table 12 Static characteristics Note During a power cycle Vpp must fall below Vpog before power is reapplied in order to ensure a power on reset see Table 12 Static characteristics Reset can be triggered from the following sources External reset pin during power up or if user configured via UCFG1 Power on detect Brownout detect Watchdog timer e Software reset UART break character detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a logic 0 to the corresponding bit More than one flag bit may be set During a power on reset both POF and BOF are set but the other flag bits are cleared A Watchdog reset is similar to a power on reset both POF and BOF are set but the other flag bits are cleared e For any other reset previously set flag bits that have not been cleared will remain set All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 35 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 19 1 7 20 7 20 1 7 20 2 7 20 3 7 20 4 7 20 5 P89LPC92X
71. lectable oscillator options in generating the CPU clock This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the flash is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source Crystal oscillator option The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz It can be the clock source of OSCCLK and RTC Low speed oscillator option can be the clock source of WDT Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 26 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 7 5 Clock output The P89LPC9201 9211 922A1 9241 9251 supports a user selectable clo
72. m eight values High accuracy internal RC oscillator option with clock doubler option allows operation without external oscillator components The RC oscillator option is selectable and fine tunable Clock switching on the fly among internal RC oscillator watchdog oscillator external clock source provides optimal support of minimal power active mode with fast switching to maximum performance Idle and two different power down reduced power modes Improved wake up from Power down mode a LOW interrupt input starts execution Typical power down current is 1 pA total power down with voltage comparators disabled Active LOW reset On chip power on reset allows operation without external reset components A software reset function is also available Configurable on chip oscillator with frequency range options selected by user programmed flash configuration bits Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz Oscillator fail detect The watchdog timer has a separate fully on chip oscillator allowing it to perform an oscillator fail detect function Programmable port output configuration options quasi bidirectional open drain push pull input only High current sourcing sinking 20 mA on eight I O pins P0 3 to P0 7 P1 4 P1 6 P1 7 All other port pins have high sinking capability 20 mA A maximum limit is specified for the entire chip Port input pattern match detect Port 0 may ge
73. microcontroller with 8 bit ADC l O ports The P89LPC9201 9211 922A1 9241 9251 has four I O ports Port 0 Port 1 and Port 3 Ports 0 and 1 are 8 bit ports and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen as shown in Table 9 Table 9 Number of I O pins available Clock source Reset option Number of I O pins 28 pin package On chip oscillator or watchdog No external reset except during 18 oscillator power up External RST pin supported 17 External clock input No external reset except during 17 power up External RST pin supported 16 Low medium high speed No external reset except during 16 oscillator external crystal or power up resonator External RST pin supported 15 Port configurations All but three I O port pins on the P89LPC9201 9211 922A1 9241 9251 may be configured by software to one of four types on a bit by bit basis These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin 1 P1 5 RST can only be an input and cannot be configured 2 P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Quasi bidirectional output configuration Quasi bidirectional output type can be used as both an input and output without the need to reconfigure the port This is possible because when
74. n The POF flag will remain set until cleared by software Power reduction modes The P89LPC9201 9211 922A1 9241 9251 supports three different power reduction modes These modes are Idle mode Power down mode and total Power down mode Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC9201 9211 922A1 9241 9251 exits Power down mode via any reset or certain interrupts In Power down mode the power supply voltage may be reduced to the data retention supply voltage Vppr This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to Vppn therefore it is highly recommended to wake up the processor via reset in this case Vpp must be raised to within the operating range before the Power down mode is exited All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 34 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 18 3 7 19 P89LPC92X1 8 bit microcontroller with 8 bit ADC Some chip functions continue to operate and draw power during Power down mode increasing the total power used
75. n TCON is set causing an interrupt request If an external interrupt is enabled when the P89LPC9201 9211 922A1 9241 9251 is put into Power down or Idle mode the interrupt will cause the processor to wake up and resume operation Refer to Section 7 18 Power reduction modes for details All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 30 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 8 bit microcontroller with 8 bit ADC ENADCIO ADCIO ENADCI1 1 ADCH ENBIO BNDIO ENBH 1 BNDI1 1 EAD 1 RTCF gt KBIF ERTC EKBI RTCCON 1 WDOVF X Ll 2 EXO IE1 EX1 9 4 EBO EWDRT CMF2 CMF1 EC EA IEO 7 ml ETO es I ee ET1 TI and RI RI J gt ES ESR P 1 Bc pepe 5 Sha 1 P89LPC9241 9251 Fig9 Interrupt sources interrupt enables and power down wake up sources wake up if in power down interrupt to CPU 002aae429 P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 31 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 16 7 16 1 7 16 1 1 7 16 1 2 P89LPC92X1 8 bit
76. n transient limits on lo or log If oj loy exceeds the test condition Vo Vou may exceed the related specification 7 This specification can be applied to pins which have A D input or analog comparator input functions when the pin is not being used for those analog functions When the pin is being used as an analog input pin the maximum voltage on the pin must be limited to 4 0 V with respect to Vss 8 Pin capacitance is characterized but not tested 9 Measured with port in quasi bidirectional mode 10 Measured with port in high impedance mode 11 Port pins source a transition current when used in quasi bidirectional mode and externally driven from logic 1 to logic 0 This current is highest when V is approximately 2 V P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 53 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 8 bit microcontroller with 8 bit ADC 10 1 Current characteristics P89LPC92X1 Note The graphs provided are a statistical summary based on a limited number of samples and only for information purposes The performance characteristics listed are not tested or guaranteed 16 002aae363 l 18 MHz DD mA 12 12 MHz 8 8 MHz C e 6 MHz 2 MHz ne A 1 MHz 0 32 kHz 2 4 2 8 32 3 6 Vpp V Test conditions normal m
77. nd exits through RXD TXD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 4G of the CPU clock frequency Mode 1 10 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in special function register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the baud rate generator described in Section 7 22 5 Baud rate generator and selection Mode 2 11 bits are transmitted through TXD or received through RXD start bit logic 0 8 data bits LSB first a programmable 9 data bit and a stop bit logic 1 When data is transmitted the 9 data bit TB8 in SCON can be assigned the value of logic 0 or logic 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9th data bit goes into RB8 in special function register SCON while the stop bit is not saved The baud rate is programmable to either 1 6 or 1 2 of the CPU clock frequency as determined by the SMOD bit in PCON All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 37 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 22 4 7 22 5 7 22 6 7 22 7 7 22 8 P89LPC92X1 8 bi
78. nerate an interrupt when the value of the pins match or do not match a programmable pattern Controlled slew rate port outputs to reduce EMI Outputs have approximately 10 ns minimum ramp times Only power and ground connections are required to operate the P89LPC9201 9211 922A1 9241 9251 when internal reset option is selected Four interrupt priority levels Eight keypad interrupt inputs plus two additional external interrupt inputs Schmitt trigger port inputs Second data pointer Emulation support All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 2 of 75 P89LPC9201 9211 922A1 9241 9251 8 bit microcontroller with 8 bit ADC NXP Semiconductors 3 Ordering information Table 1 Ordering information Type number Package Name Description Version P89LPC9201FDH TSSOP20 plastic thin shrink small outline package 20 SOT360 1 leads body width 4 4 mm P89LPC9211FDH TSSOP20 plastic thin shrink small outline package 20 SOT360 1 leads body width 4 4 mm P89LPC922A1FDH TSSOP20 plastic thin shrink small outline package 20 SOT360 1 leads body width 4 4 mm P89LPC922A1FN DIP20 plastic dual in line package 20 leads 300 mil SOT146 1 P89LPC9241FDH TSSOP20 plastic thin shrink small outline package 20 SOT360 1 leads body width 4 4 mm P89LPC9251FDH TSSOP20 plastic thin shrink small outline package 20 SOT
79. nt source P3 0 to P3 1 l O Port 3 Port 3 is a 2 bit I O port with a user configurable output type During reset P89LPC92X1 Port 3 latches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 16 1 Port configurations and Table 12 Static characteristics for details All pins have Schmitt trigger inputs Port 3 also provides various special functions as described below All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 10 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC Table 3 Pin description continued Symbol Pin Type Description TSSOP20 DIP20 P3 0 XTAL2 7 O P3 0 Port 3 bit 0 CLKOUT O XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the flash configuration O CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the RTC system timer P3 1 XTAL1 6 lO P3 1 Port 3 bit 1 XTAL1 Input to the oscillator circ
80. o specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register Flash program memory General description The P89LPC9201 9211 922A1 9241 9251 flash memory provides in circuit electrical erasure and programming The flash can be erased read and written as bytes The Sector and Page Erase functions can erase any flash sector 1 kB or page 64 bytes The Chip Erase operation will erase the entire program memory ICP using standard commercial programmers is available In addition IAP and byte erase allows code memory to be used for non volatile data storage On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC9201 9211 922A1 9241 9251 flash reliably stores memory contents even after 100 000 erase and program cycles The cell is designed to optimize the erase and All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 43 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 28 2 7 28 3 7 28 4 7 28 5 P89LPC92X1 8 bit microcontroller with 8 bit ADC programmin
81. ode code while 1 executed from on chip flash using an external clock Fig 17 Ipp oper VS frequency at 25 C 16 002aae364 IDD 18 MHz mA 12 12 MHz 8 2 4 2 8 3 2 3 6 Vpp V Test conditions normal mode code while 1 executed from on chip flash using an external clock Fig 18 Ipp oper VS frequency at 40 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 54 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 P89LPC92X1 8 bit microcontroller with 8 bit ADC 16 002aae365 18 MHz IDD mA 12 12 MHz 8 8 MHz 6 MHz 4 T Ls ee 4 MHz 2MHz 1 MHz 0 32 kHz 2 4 2 8 3 2 3 6 Vpp V Test conditions normal mode code while 1 executed from on chip flash using an external clock Fig 19 Ipp oper VS frequency at 85 C 002aae366 5 0 18 MHz Ipp mA 4 0 12 MHz 3 0 8 MHz 2 0 6 MHz CE HN ORE TRU a 4 MHz 1 0 a 2 MHz 1 MHz 32 kH 0 0 z 2 4 2 8 3 2 3 6 Vpp V Test conditions Idle mode entered executing code from on chip flash using an external clock with no active peripherals with the following functions disabled real time clock and watchdog timer
82. of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 28 6 7 28 7 7 28 8 7 28 9 P89LPC92X1 8 bit microcontroller with 8 bit ADC ICP ICP is performed without removing the microcontroller from the system The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9201 9211 922A1 9241 9251 through a two wire serial interface The NXP ICP facility has made in circuit programming in an embedded application using commercially available programmers possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature Additional details may be found in the P89LPC9201 9211 922A1 9241 9251 User manual IAP IAP is performed in the application under the control of the microcontroller s firmware The IAP facility consists of internal hardware resources to facilitate programming and erasing The NXP IAP has made in application programming in an embedded application possible without additional components Two methods are available to accomplish IAP A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface PGM_MTP Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors pages security
83. oller with 8 bit ADC P89LPC92X1 Table 19 Abbreviations Acronym ADC BOD CPU CRC DAC EPROM EEPROM EMI PLL PWM RAM RC RTC SAR SFR UART WDT Description Analog to Digital Converter Brownout Detection Central Processing Unit Cyclic Redundancy Check Digital to Analog Converter Erasable Programmable Read Only Memory Electrically Erasable Programmable Read Only Memory Electro Magnetic Interference Phase Locked Loop Pulse Width Modulator Random Access Memory Resistance Capacitance Real Time Clock Successive Approximation Register Special Function Register Universal Asynchronous Receiver Transmitter WatchDog Time All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 70 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 15 Revision history Table 20 Revision history Document ID Release date Data sheet status Change notice Supersedes P89LPC92X v 2 1 20120827 Product data sheet P89LPC92X v 2 Modifications Section 7 19 Added When this pin functions as a reset input Table 12 Added Vpon P89LPC92X v 2 20101201 Product data sheet P89LPC92xX v 1 Modifications Table 11 Updated table Table 17 Updated l max value Section 7 4 Added low speed oscillator information Section 7 26 Added low speed
84. ooi xxxx xx0O SEL 00 0000 0000 FF 1111 1111 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 H KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 RST INT1 INTO SDA TO SCL RXD TXD iui B7 B6 B5 B4 B3 B2 B1 BO XTAL1 XTAL2 HU POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFU 1111 1111 POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 oo 0000 0000 P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3l 11x1 xx11 P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 ooll 00x0 xx00 P3M1 1 P3M1 0 03L ooxxxxt1 P3M2 1 P3M2 0 00L xxxx xx00 DAV 1 q 8 YUM 19 O1 UODOISIW 319 8 SJOJONPUODIWIIS dXN LGc6 Lt66 FV666 LE66 L06c60d 168d Jays Lep 19npoJd eL0z isnbny ZZ L Z ed sieuirejosip eba 0 1oefqns s jueuunoop S14 ui pepi oid uoneuuojul y GZ 40 9L X 60d 168d pamasa suu Ily ZLOZ 5h 8 dXN Table 4 indicates SFRs that are bit addressable Special function registers P89LPC9201 9211 922A1 Name PCON PCONA PSW PTOAD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON SSTAT SP TAMOD Description SFR addr Power control 87H register Power control B5H register A Bit address Program status DOH word Port 0 digital F6H input disable Reset source DFH register RTC control D1H RTC register D
85. put voltage LOW HIGH threshold voltage HIGH level input voltage hysteresis voltage LOW level output voltage HIGH level output voltage crystal voltage voltage on any other pin input capacitance LOW level input current input leakage current Conditions Vpp 3 6 V fos 12 MHz Vpp 3 6 V fos 18 MHz Vpp 3 6 V fos 12 MHz Vpp 3 6 V fos 18 MHz Vpp 3 6 V voltage comparators powered down Vpp 3 6 V of Vpp to ensure POR signal except SCL SDA SCL SDA only except SCL SDA SCL SDA only port 1 lo 20 mA Vpp 2 4 V to 3 6 V all ports all modes except high Z lot 3 2 mA Vpp 2 4 V to 3 6 V all ports all modes except high Z lon 20 pA Vpp 2 4 V to 3 6 V all ports quasi bidirectional mode lou 3 2 mA Vpp 2 4 V to 3 6 V all ports push pull mode lou 10 mA Vpp 2 4 V to 3 6 V all ports push pull mode on XTAL1 XTAL2 pins with respect to Vss except XTAL1 XTAL2 Vpp with respect to Vss Vi 04 V Vi Vit Vig Or Vin HLy Min 2 2l 3 3 4 5 6 e Vpp 0 3 Vpp 0 7 All information provided in this document is subject to legal disclaimers Typ 10 14 3 25 20 0 4Vpp 0 6Vpp 0 2Vpp 0 6 0 2 Vpp 0 2 Vni c 0 4 3 2 Max 15 23 ol 40 5000 0 5 0 3Vpp 0 7Vpp 5 5 414 0 45 5 Unit mA mA mA mA uA uA V S V pF uA uA NXP B V 2012 All rights
86. rces that affect these SFRs are power on reset and watchdog reset CLKCON register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 SAV 1 q 8 YUM 19 O1 UODOISIW 319 8 SJOJONPUODIWIIS dXN LS26 L7c6 LVcc6 LLC6 LOC60d 168d Jays Lep 19npoJd eL0z isnbny ZZ L Z ed sieuirejosip eba 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul Iv GZ 40 SC X 60d 168d pamasa suu Iv ZLOZ 5h 8 dXN Table 7 Extended special function registers PS9LPC9241 9251 1 Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary BODCFG BOD FFC8H BOICFG1 BOICFGO El configuration register CLKCON CLOCK Control FFDEH CLKOK XTALWD CLKDBL FOSC2 FOSC1 FOSCO B register TPSCON Temperature FFCAH TSEL1 TSELO 00 0000 0000 sensor control register RTCDATH Real time clock FFBFH 00 0000 0000 data register high RTCDATL Real time clock FFBEH 00 0000 0000 data register low 1 Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX DPTR A instructions are used to access these extended SFRs 2 The BOICFG1 0 will be copied from UCFG1 5 and UCFG1 3 when power on reset 3 CLKCON register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from
87. rogress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are pending at the start of an instruction the request of higher priority level is serviced All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 29 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 15 1 P89LPC92X1 8 bit microcontroller with 8 bit ADC If requests of the same priority level are pending at the start of an instruction an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used to resolve pending requests of the same priority level External interrupt inputs The P89LPC9201 9211 922A1 9241 9251 has two external interrupt inputs as well as the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These external interrupts can be programmed to be level triggered or edge triggered by setting or clearing bit IT1 or ITO in Register TCON In edge triggered mode if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle the interrupt request flag IEn i
88. roller with 8 bit ADC whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 16 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 73 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 18 Contents 8 bit microcontroller with 8 bit ADC 1 General description 1 7 18 3 Total Power down mode 35 2 Features and benefits ee 1 7 19 HGSGl erens ena kcee dor Noc ayude t a usus 35 24 Principal features 0 0 00 0 e eee e eee 1 7 19 1 Reset Meo MEM P 36 2 2 Additional features 000 000 2 720 Timers counters 0 and 1
89. rrupt is enabled In Power down mode or Total Power down mode the A D and temperature sensor do not function If temperature sensor or the A D are enabled they will consume power Power can be reduced by disabling temperature sensor and A D P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 50 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 9 Limiting values Table 11 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Tamb bias bias ambient temperature 55 125 C Tstg storage temperature 65 150 C loH 1 0 HIGH level output current per 20 mA input output pin loLq o LOW level output current per 20 mA input output pin Ivotot max maximum total input output current 100 mA Vstal crystal voltage on XTAL1 XTAL2 pin to Vss Vpp 0 5 V Vn voltage on any other pin except XTAL1 XTAL2 to Vss 0 5 45 5 V Ptot pack total power dissipation per package based on package heat 1 5 W transfer not device power consumption Vesp electrostatic discharge voltage human body model all pins 121 3000 3000 V charged device model all 700 700 V pins 1 The following applies to Table 11 a This product includes circuitry specifically designed for the protection of it
90. s internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over ambient temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 2 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 kO series resistor system frequency MHz 2 4 2 7 3 0 3 3 3 6 Vpp V 002aae351 Fig 16 Frequency vs supply voltage P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 51 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 10 Static characteristics 8 bit microcontroller with 8 bit ADC Table 12 Static characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified Symbol IpD oper Ipp idle IDD pd IpD tpd dv dt Vpor VppR Vin HL ViL Vih LH Vin Vhys VoL VoH Vxtal P89LPC92X1 Parameter operating supply current Idle mode supply current Power down mode supply current total Power down mode supply current rise rate power on reset voltage data retention supply voltage HIGH LOW threshold voltage LOW level in
91. s or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the cus
92. sing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC9201 9211 922A1 9241 9251 is designed to run at 18 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 28 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 13 7 14 7 15 P89LPC92X1 8 bit microcontroller with 8 bit ADC Memory organization The various P89LPC9201 9211 922A1 9241 9251 memory spaces are as follows DATA 128 bytes of internal data memory space 00H 7FH accessed via direct or indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area e IDATA Indirect Data 256 bytes of internal data memory space 00H FFH accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it e SFR Special Function Reg
93. t Counter with a divide by 32 prescaler In this mode the Timer register is configured as a 13 bit register Mode 0 operation is the same for Timer 0 and Timer 1 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register are used Mode 2 Mode 2 configures the Timer register as an 8 bit Counter with automatic reload Mode 2 operation is the same for Timer 0 and Timer 1 Mode 3 When Timer 1 is in Mode 3 it is stopped Timer 0 in Mode 3 forms two separate 8 bit counters and is provided for applications that require an extra 8 bit timer When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 36 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 20 6 7 21 7 22 7 22 1 7 22 2 7 22 3 P89LPC92X1 8 bit microcontroller with 8 bit ADC Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs are also used for the timer toggle outputs The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on
94. t microcontroller with 8 bit ADC Mode 3 11 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first a programmable 9 data bit and a stop bit logic 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the baud rate generator described in Section 7 22 5 Baud rate generator and selection Baud rate generator and selection The P89LPC9201 9211 922A1 9241 9251 enhanced UART has an independent baud rate generator The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGRO SFRs which together form a 16 bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate If the baud rate generator is used Timer 1 can be used for other timing functions The UART can use either Timer 1 or the baud rate generator output see Figure 10 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7 is cleared The independent baud rate generators use OSCCLK timer 1 overflow PCLK based Mee SEHE SS mi o baud rate modes 1 and 3 SMOD1 0 baud rate generator SBRGS 1 CCLK based 002aaa897 Fig 10 Baud rate sources for UART Modes 1 3 Framing error Framing error is reported in the status register SSTAT In addition if SMODO PCON 6 is logic 1 framing errors can be made available
95. t trigger input that also has a glitch suppression circuit Input only configuration The input only port configuration has no output drivers It is a Schmitt trigger input that also has a glitch suppression circuit Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit The P89LPC9201 9211 922A1 9241 9251 device has high current source on eight pins in push pull mode See Table 11 Limiting values Port 0 analog functions The P89LPC9201 9211 922A1 9241 9251 incorporates two Analog Comparators In order to give the best analog function performance and to minimize power consumption pins that are being used for analog functions must have the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port output into the Input Only high impedance mode Digital inputs on Port 0 may be disabled through the use of the PTOAD register bits 1 5 On any reset PTOAD 1 5 defaults to logic Os to enable digital functions Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76
96. tomer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purc
97. two byte sequence If PCLK is selected as the watchdog clock and the CPU is powered down the watchdog is disabled The watchdog timer has a time out period that ranges from a few us to a few seconds Please refer to the P89LPC9201 9211 922A1 9241 9251 User manual for more details All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 42 of 75 NXP Semiconductors P89LPC9201 9211 922A1 9241 9251 8 bit microcontroller with 8 bit ADC MOV WFEED1 0A5H MOV WFEED2 05AH M PCLK watchdog PRESCALER ma 8 BIT DOWN reset oscillator n A n My po eae eae ee XTALWD i D 1 1 I SHADOW REGISTER AAA v WDCON A7H PRE2 PREt PREO WDRUN woTOF WOCLK 1 Watchdog reset can also be caused by an invalid feed sequence or by writing to WDCON not immediately followed by a feed sequence Fig 14 Watchdog timer in Watchdog mode WDTE 1 002aae015 7 27 7 27 1 7 27 2 7 28 7 28 1 P89LPC92X1 Additional features Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred Care should be taken when writing to AUXH1 to avoid accidental software resets Dual data pointers The dual Data Pointers DPTR provides two different Data Pointers t
98. uit and internal clock generator circuits when selected via the flash configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the RTC system timer Vss 5 l Ground 0 V reference Vpp 15 l Power supply This is the power supply voltage for normal operation as well as Idle and Power down modes 1 Input output for P1 0 to P1 4 P1 6 P1 7 Input for P1 5 P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 11 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 8 bit microcontroller with 8 bit ADC 7 Functional description Remark Please refer to the P89LPC9201 9211 922A1 9241 9251 User manual for a more detailed functional description 7 1 Special function registers Remark SFR accesses are restricted in the following ways User must not attempt to access any SFR locations not defined Accesses to any defined SFR locations must be strictly for the functions for the SFRs e SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must
99. use an interrupt when the output value changes P89LPC92X1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 40 of 75 NXP Semiconductors P89LPC9201 921 1 922A1 9241 9251 8 bit microcontroller with 8 bit ADC The overall connections to both comparators are shown in Figure 13 The comparators function to Vpp 2 4 V When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 us The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service When a comparator is disabled the comparator s output COn goes HIGH If the comparator output was LOW and then is disabled the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag CMFn This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFn after disabling the comparator CP1 P0 4 CINTA comparator 1 oe P0 3 CIN1B CMP1 P0 6 P0 5 CMPREF Vref bg 3 Jo 7 interrupt CP2 change detect Es owe P0 2 CIN2A comparator 2 P0
100. ut detection has 3 independent functions BOD reset BOD interrupt and BOD FLASH BOD reset is always on except in total Power down mode It could not be disabled in software BOD interrupt may be enabled or disabled in software BOD FLASH is always on except in Power down modes and could not be disabled in software BOD reset and BOD interrupt each has four trip voltage levels BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are used as trip point configuration bits of BOD reset BOICFG1 bit and BOICFGO bit in register BODCFG are used as trip point configuration bits of BOD interrupt BOD reset voltage should be lower than BOD interrupt trip point BOD FLASH is used for flash programming erase protection and has only 1 trip voltage of 2 4 V Please refer to P89LPC9201 9211 922A 1 9241 9251 User manual for detail configurations If brownout detection is enabled the brownout condition occurs when Vpp falls below the brownout trip voltage and is negated when Vpp rises above the brownout trip voltage For correct activation of brownout detect the Vpp rise and fall times must be observed Please see Table 12 Static characteristics for specifications Power on detection The Power on detect has a function similar to the brownout detect but is designed to work as power comes up initially before the power supply voltage reaches a level where brownout detect can work The POF flag in the RSTSRC register is set to indicate an initial power up conditio
101. x series of devices e After power up all I O pins except P1 5 may be configured by software Pin P1 5 is input only Pins P1 2 and P1 3 are configurable for either input only or open drain Every output on the P89LPC9201 9211 922A1 9241 9251 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to Table 12 Static characteristics for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times Power monitoring functions The P89LPC9201 9211 922A1 9241 9251 incorporates power monitoring functions designed to prevent incorrect operation during initial power up and power loss or reduction during operation This is accomplished with two hardware functions Power on detect and brownout detect All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 2 1 27 August 2012 33 of 75 NXP Semiconductors P89LPC9201 921 1 922 A1 9241 9251 7 17 1 7 17 2 7 18 7 18 1 7 18 2 P89LPC92X1 8 bit microcontroller with 8 bit ADC Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level Enhanced browno
102. xxxx xx0O SEL 00 0000 0000 FF 1111 1111 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 i KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 RST INT1 INTO SDA TO SCL RXD TXD iui B7 B6 B5 B4 B3 B2 B1 BO XTAL1 XTAL2 H POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFU 1111 1111 POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 ool 0000 0000 P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3l 11x1 xx11 P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 oo 00x0 xx00 OQV 1 q 8 YUM 19 O1 UODOISIW 319 8 SJOJONPUODIWIIS dXN LS26 L7c6 LVcc6 L C6 LOC60d 168d Jays Lep 19npoJd eL0z isnbny 22 L z ed sieuirejosip ea 0 joefqns s jueuunoop siu ui pepi oid uoneuuojul y GZ 40 Z X260d 168d pemasa suu Ily ZLOZ 588 dXN Table 6 Special function registers P89LPC9241 9251 continued indicates SFRes that are bit addressable Name Description SFR addr P3M1 Port 3 output B1H mode 1 P3M2 Port 3 output B2H mode 2 PCON Power control 87H register PCONA Power control B5H register A Bit address PSW Program status DOH word PTOAD Port 0 digital F6H input disable RSTSRC Reset source DFH register RTCCON RTC control D1H RTCH RTC register D2H high RTCL RTC register D3H low SADDR Serial port A9H address register SADEN Serial port B9H address enable

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