Board User`s Manual "CPU Board XMC4500 SDRAM"
Contents
1. 1 0 2013 02 20 28 Board User s Manual Figure 26 Satellite Connectors USB OTG 1 QNO GND GND 3 004 0028 cOVO WL 0095d81N18 021 Ot0cX 101290000 910 981 lt a 5 160 82 10A8083 LOZA 2028 0070 68 2028 t 0 lt GND 0 00 900 zozo lz olta 161 olea 161 ol 8 J9d Tod ood vod 5395 e r 9 19 65 15 GND 00 Wd S3 510 15 9 9028 00 90 L Sse ou gt 0005 010 887 lsrzlsta lst olt a lo Ezo lt a aja SrSId 9714 6714 ered orta ood anv NIA 1 MEO VOLOESVH T 7 002 zs _ o r ece ta S S SQGA 5020 5080 5341 2129 4028 4 00 GND GND 001 00 8020 22. 19 Figure 16 eiai 20 17 USB 20 Figure 18 USB power generation Host OTG 21 Figure 19 Battery Holder for 22 Figure 20 XMC4500 Power Domains and Real Time 22 Figure 21 User LEDs and User BUTTONS nennen nene nea 23 Figure 22 Satellite 24 Figure 23 Satellite Connector Type COM _ 25 Figure 24 Satellite Connector Type HMI 26 Figure 25 Satellite Connector Type 27 Figure 26 Satellite Connectors 28 Figure 27 XMC4500 29 Figure 28 gt Power Debug Connector Reset 30 31 Figure 30 Component Placement 32 Board User s Manual 5 Revision 1 0 2013 02 20 CPU 45B V1 CPU Board XMC4500 SDRAM List of Figures 6 Revi
3. gt lt XLO 2Wd ME3X AQ 9 10 E01 314 ME0 VOLOESVE cero M 01 8 1 01 5579 01 gero Z0v0 4u00L 1579 184 300 915 81 Icva Gery tery Ove 2278 sero M 01 01 5579 OSSA 1d OSSA oss 8 ossa V ssp AH SSA 28 ssn ld ZOVO HEE ZOVO HEE cOPO HEE cOPO HEE COPO HEE SSE OU cOPO HEE SSE OU cOPO HEE SSE 20 0 44001 ZOvOMOL v aP D 8 5 Vo suonng ysnd OHOODISN 1 Css caso vu 94 9794 9794 1 1 Z0d OMS OQL Ted Dl SWI ASHL 80d v 9 S je6e7 GND GND LL LOPMS Falls 518 5 8 5 Vo 8 amp 9888 1 4 207 El 8Y Vz 3 ko I 5 5 OLY
4. 1 1 1 8 9 0 8 9 v 8 9 payes senje Aue 10 sajdurexo Aue Aue jojpue 10 jo se aq ou siu UBANG ou aNd ay 5357 3 gt 5 5 S E E gt ano _ 9 29 eg 99 9 t9 19 is 97974 29 c Yid 83 td vYId 6t Yid 4 ved lt 6 E 5 5719 E Zvtd L Z0ZX 5 5 5 vo Vo vo E 8 2 9 8 9 9 5 8 Cheryl 1 9 1 10 85 PW cLOZ YO YO LA 338 19599 ET Ud Production Data CPU 45B V1 CPU Board XMC4500 SDRAM Ineon infir 1 0 2013 02 20
5. 7 1 e lj 7 1 1 I M 7 1 2 Block E c 8 2 Hardware 9 21 9 22 12 23 eise hri 13 24 BOOt OPTION EET 13 2 5 Debug Interface rot nerd EE 14 2 5 1 On board USB 15 2 5 2 Cortex Debug Connector 10 16 2 5 3 Cortex Debug ETM Connector 20 17 2 6 Se al Flash emeret m 19 2 7 SDRAM m 20 2 8 20 2 9 22 2 10 User LEDs 23 2 11 asinos 23 2 12 Satellite CONMECIONS EDI MH 24 2 12 1 COM ETENIM 25 2 12 2 PAM COMM CUO raat LUE 26 2 12 3 AGT Satellite 0 27 3 PROGUCTION Data 1 27 3 1 gt 27 3 2 Component Placement and Geometry e
6. WWW 5 DWN 04508 9vivd 3 a OWIN sviva OWIN evivd ONN 1 4544 X19 2WIA ala 58 CPU 45B V1 Hardware Description CPU Board XMC4500 SDRAM V1 board allows interface expansion through HMI satellite cards The HMI satellite connector on the CPU 45B Infineon HMI Connector 2 12 2 CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Production Data 2 12 3 ACT Satellite Connector The ACT satellite connector on the CPU 45B V1 board allows interface expansion through ACT satellite cards yp lt tim ajo S amp 5 lt 9 5 5 518 ve el ev 219 9 5 5 2 s SS oll oll ol o lt lt a 5 8 5 5 5 5 5 5
7. hnology x500 Www sec USB OTG _ oe gt 9 USB _ 3 Linear 9 3 Voltage i TONA BUTTONZ PowerScale Regulator in 2 60 ir qu 4 P aN 1151904 Power indicating LEDs Power emf Figure 3 Powering option To indicate the power status of CPU 45B V1 board three power indicating LED s are provided on board see Figure 3 The LED will be when the corresponding power rail is powered Table 1 Power status LEDs LED Reference Power Rail Voltage Note V401 VDD5 5V Must always be ON V402 VDD5USB 5V ON if powered by USB OTG connector X203 OFF in all other supply cases V403 VDD3 3 3 3V Must always be USB OTG wer wer wer LED LED LED CPU Board XMC4500 SDRAM Aq CPU_45B V1 5 gt VDDSUSB 5 VDD5 5 VDD3 3 3 3V gt ka VDD3 3 On Board Devices 0300 oie JP300 VDD5USB 8 legulato VDD3 3 HMI Sat Sat ACT Sat Connector Connector Connector Power_Block emf Figure 4 Block Diagram Of Power Supply Board User s Manual 10 Revision 1 0 2013 02 20 CPU 458 1 Infi neon CPU Board XMC4500 SDRAM Hardware Description Hitex PowerScale probe is provided on the CPU 45B V1 board to measure the power consumption of the X
8. 8 lt lt lt lt lt lt lt glg MIELE P 2 5 lt gt 5 2 352 lt 4 5 lt z 1 2 E ale lt lt lt 2292 34 5 lt lt 5 apa lt 5 gt a E 5 5 5 53182 lt m P m o w N w w a w BR a D a a o Satellite Connector Pin m m w w w 5 w a o w o a o M o o ajo gt 5 gig 2 5 8 5 5 5 5 alata 5 alg 9982668 ala gt 5 55 5 ala 2 gt gt gt gt gt 5 212 5 5 5 8 2 2 2 ajaja Q9 050 PWMP DSD PWMN DSD MCLK3 nc nc nc nc nc nc nc P15 4 Input P4 7 AGND VADC G1CH1 nc nc VADC GOCHO nc VADC G3CH6 VADC G3CH7 nc nc nc nc nc nc CCU430UTO CCU430UT1 1 0 1 1
9. Debug USB Connector ACT User LEDs Satellite and User Connector Butt On board COM Bist Debugger Satellite 1 2 ConnEctor 44 2 2 Na BUTTON 2 2 4 05 18 ae ey ry SDRAM T 22 2 ce x 0 4 x Boot Option Switch Power indicatin Debug LEDs 9 Connectors Reset Circuit Debug Connectors Battery Holder Potentiometer HMI Satellite Connector Board Interfaces emf Figure2 CPU Board XMC4500 SDRAM CPU 45B V1 2 1 Power Supply The CPU 45B V1 board can be powered via either of the USB plugs 5 V however there is a current limit that can be drawn from the host PC through USB If the CPU 45B V1 board is used to drive other satellite cards e g AUT ISO V1 or GPDLV V2 and the total current required exceeds 500 mA then the board needs to be powered by a satellite card which supports external power supply like e g AUT ISO V1 MOT GPDLV V2 COM ETH V1 The typical current drawn by the CPU board without any satellite cards connected is about 220 mA 5V For powering the board through an USB interface connect the USB cable provided with the kit to either of the Micro USB connector on board as shown in Figure 3 Board User s Manual 9 Revision 1 0 2013 02 20 CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description Debug USB
10. Cinfineon Hexagon Application Kit For XMC4000 Family CPU_45B V1 CPU Board XMC4500 SDRAM Board User s Manual Revision 1 0 2013 02 20 Microcontroller Edition 2013 02 20 Published by Infineon Technologies AG 81726 Munich Germany 2013 Infineon Technologies AG Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of tha
11. GND 99 099 lt 99 a E 92 S S 5 vo 9 300999 gt e 905 gt 300999 LOATH Cox mo 8 p HE pt fce SITS 5 S S lt 8 L9poN Production Data CPU 45B V1 CPU Board XMC4500 SDRAM Ineon infir 1 0 2013 02 20 Rev 30 Board User s Manual Figure 28 Power Debug Connector Reset SDRAM oso ZOvOMOL 6 82 3007915675 66 20 WOD si euuoosip pue sind ejeis 19522 19 661 pieoq uo ay sdeay pue jeubis sind je66ngeq 19502 preoq uo aui sdeay pue OY S eufis sjoeuuoosip peusis sind S10j2euuo SI0W09 D zon gt 807 5070 01 5070 01 0 0 3400 0075
12. 16 Board User s Manual CPU 458 1 Infi neon CPU Board XMC4500 SDRAM Hardware Description XMC 4508 p U300 Op 005 S 4 E SES Cortex Debug Ls Ei IC 10Pin Conn emf Figure 12 Cortex Debug Connector 10 pin Layout 2 5 3 Cortex Debug ETM Connector 20 pin The CPU 45B V1 board supports Serial Wire Debug operation and Instruction Trace operation through the 20 pin Cortex Debug ETM Connector The board does not support Serial Wire Viewer operation through the Cortex Debug Connectors by default because the required SWO pin mapped to P2 1 is used for the connection to the on board SDRAM If Serial Wire Viewer operation is required anyway the resistor R404 needs to be assembled JTAG operation additionally would require the TDI 7 signal By default the TDI signal is disconnected from the Cortex Debug Connectors a not assembled resistor R410 because the pin 20 7 can be used by the on board SDRAM by Actuator boards connected to the ACT satellite connector and by boards connected to the COM satellite connector Cortex Debug ETM Connector 20 pin SWDIO TMS GND SWDCLK TCK GND SWO TRACECTL NC KEY NC EXTb TDI NC GNDDetect nRESET GND TgtPwr Cap TRACECLK GND TgtPwr Cap TRACEDATA O GND TRACEDATA 1 GND T
13. of Microsoft Corporation FlexRay is licensed by FlexRay Consortium HYPERTERMINAL of Hilgraeve Incorporated IEC of Commission Electrotechnique Internationale IrDA of Infrared Data Association Corporation ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION MATLAB of MathWorks Inc MAXIM of Maxim Integrated Products Inc MICROTEC NUCLEUS of Mentor Graphics Corporation Mifare of NXP MIPI of MIPI Alliance Inc MIPS of MIPS Technologies Inc USA muRata of MURATA MANUFACTURING CO MICROWAVE OFFICE MWO of Applied Wave Research Inc OmniVision of OmniVision Technologies Inc Openwave Openwave Systems Inc RED HAT Red Hat Inc RFMD RF Micro Devices Inc SIRIUS of Sirius Satellite Radio Inc SOLARIS of Sun Microsystems Inc SPANSION of Spansion LLC Ltd Symbian of Symbian Software Limited TAIYO YUDEN of Taiyo Yuden Co TEAKLITE of CEVA Inc TEKTRONIX of Tektronix Inc TOKO of TOKO KABUSHIKI KAISHA TA UNIX of X Open Company Limited VERILOG PALLADIUM of Cadence Design Systems Inc VLYNQ of Texas Instruments Incorporated VXWORKS WIND RIVER of WIND RIVER SYSTEMS INC ZETEX of Diodes Zetex Limited Last Trademarks Update 2011 02 24 Template IFX Template 2011 02 24 dot CPU 458 1 CPU Board XMC4500 SDRAM Table of Contents Infineon Table of Contents 010110017 mm
14. 2 212 GND GND GND GND Figure 18 USB power generation Host OTG mode In the host only mode and OTG mode the CPU 45B V1 board is capable of supplying power to the connected device e g USB mouse The board has a power switch which is controlled by the USB BUSDRIVE signal of XMC4500 USB BUSDRIVE is mapped to Port active high In the Host OTG mode a low active FAULT signal indicates to XMC4500 via HIB IO 0 signal if more than 500 mA current is drawn by the external device HIB IO 0 signal is used as general purpose input pin for this implementation Diode V200 will allow powering the board through USB in all USB modes via e g a PC Board User s Manual 21 Revision 1 0 2013 02 20 e CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 9 RTC The XMC4500 CPU has two power domains the Core Domain and Hibernate Domain The Core Domain VDDP pins is connected to the VDD3 3 rail on board LDO voltage regulator generates VDD3 3 3 3 V from VDD5 5 V The Hibernate Domain is powered via the auxiliary supply pin VBAT which is supplied by either a 3 V coin cell size 1216 1220 1225 plugged into the battery holder or 3 3 V VDD3 3 generated by the on board voltage regulator Battery Holder Batt emf Figure 19 Battery Holder for Coin Cells The Real Time Clock is located in the hibernate domain The XMC4500 uses the HIB IO 1
15. 8 5 5 5 5 2 2 gt 5 8 6 5 5 GND GND e Z0v0 4U00L _ i vaa avaa b E alls ssa Ha 5 5 2159 m 5 S 8 E SNL ee SWIM 6 E SI Kjddng OL E 5 lt 5 E XOIM 00 S 19804 FISdOaM 5 E 58 R 5 6 e IH aS S ZXZ E S ZHNZ L Sif asn ZOPOJHEEL 05H SSN 6090 8016 pose 0 i ZOP HEE 1059 ge usn Qs 5 m 9 gt oo99a8 NNG abs e OLY y gt 7 9 2009 aye 2 Ovid 7 5 d J3HV 08 5 8 5 204 09 enaad onaga So 0 704019 13538 sIJSSH 8 9 0d OldO 3ALOVXL a 06 SWL WI axs uU ood AMS ed 6 voa _ E 4 0 0d Q0XG axy AMS paar ona r cog LON Layn nd no euorippe Joajap 1 3538 S 5 04 lt 55 9 zy 509 5 si ds x OISN ISON Our peio
16. closed by resistor 34 Infineon BK 885 BLM18PG600 ESD8VOL2B 03L HSEC8 MATING CARD IFX1763 PADNOP LED GE D 0603 LED GN D 0603 LED RT D 0603 I842816400F 7BL NC7WZ07P6X POTI 10K VERT 52 10 1 2750 S25FLO32POXMFIO1 TMPS2 SMD TPS2051BDBV 2 XMC4200_QFN48 XMC4500_LFBGA144 ZX62 AB 5PA no ass no ass no ass 0R 0603 no ass 4k7 0402 no ass 10k 0402 no ass 10nF 0402 no ass 33R 0402 no ass no ass 0R 0402 gt 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Board User s Manual
17. installed on your computer Please check Install J Link Serial Port Driver when installing the latest J Link driver see Figure 9 2 Serial Wire Viewer operation does not work during use of the on board SDRAM Choose optional components that should be installed Choose options for creating shortcuts Create entry in start menu Add shortcuts to desktop lt Back Cancel Figure9 Installation of Serial Port Driver The on board debugger can be accessed through the Debug USB connector shown in Figure 10 The Debug LED V502 shows the status during debugging J Link Tec inology x50 M www seg er com 9 s 2 a i Debug USB Debug LED DEBUG wee 5 LED1 P5 2 JP30Q 2294 2 gt EX S gt m 5 4 U300 00 Debug emf Figure 10 On Board USB Debugger When using an external debugger connected to the 10pin 20pin Cortex Debug Connector the on board debugger is switched off When using the USB virtual COM port function of the on board debugger connected to P1 4 and P1 5 of the XMC4500 the UART interface to the COM satellite is disabled through the switches U301 and U306 Board User s Manual 15 Revision 1 0 2013 02 20 e CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 5 2 The CPU
18. P6 6 3 5 6 5 3 10 5 P3 11 P3 12 P15 4 4 7 VAGND P14 9 nc nc P14 0 nc P15 14 P15 15 nc nc nc nc nc nc P4 6 P4 5 Figure 25 Satellite Connector Type ACT 1 7 also be used for JTAG Debugging TDI 2 P0 8 is used as TRST in order to enable JTAG Debug 3 This pin is connected with the satellite connector via an analog switch 4 This ADC input does not support Out of Range Detection 5 This pin is disconnected by a solder jumper 6 Support High Resolution PWM 3 Production Data 3 1 Schematics This chapter contains the schematics for the CPU board Satellite Connectors USB OTG XMC4500 Power Debug Connector Reset On board Debugger The board has been designed with Eagle The full PCB design data of this board can also be downloaded from www infineon com xmc dev Board User s Manual 27 Revision 1 0 2013 02 20
19. Rev 29 Board User s Manual Figure 27 0 6 QNO 4 5 8 8 8 8 lw I 5 gt 5 5 5 8 5 5 5 5 5 5 5 5 E 5 5 5 5 5 9 S amp 5 5 5 8 9 8 8 5 fo 5 2 irgi g 5 5 lt 5 lt 5 ae J5 5 o 3 5 2070 4400 1220 1014 04 0146 5 2 Sted 5 9 T eo 20 d dioH 52022 2 858 2 elle Zoen f 8 5 R R R lt lt gt HSV14 1456 Ted Ted 58 SLS SUS 91 9 2 9 9 pre 1 Qoo VOR SW 25 55 518 og g e 5 8 58 5 S D D 22 G37 Old IO 2070 3U001 1V8A W 9055 20 0 39001 0719170171 lg ol sa 117019008 aN9 8020 9080 01 3 01 Logan 8sn 850 5 0 Ol 2
20. digital converter The potentiometer is connected to the analog input GO CH1 P14 1 The analog output of the potentiometer ranges from 0 V to 3 3 V Table 10 Potentiometer Potentiometer Connected to Port Pin 0 P14 1 GO CH1 Group 0 channel 1 Board User s Manual 23 Revision 1 0 2013 02 20 CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 12 Satellite Connectors The CPU_45B V1 board provides three satellite connectors for application expansion by satellite cards e COM satellite connector Communication e HMI satellite connector Human Machine Interface e ACT satellite connector Actuator Note Satellite cards shall be connected to their matching connectors only For e g COM satellite cards shall be connected to COM satellite connector only J Link Technolo COM Satellite JENA eod ACT Satellite Connector Connector TTON2 2 1 0 10 76 Rise ae X4MC4500 0 HMI Satellite Connector Satt Conn emf Figure 22 Satellite Connectors Board User s Manual 24 Revision 1 0 2013 02 20 Revision 1 0 2013 02 20 25 Board User s Manual log switch via an ana th the satellite connector ted wi by solder jumper SJ1 IS pin IS connec Thi Attent
21. romm Lo 9 9 GND 20 0 44001 avo QNs esdWLL Li lt 0 5 1 0070 80 L Sse cOvOPI0Zc S080 A0 0 075 fue jojpue pares sanje Aue 10 sajdlurexe fue 01 1294592 uM 20 jo e aq ou eus LEA 5 GND 8 9 5 8 C07 1 LA 8St 6ngeq EN 61060070 LA GND GND re ma re S8 aS 2 9 8 6 8 2 2195 2 95 5 SIRE S 8 8 sane LAS sang sanz 16 5 5 5 Sola 5 88 95 8 S E 8 lt lt gt o o o a 5 sjujodjse 37 904 5070 4401 slic 9179 S 9 lt mE A a 008 0501 8 5 89908 NE 0 7070 J a ae 205 5 BLS QN9 QN9 2 E IE 5 m TT 242 So 8 oils 5 e 5 g S 5 2 8 8 8 2 dONGVd 9 S S 4X3 Bye 5090 30 rawasnas 170 Lorn lt Production Da
22. signal active low to shutdown the external LDO voltage regulator which generates VDD3 3 core domain Even if the Core Domain is not powered the Hibernate Domain will operate if VBAT is available The RTC keeps running as long as the Hibernate Domain is powered via the auxiliary supply VBAT The is capable to wake up the whole system from Hibernate mode by setting HIB IO 1 to high XMC4500 Hibernate Control Internal OSC Battery 1 1 p Figure 20 XMC4500 Power Domains and Real Time Clock Board User s Manual 22 Revision 1 0 2013 02 20 CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 10 User LEDs and User Button The port pins P5 2 and P1 1 of XMC4500 on the CPU 45B V1 board are connected to the LEDs V300 and V301 respectively More User LED s are available through the I2C GPIO expander on most of the satellite cards Table 8 User LEDs LED Connected to Port Pin LED1 V300 GPIO P5 2 LED2 V301 GPIO P1 1 Two User Buttons SW401 and SW402 are connected to P5 10 and P0 10 of XMC4500 Table 9 User Buttons Button Connected to Port Pin Button1 SW401 GPIO P5 10 Button2 SW402 GPIO 0 User LED1 LED2 4 BUTTON BUT n 2 2 User NS be 1 Buttons Button LED emf Figure 21 User LEDs and User Buttons 2 11 Potentiometer The CPU 45B V1 board provides a potentiometer for ease of use and testing of the on chip analog to
23. 04 0d 504 90 80 60 phd jddng Dojeuy rebia ESSA ZSSA ISSA OSSA SNL XOL 15804 1 VLX 91H ANOVA VSSA 2914 6919 91914 iid oio id i6 T gt _ QNO QNO aNd ge ge ge 58 me mo WI E JIL 5 amp 5 SIJS3H S SN S S ZHW2 L 2020 509073015 ZH389 2 1060 umb 2020730001 1159 2070730001 6059 o S v 9 5 t 2 2525 sT zs s 5 amp 5 5 g 5 E 3 E a 5 8 aNd 5 2 3 5 pra gU 20 612 a W L E 330 758 2 5 S lt o 1000 suondo 1008 gt 7 gt 5 99 ood Yyoums pieog LOY leuis 89211 Vid rnor gt 4 2 Jayn Wow WOO 8 4 5 5 8 CLO OSE LA 8St EN 61060070 LA 00999 Leron asa pj
24. 04 V405 24 1 BAV70 Diode SOT23 3 Infineon V406 25 1 BC858C Transistor SOT23 3 Infineon Q404 Revision 1 0 2013 02 20 33 Board User s Manual CPU 45B V1 CPU Board XMC4500 SDRAM Production Data X402 L201 L300 L301 L500 V201 V500 X200 X201 X202 U401 V300 V301 V401 V402 V403 V502 407 0430 0501 8300 400 0302 5400 5401 SW402 0200 X401 U500 0300 203 500 501 404 405 406 407 R417 R427 R205 R413 C503 R404 R410 JP300 42 SJ3 44 45 Revision 1 0 2013 02 20 Battery Holder 12mm Coin Cell Ferrite Bead 0603 Murata Diode TSLP 3 1 Infineon Connector Edgecard Samtec Voltage Regulator 3 3V LDO Infineon LED yellow LED green LED red Synchronous Dynamic RAM ISSI IC Dual Buffer OD SC70 6 Potentiometer KO9K1130A8G ALPS Connector FTSH 110 01 L DV K P Samtec IC qSPI Flash Memory SPANSION Switch tactile IC Power Switch SOT23 5 Connector FTSH 105 01 LM DV K w o pin 7 Samtec Connector FLE 103 01 G DV Samtec IC XMC4200 QFN48 Infineon IC XMC4500 LFBGA144 Infineon Connector Micro USB Hirose Pinheader 4 pin 0 1 TH Pinheader 1 pin 0 1 TH Resistor Resistor Resistor Capacitor Resistor Pinheader 3 pin 0 1 TH Hitex PowerScale Solder Bridge open Solder Bridge
25. 12 Revision 1 0 2013 02 20 CPU 458 1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 3 Clock Generation An external 12 MHz crystal provides the clock signal to the XMC4500 microcontroller The drive strength of the oscillator is set to maximum by software in order to ensure a safe start up of the oscillator even under worst case conditions A serial 510 Ohm resistor will attenuate the oscillations during operations For the RTC clock a separate external 32 768 kHz crystal is used on board F1 Q301 m _ a 2 8313 5108 0603 Q302 E 12 2 5 3 2 2 5 XTAL1 RESET B IPORST TA amp TMS eg ae 58 918 Ol OK Ol vsso 2 VSS1 vssa M12 XMC4500 LFBGA144 lo GND 5 GND GND GND GND lt Figure7 Clock Generation Circuit 2 4 Boot Option During power on reset the XMC4500 latches the dip switch SW300 settings the and the TMS pin Based on the values latched different boot options are possible Table 3 Boot Options Settings BSL TMS CAN UART TCK Boot Option OFF 1 UART 0 Normal Mode Boot from flash ON 0 UART 0 ASC BSL Enabled Boot from UART OFF 1 CAN 1 BMI Customized Boot Enabled ON 0 CAN 1 CAN BSL Enabled Boot from CAN EL 22300 313 1522 Boot Option Switch Boot Switch emf Figure8 Boot Options Switch Board User s Manual 13 Revision 1 0
26. 2013 02 20 e CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 5 Debug Interface The CPU 45B V1 board supports debugging via 3 different channels e On board Debugger e Cortex Debug Connector 10 pin e Cortex Debug ETM Connector 20 pin The Hexagon Application Boards are designed to use Serial Wire Debug as debug interface JTAG debug is not supported by default because the GPIO 7 where the required TDI function is mapped to also is used by the on board SDRAM device and various Actuator boards connected to the ACT satellite connector Attention It is strongly recommended not to use JTAG debug mode especially if satellites boards are connected which uses the GPIO 0 7 For the same reason also do not use the on board debugger in JTAG mode If you want to use the JTAG debug mode through the cortex debug connectors X400 X401 anyway enable the JTAG interface of the device by assembling the pull up resistor R427 4 7 Ohm and the resistor 0 0 33 Ohm Board User s Manual 14 Revision 1 0 2013 02 20 e CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 5 1 On board USB Debugger The on board debugger 1 supports e Serial Wire Debug e Serial Wire Viewer 2 e Full Duplex UART communication via a USB Virtual COM 1 Newer firmware versions of the on board debugger require the latest J Link driver V4 62 or higher and a Serial Port Driver CDC driver
27. 45B V1 board supports Serial Wire Debug operation through the 10 pin Cortex Debug Connector By default the board does not support Serial Wire Viewer operation through the 10 pin Cortex Debug Connector because the required SWO pin mapped to P2 1 is used for the connection to the on board SDRAM If Serial Wire Viewer operation is required anyway the resistor R404 needs to be assembled JTAG operation additionally would require the TDI 7 signal By default the TDI signal is disconnected from the Cortex Debug Connectors by a not assembled resistor R410 because the pin 7 can be used the on board SDRAM by Actuator boards connected to the ACT satellite connector and by boards connected to the COM satellite connector Cortex Debug Connector 10 pin Cortex Debug Connector 10 pin 2 SWDIO TMS SWDCLK TCK SWO NC TDI nRESET cortex 10pin emf GND GND KEY GNDDetect Figure 11 Cortex Debug Connector 10 pin Table 4 Cortex Debug Connector 10 Pin Pin No Signal Name Serial Wire Debug JTAG Debug 1 VCC 3 3 V 3 3 V 2 SWDIO TMS Serial Wire Data I O Test Mode Select 3 GND Ground Ground 4 SWDCLK TCK Serial Wire Clock Test Clock 5 GND Ground Ground 6 SWO TDO Trace Data OUT Test Data OUT 7 KEY KEY KEY 8 NC TDI Not connected Test Data IN 9 GNDDetect Ground Detect Ground Detect 10 nRESET Reset Active Low Reset Active Low Revision 1 0 2013 02 20
28. MC4500 device Table 2 Power Measurement Jumper Function Description JP300 PowerScale A Hitex PowerScale probe can be connected for current sensing the VDD3 3 CPU power source Default pos 1 2 closed Note On the PCB there is a shorting trace between pin 1 2 This trace has to be cut first before using PowerScale Pin 3 is GND Board User s Manual 11 Revision 1 0 2013 02 20 e CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 2 Reset A reset signal connected to the low active PORST pin of the target CPU 0300 can be issued by anon board Reset Button SW400 RESET anon board debug device 0500 e an external debugger connected to either Cortex Debug connector X400 or X401 The RESET signal is routed to all satellite connectors The reset circuit includes a red LED V407 to indicate the reset status The Reset LED V407 will be ON during active reset state and will be OFF if reset is not active Be aware that PORST is a bidirectional reset pin of the XMC4000 family which can also be pulled low by the XMC4000 device itself e a a gt R419 003 3 10 0402 R422 E 10K 0402 SW400 FI TMPS2 SMD L S LED RT D 0603 V407 0 0402 GND Figure5 Reset Circuit XMC4500 SN lt 0300 Reset LED Reset Button RST emf Figure6 Reset LED and Reset Button Board User s Manual
29. RACEDATA 2 GND TRACEDATA 3 cortex 20pin emf Figure 13 Cortex Debug ETM Connector 20 pin Board User s Manual 17 Revision 1 0 2013 02 20 CPU 45B V1 CPU Board XMC4500 SDRAM Hardware Description Infineon Table 5 Cortex Debug ETM Connector 20 Pin Pin No Signal Name Serial Wire Debug JTAG Debug 1 VCC 43 3 V 43 3 V 2 SWDIO TMS Serial Wire Data I O Test Mode Select 3 GND Ground Ground 4 SWDCLK Serial Wire Clock Test Clock 5 GND Ground Ground 6 SWO TDO Trace Data OUT Test Data OUT 7 KEY KEY KEY 8 NC TDI Not connected Test Data IN 9 GNDDetect Ground Detect Ground Detect 10 nRESET Reset Active Low Reset Active Low 11 GND TgtPwr Cap Ground Ground 12 TRACECLK Trace Clock Trace Clock 13 GND TgtPwr Cap Ground Ground 14 TRACEDATA 0 Trace Data 0 Trace Data 0 15 GND Ground Ground 16 TRACEDATA 1 Trace Data 1 Trace Data 1 17 GND Ground Ground 18 TRACEDATA 2 Trace Data 2 Trace Data 2 19 GND Ground Ground 20 TRACEDATA S3 Trace Data 3 Trace Data 3 XMC4500 5 C 0300 7 3 0 Cortex Debug ETM Connector 20 Pin 20 Pin_Conn emf Figure 14 Cortex Debug ETM Connector 20 pin Layout Board User s Manual 18 Revision 1 0 2013 02 20
30. cards can supply power to CPU board backup battery Board User s Manual 7 Revision 1 0 2013 02 20 Jum CPU 458 1 Infi neon CPU Board XMC4500 SDRAM Overview 1 2 Block Diagram Figure 1 shows the functional block diagram of the CPU 45B V1 board For more information about the power supply please refer to chapter 2 1 The CPU board has got the following building blocks Satellite Connectors COM HMI ACT 2User LEDs connected to GPIOs P5 2 and P1 1 2 User Buttons connected to GPIOs P5 10 and 10 Quad SPI flash memory 32 Mbit Synchronous Dynamic RAM SDRAM 64Mbit 2 Cortex Debug Connectors Variable resistor POTI connected to GPIO P14 1 USB On The Go Connector Micro USB On board Debugger via USB connector Micro USB USB Debug Debug Debug ETM USB 10pin 20pin OTG CPU Board XMC4500 SDRAM 2xButton CPU_45B V1 On board Debugger 5 XMC4200 2xLED CAN ENCODER EXTBUS DSMOD cc OPAMP CAN 9 SENSOR RS485 2xISOFACE 126 IOEX Block Diag emf Figure 1 CPU 45B V1 Board Block Diagram Board User s Manual 8 Revision 1 0 2013 02 20 CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 Hardware Description The following sections give a detailed description of the hardware and how it can be used USB OTG Connector I Link Tec inology www se er com
31. e CPU 45B V1 Infineon CPU Board XMC4500 SDRAM Hardware Description 2 6 Serial Flash Memory The CPU 45B V1 board has 32Mbit serial flash memory interfaced to XMC4500 through a SPI interface The SPI interface can be configured as single dual or quad SPI Table 6 Quad SPI Signals Pin No Signal Name Signal Description P0 13 CLK Clock P3 3 CS Active Low Chip Select P3 15 Data Input of Flash MTSR P3 14 DO Data Output of Flash MRST 0 14 Data I O Data Input Output 0 15 Data Data Input Output m 8 8 gt gt C 02 HOLD 103 5 gt 00 Di IO1 DO S25FL032POXMFIO1 C321 00 0402 GND GND Figure 15 Quad SPI Flash Interface Board User s Manual 19 Revision 1 0 2013 02 20 CPU 458 1 Infi neon CPU Board XMC4500 SDRAM Hardware Description 2 7 SDRAM The CPU 45B V1 board has a 64 Mbit SDRAM interfaced to the XMC4500 The SDRAM interface is shown in Figure 16 VDD3 3 VDD3 3 CSO pullup R431 1S42S16400F 7BL 100nF 0402 100nF 0402 C436 100nF 0402 C435 100nF 0402 C434 100nF 0402 C433 100nF 0402 C432 100nF 0402 C431 C430 GND GND Figure 16 SDRAM Interface 2 8 USB The 4500 supports USB interface in host only mode device only mode or as an OTG Dual Role Device DRD In USB device mode power is expected through VBUS pi
32. ejes si Ads X Ing OISN se 0 6 gt oa S zd 01n0d yndjno se SSIIWO Ezd gs 9 Sa va Loon 98 146 2 005 22 0 1d 0013S 110 so STR FId L0OW10S LNO XUI S id 01n0G ISOW SWI v Id g0Xd OSIN 8 ODON 0 3999409 8 2 9 5 6 Ineon f Infi CPU 45B V1 CPU Board XMC4500 SDRAM Production Data 1 R430 5 Coo f 659 QD ee SJ2 Che C319 R503 e 2 H HS amp gt 2 f 7 Revision 1 0 2013 02 20 R504 e R505 512 070417 _ 44 1 86 60 Infineon 3 2 Component Placement and Geometry _ 5 0 4 0301 0306 C310 0322 O E 0 1470 E 25 08 80 6 Angaben in mm 0 1 32 Figure 30 Component Placement and Geometry Board User s Manual CPU 45B V1 CPU Board XMC4500 SDRAM Infineon Production Data Bill of Mate
33. ion lect signal for the on board EEPROM and therefore disconnected ip se d as ch is pin is use Thi Attention Figure 23 Satellite Connector Type COM TT Ed TT Ed JINX uonound JINX CPU 458 1 SDRAM so so 28 0049 WOD 49 WOO vas 2259 145 1959 145 0252 145 25 axy 25 257 GASH INY HLI INY HLI INY HLI INY HLI INY HLI 5 52 1459 52 1456 215 1456 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 2141618 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 53 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 0 Satellite 13538 049 155 ATS 145 ASU 145 YSL 145 axy 8 INY HLI INY INY INY H13 GASMH 146 1459 1459 1455 19534 9d uonpund JINX CPU 458 1 SDRAM utd JINX e g COM_ETH V1 V1 board allows interface expansion through COM satellite cards The COM satellite connector on the CPU 45B COM Connector 2 12 1 Hardware Description gt T0 50 Og gt lt Y 6 I
34. n 1 of X203 from an external host e g PC When the current consumption of the application running on the Hexagon Application system is higher than 500 mA power from an external source through satellite cards shall be used Note Some PCs notebooks or hubs have a weak USB supply which is not sufficient for proper supply In this case use an external 5 Volt power supply or a powered USB hub VDD5USB i lt e XI R202 33R 0402 N R203 33R 0402 X203S 201 ESD8VOL2B 03L C200 1M 0402 100nF 0402 GND GND GND GND Figure 17 USB Connector The USB ID pin of the USB connector is connected to the port pin P15 2 of the XMC4500 This pin must be polled by software because this pin does not support USB ID detection An OTG device will detect whether a USB 3 0 Micro A or Micro B plug is inserted by checking the ID pin When the ID FALSE Micro A connector is plugged and when ID TRUE a Micro B connector is plugged in When ID is true the XMC4500 acts as USB host else as USB device Board User s Manual 20 Revision 1 0 2013 02 20 e CPU 45B V1 Infi neon CPU Board XMC4500 SDRAM Hardware Description Table 7 USB micro AB connector Pinout Pin No Pin Name Pin Description 1 VBUS 5V 2 D Data Minus 3 D Data Plus 4 ID Identification 5 GND Ground 8 B Ad 8 AB e a gt 5 gt gt gt 2 BAS3010A 03W 5 e U200 TPS2051BDBV VIN VOUT EN
35. nfineon Revision 1 0 2013 02 20 26 Figure 24 Satellite Connector Type HMI Board User s Manual INH SR eO LES ou ou elg ou 215 ou 2 3 8 ou YH2 9 2QVA HOZD JAVA JAVA ET SId H209 2QVA ST2QV 2QVA 09 2QVA T1n0 va E sejo sq H 1950 13534 SX Sd Sd 98 9d 0149 8 IOld9 IH indul S STd ET Ed 125 85 vas TT Ed TT Ed 25 5 mm 52 145 1SYW 145 Sm THSD 145 135 0 9 Sd USL 145 ala 0 52 145 20135 0221 OT Ed 25 8 S USL ved 3 15 GASY GASY ou GASH ASY
36. nne enne trennen 32 3 3 Billof Material BOM e 33 4 Revision 1 0 2013 02 20 Board User s Manual CPU 45B V1 CPU Board XMC4500 SDRAM List of Figures Infineon List of Figures Figure 1 CPU 45B V1 Board Block 8 Figure 2 CPU Board XMC4500 SDRAM CPU 458 1 9 Figure 3 mem 10 4 Block Diagram Of Power 10 Figure 5 Reset CIICUIE eoe ettet atu 12 Figure 6 Reset LED and Reset 12 Figure 7 Glock Generation ttr ere ten a 13 Figure 9 Boot Options Deu ec data Uu RET ea xeu cha 13 Figure 9 Installation of Serial Port Driven 5 15 Figure 10 On Board USB Debugger ttr ttt at Feri ke eta ee ea 15 Figure 11 Cortex Debug Connector 10 16 Figure 12 Cortex Debug Connector 10 pin 17 Figure 13 Cortex Debug ETM Connector 20 17 Figure 14 Cortex Debug ETM Connector 20 pin 18 Figure 15 Quad SPI Flash
37. or this purpose a 64 Mbit SDRAM is connected to the XMC4500 and for external bus extension an asynchronous 16 bit wide bus interface is available at the COM satellite connector Attention This board CPU 45B has not been designed to work with the General Purpose Motor Drive Card MOT GPDLV For this purpose please use the CPU boards CPU 45A CPU 44A or CPU 42 The focus is safe operation under evaluation conditions The board is neither cost nor size optimized and does not serve as a reference design 1 1 Key Features The CPU 45B V1 board is equipped with the following features XMC4500 ARM Cortex M4 based Microcontroller 1 MByte Flash 160 kByte SRAM LFBGA 144 8 MByte On board SDRAM 1 Mbit x 16 bits x 4 banks Connection to satellite cards via satellite connectors COM HMI and ACT USB Host Device support via micro USB connector Debug options On board Debugger via the Debug USB connector Cortex Debug connector 10 0 05 Cortex Debug ETM connector 20 pin 0 05 Reset push button 32 MBit quad SPI flash memory Boot option switch PowerScale Connector Ready for power consumption analysis Two User Buttons connected to P5 10 and 10 7 LED s 3 Power indicating LED s 2 User LEDs P5 2 and P1 1 1 RESET LED 1 Debug LED Potentiometer connected to analog input P14 1 Power supply Via Debug USB connector Via Micro USB connector in USB device mode Via satellite connector pins COM ACT satellites
38. rial BOM Table 11 BOM of CPU 45B V1 Board Pos Qty Value Device Reference Des No 1 1 3 Resistor R416 2 2 1M 0402 Resistor R200 R505 3 2 1 5 0603 Resistor R405 R406 4 3 2k2 0603 Resistor R306 R307 R420 5 3 4k7 0402 Resistor R302 R304 R506 6 1 4u7F 0805 Capacitor ceramic C212 7 17 2 Resistor R204 R206 R207 R303 R309 R310 R400 R401 R408 R414 R419 R422 R429 R430 R431 R503 R507 8 2 10nF 0402 Capacitor C406 C415 9 8 10uF 10V 0805 Capacitor ceramic C308 C323 C324 C325 C405 C407 C506 C510 10 2 12MHZ S 3 2X2 5 Crystal NX3225GD NDK Q302 Q500 11 6 15pF 0402 Capacitor C312 C315 C316 C317 C500 C501 12 1 22R 0402 Resistor R432 13 1 32 768KHZ Crystal NX3215SA Q301 14 11 33R 0402 Resistor R202 R203 R402 4403 R421 R423 R424 R425 R426 R501 R502 15 4 74LVC1G66DCK IC Single Analog Switch 0301 0303 0304 0306 16 40 100nF 0402 Capacitor C200 C202 C204 C205 C208 C210 C211 C300 C301 C302 C305 C306 C307 C309 C310 C311 C318 C319 C321 C322 C413 C416 C417 C430 C431 C432 C433 C434 C435 C436 0400 C401 C502 C504 C505 C507 C508 C509 C511 C512 17 2 100uF T 10V C Capacitor bipolar C213 C414 18 1 219 02 Dual DIP Switch 0 1 SMD SW300 19 1 270k 0402 Resistor R415 20 2 510R 0603 Resistor R313 R500 21 4 680R 0603 Resistor R301 R305 R407 R504 22 3 BAS3010A 03W Diode SOD323 Infineon V200 V408 V501 23 2 BAT54 02V Diode 5079 Infineon V4
39. sion 1 0 2013 02 20 Infineon List of Tables Table 1 Power status LEDSs Table 2 Power Measurement Table 3 Boot Options Settings Table 4 Cortex Debug Connector 10 Pin Table 5 Cortex Debug ETM Connector 20 Pin Table 6 Quad SPI Table 7 USB micro AB connector Pinout Table 8 User LEDS wcities Table 9 User Table 10 Table 11 of CPU 45B V1 Board User s Manual CPU 458 1 Infi neon CPU Board XMC4500 SDRAM Overview Introduction This document describes the features and hardware details of the CPU board CPU Board XMC4500 SDRAM CPU 45B V1 designed to work with Infineon s XMC4500 Microcontroller This board is part of Infineon s Hexagon Application Kits Please visit www infineon com xmc dev for more information about the Hexagon Application Kit family 1 Overview The CPU board CPU 45B V1 houses the XMC4500 Microcontroller and three satellite connectors HMI COM ACT for application expansion The board along with satellite cards e g OLED V1 COM 1 AUT ISO V1 boards demonstrates the capabilities of XMC4500 The main use case of this board is to demonstrate the external bus unit EBU of the XMC4500 device including the tool chain F
40. t device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered CPU 458 1 Infi neon CPU Board XMC4500 SDRAM Revision History Page or Item Subjects major changes since previous revision Revision 1 0 2013 02 20 Trademarks of Infineon Technologies AG AURIX C166 CanPAK CIPOS CIPURSE EconoPACK CoolMOS CoolSET CORECONTROL CROSSAVE DAVE EasyPIM EconoBRIDGE EconoDUAL EconoPIM EiceDRIVER eupec FCOS HITFET HybridPACK ISOFACE IsoPACK MIPAQ ModSTACK my d NovalithiC 5 ORIGA PRIMARION PrimePACK PrimeSTACK PRO SIL PROFET RASIC ReverSave SatRIC SIEGET SINDRION SIPMOS SmartLEWIS SOLID FLASH TEMPFET thinQ TRENCHSTOP TriCore Other Trademarks Advance Design System ADS of Agilent Technologies AMBA ARM MULTI ICE KEIL PRIMECELL REALVIEW THUMB uVision of ARM Limited UK AUTOSAR is licensed by AUTOSAR development partnership Bluetooth of Bluetooth SIG Inc CAT iq of DECT Forum COLOSSUS FirstGPS of Trimble Navigation Ltd EMV of EMVCo LLC Visa Holdings Inc ERCOS of Epcos AG FLEXGO
41. ta CPU 45B V1 CPU Board XMC4500 SDRAM Ineon f Infi 1 0 2013 02 20 Rev 31 Production Data CPU 45B V1 CPU Board XMC4500 SDRAM Board User s Manual Figure 29 On board Debugger 8 4 9 9 v 5 6 9 8 6 fue jo pue Aue Sip u fue ujasay payers 2918 1 Kue 40 Aue astueenbe se popeo aq UBAB aus a 19660090 69 RIN 2L0Z vO vO LA Z0v0 4U0 552 ou 2070 40001 soso liso X9dZ0ZMZON sse ou 4 gt LO t gt Z QNO et 109X 218 z 5 5 105 S 5 5 vo 8 aNd aNd o o G 6 6 amp 222 BS Je m E 5 5 8 B
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