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1. DFSDM data 3 APB bus Block lagram FUTURE ELECTRONICS Decode Filter Average Process Upto 8 Serial transceivers e Receive and decode raw serial bitstreams providing data clock to filter stage 1 wire Manchester coded mode or SPI clock data Sinc filter performs input stream digital filtering e Sinc Sinc Sinc3 Sinc gt FastSinc No filter Programmable Sinc oversampling ratio 1 to 1024 filter samples Output filter resolution is 31 bit max Integrator stage performs data averaging from digital filter 1 256 samples Post processing Offset compensation Programmable right bit shifting for data formatting Additional functions Min Max extremes detection Analog watchdog to watch for final data boundaries overflow Break signal generation Ly life augmented MEMS microphone support PDM Function MEMS microphone provides pulse density modulated data signal like the gt A modulator PDM microphone has stereo support if two connected in parallel Rising clock Left audio data Falling clock Right audio data Implementation into DFSDM transceivers Channels data left vs right are separated inside Each DFSDM channel transceiver inputs be redirected to next channel inputs e Configuration of those 2 channels differs only in active sampling edge e Clock signal pro
2. 5 51 2599 Bes x3 E m gt 34 2 A EAE The IDD Measure app uses the MFX onboard STM32L 151 as a non intrusive auto ranging current measurement probe The target L4 will enter a low power state the MFX will measure the current wake the L4 up and report the measurement back over 2 The project is the CubeL4 library Discovery Demonstrations folder STM32Cube FW L4 VO0 4 0 Projects STM32L476G Discovery DemonstrationsEWARM OR C Users xxxx S TM32Cube Repository S TM32Cube FW L4 0 4 0 rojects S TM32L476G Discovery Demonstrations EWARM Open the IAR Project eww workspace e Build Program the L4 Discovery Board Exit the debugger RESET and run the Demo Scroll to the Idd Measure app Select different low power modes wait for wakeup and note the current consumption STM32L151 Multi Function Expander MFX FUTURE ELECTRONICS References Refer to www st com stm32l4 discovery Ordering information Getting Started Manual User s Manual and Application notes Board Schematics Application development environments support Demonstration firmware sources Video available on YouTube and st com e Getting started with STM32L476 discovery kit for ultra low power amp performance applications life augmented em 4 Hands On Lab 1 LED Blinky in Five Easy Steps STM32CubeMX File Project Window Help
3. VDDIO2 B Backup domain Ayy VDDIO2 LSE RTC backup registers Peripheral Voltage Monitor By default independent powers are electrically isolated and the features powered by them are not available he power isolation must be removed by SW Peripheral Voltage Monitor for VDDUSB VDDIO2 Power PVM threshold EXTI line supply PVM1 VPVM1 1 2 V life augmented Power supply Supervisor BOR complies with all VDD rise fall time no constraint on power supply shape VDD rising falling edge tRSTTEMPO nReset x x life augmented ELECTRONICS Voltage Regulator All high speed digital IP is sourced by the power rail Dynamic Voltage Scaling optimizes performance vs power Vcore Voltage Range 1 1 2V Up to 80MHz Vcore Voltage Range 2 1 0V Up to 26MHz Vcore powered by main regulator MR low power regulator LPR Main voltage regulator mode MVR for Run and Sleep modes Low power regulator for LP run LP sleep and STOP1 STOP2 modes e Regulators OFF in Standby and Shutdown mode However LPR remains ON to preserve SRAM2 content in Shutdown mode if required life augmented Dynamic voltage scaling in Run mode SYSCLK MHz 127uA MHz 80MHz 6 136 2 26 2 2 oe Em 0WS 5 V Low power run Range 2 1 GORE Vcore 1 1V Vcore
4. VDD domain Battery charging life augmented m PSRAM NOR and NAND Y Innovation life augmented omart peripherals Metering CT LCD Display 88x40 or 4x44 with step up converter gt Anti Tamper pin x tamper pins for battery domain Digital Filter for Sigma Delta Modulators 8 x parallel inputs with up to 24 bit output resolution With RTC for battery backup 240 nA in mode for RTC and 32x 32 bit backup registers STM32L4 TRNG amp AES for Security 128 256 bit AES key encryption hardware accelerator SPI UART SDIO for Wireless 15 4x SPIs with the Quad 6x USARTs ISO 7816 LIN IrDA modem 1 x SDIO 4 A gt FSMC External memory interface for static memories supporting SRAM Electricity Gas Water Smart Meter I Os Up to 114 fast I Os for buttons amp relays FUTURE LECTRONICS Motor Control Smart Peripherals 2x 16 bit advanced motor control timers Industrial Sensors 3x 12 bit ADCs 5 MSPS with up to 16 bit with hardware LCD Display 8x40 or 4x44 with step up converter oversampling 200 uA MSPS 2 High temperature STM32L4 CAN Bus 2 0B Active from 40 C up to 125 C rmm e SPI UART for Security SPls 4x SPls with the 128 256 bit AES Quad SPI key encryption hardware accelerator 6x USARTs ISO 7816 LIN modem FSMC S 2 External memor
5. Analog Watchdog H W trigger High Threshold register 12bits EXTI15 XTSEL 3 0 bits J S W Low Threshold register JEXTI0 trigger 12bits 2 5 5 9 i JEXTI15 ADC interrupt to NVIC JEXTSEL 3 0 bits TIMERs q life augmented ADC Clocks ADC1 ADC2 amp ADC3 HCLK AHB interface Analog ADC1 master Analog ADC2 slave CKMODE 0 1 Analog ADC3 4 single y 4 1 4 y f A life augmented ADC oampling Time sampling Three bits programmable sampling time channel by channel programmable 2 5 cycles 6 5 cycles 2 5 cycles 12 5 cycles xem 24 5 cycles 47 5 cycles d 92 5 cycles 247 5 cycles Wu 640 5 cycles 92 5 cycles 1 247 5 cycles 640 5 cycles Note The sampling time value depends on the type of channel fast or slow the resolution and output impedance of the external signal source to be converted Ly life augmented ELECTRONICS Total Conversion Time mm Total conversion Time TSampling T Conversion 12 5 Gycles 10 5 Cycles 8 5 Cycles 6 5 Cycles Nu NAE MD 6 5 2 5 9 cycles 11 25 us gt 8 89 Oversampler Oversampler performs data pre processing to offload the CPU Handles up to 256 conversions and averages them Averaging Data rate reduction SNR improvement Basic filtering
6. Mass storage device flash programming Virtual COM port for communications 2 push buttons 2 color LEDs Arduino extension connectors Easy access for add ons 2 C29 aca N 4 Vi J D 7 7 0000 4 ani E x3 TX D Morpho extension headers direct access to all MCU I Os TT J www st com stmm32nucleo life augmented Comprehensive choice of IDEs mm JAR Embedded Workbench IDE File Edit View Project Simulator Tools Window Help Da Biss jl Y j P p Loop forever driverlib Debug Ha bitband Debug Ha Debug Turn on the LED Source blinke GPIO PORTE R 0x02 La La Bboot_ee ie 185 nbediPCINB e Bello World the Textl R intf World for include xbed h int printf ocast char include Tex LCD h o o gt gt m icdiplS 16 17 p18 19 p20 rs e 44 97 int ine 6 115 lt Ln gt LES a Compile output for program
7. SAI embeds two independent audio sub blocks which can be ransmitter and or receiver Master or slave Synchronous or asynchronous mode between the audio sub blocks Clock generator for each audio sub block to target independent audio frequencies 8 word integrated FIFOs for each audio sub block up to 16 slots available e Mute mode Stereo Mono and companding mode supporting u Law Flexible serial interface Configurable LSB MSB data slot sizes sampling edges of bits frame shape etc 2 interfaces 2 interrupts and FIFO for each audio sub block life augmented SAI In System STM32L476 486 SAI1 SAI1SEL APB Interface Cik Gen gt Sub Block A e PLLSRC auum CIk Gen T Sub BlockB APB Interface _ A 2 1 A m Eris P MCLK1 FS1_B B es MCLK1 B SAMEXTCLK Management RLLSAI1_P SAI2SEL APB Interface Cik Gen Sub Block A Gen Sub Block B UN iliam APB Interface PLLSAI2 P FS2 A E 2 1 52 B LC SCK2 01552 B Ine IO L anagement SAI2EXTCLK r SYNC IN M Ly 008 life augmented ELECTRONICS Smart peripherals Discovery Board Implementation 110 R70 5569 51 1 0402 51 19 0402 C66 C65 ST
8. aa S ap Load Project Help Step 1 Create New Project Create New Project Select STM32L476VGT6 LQFP100 1024KB Flash Click unes v STN32L4x6 Flash gt 256 KBytes Eeprom 0 Bytes L 256 5 STM32CubeMX Untitled Peripherals Nb Max Lines Package Flash Ram c IO STM32L476VCTx STM32L4x6 LQFP100 ADC 12 bit 0 is STM32L476VETx STM32L4x6 LQFP100 2 ji 0 STM32L476VGTx STM32L4x6 LQFP100 1024 12 2 DAC12 bit o 2 STM32L486VGTx 5 3146 LQFP100 wm wama prsom Bp OPAMP 0 0 e QUADSPII J esa 5902 eoo jsommc 5 life augmented Step 2 Pin Configuration In this example we are going to use the LED s present on the STM32L476 Discovery board Left click PB2 PE8 and set to GPIO Output mode bez pco z z z z z I tec j fo mS Fa ppm ejr fu j p H Pe life augmented otep 3 Generate Source Code File Project Window Help 3 b GenerateCode Ctrl Shift G Pind 5 Generate Report Ctrl R p Settings Alt P
9. e STM32L4 MCU series J Excellence in ultra low power with performance 54 Embedded Systems Conference 20154 x STM32 L4 Yy life augmented e Agenqa Presentation System check for pre installed tools STM32L4 Family Overview e Hands On Session Out of the box demos STM32L4 Low Power details Hands On Lab 1 Getting Started with CubeMX and STM32L4 SIMS32LA4 Peripheral details e Hands On Lab 2 printf debugging via onboard ST LINK Hands On Lab 3 3 axis MEMS Gyro communications e Hands On Lab 4 Autonomous peripherals ADC TIM DMA app Ly life augmented 244 FUTURE ELECTRONICS Systems Check e Please use this checklist to verify whether you have completed the steps to download and install all necessary components for this hands on seminar have a compatible laptop A Windows Laptop Windows 7 or Windows 8 MacBook running Windows Parallels VM Fusion etc Note Administrator rights are needed for software and driver installation have downloaded the Seminar Installer from the emailed Dropbox link and installed it this would have installed latest Java STM32CubeMX STM32CubeL4 HAL and extracted seminar files to CASTM32CubeSeminar have installed the STM32 ST LINK Utility by running its installer this would also have installed the ST LINK V2 Windows device drivers have downloaded and installed
10. 8 Variable T was decered but never referenced nti 0 Line 9 Cob Success 32 407 417 TM32F407 417 M32 407 417 32 4172 32407 417 STM32F4172GTx SIM32CubeMX Partners SIMStudio Generate Code Compile amp Debug Monitor Where Software Meets Hardware Embedded Studio ARM Microcontroller Tools Assistance Conseil Systemes life augmented STM32Cube oupporting all STM32 MCUs Generate your configuration code with the STM32Cube and you can focus on your added value software 4 configuration wizards pinout clock peripherals amp middleware power consumption Portable Hardware Abstraction layer from series to others Middleware with RTOS USB TCP IP File System Graphics Touch sensing e Open source TCP IP stack IwlP e USB Host and Device library from ST SlemWin graphical stack library from ST and SEGGER Open source FAI file system FatFs STM32Cube Open source real time OS FreeRTOS Middleware 9 ME 25105 Dozens of examples Abstraction of STM32 MCU through portable APIs STM32Cube e High coverage for most STM32 peripherals Production ready using CodeSonar static analysis tool e Hundreds of examples Open source BSD license Ly www st com stm32cube life augmented Comprehensive choice of S M32 free I
11. Low power modes summary Peripherals OFF OFF OFF OFF ON Any Any oN except PLL 2 CUu except PLL ON LSE LSI ON LSE LSI SRAM2 LSE LSI DOWN DOWN LSE All All except OTG SDMMC RNG All except OTG SDMMC RNG All Any IT or event All except OTG SDMMC RNG Any IT or event Reset pin all I Os BOR PVD PVM RTC LCD IWDG COMPx DACx OPAMPx USARTx LPUART I2Cx LPTIMx OTG FS SWPMI Reset pin all I Os BOR PVD PVM RTC LCD IWDG COMPx LPUART I2C3 LPTIM1 Reset pin 5 WKUPx pins BOR RTC IWDG Reset pin 5 WKUPx pins RTC 1 Can be put in power down and clock can be gated off 2 SRAM1 and SRAM2 can be gated off independently Consumption 1 8V 127 uA MHz 111 2 136 37 HA MHz 35 2 40 uA MHz 7 RTC 7 6 w RTC 1 2 uA w o 1 4 235 nA 128 nA 433 nA w RTC 43 nA w o RTC 265 nA w RTC N A TBD 6 cycles 6 cycles 4 uA RAM 6 uA Flash 5 uA RAM 7 uA Flash 14 us 256 us FUTURE ELECTRON Low power modes transitions Shutdown backup domain VBAT charging allows to charge a super cap on VBAT through internal resistor wnen VDD is present Battery charging is enabled by setting VBE bit in the PWR_CR4 register e VBRS bit value in the PWR_CR4 register selects the resistor value Backup domain VDD VBAT
12. Q3 nHOLD BK1 nCS Ne life augmented Frame format Each of the 5 phases is fully configurable e Enabled or not Length Number of lanes Exemple of Read configuration Instruction on 1 lane Address Alternate amp Data on 4 lanes 2 dummy cycles Instruction Address Alt pummy Data 23 16 158 A70 M79 Byte2 Ly IO switch from output to input life augmented Smart peripherals Sensor Hub scenario Sensors STM32L4 dx Host Wakeup from STOP lt App Processor SPI UART 3x SPI 6x USART Batch Acquisition Mode BAM Optimized mode for transferring data while the system is in low power mode Only the needed communication peripheral 1 1 SRAM SRAM1 or SRAM2 are configured with clock enable in Sleep mode I Flash is in power down mode Enter either Sleep Low power sleep mode 7 2 clock can be at 16 MHz allowing FM support Smart peripherals USB OTG FS 2 0 058 2 0 OTG 2 0 compliant e VDDUSB Dedicated 3 3V supply input STM32L4 6 bidirectional endpoints MSI in PLL mode auto trimmed with LSE to reach 48MHz amp lt 0 25 accuracy HSE not needed eLink power management LPM support New power save state L1 Sleep with fast entry exit compared to traditional L2 state Suspend 50uS vs 10mS t Battery chargin
13. Ly NW augmented EEEGTRONIGS Ly augmented GEL ND QSUB16 SADD16 GILT SASX SHADD16 SHADD8 SHASX SHSUB16 SHSUB8 SMLABB SMLABT SMLATB SMLATT SMLAD SMLALBB mi m L LDRSB SR LDRH S MUL REVSH LDRSH B GLa GD GL AD REV16 SATB i E Bg SEV m Bs E 2110 Eins STRH CORTEX M0 M1 USUB16 USUB8 GEM UXTAB16 L UXTH CORTEX M3 SMLALBT SMLALTT SMLAWB SMLSD SMMLA SMULBB SMULTB SMULWB SXTAB16 UHSUB16 UMAAL UQSUB8 USADA8 SMLALTB SMLALD SMUAD SMULTT SMULWT SSAT16 SXTAH UHSAX UHSUB8 UQADD16 UQASX UQSUB16 USAT16 Cortex M4 VABS VADD __ ___ vcvr VCVTR VDIV VLDM VLDR C ws Cortex M4F Corte Low Power Leadership from ARM m Ease of use of C programming Interrupt handling Ultra low power life augmented Single precision Ease of use Better code efficiency Faster time to market Eliminate scaling and saturation Easier support for meta language tools Cortex M4 STM32L4 Bus matrix Cortex 4 with FPU ie 1 MB ot SRAM2 32 KB ____ LENT AHB2 Periph Note QuadSPI and SRAM1 4 D bus interfaces when remapped to 0x0000 0000 only life augmented FFFF 0xE
14. NORange 131 131 02 131 09 NULL 48 0uA ims 0 16375 Parameter 5election win i pti 0 Ambient Temperature g ra h Vdd Power Supply V Battery Selection D S D ay of Capacity 19000 0 mAh B Self Discharge 0 08 month 3 Nominal Voltage 3 6 V e Max Cont Current 230 0 mA 3 LOWPOWER RUN 1 consum pt on Max Pulse Current 500 0 5 c 0 00 0 25 0 50 075 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 4 75 5 00 5 25 e A D M PS Information notes Time ms Battery lifetime Results Total Sequence Time 5 0 ms Average Consumption 2 359 Battery Life Estimation 11 months 2 days amp 14 hours Average DMIPS 10 15 DMIPS Ly life augmented STM32Cube Firmware Components Evaluation boards Discovery boards Nucleo boards Board Demonstrations Middleware level Applications Networking LwIP TCP IP amp Polar SSL USB Graphics File system RTOS Host amp Device STemWin FATFS FreeRTOS HAL STM32F401 STM32F405 7 STM32F429 STM32F439 Fx Lx Family gt FUTURE life augmented ELECTRONICS Accelerator Up to 1 Mbyte Flash memory System Up to 128 Kbyte SRAM ARM Cortex M4 CPU 80 MHz 128 byte backup SRAM BOOT ROM FSMC SRAM NOR NAND 1x Quad 5 Connectivity Encryption Display AHB bus matrix Control Analog
15. 1 0V Vcore 1 2V lu life augmented DB 2 R246 ER LE 27 yz STM32L476 D arees sprereerepeespree 111111 HNHH oC aea a iili gt 1 a orea To JE 0 ICI M x e lt BU Q lt 5 QU L gt S life augmented Hands On Lab 2 printf debugging Adding to the existing CubeMX project we will add USART2 debug via the ST LINK Virtual COM port oet up additional GPIO Clocks PD5 USART2 VirtualCOM TX Alt Fn Push Pull PD6 USART2 VirtualCOM RX Alt Fn Push Pull PAO GPIO EXTIO External Interrupt on Rising Edge Input USART2 Clock PCLK1 80MHz USART2 settings Asynchronous Mode 9600 N 8 1 No HW Flow control Tx Rx 16 sample oversampling No advanced features User Code HAL function calls required See lab2 printf debug c in Lab2 Printf directory Also Need Terminal emulator Hyperterm etc Hyperterm exe is included in Tools directory USART2 is routed to the ST LINK s and brought the USB Virtual COM port class SB13 16 have been soldered FUTURE ELECTRONICS GPIO Configuration additions Expand the 5 2 dialog and select Asynchronous mode 4 Use PD5 PD6 for Ix Rx pins These are the alternate mapping pins 2 3
16. 12bit data 20 bit register to 8 bit right shift 16 bit register Accumulation ADCx DR data register Programmable oversampling ratio X2 X4 x16 x32 x64 x128 x256 Programmable data shifting truncating e Right shift to 8 bits Example Oversampling ratio x2 Trigger for EOC Trigger End of conversion for oversampling channel oversampling channel life augmented Sampling Conversior ADC Analog Watchdogs ADC Analog Watchdog 1 12 bit programmable analog watchdog low and high thresholds Enabled on one or all converted channels Interrupt generation on low or high thresholds detection e ADC Analog Watchdog 2 amp 3 Enabled on some selected channels by programming bits in AWDCHx 18 0 Resolution Limited to 8 bits and only the 8 MSBs of the thresholds can be programmed ADC INO IN1 Status Register Low Threshold High Threshold ADC_IN1 life augmented COMPARATORS COMPx_INPSEL GPIO alternate function COMPx POL coMPx OUT COMPx INP COMPx INP Vos J INMSEL interrupt COMPx IMM I Os Y Polarity selection DAC x gt TIMERS DAC CH2 V EFINT 2 ultra low power comparators COMP1 COMP2 3 4 1 2 Wake up from low power modes thru EXTI Sleep STOP1 STOP2 1 4 VREFINT Multiplexed inputs GPIO DAC s VREFINT Programmable hysteresis and speed vs c
17. Ox7FFF FFFF pe 0x8000 0000 Bank 3 Ox8FFF 256 MB NAND Flash 0x9000 0000 Bank4 Ox9FFF FFFF Reserved life augmented Features Summary Asynchronous running capability Timeout function for wakeup from Stop 1 mode LPTIM1 amp LPTIM2 and Stop 2 mode LPTIM1 only FUTURE LP TIM Features e Up to 5 clock sources to achieve lowest power consumption HSI External clock J APB clock LSE LSI Internal External hardware triggers with digital glitch filter e Rising Falling or Both edges GPIO RTC events 1 2 Up to 2 operation modes Continuous mode free running mode many counter overruns are possible One Shot mode Counter stops counting when the overrun value is reached Encoder mode TIM1 only 6 interrupt sources life augmented LPTIM Features 3 4 Up to 3 configurable waveforms with configurable polarity PWM waveform One Pulse waveform Set Once waveform POL20 LPTIMx _ARR D _ 114 FUTURE Hands On Lab 4 ADC TIM DMA functionality Set up additional GPIO Clocks 1 IN12 Analog Input ADC Clock SYSCLK 4 20MHz PD15 TIM4CH4 Alt Fn output ADC1 settings Clock Prescaler Synch 4 12 bit Right aligned No Scan Continuous mode x16 oversampling 4 bit shif
18. Communication l Fs oscillator analog circuits timers Dedicated crystal oscillator is no longer needed for USB function I O level kept in low power modes Optimization of system consumption Internal oscillator from 100 kHz to 48 MHz 0 25 int clock accuracy over voltage temperature with L SE Ly leader and performance booster life augmented o time 4 7 V 4 300 Tamper 3 I Os RTC SHUTDOWN 30 nA 330 Wake up sources reset 5 I Os STANDBY 130 430 nA Wake up sources IWDG STANDBY 4 32 KB RAM 360 nA 660 nA Wake up sources all I Os PVD STOP 2 full retention 1 1 pA 1 4 LCD COMPs STOP 1 full retention 7 3 uA 7 6 Wake up sources all FU UART Wake up sources any interrupt SLEEP 35 MHz O oven RUN at 24 MHz 100 uA MHz RUN at 80 MHz 112 MHz Note without RTC with RTG Ly e ULP leader and performance booster th FUTURE life qugmented ELECTRONICS Efficient run and fast wake up Ready for Launch Control From 0 to 48 MHz in less than 5 us Thanks to our internal oscillator MSI used ER at start up programmable from 100 kHz Run to 48 MHz SOMME 5pns p PLL wake up time lt 15 us i needed to reach fmax STOP mode ge 4 ULP leader and performance booster 2 FUTURE ELECTRONICS Providing mo
19. GPIOB GPIO PIN 2 Delay 100 HAL GPIO TogglePin GPIOE GPIO PIN 8 HAI Delay 100 USER CODE END WHILE Ly life augmented Step 5 Build the Project e Click F7 or the Make button or use menu gt Make Project Tools Window Help amp Add Files E Add Group ion ImportFile List Add Project Connection p H Edit Configurations sy R Remove nfig in Create New Project E 5 Existing Project Options Alt F7 ND 2 Click the Download and Debug Green Version Control System Arrow button CTRL D Make F7 Compile Ctrl F Rebuild Lus Click the Go button F5 Enjoy the flashing LED 5 Ly life augmented STM32Cube M Introduction e STM32Cube M includes Aconfiguration tool STM32CubeMX generating initialization code from user choices e Firmware offering delivered per series like S TM32CubeF4 with STM32 Abstraction Layer embedded software STM32Cube HAL A consistent set of Middleware RTOS USB Graphics STM32CubeMxX Y d 3 oo generation en ei e 7 Within lt lt STM82CubeF1 RTO y Series Middleware stacks when applica life augmented o 2 STM32CubeL1 ff o lt D STM32CubeFO Ory able rr 249 D 55 gagaan HRRRARARBA B
20. High Speed Internal HSI 16MHz factory and user trimmed Selectable as wakeup clock from STOP1 STOP2 Can be automatically woken up when exiting Stop modes Can be used as I2C USART LPUART source upon wakeup life augmented HSI vs MSI design spec EN Normal mode PLL mode Over temperature 6 Over voltage Better than Accuracy max From 100 to 800 kHz 1 25 TBD From 1 to 8 MHz X296 From 16 to 48 MHz 4 100 kHz 0 5 800 kHz 20A 1 MHz 5 Consumption typ 130 8 MHz 20 uA 16 MHz 60 uA 48 MHz 160 uA 100 kHz 10 us 1 25 ms for Startup time typ 48 MHz 2 5 us 5 of final 0 9 us freq life augmented Clocks HSE High Speed External HSE 4 48MHz External source Bypass mode up to 40 MHz External Crystal Ceramic resonator 4 48MHz Clock Security System CSS Automatic detection of HSE failure with NMI generation Break input to TIM1 TIM8 TIM15 TIM16 TIM1 7 Backup clock can be HSI or 5 life augmented life augmented PLL s Each with 3 independent outputs PLL input freq 4 16 MHz PLL input can be MSI HSI or HSE f VCO clock f PLL clock input PLLM x PLLN f PLL P clock PLLP f PLL_Q f VCO clock f PLL_R clock PLLR PLLM from 1 to 8 PLLN from 8 to 86 PLLP 7 or 17 PLLQ 2 4 6 8 PLLR 2 4 6 8 Clocks PLL HS
21. IAR EWARM v7 40 Important please make sure you activate the 30 day time limited evaluation license or you already have a full license The size limited evaluation license will not be suitable for the seminar classes e The workshop exercises require a Discovery kit with STM32L476VG lt 92L4 6GDISCOVERY See the Distributor Availability listed at the bottom of the linked pa FUTURE life augmented ELECTRONICS platform effect S M32 today Select your fit product inside a wide compatible portfolio STM32 STM32 F1 Mainstream Flash size bytes 384K 256 K 16 K 216 28 36 32 48 63 100 132 144 49 64 20 Broadest 32 bit MCU product portfolio DMIPS Ultra low power Mainstream High Performance 754287 DMIPS m N N 428 DMIPS 72 STM32 14 STM32 L1 STM32 10 100 DMIPS EE MHz 75 177 245 398 608 1000 lt n Q 3 Discovery Evaluation Nucleo Kits boards 3rd parties www st com stm32nucleo www st com stm32discovery STM32 Nucleo expansion boards Wa WWW St com x nucleo life augmented SIM32 Nucleo features Flexible board power supply Through USB or external source Integrated ST Link V2 1 07777181 99 0
22. M 3 2 L 4 YaF X7B 10 0603 10 0603 2 CNG PEO SDA PBS gt LL 3 1 E 0 5 0402 5 225 02 pES SAI in 125 pE4 3V BA Philips mode 108 1 0402 C54 C58 l00nF X7R 10 0402 luF 5 10 0503 C61 10082 X7R 10 0402 X5R 10 0603 C68 luF POL 10 C59 C67 luF 5 10 0603 100 X7R 10 0402 C53 150pF NPO 5 0603 100 X7R 10 0402 C55 C48 i 150 NPO 5 0603 100 10 0402 C4 X5R 10 0603 10002 10 0402 C543L22 IC address 0594 life augmented ELECTRONICS 2 o Innovation Smart peripherals Fitness tracker application STM32L4 Sensors All known 12 limitations are corrected Flag management improvements L0 F3 like for easy use Programmable filter on input pins analog amp digital filters Wake up on address matches STOP1 1201 2 3 STOP2 1263 Fast mode Plus to 1Mbits s 20mA Dual clock domain allows high baudrates and low CPU clocks to save power Ly life augmented Smart peripherals USART LPUART Fitness tracker application STM32L4 LPUART Dual clock domain e UART functionality and wake up from Stop mode Stop 1 and Stop 2 Baudrate programming independent of PCLK Four clock sources LSE 32 768KHz HSI PCLK System Clock Supports u
23. Oe O lt qugmenteq FUTURE ELECTRONICS S TM32L476 Discovery back side E kd INIT LS 8S0 e 4 ME 2 127 Tw M 5 4 on gt JD T 87 3 i 92 ve JEN IP cee us 6185 oe 1 0795 00199 it gm Ang k A i 7 d i 1 i Tu I 4 1 i 4 7 ggo rt X x T E E kb umm mmm o f m mmm cm 5816 life augmented IDD current consumption Run 24Mhz voltage range 2 PLL off RTC LSE off Flash ART on Sleep 24Mhz voltage range 2 PLL off RTC LSE off Flash ART on Low power run Low Power Run 2Mhz PLL off RTC LSE off Flash ART on ze Run E life augmented Audio demonstrations RECORD application e Uses MP34DT01 MEMS microphone LED5 toggling during record 16 bit audio samples 48 kHz stored in N25Q128A13 QuadSPI Flas LEFI key to exit PLAYER application Uses CS43L22 audio DAC and 3 5mm jack output e Audio playback either from internal or QuadSPI Flash after a RECORD Sub menus FLASH Audio playback of any WAV binary file loaded 0x08020000 e QSPI Audio playback from QuadSPI Flash following RECORD application Options SEL key to pause resume playback e UP DOWN keys to control volume Audio is
24. Open Project gt Settings Alt P gt Project Settings Set the project Lab1 and the project location Project Settings C STM32L4Seminar Labs Project Location C STM32L4Seminar Labs Toolchain Folder Location C STM32L4Seminar Labs Lab1 Set the IDE Toolchain to EWARM Toolchain IDE Window Help 5 GenerateCode Ctrl Shift G g Generate Report Ctrl R Mcu and Firmware Package Generate sour Mcu Reference Settings STM32L476VGTx Firmware Package Name and Version Generate Code Ctrl Shift G Click Click Open Project Code Generation OM gt lt CT gt o The Code is successfully generated under C STM32L4Seminar Labs Lab1 life augmented Open Folder Open Project Step 4 Toggle The LED stm3zldxx hal msp c stm32l4xx itc The IAR EWARM IDE should now be open C C TNNT C Expand the file tree and open the main c file 52 Add the following code inside the while 1 loop Line 85 in main c a Drivers Add within USER CODE BEGIN WHILE USER CODE END EE uput WHILE section this will preserve your code after regeneration HAL GPIO TogglePin GPIOB G BEN HAL 1 100 HAL CPTO logolePin GPIOE GPIO PIN 8 HAL Delay 100 Infinite loop USER CODE BEGIN WHILE while 1 I HAL GPIO TogglePin
25. VSSA DAG1 DAC2 block diagram TSELx 2 0 SWTRIGx TIM6 TRGO TIM8 TRGO 7 TRGO TIM2 TRGO 4 TRGO TIM5 TRGO EN 27 DAC Control Register MANPx 3 0 WAVEx 1 0 DMAENx DMA Request x 12 bits DORx 12 bits Digital to Analog Converter x DAC_OUTx FUTURE ELECTRONICS Sample 8 Hold feature Maintains DAC output voltage when the MCU is in a low power mode such as STOP1 mode In Sample amp Hold mode the DAC is able to hold its output voltage while all related analog and digital blocks are shut off Up to 15x power savings in some configurations FUTURE How It works oampling phase During this phase the sample amp hold element is charged into the desired voltage Holding phase During which the DAC s output is tri stated High Z to maintain the Sample amp Hold element s stored electrical charge Refresh phase Due to leakage coming from several sources a refresh phase is essential to keep the output voltage at the desired value LSB DAC Sample amp Hold mode life augmented Voice recognition Demonstration STM32L4 with voice recognition algorithm controls an Android remote device thanks to Bluetooth Low Energy communication Microphone Shield ST BlueNRG BLE RF CR2032 With Digitais MEMS Nucleo SIM32L4 Arduino Shield MP34DTO1 Ly F life augmented ELECTRONICS Voice r
26. Voice acquisition with DFSDM 22 22 lt gt lt gt Cortex MA Main regulator MR CPU OFF Flash OFF Zzz gt 40 uA MHz at 2MHz C c 222 Flash 1MB c Range 2 up to 26MHZ H m ds ma ry Digitals MEMS M P34 DTO1 1MHz available Acquisition CPU OFF ART OFF Flash OFF SRAM ON Ly PU TURE life augmented ELECTRONICS JUL Mist gt 2MHz available Trigger detection Voice computation CPU ON Flash ON 114 pA MHz at 16MHz ss JUL gt 16MHz available Range 1 up to 80MHZ 1 83 mA 5 0111011000010 Low Power regulator LPR up to 2MHz Digitals MEMS lt JIU mS gt 2MHz available M P34DT01 1MHz available Computation CPU ON ART ON Flash ON SRAM ON Ly a FUTURE life augmented ELECTRONICS H ADC Block Diagram VREF VDDA E ADEN ADDIS VOPAMPx mes DMA Request VREFINT VBAT yip 18 0 2 gt SAR ADC 5 IN 15 1 VINN 18 0 S Sample VREF and hold 5 Regular data register a 16bits c 42 1 I I 7 I 1 2 7 l 1 AUTDLY I I gt 5 3 Analog watchdog I ADSTP I 4 _________ ros 7 1 p d i pp S W l 1 I v v trigger I EXTI0 sas
27. are default life augmented Clock Configuration We will run the STM32L4 at 80MHz for this lab Click on the Clock Configuration tab Set the PLL Source Mux to MSI set the System Clock Mux to PLLCLK Use PLLM 1 N x40 R 2 AHB Prescaler 1 HCLK should equal 80MHz MSI RC KHz PLL Source USART2 Configuration Click on the Configuration tab and select USART2 gt USART Configuration o Parameter Settings Configure the below parameters Basic Parameters Baud Rate 9600 Bits s Parameter Settings tab Word Length 8 Bits including Parity 9600Bits s EE 8 bit word length Advanced Parameters Data Direction Receive and Transmit No parity bit Over Sampling 16 Samples e 1 Stop bit Single Sample Disable Advanced Features Rx amp Ix data Auto Baudrate Disable 16 clock oversampling TX Pin Active Level Is Inverted Disable RX Pin Active Level Is Inverted Disable No advanced feature settings needed E c EN ERTE DMA settings used TX and RX Pins Are Swapped Disable Overrun Disable Enable Disable on RX Error Enable MSB Is First Disable life augmented NVIC Configuration Click on the Configuration tab and select NVIC Configuration 2 GPIO Priority Group 4 bits for pre emption priority bi
28. supports USART1 2 8 1 2 3 SPI 2 3 USB DFU life augmented 1 ERREUR 5 32KB SRAM2 features Access through D code and l code Code execution max performance without remap HW parity check 4 bit per word Enabled with SRAM2 PE user options bytes e NMI Timer Break on parity check error Optional retention in Standby mode Write protection with 1 Kbyte granularity Read protection with RDP gt Erased when RDP changed from Level 1 to Level 0 Software reset and optional Hardware reset when system reset Erased when setting SRAM2ER in SYSCFG SCSR SRAM control and status register Erased with system reset with SRAM2 RST in user option bytes Ly FUTURE life augmented ELECTRONICS 11 08 2015 Flash organization wo 512KB User Flash banks Each bank is 256 pages of 2KB e Information block System memory boot loader 1 128 double word OTP for user data Option bytes for user configuration Bank 1 0x0800 0000 0x0800 07FF Page 0 Main memory 0x0807 F800 0x0807 FFFF 2K Page 255 Bank 2 0x0808 0000 0x0808 07FF 2K Page 256 0x080F F800 0x080F FFFF 2K Page 511 Bank 1 Ox1FFF 0000 Ox1FFF 6FFF 28K System memory TE 20 Bank 2 Ox1FFF 8000 0x1 FFF EFFF 28K block Bank 1 Ox1FFF 7000 0x1 FFF 73FF 1K OTP area Bank 1 Ox1FFF 7800 0x1 FFF 780 16 Option bytes Ly Bank 2 Ox1FFF F800 Ox1FFF F80F 16 life augmented Fresentation IIe 11 06 2015
29. 010 0000 Cortex M4 internal peripherals 0xE000 0000 0 1 FFFF Ox1lFFF C008 0xB000 0000 0x1FFF C000 Option Bytes System Memory ox1FFF 0000 FMC amp QUADSPI registers 0xA000 0000 0x1000 8000 QUADSPI bank SRAM2 0x1000 0000 0x9000 0000 FMC banks 0x6000 0000 Peripherals Flash 0x4000 0000 Memory type depending on boot CODE configuration 0x0810 0000 0x0800 0000 0x0010 0000 0x2000 0000 0x0000 0000 0x0000 0000 Ly life augmented Memory Mapping FLASH up to 1 Mbytes dual bank FB MODE 0 SYSCFG MEMRMP gt Bank 1 0x0800 0000 gt Bank 2 0x0808 0000 MODE 1 in SYSCFG_MEMRMP gt Bank 2 0x0800 0000 gt Bank 1 0x0808 0000 Up to 128 Kbytes split in 2 parts 96 KBytes 02000 0000 SRAM2 32 KBytes 21000 0000 gt Access through D code and l code Physical remap at 0x0000 0000 selected by MEM MODE in SYSCFG MEMRMP Flash Bank 1 or Bank 2 see FB MODE System flash bootloader FMC bank 1 SRAM1 QUADSPI FUTURE Boot modes Boot mode selection 1 opposite of nBOOT1 Boot mode option bit User Flash Main Flash memory is selected as boot space 1 1 System System memory is memory selected as boot space 0 1 Embedded SRAMI is selected as boot space Flash Bank1 boot Option Bit BFB2 0 Flash Bank2 boot Option BFB2 1 Bootloader
30. 28 KB of SRAM with safety and security features smart and numerous peripherals advanced and low power analog circuits in packages as small as 3 8 x 4 4 mm Great Investment This new STM32 member benefits from the pin to pin compatibility of the STM32 family and the STM32 Ecosystem amp Key messages of S M32 L4 series 9 Ly life augmented ELECTRONICS ULPBench STM32L4 gets 150 2 EEMBC ULPMark CP proving excellence in ULP ULMark CP Ultra low power The higher the better Performance 180 BOB 160 140 250 120 200 100 80 150 60 100 40 50 20 0 MCU R MCU M MCU A MCU T STM32L4 MCU T MCU A ULPBENCH COREMARK An EEMBC Benchmark v An EEMBC 3 ULP leader and performance booster BZ life qugmented ELECTRONICS Ultra Low Power and Flexibility FlexPowerControl STM32L4 is based on a new platform optimized to reduce power consumption and increase llexibility Down to 30 for wake up with additional Shutdown mode RTC available for all power modes External level shifter no longer needed j from Active down to Separate supplies down to 1 08 V nA Vea mode with charging capability Automatic switch to maintain power for RTC and backup registers Down to 360 nA keeping 32 Kbytes of SRAM active in Standby mode Wake up MCU with any peripheral USB capable with 32 kHz crystal
31. 476VG STM32L476QG STM32L476ZG 1M 512 K ose MEE Gate STM32L476VC Pin count LQFP64 WLCSP72 LQFP100 UFBGA132 LQFP144 10x10x1 4 mm 4 4 3 8 0 585 mm 14x14x1 4 mm 7 7 0 6 20x20x1 4 Legend With 128 256 bit AES Hardware Encryption Im Without 128 256 bit AES Hardware Encryption Available in 03 2015 y 4 4 1 A life augmented Great investment a S TM32L4 ecosystem HARDWARE TOOLS SOFTWARE TOOLS Available in Q3 2015 Available in Q3 2015 STM32 Nucleo Discovery kit Evaluation board STM32CubeMX featuring code generation and power consumption calculation Flexible Key feature prototyping prototyping Ly life augmented FUTURE ELECTRONICS Great investment au LCD 96 segments gt I Ca nm 44894444994 3 push buttons and joystick 2 color LEDs w _ 29 Nj e 93 1 T 7 164 0050 OM i Gate USB OTG connector Sm A S gt a 5 O TTF m coo ORION ESS BS TON rast is pete Bo 855888 O O O O Microphone Mems 20 O O
32. 56 Kbytes to 1 Mbyte of 16 to 192 Kbytes of Flash 32 to 512 Kbytes of Flash Flash Up to 20 Kbytes of SRAM Up to 80 Kbytes of SRAM Up to 128 Kbytes of SRAM Ly life augmented Great investment S T M32L a complete offer STM32L4 completes the ultra low power family 100 DMIPS 273 CoreMark More erformance P T More memory and counts More packages Flash size bytes WLCSP STM32 14 ld 33 DMIPS 26 DMIPS 93 CoreMark 75 CoreMark Pins MHz 20 28 36 32 48 63 100 132 144 49 64 Great investment rac ELECTRONICS life augmented STM32L4 series ART Accelerator 8 ch USART SPI AA 2 4x 16 bit Segment Quad SPI line Op oe OTG FS 128 256 bit 16 and 32 bit timers elta 5 Msps river SAI audio PLL Interface SWP 1x STM32L471 SDIO Access FSMC 1024 STM32L476 2x 12 bit DAC Net STM32L475 256 SDIO to 128 FSMC 3 1024 Cortex M4 DSP FPU 80 MHz T ture senso emperatu USB OTC EUN SDIO to 128 FSMC Unique ID STM32L486 ss SC USB OTG amp 1024 128 sensing LCD amp AES FSMC Legend Available in Q4 2015 RO 55 4 Ly x Great investment life augmented STM32L4 portfolio Flash size bytes STM32L486RG B SIMS2E466UG 8 STM32L486VG STM32L486QG STM32L486ZG STM32L476RG 8 STM32L476JG STM32L
33. 9 product series 32 product lines STM32L4 benefits from pin to pin compatibility across the family I 1 I j i j I 1 I 1 I 1000 CoreMark j 398 CoreMark 608 CoreMark 120 MHz 180MHz 200 MHz 225 DMIPS 428 DMIPS High performance 150DMIPS I I 177 CoreMark 72 MHz 106 CoreMark 90 DMIPS Mainstream 48 2 j 72 38 DMIPS 1 61 DMIPS 1 from CCM SRAM Mg MF Kalka 8 Ultra low power 75 CoreMark 93 CoreMark 273 32 MHz 32 MHz 80 MHz 26 DMIPS 33 DMIPS 100 DMIPS 0 Cortex M0 1 A Cortex M3 Cortex M4 i Cortex M7 Cortex M0 Great investment hy C number of lines life augmented 2 ULP offer STM32L4 completes the ultra low power family Cost smart Broad Range ULP with ULP Champion Foundation performance STM32 4 Cortex M0 32 MHz Cortex M3 32 MHz Cortex M4 w FPU 80 MHz Operating range Operating range Operating range 1 65 to 3 6V 1 65 to 3 6V 1 71 to 3 6V 8 16 bit applications Wide choice of Advanced Peripheral Numerous pin counts memory sizes Performance 3 product lines 3 product lines 3 product lines USB LCD AES ADC 5 Msps PGA Compar Cost effective Rich Analog DAC op amp USB Smaller packages True EEPROM 5 USB LCD Analog Dual bank Flash RWW 2
34. DEs 966 System u gv D MDK ARM Microsoft Microsoft Microsoft Microsoft Q2 2015 7 7 0272015 licenses for access to STM32F0 all STM32Nucleo amp STM32L0 licenses for all STM32 microcontrollers New ST MCU Finder Application Quickly find the right ST MCU Easy access to technical materials Latest news from ST MCU world ROID J gt Google play WWW St com stmcufinder 4 LL life augmented ELECTRONICS Birth of the STM32 L4 High performance ARM Cortex M4 FPU DSP Advanced analog New digital peripheral set Ultra low power STM32L4 is a perfect fit in terms of ultra low power performances memory size and peripherals at a cost effective price Convergence between High performance and Ultra low power series life augmented ULP leader and performance booster ST has built a new architecture delivering best in class ultra low power ULP figures thanks to its high flexibility In addition the performance of the STM32L4 far exceeds the competition in the ultra low power world It delivers 100 DMIPS based on its ARM Cortex M4 core with FPU and ST ART Accelerator at 80 MHz Innovation Covering a large range of applications the 5 3214 features many architectural innovations and new smart embedded peripherals Integration and safety 1 MB of Flash and 1
35. I CK PLL SAI CK PLL SAI2 SAI CK IP1 PLL CK PLL SAI3 PAD CK PLL SAI CK PLL SAI2 SAI CK IP2 VCO 344MHz CK PLL SAIS N 43 PAD CK PLL USB1 CK PLL USB2 CK 48M PLL SAI MSI USB SDIO HSI MSI HSE VCO 160MHz 192MHz mes 256MHz 288MHz CK PLL ADC1 CK PLL ADC2 L ADC SYS CK PLL System PLLP from 2 to 31 in derivatives 8MHz MSI M HSE 12 34 5 6 7 8 VCO 192MHz 24 PLL SAI1 11 2896 2 CK PLL USB1 48MHZ CK ADC1 CK PLL SAI2 49 152MHZ UNUSED CK PLL ADC2 86MHZ 11 2896MHZ CK PLL USB2 48MHZ CK PLL 80MHz 48MHz 64MHz 72 2 ADC FUTURE Clocks LSE Low Speed External LSE programmable amplifier driving capability 4 modes Mode Crystal max Consumption typ Ultra low power 50kOhm 6pF 200 nA Medium low driving 80kOhm 6pF 260 nA Medium high driving 50kOhm 12 5pF 410 High driving 80kOhm 12 5pF 540 Avallable in all low power modes PA 7 FUTUR ELECTRONICS Clocks LSI Low Speed Internal e LSI 32kHz STM32L15x STM32L4x Accuracy over parts 26 56KHz 8 Accuracy over temperature 10 4 0 85 e 40 125 C Consumption typ 400nA 110nA Available in all low power modes except Shutdown and VBAT Power schemes 1 3 2 OPAMP USB transceivers VDDUSB 2 DAC VREF VREEF buffer d VLCD LCD d LCD booster
36. Mode Standby 405 nA 3 0V wi SRAM2 363 1 8V w o RTC D ji Wake up event RTC Tamper RTC 14 us wake up Available Clock Available Peripheral M32L4 Power Mode mm Standby Mode Standby w 674 nA 3 0 on LSE quartz 433 NA 1 8V m 1 Ea i D Wake up event Available Clock CT NE 14 us wake up Available Peripheral voseanbeconteured M32L4 Power Mode w or w o pull down Standby Mode 169 nA 3 0V Standby gt 128 nA 1 8V Wake up event gt mr Ea i Available Clock RTC Tamper RTC 14 us wake up Available Peripheral I Os be configured STM32 4 Power Mode w or w o pull up w or w o pull down But floating when exit from Shutdown S n u Id own M od Shutdown w gt 476 3 0V on LSE quartz 265 1 8 D m 1 Ea i Wake up event NRST Available Clock 5WKUP pins 250 us wake up Available Peripheral I Os can be configured STM32L4 Power Mode w or w o pull up aod ambi from Shutdown S n u Id od 43 1 8V Wake up Available ok 5WKUP pins uU EM LSI LSE Cy life augmented JJ N LPR H1 H2 LPR LPR LPR LPR OFF OFF Yes Yes No No No No DOWN DOWN
37. Program Erase 5 Error Code Correction 8 bit 64 bit word e Single error correction Double error detection NMI Programming granularity is 64 bit Page granularity for erase 15 2 Kbytes Parameter 64 bit programming time 82 us Page 2 KB erase time 22 ms One row 32 double word programming time Normal 2 6 ms Fast 1 9 ms One page 2 KB programming time Normal 20 9 ms Fast 15 3 ms One bank 512 KB programming time Normal 5 35 s Fast 3 9 Mass erase time 1 or 2 banks 22 ms Ly FUTURE life augmented Performances STM32L15x STM32L4x CPU CortexM3 CortexM4 FPU Flash I F Prefetch ART Frequency 3aMHz 80MHz Performance 35 DMIPS 100 DMIPS no loss DMIPS 1 0 4 8 121620242832364044485256606468727680 PA 7 FUTUR ELECTRONICS 6 ARI overview Instruction cache 32 lines of 4x64 bits 1KB Data cache 8 lines of 4x64 bits 256 B Best tradeoff between cache size Power and Dhrystone CM performances 32 4 Current buffer 64 AHB 32 Prefetch buffer 64 life augmented Flash protections Flexible Protections configurable with option bytes Readout protection RDP Forbids access to Flash SRAM2 Backup registers by Debug interface JTAG SWD Boot from Bootloade
38. asic Parameters RTC_AF1 Ward Length 8 Bits including Parity 1 USB OTG FS DP OSC IN Use FS Parity None RCC_OSC_OUT USART1_RX USARTI TX ST M 3 2 G D M x Stop Bits 1 SDIO_D1 u e E Advanced Parameters 1252 ext so SDIO DO 125250 Data Direction Receive and Transmit 1262 EB FTC_REFIN Over S ampling 15 Sa mples USART2 TX 9 1262 WS Baud Rate BaudRate must be between 110 Bits s and 10 5 MBits s 4l G E r n gt gt 33 Gu 2 Peripherals amp Middleware Wizard Pinout Wizard Power Consumption Wizard Clock Tree wizard HSI RC mm m Mux lt gt AHz ais SYSCLK MHz 5 16 PLL Source Mux n gt L x CSS Input frequency 192 2 gt r jl HSE wm T 0 00 0 25 0 50 0 25 125 150 17 200 HSE E E Time ms 26MHz 4 Main PLL Sequence Average Current Ly life augmented ELECTRONICS FUTURE Power consumption calculator 29 Micro plorer Unt ed STM32L100R E x Power step m d ef n t n S I Calculator Microcontroller Selection Family STM32L1 Batt lect a e ry S e SubFamily STM32L100 M dorm dE Range Memory Clock C SrcFreq CPU Bus Peripher Add Cu Step Cu Duration UEM LOWPOW
39. eam final 24 bit result e Security emergency functions FUT ELECTRONICS not in Orca External gt A modulator s Analog signal Ly life augmented DFSDM EXTRG 1 0 APB bus Memory buffer data DMA CPU transfer parallel input data register 7 parallel input data register 0 DFSDM CKOUT 7 Channels multiplexer NF serial Integrator unit 3 DFSDM CKIN7 3 transceiver 7 Oversampling D LI ae il Oversampling ratio DFSDM DATINT tanidi Filter order PG Sincx filter 0 Integrator unit O transceiver O Oversampling Filter order OVersampling Clock control Mode control ratio 8 watchdog filters 8 watchdog comparators short circuit detector 0 Interrupt break 1 s O s counter threshold detector 7 1 s 05 counter threshold DFSDM_CKINO E DFSDM DATINO 6 Right bit shift count Calibration data correction unit config High threshold Low threshold Interrupt break conii DFSDM data 0 3 Analog watchdog 0 reshold Low threshold filter 3 fi TUM Analog watchdog 3 K _____ Data output Extremes Control unit Extremes Interrupts and events detector O Configuration registers 1 end of conversion DMA interrupt break 2 analog watchdog et control clock control 3 short circuit detection Minimum value 4
40. ecognition function blocks Always on LOW Voice acquisition yield trigger PDM to PCM amp signal sound E conditioning detector Always on BLE connection life augmented Low power audio DSP replacement Voice recognition example BENI Always on OW Voice acquisition p trigger PDM to PCM amp signal sound detection conditioning detector Sub microwatt acquisition thanks to PDM to PCM HW processing with DFSDM and low power Batch Acquisition Mode BAM life augmented Hardware Software blocks STM32 L4 x PDM Signal PCM wal TUS Conditioning Output Decimation 16 2 Digitals 5 Decimation by 64 Gain control HP filtering MP34DT01 2MHz Low Power Sound Detector Voice Trigger Indicator Output LPSD Detection 16MHz life augmented BAM explained Voice recognition use case PS M K M M M d H 7 no STM32L476 10100110105 ___ __ _ Filtering Decimation Gain control done by HW with DFSDM Cortex M4 Flash fetch Algorithm Cortex M4 Cortex M4 Processing RAM fetch RAM fetch Voice trigger Current LPSD LPSD detection consumption Quiet Detected 4 m Ly life augmented
41. ed for energy measurement This device can be used in medium and high resolution measurement applications where single or double inputs must be monitored at the same time The STPMS2 are mixed signal ICs consisting of an analog and digital The analog section consists of a programmable gain low noise choppered amplifier two second order AX modulator blocks a band gap voltage a low drop voltage regulator and DC buffers while the digital section consis of a clock generator Smart peripherals DFSDM Metering STM32L4 Electricity Meter Digital Filter for Sigma SMart peripherals DFSDM Delta Modulators Metering ui SIPMS2H L DAT ce NS STM32L4 R2 150k 160k ca ku Ampl x4 MSi TC C L1 1 PASS eum me chan ON DAT DIE bec PASS Moda OFF Electricity Meter Smart peripherals Serial Audio Interface Fitness tracker application Serial Audio Interface supports a wide set of audio protocols thanks to its flexible architecture 125 Philips standards Inter IC Sound STM32 L4 125 LSB or MSB justified 125 variant SPDIF Output Sony Philips Digital InterFace PCM Pulse Code Modulation TDM Time Division Multiplexing AC 97 Audio Codec 97 from Intel SAI 2x serial audio interfaces life augmented SAI Features
42. g detection BCD support USB Detect and identify the port type standard or charging USB OTG 2 0 full speed Detection Protocol ADP support LPM and BCD Allows an OTG device embedded host or USB device to determine attachment status in the absence of bus power Suspend resume support Wakeup from STOP Ly 2 life augmented o nn ovat ION Analog Peripherals 5 Rail to rail inputs 1mV offset after calibration Outputs sink source 100UA low power mode 1MHz GBW normal mode 500kHz low power mode 0 7V us slew rate normal 0 3V us low power Mode Comparators ADC s 57 life augmented 2 Comparators Window mode Available in low power modes S 8 12 bit mode Lots of conversion triggers Programmable output buffer to drive more current Supply VDDA 1 8 V to 3 6 V NEW Sample and hold low power mode ADC1 ADC2 are tightly coupled ADC3 is standalone Consumption linear vs conversion rate 200 uA MSPS Dual clock architecture Up to 5 3Ms s with 12 bit resolution in single mode oingle ended or differential inputs Internal channels Temp sensor VREF VBAT 3 DAC NEW Hardware Oversampling omart peripherals STM32L4 2x with built in PGA COMP 2x Low power DAC 2x Low power sample and hold ADC 3x 12 bit ADC 5 MSPS e innovation Ly life augmented Ext IT 9 VREF VDDA
43. he PCROP regions are execute only 1 per bank 64 bit granularity e PCROP area can be increased but never decreased Only way to deactivate PCROP is to change RDP from Level 1 to Level 0 Option bit RDP When DISABLED PCROP content is erased when RDP is changed from Level 1 to Level 0 PCROP RDP is locked in this state When ENABLED PCROP content is preserved when RDP is changed from Level 1 to Level 0 Flash Write Protection Write protected area is protected against erasing and programming 2 areas per bank 2 KByte granularity Ly life augmented STM32 Firewall FW FIREWALL is made to protect parts of code data volatile and non volatile from access from the rest of the code executed outside of the protected area Code Segment NVM Code StartAddress CSSA 31 22 21 8 7 1 Length Protection Code fetch Eu Non Volatile Data Segment NVM Data 31 24 23 Start Address FW NVDSSA 31 22 21 8 7 1 NvDSL EL code Protection Data NVM data AHB APB AHB APB Volatile Data Volatile Data Segment SRAMI Data 31 17 16 Reset event _ Start Address FW_VDSSA 31 22 21 8 7 1 ___ Lenth 3 Segments may be protected NENNEN Length LLL Fw by the Firewall Protection Code fetch if SRAM1 is executable not shared Data ws res FW _ FPA Pre alarm bit t
44. n power down Available Peripheral QUADSPI Cortex M4 Range 2 up to 26MHZ Seiad Cell in Available power down Periph and clock LPTIM 1 mE 2 Available woe wo Svstick Timer ____8 ___ ____ 5__ _ E LSI LSE Available Peripheral USB OTG 24 Flash 1 Available Clock Available I Os kept and configurable USB OTG EE 222 Wake up c event c Lr SRAM 1 96KB Flash 1MB SRAM 2 32KB Available Clock WWDG Systick Timer Temp Sensor Timers ____8 ___ Available I Os kept and configurable NJ _ QSPI_ 222 Wake up c event SRAM 1 Flash 1MB SRAM 2 Available Clock WWDG Systick Timer ____8 ___ Available USB OTG USART 2 1 12C 2 __ SDMMC Temp Sensor Timers LPTIM 2 WWDG Systick Timer ____8 ___ I Os kept and configurable Available Clock Wake up event Available USB OTG USART 2 1 12C 2 __ SDMMC SWPMI ____ __ _ ____ __ _ Temp Sensor Timers LPTIM 2 WWDG Systick Timer ____8 ___ I Os kept and configurable Cortex M4 N Flash 1MB Available Clock SRAM 1 96KB SRAM 2 32KB Wake up event RTC Tamper Available Peripheral wwe OSITM32LA4 Power Mode mm w or w o pull down Standby
45. o control the exit point of the protected code life 244 VDS SRAM1 protected segment is sharable with non protected code VDE SRAM1 is executable into the protected volatile data segment Clock Tree to RTC and LED ta FWR ta AHB bus core memory and Corigx free running cock to Cortex system timer PCLK4 PRESC 1 24 8 16 ip peripherals to 2 7 LSE L C ee SYSCLK L SARTX TER X22 5 to LPUART1 mw MSI RC SYSCLK io 2 100 kHz 48 MHz LsSE to LPTIMx HSI x 1 2 to SWPMI PCLK2 u to APBZ peripherals HART 2 T in amp AIZ FUTURE ELECTRONICS to x 18 15 16 17 LSE HSI to SYSCLK USARTI 48 MHz clock to USB RNG SDMMC to AD ip life augmented Clocks MSI Multi Speed Internal 63 MSI clock at startup from Reset Standby or Shutdown modes 12 Programmable frequency ranges 100 kHz 200 kHz 400 kHz 800 kHz 1 MHz 2 MHz 4 MHz reset value 8 MHz 16 MHz 24 MHz 32 MHz 48 MHz After Standby Frequency selected from 1 2 4 or 8 MHz with MSISRANGE in register Normal mode and PLL mode auto calibration with LSE PLL mode allows USB FS device functionality 0 2596 accuracy Factory and user trimmed Clocks HSI
46. onsumption e Redirection of output to IO or timer inputs e g TIM Break event Outputs with blanking source Comparators can be combined in the window comparator life augmented COMP low power features Power consumption vs propagation delay can be aqjusted PWRMODE Max propagation delay Consumption Typ 00 80 ns 70 01 or 10 1 us 5 11 12 us 350 Feature limitation Run LPRun no limitation state polling or interrupt thru EXTI Sleep LPSleep wakeup capability thru EXTI otop 1 Stop 2 wakeup capability thru EXT otandby not available ohutdown not available life augmented Smart peripherals NOR Signals TFT Display IRQ STM32L4 Parallel interface to TFT Shared Up 040 Mz Signals BS NOR Flash PSRAM and NAND controllers Differences from FSMC Continuous clock generation for synchronous and asynchronous modes Performance enhancement Removal of PCCard controller on new products Ly iicquamentea o Innovation Bank memory mapping For the the external memory is divided into 4 fixed size banks of 4x64 MB each Bank 1 be used to address NOR Flash OneNAND or PSRAM memory devices Banks is used to address NAND Flash devices Bank 2 amp 3 reserved Supported Memory Type 0x6000 0000 1 NOR PSRAM SRAM CRAM OneNAND Ox6FFF FFFF 4x64 MB 0x7000 0000 Bank 2
47. p to 9600 baud via 32 768KHz LSE e wakeup from STOP mode clock source must be LSE or HSI 3 Wakeup events Address match START bit detection or RXNE receive buffer not empty or Ly F life augmented o n n ovat n STM32L4 USART Implementation e s 2 5 and LPUART USART features USART1 2 3 UART4 5 LPUART Hardware Flow Control Continous communication using DMA Multiprocessor communication Synchronous mode Smartcard mode Single wire half duplex mode IrDA LIN Dual clock wake up from STOP1 Dual clock wake up from STOP2 Receiver timeout Modbus Communication Autobaudrate detection RS 485 Driver enable Ly life augmented YES YES YES YES YES YES YES YES NO YES YES YES YES YES YES NO NO YES YES YES YES NO YES YES YES YES YES YES NO NO YES NO NO YES YES NO NO NO YES FUTURE Smart peripherals STM32L4 Programmable from 4 to 16bit bit granularity 32 bit FIFO to optimize bus bandwidth performance amp power consumption BUSY status bit IP fix Up to 40 Mbits s in master mode 25 functionality no longer supported in SPI Now in SAI peripheral Ly life augmented Hands On Lab 3 communications to 3 axis Gyro Adding to the existing CubeMX project we will add communications to the L3GD20 MEMS gyroscope Set up additional GPIO Clock
48. played back in loops until LEFT key is pressed life augmented Compass and sound meter demonstrations COMPASS application e Uses LSM303C eCompass MEMS device 2 tJ i 3D accelerometer and 3D magnetometer A S u b M enu ANN e CALIB rotate board 360 on all axis s after scrolling message invitation d 22 e RUN displays angle degrees di A ISS LEFT key to exit Z SOUND meter application e Uses MP34DT01 audio sensor to measure ambient r e Displays measurement value in dB on LCD screen LEFI key to exit Ly life augmented Guitar tuner demonstration Select guitar string SIR1 E low E thickest string closest to the ceiling e SIR2 SSTR3 D G STRI B STRO high E thinnest string closest to the floor RIGHT SEL to start recording Ouputs when string needs to be strained when string needs to be slightly strained close to correct tune e OK when string correctly tuned when string needs to be slightly loosen close to correct tune when string needs to be loosen LEFT key to exit Ly life augmented LLLP I4 LE P 7 9 S 150800 e 1 s 5 5 26 L L 1 FI L476 Discovery Demonstration Source Code
49. r Proprietary Code Protection PCROP with 64 bit granularity Used to protect specific code area from any read or write access The code can only be executed Write Protection WRP with 2 KByte granularity Used to protect specific code area from unwanted write erase Ly life augmented Readout Protections Readout protection Level 0 No read protection operations are possible in all boot configurations Readout protection Level 1 User mode Code executing in user mode can access main Flash memory option bytes RTC backup registers and SRAM2 with all operations Debug boot RAM and boot loader modes main Flash memory backup registers and SRAM2 are totally inaccessible in these modes a simple read access generates a bus error and a Hard Fault interrupt Un protection Level 1 to Level 0 Flash memory is mass erased backup registers and 2 are cleared f Option bit PCROP RDP is set the PCROP protected area is not erased Readout protection Level 2 No debug All protections provided by Level 1 are active RAM boot System memory boot and all debug features are disabled Option bytes can no longer be changed in user mode Un protection is not possible It is an irreversible operation life augmented Proprietary Code PCROP Write Protections When enabled PCROP area is protected against all D code bus accesses T
50. re performance Do not compromise on performance with STM32L4 CoreMark Execution performance score from Flash 2 Up to 80 MHz 100 DMIPS with Linear performance thanks ART Accelerator Up to 273 CoreMark Result ARM Cortex M4 with DSP instructions and to ST Accelerator M floating point unit FPU Optimized DMA 14 channels SPI upto 40 Mbit s USART 10 Mbit s Competitors impact of wait states CPU frequency 80 MHz y ULP leader and performance booster C d FUTURE life augmented ELECTRONICS augmented Parallel Interface Display Timers I Os Cortex M4 80 MHz FPU MPU ETM Connectivity Digital Analog Package size down to 4 4 x 3 8 mm e Integration and safety ELE Safety and security Integrated safety and security features SECURITY Brown out Reset all modes Anti tamper detection Memory Protection Unit e Clock Security System MPU SRAM parity check Read and Write Backup byte registers Protection Supply monitoring Unique ID Flash with with AES 256 Encryption status register JTAG fuse address rue Random Number Dual watchdog Generator Software IP Protection yg Integration and safety life augmented ELECTRONICS STM32L4 continuity in STM32 portfolio
51. s PD1 5 12 5 Alt Push Pull PD3 SPI2 MISO Alt Fn Push Pull PD4 SPI2 MOSI Alt Fn Push Pull PD7 nCS Output Push Pull 2 settings Full Duplex Master Motorola 8 bit MSB first Prescaler 16 CPOL Low CPHA 1 Edge No CRC Software NSS User Code HAL function calls required to be added to main c CASTMS32LA4SeminanLabsMab3 spi gyro c Gyro under LCD data is routed to SPI2 2 FUTURE life augmented ELECTRONICS Smart peripherals QuadSPI 3V 256 Multiple VO Ser STM32L4 Micron Serial NOR Flash Memory 3V Multiple 0 4KB Sector Erase N25Q256A QuadSPI Communication interface for single dual quad SPI flash memories life augmented o Innovation QuadSPI Overview Three operating modes ndirect all the operations are performed through registers classical Status polling periodical read of the flash status registers interrrupt generation Memory mapped External flash seen as internal for read operations 256MB limit SDR and DDR support e Integrated FIFO for reception and transmission 8 16 and 32 bit data accesses channel for indirect mode operations Interrupt generation on FIFO threshold timeout operation complete and access error Registers Clock Control Management QSPI Flash 1 100 5 00 81 BK1 101 5 Q1 SO ift Register 3 BK1 02 Q2InWP Bl
52. t continued mode Trigger on TIMACCA Rising edge Enable DMA 1 conversion Channel 12 Rank1 6 5 cycle sampling no offset DMA settings DMA1CH1 Circular mode Increment memory address Word data width DMA1CH1 interrupt enabled preempt priority TIM4 settings M EI EI uit 24643 x vr EIU 4C46 7 EX 1 54 Im 855 t i X Counting UP Prescaler 79 Counter Period 1000 PWM Mode 1 Pulse 200 Fast Mode enabled Polarity High y lt User Code HAL function calls required C STM32L4SeminarvLabsiab4 adc tim dma c Internal L4 ADC TIM DMA peripherals NW Extra Credit Lab 5 1220 communications to Adding to the existing CubeMX project we will add 2 communications to the onboard STM32L151 device Set up additional GPIO Clocks PB10 12202 SCL Alt Fn Open Drain Pullup enabled PB11 1262 SDA Alt Open Drain Pullup enabled 2 2 Clock PCLK1 80MHz 2 2 settings 100KHz Standard Mode Analog Filter enabled bit address Rise Time 0 5 Fall Time 0nS 2 2 Event Interrupt enabled Preempt priority 2 Sub 0 2 2 Error Interrupt enabled Preempt priority 2 Sub 0 r A 1 4 a Ll L TI 1 GNE lt Q uv Z Systick Interrupt Preempt Priority 1 Sub 0 User Code HAL func
53. tion calls required C STM32L4Seminar Labs lab5 i2c_mfx c STM32L151 Multi Function Expander 126 slave 2 FUTURE life augmented ELECTRONICS SUMMARY 4 Keys of S M32 14 series e ULP leader and performance booster eo Innovation Integration safety Great Investment Thank you 3 QST World ee st com e2e www st com stm32l4 FUTURE ELECTRONICS
54. ts for subprio Sort by Premption Priority and Sub Searc Show only enabled interrupts Enabled Preemption Priority Sub Priority aaa e Enable EXTI lineO E pe e a Set Preemption Priority to 2 Click OK Enabled Preemption Priority Sub Priority Ly life augmented Hegenerate Source Code for Lab1 mm Generate Code Ctrl Shift G Generate Code Ctrl Shift G g Generate Report Ctrl R Alt P Open Project oc T The Code is successfully generated under C STM32L4Seminar Labs Lab1 Open Folder Open Project Copy Paste needed code bits for Hands On Lab 2 into main c e C STM32L4Seminar Labs lab2_printf_debug c Open a terminal emulator using USART2 settings Virtual COM port xx Rebuild Program Debug Run Ly life augmented Available Peripheral STM32L4 Power Mode Run mode Run Mode Range 1 Ex execution from Flash Range 2 up to 26 2 Available Clock Cell power down Range 1 127uA MHz at 80 MHz 10 2mA Range 2 111uA MHz at 26 MHz 2 9 mA Available Peripheral STM32L4 Power Mode Low power run mode Low power run mode Ex execution from Flash Main regulator MR from Flash 136 2 at 2 MHz Range 1 up to 80MHZ 272 uA Range 2 up to 26MHZ From SRAM1 121 2 at 2 MHz Available Clock Cell i
55. vided by DFSDM CKOUT PDM microphones are slaves FUT ELECTRONICS life augmented MEMS microphone application schematic DFSDM peripheral Channel 7 Filter 3 Filter 2 Stereo microphone Filter 1 DFSDM DATINS3 Channel 3 Filter O L DFSDM DATIN2 Channel 2 DFSDM DATIN1 difectinput Channel 1 alling edge sampling R data DFSDM DATINO redirected from next channel Channel 0 rising edge sampling L data MEMS microphone Left MEMS microphone Right internal clock DFSDM_CKOUT clock life augmented Digital Filter for Sigma Delta Modulators Ly life augmented 57 second order sigma delta modulator with STPMS2 Smart sensor dual channel 1 bit 4 MHz Features B Vor supply range 3 2 V 5 5 V Two second order sigma delta EA Programmable chopper stabilized low noise Supports 50 60 Hz 50470 1 EN 50470 3 IEC 62053 21 IEC 62063 22 and IEC 62053 23 standards specs for class 1 class 0 5 and class 0 2 AC watt meters B STPMOZH less than 0 5 error over 1 10000 range STPMOOI than 0 5 error over 1 5000 range Precision valtage reference 1 23 V with programmable TC STPMS2L only W internal low drop regulator amp 3 V typ Applications Power metering B Motor industrial process W Weight scales Pressure transducers bedded PGLNA STPMC1 device a digital signal processor design
56. y interface 2 FM 1 Mbit s SMBus PMBus for static memories supporting I Os SRAM PSRAM NOR and NAND Up to 114 GPIOs Ly o ES life augmented Digital Filter for Sigma peripherals Fitness application with PDM microphone input support P N Display STM32L4 rome Parallel interface to TFT SPI Up to 40 MHz speed OL 9 USB Sensors Batch Acquisition Mode USB OTG 2 0 UART full speed 3x SPls LPM and BCD Quad SPI OPAMP 6x USARTs e 2X With built in PGA DAC SAI 2x serial audio interfaces Low power sample and hold SWP ADC Ly Single wire protocol 3x 12 bit ADC 5 MSPS master interface SWPMI NM c life augmented n n ovat O n ELECTRONICS DFSDM Introduction External modulators on market his is external standalone device ADC converter on sigma delta principle Analog input usually differential and digital output Precision 16 bit resolution Provides digital output as fast 1 bit data stream gt serial interface Up to 20MHz speed of serial data Wide range of suppliers ST Analog Devices e STM32 interface DFSDM Digital Filter for Sigma Delta Modulators Implements complete post processing from external XA modulators outputs Receiving of data streams from XA modulators in various serial data formats Digital filtering of data str

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