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DPD/XPD VMEbus Intel® Core™ Duo Based Single

1. B 11 Firmbase Setup Menu The Firmbase menu configures the Firmbase Technology component of the system BIOS including all of the features enabled by it i e legacy USB keyboard and mouse boot from USB devices and support of Firmbase applications such as Boot Security Platform Update Facility and High Availability Monitor This menu has several parts with the most basic user oriented feature options in the top section and the more technical tuning parameters located in the lower sections The following table presents the settings that enable high level features enabled by Firmbase Technology Legacy USB Enables BIOS support for USB keyboards and mice Up to 8 USB keyboards and 8 USB mice may be supported at a time Use of PS 2 keyboard and mouse concurrently with USB devices is discouraged as the legacy PS 2 keyboard controller cannot easily separate simultaneous data streams from both device classes USB Boot Enables BIOS support for accessing USB mass storage devices and emulating legacy floppy hard drive and CDROM drive devices with them Enable this option in order for USB devices to be supported in the BBS device list see the BOOT menu EHCI USB 2 0 Enables EHCI Firmbase Technology driver allowing USB Boot feature to use high speed transfers on USB 2 0 ports in the system 42 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix B BIOS amp Setup Firmbase Disk I O
2. DPD XPD VMEbus Intel Core Duo Based Single Board Computer User s Manual XPD User s Manual Rev 1 01 October 2007 Dynatem 23263 Madero Suite C Mission Viejo CA 92691 Phone 949 855 3235 Fax 949 770 3481 www dynatem com Table of Contents 1 Features 2 Related Documents 3 Hardware Description 3 1 OVEN VIG WA e ccn eve le DE 2224024 ea pod o E 3 2 24 0 TEXT 0 L Lee pu Aan is WA IAA a DEIS E ANIL AE ted e 3 3 Chipset AA O RM O A COR E 3 4 IN MEETS 3 5 Intel 82571EB Dual Gigabit Ethernet Controller nn nn aaa aaa 3 6 ATI Rage Mobility MI Graphics Processor 3 7 Tundra Universe IID CA91C142D PCI VMEbus Interface 0000 3 8 PCI Mezzanine Card PMCX and KMC Expansion un 3 9 Intel s FW82802A Firmware Hub Holds the System BIOS In Flash Memory _ 3 10 Clock Drivers S eset testati dne eec toot Nana URA KE ABANA Cede se UNA La seien oa ON URA aan ab 3 11 CA eod 2 ds Dena io dt RS nd pest NN MI Tama Ne ada ad Nyata 3 12 Watchdog Timer Operation 00 4 Installation 41 Jumper Selectable Options 000 4 2 CompactFlash Drive Installation 000 LLL 4 3 PCI Mezzanine Card PMC Installation 0000 4 4 VMEbus Chassis Installation 202020222 2222222020202202 4 5 Front Panel Connectors and Reset Switch Dynatem XPD VMEbus Pentium Processor Board User s Manual D D J Connector Pin outs Front Panel USB Connector USB1 amp USB2 _ _ 1000BaseTX
3. 86K pulldown m mmm O A 5 PX PIRGTHEX PIRO 6 PXPIRGeWPX PIROS 7 Necmmedon 8 sve 9 PXPIROSWPX PIRGOK 10 No connection 31 32 _ 33 34 35 36 37 38 wwe O 39 pcxcap 40 LOCK 41 Noconnection 42 Noconnection Lis Ph 4 Nb 45 VOfrmJP3 46 AIS EMEN NM ME NN 49 50 We O 51 52 Gi8Eot 53 54 A 55 956 COND J _ 57 58 ADS 59 Aa 0 60 A 68 AD J 62 wo O 63 GND 64 Ra PCI X Mezzanine Card PMCX Connector JN1 Molex 71439 0164 VI O fro JP3 VIO is jumper selectable through JP3 please see Section 4 1 Dynatem XPD VMEbus Pentium Processor Board User s Manual 25 Appendix A Connector Pin outs 26 Signal O ND No connection No connection GND 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 9 18 15 17 19 21 23 25 27 29 381 33 95 37 39 al 43 45 I E49 51 s 53 55 al c GND 20 2 24 26 28 0 3 34 36 3 0 4 4 46 4 0 4 6 2 3 2 8 4 2 4 8 5 52 5 5 58 62 TRST pulled down C BE2 D D a0 60 Noconnection ACK64 62 43 3 VDC No connection PCI X Mezzanine Card PMCX Connector JN2 Molex 71439 0164 XPD VMEbus Pentium Processor
4. Dynatem XPD VMEbus Pentium Processor Board User s Manual 5 Chapter 3 Hardware Description AAA AA A iia ii ulo 3 2 Processor The KPD supports a Core Duo processor at 1 66 GHz The Intel Core Duo processor with 2 MB of L2 cache is the first dual core processor available for mobile and embedded applications Features include e 667 MHz front side bus limited by the E7520 FSB e On die 2 MB of L2 cache with Advanced Transfer Cache Architecture e On die primary 32 KB instruction cache and 32 KB write back data cache e Second generation Streaming SIMD Extensions 2 SSE2 and streaming SIMD Extensions 3 SSE3 e Supports Intel Architecture and Dynamic Execution For further information on the Core Duo processor available from Intel Corporation search at http developer intel com design mobile core duodocumentation htm The Intel Core Duo processor was designed to deliver high dual processor high performance with low power consumption With its 65 nm processing technology and 2 MB of L2 advanced transfer cache the Core Duo offers more performance per Watt The Thermal Design Power TDP is 15 W Advanced power management included Enhanced Intel SpeedStep Technology are supported SpeedStep enables clock and core voltage throttling based on temperature or processor loading The processor s 667 MHz Front Side Bus utilizes a split transaction deferred reply protocol The FSB uses a Source Synchronous Transfer SST of
5. Enables Firmbase Technology FAT file system driver so that Firmbase applications such as Boot Security Platform Update Facility and HA Monitor as well as the HA and TCB components of the kerne have access to files residing on drives containing FAT file systems Also turn on this option if you wish to run Firmbase applications from FAT file systems on either ATA or USB mass storage devices Firmware Application Suite Enables Firmbase applications configured for the system by the OEM Typically includes Boot Security Platform Update Facility and High Availability Monitor Firmbase User Registry Not used Firmbase User Shell Enables Firmbase Technology command line interpreter a multi user command shell with DOS like and Unix like command structure can be used to start Firmbase applications written with the Firmbase SDK a General Software product Firmbase Technology Enables Firmbase Technology as a whole the industry s most comprehensive and fullfeatured System Management Mode SMM operating environment Some hardware platforms reguire Firmbase Technology to run as they may use it to virtualize hardware such as virtual video and audio PCI devices Some BIOS features such as ACPI and APM may reguire Firmbase Technology to operate Firmbase Debug Log Specifies the device used by Firmbase Technology components kernel drivers and programs to display debugging instrumentation produced with the dprintf and
6. LPT1 and FDC is SMSC s LPC47B272 and a data sheet can be found at http www smsc com main catalog Ipc47b27x html Here is a photograph of the XPDPTB with the connectors indicated SATAO SATA1 Cms wm D Dynatem XPD VMEbus Pentium Processor Board User s Manual 49 Appendix D XPDPTB Rear Plug in I O Expansion Module for the XPD D 1 XPDPTB Connector Pinouts RST GND Pn Sina Pn Signal 3 Ins 2 Ion fr fs s os 7 8 w 1 9 m 39 b n p tee 1 p 4 b 1 p b4 o V 8 b Primary IDE Interface Connector J5 40 pin Dual row 0 1 Header D7 D5 D4 D3 D2 D1 COMI and COM2 ports are set up for RS 232 operation J3 is used for COMI and J4 is used for COM2 The pinouts of the two connectors are identical 50 an 2 Data Carrier Detect DCD Input o Received Data RID input ND 5 GND 7 8 Clear To Send CTS Input Ring Indicator RI Input COM1 J3 and COM2 J4 Connectors DB9M Connector The metal shell of the connector goes to chassis ground Ed 6 Data Set Ready DSR Input 7 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix D XPDPTB Rear Plug in I O Expansion Module for the XPD COM3 and COM4 ports are set up for two wire RS 232 operation J2 is used for COM3 and Jl is used for COMA The pinouts of the two connector
7. Clock 48 MHz To ICH for USB amp Serial MH To Ethernet Routed to ICH for Jui 250 _ Controllers USB and UART s and Oscillators 82571EB amp to the MCH for 82571EB and Graphics 64 0 MHz To Universe Oscillator IID CLK64 To MCH for dot clocks Clock Driver Circuitry The clocks are generated by the 9328208 which is driven by a 14 31818 MHz crystal DRAM clocks are synthesized by the MCH and Hub Interface and PCI X clocks are produced by the ICH A 32 768 KHz Crystal drives the Real Time Clock RTC on the ICH The Fast Ethernet port provided to the front panel by the 82571EB and the two 1 Gb Ethernet ports provided to the backplane by the 82571EB require separate 25 0 MHz oscillators one of the two oscillators is also used for the watchdog timer clock A 64 0 MHz oscillator drives the Universe IID CA91C142D VMEbus circuitry 12 XPD VMEbus Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description 311 Reset Circuitry The reset circuitry is shown below Pull up Universe IID CA91C142D sa Front Panel Reset Switch 5 VDC Monitor VCSR_SET RESET VCSR_CLR RESET m VMEbus SYSRESET rr p JP4 DS1232 Reset Registers State Machines m PB1 Watchdog Strobe ian 2 NAND Gate SYSRESET PCIRST PCI peripherals General Purpose Output Reaister s GPIO20 14 318 MHz Clock Reset Control Register INIT Core Duo soft reset MA PWRGD_VR Vcore 4 Monitor g
8. Fast Ethernet Front Panel Connector J1 CompactFlash Interface Connector J3 VMEbus Connectors P1 P2 and PO PCI X Mezzanine Card Connectors JN1 JN2 JN3 and JN4 and XMC Connector J15 BIOS amp Setup Setup Menus ss Navigating Setup Menus amp Fields Main Setup Menu Exit Setup Menu Boot Setup Menu 2 2 1 POST Setup Menu PnP Setup Menu Super I O SIO Setup Menu Features Setup Mena sss Firmbase Setup Menu Miscellaneous Setup Menu Power and Environmental Requirements XPDPTB Rear Plug in I O Expansion Module for the XPDPTB Connector Pin outs XPD XPD VMEbus Pentium Processor Board User s Manual 47 49 50 Dynatem Chapter 1 Features 1 Features The Dynatem XPD is a single slot 6U VMEbus Single Board Computer SBC The XPD offers full PC performance with a Core Duo processor The XPD is available in two versions the lower cost DPD for standard industrial applications and the 1101 2 compliant conduction cooled RPD with wedgelocks stiffener bar and a full board heatsink for rugged applications When referring to attributes of both versions we will use the common name XPD The XPD employs Intel s embedded technology to assure long term availability Features of the XPD include e A 1 66 GHz Intel Core Duo processor with 2 MB of L2 cache e Single slot VMEbus operation with on board CompactFlash disk for bootable mass storage and front panel connectors for two USB 2 0 port
9. The standard Embedded BIOS setup menus are described below in the order they generally appear in the menuing system Dynatem cannot vouch for support for all BIOS functions described in the subseguent sections Main Display main system components and allow editing of date and time Exit Save changes and exit discard changes and exit or restore factory default settings Boot Configure boot actions and boot devices POST Configure POST PnP Configure Plug n Play for non ACPI OSes SIO Configure Super I O devices such as serial ports and parallel ports Dynatem XPD VMEbus Pentium Processor Board User s Manual 31 Appendix B BIOS amp Setup Features Enable and disable system BIOS features like ACPI APM PnP MP guick boot and the splash screen Firmbase Configure Firmbase Technology and the features that use it such as USB keyboard and mouse support commonly USB HID boot from USB commonly USB Boot and applications such as high availability boot security not user security but chain of trust security and network based remote access Misc Configure miscellaneous BIOS settings that do not fall into any other category Shadowing Configure chipset shadow RAM regions Security Configure which BIOS features reguire user authentication before they perform their functions CUI Configure the layout and coloring of the Common User Interface CUI display engine that supports pre
10. bits wide with ECC The XPD can be populated with one or two banks of DRAM for GB or 2 GB of total memory respectively Each bank is serviced by a separate channel from the MCH that function in lock step mode Memory controller features include e Memory mirroring allows for two copies of all data in the memory subsystem one on each channel to be maintained e Hardware periodic memory scrubbing including demand scrub support 6 XPD VMEbus Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description b t a zx e Retry on uncorrectable memory e ECC is supported e DDR2 400 DRAM is supported on board The 6300ESB I O Controller Hub ICH provides most of the XPD s on board I O and it s the XPD s PCI X expansion bridge The ICH is designed as a low power high performance I O hub that features e 64 bit E 66 MHz PCI X expansion that is used on the XPD for the two on board PMC X slots e Four USB 2 0 compliant ports two of which are routed to the front panel while the other twoare routed to the P2 connector to the backplane e Integrated IDE controller supports Ultra 100 DMA Mode Transfers up to 100 MB sec read cycles and 88 88 MB sec write cycles for a CompactFlash drive on board and a primary IDE port that is routed through P2 to the XPDPTB e Two Serial ATA ports providing 150 MB sec data rates are routed through PO e Standard PC functionality like a battery bac
11. causing certain preconfigured OEM optimizations to be made when the system boots Depending on the system Quick Boot can reach the DOS prompt in as little as 85ms milliseconds Advanced Power Enable legacy power management used by the system when an ACPl aware Management APM operating system is not running during POST such as when the system is running the preboot environment or while running DOS Windows95 Windows98 or Linux kernels below version 2 6 Uses the SMM feature see Firmbase to operate properly ACPI Enable ACPI system description and power management ACPI replaces PnP and APM Used with ACPI aware OSes such as Linux kernels version 2 6 and above Windows XP and Windows Vista Commonly also uses the SMM feature see Firmbase to operate properly POST Memory Manager Enable memory allocation services for option ROMs especially network cards PMM running PXE Some option ROMs may use this interface incorrectly causing system crashes Other PXE option ROMs may not run if PXE is not supported Because of the state of these option ROMs the setting is provided as an option to the user SMBUS API Enable INT 15h services that permit certain software to access devices on the system s SMBUS without having knowledge of the SMBUS controller itself System Management BIOS Enable System Management BIOS interface specification support exposing SMBIOS information about the type of hardware including the chassis motherboard layout
12. i e whether or not to load SMM POST Display PCI Devices Enable display of PCI devices POST Display PnP Devices Enable display of ISA PnP devices The following table describes the settings associated with the POST setup menu s Debugging section POST Debugger Breakpoints Enable processing of INT 3 breakpoint instructions embedded into option ROMs When enabled if an INT 3 instruction is encountered control is transferred to the BIOS debugger so that the option ROM can be debugged When disabled these instructions perform no action POST Fast Reboot Cycle Enable early reboot in POST allowing service technician to verify that the hardware can technician to verify that the hardware can reboot very quickly many times in succession Platform will continue to reboot after every boot until the system s CMOS is reset as there is no way to enter Setup from this early point during POST POST Slow Reboot Cycle Enable late reboot in POST allowing service technician to cause the system to move through POST and then reboot causing POST to be reexecuted over and over until Setup is reentered and this option is disabled When left unattended this is a straightforward way of having POST exercise system memory and peripherals without requiring a boot to a drive with an operating system installed The following table describes the settings associated with the POST setup menu s Device Initialization sec
13. out to the PO backplane connector in compliance with the VITA 31 1 specification VITA 31 1permits fabric switching on the backplane where 31 1 compliant SBC s can communicate with each other and with an external network through switch modules that are located at either end of the backplane Optionally these two 1 Gb Ethernet ports are brought to industry standard RJ 45 connectors on Dynatem s rear I O plug in module XPDPTB The two Ethernet ports provided by the DPD s 2 8257 1EB are accessible from the front panel Technical documents on Intel s 82571EB Dual Gigabit Ethernet Controller are available at http www intel com design network products lan docs 82571eb docs htm 3 6 ATI Rage Mobility M1 Graphics Processor The ATI Rage Mobility M1 processor generates VGA graphics which are routed to the PO backplane connector A VGA connector is provided by the optional XPDPTB rear I O module The Rage Mobility M1 s features include e Supports both independent displays at 1280x1024 24bpp 60Hz in 64 bit and 1024x768 24bpp 60Hz in 32 bit see mode tables for details e Primary display path supports VGA and accelerated modes video overlay hardware cursor hardware icon 128x128 and 24 bit palette gamma correction The Rage Mobility M1 offers low power graphics for limited GUI purposes It attaches to the system via the ICH s 32 bit 9 33 MHz PCI bus ATI Rage Mobility M1 Signal PCI Bus Connection Bus PCI IDSEL AD17
14. perform the actions in order During this boot phase if the list item is a drive an attempt is made to boot from the boot record of that drive If the list item is a device like a network card or PCI slot an attempt is made to boot from that device If the list item is a software item like Boot Debugger then it performs that action and when that action completes it moves on to the next item in the BBS list The table that follows lists the set of standard boot action items drive name The system BIOS may list the Boot from the MBR PBR of the named BIOSaware IPL drive s name in a generic sense i e USB Hard drive BAID The drive may be Legacy Floppy PATA Drive if the drive has not been detected yet orthe SATA Compact Flash or a USB drive drive s full manufacturing name and serial number Dynatem XPD VMEbus Pentium Processor Board User s Manual 35 Appendix B BIOS amp Setup if detected IDEO Primary Master Primary Master PATA drive or SATA mapping by the chipset routed to the backplane via P2 IDE1 Primary Slave Primary Slave PATA drive or SATA mapping by the chipset routed to the backplane via P2 IDE2 Secondary Master Secondary Master PATA drive or SATA mapping by the chipset routed to on baord CompactFlash IDE CDROM First detected IDE CDROM USB Floppy Drive First detected USB floppy drive USB Hard Drive First detected USB hard drive US
15. 3 0 VDC Lithium Coin Cell 3 4 uA Power Reguirements The 3 Volt lithium coin cell is a CR2032 with 190 mAhours capacity and it is used to battery back the Real Time Clock the 2 MB of NV SRAM and the BIOS s NV RAM At 3 4 UA this battery should last for over six years with power off Operating Temperature 20 to 85 C with Thermal Monitor II enabled Storage Temperature 50 to 105 C Environmental Reguirements Dynatem XPD VMEbus Pentium Processor Board User s Manual 47 Appendix C Power 8 Environment Requirements A E 48 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix D XPDPTB Rear Plug in I O Expansion Module for the XPD D XPDPTB Rear Plug in I O Expansion Module for the XPD Dynatem offers a rear plug in paddle card for 1 0 expansion with the XPD Essentially the XPDPTB routes the XPD s backplane I O including IDE COM1 2 3 4 P S2 Mouse Keyboard interfaces VGA two USB ports and two SATA ports to industry standard connectors IDE the four COM ports two USB ports and mouse and keyboard ports are routed through P2 The two Ethernet ports two SATA ports and the VGA port are routed through PO Two Serial ATA ports are routed through RPO The XPDPTB also routes two VITA 31 1 compliant 1 Gb Ethernet ports from RPO to two industry standard connectors for situations where VITA 31 1 backplane fabric switching is not used The Super I O device used for COM3 4 P S2 Mouse Keyboard
16. B CDROM Drive First detected USB CDROM Enter Board Information Browser Invoke HTML Browser on 0 HTM in ROM Enter BIOS Setup Screen Invoke System Setup Utility in ROM Reboot System Enter BIOS Debugger Invoke BIOS debugger in ROM Restart system Power Off System Invoke S5 state powering off system PCI Slot n Boot from device in PCI Slot n Network Boot from any network adapter SCSI Boot from external SCSI device on PMC XMC card Boot EFI Binary Boot EFI kernel from ROM or disk depending on the EFI source setting in the Features menu If disk is selected then the BIOS searches all the configured disks in the system in the order they appear in the BBS list attempting to load EFILDR BIN from the root directory in the FAT file system located on those drives Boot Windows CE Image Boot Windows CE kernel from disk The BIOS searches all the configured disks in the system in the order they appear in the BBS list attempting to load NK BIN from the root directory in the FAT file system located on those drives Boot Graphical Desktop Boot Firmbase GUI supporting graphical Firmbase applications as well as booting DOS in a graphical window For applications requiring instant on functionality even when the OS is not available or is still loading The photograph above shows a common setup of the BBS list for desktop applications In this example the first boot devic
17. Board User s Manual Dynatem Dynatem Appendix A Connector Pin outs Pin Signal Pin Signal 3 GND 5 a 6 CBE 7 cB 8 GND s vio 10 Paa 5 Nocomecion 60 Noconnecion PCI X Mezzanine Card PMCX Connector JN3 Molex 71439 0164 XPD VMEbus Pentium Processor Board User s Manual 27 Appendix A Connector Pin outs No connection 60 Noconnection PCI X Mezzanine Card PMCX Site 1 Connector J14 Molex 71439 0164 J14 is the JN4 I O connector for PMC Site 1 These lines will be routed to the D amp Z rows of the P2 backplane connector 28 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs PCI X Mezzanine Card PMCX Site 2 Connector J24 Molex 71439 0164 J24 is the JN4 I O connector for PMC Site 2 These lines will be routed to the pins shown for the PO backplane connector Dynatem XPD VMEbus Pentium Processor Board User s Manual 29 Appendix A Connector Pin outs Following is the pinout for the XMC connector associated with PMC XMC Site 1 The XMC site routes x8 PCI Express to the mezzanine card Pin Column A ColummB ColumnC ColummD ColumnE ColumnF KMC Bus Connector J15 for XPD Rev A PWB D010 6065 001 30 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix B BIOS amp Setup B BIOS amp Setup The DPD uses General Softw
18. DPRINTF system functions None Instrumentation disabled COMI Write text to 1st serial port COM2 Write text to 2nd serial port COM3 Write text to 3rd serial port COM4 Write text to 4th serial port Virtual Write text to virtual console If enabled this console can provide diagnostic messages similar to the types displayed by Linux when it boots for Firmbase Technology features such as USB HID and USB Boot Firmbase System Console Specifies the device used by Firmbase Technology s system process when it initializes the kernel and processes the SYSTEM registry section including its Start and Run commands None System console disabled COMI Write text to Ist serial port COM2 Write text to 2nd serial port COM3 Write text to 3rd serial port COM4 Write text to 4th serial port Virtual Write text to virtual console If enabled this console can provide a list of sign on banners of all Firmbase applications loaded during system initialization Firmbase Shell on Serial Port Specifies a serial port that may be used by Firmbase Technology s command line interpreter as an extra user session for systems that do not have a keyboard or monitor to support virtual consoles None Serial console disabled COMI Console on Ist serial port COM2 Console on 2nd serial port COM3 Console on 3rd serial port COMA Console on 4th serial port Dynatem XPD VMEbus Pentium Proc
19. JEFE Draft Std P1386 1 2 0 Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC The Institute of Electrical and Electronic Engineers 345 East 47th Street New York NY 10017 800 678 4333 e VITA 42 0 KMC Switched Mezzanine Card Auxiliary Standard VITA 10229 North Scottsdale Road Suite B Scottsdale AZ 85253 480 951 8866 4 XPD VMEbus Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description muA M M d eae 3 Hardware Description 3 1 Overview The block diagram of the XPD is shown below The sections that follow describe the major functional blocks of the XPD Intel Core Duo Processor 65 nm 1 667 MHz Front E Intel I Panel co 82571EB y ENET 4 FSB x4 PCle 64 GBytes s 2GB DDR2 400 Controller Hub x4 PCle 1 x8 PCle 1 Compact I B bit HI 1 5 8 266 MB s Flash 1 i I T A Secondary IDE E SATA 0 and 1 LPS Due IDE Bus si 64 bit PCI X 66 MHz 32 bit 33 MHz B 4 Intel 82571EB M 1 1 CA91C142 i PMC 1 ATI i XMC 1 Universe It 1 Site I Rage I YAA L Dual Gb je 1 Mobility I Front end 1 ie 5 I p andrear I a PMC VO I XMC PMC m mm q m m m m m VME P0 F oa VME P1 and P2 O 2 A aa aaa a a a ua a d
20. REQ REQ1 GNT GNT1 INTR INTB 8 XPD VMEbus Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description ea Se A AAA 3 7 Tundra Universe IID CA91C142D PCI VMEbus Interface The PCI VMEbus interface based on the Tundra Universe IID CA91C142D offers the following features e High performance 64 bit VMEbus interface e Integral FIFOs for write posting allow the Universe IID to quickly relinquish the bus e Programmable DMA controller with linked list support e Full VMEbus system controller functionality e Complete VMEbus address and data transfer modes A32 A24 A16 master and slave D64 MBLT D32 D16 D08 master and slave The block diagram of the PCI VMEbus interface is shown below A01 A31 LWORD VMEbus DOO D31 AS DS0 DS1 Ctrl Universe IID CA91C142D IRQx BRx PCI Bus AD 31 0 INTG REQ1 GNT1 VMEbus P1 Connector VMEbus P2 Connector Reset Circuitry I O Controller Hub ICH IDE P2 User Defined Pins Low Pin Count LPC Bus PCI VMEbus Interface Block Diagram Dynatem XPD VMEbus Pentium Processor Board User s Manual 9 Chapter 3 Hardware Description s5 553333335 As shown in the block diagram several peripheral signals are routed to the user defined pins of the VMEbus P2 connector the IDE bus and the LPC bus which routes to a Super I O chip on the XPDPTB rear plug in card for I O expansion The VMEbus PI and P2 connector pin outs are gi
21. VMEbus Pentium Processor Board User s Manual 33 Appendix B BIOS amp Setup The system memory information does not describe physical RAM rather it describes the RAM as configured subtracting RAM used for System Management Mode Shadowing Video buffers and other uses This provides realistic values about how much memory is actually available to operating systems and applications The Real Time Clock fields are editable with keystrokes To navigate through the MM DD Y Y YY and HH MM SS fields use the TAB and BACKTAB keys The hours are normally specified in military time thus 13 means 1pm or one hour after noon whereas 01 means lam or one hour after midnight When the cursor leaves RTC fields they either affect the battery backed RTC right away allowing the system to continue with your new settings or they revert back to old values if the new values are not valid entries B 5 Exit Setup Menu The Exit menu provides methods for saving changes made in other menus discarding changes or reloading the standard system settings This menu is shown in Figure 3 2 below To select any of these options position the cursor over the option and press the ENTER key Pressing the ESC key at any time within the Setup system is equivalent to requesting Exit Setup Without Saving Changes 34 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix B BIOS amp Setup B 6 Boot Setup Menu The Boot menu allows the s
22. address and data to improve performance by transferring data four times per bus clock The address bus can deliver addresses twice per clock cycle Together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 5 33 GB second 3 3 Chipset The Intel E7520 Memory Controller Hub MCH and Intel 6300ESB I O Controller Hub ICH chipset provide memory control mass storage and basic I O and standard PC system resources including the real time clock NV RAM timers thermal management and interrupt management Also the MCH provides 24 lanes of PCI Express expansion 16 of which are implemented on the XPD for high speed expansion through the two dual 1000BaseTX controller chips and the XMC site The ICH supports a 32 bit 33 MHz PCI bus to support the Universe VMEbus interface controller and the ATI Rage Mobility M1 graphics chip and a 64 bit 66 MHz PCI X bus for user I O expansion through the two PMC sites The ICH also provides a Low Pin Count LPC interface for the BIOS flash chip and for Super I O and an SMBus interface for on board resources like the DRAM circuit s SPD PROMs and the thermal monitors The MCH supports a base system bus frequency of 200 MHz The address and request interface is double pumped to 400 MHz while the 64 bit data interface parity is quad pumped to 800 MHz This provides a matched system bus address and data bandwidth of 6 4 GB s The E7520 MCH provides a 400 MHz interface to DDR2 RAM 72
23. al Description Port B Transmit Data TX B Transmit Data TX B Receive Data RX Unused Unused B Receive Data RC Unused Unused Gb Signal Description 2 gt gt WANA UND E In dun E p a EE as gt o c o de UJ UJ w 10BaseT 100BaseTX Fast Ethernet Connector J7 J6 RJ45 Connectors The metal shell of the connectors go to chassis ground J8 is a dual USB connector Each connector has the same pinout as shown in Section A 3 52 XPD VMEbus Pentium Processor Board User s Manual Dynatem
24. apses GPIO20 is controlled by bit 20 in the ICH s GP LVL register GPIO20 reflects the status of bit 20 GPIO20 is high if bit 20 is at logic 1 and it is low if bit 20 is at logic 0 GPIO20 is high at reset so the watchdog timer will only be activated when the user drives bit 20 of the GP LVL register low For instructions on programming the GP LVL register refer to the Intel 6300ESB I O Controller Hub Data Sheet from Intel Corporation Document 300641 002 14 XPD VMEbus Pentium Processor Board User s Manual Dynatem Chapter 4 Installation 4 Installation The following sections cover the steps necessary to configure the XPD and install it into a VMEbus system for single slot operation This chapter should be read in its entirety before proceeding with the installation 4 1 Selectable Options This section explains how to set up user configurable jumpers and how to install CompactFlash drives and PMC modules The XPD is shipped in an antistatic bag Be sure to observe proper handling procedures during the configuration and installation process to avoid damage due to electrostatic discharge ESD The XPD contains eight jumpers JP3 is located near JN1 for the second PMC site Jumpers JP1 through JP8 minus JP3 are arranged in order as shown below CompactFlash Drive aan renee nes e RP T iin ii 1111411 1141 j JP3 JP1 JP8 Dynatem XPD VMEbus Pentium Processor Board User s Manual 15 Chapter 4 In
25. are s Embedded BIOS with StrongFrame Technology Rev 6 The BIOS is configured with the System Setup Utility accessible from the Preboot Menu This photo shows the initial splash screen that is displayed after powering up the system as the BIOS runs through the Power On Self Test POST When your system is powered on Embedded BIOS tests and initializes the hardware and programs the chipset and other peripheral components Embedded BIOS with StrongFrame Technology DPD Dynatem Core CPU Chipset Intel E7520 amp 6300ESB www dynatem com To enter the Setup mode please press the delete Del key on your keyboard after powering up your system during POST B 1 Redirecting to a Serial Port Setup may be run from the main keyboard and video display or from a terminal emulator program running on a host computer connected to the system through a serial cable To use a serial port connect a dumb terminal or a PC running a terminal emulation utility like Hyperterminal to COMI via a null modem Next set the communications parameters of the host s terminal program to 115Kbaud Other parameters are 8 bit no parity and one stop bit Do not enable XON XOFF or hardware flow control With this link set up power on the system Press C a few times on your dumb terminal or your PC as the system boots POST will redirect to the serial console and after it has completed its early stages it will start the preboot menu B 2 Setup Menus
26. atible and can support any modules from 32 bit PMC cards at 33 MHz to 64 bit PMCX modules at 66 MHz The PMCX sites on the XPD are routed from the ICH s PCI X bus interface which is 64 bits wide and has a maximum clock rate of 66 MHz PMCX sites Available Data Rates with VIO 5 V Available Data Rates with VIO 3 3 V JP3 is shunted between pins 2 amp 3 JP3 is shunted between pins 1 amp 2 1 amp 2 33 MHz 33 MHz and 66 MHz The General Software BIOS will determine during startup what the status of the PCI X bus The BIOS monitors the following pins that are routed to the ICH PCIXCAP PCX X capable and M66EN 66 MHz capable The user s manual on your PMC X modules will tell you how PCIXCAP JNI pin 39 and M66EN JN2 pin 47 are configured Since both sites share the same bus JP3 sets the VIO voltage for both sites and the bus will only clock as fast as the slower PMC card Conventionally PMC connectors have four designators JN1 JN4 JN1 8 JN2 provide all the signals necessary for 32 bit PCI transactions JN3 has the 32 additional data lines required for 64 bit transfers and JN4 routes I O off the module for possible backplane access see Section A for J14 to P2 and J24 to PO backplane PMCX I O routing The following table lists the reference designators used on the XPD s PMC X sites 1 also supports XMC J14 to P3 124 to PO 4 4 VMEbus Chassis Installation Unless your VMEbus chassis features automatic daisy chain
27. boot applications Chipset Configure any chipset specific parameters such as memory CPU and bus timing and availability of chipset specific features such as TFT support Highly platform specific and entirely up to the OEM s implementation B 3 Navigating Setup Menus and Fields Navigation moving your cursor around selecting items and changing them is easy in theSetup system The following chart is a helpful user reference UP key also E Move the cursor to the line above scrolling the window as necessary DOWN key also X Move the cursor to the line below scrolling the window as necessary LEFT key Go back to the menu to the left of the currently displayed menu in the menu bar RIGHT key Go forward to the menu to the right of the currently displayed menu in the menu bar PGUP key Move the cursor up several lines a full window s worth scrolling the window as necessary PGDN key Move the cursor down several lines a full window s worth scrolling the window as necessary HOME key Move the cursor to the first configurable field in the current menu scrolling the window as necessary END key Move the cursor to the last configurable field in the current menu scrolling the window as necessary ESC key Exit the Setup system discarding all changes except date time changes which take place on the fly TAB key Move the cursor down to the next configurable field Shift TAB key back
28. crews to the outside of the ejector handles to complete the installation of the XPD in the VMEbus chassis 4 5 Front Panel Connectors and Reset Switch The XPD offers front panel connections for two USB ports and two RJ45 connector for 1000BaseTX Ethernet ports Install all front panel cables by inserting them into the appropriate connector COM1 and DVO VGA cables can be secured to the XPD by tightening their thumbscrews into the connectors jackscrews USB and Ethernet mating connectors should snap into place Mounting hardware for the front panel connectors are isolated from the XPD s digital ground They are continuous with the front panel itself that in turn is common with chassis ground The XPD contains a recessed reset switch accessible from the front panel To reset the XPD press the reset switch using a small screwdriver blade or similar implement The Ethernet connectors each have a pair of indicator LEDs built in These two green LEDs offer stats on the 1000BaseTX port provided by the 82571EB Ethernet controller on the XPD e Link Ethernet link is established when on This LED is to the left or top when the XPD is held vertically e Activity Ethernet data is being transmitted from or received by the XPD when on This LED is to the right bottom of the Link LED 18 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs A Connector Pin outs The locations of the XPD connec
29. d can also support an MC module with up to x8 PCI Express e Secondary IDE port for CompactFlash on board for flash based or mechanical mass storage for 1 slot booting e General Software s Version 6 0 flash based system BIOS e PXE for diskless booting over Ethernet e Programmable watchdog timer for system recovery and a CPLD for LED control Geographical Addressing and Built In Test BIT status and control e Operating System OS and driver support including Windows NT Embedded NT XP QNX VxWorks Linux Solaris and pSOS 2 XPD VMEbus Pentium Processor Board User s Manual Dynatem Chapter 2 Related Documents AAA AAA A AAA A A AAA AAA 2 Related Documents Listed below are documents that describe the Pentium processor and chipset and the peripheral components used on the XPD Either download from the Internet or contact your local distributor for copies of these documents The XPD uses the L2400 Low Voltage Core Duo For information on this processor go to http developer intel com design mobile core duodocumentation htm For the ICH component in the 6300ESBchipset get the Intel e 6300ESB I O Controller Hub Datasheet It is document number 300641 002 ftp download intel com design intarch datashts 30064102 pdf For information on the E7520 MCH component in the chipset please go to http www intel com design chipsets embedded e7520_7320 htm For data sheets on I O controllers e 82571EB Fast Ethe
30. e Description aa aa zH 3 8 PCI X Mezzanine Card PMCX and XMC Expansion The XPD supports two PCI X Mezzanine Card PMC X sites on board Site 1 also supports x8 XMC cards Site 1 routes I O from J14 out through the P2 connector please see Appendix A or it can be accessed from the front panel Site 2 routes I O from J24 to the PO backplane connector and or to the front panel 3 9 Intel s FW82802AC Firmware Hub Holds the System BIOS In Flash Memory The Intel FW82802AC uses a 5 pin interface and provides 1 MByte of flash memory for the system BIOS This device can fill the 1 MB real mode memory map so only a portion its upper 256 MB is used The FW82802AC s 1 MB of memory space is segmented into sixteen parameter blocks of 64 KB each The XPD powers up into real mode and the BIOS is eventually shadowed into system DRAM after booting through the BIOS The ICH provides the 5 pin interface to the ES2802AC The upper 256 KB of the E82802AC is located from 000C0000 OOOFFFFF and its full 1 MB of memory is aliased from FFF00000 FFFFFFFF where it can be fully accessed after booting up through the BIOS Here s a link to a datasheet for the 82802AC ftp download intel com design chipsets datashts 29065804 pdf 3 10 Clock Drivers The clock driver circuitry is shown below 9325208 Crystal E f 100 MHz differential clocks for MCH ICH To MCH for SDRAM Clocks ITP amp CPU clocks ICH 32 768 KHz To ICH for Real Time ITP Port
31. e is theWestern Digital IDE hard drive WDC WD800JB 00JJCO connected to the target as a Primary Master IDE drive The second boot device is the Secondary Master and this is the on board CompactFlash The third device is a USB Hard Drive A fourth boot device None is a placeholder that is simply used to add more entries in the setup screen None is not actually executed by POST as a boot action item In addition to the BBS boot device list there are two more sections in the BOOT menu namely the Floppy Drive Configuration and IDE Drive Configuration sections Both of these sections tell the BIOS what kind of equipment is connected to the motherboard but the floppy drive interface has not been implemented so please ignore this and leave it as Not Installed Similarly the IDE Drive Configuration section describes the type of hard drive equipment that is connected to the motherboard including the cable type IDE drives or actually more properly Parallel ATA PATA drives are connected to the motherboard with a flat cable with either 40 or 80 wires running in parallel hence Parallel ATA as opposed to Serial ATA The 40 pin connector supports speeds up to UDMA2 whereas 80 pin cables are needed for higher transfer rates to eliminate noise The BIOS can be told what type of cable is available so that it knows whether higher transfer rates are allowed or it can be told to autodetect the cable type in which case the drive and the moth
32. em Modern processors virtually require cache to be enabled to achieve acceptable performance However to diagnose certain problems related to caching in the system such as multiprocessing systems it may be desirable to disable this setting Keyboard Numlock LED Enables the Numlock key when POST initializes the PS 2 keyboard Typematic Rate Specify the rate at which the PS 2 keyboard controller repeats characters when most keys are pressed down USB typematic is automatic and does not use this parameter Typematic Delay Specifies the amount of time a repeating key may be pressed on a PS 2 keyboard until the key repeat feature begins repeating the keystroke USB typematic is automatic and does not use this parameter 44 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix B BIOS amp Setup Lowercase Hex Displays Enables the display of hexadecimal numbers in the debugger with lowercase letters instead of uppercase letters ie 2f8ah instead of 2F8AH Proprietary Stimulation Enables System Monitor s callout to the OEM s BPM adaptation code to execute code that causes stimulation of the SMM environment for measurement purposes Hard Disk Read Stimulation Enables System Monitor s read of a preconfigured number of sectors from a location on the first hard disk in the system in order to stimulate the SMM environment This is useful when measuring code path lengths in USB boot wh
33. en the first hard drive is configured in the BBS list as a USB hard drive Hard Disk Write Stimulation Enables System Monitor s write of a preconfigured number of sectors to a location on the first hard disk in the system in order to stimulate the SMM environment This is useful when measuring code path lengths in USB boot when the first hard drive is configured in the BBS list as a USB hard drive Please note that when this parameter is selected the system automatically enables reading so that the stimulation of the system includes reading a range of sectors into a memory buffer and writing the same data back to the same range of sectors for safety Thus this feature is theoretically nondestructive WARNING YOU ARE ADVISED THAT THIS FEATURE COULD CAUSE DATA LOSS AT YOUR SOLE EXPENSE ACCORDINGLY IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND ALWAYS BACKUP YOUR DATA BEFORE PERFORMING DIAGNOSTICS ON ANY SYSTEM AS THEY COULD CAUSE DATA LOSS Floppy Disk Read Stimulation There is no Floppy Drive interface implemented on the DPD Dynatem XPD VMEbus Pentium Processor Board User s Manual 45 Appendix B BIOS amp Setup 46 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix C Power 8 Environment Requirements 555 C Power and Environmental Reguirements The KPD power and environmental reguirements are shown in the tables below 1 66 GHz Core Duo 45 VDC 6 0 typ
34. erboard must both support the hardware protocol used to autodetect the drive s cable type Note PATA cable autodetection sometimes fails with older drives so 40 pin is the default to ensure data integrity For higher performance you should change this setting to 80 pin or AUTO if an 80 pin cable is installed 36 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix B BIOS amp Setup B 7 POST Setup Menu The POST menu is used to configure POST This menu is shown in the following figure scrolled down more so the full set of options can be seen Be sure to review the Features menu where additional items can be configured such as the Splash Screen and BIOS initiatives nfiguration Utility TM Technology C The figure below shows the same menu scrolled down so that the remainder of its fields may be viewed System Conf iguration Utility Tn m Enab led are Inc Embedded BIOS R w StrongFrame TM Technology C 2887 General Software Dynatem XPD VMEbus Pentium Processor Board User s Manual 37 Appendix B BIOS amp Setup The following table describes the settings associated with the POST setup menu s Memory Test section Low Memory Standard Test Enable basic memory confidence test of memory below 1MB address boundary conventional memory or memory normally used by DOS Low Memory Exhaustive Test Enable exhaustive memory confidence test of memory below 1MB addres
35. ermine the signaling voltage on the PMC modules PCI interface Refer to the PMC modules reference manuals to ascertain the recommended VIO Shunting pins 1 2 of JP1 provides a VIO of 3 3 VDC Shunting pins 2 amp 3 routes 5 VDC to the VIO pins on the PMC modules VIO Voltage Level 83 VDC 5 VDC Battery Voltage Supply Selection JP4 lets VMEbus SYSRESET reset the XPD when closed When open a VMEbus SYSRESET from other modules will not reset the XPD VMEbus SYSRESET In Selection XPD Won t Receive SYSRESET from the VMEbus Open XPD Receives SYSRESET from the VMEbus VMEbus SYSRESET In Selection 16 XPD VMEbus Pentium Processor Board User s Manual Dynatem Chapter 4 Installation Eee AAA Jumper JP5 is provided for clearing the NVRAM If BIOS parameters are modified and the XPD goes into a failure mode default variables can be restored by closing JP5 for roughly 15 seconds 4 2 CompactFlash Drive Installation The XPD supports a bootable CompactFlash Drive for booting up into an Operating System OS while occupying only one slot in the VMEbus chassis Connector J3 is a Type II CompactFlash connector and is used for this purpose J3 is located below PMC site 1 4 3 PCI Mezzanine Card PMC Installation The XPD supports two PMC add on module sites that let the user expand the XPD s local I O with PCI Mezzanine Cards PMC or PMCX PMC modules capable of PCI X transfers modules The PMCX sites are backwards comp
36. essor Board User s Manual 43 Appendix B BIOS amp Setup AAA Y Virtual Console History Specifies the number of lines of text that Firmbase Technology maintains in its virtual console feature allowing the user to scrollback through lines previously displayed and scrolled off the screen OEMs may configure a set of values such as 20 50 100 200 and 500 lines Quiet Mode Enables a feature that causes the Firmbase kernel to suppress its standard messages to the system console Strict Mode Enables a feature that causes the Firmbase kernel to abort any processes in the system that make software errors in calling system API functions Examples include blocking at IROLs other than IRQL_THREAD or passing a NULL pointer to a C library function that requires a non NULL pointer etc Disabling this feature causes the kernel to skip over the activity that discovered the programming error in the application allowing it to continue if at all possible with the consequence that the program may not operate correctly B 12 Miscellaneous Setup Menu The Misc menu provides for configuration of BIOS settings that don t easily fit in any other category They include Cache Control Keyboard Control Debugger Settings and System Monitor Utility Configuration parameters Technology C 2087 Genera The following table presents the settings in the Misc Setup menu System Cache Enables POST s support for cache in the syst
37. ing it will have a set of five jumpers for each slot e Interrupt Acknowledge TACKIN and IACKOUT e Bus Grant 0 BGOIN and BGOOUT e Bus Grant 1 BGIIN and BGIOUT e Bus Grant 2 BG2IN and BG20UT e Bus Grant 3 BG3IN and BG30UT Dynatem XPD VMEbus Pentium Processor Board User s Manual 17 Chapter 4 Installation eee A These jumpers are typically found between slots and when configuring a VMEbus chassis care must be taken to correctly determine the slot affected by the jumpers the slot to the right of the jumpers The interrupt acknowledge is a daisy chain from the board acknowledging the interrupt request to the boards that can issue an interrupt request The bus grant signals are daisy chains from the system controller which contains the bus arbiter to the boards that can request the bus Empty VMEbus slots between boards should have all of these jumpers installed Any slot containing the XPD should have all of these jumpers removed Any VMEbus slots after the last board in the chassis that is the board farthest away from the system controller which is always in slot 1 do not require these jumpers For other boards in the VMEbus chassis refer to their installation instructions for their jumper requirements Once the VMEbus chassis jumpers are installed insert the XPD into its designated slot With the XPD ejector handles inward firmly push the XPD into the VMEbus connectors on the chassis Tighten the s
38. is defined by the following registers in the Universe IID User s Manual Address Space VAS in Table A 76 A32 A24 or A16 Base Address BS 31 12 in Table A 77 Lowest address in the 4 KB slave image Slave Image Enable EN in Table A 76 Enable VMEbus Register Access Image SUPER in Table A 76 Supervisor and or Non Privileged PGM in Table A 76 Program and or Data The reset state of the VAS BS 31 12 and EN fields can be configured as power up options On the XPD all of these fields reset to 0 Thus the VRAI method must be configured and enabled by accessing the Universe IID registers in the memory space The second mechanism for accessing the UCSR block from the VMEbus is the CS CSR method which is defined by the following registers in the Universe IID section of the User s Manual Rea ResserBus daaa Base Address BS 23 19 in Table A 84 Base address of Universe IID 512 KB slot Slave Image Enable EN in Table A 78 Enable CS CSR image The BS 23 19 and EN fields reset to all Os and the EN bit can be set by the VME64 Auto ID process Thus the CR CSR method must be configured by accessing the Universe IID registers in the memory space The PCI signals specific to the Tundra Universe IID CA91C142D are routed from the PCI bus of the ICH and they are shown below Tundra Universe IID CA91C142D PCI Bus Connection Signal Bus PCI IDSEL AD16 Dynatem XPD VMEbus Pentium Processor Board User s Manual 11 Chapter 3 Hardwar
39. ister of the Universe IID is set by code running on the XPD processor This performs a local hard reset via signal LRST of the XPD board circuitry If SW1 2 is open LRST will reset the XPD without asserting a VMEbus SYSRESET signal e Another VMEbus master sets the RESET bit in the VCSR_SET register of the Universe IID over the VMEbus In this case the LRST signals remains asserted until the RESET bit of the VCSR_CLR register of the Universe IID is set by another VMEbus master over the VMEbus e The Reset Control Register in the ICH can be set appropriately by code running on the XPD processor e Let the watchdog timer time out see Section 3 12 below For further information on the peripherals that play a part in the reset circuitry refer to ICH datasheet that s referenced in Section 2 3 12 Watchdog Timer Operation The XPD s DS1232 if the watchdog timer is enabled and times out The XPD s watchdog timer is controlled by one general purpose output line GPIO20 that is asserted by the ICH The DS1232 has a strobe input pin that must see an active clock If no clock pulse is generated to the pin within 500 milliseconds the entire XPD board will be reset As long as GPIO20 is high a 14 31818 MHz clock will be present at the strobe input To use the watchdog timer drive GPIO20 low thereby turning off the 14 31818 MHz clock to the DS1232 s strobe input and write a software routine that will bring GPIO20 high before 500 milliseconds el
40. ked RTC and 256 bytes of CMOS RAM Power Management Logic Interrupt Controller Watchdog Timer AC 97 CODEC Integrated 16550 compatible UART s and multimedia timers based on the 82C54 For further information see the documents referenced in Section 2 3 4 DRAM The XPD supports two 72 bit wide DDR2 400 memory interface channels with a memory bandwidth of 6 4 GB s with ECC The XPD can be populated to support IGB or 2GB of DRAM 3 5 Intel 82571EB Dual Gigabit Ethernet Controller The XPD supports two Intel amp 82571EB Gigabit Ethernet Controllers one provides two Vita 31 1 compliant Gigabit LAN ports to the backplane while the other provides two that are accessible from the front panel The 82571EB isa single compact component with two fully integrated Gigabit Ethernet Media Access Control MAC and physical layer PHY ports This device uses the PCI Express architecture Rev 1 02 and also enables a dual port Gigabit Ethernet implementation in a very small area which is useful for embedded designs with critical space constraints The Intel 82571EB Gigabit Ethernet Controller provides two IEEE 802 3 Ethernet interfaces for 1000BASE T 100BASE TX and IOBASE T applications In addition to managing MAC and PHY Ethernet layer functions the controller manages PCI Express packet traffic across its transaction link and physical logical layers The Intel 82571EB Gigabit Ethernet Controller for PCI Express is designed for high performance and low
41. lash Interface Connector J3 DIRA IRGIS Pulled Low master 42 Pulled Up to 3 3 VDC CompactFlash Type Il Interface Connector J3 Dynatem XPD VMEbus Pentium Processor Board User s Manual 21 Appendix A Connector Pin outs A 4 VMEbus Connectors P1 P2 and PO zn wc avr ooo sv easy co be Ia zoe end aoe oor 8e scm a a zw eno A06 mos 806 sai f ce pis Dos NC zor uma Tw A07 bos 807 eco cor ma bor nc zos srac mms o GND Boo BGeour co enn Doo camm VMEbus Connector P1 DIN 41612 96 pin 3 rows x 32 pins 22 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs The XPD routes the primary IDE interface to the P2 connector s a and c rows while the middle row row b is used for the VMEbus extended address and data bus The IDE pins are in blue font Other I O routed out through the P2 connector are two USB 2 0 ports PS 2 Mouse amp Keyboard and four RS232 serial ports two have full handshaking while the other two are just two wire interfaces I O pins from JN4 connector P14 of the PMCX module are routed to rows d and z zs eno 40s Poo eo fas cos Poons bos Ps zos Praia aoo Pony eoo a coo bona bos Pts VMEbus Connector P2 160 pin 5 rows x 32 pins Dynatem XPD VMEbus Pentium Processor Board User s Manual 23 Appendix A Connector Pin outs Con
42. memory latency The device is optimized to connect to the E7520 MCH using four PCI Express lanes Alternatively the controller can connect to an Input Output I O Control Hub ICH that has a PCI Express interface Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words Combining a parallel and pipelined logic architecture optimized for Gigabit Ethernet and for independent transmit and receive queues the controller efficiently handles packets with minimum latency The controller includes advanced interrupt handling features and uses efficient ring buffer descriptor data structures with up to 64 packet descriptors cached on chip A large 48 KByte per port on chip packet buffer maintains superior performance In addition using hardware acceleration the controller offloads tasks from the host such as checksum calculations for transmission control protocol TCP user datagram protocol UDP and Internet protocol IP header and data splitting and TCP segmentation Dynatem XPD VMEbus Pentium Processor Board User s Manual 7 Chapter 3 Hardware Description The Intel 82571EB offers the following features e 10 100 and 1000BaseTX support with auto negotiation e Uses x4 PCI Express from MCH e Dual 48 KB configurable RX and TX packet FIFOs e Built in Phyceiver e Serial EEPROM for non volatile Ethernet address storage Both 10 100 1000BaseTX ports of one 82571EB device are brought
43. ndows Vista or for Linux operating systems with ACPI support Plug n Play OS Enable delay of configuration of PnP hardware and option ROMs When enabled BIOS will NOT configure the devices and instead defer assignment of resources such as DMA I O memory and IRQs to the PnP OS When disabled the BIOS performs conflict detection and resolution and assigns resources for the OS Disable this parameter when running non PnP OSes like DOS Enable this parameter when running PnP OSes like Windows95 Windows98 and WindowsNT IROO Enable exclusive use of IROO by PnP IRQI Enable exclusive use of IRQ1 by PnP IRQ2 Enable exclusive use of IRQ2 by PnP IRQ3 Enable exclusive use of IRQ3 by PnP IRO4 Enable exclusive use of IRO4 by PnP IROS Enable exclusive use of IROS by PnP IRO6 Enable exclusive use of IRQ6 by PnP IRO7 Enable exclusive use of IRQ7 by PnP IRO8 Enable exclusive use of IRQ8 by PnP IRQ9 Enable exclusive use of IRQ9 by PnP IRO10 Enable exclusive use of IRQ10 by PnP Dynatem XPD VMEbus Pentium Processor Board User s Manual 39 Appendix B BIOS amp Setup IRQ11 Enable exclusive use of IRQ11 by PnP IRQ12 Enable exclusive use of IRQ12 by PnP IRQ13 Enable exclusive use of IRQ13 by PnP IRQ14 Enable exclusive use of IRQ14 by PnP IRQ15 Enable exclusive use of IRQ15 by PnP B 9 Super I O SIO Setup Menu The SIO menu is used to configure the LPC47B27x Su
44. nector PO routes two Gb Ethernet ports in compliance with VITA 31 1 a VGA interface and two Serial ATA ports The two Gb Ethernet ports occupy rows 2 through 5 To follow Vita 31 1 to the letter rows 1 amp 6 are all no connects and pins C02 through C05 are grounded The XPD can comply to Vita 31 1 by the appropriate use of 0 ohm resistors but in the pin out below these pins are used for two SATA ports and the VGA port Lace BALA _ BOG GATAL AN GOR VGA diada Dos amen EOB Sara A08 Pioro Bog Pioo cos pics Dog Pioz Eos Pios A09 PIO 5 Bog Piore co9 piows Dog ioe Eog Pion PO VME64 Extensions Bus Connector PO for XPD Rev A PWB D010 6065 001 Row F is grounded 24 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs A 5 PCI X Mezzanine Card Connectors JN1 JN2 JN3 and JN4 and the XMC connector J15 This section has the pin outs for all four PMC connectors There are two PMC sites Their pinouts are largely identical When signals differ between the two PMC sites red font will be used for PMC Site 1 see the photo at the beginning of Section 4 of this User s Manual and blue font will be used for PMC Site 2 JN4 pinouts for the two different sites I O connectors where the pins are routed to P2 amp PO respectively are completely different for the two sites so these pinouts will be provided separately EA RMENME NN 1
45. per I O device The only implemented I O on this chip are the PS 2 mouse and keyboard and two 2 wire COM ports COM3 amp COM4 Basically this window is used to configure COM3 amp COM4 though they are referred to as Serial Ports 1 amp 2 in the SIO Setup Menu POST reads these settings in the menu shown above and programs the Super I O part accordingly enabling and disabling devices as requested The disabled devices are not further programmed since they are actually disabled in hardware In the figure above legacy 1 0 addresses and IROs are as follows COM3 I O 3f8h IRQ4 COMA I O 2f8h IRQ3 It should be noted that these are not the only possible addresses but they are the ones that will ensure compatibility with the most legacy software especially early DOS programs that do not use BIOS to access the COM ports 40 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix B BIOS amp Setup B 10 Features Setup Menu The Features menu is used to configure the system BIOS major features including Quick Boot APM ACPI PMM SMBUS SMBIOS Manufacturing Mode Splash Screen Console Redirection and others added by the OEM This figure shows a typical Features Setup menu system Configuration Util ity Inferrupt Processing Use APIC w StrongFrame TM Tec hno logy C 2007 General Software The following table describes each setting in the Features menu Quick Boot Enable time optimized POST
46. rm a 4 KB block divided into three groups e PCI Configuration Space PCICS e Universe IID Device Specific Status Registers UDSRs e VMEbus Control and Status Registers VCSRs These registers are accessible to varying degrees via three address spaces e PCI Configuration Space Only the PCICS register block is accessible in this space e PCI Memory Space The entire 4 KB UCSR block is accessible in this space e VMEbus A32 A24 A16 Space The entire 4 KB UCSR block is accessible in this space 10 XPD VMEbus Pentium Processor Board User s Manual Dynatem Chapter 3 Hardware Description ee During initialization the system BIOS maps PCI peripherals that reguire space beyond the PCI configuration space into the memory space or I O space The Universe IID UCSR block is 4 KB in size and must be aligned on a 64 KB boundary The total I O space of an Intel processor is 64 KB and many of the common PC peripherals are found in the first 1 KB of this space Thus a request for a 64 KB block of I O space for the Universe IID registers would be denied by the system BIOS leaving the Universe IID unmapped To avoid this situation the Universe IID offers a power up option to map its registers into the memory space This is accomplished on the XPD by tying the VA 1 line high via a pull up resistor There are two mechanisms to access the UCSR block from the VMEbus The first is the VMEbus Register Access Image VRAI method which
47. rnet PCI Controller http www intel com design network products lan controllers 8257 leb htm e VMEbus Interface Components Manual Tundra Semiconductor Corporation Universe IID revisions are found at www tundra com The following documents provide information on the PC architecture and I O e PCI Local Bus Specification Revision 2 2 http www pcisig com specifications e PCI X Specification Revision 1 0A http www pcisig com specifications e System Management Bus Specification SMBus Revision 1 1 http www smbus org specs e Universal Serial Bus Specification http www usb org developers The following documents cover topics relevant to the VMEbus and can be purchased through VITA e IEEE Std 1014 1987 IEEE Standard for a Versatile Backplane Bus VMEbus The Institute of Electrical and Electronic Engineers 345 East 47th Street New York NY 10017 800 678 4333 e Wade D Peterson The VMEbus Handbook VITA 10229 North Scottsdale Road Suite B Scottsdale AZ 85253 480 951 8866 Dynatem XPD VMEbus Pentium Processor Board User s Manual 3 Chapter 2 Related Documents s5 bwmwbv 55bw 44 4 The following documents are the current draft standards for the PCI Mezzanine Card PMC and XMC cards e JEFE Draft Std P1386 2 0 Draft Standard for a Common Mezzanine Card Family CMC The Institute of Electrical and Electronic Engineers 345 East 47th Street New York NY 10017 800 678 4333 e
48. s two Fast Ethernet ports and XPD amp PMC I O e An IDE port four RS232 COM ports PS 2 Mouse amp Keyboard two USB ports and PMC I O are routed out to the backplane via the P2 connector e Two Serial ATA ports VGA graphics two Gbit Ethernet ports Vita 31 1 compliant and PMC XMC I O are routed to the PO connector Dynatem XPD VMEbus Pentium Processor Board User s Manual 1 Chapter 1 Features ii EK ET KI iii e The Intel E7520 Memory Controller Hub MCH and Intel 6300ESB I O Controller Hub ICH provide high speed memory control 16 lanes of PCI Express I O integrated I O like Serial ATA USB 2 0 IDE supporting Ultra 100 DMA Mode for transfers up to 88 88 MB sec and 64 bit PCI X bus transfers at 66 MHz e ATT s Rage Mobility MI VGA Controller e Two Intel 82571EB Ethernet Controllers with a x4 PCI Express interface each offering two 10 100 1000BaseTX support two ports are routed to PO in compliance with Vita 31 1 for backplane fabric switching while the other two are routed to the front panel e 2GB of DDR2 400 DRAM provided on board e Tundra Universe IID PCI VMEbus Interface provides 64 bit VMEbus transfer rates over 30 MB sec Integral FIFOs permit write posting to maximize available PCI and VMEbus bandwidth Full Slot 1 System Controller functionality is provided e PCI Mezzanine Card PMC expansion supports 64 bits 9 up to 66 MHz e Asecond PCI Mezzanine Card PMC expansion supports 64 bits 9 up to 66 MHz an
49. s are identical A 2 Received Data RxD Input Transmitted Data TxD Output 4 NoConnection GND NND DECLA 6 cone 8 No Connect 9 ___NoConnect COM3 J2 and COM4 J1 Connectors DB9M Connector The metal shell of the connector goes to chassis ground J9 SATA and J10 SATAO are Serial ATA connectors where both ports have the following pinout Serial ATA Connectors J9 J10 Pinout for either of the connectors J12 combines the PS 2 Mouse and Keyboard interfaces on one connector A Y splitter cable is required to separate them Signal Description Keyboard Data 5 VDC via 1 amp self resetting fuse F1 5 Keyboard Clock 6 Mouse Clock Keyboard Mouse Connector J12 Mini DIN Receptacle The metal shell of the connector goes to chassis ground Dynatem XPD VMEbus Pentium Processor Board User s Manual 51 Appendix D XPDPTB Rear Plug in I O Expansion Module for the XPD The XPDPTB uses two RJ45 connectors to provide two 1 Gb Ethernet ports These lines are routed through 0 ohm resistors RI R16 These ports are also routed to the PO connector in compliance with VITA 31 1 Leave the resistors off in systems that utilize Vita 31 1 backplane networking c NX 10 100 Signal Description Port A Transmit Data TX TPO A Transmit Data TX TPO A Receive Data RX TP1 Unused TP2 Unused TP2 A Receive Data RX TP1 Unused TP3 Unused TP3 10 100 Sign
50. s boundary High Memory Standard Enable basic memory confidence test of memory between 1MB and 4 2GB address Test boundaries extended memory High Memory Exhaustive Enable exhaustive memory confidence test of memory between 1MB and 4 2GB Test address boundaries Huge Memory Standard Enable basic memory confidence test of memory above 4 2GB address boundary Test available using PAE technology Huge Memory Exhaustive Test Enable exhaustive memory confidence test of memory above 4 2GB address boundary Clear Memory During Test Click During Memory Test Enable disable speaker click when testing each block Enable storing 0 s in all memory locations tested Only necessary when some legacy DOS programs are run as they may rely on cleared memory to operate properly The following table describes the settings associated with the POST setup menu s Error Control section Pause on POST Errors Enable pause when errors are detected during POST so that the user can view the error message and enter Setup or continue to boot the OS POST Display Messages The following table describes the settings associated with the POST setup menu s POST User Interface section Enable display of text messages during POST When disabled POST is quiet POST Operator Prompt Enable operator prompts if POST is configured to ask interactive questions of the user about whether to load specific features
51. stallation The XPD offers a number of user configurable hardware options Jumpers Description JP1 VMEbus Slot 1 Controller when open JP2 XPD drives SYSRESET to the VMEbus when closed JP3 Determines VIO for the two PMC sites 1 2 for 3 3 VDC 2 3 for 5 0 VDC JP4 XPD is reset by the VMEbus SYSRESET when closed JP5 Close momentarily to flush RTC and NV RAM and revert to BIOS defaults JP6 Bit Control 1 grounded when shunted JP7 Bit Control 0 grounded when shunted JP8 MUST STAY CLOSED on board BIOS is disabled when open SW2 1 through SW2 4 DDC Routing for DVI I Interface set at the factory JP2 lets an XPD SYSRESET reset the VMEbus when closed When open the XPD cannot drive a SYSRESET to other modules on the VMEbus The Universe IID only drives SYSRESET when the XPD is a Slot 1 Controller VMEbus SYSRESET Out Selection XPD Won t Drive SYSRESET to the VMEbus Open XPD Drives SYSRESET to the VMEbus VMEbus SYSRESET Out Selection When a VMEbus module occupies slot 1 of the VMEbus chassis the slot to the extreme left it must operate as system controller act as multiprocessing arbiter and generate utility bus signals JP1 configures the VMEbus System Controller functionality of the Universe IID as shown below VMEbus System Controller Enabled Disabled VMEbus System Controller Configuration Jumper JP3 selects the VIO routed to the XPD s two PMC modules The VIO pins det
52. t Core Duo hard reset LTC1778 3 3V Reset Reset Circuitry Dynatem XPD VMEbus Pentium Processor Board User s Manual 13 Chapter 3 Hardware Description s5 5555533 A There are eight ways to perform a hard reset of the XPD e The DS1232 senses that the 5 VDC supply has dropped too low asserting a PWROK signal to the ICH This signal resets the processor and the Chipset and ultimately all PCI and PCI X peripherals The output of the DS1232 runs through the Universe IID If the board is delivered without the VMEbus interface circuitry the XPD this path is replaced with a bypass O ohm resistor e A DS1233 monitors the on board 3 3 VDC regulated from the 5 0 VDC off the backplane and provides proper power sequencing for the CPU e The local on board voltage regulator for the CPU s core voltage will generate a reset if its output voltage is out of range through signal PWRGD_VR e The front panel reset switch PB1 is pressed which also asserts a PWROK signal from the DS1232 and resets the XPD e Another VMEbus board asserts SYSRESET which asserts the Universe IID VRSYSRST input and if Jumper SW 1 1 is closed will reset the XPD e The SW_SYSRST bit in the MISC_CTL register of the Universe IID is set by code running on the XPD processor This asserts the VMEbus SYSRESET signal if SW1 2 is closed If SW1 1 is open the XPD can reset the VMEbus without resetting itself e The SW_LRST bit in the MISC_CTL reg
53. tab Move the cursor up to the last configurable field key Toggle an Enable Disable field or increase a numeric field s value key Toggle an Enable Disable field or decrease a numeric field s value SPACE key Toggle an Enable Disable field BKSP key Reset an Enable Disable or multiple choice field or back up in numeric or string fields Digits 0 9 Used to enter numeric parameters Alphabetic A Z a z Used to enter text data on ASCII fields such as email addresses Special symbols Used to enter special text on ASCII fields that permit these characters 1 amp _ H etc The basic idea when using the Setup system is to navigate to the menus containing fields you want to review and change those fields as desired When your settings are complete navigate to the EXIT menu and select Save Settings and Restart This causes the settings to be stored in nonvolatile memory in the system and the system will reboot so that POST can configure itself with the new settings After rebooting it may be desirable to reenter the Setup system as necessary to adjust settings as necessary 32 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix B BIOS amp Setup Once the system boots the Setup system cannot be entered this is because the memory used by the BIOS configuration manager is deallocated by the system BIOS so that it can be used by the OS when it boots To reenter the Setup system af
54. ter boot simply reset the system or power off and power back on B 4 Main Setup Menu The first menu always showing in the Setup system is the Main menu unless disabled by the OEM This menu is shown in Figure 3 1 below The Main menu provides a system summary about the BIOS processor system memory date and time and any other items configured by the OEM The BIOS information is obtained by Setup from the internal system BIOS build itself this information is useful when obtaining support for your system PLEASE CALL Dynatem at 800 543 2830 FOR BIOS SUPPORT DO NOT CALL GENERAL SOFTWARE DIRECTLY BIOS Version Indicates the major and minor core architecture versions 6 x where x is a number from 0 to 999 BIOS Build Date Date in MM DD YY format on which Dynatem built the system BIOS binary file System BIOS Size Size of BIOS exposed in low memory below the 1MB boundary Commonly 128KB would mean that the BIOS is visible in the address space from E000 0000 to F000 FFFF CPM CSPM BPM Indicates the names of the key architectural modules used to create the system BIOS Modules binary file The CPM module provides the CPU family support the CSPM module provides the northbridge support and the BPM module provides the board level support The CPU information is normally obtained by querying the Processor Brand String in the CPU s MSRs the method used to achieve this is beyond the scope of this document Dynatem XPD
55. tion POST Floppy Seek Enable head seek on each floppy drive configured in the system Used to recalibrate the drive in some systems with older DOS operating systems POST Hard Disk Seek Enable head seek on each hard drive configured in the system This is a way of extending the standard testing performed on each drive during POST by requesting that the drive actually move the head Not available with all drives 38 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix B BIOS amp Setup B 8 PnP Setup Menu The PnP menu is used to configure Plug n Play a legacy BIOS initiative used to support operating systems such as Windows95 Windows98 and WindowsNT ACPI has largely replaced this feature however it is necessary for platforms to support older operating systems The PnP menu consists of two sections basic configuration that enables Plug n Play and identifies if a PnP should perform configuration or let the OS do it and then another section that defines which system IROs should be reserved for PnP s use so that PCI doesn t use them The following table presents the fields in the PnP menu Plug n Play Enable PnP feature When disabled a PnPaware OS will not find any PnP services in the BIOS and all other configuration parameters in the menu will be greyed out Enable to support legacy OSes like DOS Windows95 Windows98 and WindowsNT Disable for operating systems like WindowsXP or Wi
56. tors are shown below The connectors that do not go to the front panel have their pin 1 location designated accordingly Two 1Gb LAN Ports Ji USBO 1 line LAN t ds n dista po A XMC Connector PMC Connectors VMEbus P2 VMEbus PO VMEbus P1 Dynatem XPD VMEbus Pentium Processor Board User s Manual 19 Appendix A Connector Pin outs A 1 Front Panel USB Connector USB1 amp USB2 There are two USB connectors labeled USB1 amp USB2 accessible at the XPD s front panel Though they are separate ports their pin outs are identical so the following table offers the pin out of one connector as both en Sonar een OOO 6 ena JA 8 Chassis NO USB Connectors USB1 amp USB2 Front Panel USB Receptacles The metal shell of the connector goes to chassis ground A 2 1000BaseTX Fast Ethernet Front Panel Connector J1 The XPD uses a dual RJ45 connector to provide two 1000BaseTX Ethernet ports at the front panel Though there are two separate ports in one connector the pin outs are identical so the following table offers the pin out of one connector as both TPO TPO TPis TP2 TP2 A Receive Data RX TP1 TP3 TP3 1000BaseTX Fast Ethernet Connector J1 Front Panel RJ 45 Connector The metal shell of the connector goes to chassis ground 20 XPD VMEbus Pentium Processor Board User s Manual Dynatem Appendix A Connector Pin outs A 3 CompactF
57. type of CPU and DRAM sticks to applications such as WfM which runs on PXE in the preboot environment Manufacturing Mode Enable automatic entry into manufacturing mode when POST encounters a critical error Used in closed device settings such as smart phones that need access to docking stations when they don t boot Leave disabled Splash Screen Enable graphical POST Dynatem XPD VMEbus Pentium Processor Board User s Manual 41 Appendix B BIOS amp Setup A AAA lt A Console Redirection Configure the console redirection feature over a serial port Automatic causes POST the debugger and the preboot environment to use the system s first serial port COM 1 when an RS232 cable is detected with DSR and CTS modem signals active indicating a terminal emulation program is likely to be attached to the other end of the cable Always causes the BIOS to always use the serial port as the console without testing for the presence of the terminal emulation program Never causes the BIOS to never invoke console redirection but instead always use the main keyboard and video display If there is no keyboard or video display the system operates headless EFI Source Configure the location ROM or disk where the EFI boot action can find the EFILDR BIN image An image may be merged with the system BIOS into the system ROM or it may be placed in the root directory of any bootable mass storage device
58. ven in Appendix A The Universe IID CA91C142D can act as a PCI bus initiator master or target slave and a VMEbus master or slave The Universe IID is capable of generating interrupts on the VMEbus and can act as a VMEbus interrupt handler The Universe IID provides full VMEbus system controller functionality The XPD reset circuitry is tied to the Universe IID since the XPD can generate the VMEbus SYSRESET signal as well as be reset by another VMEbus board that asserts the SYSRESET signal The XPD reset circuitry is discussed in detail in Section 3 12 This section is intended to supplement the VME to PCI Bus Bridge Manual User Manual downloadable from www tundra com which contains comprehensive descriptions of the operation and programming of the Universe IID That manual provides the necessary information to understand the operating modes of the Universe IID e XPD initiated transfers PCI slave VMEbus master e Other VMEbus master initiated transfers PCI master VMEbus slave e DMA controller transfers PCI master VMEbus master e VMEbus interrupt generation e VMEbus interrupt handling e System controller functionality e Register programming via the PCI bus and the VMEbus e Coupled and uncoupled transfers between the PCI bus and the VMEbus e 4 mailboxes and 8 semaphores e VMEbus arbitration The Universe IID Control and Status Registers UCSRs are used for the configuration of the Universe IID These registers fo
59. ystem s boot actions and boot devices to be configured This menu is shown here System Configuration Utilitu The BBS portion of this menu lists the devices and activities to be performed in the order in which they appear in the list When the BIOS completes POST it follows this list attempting to process each item Some items are drives such as an ATA IDE drive or a USB hard disk or CDROM The ordering of the drives in the BBS list controls the BIOS in several ways First it is the list of drives that is scanned and assigned BIOS unit numbers for DOS for example 80h 81h 83h and so on for hard drives If a drive on the list is not plugged in or working properly the BIOS moves on to the next drive skipping the inoperative one Second once the drives in the list have been verified POST attempts to boot from them in that order as well Drives without bootable partitions might be configured but skipped over in the boot phase so that other drives on the list become candidates for booting the OS The BBS list also contains other boot actions such as boot from network cards and PCI slots as well as special BIOS boot actions like Boot EFT Boot Windows CE or even Boot Debugger When deciding what boot action to do first and then next in succession POST first scans all the drives in the list to verify they are present and operating properly as described earlier in this section and then goes down the list and tries to

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